drivers/acpi/acpica/acutils.h
347
acpi_ut_debug_dump_buffer(u8 *buffer, u32 count, u32 display, u32 component_id);
drivers/acpi/acpica/acutils.h
349
void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 offset);
drivers/acpi/acpica/acutils.h
355
u32 count, u32 display, u32 base_offset);
drivers/acpi/acpica/dbdisply.c
146
u32 display = DB_BYTE_DISPLAY;
drivers/acpi/acpica/dbdisply.c
161
display = DB_WORD_DISPLAY;
drivers/acpi/acpica/dbdisply.c
163
display = DB_DWORD_DISPLAY;
drivers/acpi/acpica/dbdisply.c
165
display = DB_QWORD_DISPLAY;
drivers/acpi/acpica/dbdisply.c
216
display, ACPI_UINT32_MAX);
drivers/acpi/acpica/dbdisply.c
235
display, ACPI_UINT32_MAX);
drivers/acpi/acpica/dbdisply.c
255
acpi_ut_debug_dump_buffer(obj_ptr, size, display,
drivers/acpi/acpica/dbdisply.c
289
sizeof(struct acpi_namespace_node), display,
drivers/acpi/acpica/dbdisply.c
325
display, ACPI_UINT32_MAX);
drivers/acpi/acpica/dbdisply.c
331
display, ACPI_UINT32_MAX);
drivers/acpi/acpica/utbuffer.c
109
j += display;
drivers/acpi/acpica/utbuffer.c
170
acpi_ut_debug_dump_buffer(u8 *buffer, u32 count, u32 display, u32 component_id)
drivers/acpi/acpica/utbuffer.c
180
acpi_ut_dump_buffer(buffer, count, display, 0);
drivers/acpi/acpica/utbuffer.c
206
u8 *buffer, u32 count, u32 display, u32 base_offset)
drivers/acpi/acpica/utbuffer.c
219
display = DB_BYTE_DISPLAY;
drivers/acpi/acpica/utbuffer.c
237
fprintf(file, "%*s", ((display * 2) + 1), " ");
drivers/acpi/acpica/utbuffer.c
238
j += display;
drivers/acpi/acpica/utbuffer.c
242
switch (display) {
drivers/acpi/acpica/utbuffer.c
277
j += display;
drivers/acpi/acpica/utbuffer.c
34
void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset)
drivers/acpi/acpica/utbuffer.c
40
u32 display_data_only = display & DB_DISPLAY_DATA_ONLY;
drivers/acpi/acpica/utbuffer.c
42
display &= ~DB_DISPLAY_DATA_ONLY;
drivers/acpi/acpica/utbuffer.c
49
display = DB_BYTE_DISPLAY;
drivers/acpi/acpica/utbuffer.c
69
acpi_os_printf("%*s", ((display * 2) + 1), " ");
drivers/acpi/acpica/utbuffer.c
70
j += display;
drivers/acpi/acpica/utbuffer.c
74
switch (display) {
drivers/auxdisplay/charlcd.c
213
lcd->ops->display(lcd, CHARLCD_ON);
drivers/auxdisplay/charlcd.c
220
lcd->ops->display(lcd, CHARLCD_OFF);
drivers/auxdisplay/charlcd.h
89
int (*display)(struct charlcd *lcd, enum charlcd_onoff on);
drivers/auxdisplay/hd44780.c
135
.display = hd44780_common_display,
drivers/auxdisplay/hd44780.c
191
.display = hd44780_common_display,
drivers/auxdisplay/lcd2s.c
291
.display = lcd2s_display,
drivers/auxdisplay/panel.c
820
.display = hd44780_common_display,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
541
struct mod_hdcp_display *display = &hdcp_work[link_index].display;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
553
memset(display, 0, sizeof(*display));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
556
display->index = aconnector->base.index;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
557
display->state = MOD_HDCP_DISPLAY_ACTIVE;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
567
display->controller = CONTROLLER_ID_D0 + config->otg_inst;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
568
display->dig_fe = config->dig_fe;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
571
display->stream_enc_idx = config->stream_enc_idx;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
586
display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
592
hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
602
mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
59
struct mod_hdcp_display display;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
67
enum dm_acpi_display_type display, struct dm_acpi_atif_backlight_caps *pCaps)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
71
int bl_index = (display == AcpiDisplayType_LCD1) ? 0 : 1;
drivers/gpu/drm/amd/display/dc/dm_services.h
239
(struct dc_context *ctx, enum dm_acpi_display_type display,
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
257
struct mod_hdcp_display *display,
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
264
display->adjust.disable == true &&
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
266
display->adjust.disable = false;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
273
display->adjust.disable = true;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
277
memcmp(adj, &display->adjust,
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
322
struct mod_hdcp_link *link, struct mod_hdcp_display *display,
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
328
HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
332
if (display->state != MOD_HDCP_DISPLAY_ACTIVE) {
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
338
if (get_active_display_at_index(hdcp, display->index)) {
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
363
*display_container = *display;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
384
struct mod_hdcp_display *display = NULL;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
390
display = get_active_display_at_index(hdcp, index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
391
if (!display) {
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
411
memset(display, 0, sizeof(struct mod_hdcp_display));
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
430
struct mod_hdcp_display *display = NULL;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
436
display = get_active_display_at_index(hdcp, index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
437
if (!display) {
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
445
memcmp(display_adjust, &display->adjust,
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
453
memcmp(display_adjust, &display->adjust,
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
455
status = update_display_adjustments(hdcp, display, display_adjust);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
473
display->adjust = *display_adjust;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
490
struct mod_hdcp_display *display = NULL;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
493
display = get_active_display_at_index(hdcp, index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
494
if (!display) {
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
501
query->display = display;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
505
if (is_display_encryption_enabled(display)) {
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
523
static inline uint8_t is_display_active(struct mod_hdcp_display *display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
525
return display->state >= MOD_HDCP_DISPLAY_ACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
528
static inline uint8_t is_display_encryption_enabled(struct mod_hdcp_display *display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
530
return display->state >= MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
548
struct mod_hdcp_display *display = NULL;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
552
display = &hdcp->displays[i];
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
555
return display;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
562
struct mod_hdcp_display *display = NULL;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
567
display = &hdcp->displays[i];
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
570
return display;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
577
struct mod_hdcp_display *display = NULL;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
581
display = &hdcp->displays[i];
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
584
return display;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
103
dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
113
display->state = MOD_HDCP_DISPLAY_INACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
115
display->state = MOD_HDCP_DISPLAY_ACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
116
HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
123
struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
132
display->state = MOD_HDCP_DISPLAY_INACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
142
dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
144
dtm_cmd->dtm_in_message.topology_update_v2.controller = display->controller;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
147
dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
151
dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
159
display->state = MOD_HDCP_DISPLAY_INACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
162
HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
170
struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
179
display->state = MOD_HDCP_DISPLAY_INACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
189
dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
191
dtm_cmd->dtm_in_message.topology_update_v3.controller = display->controller;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
194
dtm_cmd->dtm_in_message.topology_update_v3.stream_enc = display->stream_enc_idx;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
198
dtm_cmd->dtm_in_message.topology_update_v3.dp_mst_vcid = display->vc_id;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
216
status = add_display_to_topology_v2(hdcp, display);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
218
display->state = MOD_HDCP_DISPLAY_INACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
220
HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
240
struct mod_hdcp_display *display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
245
status = add_display_to_topology_v3(hdcp, display);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
247
status = add_display_to_topology_v2(hdcp, display);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
256
struct mod_hdcp_display *display = get_first_active_display(hdcp);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
265
if (!display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
273
hdcp_cmd->in_msg.hdcp1_create_session.display_handle = display->index;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
373
struct mod_hdcp_display *display = get_first_active_display(hdcp);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
376
if (!display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
391
display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
392
HDCP_HDCP1_ENABLED_TRACE(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
507
struct mod_hdcp_display *display = get_first_active_display(hdcp);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
516
if (!display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
524
hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
53
struct mod_hdcp_display *display =
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
59
if (!display || !is_display_active(display))
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
67
dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
76
display->state = MOD_HDCP_DISPLAY_ACTIVE;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
77
HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
838
struct mod_hdcp_display *display = get_first_active_display(hdcp);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
841
if (!display)
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
857
display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
858
HDCP_HDCP2_ENABLED_TRACE(hdcp, display->index);
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
89
struct mod_hdcp_display *display =
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
95
if (!display || !is_display_active(display))
drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
317
const struct mod_hdcp_display *display;
drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
342
struct mod_hdcp_link *link, struct mod_hdcp_display *display,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
704
ps->display.disableFrameModulation = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
714
ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
715
ps->display.explicitRefreshrate = look_up[rrr_index];
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
716
ps->display.limitRefreshrate = true;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
718
if (ps->display.explicitRefreshrate == 0)
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
719
ps->display.limitRefreshrate = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
721
ps->display.limitRefreshrate = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
726
ps->display.enableVariBright = (0 != tmp);
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
109
uint32_t display : 1;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3721
power_state->display.disableFrameModulation = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3722
power_state->display.limitRefreshrate = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3723
power_state->display.enableVariBright =
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
132
uint32_t display : 1;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3173
power_state->display.disableFrameModulation = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3174
power_state->display.limitRefreshrate = false;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3175
power_state->display.enableVariBright =
drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h
159
struct PP_StateDisplayBlock display;
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
201
struct smu_state_display_block display;
drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
54
const struct drm_display_info *display,
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1381
const struct drm_display_info *display)
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1392
if (!display->hdmi.scdc.supported ||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1393
!display->hdmi.scdc.scrambling.supported)
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1400
if (!display->hdmi.scdc.scrambling.low_rates &&
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1401
display->max_tmds_clock <= 340000)
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1421
const struct drm_display_info *display)
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1426
if (dw_hdmi_support_scdc(hdmi, display)) {
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1638
const struct drm_display_info *display)
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1648
dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1679
const struct drm_display_info *display,
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1689
ret = hdmi_phy_configure(hdmi, display);
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1995
const struct drm_display_info *display,
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
1999
const struct drm_hdmi_info *hdmi_info = &display->hdmi;
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
2032
(dw_hdmi_support_scdc(hdmi, display) &&
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
2100
if (dw_hdmi_support_scdc(hdmi, display)) {
drivers/gpu/drm/drm_modes.c
2711
bool drm_mode_is_420_only(const struct drm_display_info *display,
drivers/gpu/drm/drm_modes.c
2716
return test_bit(vic, display->hdmi.y420_vdb_modes);
drivers/gpu/drm/drm_modes.c
2731
bool drm_mode_is_420_also(const struct drm_display_info *display,
drivers/gpu/drm/drm_modes.c
2736
return test_bit(vic, display->hdmi.y420_cmdb_modes);
drivers/gpu/drm/drm_modes.c
2750
bool drm_mode_is_420(const struct drm_display_info *display,
drivers/gpu/drm/drm_modes.c
2753
return drm_mode_is_420_only(display, mode) ||
drivers/gpu/drm/drm_modes.c
2754
drm_mode_is_420_also(display, mode);
drivers/gpu/drm/i915/display/g4x_dp.c
1033
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1040
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
drivers/gpu/drm/i915/display/g4x_dp.c
1046
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
1047
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
1081
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1088
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
drivers/gpu/drm/i915/display/g4x_dp.c
1094
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
1095
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
1133
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1140
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
drivers/gpu/drm/i915/display/g4x_dp.c
1146
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
1147
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
1188
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1189
u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/g4x_dp.c
1191
return intel_de_read(display, SDEISR) & bit;
drivers/gpu/drm/i915/display/g4x_dp.c
1196
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1214
return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
drivers/gpu/drm/i915/display/g4x_dp.c
1219
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1220
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/g4x_dp.c
1222
return intel_de_read(display, DEISR) & bit;
drivers/gpu/drm/i915/display/g4x_dp.c
1229
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
1232
if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A)
drivers/gpu/drm/i915/display/g4x_dp.c
124
intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
drivers/gpu/drm/i915/display/g4x_dp.c
1263
struct intel_display *display = to_intel_display(encoder->dev);
drivers/gpu/drm/i915/display/g4x_dp.c
1266
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
1271
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
1282
bool g4x_dp_init(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_dp.c
1291
if (!assert_port_valid(display, port))
drivers/gpu/drm/i915/display/g4x_dp.c
1294
devdata = intel_bios_encoder_data_lookup(display, port);
drivers/gpu/drm/i915/display/g4x_dp.c
1298
drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
drivers/gpu/drm/i915/display/g4x_dp.c
1314
if (drm_encoder_init(display->drm, &intel_encoder->base,
drivers/gpu/drm/i915/display/g4x_dp.c
132
if (display->platform.ivybridge && port == PORT_A) {
drivers/gpu/drm/i915/display/g4x_dp.c
1331
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/g4x_dp.c
1338
} else if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/g4x_dp.c
1353
if ((display->platform.ivybridge && port == PORT_A) ||
drivers/gpu/drm/i915/display/g4x_dp.c
1354
(HAS_PCH_CPT(display) && port != PORT_A)) {
drivers/gpu/drm/i915/display/g4x_dp.c
1362
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
1364
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/g4x_dp.c
1366
else if (display->platform.ivybridge && port == PORT_A)
drivers/gpu/drm/i915/display/g4x_dp.c
1368
else if (display->platform.sandybridge && port == PORT_A)
drivers/gpu/drm/i915/display/g4x_dp.c
1373
if (display->platform.valleyview || display->platform.cherryview ||
drivers/gpu/drm/i915/display/g4x_dp.c
1374
(HAS_PCH_SPLIT(display) && port != PORT_A)) {
drivers/gpu/drm/i915/display/g4x_dp.c
1385
intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
drivers/gpu/drm/i915/display/g4x_dp.c
1386
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/g4x_dp.c
1400
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/g4x_dp.c
143
} else if (HAS_PCH_CPT(display) && port != PORT_A) {
drivers/gpu/drm/i915/display/g4x_dp.c
146
intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
drivers/gpu/drm/i915/display/g4x_dp.c
151
if (display->platform.g4x && pipe_config->limited_color_range)
drivers/gpu/drm/i915/display/g4x_dp.c
163
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
172
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
174
bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
drivers/gpu/drm/i915/display/g4x_dp.c
176
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/g4x_dp.c
183
static void assert_edp_pll(struct intel_display *display, bool state)
drivers/gpu/drm/i915/display/g4x_dp.c
185
bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;
drivers/gpu/drm/i915/display/g4x_dp.c
187
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/g4x_dp.c
197
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
200
assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
drivers/gpu/drm/i915/display/g4x_dp.c
202
assert_edp_pll_disabled(display);
drivers/gpu/drm/i915/display/g4x_dp.c
204
drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
drivers/gpu/drm/i915/display/g4x_dp.c
214
intel_de_write(display, DP_A, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
215
intel_de_posting_read(display, DP_A);
drivers/gpu/drm/i915/display/g4x_dp.c
224
if (display->platform.ironlake)
drivers/gpu/drm/i915/display/g4x_dp.c
225
intel_wait_for_vblank_if_active(display, !crtc->pipe);
drivers/gpu/drm/i915/display/g4x_dp.c
229
intel_de_write(display, DP_A, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
230
intel_de_posting_read(display, DP_A);
drivers/gpu/drm/i915/display/g4x_dp.c
237
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
239
assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/g4x_dp.c
241
assert_edp_pll_enabled(display);
drivers/gpu/drm/i915/display/g4x_dp.c
243
drm_dbg_kms(display->drm, "disabling eDP PLL\n");
drivers/gpu/drm/i915/display/g4x_dp.c
247
intel_de_write(display, DP_A, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
248
intel_de_posting_read(display, DP_A);
drivers/gpu/drm/i915/display/g4x_dp.c
252
static bool cpt_dp_port_selected(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_dp.c
257
for_each_pipe(display, p) {
drivers/gpu/drm/i915/display/g4x_dp.c
258
u32 val = intel_de_read(display, TRANS_DP_CTL(p));
drivers/gpu/drm/i915/display/g4x_dp.c
266
drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",
drivers/gpu/drm/i915/display/g4x_dp.c
275
bool g4x_dp_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_dp.c
282
val = intel_de_read(display, dp_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
287
if (display->platform.ivybridge && port == PORT_A)
drivers/gpu/drm/i915/display/g4x_dp.c
289
else if (HAS_PCH_CPT(display) && port != PORT_A)
drivers/gpu/drm/i915/display/g4x_dp.c
290
ret &= cpt_dp_port_selected(display, port, pipe);
drivers/gpu/drm/i915/display/g4x_dp.c
291
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
302
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
307
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/g4x_dp.c
312
ret = g4x_dp_port_enabled(display, intel_dp->output_reg,
drivers/gpu/drm/i915/display/g4x_dp.c
315
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/g4x_dp.c
338
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
349
tmp = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
353
if (HAS_PCH_CPT(display) && port != PORT_A) {
drivers/gpu/drm/i915/display/g4x_dp.c
354
u32 trans_dp = intel_de_read(display,
drivers/gpu/drm/i915/display/g4x_dp.c
386
if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
drivers/gpu/drm/i915/display/g4x_dp.c
394
if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)
drivers/gpu/drm/i915/display/g4x_dp.c
414
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
419
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/g4x_dp.c
420
(intel_de_read(display, intel_dp->output_reg) &
drivers/gpu/drm/i915/display/g4x_dp.c
424
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/g4x_dp.c
427
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
428
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
435
if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {
drivers/gpu/drm/i915/display/g4x_dp.c
440
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/g4x_dp.c
441
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/g4x_dp.c
447
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
448
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
451
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
452
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
454
intel_wait_for_vblank_if_active(display, PIPE_A);
drivers/gpu/drm/i915/display/g4x_dp.c
455
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/g4x_dp.c
456
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/g4x_dp.c
461
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
469
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
477
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
486
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
496
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
55
const struct dpll *vlv_get_dpll(struct intel_display *display)
drivers/gpu/drm/i915/display/g4x_dp.c
57
return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];
drivers/gpu/drm/i915/display/g4x_dp.c
579
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
598
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
599
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
606
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
611
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
612
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
620
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
63
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.c
639
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
640
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
647
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
652
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
653
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
659
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/g4x_dp.c
67
if (display->platform.g4x) {
drivers/gpu/drm/i915/display/g4x_dp.c
674
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
drivers/gpu/drm/i915/display/g4x_dp.c
675
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
683
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/g4x_dp.c
685
u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/g4x_dp.c
687
if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))
drivers/gpu/drm/i915/display/g4x_dp.c
691
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
70
} else if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/g4x_dp.c
701
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/g4x_dp.c
704
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_dp.c
73
} else if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/g4x_dp.c
76
} else if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/g4x_dp.c
95
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_dp.h
21
const struct dpll *vlv_get_dpll(struct intel_display *display);
drivers/gpu/drm/i915/display/g4x_dp.h
22
bool g4x_dp_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_dp.h
25
bool g4x_dp_init(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_dp.h
28
static inline const struct dpll *vlv_get_dpll(struct intel_display *display)
drivers/gpu/drm/i915/display/g4x_dp.h
32
static inline bool g4x_dp_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_dp.h
38
static inline bool g4x_dp_init(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_hdmi.c
133
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
137
if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/g4x_hdmi.c
140
if (display->platform.g4x)
drivers/gpu/drm/i915/display/g4x_hdmi.c
152
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
159
tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
183
if (!HAS_PCH_SPLIT(display) &&
drivers/gpu/drm/i915/display/g4x_hdmi.c
219
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
223
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
227
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
228
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
235
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
241
drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);
drivers/gpu/drm/i915/display/g4x_hdmi.c
244
intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
drivers/gpu/drm/i915/display/g4x_hdmi.c
253
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
262
intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
drivers/gpu/drm/i915/display/g4x_hdmi.c
278
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
282
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
290
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
291
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
292
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
293
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
30
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
304
intel_de_write(display, intel_hdmi->hdmi_reg,
drivers/gpu/drm/i915/display/g4x_hdmi.c
306
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
312
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
313
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
314
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
315
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
324
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
330
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
345
intel_de_rmw(display, TRANS_CHICKEN1(pipe),
drivers/gpu/drm/i915/display/g4x_hdmi.c
352
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
353
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
359
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
360
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
362
intel_de_rmw(display, TRANS_CHICKEN1(pipe),
drivers/gpu/drm/i915/display/g4x_hdmi.c
379
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
386
temp = intel_de_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
389
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
39
if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range)
drivers/gpu/drm/i915/display/g4x_hdmi.c
390
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
397
if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {
drivers/gpu/drm/i915/display/g4x_hdmi.c
402
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/g4x_hdmi.c
403
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/g4x_hdmi.c
411
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
412
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
413
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
414
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
417
intel_de_write(display, intel_hdmi->hdmi_reg, temp);
drivers/gpu/drm/i915/display/g4x_hdmi.c
418
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
420
intel_wait_for_vblank_if_active(display, PIPE_A);
drivers/gpu/drm/i915/display/g4x_hdmi.c
421
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/g4x_hdmi.c
422
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/g4x_hdmi.c
54
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/g4x_hdmi.c
56
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/g4x_hdmi.c
597
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/g4x_hdmi.c
606
if (!display->platform.g4x)
drivers/gpu/drm/i915/display/g4x_hdmi.c
61
intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);
drivers/gpu/drm/i915/display/g4x_hdmi.c
62
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
drivers/gpu/drm/i915/display/g4x_hdmi.c
620
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/g4x_hdmi.c
629
drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/g4x_hdmi.c
654
static bool is_hdmi_port_valid(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/g4x_hdmi.c
656
if (display->platform.g4x || display->platform.valleyview)
drivers/gpu/drm/i915/display/g4x_hdmi.c
662
static bool assert_hdmi_port_valid(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/g4x_hdmi.c
664
return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port),
drivers/gpu/drm/i915/display/g4x_hdmi.c
668
bool g4x_hdmi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_hdmi.c
676
if (!assert_port_valid(display, port))
drivers/gpu/drm/i915/display/g4x_hdmi.c
679
if (!assert_hdmi_port_valid(display, port))
drivers/gpu/drm/i915/display/g4x_hdmi.c
68
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/g4x_hdmi.c
682
devdata = intel_bios_encoder_data_lookup(display, port);
drivers/gpu/drm/i915/display/g4x_hdmi.c
686
drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",
drivers/gpu/drm/i915/display/g4x_hdmi.c
701
if (drm_encoder_init(display->drm, &intel_encoder->base,
drivers/gpu/drm/i915/display/g4x_hdmi.c
708
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/g4x_hdmi.c
716
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/g4x_hdmi.c
722
} else if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/g4x_hdmi.c
729
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/g4x_hdmi.c
73
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/g4x_hdmi.c
731
else if (HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/g4x_hdmi.c
741
intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
drivers/gpu/drm/i915/display/g4x_hdmi.c
743
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/g4x_hdmi.c
758
if (display->platform.g4x)
drivers/gpu/drm/i915/display/g4x_hdmi.c
78
ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);
drivers/gpu/drm/i915/display/g4x_hdmi.c
80
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/g4x_hdmi.h
19
bool g4x_hdmi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/g4x_hdmi.h
24
static inline bool g4x_hdmi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/hsw_ips.c
116
if (display->platform.haswell &&
drivers/gpu/drm/i915/display/hsw_ips.c
139
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/hsw_ips.c
157
if (display->platform.haswell &&
drivers/gpu/drm/i915/display/hsw_ips.c
187
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/hsw_ips.c
189
return HAS_IPS(display) && crtc->pipe == PIPE_A;
drivers/gpu/drm/i915/display/hsw_ips.c
207
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/hsw_ips.c
209
if (display->platform.broadwell)
drivers/gpu/drm/i915/display/hsw_ips.c
21
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/hsw_ips.c
218
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/hsw_ips.c
230
if (min_cdclk > display->cdclk.max_cdclk_freq)
drivers/gpu/drm/i915/display/hsw_ips.c
239
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/hsw_ips.c
248
if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq)
drivers/gpu/drm/i915/display/hsw_ips.c
251
if (!display->params.enable_ips)
drivers/gpu/drm/i915/display/hsw_ips.c
274
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/hsw_ips.c
280
if (display->platform.haswell) {
drivers/gpu/drm/i915/display/hsw_ips.c
281
crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
drivers/gpu/drm/i915/display/hsw_ips.c
295
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/hsw_ips.c
297
*val = display->ips.false_color;
drivers/gpu/drm/i915/display/hsw_ips.c
305
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/hsw_ips.c
313
display->ips.false_color = val;
drivers/gpu/drm/i915/display/hsw_ips.c
32
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/hsw_ips.c
340
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/hsw_ips.c
343
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/hsw_ips.c
346
str_yes_no(display->params.enable_ips));
drivers/gpu/drm/i915/display/hsw_ips.c
348
if (DISPLAY_VER(display) >= 8) {
drivers/gpu/drm/i915/display/hsw_ips.c
351
if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
drivers/gpu/drm/i915/display/hsw_ips.c
357
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/hsw_ips.c
37
if (display->ips.false_color)
drivers/gpu/drm/i915/display/hsw_ips.c
40
if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/hsw_ips.c
41
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/hsw_ips.c
42
intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL,
drivers/gpu/drm/i915/display/hsw_ips.c
51
intel_de_write(display, IPS_CTL, val);
drivers/gpu/drm/i915/display/hsw_ips.c
59
if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))
drivers/gpu/drm/i915/display/hsw_ips.c
60
drm_err(display->drm,
drivers/gpu/drm/i915/display/hsw_ips.c
67
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/hsw_ips.c
73
if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/hsw_ips.c
74
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/hsw_ips.c
75
intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL, 0));
drivers/gpu/drm/i915/display/hsw_ips.c
81
if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))
drivers/gpu/drm/i915/display/hsw_ips.c
82
drm_err(display->drm,
drivers/gpu/drm/i915/display/hsw_ips.c
85
intel_de_write(display, IPS_CTL, 0);
drivers/gpu/drm/i915/display/hsw_ips.c
86
intel_de_posting_read(display, IPS_CTL);
drivers/gpu/drm/i915/display/hsw_ips.c
98
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
15
static void i9xx_display_save_swf(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
20
if (DISPLAY_VER(display) == 2 && display->platform.mobile) {
drivers/gpu/drm/i915/display/i9xx_display_sr.c
22
display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
23
display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
26
display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
27
} else if (DISPLAY_VER(display) == 2) {
drivers/gpu/drm/i915/display/i9xx_display_sr.c
29
display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
30
} else if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/i9xx_display_sr.c
32
display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
33
display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
36
display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
40
static void i9xx_display_restore_swf(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
45
if (DISPLAY_VER(display) == 2 && display->platform.mobile) {
drivers/gpu/drm/i915/display/i9xx_display_sr.c
47
intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
48
intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
51
intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
52
} else if (DISPLAY_VER(display) == 2) {
drivers/gpu/drm/i915/display/i9xx_display_sr.c
54
intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
55
} else if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/i9xx_display_sr.c
57
intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
58
intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
61
intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
65
void i9xx_display_sr_save(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
67
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
69
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/i9xx_display_sr.c
73
if (DISPLAY_VER(display) <= 4)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
74
display->restore.saveDSPARB = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_display_sr.c
76
if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
77
pci_read_config_word(pdev, GCDGMBUS, &display->restore.saveGCDGMBUS);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
79
i9xx_display_save_swf(display);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
82
void i9xx_display_sr_restore(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
84
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
86
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/i9xx_display_sr.c
89
i9xx_display_restore_swf(display);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
91
if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
92
pci_write_config_word(pdev, GCDGMBUS, display->restore.saveGCDGMBUS);
drivers/gpu/drm/i915/display/i9xx_display_sr.c
95
if (DISPLAY_VER(display) <= 4)
drivers/gpu/drm/i915/display/i9xx_display_sr.c
96
intel_de_write(display, DSPARB(display), display->restore.saveDSPARB);
drivers/gpu/drm/i915/display/i9xx_display_sr.h
11
void i9xx_display_sr_save(struct intel_display *display);
drivers/gpu/drm/i915/display/i9xx_display_sr.h
12
void i9xx_display_sr_restore(struct intel_display *display);
drivers/gpu/drm/i915/display/i9xx_plane.c
1004
if (display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/i9xx_plane.c
1010
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/i9xx_plane.c
1012
else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/i9xx_plane.c
1014
else if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
1020
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/i9xx_plane.c
1023
if (display->platform.i830 || display->platform.i845g) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1033
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
1038
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/i9xx_plane.c
1040
else if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
1045
if (HAS_ASYNC_FLIPS(display)) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1046
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1051
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1057
} else if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1062
} else if (DISPLAY_VER(display) >= 5) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1072
modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);
drivers/gpu/drm/i915/display/i9xx_plane.c
1074
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/i9xx_plane.c
1075
ret = drm_universal_plane_init(display->drm, &plane->base,
drivers/gpu/drm/i915/display/i9xx_plane.c
1082
ret = drm_universal_plane_init(display->drm, &plane->base,
drivers/gpu/drm/i915/display/i9xx_plane.c
1095
if (display->platform.cherryview && pipe == PIPE_B) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1099
} else if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1106
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
114
static bool i9xx_plane_has_fbc(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1161
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_plane.c
117
if (!HAS_FBC(display))
drivers/gpu/drm/i915/display/i9xx_plane.c
1174
drm_WARN_ON(display->drm, pipe != crtc->pipe);
drivers/gpu/drm/i915/display/i9xx_plane.c
1178
drm_dbg_kms(display->drm, "failed to alloc fb\n");
drivers/gpu/drm/i915/display/i9xx_plane.c
1184
fb->dev = display->drm;
drivers/gpu/drm/i915/display/i9xx_plane.c
1186
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1188
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1196
if (display->platform.cherryview &&
drivers/gpu/drm/i915/display/i9xx_plane.c
120
if (display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/i9xx_plane.c
1203
fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier);
drivers/gpu/drm/i915/display/i9xx_plane.c
1205
if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1206
offset = intel_de_read(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1207
DSPOFFSET(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1208
base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;
drivers/gpu/drm/i915/display/i9xx_plane.c
1209
} else if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
1211
offset = intel_de_read(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1212
DSPTILEOFF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1214
offset = intel_de_read(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
1215
DSPLINOFF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1216
base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;
drivers/gpu/drm/i915/display/i9xx_plane.c
1219
base = intel_de_read(display, DSPADDR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
122
else if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/i9xx_plane.c
1223
drm_WARN_ON(display->drm, offset != 0);
drivers/gpu/drm/i915/display/i9xx_plane.c
1225
val = intel_de_read(display, PIPESRC(display, pipe));
drivers/gpu/drm/i915/display/i9xx_plane.c
1229
val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
1236
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_plane.c
1249
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_plane.c
125
else if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
1265
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
1266
intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);
drivers/gpu/drm/i915/display/i9xx_plane.c
1268
intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);
drivers/gpu/drm/i915/display/i9xx_plane.c
131
static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_plane.c
134
if (i9xx_plane_has_fbc(display, i9xx_plane))
drivers/gpu/drm/i915/display/i9xx_plane.c
135
return display->fbc.instances[INTEL_FBC_A];
drivers/gpu/drm/i915/display/i9xx_plane.c
142
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
145
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/i9xx_plane.c
147
else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/i9xx_plane.c
149
else if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
158
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/i9xx_plane.c
165
if (display->platform.g4x || display->platform.ironlake ||
drivers/gpu/drm/i915/display/i9xx_plane.c
166
display->platform.sandybridge || display->platform.ivybridge)
drivers/gpu/drm/i915/display/i9xx_plane.c
214
if (DISPLAY_VER(display) >= 4 &&
drivers/gpu/drm/i915/display/i9xx_plane.c
229
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/i9xx_plane.c
248
if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) {
drivers/gpu/drm/i915/display/i9xx_plane.c
249
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_plane.c
257
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
274
if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {
drivers/gpu/drm/i915/display/i9xx_plane.c
280
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_plane.c
299
if (!display->platform.haswell && !display->platform.broadwell) {
drivers/gpu/drm/i915/display/i9xx_plane.c
312
if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/i9xx_plane.c
313
drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095);
drivers/gpu/drm/i915/display/i9xx_plane.c
314
} else if (DISPLAY_VER(display) >= 4 &&
drivers/gpu/drm/i915/display/i9xx_plane.c
316
drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095);
drivers/gpu/drm/i915/display/i9xx_plane.c
375
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_plane.c
385
if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/i9xx_plane.c
443
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
446
intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
449
if (DISPLAY_VER(display) < 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
460
intel_de_write_fw(display, DSPPOS(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
462
intel_de_write_fw(display, DSPSIZE(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
472
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
485
if (display->platform.cherryview && i9xx_plane == PLANE_B) {
drivers/gpu/drm/i915/display/i9xx_plane.c
491
intel_de_write_fw(display, PRIMPOS(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
493
intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
495
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/i9xx_plane.c
496
PRIMCNSTALPHA(display, i9xx_plane), 0);
drivers/gpu/drm/i915/display/i9xx_plane.c
499
if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/i9xx_plane.c
500
intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
502
} else if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
503
intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
505
intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane),
drivers/gpu/drm/i915/display/i9xx_plane.c
514
intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
drivers/gpu/drm/i915/display/i9xx_plane.c
516
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
517
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);
drivers/gpu/drm/i915/display/i9xx_plane.c
519
intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);
drivers/gpu/drm/i915/display/i9xx_plane.c
541
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
557
intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
drivers/gpu/drm/i915/display/i9xx_plane.c
559
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
560
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0);
drivers/gpu/drm/i915/display/i9xx_plane.c
562
intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0);
drivers/gpu/drm/i915/display/i9xx_plane.c
569
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
572
error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
573
error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
574
error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
581
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
584
error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
585
error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
592
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
595
error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
596
error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
606
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
613
intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
drivers/gpu/drm/i915/display/i9xx_plane.c
614
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);
drivers/gpu/drm/i915/display/i9xx_plane.c
624
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
627
intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);
drivers/gpu/drm/i915/display/i9xx_plane.c
633
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
636
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
637
bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
drivers/gpu/drm/i915/display/i9xx_plane.c
638
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
644
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
647
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
648
bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
drivers/gpu/drm/i915/display/i9xx_plane.c
649
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
655
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
657
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
658
ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
659
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
665
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
667
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
668
ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
669
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
675
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
677
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
678
ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
679
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
685
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
687
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
688
ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
689
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
695
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
698
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
699
i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
drivers/gpu/drm/i915/display/i9xx_plane.c
700
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
706
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
709
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
710
i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
drivers/gpu/drm/i915/display/i9xx_plane.c
711
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/i9xx_plane.c
722
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
735
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/i9xx_plane.c
739
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
743
if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/i9xx_plane.c
748
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/i9xx_plane.c
818
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
824
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/i9xx_plane.c
842
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
847
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/i9xx_plane.c
904
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
909
dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
911
intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
drivers/gpu/drm/i915/display/i9xx_plane.c
913
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
914
reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
915
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg);
drivers/gpu/drm/i915/display/i9xx_plane.c
918
reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));
drivers/gpu/drm/i915/display/i9xx_plane.c
919
intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg);
drivers/gpu/drm/i915/display/i9xx_plane.c
924
intel_primary_plane_create(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/i9xx_plane.c
943
if (HAS_FBC(display) && DISPLAY_VER(display) < 4 &&
drivers/gpu/drm/i915/display/i9xx_plane.c
944
INTEL_NUM_PIPES(display) == 2)
drivers/gpu/drm/i915/display/i9xx_plane.c
951
intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane);
drivers/gpu/drm/i915/display/i9xx_plane.c
953
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_plane.c
956
} else if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/i9xx_plane.c
970
if (display->platform.ivybridge) {
drivers/gpu/drm/i915/display/i9xx_plane.c
982
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
987
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/i9xx_plane.c
989
else if (display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/i9xx_plane.c
991
else if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/i9xx_plane.c
996
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/i9xx_plane.c
997
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/i9xx_plane.c
999
else if (DISPLAY_VER(display) == 3)
drivers/gpu/drm/i915/display/i9xx_plane.h
31
intel_primary_plane_create(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/i9xx_plane.h
49
intel_primary_plane_create(struct intel_display *display, int pipe)
drivers/gpu/drm/i915/display/i9xx_wm.c
1027
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
1030
for (; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1043
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
1049
for (; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1066
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
1079
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
108
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1119
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1127
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1147
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
1149
if (level >= display->wm.num_levels)
drivers/gpu/drm/i915/display/i9xx_wm.c
116
static void chv_set_memory_dvfs(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/i9xx_wm.c
121
vlv_punit_get(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
123
val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2);
drivers/gpu/drm/i915/display/i9xx_wm.c
1291
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/i9xx_wm.c
130
vlv_punit_write(display, PUNIT_REG_DDR_SETUP2, val);
drivers/gpu/drm/i915/display/i9xx_wm.c
132
ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2),
drivers/gpu/drm/i915/display/i9xx_wm.c
1321
drm_WARN_ON(display->drm, intermediate->wm.plane[plane_id] >
drivers/gpu/drm/i915/display/i9xx_wm.c
1339
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1345
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1352
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1355
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
136
drm_err(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
1386
static void g4x_merge_wm(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
139
vlv_punit_put(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
1396
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1418
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
142
static void chv_set_memory_pm5(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/i9xx_wm.c
1430
static void g4x_program_watermarks(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
1432
struct g4x_wm_values *old_wm = &display->wm.g4x;
drivers/gpu/drm/i915/display/i9xx_wm.c
1435
g4x_merge_wm(display, &new_wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
1441
_intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
1443
g4x_write_wm_values(display, &new_wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
1446
_intel_set_memory_cxsr(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
1454
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
1458
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
146
vlv_punit_get(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
1460
g4x_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
1461
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
1467
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
1474
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
1476
g4x_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
1477
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
148
val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);
drivers/gpu/drm/i915/display/i9xx_wm.c
1496
static void vlv_setup_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
1499
display->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
drivers/gpu/drm/i915/display/i9xx_wm.c
1501
display->wm.num_levels = VLV_WM_LEVEL_PM2 + 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
1503
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1504
display->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
drivers/gpu/drm/i915/display/i9xx_wm.c
1505
display->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
drivers/gpu/drm/i915/display/i9xx_wm.c
1507
display->wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
1515
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
1521
if (display->wm.pri_latency[level] == 0)
drivers/gpu/drm/i915/display/i9xx_wm.c
153
vlv_punit_write(display, PUNIT_REG_DSPSSPM, val);
drivers/gpu/drm/i915/display/i9xx_wm.c
1542
display->wm.pri_latency[level] * 10);
drivers/gpu/drm/i915/display/i9xx_wm.c
155
vlv_punit_put(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
1556
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
161
static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/i9xx_wm.c
1626
drm_WARN_ON(display->drm, active_planes != 0 && fifo_left != 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
1630
drm_WARN_ON(display->drm, fifo_left != fifo_size);
drivers/gpu/drm/i915/display/i9xx_wm.c
1641
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
1643
for (; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
166
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1669
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
167
was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
drivers/gpu/drm/i915/display/i9xx_wm.c
1672
for (; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
168
intel_de_write(display, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
1685
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
169
intel_de_posting_read(display, FW_BLC_SELF_VLV);
drivers/gpu/drm/i915/display/i9xx_wm.c
1696
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
170
} else if (display->platform.g4x || display->platform.i965gm) {
drivers/gpu/drm/i915/display/i9xx_wm.c
171
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
1713
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
172
intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
173
intel_de_posting_read(display, FW_BLC_SELF);
drivers/gpu/drm/i915/display/i9xx_wm.c
174
} else if (display->platform.pineview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1744
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
175
val = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
1755
wm_state->num_levels = display->wm.num_levels;
drivers/gpu/drm/i915/display/i9xx_wm.c
1765
const int sr_fifo_size = INTEL_NUM_PIPES(display) * 512 - 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
181
intel_de_write(display, DSPFW3(display), val);
drivers/gpu/drm/i915/display/i9xx_wm.c
182
intel_de_posting_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
183
} else if (display->platform.i945g || display->platform.i945gm) {
drivers/gpu/drm/i915/display/i9xx_wm.c
184
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
1865
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
1866
struct intel_uncore *uncore = to_intel_uncore(display->drm);
drivers/gpu/drm/i915/display/i9xx_wm.c
187
intel_de_write(display, FW_BLC_SELF, val);
drivers/gpu/drm/i915/display/i9xx_wm.c
188
intel_de_posting_read(display, FW_BLC_SELF);
drivers/gpu/drm/i915/display/i9xx_wm.c
1881
drm_WARN_ON(display->drm, fifo_state->plane[PLANE_CURSOR] != 63);
drivers/gpu/drm/i915/display/i9xx_wm.c
1882
drm_WARN_ON(display->drm, fifo_size != 511);
drivers/gpu/drm/i915/display/i9xx_wm.c
189
} else if (display->platform.i915gm) {
drivers/gpu/drm/i915/display/i9xx_wm.c
1899
dsparb = intel_de_read_fw(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
1900
dsparb2 = intel_de_read_fw(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
1912
intel_de_write_fw(display, DSPARB(display), dsparb);
drivers/gpu/drm/i915/display/i9xx_wm.c
1913
intel_de_write_fw(display, DSPARB2, dsparb2);
drivers/gpu/drm/i915/display/i9xx_wm.c
1916
dsparb = intel_de_read_fw(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
1917
dsparb2 = intel_de_read_fw(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
1929
intel_de_write_fw(display, DSPARB(display), dsparb);
drivers/gpu/drm/i915/display/i9xx_wm.c
1930
intel_de_write_fw(display, DSPARB2, dsparb2);
drivers/gpu/drm/i915/display/i9xx_wm.c
1933
dsparb3 = intel_de_read_fw(display, DSPARB3);
drivers/gpu/drm/i915/display/i9xx_wm.c
1934
dsparb2 = intel_de_read_fw(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
1946
intel_de_write_fw(display, DSPARB3, dsparb3);
drivers/gpu/drm/i915/display/i9xx_wm.c
1947
intel_de_write_fw(display, DSPARB2, dsparb2);
drivers/gpu/drm/i915/display/i9xx_wm.c
195
was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
1953
intel_de_read_fw(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
198
intel_de_write(display, INSTPM, val);
drivers/gpu/drm/i915/display/i9xx_wm.c
199
intel_de_posting_read(display, INSTPM);
drivers/gpu/drm/i915/display/i9xx_wm.c
2028
static void vlv_merge_wm(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2034
wm->level = display->wm.num_levels - 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
2037
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
204
trace_intel_memory_cxsr(display, was_enabled, enable);
drivers/gpu/drm/i915/display/i9xx_wm.c
2056
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
206
drm_dbg_kms(display->drm, "memory self-refresh is %s (was %s)\n",
drivers/gpu/drm/i915/display/i9xx_wm.c
2071
static void vlv_program_watermarks(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2073
struct vlv_wm_values *old_wm = &display->wm.vlv;
drivers/gpu/drm/i915/display/i9xx_wm.c
2076
vlv_merge_wm(display, &new_wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
2082
chv_set_memory_dvfs(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2085
chv_set_memory_pm5(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2088
_intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2090
vlv_write_wm_values(display, &new_wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
2093
_intel_set_memory_cxsr(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2096
chv_set_memory_pm5(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2099
chv_set_memory_dvfs(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2107
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
2111
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
2113
vlv_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2114
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
2120
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
2127
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
2129
vlv_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2130
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
2133
static void i965_update_wm(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2141
crtc = single_enabled_crtc(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2162
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2177
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2185
intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2188
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2193
intel_de_write(display, DSPFW1(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
2198
intel_de_write(display, DSPFW2(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
2202
intel_de_write(display, DSPFW3(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
2206
intel_set_memory_cxsr(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2211
static struct intel_crtc *intel_crtc_for_plane(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2216
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/i9xx_wm.c
2219
return intel_crtc_for_pipe(display, plane->pipe);
drivers/gpu/drm/i915/display/i9xx_wm.c
2225
static void i9xx_update_wm(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2235
if (display->platform.i945gm)
drivers/gpu/drm/i915/display/i9xx_wm.c
2237
else if (DISPLAY_VER(display) != 2)
drivers/gpu/drm/i915/display/i9xx_wm.c
2242
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/i9xx_wm.c
2243
fifo_size = i830_get_fifo_size(display, PLANE_A);
drivers/gpu/drm/i915/display/i9xx_wm.c
2245
fifo_size = i9xx_get_fifo_size(display, PLANE_A);
drivers/gpu/drm/i915/display/i9xx_wm.c
2246
crtc = intel_crtc_for_plane(display, PLANE_A);
drivers/gpu/drm/i915/display/i9xx_wm.c
2252
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/i9xx_wm.c
2257
planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
2266
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/i9xx_wm.c
2269
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/i9xx_wm.c
2270
fifo_size = i830_get_fifo_size(display, PLANE_B);
drivers/gpu/drm/i915/display/i9xx_wm.c
2272
fifo_size = i9xx_get_fifo_size(display, PLANE_B);
drivers/gpu/drm/i915/display/i9xx_wm.c
2273
crtc = intel_crtc_for_plane(display, PLANE_B);
drivers/gpu/drm/i915/display/i9xx_wm.c
2279
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/i9xx_wm.c
2284
planeb_wm = intel_calculate_wm(display, crtc->config->pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
2293
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2296
crtc = single_enabled_crtc(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2297
if (display->platform.i915gm && crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
2312
intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2315
if (HAS_FW_BLC(display) && crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
2328
if (display->platform.i915gm || display->platform.i945gm)
drivers/gpu/drm/i915/display/i9xx_wm.c
2336
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2342
if (display->platform.i945g || display->platform.i945gm)
drivers/gpu/drm/i915/display/i9xx_wm.c
2343
intel_de_write(display, FW_BLC_SELF,
drivers/gpu/drm/i915/display/i9xx_wm.c
2346
intel_de_write(display, FW_BLC_SELF, srwm & 0x3f);
drivers/gpu/drm/i915/display/i9xx_wm.c
2349
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2360
intel_de_write(display, FW_BLC, fwater_lo);
drivers/gpu/drm/i915/display/i9xx_wm.c
2361
intel_de_write(display, FW_BLC2, fwater_hi);
drivers/gpu/drm/i915/display/i9xx_wm.c
2364
intel_set_memory_cxsr(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2367
static void i845_update_wm(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2373
crtc = single_enabled_crtc(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2377
planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
2379
i845_get_fifo_size(display, PLANE_A),
drivers/gpu/drm/i915/display/i9xx_wm.c
2381
fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;
drivers/gpu/drm/i915/display/i9xx_wm.c
2384
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2387
intel_de_write(display, FW_BLC, fwater_lo);
drivers/gpu/drm/i915/display/i9xx_wm.c
250
bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/i9xx_wm.c
254
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
2542
ilk_display_fifo_size(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2544
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/i9xx_wm.c
2546
else if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/i9xx_wm.c
255
ret = _intel_set_memory_cxsr(display, enable);
drivers/gpu/drm/i915/display/i9xx_wm.c
2553
ilk_plane_wm_reg_max(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2556
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/i9xx_wm.c
2559
else if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/i9xx_wm.c
256
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/i9xx_wm.c
257
display->wm.vlv.cxsr = enable;
drivers/gpu/drm/i915/display/i9xx_wm.c
2571
ilk_cursor_wm_reg_max(struct intel_display *display, int level)
drivers/gpu/drm/i915/display/i9xx_wm.c
2573
if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/i9xx_wm.c
2579
static unsigned int ilk_fbc_wm_reg_max(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
258
else if (display->platform.g4x)
drivers/gpu/drm/i915/display/i9xx_wm.c
2581
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/i9xx_wm.c
2588
static unsigned int ilk_plane_wm_max(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
259
display->wm.g4x.cxsr = enable;
drivers/gpu/drm/i915/display/i9xx_wm.c
2594
unsigned int fifo_size = ilk_display_fifo_size(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
260
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
2602
fifo_size /= INTEL_NUM_PIPES(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2609
if (DISPLAY_VER(display) < 7)
drivers/gpu/drm/i915/display/i9xx_wm.c
2625
return min(fifo_size, ilk_plane_wm_reg_max(display, level, is_sprite));
drivers/gpu/drm/i915/display/i9xx_wm.c
2629
static unsigned int ilk_cursor_wm_max(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2638
return ilk_cursor_wm_reg_max(display, level);
drivers/gpu/drm/i915/display/i9xx_wm.c
2641
static void ilk_compute_wm_maximums(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2647
max->pri = ilk_plane_wm_max(display, level, config, ddb_partitioning, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2648
max->spr = ilk_plane_wm_max(display, level, config, ddb_partitioning, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2649
max->cur = ilk_cursor_wm_max(display, level, config);
drivers/gpu/drm/i915/display/i9xx_wm.c
2650
max->fbc = ilk_fbc_wm_reg_max(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2653
static void ilk_compute_wm_reg_maximums(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2657
max->pri = ilk_plane_wm_reg_max(display, level, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
2658
max->spr = ilk_plane_wm_reg_max(display, level, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
2659
max->cur = ilk_cursor_wm_reg_max(display, level);
drivers/gpu/drm/i915/display/i9xx_wm.c
2660
max->fbc = ilk_fbc_wm_reg_max(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2663
static bool ilk_validate_wm_level(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2687
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2691
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2695
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2708
static void ilk_compute_wm_level(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2717
u16 pri_latency = display->wm.pri_latency[level];
drivers/gpu/drm/i915/display/i9xx_wm.c
2718
u16 spr_latency = display->wm.spr_latency[level];
drivers/gpu/drm/i915/display/i9xx_wm.c
2719
u16 cur_latency = display->wm.cur_latency[level];
drivers/gpu/drm/i915/display/i9xx_wm.c
2743
static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])
drivers/gpu/drm/i915/display/i9xx_wm.c
2747
display->wm.num_levels = 5;
drivers/gpu/drm/i915/display/i9xx_wm.c
2749
sskpd = intel_mchbar_read64_2x32(display, MCH_SSKPD);
drivers/gpu/drm/i915/display/i9xx_wm.c
2760
static void snb_read_wm_latency(struct intel_display *display, u16 wm[])
drivers/gpu/drm/i915/display/i9xx_wm.c
2764
display->wm.num_levels = 4;
drivers/gpu/drm/i915/display/i9xx_wm.c
2766
sskpd = intel_mchbar_read(display, MCH_SSKPD);
drivers/gpu/drm/i915/display/i9xx_wm.c
2774
static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])
drivers/gpu/drm/i915/display/i9xx_wm.c
2778
display->wm.num_levels = 3;
drivers/gpu/drm/i915/display/i9xx_wm.c
2780
mltr = intel_mchbar_read(display, MLTR_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
2788
static void intel_fixup_spr_wm_latency(struct intel_display *display, u16 wm[5])
drivers/gpu/drm/i915/display/i9xx_wm.c
2791
if (DISPLAY_VER(display) == 5)
drivers/gpu/drm/i915/display/i9xx_wm.c
2795
static void intel_fixup_cur_wm_latency(struct intel_display *display, u16 wm[5])
drivers/gpu/drm/i915/display/i9xx_wm.c
2798
if (DISPLAY_VER(display) == 5)
drivers/gpu/drm/i915/display/i9xx_wm.c
2802
static bool ilk_increase_wm_latency(struct intel_display *display, u16 wm[5], u16 min)
drivers/gpu/drm/i915/display/i9xx_wm.c
2810
for (level = 1; level < display->wm.num_levels; level++)
drivers/gpu/drm/i915/display/i9xx_wm.c
2816
static void snb_wm_latency_quirk(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2824
changed = ilk_increase_wm_latency(display, display->wm.pri_latency, 12);
drivers/gpu/drm/i915/display/i9xx_wm.c
2825
changed |= ilk_increase_wm_latency(display, display->wm.spr_latency, 12);
drivers/gpu/drm/i915/display/i9xx_wm.c
2826
changed |= ilk_increase_wm_latency(display, display->wm.cur_latency, 12);
drivers/gpu/drm/i915/display/i9xx_wm.c
2831
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2833
intel_print_wm_latency(display, "Primary", display->wm.pri_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2834
intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2835
intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2838
static void snb_wm_lp3_irq_quirk(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2851
if (display->wm.pri_latency[3] == 0 &&
drivers/gpu/drm/i915/display/i9xx_wm.c
2852
display->wm.spr_latency[3] == 0 &&
drivers/gpu/drm/i915/display/i9xx_wm.c
2853
display->wm.cur_latency[3] == 0)
drivers/gpu/drm/i915/display/i9xx_wm.c
2856
display->wm.pri_latency[3] = 0;
drivers/gpu/drm/i915/display/i9xx_wm.c
2857
display->wm.spr_latency[3] = 0;
drivers/gpu/drm/i915/display/i9xx_wm.c
2858
display->wm.cur_latency[3] = 0;
drivers/gpu/drm/i915/display/i9xx_wm.c
286
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
2860
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
2862
intel_print_wm_latency(display, "Primary", display->wm.pri_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2863
intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2864
intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2867
static void ilk_setup_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
2869
if (display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/i9xx_wm.c
2870
hsw_read_wm_latency(display, display->wm.pri_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2871
else if (DISPLAY_VER(display) >= 6)
drivers/gpu/drm/i915/display/i9xx_wm.c
2872
snb_read_wm_latency(display, display->wm.pri_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2874
ilk_read_wm_latency(display, display->wm.pri_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2876
memcpy(display->wm.spr_latency, display->wm.pri_latency,
drivers/gpu/drm/i915/display/i9xx_wm.c
2877
sizeof(display->wm.pri_latency));
drivers/gpu/drm/i915/display/i9xx_wm.c
2878
memcpy(display->wm.cur_latency, display->wm.pri_latency,
drivers/gpu/drm/i915/display/i9xx_wm.c
2879
sizeof(display->wm.pri_latency));
drivers/gpu/drm/i915/display/i9xx_wm.c
2881
intel_fixup_spr_wm_latency(display, display->wm.spr_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2882
intel_fixup_cur_wm_latency(display, display->wm.cur_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2884
intel_print_wm_latency(display, "Primary", display->wm.pri_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2885
intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2886
intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);
drivers/gpu/drm/i915/display/i9xx_wm.c
2888
if (DISPLAY_VER(display) == 6) {
drivers/gpu/drm/i915/display/i9xx_wm.c
2889
snb_wm_latency_quirk(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2890
snb_wm_lp3_irq_quirk(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
2894
static bool ilk_validate_pipe_wm(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
2906
ilk_compute_wm_maximums(display, 0, &config, INTEL_DDB_PART_1_2, &max);
drivers/gpu/drm/i915/display/i9xx_wm.c
2909
if (!ilk_validate_wm_level(display, 0, &max, &pipe_wm->wm[0])) {
drivers/gpu/drm/i915/display/i9xx_wm.c
2910
drm_dbg_kms(display->drm, "LP0 watermark invalid\n");
drivers/gpu/drm/i915/display/i9xx_wm.c
2921
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/i9xx_wm.c
2948
usable_level = display->wm.num_levels - 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
295
dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
2951
if (DISPLAY_VER(display) < 7 && pipe_wm->sprites_enabled)
drivers/gpu/drm/i915/display/i9xx_wm.c
2959
ilk_compute_wm_level(display, crtc, 0, crtc_state,
drivers/gpu/drm/i915/display/i9xx_wm.c
296
dsparb2 = intel_de_read(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
2962
if (!ilk_validate_pipe_wm(display, pipe_wm))
drivers/gpu/drm/i915/display/i9xx_wm.c
2965
ilk_compute_wm_reg_maximums(display, 1, &max);
drivers/gpu/drm/i915/display/i9xx_wm.c
2970
ilk_compute_wm_level(display, crtc, level, crtc_state,
drivers/gpu/drm/i915/display/i9xx_wm.c
2978
if (!ilk_validate_wm_level(display, level, &max, wm)) {
drivers/gpu/drm/i915/display/i9xx_wm.c
2995
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
301
dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
302
dsparb2 = intel_de_read(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
3020
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3041
if (!ilk_validate_pipe_wm(display, intermediate))
drivers/gpu/drm/i915/display/i9xx_wm.c
307
dsparb2 = intel_de_read(display, DSPARB2);
drivers/gpu/drm/i915/display/i9xx_wm.c
3073
static void ilk_merge_wm_level(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
308
dsparb3 = intel_de_read(display, DSPARB3);
drivers/gpu/drm/i915/display/i9xx_wm.c
3081
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3106
static void ilk_wm_merge(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3111
int level, num_levels = display->wm.num_levels;
drivers/gpu/drm/i915/display/i9xx_wm.c
3115
if ((DISPLAY_VER(display) < 7 || display->platform.ivybridge) &&
drivers/gpu/drm/i915/display/i9xx_wm.c
3120
merged->fbc_wm_enabled = DISPLAY_VER(display) >= 6;
drivers/gpu/drm/i915/display/i9xx_wm.c
3126
ilk_merge_wm_level(display, level, wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
3130
else if (!ilk_validate_wm_level(display, level, max, wm))
drivers/gpu/drm/i915/display/i9xx_wm.c
3146
if (DISPLAY_VER(display) == 5 && HAS_FBC(display) &&
drivers/gpu/drm/i915/display/i9xx_wm.c
3147
display->params.enable_fbc && !merged->fbc_wm_enabled) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3163
static unsigned int ilk_wm_lp_latency(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3166
if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/i9xx_wm.c
3169
return display->wm.pri_latency[level];
drivers/gpu/drm/i915/display/i9xx_wm.c
3172
static void ilk_compute_wm_results(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3196
WM_LP_LATENCY(ilk_wm_lp_latency(display, level)) |
drivers/gpu/drm/i915/display/i9xx_wm.c
3203
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/i9xx_wm.c
3214
if (DISPLAY_VER(display) < 7 && r->spr_val) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3215
drm_WARN_ON(display->drm, wm_lp != 1);
drivers/gpu/drm/i915/display/i9xx_wm.c
3221
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3226
if (drm_WARN_ON(display->drm, !r->enable))
drivers/gpu/drm/i915/display/i9xx_wm.c
323
static int i9xx_get_fifo_size(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3241
ilk_find_best_result(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3247
for (level = 1; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
326
u32 dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3273
static unsigned int ilk_compute_wm_dirty(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3281
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3319
static bool _ilk_disable_lp_wm(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3322
struct ilk_wm_values *previous = &display->wm.hw;
drivers/gpu/drm/i915/display/i9xx_wm.c
3327
intel_de_write(display, WM3_LP_ILK, previous->wm_lp[2]);
drivers/gpu/drm/i915/display/i9xx_wm.c
333
drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",
drivers/gpu/drm/i915/display/i9xx_wm.c
3332
intel_de_write(display, WM2_LP_ILK, previous->wm_lp[1]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3337
intel_de_write(display, WM1_LP_ILK, previous->wm_lp[0]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3353
static void ilk_write_wm_values(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3356
struct ilk_wm_values *previous = &display->wm.hw;
drivers/gpu/drm/i915/display/i9xx_wm.c
3359
dirty = ilk_compute_wm_dirty(display, previous, results);
drivers/gpu/drm/i915/display/i9xx_wm.c
3363
_ilk_disable_lp_wm(display, dirty);
drivers/gpu/drm/i915/display/i9xx_wm.c
3366
intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3368
intel_de_write(display, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3370
intel_de_write(display, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3373
if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/i9xx_wm.c
3374
intel_de_rmw(display, WM_MISC, WM_MISC_DATA_PARTITION_5_6,
drivers/gpu/drm/i915/display/i9xx_wm.c
3378
intel_de_rmw(display, DISP_ARB_CTL2, DISP_DATA_PARTITION_5_6,
drivers/gpu/drm/i915/display/i9xx_wm.c
3384
intel_de_rmw(display, DISP_ARB_CTL, DISP_FBC_WM_DIS,
drivers/gpu/drm/i915/display/i9xx_wm.c
3389
intel_de_write(display, WM1S_LP_ILK, results->wm_lp_spr[0]);
drivers/gpu/drm/i915/display/i9xx_wm.c
339
static int i830_get_fifo_size(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3391
if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3393
intel_de_write(display, WM2S_LP_IVB, results->wm_lp_spr[1]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3395
intel_de_write(display, WM3S_LP_IVB, results->wm_lp_spr[2]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3399
intel_de_write(display, WM1_LP_ILK, results->wm_lp[0]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3401
intel_de_write(display, WM2_LP_ILK, results->wm_lp[1]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3403
intel_de_write(display, WM3_LP_ILK, results->wm_lp[2]);
drivers/gpu/drm/i915/display/i9xx_wm.c
3405
display->wm.hw = *results;
drivers/gpu/drm/i915/display/i9xx_wm.c
3408
bool ilk_disable_cxsr(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
3410
return _ilk_disable_lp_wm(display, WM_DIRTY_LP_ALL);
drivers/gpu/drm/i915/display/i9xx_wm.c
3413
static void ilk_compute_wm_config(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3419
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
342
u32 dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3431
static void ilk_program_watermarks(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
3439
ilk_compute_wm_config(display, &config);
drivers/gpu/drm/i915/display/i9xx_wm.c
3441
ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_1_2, &max);
drivers/gpu/drm/i915/display/i9xx_wm.c
3442
ilk_wm_merge(display, &config, &max, &lp_wm_1_2);
drivers/gpu/drm/i915/display/i9xx_wm.c
3445
if (DISPLAY_VER(display) >= 7 &&
drivers/gpu/drm/i915/display/i9xx_wm.c
3447
ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_5_6, &max);
drivers/gpu/drm/i915/display/i9xx_wm.c
3448
ilk_wm_merge(display, &config, &max, &lp_wm_5_6);
drivers/gpu/drm/i915/display/i9xx_wm.c
3450
best_lp_wm = ilk_find_best_result(display, &lp_wm_1_2, &lp_wm_5_6);
drivers/gpu/drm/i915/display/i9xx_wm.c
3458
ilk_compute_wm_results(display, best_lp_wm, partitioning, &results);
drivers/gpu/drm/i915/display/i9xx_wm.c
3460
ilk_write_wm_values(display, &results);
drivers/gpu/drm/i915/display/i9xx_wm.c
3466
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
3470
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
3472
ilk_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
3473
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
3479
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
3486
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
3488
ilk_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
3489
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
3494
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/i9xx_wm.c
3495
struct ilk_wm_values *hw = &display->wm.hw;
drivers/gpu/drm/i915/display/i9xx_wm.c
350
drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",
drivers/gpu/drm/i915/display/i9xx_wm.c
3500
hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));
drivers/gpu/drm/i915/display/i9xx_wm.c
3527
for (level = 0; level < display->wm.num_levels; level++)
drivers/gpu/drm/i915/display/i9xx_wm.c
3536
struct intel_display *display = to_intel_display(state->dev);
drivers/gpu/drm/i915/display/i9xx_wm.c
3540
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
356
static int i845_get_fifo_size(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3577
void ilk_wm_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
3587
if (!display->wm.funcs->optimize_watermarks)
drivers/gpu/drm/i915/display/i9xx_wm.c
359
u32 dsparb = intel_de_read(display, DSPARB(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3590
if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))
drivers/gpu/drm/i915/display/i9xx_wm.c
3593
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/i9xx_wm.c
3594
if (drm_WARN_ON(display->drm, !state))
drivers/gpu/drm/i915/display/i9xx_wm.c
3610
if (!HAS_GMCH(display))
drivers/gpu/drm/i915/display/i9xx_wm.c
3617
ret = intel_atomic_check(display->drm, state);
drivers/gpu/drm/i915/display/i9xx_wm.c
3647
drm_WARN(display->drm, ret,
drivers/gpu/drm/i915/display/i9xx_wm.c
365
drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",
drivers/gpu/drm/i915/display/i9xx_wm.c
3661
static void g4x_read_wm_values(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3666
tmp = intel_de_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3672
tmp = intel_de_read(display, DSPFW2(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3680
tmp = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3687
static void vlv_read_wm_values(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
3693
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3694
tmp = intel_de_read(display, VLV_DDL(pipe));
drivers/gpu/drm/i915/display/i9xx_wm.c
3706
tmp = intel_de_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3712
tmp = intel_de_read(display, DSPFW2(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3717
tmp = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
3720
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3721
tmp = intel_de_read(display, DSPFW7_CHV);
drivers/gpu/drm/i915/display/i9xx_wm.c
3725
tmp = intel_de_read(display, DSPFW8_CHV);
drivers/gpu/drm/i915/display/i9xx_wm.c
3729
tmp = intel_de_read(display, DSPFW9_CHV);
drivers/gpu/drm/i915/display/i9xx_wm.c
3733
tmp = intel_de_read(display, DSPHOWM);
drivers/gpu/drm/i915/display/i9xx_wm.c
3745
tmp = intel_de_read(display, DSPFW7);
drivers/gpu/drm/i915/display/i9xx_wm.c
3749
tmp = intel_de_read(display, DSPHOWM);
drivers/gpu/drm/i915/display/i9xx_wm.c
3763
static void g4x_wm_get_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
3765
struct g4x_wm_values *wm = &display->wm.g4x;
drivers/gpu/drm/i915/display/i9xx_wm.c
3768
g4x_read_wm_values(display, wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
3770
wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/i9xx_wm.c
3772
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3837
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
3845
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
3848
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
3851
drm_dbg_kms(display->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
drivers/gpu/drm/i915/display/i9xx_wm.c
3856
static void g4x_wm_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
3861
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
3863
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3865
intel_crtc_for_pipe(display, plane->pipe);
drivers/gpu/drm/i915/display/i9xx_wm.c
3876
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3887
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3893
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/i9xx_wm.c
3900
g4x_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
3902
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
3905
static void vlv_wm_get_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
3907
struct vlv_wm_values *wm = &display->wm.vlv;
drivers/gpu/drm/i915/display/i9xx_wm.c
3912
vlv_read_wm_values(display, wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
3914
wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
drivers/gpu/drm/i915/display/i9xx_wm.c
3917
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3918
vlv_punit_get(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
3920
val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);
drivers/gpu/drm/i915/display/i9xx_wm.c
3933
val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2);
drivers/gpu/drm/i915/display/i9xx_wm.c
3935
vlv_punit_write(display, PUNIT_REG_DDR_SETUP2, val);
drivers/gpu/drm/i915/display/i9xx_wm.c
3937
ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2),
drivers/gpu/drm/i915/display/i9xx_wm.c
3941
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
3944
display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
3946
val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2);
drivers/gpu/drm/i915/display/i9xx_wm.c
3951
vlv_punit_put(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
3954
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
3994
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
4003
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
4008
static void vlv_wm_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
4013
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
4015
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4017
intel_crtc_for_pipe(display, plane->pipe);
drivers/gpu/drm/i915/display/i9xx_wm.c
4028
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4036
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4042
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/i9xx_wm.c
4049
vlv_program_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
4051
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/i9xx_wm.c
4058
static void ilk_init_lp_watermarks(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
4060
intel_de_rmw(display, WM3_LP_ILK, WM_LP_ENABLE, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
4061
intel_de_rmw(display, WM2_LP_ILK, WM_LP_ENABLE, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
4062
intel_de_rmw(display, WM1_LP_ILK, WM_LP_ENABLE, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
4070
static void ilk_wm_get_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
4072
struct ilk_wm_values *hw = &display->wm.hw;
drivers/gpu/drm/i915/display/i9xx_wm.c
4075
ilk_init_lp_watermarks(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
4077
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/i9xx_wm.c
4080
hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4081
hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4082
hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4084
hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);
drivers/gpu/drm/i915/display/i9xx_wm.c
4085
if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4086
hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);
drivers/gpu/drm/i915/display/i9xx_wm.c
4087
hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);
drivers/gpu/drm/i915/display/i9xx_wm.c
4090
if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/i9xx_wm.c
4091
hw->partitioning = (intel_de_read(display, WM_MISC) &
drivers/gpu/drm/i915/display/i9xx_wm.c
4094
else if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/i9xx_wm.c
4095
hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &
drivers/gpu/drm/i915/display/i9xx_wm.c
4100
!(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
drivers/gpu/drm/i915/display/i9xx_wm.c
4150
void i9xx_wm_init(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
4153
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4154
ilk_setup_wm_latency(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
4155
display->wm.funcs = &ilk_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4156
} else if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4157
vlv_setup_wm_latency(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
4158
display->wm.funcs = &vlv_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4159
} else if (display->platform.g4x) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4160
g4x_setup_wm_latency(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
4161
display->wm.funcs = &g4x_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4162
} else if (display->platform.pineview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4163
if (!pnv_get_cxsr_latency(display)) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4164
drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
drivers/gpu/drm/i915/display/i9xx_wm.c
4166
intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
4167
display->wm.funcs = &nop_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4169
display->wm.funcs = &pnv_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4171
} else if (DISPLAY_VER(display) == 4) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4172
display->wm.funcs = &i965_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4173
} else if (DISPLAY_VER(display) == 3) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4174
display->wm.funcs = &i9xx_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4175
} else if (DISPLAY_VER(display) == 2) {
drivers/gpu/drm/i915/display/i9xx_wm.c
4176
if (INTEL_NUM_PIPES(display) == 1)
drivers/gpu/drm/i915/display/i9xx_wm.c
4177
display->wm.funcs = &i845_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4179
display->wm.funcs = &i9xx_wm_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
4181
drm_err(display->drm,
drivers/gpu/drm/i915/display/i9xx_wm.c
4183
display->wm.funcs = &nop_funcs;
drivers/gpu/drm/i915/display/i9xx_wm.c
568
static unsigned int intel_calculate_wm(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
586
drm_dbg_kms(display->drm, "FIFO entries required for mode: %d\n", entries);
drivers/gpu/drm/i915/display/i9xx_wm.c
589
drm_dbg_kms(display->drm, "FIFO watermark level: %d\n", wm_size);
drivers/gpu/drm/i915/display/i9xx_wm.c
639
static struct intel_crtc *single_enabled_crtc(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
643
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/i9xx_wm.c
654
static void pnv_update_wm(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
661
latency = pnv_get_cxsr_latency(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
663
drm_dbg_kms(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
drivers/gpu/drm/i915/display/i9xx_wm.c
664
intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
668
crtc = single_enabled_crtc(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
676
wm = intel_calculate_wm(display, pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
680
reg = intel_de_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
683
intel_de_write(display, DSPFW1(display), reg);
drivers/gpu/drm/i915/display/i9xx_wm.c
684
drm_dbg_kms(display->drm, "DSPFW1 register is %x\n", reg);
drivers/gpu/drm/i915/display/i9xx_wm.c
687
wm = intel_calculate_wm(display, pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
691
intel_de_rmw(display, DSPFW3(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
695
wm = intel_calculate_wm(display, pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
699
intel_de_rmw(display, DSPFW3(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
703
wm = intel_calculate_wm(display, pixel_rate,
drivers/gpu/drm/i915/display/i9xx_wm.c
707
reg = intel_de_read(display, DSPFW3(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
710
intel_de_write(display, DSPFW3(display), reg);
drivers/gpu/drm/i915/display/i9xx_wm.c
711
drm_dbg_kms(display->drm, "DSPFW3 register is %x\n", reg);
drivers/gpu/drm/i915/display/i9xx_wm.c
713
intel_set_memory_cxsr(display, true);
drivers/gpu/drm/i915/display/i9xx_wm.c
715
intel_set_memory_cxsr(display, false);
drivers/gpu/drm/i915/display/i9xx_wm.c
806
static void g4x_write_wm_values(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
811
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/i9xx_wm.c
812
trace_g4x_wm(intel_crtc_for_pipe(display, pipe), wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
814
intel_de_write(display, DSPFW1(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
819
intel_de_write(display, DSPFW2(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
826
intel_de_write(display, DSPFW3(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
832
intel_de_posting_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
838
static void vlv_write_wm_values(struct intel_display *display,
drivers/gpu/drm/i915/display/i9xx_wm.c
843
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/i9xx_wm.c
844
trace_vlv_wm(intel_crtc_for_pipe(display, pipe), wm);
drivers/gpu/drm/i915/display/i9xx_wm.c
846
intel_de_write(display, VLV_DDL(pipe),
drivers/gpu/drm/i915/display/i9xx_wm.c
858
intel_de_write(display, DSPHOWM, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
859
intel_de_write(display, DSPHOWM1, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
860
intel_de_write(display, DSPFW4, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
861
intel_de_write(display, DSPFW5, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
862
intel_de_write(display, DSPFW6, 0);
drivers/gpu/drm/i915/display/i9xx_wm.c
864
intel_de_write(display, DSPFW1(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
869
intel_de_write(display, DSPFW2(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
873
intel_de_write(display, DSPFW3(display),
drivers/gpu/drm/i915/display/i9xx_wm.c
876
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/i9xx_wm.c
877
intel_de_write(display, DSPFW7_CHV,
drivers/gpu/drm/i915/display/i9xx_wm.c
880
intel_de_write(display, DSPFW8_CHV,
drivers/gpu/drm/i915/display/i9xx_wm.c
883
intel_de_write(display, DSPFW9_CHV,
drivers/gpu/drm/i915/display/i9xx_wm.c
886
intel_de_write(display, DSPHOWM,
drivers/gpu/drm/i915/display/i9xx_wm.c
898
intel_de_write(display, DSPFW7,
drivers/gpu/drm/i915/display/i9xx_wm.c
901
intel_de_write(display, DSPHOWM,
drivers/gpu/drm/i915/display/i9xx_wm.c
91
static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
911
intel_de_posting_read(display, DSPFW1(display));
drivers/gpu/drm/i915/display/i9xx_wm.c
916
static void g4x_setup_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.c
919
display->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
drivers/gpu/drm/i915/display/i9xx_wm.c
920
display->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
drivers/gpu/drm/i915/display/i9xx_wm.c
921
display->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
drivers/gpu/drm/i915/display/i9xx_wm.c
923
display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1;
drivers/gpu/drm/i915/display/i9xx_wm.c
93
const struct dram_info *dram_info = intel_dram_info(display);
drivers/gpu/drm/i915/display/i9xx_wm.c
972
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/i9xx_wm.c
976
unsigned int latency = display->wm.pri_latency[level] * 10;
drivers/gpu/drm/i915/display/i9xx_wm.c
99
bool is_desktop = !display->platform.mobile;
drivers/gpu/drm/i915/display/i9xx_wm.h
16
bool ilk_disable_cxsr(struct intel_display *display);
drivers/gpu/drm/i915/display/i9xx_wm.h
17
void ilk_wm_sanitize(struct intel_display *display);
drivers/gpu/drm/i915/display/i9xx_wm.h
18
bool intel_set_memory_cxsr(struct intel_display *display, bool enable);
drivers/gpu/drm/i915/display/i9xx_wm.h
19
void i9xx_wm_init(struct intel_display *display);
drivers/gpu/drm/i915/display/i9xx_wm.h
21
static inline bool ilk_disable_cxsr(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.h
25
static inline void ilk_wm_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/i9xx_wm.h
28
static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/i9xx_wm.h
32
static inline void i9xx_wm_init(struct intel_display *display)
drivers/gpu/drm/i915/display/icl_dsi.c
1000
drm_err(display->drm, "vsync_start less than vactive\n");
drivers/gpu/drm/i915/display/icl_dsi.c
1006
intel_de_write(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1007
TRANS_VSYNC(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1021
intel_de_write(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1022
TRANS_VSYNCSHIFT(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1033
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/icl_dsi.c
1036
intel_de_write(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1037
TRANS_VBLANK(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1045
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1052
intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
drivers/gpu/drm/i915/display/icl_dsi.c
1056
if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1058
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
1066
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1090
intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1097
intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1104
intel_de_rmw(display, DSI_TA_TO(dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1113
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1125
tmp = intel_de_read(display, UTIL_PIN_CTL);
drivers/gpu/drm/i915/display/icl_dsi.c
1133
intel_de_write(display, UTIL_PIN_CTL, tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
115
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1171
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1187
tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1194
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
125
wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
drivers/gpu/drm/i915/display/icl_dsi.c
1254
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1256
if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
drivers/gpu/drm/i915/display/icl_dsi.c
1257
intel_de_rmw(display, CHICKEN_PAR1_1,
drivers/gpu/drm/i915/display/icl_dsi.c
126
wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
drivers/gpu/drm/i915/display/icl_dsi.c
1270
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1274
if (DISPLAY_VER(display) == 13) {
drivers/gpu/drm/i915/display/icl_dsi.c
1276
intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
drivers/gpu/drm/i915/display/icl_dsi.c
1312
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1321
intel_de_rmw(display, TRANSCONF(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1325
if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1327
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
1344
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1354
intel_de_rmw(display, DSI_CMD_FRMCTL(port),
drivers/gpu/drm/i915/display/icl_dsi.c
136
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
1361
tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1364
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
1366
ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1369
drm_err(display->drm, "DSI link not in ULPS\n");
drivers/gpu/drm/i915/display/icl_dsi.c
1375
intel_de_rmw(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1376
TRANS_DDI_FUNC_CTL(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1384
intel_de_rmw(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1385
TRANS_DDI_FUNC_CTL2(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
1393
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1400
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
drivers/gpu/drm/i915/display/icl_dsi.c
1402
ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),
drivers/gpu/drm/i915/display/icl_dsi.c
1406
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
1415
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1423
intel_display_power_put(display,
drivers/gpu/drm/i915/display/icl_dsi.c
143
wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
drivers/gpu/drm/i915/display/icl_dsi.c
1432
intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
drivers/gpu/drm/i915/display/icl_dsi.c
1494
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/icl_dsi.c
1497
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/icl_dsi.c
150
ret = intel_de_wait_for_clear_us(display,
drivers/gpu/drm/i915/display/icl_dsi.c
154
drm_err(display->drm, "LPTX bit not cleared\n");
drivers/gpu/drm/i915/display/icl_dsi.c
1546
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/icl_dsi.c
1555
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1598
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1609
if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
drivers/gpu/drm/i915/display/icl_dsi.c
1610
!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
drivers/gpu/drm/i915/display/icl_dsi.c
1611
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
162
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/icl_dsi.c
1620
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1622
int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
drivers/gpu/drm/i915/display/icl_dsi.c
1643
drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
drivers/gpu/drm/i915/display/icl_dsi.c
1644
drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
drivers/gpu/drm/i915/display/icl_dsi.c
1645
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
1647
drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
drivers/gpu/drm/i915/display/icl_dsi.c
1648
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
1664
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1698
drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
drivers/gpu/drm/i915/display/icl_dsi.c
170
drm_err(display->drm, "payload size exceeds max queue limit\n");
drivers/gpu/drm/i915/display/icl_dsi.c
1722
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
1730
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1737
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/icl_dsi.c
1738
TRANS_DDI_FUNC_CTL(display, dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1753
drm_err(display->drm, "Invalid PIPE input\n");
drivers/gpu/drm/i915/display/icl_dsi.c
1757
tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
1761
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/icl_dsi.c
177
if (!wait_for_payload_credits(display, dsi_trans, 1))
drivers/gpu/drm/i915/display/icl_dsi.c
183
intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
1924
void icl_dsi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/icl_dsi.c
194
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/icl_dsi.c
1954
drm_encoder_init(display->drm, &encoder->base,
drivers/gpu/drm/i915/display/icl_dsi.c
198
if (!wait_for_header_credits(display, dsi_trans, 1))
drivers/gpu/drm/i915/display/icl_dsi.c
1980
drm_connector_init(display->drm, connector,
drivers/gpu/drm/i915/display/icl_dsi.c
1992
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
drivers/gpu/drm/i915/display/icl_dsi.c
1994
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/icl_dsi.c
1996
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/icl_dsi.c
1999
drm_err(display->drm, "DSI fixed mode info missing\n");
drivers/gpu/drm/i915/display/icl_dsi.c
201
tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
2012
if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
drivers/gpu/drm/i915/display/icl_dsi.c
2015
if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
drivers/gpu/drm/i915/display/icl_dsi.c
2029
drm_dbg_kms(display->drm, "no device found\n");
drivers/gpu/drm/i915/display/icl_dsi.c
220
intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
227
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/icl_dsi.c
245
intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
drivers/gpu/drm/i915/display/icl_dsi.c
251
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
265
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
268
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
269
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
drivers/gpu/drm/i915/display/icl_dsi.c
275
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
278
intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
279
intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
drivers/gpu/drm/i915/display/icl_dsi.c
285
intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
drivers/gpu/drm/i915/display/icl_dsi.c
289
intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
drivers/gpu/drm/i915/display/icl_dsi.c
297
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
303
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/icl_dsi.c
313
dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
drivers/gpu/drm/i915/display/icl_dsi.c
328
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
333
intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
drivers/gpu/drm/i915/display/icl_dsi.c
340
intel_de_write(display, dss_ctl1_reg, dss_ctl1);
drivers/gpu/drm/i915/display/icl_dsi.c
361
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
370
if (display->platform.alderlake_s || display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/icl_dsi.c
380
intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
drivers/gpu/drm/i915/display/icl_dsi.c
382
intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
drivers/gpu/drm/i915/display/icl_dsi.c
386
intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
drivers/gpu/drm/i915/display/icl_dsi.c
388
intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
drivers/gpu/drm/i915/display/icl_dsi.c
391
if (display->platform.alderlake_s || display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/icl_dsi.c
393
intel_de_write(display, ADL_MIPIO_DW(port, 8),
drivers/gpu/drm/i915/display/icl_dsi.c
395
intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
drivers/gpu/drm/i915/display/icl_dsi.c
402
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/icl_dsi.c
406
drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
drivers/gpu/drm/i915/display/icl_dsi.c
408
intel_display_power_get(display,
drivers/gpu/drm/i915/display/icl_dsi.c
417
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
422
intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
drivers/gpu/drm/i915/display/icl_dsi.c
430
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
435
intel_combo_phy_power_up_lanes(display, phy, true,
drivers/gpu/drm/i915/display/icl_dsi.c
441
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
449
intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
drivers/gpu/drm/i915/display/icl_dsi.c
452
intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
drivers/gpu/drm/i915/display/icl_dsi.c
458
intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
drivers/gpu/drm/i915/display/icl_dsi.c
460
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
463
intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
466
if (display->platform.jasperlake || display->platform.elkhartlake ||
drivers/gpu/drm/i915/display/icl_dsi.c
467
(DISPLAY_VER(display) >= 12)) {
drivers/gpu/drm/i915/display/icl_dsi.c
468
intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
drivers/gpu/drm/i915/display/icl_dsi.c
471
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/icl_dsi.c
475
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
drivers/gpu/drm/i915/display/icl_dsi.c
484
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
491
tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
493
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
494
intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
drivers/gpu/drm/i915/display/icl_dsi.c
503
intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
drivers/gpu/drm/i915/display/icl_dsi.c
508
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
510
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
511
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
drivers/gpu/drm/i915/display/icl_dsi.c
519
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/icl_dsi.c
521
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
522
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
drivers/gpu/drm/i915/display/icl_dsi.c
528
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
534
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
drivers/gpu/drm/i915/display/icl_dsi.c
536
ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),
drivers/gpu/drm/i915/display/icl_dsi.c
539
drm_err(display->drm, "DDI port:%c buffer idle\n",
drivers/gpu/drm/i915/display/icl_dsi.c
548
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
555
intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
drivers/gpu/drm/i915/display/icl_dsi.c
560
intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
drivers/gpu/drm/i915/display/icl_dsi.c
569
if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/icl_dsi.c
572
intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
drivers/gpu/drm/i915/display/icl_dsi.c
578
if (display->platform.jasperlake || display->platform.elkhartlake) {
drivers/gpu/drm/i915/display/icl_dsi.c
580
intel_de_rmw(display, ICL_DPHY_CHKN(phy),
drivers/gpu/drm/i915/display/icl_dsi.c
589
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
59
static int header_credits_available(struct intel_display *display,
drivers/gpu/drm/i915/display/icl_dsi.c
595
intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
drivers/gpu/drm/i915/display/icl_dsi.c
600
intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
drivers/gpu/drm/i915/display/icl_dsi.c
605
intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
drivers/gpu/drm/i915/display/icl_dsi.c
609
if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/icl_dsi.c
612
intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
drivers/gpu/drm/i915/display/icl_dsi.c
62
return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
drivers/gpu/drm/i915/display/icl_dsi.c
622
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
627
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/icl_dsi.c
628
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
632
intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
633
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/icl_dsi.c
638
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
643
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/icl_dsi.c
644
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
648
intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
649
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/icl_dsi.c
654
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
66
static int payload_credits_available(struct intel_display *display,
drivers/gpu/drm/i915/display/icl_dsi.c
660
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
673
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
679
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/icl_dsi.c
681
val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
686
intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
drivers/gpu/drm/i915/display/icl_dsi.c
69
return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
drivers/gpu/drm/i915/display/icl_dsi.c
691
intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
drivers/gpu/drm/i915/display/icl_dsi.c
693
intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/icl_dsi.c
695
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/icl_dsi.c
702
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
712
tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
73
static bool wait_for_header_credits(struct intel_display *display,
drivers/gpu/drm/i915/display/icl_dsi.c
732
if (DISPLAY_VER(display) >= 12 &&
drivers/gpu/drm/i915/display/icl_dsi.c
774
if (DISPLAY_VER(display) >= 12 &&
drivers/gpu/drm/i915/display/icl_dsi.c
78
ret = poll_timeout_us(available = header_credits_available(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
808
intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
815
intel_de_rmw(display,
drivers/gpu/drm/i915/display/icl_dsi.c
816
TRANS_DDI_FUNC_CTL2(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
82
drm_err(display->drm, "DSI header credits not released\n");
drivers/gpu/drm/i915/display/icl_dsi.c
828
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/icl_dsi.c
829
TRANS_DDI_FUNC_CTL(display, dsi_trans));
drivers/gpu/drm/i915/display/icl_dsi.c
855
intel_de_write(display,
drivers/gpu/drm/i915/display/icl_dsi.c
856
TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
drivers/gpu/drm/i915/display/icl_dsi.c
865
ret = intel_de_wait_for_set_us(display,
drivers/gpu/drm/i915/display/icl_dsi.c
869
drm_err(display->drm, "DSI link not ready\n");
drivers/gpu/drm/i915/display/icl_dsi.c
877
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/icl_dsi.c
89
static bool wait_for_payload_credits(struct intel_display *display,
drivers/gpu/drm/i915/display/icl_dsi.c
94
ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
944
drm_err(display->drm, "hactive is less then 256 pixels\n");
drivers/gpu/drm/i915/display/icl_dsi.c
948
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
954
intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
963
drm_err(display->drm,
drivers/gpu/drm/i915/display/icl_dsi.c
968
drm_err(display->drm, "hback porch < 16 pixels\n");
drivers/gpu/drm/i915/display/icl_dsi.c
977
intel_de_write(display,
drivers/gpu/drm/i915/display/icl_dsi.c
978
TRANS_HSYNC(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
98
drm_err(display->drm, "DSI payload credits not released\n");
drivers/gpu/drm/i915/display/icl_dsi.c
992
intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
drivers/gpu/drm/i915/display/icl_dsi.c
997
drm_err(display->drm, "Invalid vsync_end value\n");
drivers/gpu/drm/i915/display/icl_dsi.h
13
void icl_dsi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_acpi.c
190
void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_acpi.c
192
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_acpi.c
270
void intel_acpi_device_id_update(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_acpi.c
277
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_acpi.c
294
void intel_acpi_assign_connector_fwnodes(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_acpi.c
296
struct drm_device *drm_dev = display->drm;
drivers/gpu/drm/i915/display/intel_acpi.c
339
void intel_acpi_video_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_acpi.c
353
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_acpi.h
14
void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_acpi.h
15
void intel_acpi_device_id_update(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_acpi.h
16
void intel_acpi_assign_connector_fwnodes(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_acpi.h
17
void intel_acpi_video_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_acpi.h
22
void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; }
drivers/gpu/drm/i915/display/intel_acpi.h
24
void intel_acpi_device_id_update(struct intel_display *display) { return; }
drivers/gpu/drm/i915/display/intel_acpi.h
26
void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; }
drivers/gpu/drm/i915/display/intel_acpi.h
28
void intel_acpi_video_register(struct intel_display *display) { return; }
drivers/gpu/drm/i915/display/intel_alpm.c
123
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
140
if (display->params.psr_safest_params)
drivers/gpu/drm/i915/display/intel_alpm.c
153
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
156
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/intel_alpm.c
169
if (display->params.psr_safest_params)
drivers/gpu/drm/i915/display/intel_alpm.c
194
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_alpm.c
196
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_alpm.c
205
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
218
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_alpm.c
220
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_alpm.c
237
if (display->params.psr_safest_params)
drivers/gpu/drm/i915/display/intel_alpm.c
327
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
330
drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
drivers/gpu/drm/i915/display/intel_alpm.c
340
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/intel_alpm.c
349
if (!intel_vrr_always_use_vrr_tg(display) ||
drivers/gpu/drm/i915/display/intel_alpm.c
383
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
387
if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
drivers/gpu/drm/i915/display/intel_alpm.c
410
intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_alpm.c
421
drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n");
drivers/gpu/drm/i915/display/intel_alpm.c
426
intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
drivers/gpu/drm/i915/display/intel_alpm.c
440
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
444
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/intel_alpm.c
462
intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);
drivers/gpu/drm/i915/display/intel_alpm.c
464
intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);
drivers/gpu/drm/i915/display/intel_alpm.c
469
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_alpm.c
473
for_each_intel_encoder_mask(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_alpm.c
486
intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_alpm.c
487
drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");
drivers/gpu/drm/i915/display/intel_alpm.c
511
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_alpm.c
514
for_each_intel_encoder_mask(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_alpm.c
533
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_alpm.c
540
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_alpm.c
552
alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_alpm.c
559
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_alpm.c
594
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_alpm.c
597
if (DISPLAY_VER(display) < 20 ||
drivers/gpu/drm/i915/display/intel_alpm.c
610
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
613
if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)
drivers/gpu/drm/i915/display/intel_alpm.c
618
intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_alpm.c
621
drm_dbg_kms(display->drm, "Disabling ALPM\n");
drivers/gpu/drm/i915/display/intel_alpm.c
627
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_alpm.c
634
drm_err(display->drm, "Error reading ALPM status\n");
drivers/gpu/drm/i915/display/intel_alpm.c
639
drm_dbg_kms(display->drm, "ALPM lock timeout error\n");
drivers/gpu/drm/i915/display/intel_atomic.c
104
if (property == display->properties.broadcast_rgb) {
drivers/gpu/drm/i915/display/intel_atomic.c
109
drm_dbg_atomic(display->drm, "Unknown property [PROP:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_atomic.c
63
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_atomic.c
67
if (property == display->properties.force_audio)
drivers/gpu/drm/i915/display/intel_atomic.c
69
else if (property == display->properties.broadcast_rgb)
drivers/gpu/drm/i915/display/intel_atomic.c
72
drm_dbg_atomic(display->drm,
drivers/gpu/drm/i915/display/intel_atomic.c
95
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_atomic.c
99
if (property == display->properties.force_audio) {
drivers/gpu/drm/i915/display/intel_audio.c
1006
if (DISPLAY_VER(display) == 10) {
drivers/gpu/drm/i915/display/intel_audio.c
1009
} else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_audio.c
1019
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_audio.c
1029
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_audio.c
1038
struct intel_display *display = to_intel_display(kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1044
wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK);
drivers/gpu/drm/i915/display/intel_audio.c
1046
if (display->audio.power_refcount++ == 0) {
drivers/gpu/drm/i915/display/intel_audio.c
1047
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_audio.c
1048
intel_de_write(display, AUD_FREQ_CNTRL,
drivers/gpu/drm/i915/display/intel_audio.c
1049
display->audio.freq_cntrl);
drivers/gpu/drm/i915/display/intel_audio.c
1050
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
1052
display->audio.freq_cntrl);
drivers/gpu/drm/i915/display/intel_audio.c
1056
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_audio.c
1057
glk_force_audio_cdclk(display, true);
drivers/gpu/drm/i915/display/intel_audio.c
1059
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_audio.c
1060
intel_de_rmw(display, AUD_PIN_BUF_CTL,
drivers/gpu/drm/i915/display/intel_audio.c
1070
struct intel_display *display = to_intel_display(kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1074
if (--display->audio.power_refcount == 0)
drivers/gpu/drm/i915/display/intel_audio.c
1075
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_audio.c
1076
glk_force_audio_cdclk(display, false);
drivers/gpu/drm/i915/display/intel_audio.c
1078
intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref);
drivers/gpu/drm/i915/display/intel_audio.c
1084
struct intel_display *display = to_intel_display(kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1087
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_audio.c
1096
intel_de_rmw(display, HSW_AUD_CHICKENBIT,
drivers/gpu/drm/i915/display/intel_audio.c
1101
intel_de_rmw(display, HSW_AUD_CHICKENBIT,
drivers/gpu/drm/i915/display/intel_audio.c
1112
struct intel_display *display = to_intel_display(kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1114
if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display)))
drivers/gpu/drm/i915/display/intel_audio.c
1117
return display->cdclk.hw.cdclk;
drivers/gpu/drm/i915/display/intel_audio.c
1129
static struct intel_audio_state *find_audio_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_audio.c
1137
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
1138
cpu_transcoder >= ARRAY_SIZE(display->audio.state)))
drivers/gpu/drm/i915/display/intel_audio.c
1141
audio_state = &display->audio.state[cpu_transcoder];
drivers/gpu/drm/i915/display/intel_audio.c
1153
for_each_cpu_transcoder(display, cpu_transcoder) {
drivers/gpu/drm/i915/display/intel_audio.c
1157
audio_state = &display->audio.state[cpu_transcoder];
drivers/gpu/drm/i915/display/intel_audio.c
1171
struct intel_display *display = to_intel_display(kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1172
struct i915_audio_component *acomp = display->audio.component;
drivers/gpu/drm/i915/display/intel_audio.c
1179
if (!HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_audio.c
1183
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
1185
audio_state = find_audio_state(display, port, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_audio.c
1187
drm_dbg_kms(display->drm, "Not valid for port %c\n",
drivers/gpu/drm/i915/display/intel_audio.c
1205
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
1214
struct intel_display *display = to_intel_display(kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1218
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
1220
audio_state = find_audio_state(display, port, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_audio.c
1222
drm_dbg_kms(display->drm, "Not valid for port %c\n",
drivers/gpu/drm/i915/display/intel_audio.c
1224
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
1236
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
1253
struct intel_display *display = to_intel_display(drv_kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1257
if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev))
drivers/gpu/drm/i915/display/intel_audio.c
1260
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
1265
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_audio.c
1271
display->audio.component = acomp;
drivers/gpu/drm/i915/display/intel_audio.c
1272
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_audio.c
1280
struct intel_display *display = to_intel_display(drv_kdev);
drivers/gpu/drm/i915/display/intel_audio.c
1283
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_audio.c
1286
display->audio.component = NULL;
drivers/gpu/drm/i915/display/intel_audio.c
1287
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_audio.c
1291
if (display->audio.power_refcount)
drivers/gpu/drm/i915/display/intel_audio.c
1292
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
1294
display->audio.power_refcount);
drivers/gpu/drm/i915/display/intel_audio.c
1327
static void intel_audio_component_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
1331
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_audio.c
1332
aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);
drivers/gpu/drm/i915/display/intel_audio.c
1334
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_audio.c
1340
if ((display->platform.tigerlake || display->platform.rocketlake) &&
drivers/gpu/drm/i915/display/intel_audio.c
1344
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
1348
display->audio.freq_cntrl = aud_freq;
drivers/gpu/drm/i915/display/intel_audio.c
1352
intel_audio_cdclk_change_post(display);
drivers/gpu/drm/i915/display/intel_audio.c
1355
static void intel_audio_component_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
1359
ret = component_add_typed(display->drm->dev,
drivers/gpu/drm/i915/display/intel_audio.c
1363
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
1369
display->audio.component_registered = true;
drivers/gpu/drm/i915/display/intel_audio.c
1379
static void intel_audio_component_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
1381
if (!display->audio.component_registered)
drivers/gpu/drm/i915/display/intel_audio.c
1384
component_del(display->drm->dev, &intel_audio_component_bind_ops);
drivers/gpu/drm/i915/display/intel_audio.c
1385
display->audio.component_registered = false;
drivers/gpu/drm/i915/display/intel_audio.c
1394
void intel_audio_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
1396
if (intel_lpe_audio_init(display) < 0)
drivers/gpu/drm/i915/display/intel_audio.c
1397
intel_audio_component_init(display);
drivers/gpu/drm/i915/display/intel_audio.c
1400
void intel_audio_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
1402
if (!display->audio.lpe.platdev)
drivers/gpu/drm/i915/display/intel_audio.c
1403
intel_audio_component_register(display);
drivers/gpu/drm/i915/display/intel_audio.c
1410
void intel_audio_deinit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
1412
if (display->audio.lpe.platdev)
drivers/gpu/drm/i915/display/intel_audio.c
1413
intel_lpe_audio_teardown(display);
drivers/gpu/drm/i915/display/intel_audio.c
1415
intel_audio_component_cleanup(display);
drivers/gpu/drm/i915/display/intel_audio.c
191
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_audio.c
201
if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500)
drivers/gpu/drm/i915/display/intel_audio.c
205
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
211
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
246
static int g4x_eld_buffer_size(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
250
tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
drivers/gpu/drm/i915/display/intel_audio.c
258
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
263
tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
drivers/gpu/drm/i915/display/intel_audio.c
267
intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);
drivers/gpu/drm/i915/display/intel_audio.c
269
eld_buffer_size = g4x_eld_buffer_size(display);
drivers/gpu/drm/i915/display/intel_audio.c
273
eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);
drivers/gpu/drm/i915/display/intel_audio.c
280
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
284
intel_de_rmw(display, G4X_AUD_CNTL_ST,
drivers/gpu/drm/i915/display/intel_audio.c
295
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
302
intel_de_rmw(display, G4X_AUD_CNTL_ST,
drivers/gpu/drm/i915/display/intel_audio.c
305
eld_buffer_size = g4x_eld_buffer_size(display);
drivers/gpu/drm/i915/display/intel_audio.c
309
intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]);
drivers/gpu/drm/i915/display/intel_audio.c
311
intel_de_write(display, G4X_HDMIW_HDMIEDID, 0);
drivers/gpu/drm/i915/display/intel_audio.c
313
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
314
(intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);
drivers/gpu/drm/i915/display/intel_audio.c
316
intel_de_rmw(display, G4X_AUD_CNTL_ST,
drivers/gpu/drm/i915/display/intel_audio.c
324
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
328
intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_audio.c
342
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
343
struct i915_audio_component *acomp = display->audio.component;
drivers/gpu/drm/i915/display/intel_audio.c
351
tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_audio.c
359
drm_dbg_kms(display->drm, "using N %d\n", n);
drivers/gpu/drm/i915/display/intel_audio.c
365
drm_dbg_kms(display->drm, "using automatic N\n");
drivers/gpu/drm/i915/display/intel_audio.c
368
intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp);
drivers/gpu/drm/i915/display/intel_audio.c
374
tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_audio.c
377
intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
drivers/gpu/drm/i915/display/intel_audio.c
393
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_audio.c
396
if (!HAS_DP20(display))
drivers/gpu/drm/i915/display/intel_audio.c
399
intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,
drivers/gpu/drm/i915/display/intel_audio.c
407
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
411
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
414
intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_audio.c
423
intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
drivers/gpu/drm/i915/display/intel_audio.c
430
intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
drivers/gpu/drm/i915/display/intel_audio.c
437
if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754))
drivers/gpu/drm/i915/display/intel_audio.c
438
intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0);
drivers/gpu/drm/i915/display/intel_audio.c
442
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
448
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
460
cdclk = display->cdclk.hw.cdclk;
drivers/gpu/drm/i915/display/intel_audio.c
466
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
511
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
516
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_audio.c
519
val = intel_de_read(display, AUD_CONFIG_BE);
drivers/gpu/drm/i915/display/intel_audio.c
521
if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_audio.c
523
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_audio.c
550
intel_de_write(display, AUD_CONFIG_BE, val);
drivers/gpu/drm/i915/display/intel_audio.c
557
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
561
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
573
if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754))
drivers/gpu/drm/i915/display/intel_audio.c
574
intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX);
drivers/gpu/drm/i915/display/intel_audio.c
577
intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
drivers/gpu/drm/i915/display/intel_audio.c
583
intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
drivers/gpu/drm/i915/display/intel_audio.c
594
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
601
static void ibx_audio_regs_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_audio.c
605
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_audio.c
610
} else if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_audio.c
615
} else if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_audio.c
627
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
633
if (drm_WARN_ON(display->drm, port == PORT_A))
drivers/gpu/drm/i915/display/intel_audio.c
636
ibx_audio_regs_init(display, pipe, ®s);
drivers/gpu/drm/i915/display/intel_audio.c
638
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
641
intel_de_rmw(display, regs.aud_config,
drivers/gpu/drm/i915/display/intel_audio.c
650
intel_de_rmw(display, regs.aud_cntrl_st2,
drivers/gpu/drm/i915/display/intel_audio.c
653
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
663
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
669
if (drm_WARN_ON(display->drm, port == PORT_A))
drivers/gpu/drm/i915/display/intel_audio.c
674
ibx_audio_regs_init(display, pipe, ®s);
drivers/gpu/drm/i915/display/intel_audio.c
676
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
679
intel_de_rmw(display, regs.aud_cntrl_st2,
drivers/gpu/drm/i915/display/intel_audio.c
688
intel_de_rmw(display, regs.aud_config,
drivers/gpu/drm/i915/display/intel_audio.c
696
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
703
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
710
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
739
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
740
struct i915_audio_component *acomp = display->audio.component;
drivers/gpu/drm/i915/display/intel_audio.c
750
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
757
if (display->audio.funcs)
drivers/gpu/drm/i915/display/intel_audio.c
758
display->audio.funcs->audio_codec_enable(encoder, crtc_state, conn_state);
drivers/gpu/drm/i915/display/intel_audio.c
760
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
762
audio_state = &display->audio.state[cpu_transcoder];
drivers/gpu/drm/i915/display/intel_audio.c
768
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
779
intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,
drivers/gpu/drm/i915/display/intel_audio.c
797
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
798
struct i915_audio_component *acomp = display->audio.component;
drivers/gpu/drm/i915/display/intel_audio.c
808
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_audio.c
814
if (display->audio.funcs)
drivers/gpu/drm/i915/display/intel_audio.c
815
display->audio.funcs->audio_codec_disable(encoder, old_crtc_state, old_conn_state);
drivers/gpu/drm/i915/display/intel_audio.c
817
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
819
audio_state = &display->audio.state[cpu_transcoder];
drivers/gpu/drm/i915/display/intel_audio.c
824
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
835
intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false);
drivers/gpu/drm/i915/display/intel_audio.c
841
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
845
mutex_lock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
847
audio_state = &display->audio.state[cpu_transcoder];
drivers/gpu/drm/i915/display/intel_audio.c
852
mutex_unlock(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_audio.c
858
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_audio.c
863
if (display->audio.funcs)
drivers/gpu/drm/i915/display/intel_audio.c
864
display->audio.funcs->audio_codec_get_config(encoder, crtc_state);
drivers/gpu/drm/i915/display/intel_audio.c
889
void intel_audio_hooks_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
891
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_audio.c
892
display->audio.funcs = &g4x_audio_funcs;
drivers/gpu/drm/i915/display/intel_audio.c
893
else if (display->platform.valleyview || display->platform.cherryview ||
drivers/gpu/drm/i915/display/intel_audio.c
894
HAS_PCH_CPT(display) || HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/intel_audio.c
895
display->audio.funcs = &ibx_audio_funcs;
drivers/gpu/drm/i915/display/intel_audio.c
896
else if (display->platform.haswell || DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_audio.c
897
display->audio.funcs = &hsw_audio_funcs;
drivers/gpu/drm/i915/display/intel_audio.c
905
void intel_audio_cdclk_change_pre(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
907
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_audio.c
908
intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);
drivers/gpu/drm/i915/display/intel_audio.c
917
void intel_audio_cdclk_change_post(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_audio.c
921
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_audio.c
922
get_aud_ts_cdclk_m_n(display->cdclk.hw.ref,
drivers/gpu/drm/i915/display/intel_audio.c
923
display->cdclk.hw.cdclk, &aud_ts);
drivers/gpu/drm/i915/display/intel_audio.c
925
intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n);
drivers/gpu/drm/i915/display/intel_audio.c
926
intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
drivers/gpu/drm/i915/display/intel_audio.c
927
drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n",
drivers/gpu/drm/i915/display/intel_audio.c
953
static void glk_force_audio_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_audio.c
961
crtc = intel_first_crtc(display);
drivers/gpu/drm/i915/display/intel_audio.c
966
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_audio.c
967
if (drm_WARN_ON(display->drm, !state))
drivers/gpu/drm/i915/display/intel_audio.c
982
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/intel_audio.c
992
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_audio.h
16
void intel_audio_hooks_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_audio.h
28
void intel_audio_cdclk_change_pre(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_audio.h
29
void intel_audio_cdclk_change_post(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_audio.h
31
void intel_audio_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_audio.h
32
void intel_audio_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_audio.h
33
void intel_audio_deinit(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_backlight.c
100
intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)) {
drivers/gpu/drm/i915/display/intel_backlight.c
1003
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1030
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1032
return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq),
drivers/gpu/drm/i915/display/intel_backlight.c
1069
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1078
if (HAS_PCH_LPT_H(display))
drivers/gpu/drm/i915/display/intel_backlight.c
1092
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1094
return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq),
drivers/gpu/drm/i915/display/intel_backlight.c
110
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1108
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1111
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_backlight.c
1112
clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);
drivers/gpu/drm/i915/display/intel_backlight.c
1114
clock = KHz(display->cdclk.hw.cdclk);
drivers/gpu/drm/i915/display/intel_backlight.c
1126
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1129
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_backlight.c
113
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n",
drivers/gpu/drm/i915/display/intel_backlight.c
1130
clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);
drivers/gpu/drm/i915/display/intel_backlight.c
1132
clock = KHz(display->cdclk.hw.cdclk);
drivers/gpu/drm/i915/display/intel_backlight.c
1144
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1147
if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {
drivers/gpu/drm/i915/display/intel_backlight.c
1148
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_backlight.c
1154
clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);
drivers/gpu/drm/i915/display/intel_backlight.c
1163
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1167
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1172
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1182
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1188
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1195
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
120
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1208
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1212
drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);
drivers/gpu/drm/i915/display/intel_backlight.c
1223
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
123
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1234
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1239
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_backlight.c
1240
alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
drivers/gpu/drm/i915/display/intel_backlight.c
1242
alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
drivers/gpu/drm/i915/display/intel_backlight.c
1245
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
1248
pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1251
cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1263
cpu_mode = panel->backlight.pwm_enabled && HAS_PCH_LPT(display) &&
drivers/gpu/drm/i915/display/intel_backlight.c
1270
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1275
intel_de_write(display, BLC_PWM_PCH_CTL1,
drivers/gpu/drm/i915/display/intel_backlight.c
1278
intel_de_write(display, BLC_PWM_CPU_CTL2,
drivers/gpu/drm/i915/display/intel_backlight.c
1282
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1291
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1295
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
1298
pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1309
cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
1313
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1322
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1326
ctl = intel_de_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
1328
if (DISPLAY_VER(display) == 2 || display->platform.i915gm || display->platform.i945gm)
drivers/gpu/drm/i915/display/intel_backlight.c
1331
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_backlight.c
134
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1355
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1364
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1368
ctl2 = intel_de_read(display, BLC_PWM_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
137
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1372
ctl = intel_de_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
1388
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1397
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
140
if (display->params.invert_brightness > 0 ||
drivers/gpu/drm/i915/display/intel_backlight.c
1401
if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
drivers/gpu/drm/i915/display/intel_backlight.c
1404
ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
1407
ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
141
(display->params.invert_brightness == 0 &&
drivers/gpu/drm/i915/display/intel_backlight.c
142
intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)))
drivers/gpu/drm/i915/display/intel_backlight.c
1420
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1430
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1436
pwm_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_backlight.c
1441
val = intel_de_read(display, UTIL_PIN_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
1448
intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
1460
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1468
static int cnp_num_backlight_controllers(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_backlight.c
1470
if (INTEL_PCH_TYPE(display) >= PCH_MTL)
drivers/gpu/drm/i915/display/intel_backlight.c
1473
if (INTEL_PCH_TYPE(display) >= PCH_DG1)
drivers/gpu/drm/i915/display/intel_backlight.c
1476
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_backlight.c
1482
static bool cnp_backlight_controller_is_valid(struct intel_display *display, int controller)
drivers/gpu/drm/i915/display/intel_backlight.c
1484
if (controller < 0 || controller >= cnp_num_backlight_controllers(display))
drivers/gpu/drm/i915/display/intel_backlight.c
1488
INTEL_PCH_TYPE(display) >= PCH_ICP &&
drivers/gpu/drm/i915/display/intel_backlight.c
1489
INTEL_PCH_TYPE(display) <= PCH_ADP)
drivers/gpu/drm/i915/display/intel_backlight.c
1490
return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
drivers/gpu/drm/i915/display/intel_backlight.c
1498
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1507
if (!cnp_backlight_controller_is_valid(display, panel->backlight.controller)) {
drivers/gpu/drm/i915/display/intel_backlight.c
1508
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
151
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1515
pwm_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_backlight.c
1520
intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
153
return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
1532
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1543
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1550
panel->backlight.pwm = pwm_get(display->drm->dev,
drivers/gpu/drm/i915/display/intel_backlight.c
1554
panel->backlight.pwm = pwm_get(display->drm->dev,
drivers/gpu/drm/i915/display/intel_backlight.c
1560
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1579
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
158
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1590
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
160
return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
165
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1656
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1662
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
1666
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
1671
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1676
if (intel_has_quirk(display, QUIRK_BACKLIGHT_PRESENT)) {
drivers/gpu/drm/i915/display/intel_backlight.c
1677
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1681
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
1689
if (drm_WARN_ON(display->drm, !panel->backlight.funcs))
drivers/gpu/drm/i915/display/intel_backlight.c
169
val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
1693
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
1695
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
1698
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
170
if (DISPLAY_VER(display) < 4)
drivers/gpu/drm/i915/display/intel_backlight.c
1706
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
174
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_backlight.c
1817
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
1823
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_backlight.c
1825
} else if (INTEL_PCH_TYPE(display) >= PCH_CNP) {
drivers/gpu/drm/i915/display/intel_backlight.c
1827
} else if (INTEL_PCH_TYPE(display) >= PCH_LPT_H) {
drivers/gpu/drm/i915/display/intel_backlight.c
1828
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_backlight.c
1832
} else if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_backlight.c
1834
} else if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_backlight.c
1840
} else if (DISPLAY_VER(display) == 4) {
drivers/gpu/drm/i915/display/intel_backlight.c
1850
if (!intel_has_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
drivers/gpu/drm/i915/display/intel_backlight.c
186
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
188
if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
drivers/gpu/drm/i915/display/intel_backlight.c
191
return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
196
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
199
return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
214
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
217
val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
218
intel_de_write(display, BLC_PWM_PCH_CTL2, val | level);
drivers/gpu/drm/i915/display/intel_backlight.c
224
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
227
tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
228
intel_de_write(display, BLC_PWM_CPU_CTL, tmp | level);
drivers/gpu/drm/i915/display/intel_backlight.c
234
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
238
if (drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0))
drivers/gpu/drm/i915/display/intel_backlight.c
242
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_backlight.c
250
if (DISPLAY_VER(display) == 4) {
drivers/gpu/drm/i915/display/intel_backlight.c
257
tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;
drivers/gpu/drm/i915/display/intel_backlight.c
258
intel_de_write(display, BLC_PWM_CTL, tmp | level);
drivers/gpu/drm/i915/display/intel_backlight.c
264
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
268
tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
drivers/gpu/drm/i915/display/intel_backlight.c
269
intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level);
drivers/gpu/drm/i915/display/intel_backlight.c
275
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
278
intel_de_write(display, BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
drivers/gpu/drm/i915/display/intel_backlight.c
293
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
296
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight level = %d\n",
drivers/gpu/drm/i915/display/intel_backlight.c
309
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
322
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
324
drm_WARN_ON(display->drm, panel->backlight.max == 0);
drivers/gpu/drm/i915/display/intel_backlight.c
338
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
344
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
357
tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
359
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] CPU backlight was enabled, disabling\n",
drivers/gpu/drm/i915/display/intel_backlight.c
361
intel_de_write(display, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
364
intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
370
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
374
intel_de_rmw(display, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
376
intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
387
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
391
intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
397
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
402
intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
408
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
413
intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
417
intel_de_rmw(display, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
423
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
428
intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
446
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
458
if (display->drm->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
drivers/gpu/drm/i915/display/intel_backlight.c
459
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Skipping backlight disable on vga switch\n",
drivers/gpu/drm/i915/display/intel_backlight.c
464
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
471
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
478
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
482
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
484
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
488
intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);
drivers/gpu/drm/i915/display/intel_backlight.c
491
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_backlight.c
492
intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY,
drivers/gpu/drm/i915/display/intel_backlight.c
496
intel_de_rmw(display, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY,
drivers/gpu/drm/i915/display/intel_backlight.c
501
intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
508
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_backlight.c
511
intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);
drivers/gpu/drm/i915/display/intel_backlight.c
512
intel_de_posting_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
513
intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
523
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
528
cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
530
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
534
intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
537
pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
539
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
543
intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);
drivers/gpu/drm/i915/display/intel_backlight.c
550
intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
551
intel_de_posting_read(display, BLC_PWM_CPU_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
552
intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
558
intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
564
intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1);
drivers/gpu/drm/i915/display/intel_backlight.c
565
intel_de_posting_read(display, BLC_PWM_PCH_CTL1);
drivers/gpu/drm/i915/display/intel_backlight.c
566
intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
573
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
577
ctl = intel_de_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
579
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
582
intel_de_write(display, BLC_PWM_CTL, 0);
drivers/gpu/drm/i915/display/intel_backlight.c
592
if (display->platform.pineview && panel->backlight.active_low_pwm)
drivers/gpu/drm/i915/display/intel_backlight.c
595
intel_de_write(display, BLC_PWM_CTL, ctl);
drivers/gpu/drm/i915/display/intel_backlight.c
596
intel_de_posting_read(display, BLC_PWM_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
606
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_backlight.c
607
intel_de_write(display, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
614
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
619
ctl2 = intel_de_read(display, BLC_PWM_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
621
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
625
intel_de_write(display, BLC_PWM_CTL2, ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
633
intel_de_write(display, BLC_PWM_CTL, ctl);
drivers/gpu/drm/i915/display/intel_backlight.c
640
intel_de_write(display, BLC_PWM_CTL2, ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
641
intel_de_posting_read(display, BLC_PWM_CTL2);
drivers/gpu/drm/i915/display/intel_backlight.c
642
intel_de_write(display, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
651
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
656
ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
658
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
662
intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
666
intel_de_write(display, VLV_BLC_PWM_CTL(pipe), ctl);
drivers/gpu/drm/i915/display/intel_backlight.c
674
intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);
drivers/gpu/drm/i915/display/intel_backlight.c
675
intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
676
intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);
drivers/gpu/drm/i915/display/intel_backlight.c
683
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
690
val = intel_de_read(display, UTIL_PIN_CTL);
drivers/gpu/drm/i915/display/intel_backlight.c
692
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
696
intel_de_write(display, UTIL_PIN_CTL, val);
drivers/gpu/drm/i915/display/intel_backlight.c
702
intel_de_write(display, UTIL_PIN_CTL,
drivers/gpu/drm/i915/display/intel_backlight.c
706
pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
708
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
712
intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
716
intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
725
intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
drivers/gpu/drm/i915/display/intel_backlight.c
726
intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
727
intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
735
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
739
pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
741
drm_dbg_kms(display->drm, "backlight already enabled\n");
drivers/gpu/drm/i915/display/intel_backlight.c
743
intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
747
intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
756
intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
drivers/gpu/drm/i915/display/intel_backlight.c
757
intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
drivers/gpu/drm/i915/display/intel_backlight.c
758
intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller),
drivers/gpu/drm/i915/display/intel_backlight.c
800
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
807
drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(pipe));
drivers/gpu/drm/i915/display/intel_backlight.c
809
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
813
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
819
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
823
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
828
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
830
drm_dbg_kms(display->drm, "get backlight PWM = %d\n", val);
drivers/gpu/drm/i915/display/intel_backlight.c
849
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
856
mutex_lock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
858
drm_WARN_ON(display->drm, panel->backlight.max == 0);
drivers/gpu/drm/i915/display/intel_backlight.c
866
mutex_unlock(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_backlight.c
872
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
875
drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);
drivers/gpu/drm/i915/display/intel_backlight.c
877
drm_dbg_kms(display->drm, "updating intel_backlight, brightness=%d/%d\n",
drivers/gpu/drm/i915/display/intel_backlight.c
898
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_backlight.c
906
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
909
with_intel_display_rpm(display) {
drivers/gpu/drm/i915/display/intel_backlight.c
91
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
912
drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);
drivers/gpu/drm/i915/display/intel_backlight.c
918
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_backlight.c
931
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_backlight.c
94
drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);
drivers/gpu/drm/i915/display/intel_backlight.c
947
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_backlight.c
96
if (display->params.invert_brightness < 0)
drivers/gpu/drm/i915/display/intel_backlight.c
985
display->drm->primary->index,
drivers/gpu/drm/i915/display/intel_backlight.c
99
if (display->params.invert_brightness > 0 ||
drivers/gpu/drm/i915/display/intel_backlight.c
994
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1028
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1036
parse_lfp_backlight(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1044
backlight_data = bdb_find_section(display, BDB_LFP_BACKLIGHT);
drivers/gpu/drm/i915/display/intel_bios.c
1049
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1059
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1067
if (display->vbt.version >= 191) {
drivers/gpu/drm/i915/display/intel_bios.c
1078
if (display->vbt.version >= 234) {
drivers/gpu/drm/i915/display/intel_bios.c
1085
if (display->vbt.version >= 236)
drivers/gpu/drm/i915/display/intel_bios.c
1094
drm_warn(display->drm, "Brightness min level > 255\n");
drivers/gpu/drm/i915/display/intel_bios.c
1106
if (display->vbt.version >= 239)
drivers/gpu/drm/i915/display/intel_bios.c
1112
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1123
parse_sdvo_lvds_data(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1130
index = display->params.vbt_sdvo_panel_type;
drivers/gpu/drm/i915/display/intel_bios.c
1132
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1140
sdvo_lvds_options = bdb_find_section(display, BDB_SDVO_LVDS_OPTIONS);
drivers/gpu/drm/i915/display/intel_bios.c
1147
dtd = bdb_find_section(display, BDB_SDVO_LVDS_DTD);
drivers/gpu/drm/i915/display/intel_bios.c
1158
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1168
fill_detail_timing_data(display, panel_fixed_mode, &dtd->dtd[index]);
drivers/gpu/drm/i915/display/intel_bios.c
1172
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1177
static int intel_bios_ssc_frequency(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1180
switch (DISPLAY_VER(display)) {
drivers/gpu/drm/i915/display/intel_bios.c
1192
parse_general_features(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
1196
general = bdb_find_section(display, BDB_GENERAL_FEATURES);
drivers/gpu/drm/i915/display/intel_bios.c
1200
display->vbt.int_tv_support = general->int_tv_support;
drivers/gpu/drm/i915/display/intel_bios.c
1202
if (display->vbt.version >= 155 &&
drivers/gpu/drm/i915/display/intel_bios.c
1203
(HAS_DDI(display) || display->platform.valleyview))
drivers/gpu/drm/i915/display/intel_bios.c
1204
display->vbt.int_crt_support = general->int_crt_support;
drivers/gpu/drm/i915/display/intel_bios.c
1205
display->vbt.lvds_use_ssc = general->enable_ssc;
drivers/gpu/drm/i915/display/intel_bios.c
1206
display->vbt.lvds_ssc_freq =
drivers/gpu/drm/i915/display/intel_bios.c
1207
intel_bios_ssc_frequency(display, general->ssc_freq);
drivers/gpu/drm/i915/display/intel_bios.c
1208
display->vbt.display_clock_mode = general->display_clock_mode;
drivers/gpu/drm/i915/display/intel_bios.c
1209
display->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
drivers/gpu/drm/i915/display/intel_bios.c
1210
if (display->vbt.version >= 181) {
drivers/gpu/drm/i915/display/intel_bios.c
1211
display->vbt.orientation = general->rotate_180 ?
drivers/gpu/drm/i915/display/intel_bios.c
1215
display->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
drivers/gpu/drm/i915/display/intel_bios.c
1218
if (display->vbt.version >= 249 && general->afc_startup_config) {
drivers/gpu/drm/i915/display/intel_bios.c
1219
display->vbt.override_afc_startup = true;
drivers/gpu/drm/i915/display/intel_bios.c
1220
display->vbt.override_afc_startup_val = general->afc_startup_config == 1 ? 0 : 7;
drivers/gpu/drm/i915/display/intel_bios.c
1223
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1225
display->vbt.int_tv_support,
drivers/gpu/drm/i915/display/intel_bios.c
1226
display->vbt.int_crt_support,
drivers/gpu/drm/i915/display/intel_bios.c
1227
display->vbt.lvds_use_ssc,
drivers/gpu/drm/i915/display/intel_bios.c
1228
display->vbt.lvds_ssc_freq,
drivers/gpu/drm/i915/display/intel_bios.c
1229
display->vbt.display_clock_mode,
drivers/gpu/drm/i915/display/intel_bios.c
1230
display->vbt.fdi_rx_polarity_inverted);
drivers/gpu/drm/i915/display/intel_bios.c
1240
parse_sdvo_device_mapping(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
1249
if (!IS_DISPLAY_VER(display, 3, 7)) {
drivers/gpu/drm/i915/display/intel_bios.c
1250
drm_dbg_kms(display->drm, "Skipping SDVO device mapping\n");
drivers/gpu/drm/i915/display/intel_bios.c
1254
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
1269
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1273
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1279
mapping = &display->vbt.sdvo_mappings[child->dvo_port - 1];
drivers/gpu/drm/i915/display/intel_bios.c
1287
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1293
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1300
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1309
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1315
parse_driver_features(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
1319
driver = bdb_find_section(display, BDB_DRIVER_FEATURES);
drivers/gpu/drm/i915/display/intel_bios.c
1323
if (DISPLAY_VER(display) >= 5) {
drivers/gpu/drm/i915/display/intel_bios.c
1330
display->vbt.int_lvds_support = 0;
drivers/gpu/drm/i915/display/intel_bios.c
1343
if (display->vbt.version >= 134 &&
drivers/gpu/drm/i915/display/intel_bios.c
1346
display->vbt.int_lvds_support = 0;
drivers/gpu/drm/i915/display/intel_bios.c
1351
parse_panel_driver_features(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1356
driver = bdb_find_section(display, BDB_DRIVER_FEATURES);
drivers/gpu/drm/i915/display/intel_bios.c
1360
if (display->vbt.version < 228) {
drivers/gpu/drm/i915/display/intel_bios.c
1361
drm_dbg_kms(display->drm, "DRRS State Enabled:%d\n",
drivers/gpu/drm/i915/display/intel_bios.c
1385
parse_power_conservation_features(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1393
if (display->vbt.version < 228)
drivers/gpu/drm/i915/display/intel_bios.c
1396
power = bdb_find_section(display, BDB_LFP_POWER);
drivers/gpu/drm/i915/display/intel_bios.c
1419
if (display->vbt.version >= 232)
drivers/gpu/drm/i915/display/intel_bios.c
1422
if (display->vbt.version >= 233)
drivers/gpu/drm/i915/display/intel_bios.c
1438
parse_edp(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1445
edp = bdb_find_section(display, BDB_EDP);
drivers/gpu/drm/i915/display/intel_bios.c
1467
if (display->vbt.version >= 224) {
drivers/gpu/drm/i915/display/intel_bios.c
1482
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1500
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
152
bdb_find_section(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1520
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1540
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1546
if (display->vbt.version >= 173) {
drivers/gpu/drm/i915/display/intel_bios.c
1550
if (display->params.edp_vswing) {
drivers/gpu/drm/i915/display/intel_bios.c
1552
display->params.edp_vswing == 1;
drivers/gpu/drm/i915/display/intel_bios.c
1562
if (display->vbt.version >= 244)
drivers/gpu/drm/i915/display/intel_bios.c
1566
if (display->vbt.version >= 251)
drivers/gpu/drm/i915/display/intel_bios.c
157
list_for_each_entry(entry, &display->vbt.bdb_blocks, node) {
drivers/gpu/drm/i915/display/intel_bios.c
1570
if (display->vbt.version >= 261)
drivers/gpu/drm/i915/display/intel_bios.c
1576
parse_psr(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1583
psr = bdb_find_section(display, BDB_PSR);
drivers/gpu/drm/i915/display/intel_bios.c
1585
drm_dbg_kms(display->drm, "No PSR BDB found.\n");
drivers/gpu/drm/i915/display/intel_bios.c
1599
if (display->vbt.version >= 205 &&
drivers/gpu/drm/i915/display/intel_bios.c
1600
(DISPLAY_VER(display) >= 9 && !display->platform.broxton)) {
drivers/gpu/drm/i915/display/intel_bios.c
1612
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1632
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1645
if (display->vbt.version >= 226) {
drivers/gpu/drm/i915/display/intel_bios.c
1671
static void parse_dsi_backlight_ports(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1675
enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C;
drivers/gpu/drm/i915/display/intel_bios.c
1677
if (!panel->vbt.dsi.config->dual_link || display->vbt.version < 197) {
drivers/gpu/drm/i915/display/intel_bios.c
1717
parse_mipi_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1727
if (!intel_bios_is_dsi_present(display, &port))
drivers/gpu/drm/i915/display/intel_bios.c
1733
start = bdb_find_section(display, BDB_MIPI_CONFIG);
drivers/gpu/drm/i915/display/intel_bios.c
1735
drm_dbg_kms(display->drm, "No MIPI config BDB found");
drivers/gpu/drm/i915/display/intel_bios.c
1739
drm_dbg_kms(display->drm, "Found MIPI Config block, panel index = %d\n",
drivers/gpu/drm/i915/display/intel_bios.c
1760
parse_dsi_backlight_ports(display, panel, port);
drivers/gpu/drm/i915/display/intel_bios.c
1792
find_panel_sequence_block(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1810
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1824
drm_err(display->drm, "Invalid sequence block\n");
drivers/gpu/drm/i915/display/intel_bios.c
1836
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1842
static int goto_next_sequence(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1873
drm_err(display->drm, "Unknown operation byte\n");
drivers/gpu/drm/i915/display/intel_bios.c
1881
static int goto_next_sequence_v3(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1893
drm_err(display->drm, "Too small sequence size\n");
drivers/gpu/drm/i915/display/intel_bios.c
1910
drm_err(display->drm, "Invalid sequence size\n");
drivers/gpu/drm/i915/display/intel_bios.c
1920
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1943
drm_err(display->drm, "Unknown operation byte %u\n",
drivers/gpu/drm/i915/display/intel_bios.c
1956
static int get_init_otp_deassert_fragment_len(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
1962
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
1991
static void vlv_fixup_mipi_sequences(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
2009
len = get_init_otp_deassert_fragment_len(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
2013
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2046
static void icl_fixup_mipi_sequences(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
2051
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2059
static void fixup_mipi_sequences(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
2062
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_bios.c
2063
icl_fixup_mipi_sequences(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
2064
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_bios.c
2065
vlv_fixup_mipi_sequences(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
2069
parse_mipi_sequence(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
207
static size_t lfp_data_min_size(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
2083
sequence = bdb_find_section(display, BDB_MIPI_SEQUENCE);
drivers/gpu/drm/i915/display/intel_bios.c
2085
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2092
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2098
drm_dbg_kms(display->drm, "Found MIPI sequence block v%u\n",
drivers/gpu/drm/i915/display/intel_bios.c
2101
seq_data = find_panel_sequence_block(display, sequence, panel_type, &seq_size);
drivers/gpu/drm/i915/display/intel_bios.c
2116
drm_err(display->drm, "Unknown sequence %u\n",
drivers/gpu/drm/i915/display/intel_bios.c
212
ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);
drivers/gpu/drm/i915/display/intel_bios.c
2123
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2129
index = goto_next_sequence_v3(display, data, index, seq_size);
drivers/gpu/drm/i915/display/intel_bios.c
2131
index = goto_next_sequence(display, data, index, seq_size);
drivers/gpu/drm/i915/display/intel_bios.c
2133
drm_err(display->drm, "Invalid sequence %u\n",
drivers/gpu/drm/i915/display/intel_bios.c
2143
fixup_mipi_sequences(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
2145
drm_dbg_kms(display->drm, "MIPI related VBT parsing complete\n");
drivers/gpu/drm/i915/display/intel_bios.c
2154
parse_compression_parameters(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
2161
if (display->vbt.version < 198)
drivers/gpu/drm/i915/display/intel_bios.c
2164
params = bdb_find_section(display, BDB_COMPRESSION_PARAMETERS);
drivers/gpu/drm/i915/display/intel_bios.c
2168
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2175
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2181
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
2188
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2194
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2206
static u8 translate_iboost(struct intel_display *display, u8 val)
drivers/gpu/drm/i915/display/intel_bios.c
2211
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2268
static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin)
drivers/gpu/drm/i915/display/intel_bios.c
2273
if (INTEL_PCH_TYPE(display) >= PCH_MTL || display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/intel_bios.c
2276
} else if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_bios.c
2279
} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {
drivers/gpu/drm/i915/display/intel_bios.c
2281
} else if (display->platform.rocketlake && INTEL_PCH_TYPE(display) == PCH_TGP) {
drivers/gpu/drm/i915/display/intel_bios.c
2284
} else if (HAS_PCH_TGP(display) && DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_bios.c
2287
} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {
drivers/gpu/drm/i915/display/intel_bios.c
2290
} else if (HAS_PCH_CNP(display)) {
drivers/gpu/drm/i915/display/intel_bios.c
2303
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2361
static enum port dvo_port_to_port(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
2415
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_bios.c
2420
else if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_bios.c
2425
else if (display->platform.dg1 || display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_bios.c
2438
dsi_dvo_port_to_port(struct intel_display *display, u8 dvo_port)
drivers/gpu/drm/i915/display/intel_bios.c
2444
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_bios.c
2455
struct intel_display *display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
2459
port = dvo_port_to_port(display, child->dvo_port);
drivers/gpu/drm/i915/display/intel_bios.c
2460
if (port == PORT_NONE && DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_bios.c
2461
port = dsi_dvo_port_to_port(display, child->dvo_port);
drivers/gpu/drm/i915/display/intel_bios.c
2525
if (!devdata || devdata->display->vbt.version < 216)
drivers/gpu/drm/i915/display/intel_bios.c
2528
if (devdata->display->vbt.version >= 230)
drivers/gpu/drm/i915/display/intel_bios.c
2536
if (!devdata || devdata->display->vbt.version < 244)
drivers/gpu/drm/i915/display/intel_bios.c
2546
if (!devdata || devdata->display->vbt.version < 263)
drivers/gpu/drm/i915/display/intel_bios.c
2558
struct intel_display *display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
2574
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2585
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2596
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2606
struct intel_display *display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
2609
if (port != PORT_A || DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_bios.c
2617
drm_dbg_kms(display->drm, "VBT claims port A supports DVI%s, ignoring\n",
drivers/gpu/drm/i915/display/intel_bios.c
2627
struct intel_display *display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
2637
if (display->platform.broadwell && devdata->child.hdmi_level_shifter_value > 9) {
drivers/gpu/drm/i915/display/intel_bios.c
2638
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2687
return devdata && HAS_LSPCON(devdata->display) && devdata->child.lspcon;
drivers/gpu/drm/i915/display/intel_bios.c
2693
if (!devdata || devdata->display->vbt.version < 158 ||
drivers/gpu/drm/i915/display/intel_bios.c
2694
DISPLAY_VER(devdata->display) >= 14)
drivers/gpu/drm/i915/display/intel_bios.c
2702
if (!devdata || devdata->display->vbt.version < 204)
drivers/gpu/drm/i915/display/intel_bios.c
2724
static bool is_port_valid(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_bios.c
2731
if (port == PORT_F && display->platform.icelake)
drivers/gpu/drm/i915/display/intel_bios.c
2732
return display->platform.icelake_port_f;
drivers/gpu/drm/i915/display/intel_bios.c
2739
struct intel_display *display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
2759
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2768
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2773
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2779
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2786
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2793
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2799
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2805
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2813
drm_WARN(display->drm, child->use_vbt_vswing,
drivers/gpu/drm/i915/display/intel_bios.c
2820
struct intel_display *display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
2827
if (!is_port_valid(display, port)) {
drivers/gpu/drm/i915/display/intel_bios.c
2828
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2839
static bool has_ddi_port_info(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
2841
return DISPLAY_VER(display) >= 5 || display->platform.g4x;
drivers/gpu/drm/i915/display/intel_bios.c
2844
static void parse_ddi_ports(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
2848
if (!has_ddi_port_info(display))
drivers/gpu/drm/i915/display/intel_bios.c
2851
list_for_each_entry(devdata, &display->vbt.display_devices, node)
drivers/gpu/drm/i915/display/intel_bios.c
2854
list_for_each_entry(devdata, &display->vbt.display_devices, node)
drivers/gpu/drm/i915/display/intel_bios.c
2882
static bool child_device_size_valid(struct intel_display *display, int size)
drivers/gpu/drm/i915/display/intel_bios.c
2886
expected_size = child_device_expected_size(display->vbt.version);
drivers/gpu/drm/i915/display/intel_bios.c
2889
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2891
display->vbt.version, expected_size);
drivers/gpu/drm/i915/display/intel_bios.c
2896
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2898
size, expected_size, display->vbt.version);
drivers/gpu/drm/i915/display/intel_bios.c
2902
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2912
parse_general_definitions(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
2921
defs = bdb_find_section(display, BDB_GENERAL_DEFINITIONS);
drivers/gpu/drm/i915/display/intel_bios.c
2923
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2930
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2937
drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
drivers/gpu/drm/i915/display/intel_bios.c
2938
if (intel_gmbus_is_valid_pin(display, bus_pin))
drivers/gpu/drm/i915/display/intel_bios.c
2939
display->vbt.crt_ddc_pin = bus_pin;
drivers/gpu/drm/i915/display/intel_bios.c
2941
if (!child_device_size_valid(display, defs->child_dev_size))
drivers/gpu/drm/i915/display/intel_bios.c
2952
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2960
devdata->display = display;
drivers/gpu/drm/i915/display/intel_bios.c
2970
list_add_tail(&devdata->node, &display->vbt.display_devices);
drivers/gpu/drm/i915/display/intel_bios.c
2973
if (list_empty(&display->vbt.display_devices))
drivers/gpu/drm/i915/display/intel_bios.c
2974
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
2980
init_vbt_defaults(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
2982
display->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
drivers/gpu/drm/i915/display/intel_bios.c
2985
display->vbt.int_tv_support = 1;
drivers/gpu/drm/i915/display/intel_bios.c
2986
display->vbt.int_crt_support = 1;
drivers/gpu/drm/i915/display/intel_bios.c
2989
display->vbt.int_lvds_support = 1;
drivers/gpu/drm/i915/display/intel_bios.c
2992
display->vbt.lvds_use_ssc = 1;
drivers/gpu/drm/i915/display/intel_bios.c
2997
display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display,
drivers/gpu/drm/i915/display/intel_bios.c
2998
!HAS_PCH_SPLIT(display));
drivers/gpu/drm/i915/display/intel_bios.c
2999
drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n",
drivers/gpu/drm/i915/display/intel_bios.c
3000
display->vbt.lvds_ssc_freq);
drivers/gpu/drm/i915/display/intel_bios.c
3016
init_vbt_missing_defaults(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
3018
unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask;
drivers/gpu/drm/i915/display/intel_bios.c
3021
if (!HAS_DDI(display) && !display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_bios.c
3027
enum phy phy = intel_port_to_phy(display, port);
drivers/gpu/drm/i915/display/intel_bios.c
3033
if (intel_phy_is_tc(display, phy))
drivers/gpu/drm/i915/display/intel_bios.c
3041
devdata->display = display;
drivers/gpu/drm/i915/display/intel_bios.c
3060
list_add_tail(&devdata->node, &display->vbt.display_devices);
drivers/gpu/drm/i915/display/intel_bios.c
3062
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3068
display->vbt.version = 155;
drivers/gpu/drm/i915/display/intel_bios.c
3089
bool intel_bios_is_valid_vbt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3099
drm_dbg_kms(display->drm, "VBT header incomplete\n");
drivers/gpu/drm/i915/display/intel_bios.c
3104
drm_dbg_kms(display->drm, "VBT invalid signature\n");
drivers/gpu/drm/i915/display/intel_bios.c
3109
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3120
drm_dbg_kms(display->drm, "BDB header incomplete\n");
drivers/gpu/drm/i915/display/intel_bios.c
3126
drm_dbg_kms(display->drm, "BDB incomplete\n");
drivers/gpu/drm/i915/display/intel_bios.c
3133
static struct vbt_header *firmware_get_vbt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3138
const char *name = display->params.vbt_firmware;
drivers/gpu/drm/i915/display/intel_bios.c
3144
ret = request_firmware(&fw, name, display->drm->dev);
drivers/gpu/drm/i915/display/intel_bios.c
3146
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3152
if (intel_bios_is_valid_vbt(display, fw->data, fw->size)) {
drivers/gpu/drm/i915/display/intel_bios.c
3155
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3161
drm_dbg_kms(display->drm, "Invalid VBT firmware \"%s\"\n",
drivers/gpu/drm/i915/display/intel_bios.c
3170
static struct vbt_header *oprom_get_vbt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3189
drm_dbg_kms(display->drm, "VBT header incomplete\n");
drivers/gpu/drm/i915/display/intel_bios.c
3197
drm_dbg_kms(display->drm, "VBT incomplete (vbt_size overflows)\n");
drivers/gpu/drm/i915/display/intel_bios.c
3207
if (!intel_bios_is_valid_vbt(display, vbt, vbt_size))
drivers/gpu/drm/i915/display/intel_bios.c
3210
drm_dbg_kms(display->drm, "Found valid VBT in %s\n", type);
drivers/gpu/drm/i915/display/intel_bios.c
3226
static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3231
vbt = firmware_get_vbt(display, sizep);
drivers/gpu/drm/i915/display/intel_bios.c
3234
vbt = intel_opregion_get_vbt(display, sizep);
drivers/gpu/drm/i915/display/intel_bios.c
3240
if (!vbt && display->platform.dgfx)
drivers/gpu/drm/i915/display/intel_bios.c
3241
with_intel_display_rpm(display)
drivers/gpu/drm/i915/display/intel_bios.c
3242
vbt = oprom_get_vbt(display, intel_rom_spi(display->drm), sizep, "SPI flash");
drivers/gpu/drm/i915/display/intel_bios.c
3245
with_intel_display_rpm(display)
drivers/gpu/drm/i915/display/intel_bios.c
3246
vbt = oprom_get_vbt(display, intel_rom_pci(display->drm), sizep, "PCI ROM");
drivers/gpu/drm/i915/display/intel_bios.c
3259
void intel_bios_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
3264
INIT_LIST_HEAD(&display->vbt.display_devices);
drivers/gpu/drm/i915/display/intel_bios.c
3265
INIT_LIST_HEAD(&display->vbt.bdb_blocks);
drivers/gpu/drm/i915/display/intel_bios.c
3267
if (!HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_bios.c
3268
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3273
init_vbt_defaults(display);
drivers/gpu/drm/i915/display/intel_bios.c
3275
vbt = intel_bios_get_vbt(display, NULL);
drivers/gpu/drm/i915/display/intel_bios.c
3281
display->vbt.version = bdb->version;
drivers/gpu/drm/i915/display/intel_bios.c
3283
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3286
display->vbt.version);
drivers/gpu/drm/i915/display/intel_bios.c
3288
init_bdb_blocks(display, bdb);
drivers/gpu/drm/i915/display/intel_bios.c
3291
parse_general_features(display);
drivers/gpu/drm/i915/display/intel_bios.c
3292
parse_general_definitions(display);
drivers/gpu/drm/i915/display/intel_bios.c
3293
parse_driver_features(display);
drivers/gpu/drm/i915/display/intel_bios.c
3296
parse_compression_parameters(display);
drivers/gpu/drm/i915/display/intel_bios.c
3300
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3302
init_vbt_missing_defaults(display);
drivers/gpu/drm/i915/display/intel_bios.c
3306
parse_sdvo_device_mapping(display);
drivers/gpu/drm/i915/display/intel_bios.c
3307
parse_ddi_ports(display);
drivers/gpu/drm/i915/display/intel_bios.c
3312
static void intel_bios_init_panel(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3320
drm_WARN_ON(display->drm, !use_fallback);
drivers/gpu/drm/i915/display/intel_bios.c
3324
panel->vbt.panel_type = get_panel_type(display, devdata,
drivers/gpu/drm/i915/display/intel_bios.c
3327
drm_WARN_ON(display->drm, use_fallback);
drivers/gpu/drm/i915/display/intel_bios.c
3333
parse_panel_options(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3334
parse_generic_dtd(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3335
parse_lfp_data(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3336
parse_lfp_backlight(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3337
parse_sdvo_lvds_data(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3338
parse_panel_driver_features(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3339
parse_power_conservation_features(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3340
parse_edp(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3341
parse_psr(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3342
parse_mipi_config(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3343
parse_mipi_sequence(display, panel);
drivers/gpu/drm/i915/display/intel_bios.c
3346
void intel_bios_init_panel_early(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3350
intel_bios_init_panel(display, panel, devdata, NULL, false);
drivers/gpu/drm/i915/display/intel_bios.c
3353
void intel_bios_init_panel_late(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3358
intel_bios_init_panel(display, panel, devdata, drm_edid, true);
drivers/gpu/drm/i915/display/intel_bios.c
3365
void intel_bios_driver_remove(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
3370
list_for_each_entry_safe(devdata, nd, &display->vbt.display_devices,
drivers/gpu/drm/i915/display/intel_bios.c
3377
list_for_each_entry_safe(entry, ne, &display->vbt.bdb_blocks, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3406
bool intel_bios_is_tv_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
3410
if (!display->vbt.int_tv_support)
drivers/gpu/drm/i915/display/intel_bios.c
3413
if (list_empty(&display->vbt.display_devices))
drivers/gpu/drm/i915/display/intel_bios.c
3416
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3448
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
drivers/gpu/drm/i915/display/intel_bios.c
3452
if (list_empty(&display->vbt.display_devices))
drivers/gpu/drm/i915/display/intel_bios.c
3455
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3466
if (intel_gmbus_is_valid_pin(display, child->i2c_pin))
drivers/gpu/drm/i915/display/intel_bios.c
3482
return intel_opregion_vbt_present(display);
drivers/gpu/drm/i915/display/intel_bios.c
3495
bool intel_bios_is_port_present(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_bios.c
3499
if (WARN_ON(!has_ddi_port_info(display)))
drivers/gpu/drm/i915/display/intel_bios.c
3502
if (!is_port_valid(display, port))
drivers/gpu/drm/i915/display/intel_bios.c
3505
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3508
if (dvo_port_to_port(display, child->dvo_port) == port)
drivers/gpu/drm/i915/display/intel_bios.c
3544
bool intel_bios_is_dsi_present(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3549
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3556
if (dsi_dvo_port_to_port(display, dvo_port) == PORT_NONE) {
drivers/gpu/drm/i915/display/intel_bios.c
3557
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3564
*port = dsi_dvo_port_to_port(display, dvo_port);
drivers/gpu/drm/i915/display/intel_bios.c
3575
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_bios.c
3590
drm_dbg_kms(display->drm, "VBT: Unsupported BPC %d for DCS\n",
drivers/gpu/drm/i915/display/intel_bios.c
3613
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3619
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3620
!intel_dsc_get_slice_config(display, 1, slices_per_line,
drivers/gpu/drm/i915/display/intel_bios.c
3626
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3653
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_bios.c
3656
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3662
if (dsi_dvo_port_to_port(display, child->dvo_port) == encoder->port) {
drivers/gpu/drm/i915/display/intel_bios.c
367
static void *generate_lfp_data_ptrs(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3720
static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel)
drivers/gpu/drm/i915/display/intel_bios.c
3725
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_bios.c
3728
} else if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_bios.c
3731
} else if (display->platform.dg1 || display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_bios.c
3744
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
3756
return map_aux_ch(devdata->display, devdata->child.aux_channel);
drivers/gpu/drm/i915/display/intel_bios.c
3761
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_bios.c
3768
display = devdata->display;
drivers/gpu/drm/i915/display/intel_bios.c
3771
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3782
if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)
drivers/gpu/drm/i915/display/intel_bios.c
3785
return translate_iboost(devdata->display, devdata->child.dp_iboost_level);
drivers/gpu/drm/i915/display/intel_bios.c
3790
if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)
drivers/gpu/drm/i915/display/intel_bios.c
3793
return translate_iboost(devdata->display, devdata->child.hdmi_iboost_level);
drivers/gpu/drm/i915/display/intel_bios.c
3801
return map_ddc_pin(devdata->display, devdata->child.ddc_pin);
drivers/gpu/drm/i915/display/intel_bios.c
3806
return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
drivers/gpu/drm/i915/display/intel_bios.c
381
if (display->vbt.version < 155)
drivers/gpu/drm/i915/display/intel_bios.c
3811
return devdata->display->vbt.version >= 209 && devdata->child.tbt;
drivers/gpu/drm/i915/display/intel_bios.c
3816
return devdata->display->vbt.version >= 264 &&
drivers/gpu/drm/i915/display/intel_bios.c
3822
return devdata->display->vbt.version >= 264 &&
drivers/gpu/drm/i915/display/intel_bios.c
3837
intel_bios_encoder_data_lookup(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_bios.c
3841
list_for_each_entry(devdata, &display->vbt.display_devices, node) {
drivers/gpu/drm/i915/display/intel_bios.c
3849
void intel_bios_for_each_encoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3850
void (*func)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
3855
list_for_each_entry(devdata, &display->vbt.display_devices, node)
drivers/gpu/drm/i915/display/intel_bios.c
3856
func(display, devdata);
drivers/gpu/drm/i915/display/intel_bios.c
3861
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_bios.c
3865
vbt = intel_bios_get_vbt(display, &vbt_size);
drivers/gpu/drm/i915/display/intel_bios.c
3877
void intel_bios_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bios.c
3879
debugfs_create_file("i915_vbt", 0444, display->drm->debugfs_root,
drivers/gpu/drm/i915/display/intel_bios.c
3880
display, &intel_bios_vbt_fops);
drivers/gpu/drm/i915/display/intel_bios.c
390
drm_dbg_kms(display->drm, "Generating LFP data table pointers\n");
drivers/gpu/drm/i915/display/intel_bios.c
458
init_bdb_block(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
471
temp_block = generate_lfp_data_ptrs(display, bdb);
drivers/gpu/drm/i915/display/intel_bios.c
478
drm_WARN(display->drm, min_size == 0,
drivers/gpu/drm/i915/display/intel_bios.c
501
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
507
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
513
list_add_tail(&entry->node, &display->vbt.bdb_blocks);
drivers/gpu/drm/i915/display/intel_bios.c
516
static void init_bdb_blocks(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
526
min_size = lfp_data_min_size(display);
drivers/gpu/drm/i915/display/intel_bios.c
528
init_bdb_block(display, bdb, section_id, min_size);
drivers/gpu/drm/i915/display/intel_bios.c
533
fill_detail_timing_data(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
576
drm_dbg_kms(display->drm, "reducing hsync_end %d->%d\n",
drivers/gpu/drm/i915/display/intel_bios.c
581
drm_dbg_kms(display->drm, "reducing vsync_end %d->%d\n",
drivers/gpu/drm/i915/display/intel_bios.c
641
static int opregion_get_panel_type(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
645
return intel_opregion_get_panel_type(display);
drivers/gpu/drm/i915/display/intel_bios.c
648
static int vbt_get_panel_type(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
654
lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);
drivers/gpu/drm/i915/display/intel_bios.c
659
drm_dbg_kms(display->drm, "Invalid VBT panel type 0x%x\n",
drivers/gpu/drm/i915/display/intel_bios.c
666
drm_dbg_kms(display->drm, "Invalid VBT panel type 2 0x%x\n",
drivers/gpu/drm/i915/display/intel_bios.c
674
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
680
static int pnpid_get_panel_type(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
699
p = drm_dbg_printer(display->drm, DRM_UT_KMS, "EDID");
drivers/gpu/drm/i915/display/intel_bios.c
702
ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);
drivers/gpu/drm/i915/display/intel_bios.c
706
data = bdb_find_section(display, BDB_LFP_DATA);
drivers/gpu/drm/i915/display/intel_bios.c
73
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_bios.c
730
static int fallback_get_panel_type(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
744
static int get_panel_type(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
750
int (*get_panel_type)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
775
panel_types[i].panel_type = panel_types[i].get_panel_type(display, devdata,
drivers/gpu/drm/i915/display/intel_bios.c
778
drm_WARN_ON(display->drm, panel_types[i].panel_type > 0xf &&
drivers/gpu/drm/i915/display/intel_bios.c
782
drm_dbg_kms(display->drm, "Panel type (%s): %d\n",
drivers/gpu/drm/i915/display/intel_bios.c
796
drm_dbg_kms(display->drm, "Selected panel type (%s): %d\n",
drivers/gpu/drm/i915/display/intel_bios.c
814
parse_panel_options(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
821
lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);
drivers/gpu/drm/i915/display/intel_bios.c
845
drm_dbg_kms(display->drm, "DRRS supported mode is static\n");
drivers/gpu/drm/i915/display/intel_bios.c
849
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
854
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
861
parse_lfp_panel_dtd(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
879
fill_detail_timing_data(display, panel_fixed_mode, panel_dvo_timing);
drivers/gpu/drm/i915/display/intel_bios.c
883
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
895
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
902
parse_lfp_data(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
912
ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);
drivers/gpu/drm/i915/display/intel_bios.c
916
data = bdb_find_section(display, BDB_LFP_DATA);
drivers/gpu/drm/i915/display/intel_bios.c
921
parse_lfp_panel_dtd(display, panel, data, ptrs);
drivers/gpu/drm/i915/display/intel_bios.c
925
p = drm_dbg_printer(display->drm, DRM_UT_KMS, "Panel");
drivers/gpu/drm/i915/display/intel_bios.c
932
drm_dbg_kms(display->drm, "Panel name: %.*s\n",
drivers/gpu/drm/i915/display/intel_bios.c
936
if (display->vbt.version >= 188) {
drivers/gpu/drm/i915/display/intel_bios.c
939
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bios.c
946
parse_generic_dtd(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.c
962
if (display->vbt.version < 229)
drivers/gpu/drm/i915/display/intel_bios.c
965
generic_dtd = bdb_find_section(display, BDB_GENERIC_DTD);
drivers/gpu/drm/i915/display/intel_bios.c
970
drm_err(display->drm, "GDTD size %u is too small.\n",
drivers/gpu/drm/i915/display/intel_bios.c
975
drm_err(display->drm, "Unexpected GDTD size %u\n",
drivers/gpu/drm/i915/display/intel_bios.c
983
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bios.h
102
void intel_bios_for_each_encoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.h
103
void (*func)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.h
106
void intel_bios_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bios.h
53
void intel_bios_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bios.h
54
void intel_bios_init_panel_early(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.h
57
void intel_bios_init_panel_late(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.h
62
void intel_bios_driver_remove(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bios.h
63
bool intel_bios_is_valid_vbt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bios.h
65
bool intel_bios_is_tv_present(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bios.h
66
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);
drivers/gpu/drm/i915/display/intel_bios.h
67
bool intel_bios_is_port_present(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_bios.h
68
bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port);
drivers/gpu/drm/i915/display/intel_bios.h
74
intel_bios_encoder_data_lookup(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_bo.c
102
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
104
display->parent->bo->fbdev_destroy(obj);
drivers/gpu/drm/i915/display/intel_bo.c
110
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
112
return display->parent->bo->fbdev_fill_info(obj, info, vma);
drivers/gpu/drm/i915/display/intel_bo.c
13
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
15
return display->parent->bo->is_tiled && display->parent->bo->is_tiled(obj);
drivers/gpu/drm/i915/display/intel_bo.c
20
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
22
return display->parent->bo->is_userptr && display->parent->bo->is_userptr(obj);
drivers/gpu/drm/i915/display/intel_bo.c
27
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
29
return display->parent->bo->is_shmem && display->parent->bo->is_shmem(obj);
drivers/gpu/drm/i915/display/intel_bo.c
34
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
36
return display->parent->bo->is_protected(obj);
drivers/gpu/drm/i915/display/intel_bo.c
41
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
43
return display->parent->bo->key_check(obj);
drivers/gpu/drm/i915/display/intel_bo.c
48
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
50
return display->parent->bo->fb_mmap(obj, vma);
drivers/gpu/drm/i915/display/intel_bo.c
55
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
57
return display->parent->bo->read_from_page(obj, offset, dst, size);
drivers/gpu/drm/i915/display/intel_bo.c
62
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
64
if (display->parent->bo->describe)
drivers/gpu/drm/i915/display/intel_bo.c
65
display->parent->bo->describe(m, obj);
drivers/gpu/drm/i915/display/intel_bo.c
70
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
72
return display->parent->bo->framebuffer_init(obj, mode_cmd);
drivers/gpu/drm/i915/display/intel_bo.c
77
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_bo.c
79
display->parent->bo->framebuffer_fini(obj);
drivers/gpu/drm/i915/display/intel_bo.c
82
struct drm_gem_object *intel_bo_framebuffer_lookup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bo.c
86
return display->parent->bo->framebuffer_lookup(display->drm, filp, user_mode_cmd);
drivers/gpu/drm/i915/display/intel_bo.c
90
u32 intel_bo_fbdev_pitch_align(struct intel_display *display, u32 stride)
drivers/gpu/drm/i915/display/intel_bo.c
92
return display->parent->bo->fbdev_pitch_align(stride);
drivers/gpu/drm/i915/display/intel_bo.c
95
struct drm_gem_object *intel_bo_fbdev_create(struct intel_display *display, int size)
drivers/gpu/drm/i915/display/intel_bo.c
97
return display->parent->bo->fbdev_create(display->drm, size);
drivers/gpu/drm/i915/display/intel_bo.h
32
struct drm_gem_object *intel_bo_framebuffer_lookup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bo.h
36
u32 intel_bo_fbdev_pitch_align(struct intel_display *display, u32 stride);
drivers/gpu/drm/i915/display/intel_bo.h
37
struct drm_gem_object *intel_bo_fbdev_create(struct intel_display *display, int size);
drivers/gpu/drm/i915/display/intel_bw.c
1008
static void icl_force_disable_sagv(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
1011
unsigned int qgv_points = icl_max_bw_qgv_point_mask(display, 0);
drivers/gpu/drm/i915/display/intel_bw.c
1012
unsigned int psf_points = icl_max_bw_psf_gv_point_mask(display);
drivers/gpu/drm/i915/display/intel_bw.c
1014
bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display,
drivers/gpu/drm/i915/display/intel_bw.c
1018
drm_dbg_kms(display->drm, "Forcing SAGV disable: mask 0x%x\n",
drivers/gpu/drm/i915/display/intel_bw.c
102
val = intel_mchbar_read(display, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
drivers/gpu/drm/i915/display/intel_bw.c
1021
icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask);
drivers/gpu/drm/i915/display/intel_bw.c
1026
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
1044
drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
drivers/gpu/drm/i915/display/intel_bw.c
1053
icl_pcode_restrict_qgv_points(display, new_mask);
drivers/gpu/drm/i915/display/intel_bw.c
1058
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
1076
drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
drivers/gpu/drm/i915/display/intel_bw.c
1085
icl_pcode_restrict_qgv_points(display, new_mask);
drivers/gpu/drm/i915/display/intel_bw.c
1088
static int mtl_find_qgv_points(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
1094
unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
drivers/gpu/drm/i915/display/intel_bw.c
1108
if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
drivers/gpu/drm/i915/display/intel_bw.c
111
static int icl_pcode_read_qgv_point_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
1110
drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");
drivers/gpu/drm/i915/display/intel_bw.c
1120
tgl_max_bw_index(display, num_active_planes, i);
drivers/gpu/drm/i915/display/intel_bw.c
1123
if (bw_index >= ARRAY_SIZE(display->bw.max))
drivers/gpu/drm/i915/display/intel_bw.c
1126
max_data_rate = display->bw.max[bw_index].deratedbw[i];
drivers/gpu/drm/i915/display/intel_bw.c
1133
qgv_peak_bw = display->bw.max[bw_index].peakbw[i];
drivers/gpu/drm/i915/display/intel_bw.c
1136
drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
drivers/gpu/drm/i915/display/intel_bw.c
1140
drm_dbg_kms(display->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",
drivers/gpu/drm/i915/display/intel_bw.c
1148
drm_dbg_kms(display->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",
drivers/gpu/drm/i915/display/intel_bw.c
1159
static int icl_find_qgv_points(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
1165
unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;
drivers/gpu/drm/i915/display/intel_bw.c
1166
unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
drivers/gpu/drm/i915/display/intel_bw.c
1177
unsigned int max_data_rate = icl_qgv_bw(display,
drivers/gpu/drm/i915/display/intel_bw.c
118
ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
drivers/gpu/drm/i915/display/intel_bw.c
1182
drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d\n",
drivers/gpu/drm/i915/display/intel_bw.c
1187
unsigned int max_data_rate = adl_psf_bw(display, i);
drivers/gpu/drm/i915/display/intel_bw.c
1192
drm_dbg_kms(display->drm, "PSF GV point %d: max bw %d"
drivers/gpu/drm/i915/display/intel_bw.c
1203
drm_dbg_kms(display->drm, "No QGV points provide sufficient memory"
drivers/gpu/drm/i915/display/intel_bw.c
1210
drm_dbg_kms(display->drm, "No PSF GV points provide sufficient memory"
drivers/gpu/drm/i915/display/intel_bw.c
1221
if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
drivers/gpu/drm/i915/display/intel_bw.c
1222
qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);
drivers/gpu/drm/i915/display/intel_bw.c
1223
drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",
drivers/gpu/drm/i915/display/intel_bw.c
1231
new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(display,
drivers/gpu/drm/i915/display/intel_bw.c
1247
static int intel_bw_check_qgv_points(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
1251
unsigned int data_rate = intel_bw_data_rate(display, new_bw_state);
drivers/gpu/drm/i915/display/intel_bw.c
1253
intel_bw_num_active_planes(display, new_bw_state);
drivers/gpu/drm/i915/display/intel_bw.c
1257
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_bw.c
1258
return mtl_find_qgv_points(display, data_rate, num_active_planes,
drivers/gpu/drm/i915/display/intel_bw.c
1261
return icl_find_qgv_points(display, data_rate, num_active_planes,
drivers/gpu/drm/i915/display/intel_bw.c
1267
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
1299
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
1311
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
1339
if (intel_bw_can_enable_sagv(display, new_bw_state) !=
drivers/gpu/drm/i915/display/intel_bw.c
1340
intel_bw_can_enable_sagv(display, old_bw_state)) {
drivers/gpu/drm/i915/display/intel_bw.c
1355
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
136
static int adls_pcode_read_psf_gv_point_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
1361
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_bw.c
1369
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_bw.c
1380
intel_bw_can_enable_sagv(display, old_bw_state) !=
drivers/gpu/drm/i915/display/intel_bw.c
1381
intel_bw_can_enable_sagv(display, new_bw_state))
drivers/gpu/drm/i915/display/intel_bw.c
1391
ret = intel_bw_check_qgv_points(display, old_bw_state, new_bw_state);
drivers/gpu/drm/i915/display/intel_bw.c
1401
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_bw.c
1409
drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n",
drivers/gpu/drm/i915/display/intel_bw.c
1415
void intel_bw_update_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
1418
to_intel_bw_state(display->bw.obj.state);
drivers/gpu/drm/i915/display/intel_bw.c
1421
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_bw.c
1426
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_bw.c
143
ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
drivers/gpu/drm/i915/display/intel_bw.c
1431
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_bw.c
1441
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_bw.c
1443
to_intel_bw_state(display->bw.obj.state);
drivers/gpu/drm/i915/display/intel_bw.c
1446
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_bw.c
1476
int intel_bw_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
1484
intel_atomic_global_obj_init(display, &display->bw.obj,
drivers/gpu/drm/i915/display/intel_bw.c
1491
if (intel_has_sagv(display) && IS_DISPLAY_VER(display, 11, 13))
drivers/gpu/drm/i915/display/intel_bw.c
1492
icl_force_disable_sagv(display, state);
drivers/gpu/drm/i915/display/intel_bw.c
1511
bool intel_bw_can_enable_sagv(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
156
static u16 icl_qgv_points_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
158
unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;
drivers/gpu/drm/i915/display/intel_bw.c
159
unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
drivers/gpu/drm/i915/display/intel_bw.c
176
static bool is_sagv_enabled(struct intel_display *display, u16 points_mask)
drivers/gpu/drm/i915/display/intel_bw.c
178
return !is_power_of_2(~points_mask & icl_qgv_points_mask(display) &
drivers/gpu/drm/i915/display/intel_bw.c
182
static int icl_pcode_restrict_qgv_points(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
187
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_bw.c
191
ret = intel_parent_pcode_request(display, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
drivers/gpu/drm/i915/display/intel_bw.c
198
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
204
display->sagv.status = is_sagv_enabled(display, points_mask) ?
drivers/gpu/drm/i915/display/intel_bw.c
210
static int mtl_read_qgv_point_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
215
val = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
drivers/gpu/drm/i915/display/intel_bw.c
216
val2 = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
drivers/gpu/drm/i915/display/intel_bw.c
231
intel_read_qgv_point_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
235
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_bw.c
236
return mtl_read_qgv_point_info(display, sp, point);
drivers/gpu/drm/i915/display/intel_bw.c
237
else if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_bw.c
238
return dg1_mchbar_read_qgv_point_info(display, sp, point);
drivers/gpu/drm/i915/display/intel_bw.c
240
return icl_pcode_read_qgv_point_info(display, sp, point);
drivers/gpu/drm/i915/display/intel_bw.c
243
static bool is_y_tile(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
246
return !HAS_4TILE(display);
drivers/gpu/drm/i915/display/intel_bw.c
249
static int icl_get_qgv_points(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
258
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_bw.c
287
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_bw.c
290
qi->t_bl = is_y_tile(display) ? 8 : 4;
drivers/gpu/drm/i915/display/intel_bw.c
293
qi->deinterleave = is_y_tile(display) ? 1 : 2;
drivers/gpu/drm/i915/display/intel_bw.c
296
qi->t_bl = is_y_tile(display) ? 16 : 8;
drivers/gpu/drm/i915/display/intel_bw.c
299
qi->deinterleave = is_y_tile(display) ? 1 : 2;
drivers/gpu/drm/i915/display/intel_bw.c
302
if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_bw.c
314
qi->deinterleave = is_y_tile(display) ? 2 : 4;
drivers/gpu/drm/i915/display/intel_bw.c
321
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/intel_bw.c
326
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
333
ret = intel_read_qgv_point_info(display, sp, i);
drivers/gpu/drm/i915/display/intel_bw.c
335
drm_dbg_kms(display->drm, "Could not read QGV %d info\n", i);
drivers/gpu/drm/i915/display/intel_bw.c
339
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
346
ret = adls_pcode_read_psf_gv_point_info(display, qi->psf_points);
drivers/gpu/drm/i915/display/intel_bw.c
348
drm_err(display->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
drivers/gpu/drm/i915/display/intel_bw.c
353
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
436
static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
439
if (display->platform.icelake ||
drivers/gpu/drm/i915/display/intel_bw.c
440
display->platform.jasperlake ||
drivers/gpu/drm/i915/display/intel_bw.c
441
display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_bw.c
443
else if (display->platform.tigerlake ||
drivers/gpu/drm/i915/display/intel_bw.c
444
display->platform.dg1)
drivers/gpu/drm/i915/display/intel_bw.c
446
else if (display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_bw.c
448
else if (display->platform.alderlake_s ||
drivers/gpu/drm/i915/display/intel_bw.c
449
display->platform.meteorlake ||
drivers/gpu/drm/i915/display/intel_bw.c
450
display->platform.lunarlake)
drivers/gpu/drm/i915/display/intel_bw.c
452
else if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_bw.c
454
else if (display->platform.battlemage &&
drivers/gpu/drm/i915/display/intel_bw.c
457
else if (display->platform.battlemage)
drivers/gpu/drm/i915/display/intel_bw.c
459
else if (display->platform.pantherlake_wildcatlake)
drivers/gpu/drm/i915/display/intel_bw.c
461
else if (display->platform.pantherlake ||
drivers/gpu/drm/i915/display/intel_bw.c
462
display->platform.novalake)
drivers/gpu/drm/i915/display/intel_bw.c
492
static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
494
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_bw.c
496
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_bw.c
503
if (display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_bw.c
507
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/intel_bw.c
514
static int icl_get_bw_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
524
int num_groups = ARRAY_SIZE(display->bw.max);
drivers/gpu/drm/i915/display/intel_bw.c
527
ret = icl_get_qgv_points(display, dram_info, &qi);
drivers/gpu/drm/i915/display/intel_bw.c
529
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
537
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile(display) ? 4 : 2);
drivers/gpu/drm/i915/display/intel_bw.c
540
struct intel_bw_info *bi = &display->bw.max[i];
drivers/gpu/drm/i915/display/intel_bw.c
567
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
578
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/intel_bw.c
580
display->sagv.status = I915_SAGV_ENABLED;
drivers/gpu/drm/i915/display/intel_bw.c
590
static int tgl_get_bw_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
600
int num_groups = ARRAY_SIZE(display->bw.max);
drivers/gpu/drm/i915/display/intel_bw.c
603
ret = icl_get_qgv_points(display, dram_info, &qi);
drivers/gpu/drm/i915/display/intel_bw.c
605
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
610
if (DISPLAY_VER(display) < 14 &&
drivers/gpu/drm/i915/display/intel_bw.c
614
if (num_channels < qi.max_numchannels && DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_bw.c
617
if (DISPLAY_VER(display) >= 12 && num_channels > qi.max_numchannels)
drivers/gpu/drm/i915/display/intel_bw.c
618
drm_warn(display->drm, "Number of channels exceeds max number of channels.");
drivers/gpu/drm/i915/display/intel_bw.c
633
struct intel_bw_info *bi = &display->bw.max[i];
drivers/gpu/drm/i915/display/intel_bw.c
641
bi_next = &display->bw.max[i + 1];
drivers/gpu/drm/i915/display/intel_bw.c
670
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
681
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
693
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/intel_bw.c
695
display->sagv.status = I915_SAGV_ENABLED;
drivers/gpu/drm/i915/display/intel_bw.c
700
static void dg2_get_bw_info(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
702
unsigned int deratedbw = display->platform.dg2_g11 ? 38000 : 50000;
drivers/gpu/drm/i915/display/intel_bw.c
703
int num_groups = ARRAY_SIZE(display->bw.max);
drivers/gpu/drm/i915/display/intel_bw.c
714
struct intel_bw_info *bi = &display->bw.max[i];
drivers/gpu/drm/i915/display/intel_bw.c
722
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/intel_bw.c
725
static int xe2_hpd_get_bw_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
734
ret = icl_get_qgv_points(display, dram_info, &qi);
drivers/gpu/drm/i915/display/intel_bw.c
736
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_bw.c
748
display->bw.max[0].deratedbw[i] =
drivers/gpu/drm/i915/display/intel_bw.c
750
display->bw.max[0].peakbw[i] = bw;
drivers/gpu/drm/i915/display/intel_bw.c
752
drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
drivers/gpu/drm/i915/display/intel_bw.c
753
i, display->bw.max[0].deratedbw[i],
drivers/gpu/drm/i915/display/intel_bw.c
754
display->bw.max[0].peakbw[i]);
drivers/gpu/drm/i915/display/intel_bw.c
758
display->bw.max[0].num_planes = 1;
drivers/gpu/drm/i915/display/intel_bw.c
759
display->bw.max[0].num_qgv_points = qi.num_points;
drivers/gpu/drm/i915/display/intel_bw.c
76
static int dg1_mchbar_read_qgv_point_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
760
for (i = 1; i < ARRAY_SIZE(display->bw.max); i++)
drivers/gpu/drm/i915/display/intel_bw.c
761
memcpy(&display->bw.max[i], &display->bw.max[0],
drivers/gpu/drm/i915/display/intel_bw.c
762
sizeof(display->bw.max[0]));
drivers/gpu/drm/i915/display/intel_bw.c
768
drm_WARN_ON(display->drm, qi.num_points != 2);
drivers/gpu/drm/i915/display/intel_bw.c
769
display->sagv.status = I915_SAGV_ENABLED;
drivers/gpu/drm/i915/display/intel_bw.c
774
static unsigned int icl_max_bw_index(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
784
for (i = 0; i < ARRAY_SIZE(display->bw.max); i++) {
drivers/gpu/drm/i915/display/intel_bw.c
786
&display->bw.max[i];
drivers/gpu/drm/i915/display/intel_bw.c
802
static unsigned int tgl_max_bw_index(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
807
for (i = ARRAY_SIZE(display->bw.max) - 1; i >= 0; i--) {
drivers/gpu/drm/i915/display/intel_bw.c
809
&display->bw.max[i];
drivers/gpu/drm/i915/display/intel_bw.c
825
static unsigned int adl_psf_bw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
829
&display->bw.max[0];
drivers/gpu/drm/i915/display/intel_bw.c
83
val = intel_mchbar_read(display, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
drivers/gpu/drm/i915/display/intel_bw.c
834
static unsigned int icl_qgv_bw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
839
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_bw.c
840
idx = tgl_max_bw_index(display, num_active_planes, qgv_point);
drivers/gpu/drm/i915/display/intel_bw.c
842
idx = icl_max_bw_index(display, num_active_planes, qgv_point);
drivers/gpu/drm/i915/display/intel_bw.c
844
if (idx >= ARRAY_SIZE(display->bw.max))
drivers/gpu/drm/i915/display/intel_bw.c
847
return display->bw.max[idx].deratedbw[qgv_point];
drivers/gpu/drm/i915/display/intel_bw.c
850
void intel_bw_init_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
856
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_bw.c
859
dram_info = intel_dram_info(display);
drivers/gpu/drm/i915/display/intel_bw.c
860
soc_bw_params = get_soc_bw_params(display, dram_info);
drivers/gpu/drm/i915/display/intel_bw.c
861
display_bw_params = get_display_bw_params(display);
drivers/gpu/drm/i915/display/intel_bw.c
869
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_bw.c
870
drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
drivers/gpu/drm/i915/display/intel_bw.c
872
if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
drivers/gpu/drm/i915/display/intel_bw.c
873
xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
drivers/gpu/drm/i915/display/intel_bw.c
874
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_bw.c
875
dg2_get_bw_info(display);
drivers/gpu/drm/i915/display/intel_bw.c
876
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_bw.c
877
tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
drivers/gpu/drm/i915/display/intel_bw.c
878
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/intel_bw.c
879
icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
drivers/gpu/drm/i915/display/intel_bw.c
883
static unsigned int intel_bw_num_active_planes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
889
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_bw.c
895
static unsigned int intel_bw_data_rate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
90
val = intel_mchbar_read(display, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
drivers/gpu/drm/i915/display/intel_bw.c
901
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_bw.c
904
if (DISPLAY_VER(display) >= 13 && intel_display_vtd_active(display))
drivers/gpu/drm/i915/display/intel_bw.c
918
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
921
bw_state = intel_atomic_get_old_global_obj_state(state, &display->bw.obj);
drivers/gpu/drm/i915/display/intel_bw.c
929
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
932
bw_state = intel_atomic_get_new_global_obj_state(state, &display->bw.obj);
drivers/gpu/drm/i915/display/intel_bw.c
940
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_bw.c
943
bw_state = intel_atomic_get_global_obj_state(state, &display->bw.obj);
drivers/gpu/drm/i915/display/intel_bw.c
950
static unsigned int icl_max_bw_qgv_point_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
953
unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
drivers/gpu/drm/i915/display/intel_bw.c
960
icl_qgv_bw(display, num_active_planes, i);
drivers/gpu/drm/i915/display/intel_bw.c
979
static u16 icl_prepare_qgv_points_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_bw.c
98
val = intel_mchbar_read(display, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
drivers/gpu/drm/i915/display/intel_bw.c
984
ADLS_PCODE_REQ_PSF_PT(psf_points)) & icl_qgv_points_mask(display);
drivers/gpu/drm/i915/display/intel_bw.c
987
static unsigned int icl_max_bw_psf_gv_point_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_bw.c
989
unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;
drivers/gpu/drm/i915/display/intel_bw.c
995
unsigned int max_data_rate = adl_psf_bw(display, i);
drivers/gpu/drm/i915/display/intel_bw.h
29
void intel_bw_init_hw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bw.h
30
int intel_bw_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bw.h
32
void intel_bw_update_hw_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_bw.h
36
bool intel_bw_can_enable_sagv(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_casf.c
102
drm_dbg_kms(display->drm, "CASF not supported with joiner\n");
drivers/gpu/drm/i915/display/intel_casf.c
128
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_casf.c
132
sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
drivers/gpu/drm/i915/display/intel_casf.c
134
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_casf.c
171
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_casf.c
177
drm_WARN(display->drm, 0, "Second scaler not enabled\n");
drivers/gpu/drm/i915/display/intel_casf.c
181
intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),
drivers/gpu/drm/i915/display/intel_casf.c
194
intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0),
drivers/gpu/drm/i915/display/intel_casf.c
66
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_casf.c
70
intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
drivers/gpu/drm/i915/display/intel_casf.c
74
intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
drivers/gpu/drm/i915/display/intel_casf.c
95
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
1006
static void skl_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1011
skl_dpll0_update(display, cdclk_config);
drivers/gpu/drm/i915/display/intel_cdclk.c
1018
cdctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1073
static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1075
bool changed = display->cdclk.skl_preferred_vco_freq != vco;
drivers/gpu/drm/i915/display/intel_cdclk.c
1077
display->cdclk.skl_preferred_vco_freq = vco;
drivers/gpu/drm/i915/display/intel_cdclk.c
1080
intel_update_max_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
1083
static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1085
drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
drivers/gpu/drm/i915/display/intel_cdclk.c
1102
static void skl_dpll0_enable(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1104
intel_de_rmw(display, DPLL_CTRL1,
drivers/gpu/drm/i915/display/intel_cdclk.c
1109
skl_dpll0_link_rate(display, vco));
drivers/gpu/drm/i915/display/intel_cdclk.c
1110
intel_de_posting_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_cdclk.c
1112
intel_de_rmw(display, LCPLL1_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
1115
if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
drivers/gpu/drm/i915/display/intel_cdclk.c
1116
drm_err(display->drm, "DPLL0 not locked\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1118
display->cdclk.hw.vco = vco;
drivers/gpu/drm/i915/display/intel_cdclk.c
1121
skl_set_preferred_cdclk_vco(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
1124
static void skl_dpll0_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
1126
intel_de_rmw(display, LCPLL1_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
1129
if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
drivers/gpu/drm/i915/display/intel_cdclk.c
1130
drm_err(display->drm, "Couldn't disable DPLL0\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1132
display->cdclk.hw.vco = 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
1135
static u32 skl_cdclk_freq_sel(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1140
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
1141
cdclk != display->cdclk.hw.bypass);
drivers/gpu/drm/i915/display/intel_cdclk.c
1142
drm_WARN_ON(display->drm, vco != 0);
drivers/gpu/drm/i915/display/intel_cdclk.c
1158
static void skl_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1175
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
1176
display->platform.skylake && vco == 8640000);
drivers/gpu/drm/i915/display/intel_cdclk.c
1178
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
1183
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
1188
freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
1190
if (display->cdclk.hw.vco != 0 &&
drivers/gpu/drm/i915/display/intel_cdclk.c
1191
display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1192
skl_dpll0_disable(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
1194
cdclk_ctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1196
if (display->cdclk.hw.vco != vco) {
drivers/gpu/drm/i915/display/intel_cdclk.c
1200
intel_de_write(display, CDCLK_CTL, cdclk_ctl);
drivers/gpu/drm/i915/display/intel_cdclk.c
1205
intel_de_write(display, CDCLK_CTL, cdclk_ctl);
drivers/gpu/drm/i915/display/intel_cdclk.c
1206
intel_de_posting_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1208
if (display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1209
skl_dpll0_enable(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
1213
intel_de_write(display, CDCLK_CTL, cdclk_ctl);
drivers/gpu/drm/i915/display/intel_cdclk.c
1216
intel_de_write(display, CDCLK_CTL, cdclk_ctl);
drivers/gpu/drm/i915/display/intel_cdclk.c
1220
intel_de_write(display, CDCLK_CTL, cdclk_ctl);
drivers/gpu/drm/i915/display/intel_cdclk.c
1221
intel_de_posting_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1224
intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
1227
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
1230
static void skl_sanitize_cdclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
1239
if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
drivers/gpu/drm/i915/display/intel_cdclk.c
1242
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
1243
intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
drivers/gpu/drm/i915/display/intel_cdclk.c
1246
if (display->cdclk.hw.vco == 0 ||
drivers/gpu/drm/i915/display/intel_cdclk.c
1247
display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
drivers/gpu/drm/i915/display/intel_cdclk.c
1256
cdctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1258
skl_cdclk_decimal(display->cdclk.hw.cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
1267
drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
1268
intel_de_read(display, CDCLK_CTL), expected);
drivers/gpu/drm/i915/display/intel_cdclk.c
1270
intel_de_write(display, CDCLK_CTL, expected);
drivers/gpu/drm/i915/display/intel_cdclk.c
1277
drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1280
display->cdclk.hw.cdclk = 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
1282
display->cdclk.hw.vco = ~0;
drivers/gpu/drm/i915/display/intel_cdclk.c
1285
static void skl_cdclk_init_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
1289
skl_sanitize_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
1291
if (display->cdclk.hw.cdclk != 0 &&
drivers/gpu/drm/i915/display/intel_cdclk.c
1292
display->cdclk.hw.vco != 0) {
drivers/gpu/drm/i915/display/intel_cdclk.c
1297
if (display->cdclk.skl_preferred_vco_freq == 0)
drivers/gpu/drm/i915/display/intel_cdclk.c
1298
skl_set_preferred_cdclk_vco(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1299
display->cdclk.hw.vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
1303
cdclk_config = display->cdclk.hw;
drivers/gpu/drm/i915/display/intel_cdclk.c
1305
cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
1311
skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
1314
static void skl_cdclk_uninit_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
1316
struct intel_cdclk_config cdclk_config = display->cdclk.hw;
drivers/gpu/drm/i915/display/intel_cdclk.c
1322
skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
1598
static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
1600
const struct intel_cdclk_vals *table = display->cdclk.table;
drivers/gpu/drm/i915/display/intel_cdclk.c
1604
if (table[i].refclk == display->cdclk.hw.ref &&
drivers/gpu/drm/i915/display/intel_cdclk.c
1608
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_cdclk.c
161
void (*get_cdclk)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1610
min_cdclk, display->cdclk.hw.ref);
drivers/gpu/drm/i915/display/intel_cdclk.c
1611
return display->cdclk.max_cdclk_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
1614
static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
1616
const struct intel_cdclk_vals *table = display->cdclk.table;
drivers/gpu/drm/i915/display/intel_cdclk.c
1619
if (cdclk == display->cdclk.hw.bypass)
drivers/gpu/drm/i915/display/intel_cdclk.c
1623
if (table[i].refclk == display->cdclk.hw.ref &&
drivers/gpu/drm/i915/display/intel_cdclk.c
1625
return display->cdclk.hw.ref * table[i].ratio;
drivers/gpu/drm/i915/display/intel_cdclk.c
1627
drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
1628
cdclk, display->cdclk.hw.ref);
drivers/gpu/drm/i915/display/intel_cdclk.c
163
void (*set_cdclk)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
170
void intel_cdclk_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1720
static void icl_readout_refclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1723
u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
173
display->cdclk.funcs->get_cdclk(display, cdclk_config);
drivers/gpu/drm/i915/display/intel_cdclk.c
1741
static void bxt_de_pll_readout(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1746
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_cdclk.c
1748
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_cdclk.c
1749
icl_readout_refclk(display, cdclk_config);
drivers/gpu/drm/i915/display/intel_cdclk.c
1753
val = intel_de_read(display, BXT_DE_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_cdclk.c
176
static void intel_cdclk_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1768
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_cdclk.c
1771
ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
1776
static void bxt_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1783
bxt_de_pll_readout(display, cdclk_config);
drivers/gpu/drm/i915/display/intel_cdclk.c
1785
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_cdclk.c
1787
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_cdclk.c
1797
divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
180
display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
1817
if (HAS_CDCLK_SQUASH(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
1818
squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
1834
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_cdclk.c
1835
cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
drivers/gpu/drm/i915/display/intel_cdclk.c
1841
intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
1844
static void bxt_de_pll_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
1846
intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_cdclk.c
1849
if (intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
185
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
1851
drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1853
display->cdclk.hw.vco = 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
1856
static void bxt_de_pll_enable(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1858
int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
drivers/gpu/drm/i915/display/intel_cdclk.c
1860
intel_de_rmw(display, BXT_DE_PLL_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
1863
intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_cdclk.c
1866
if (intel_de_wait_for_set_ms(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1868
drm_err(display->drm, "timeout waiting for DE PLL lock\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
187
return display->cdclk.funcs->modeset_calc_cdclk(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
1870
display->cdclk.hw.vco = vco;
drivers/gpu/drm/i915/display/intel_cdclk.c
1873
static void icl_cdclk_pll_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
1886
if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614))
drivers/gpu/drm/i915/display/intel_cdclk.c
1887
intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK);
drivers/gpu/drm/i915/display/intel_cdclk.c
1889
intel_de_rmw(display, BXT_DE_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_cdclk.c
1893
if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drivers/gpu/drm/i915/display/intel_cdclk.c
1894
drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1896
display->cdclk.hw.vco = 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
1899
static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
190
static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1901
int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
drivers/gpu/drm/i915/display/intel_cdclk.c
1905
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
1908
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
1911
if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drivers/gpu/drm/i915/display/intel_cdclk.c
1912
drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1914
display->cdclk.hw.vco = vco;
drivers/gpu/drm/i915/display/intel_cdclk.c
1917
static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
1919
int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
drivers/gpu/drm/i915/display/intel_cdclk.c
1924
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
1928
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
193
return display->cdclk.funcs->calc_voltage_level(cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
1931
if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_cdclk.c
1933
drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
1936
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
1938
display->cdclk.hw.vco = vco;
drivers/gpu/drm/i915/display/intel_cdclk.c
1941
static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_cdclk.c
1943
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_cdclk.c
1948
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_cdclk.c
196
static void fixed_133mhz_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1961
static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
1969
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
1970
cdclk != display->cdclk.hw.bypass);
drivers/gpu/drm/i915/display/intel_cdclk.c
1971
drm_WARN_ON(display->drm, vco != 0);
drivers/gpu/drm/i915/display/intel_cdclk.c
1991
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_cdclk.c
1992
drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1);
drivers/gpu/drm/i915/display/intel_cdclk.c
1997
static u16 cdclk_squash_waveform(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2000
const struct intel_cdclk_vals *table = display->cdclk.table;
drivers/gpu/drm/i915/display/intel_cdclk.c
2003
if (cdclk == display->cdclk.hw.bypass)
drivers/gpu/drm/i915/display/intel_cdclk.c
2007
if (table[i].refclk == display->cdclk.hw.ref &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2011
drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
2012
cdclk, display->cdclk.hw.ref);
drivers/gpu/drm/i915/display/intel_cdclk.c
2017
static void icl_cdclk_pll_update(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2019
if (display->cdclk.hw.vco != 0 &&
drivers/gpu/drm/i915/display/intel_cdclk.c
202
static void fixed_200mhz_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2020
display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2021
icl_cdclk_pll_disable(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2023
if (display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2024
icl_cdclk_pll_enable(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
2027
static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2029
if (display->cdclk.hw.vco != 0 &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2030
display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2031
bxt_de_pll_disable(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2033
if (display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2034
bxt_de_pll_enable(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
2037
static void dg2_cdclk_squash_program(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2046
intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
drivers/gpu/drm/i915/display/intel_cdclk.c
2059
static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2061
return DISPLAY_VER(display) >= 20;
drivers/gpu/drm/i915/display/intel_cdclk.c
2064
static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2066
if (mdclk_source_is_cdclk_pll(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2072
int intel_mdclk_cdclk_ratio(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2075
if (mdclk_source_is_cdclk_pll(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
208
static void fixed_266mhz_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2082
static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2085
intel_dbuf_mdclk_cdclk_ratio_update(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2086
intel_mdclk_cdclk_ratio(display, cdclk_config),
drivers/gpu/drm/i915/display/intel_cdclk.c
2090
static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2103
if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2106
old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2107
new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2124
if (drm_WARN_ON(display->drm, old_div != new_div))
drivers/gpu/drm/i915/display/intel_cdclk.c
214
static void fixed_333mhz_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2153
drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
drivers/gpu/drm/i915/display/intel_cdclk.c
2155
drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
drivers/gpu/drm/i915/display/intel_cdclk.c
2156
display->cdclk.max_cdclk_freq);
drivers/gpu/drm/i915/display/intel_cdclk.c
2157
drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
drivers/gpu/drm/i915/display/intel_cdclk.c
2163
static bool pll_enable_wa_needed(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2165
return (DISPLAY_VERx100(display) == 2000 ||
drivers/gpu/drm/i915/display/intel_cdclk.c
2166
DISPLAY_VERx100(display) == 1400 ||
drivers/gpu/drm/i915/display/intel_cdclk.c
2167
display->platform.dg2) &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2168
display->cdclk.hw.vco > 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
2171
static u32 bxt_cdclk_ctl(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2180
waveform = cdclk_squash_waveform(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2182
val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform);
drivers/gpu/drm/i915/display/intel_cdclk.c
2184
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/intel_cdclk.c
2185
val |= bxt_cdclk_cd2x_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
2191
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2195
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_cdclk.c
220
static void fixed_400mhz_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2202
if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614) &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2206
val |= xe2lpd_mdclk_source_sel(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2214
static void _bxt_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2221
if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2222
!cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2223
if (display->cdclk.hw.vco != vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2224
adlp_cdclk_pll_crawl(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
2225
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2227
if (pll_enable_wa_needed(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2228
dg2_cdclk_squash_program(display, 0);
drivers/gpu/drm/i915/display/intel_cdclk.c
2230
icl_cdclk_pll_update(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
2232
bxt_cdclk_pll_update(display, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
2235
if (HAS_CDCLK_SQUASH(display)) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2236
u16 waveform = cdclk_squash_waveform(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2238
dg2_cdclk_squash_program(display, waveform);
drivers/gpu/drm/i915/display/intel_cdclk.c
2241
intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
drivers/gpu/drm/i915/display/intel_cdclk.c
2244
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
drivers/gpu/drm/i915/display/intel_cdclk.c
2247
static void bxt_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
226
static void fixed_450mhz_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2261
if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
drivers/gpu/drm/i915/display/intel_cdclk.c
2263
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_cdclk.c
2264
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
2273
ret = intel_parent_pcode_write_timeout(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2278
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
2284
if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
2285
xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
drivers/gpu/drm/i915/display/intel_cdclk.c
2287
if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
drivers/gpu/drm/i915/display/intel_cdclk.c
2289
_bxt_set_cdclk(display, &mid_cdclk_config, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
2290
_bxt_set_cdclk(display, cdclk_config, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
2292
_bxt_set_cdclk(display, cdclk_config, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
2295
if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
2296
xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
drivers/gpu/drm/i915/display/intel_cdclk.c
2298
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_cdclk.c
2303
else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
drivers/gpu/drm/i915/display/intel_cdclk.c
2304
ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
2306
if (DISPLAY_VER(display) < 11) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2313
ret = intel_parent_pcode_write_timeout(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2318
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
232
static void i85x_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2324
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2326
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_cdclk.c
2331
display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
drivers/gpu/drm/i915/display/intel_cdclk.c
2334
static void bxt_sanitize_cdclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2339
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2340
intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
drivers/gpu/drm/i915/display/intel_cdclk.c
2342
if (display->cdclk.hw.vco == 0 ||
drivers/gpu/drm/i915/display/intel_cdclk.c
2343
display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
drivers/gpu/drm/i915/display/intel_cdclk.c
2347
cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2348
if (cdclk != display->cdclk.hw.cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
235
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
2352
vco = bxt_calc_cdclk_pll_vco(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2353
if (vco != display->cdclk.hw.vco)
drivers/gpu/drm/i915/display/intel_cdclk.c
2361
cdctl = intel_de_read(display, CDCLK_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
2362
expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
2369
cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
2370
cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
2373
if (DISPLAY_VER(display) < 20) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2381
drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
2382
intel_de_read(display, CDCLK_CTL), expected);
drivers/gpu/drm/i915/display/intel_cdclk.c
2384
intel_de_write(display, CDCLK_CTL, expected);
drivers/gpu/drm/i915/display/intel_cdclk.c
2391
drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
2394
display->cdclk.hw.cdclk = 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
2397
display->cdclk.hw.vco = ~0;
drivers/gpu/drm/i915/display/intel_cdclk.c
2400
static void bxt_cdclk_init_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2404
bxt_sanitize_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2406
if (display->cdclk.hw.cdclk != 0 &&
drivers/gpu/drm/i915/display/intel_cdclk.c
2407
display->cdclk.hw.vco != 0)
drivers/gpu/drm/i915/display/intel_cdclk.c
2410
cdclk_config = display->cdclk.hw;
drivers/gpu/drm/i915/display/intel_cdclk.c
2417
cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
drivers/gpu/drm/i915/display/intel_cdclk.c
2418
cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2420
intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2422
bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
2425
static void bxt_cdclk_uninit_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2427
struct intel_cdclk_config cdclk_config = display->cdclk.hw;
drivers/gpu/drm/i915/display/intel_cdclk.c
2432
intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2434
bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_cdclk.c
2446
void intel_cdclk_init_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2448
if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_cdclk.c
2449
bxt_cdclk_init_hw(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2450
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_cdclk.c
2451
skl_cdclk_init_hw(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2461
void intel_cdclk_uninit_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2463
if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_cdclk.c
2464
bxt_cdclk_uninit_hw(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2465
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_cdclk.c
2466
skl_cdclk_uninit_hw(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2469
static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2476
drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
drivers/gpu/drm/i915/display/intel_cdclk.c
2481
if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2484
old_waveform = cdclk_squash_waveform(display, a->cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2485
new_waveform = cdclk_squash_waveform(display, b->cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
2491
static bool intel_cdclk_can_crawl(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2497
if (!HAS_CDCLK_CRAWL(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2513
static bool intel_cdclk_can_squash(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2523
if (!HAS_CDCLK_SQUASH(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2560
static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2565
if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
drivers/gpu/drm/i915/display/intel_cdclk.c
2574
if (HAS_CDCLK_SQUASH(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
2598
void intel_cdclk_dump_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2602
drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
2608
static void intel_pcode_notify(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2618
if (!display->platform.dg2)
drivers/gpu/drm/i915/display/intel_cdclk.c
2629
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
2635
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
2640
static void intel_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2646
if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
drivers/gpu/drm/i915/display/intel_cdclk.c
2649
if (drm_WARN_ON_ONCE(display->drm, !display->cdclk.funcs->set_cdclk))
drivers/gpu/drm/i915/display/intel_cdclk.c
2652
intel_cdclk_dump_config(display, cdclk_config, context);
drivers/gpu/drm/i915/display/intel_cdclk.c
2654
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2660
intel_audio_cdclk_change_pre(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2667
mutex_lock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_cdclk.c
2668
for_each_intel_dp(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2672
&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_cdclk.c
2675
intel_cdclk_set_cdclk(display, cdclk_config, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
2677
for_each_intel_dp(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2682
mutex_unlock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_cdclk.c
2684
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_cdclk.c
2690
intel_audio_cdclk_change_post(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2692
if (drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
2693
intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
drivers/gpu/drm/i915/display/intel_cdclk.c
2695
intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
drivers/gpu/drm/i915/display/intel_cdclk.c
2696
intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
drivers/gpu/drm/i915/display/intel_cdclk.c
2700
static bool dg2_power_well_count(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2703
return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
drivers/gpu/drm/i915/display/intel_cdclk.c
2708
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2718
dg2_power_well_count(display, old_cdclk_state) ==
drivers/gpu/drm/i915/display/intel_cdclk.c
2719
dg2_power_well_count(display, new_cdclk_state))
drivers/gpu/drm/i915/display/intel_cdclk.c
2726
update_pipe_count = dg2_power_well_count(display, new_cdclk_state) >
drivers/gpu/drm/i915/display/intel_cdclk.c
2727
dg2_power_well_count(display, old_cdclk_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
274
static void i915gm_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2745
num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2747
intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
drivers/gpu/drm/i915/display/intel_cdclk.c
2753
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2765
update_pipe_count = dg2_power_well_count(display, new_cdclk_state) <
drivers/gpu/drm/i915/display/intel_cdclk.c
2766
dg2_power_well_count(display, old_cdclk_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
277
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
2782
num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2784
intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
drivers/gpu/drm/i915/display/intel_cdclk.c
2809
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2824
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_cdclk.c
2849
drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
drivers/gpu/drm/i915/display/intel_cdclk.c
2851
intel_set_cdclk(display, &cdclk_config, pipe,
drivers/gpu/drm/i915/display/intel_cdclk.c
2865
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2879
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_cdclk.c
2888
drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
drivers/gpu/drm/i915/display/intel_cdclk.c
2890
intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
drivers/gpu/drm/i915/display/intel_cdclk.c
2895
static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
drivers/gpu/drm/i915/display/intel_cdclk.c
2897
return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
drivers/gpu/drm/i915/display/intel_cdclk.c
2901
static int intel_cdclk_guardband(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
2903
if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_cdclk.c
2904
display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_cdclk.c
2906
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_cdclk.c
2914
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
2915
int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
drivers/gpu/drm/i915/display/intel_cdclk.c
2916
int guardband = intel_cdclk_guardband(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
2929
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_cdclk.c
2933
for_each_intel_plane_on_crtc(display->drm, crtc, plane)
drivers/gpu/drm/i915/display/intel_cdclk.c
2963
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
298
static void i945gm_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
2994
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3008
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
301
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
3041
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3053
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3084
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3091
static bool glk_cdclk_audio_wa_needed(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
3094
return display->platform.geminilake &&
drivers/gpu/drm/i915/display/intel_cdclk.c
3101
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3109
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_cdclk.c
3120
if (glk_cdclk_audio_wa_needed(display, cdclk_state))
drivers/gpu/drm/i915/display/intel_cdclk.c
3123
if (min_cdclk > display->cdclk.max_cdclk_freq) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3124
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3126
min_cdclk, display->cdclk.max_cdclk_freq);
drivers/gpu/drm/i915/display/intel_cdclk.c
3148
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3175
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_cdclk.c
3184
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3193
cdclk = vlv_calc_cdclk(display, min_cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3197
vlv_calc_voltage_level(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3200
cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3204
vlv_calc_voltage_level(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
322
static unsigned int intel_hpll_vco(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3243
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3252
vco = display->cdclk.skl_preferred_vco_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
3314
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3327
cdclk = bxt_calc_cdclk(display, min_cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3328
vco = bxt_calc_cdclk_pll_vco(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3334
intel_cdclk_calc_voltage_level(display, cdclk));
drivers/gpu/drm/i915/display/intel_cdclk.c
3337
cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3338
vco = bxt_calc_cdclk_pll_vco(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3343
intel_cdclk_calc_voltage_level(display, cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3395
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3398
cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
drivers/gpu/drm/i915/display/intel_cdclk.c
3408
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3436
if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) !=
drivers/gpu/drm/i915/display/intel_cdclk.c
3437
glk_cdclk_audio_wa_needed(display, new_cdclk_state))
drivers/gpu/drm/i915/display/intel_cdclk.c
3440
if (dg2_power_well_count(display, old_cdclk_state) !=
drivers/gpu/drm/i915/display/intel_cdclk.c
3441
dg2_power_well_count(display, new_cdclk_state))
drivers/gpu/drm/i915/display/intel_cdclk.c
3488
int intel_cdclk_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3496
intel_atomic_global_obj_init(display, &display->cdclk.obj,
drivers/gpu/drm/i915/display/intel_cdclk.c
3502
static bool intel_cdclk_need_serialize(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
3512
dg2_power_well_count(display, old_cdclk_state) !=
drivers/gpu/drm/i915/display/intel_cdclk.c
3513
dg2_power_well_count(display, new_cdclk_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3518
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3534
if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3552
intel_cdclk_can_cd2x_update(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
3559
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_cdclk.c
3569
if (intel_cdclk_can_crawl_and_squash(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
3572
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3574
} else if (intel_cdclk_can_squash(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
3577
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3579
} else if (intel_cdclk_can_crawl(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
3582
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3587
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3599
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3603
if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
drivers/gpu/drm/i915/display/intel_cdclk.c
3604
intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3605
int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
drivers/gpu/drm/i915/display/intel_cdclk.c
3612
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
3616
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
366
if (display->platform.gm45)
drivers/gpu/drm/i915/display/intel_cdclk.c
3664
void intel_cdclk_update_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3667
to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3669
to_intel_cdclk_state(display->cdclk.obj.state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3675
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_cdclk.c
368
else if (display->platform.g45)
drivers/gpu/drm/i915/display/intel_cdclk.c
3689
cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
3694
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_cdclk.c
3696
intel_cdclk_update_hw_state(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3699
static int intel_compute_max_dotclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
370
else if (display->platform.i965gm)
drivers/gpu/drm/i915/display/intel_cdclk.c
3701
int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
drivers/gpu/drm/i915/display/intel_cdclk.c
3702
int guardband = intel_cdclk_guardband(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3703
int max_cdclk_freq = display->cdclk.max_cdclk_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
3716
void intel_update_max_cdclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3718
if (DISPLAY_VER(display) >= 35) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3719
display->cdclk.max_cdclk_freq = 787200;
drivers/gpu/drm/i915/display/intel_cdclk.c
372
else if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_cdclk.c
3720
} else if (DISPLAY_VERx100(display) >= 3002) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3721
display->cdclk.max_cdclk_freq = 480000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3722
} else if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3723
display->cdclk.max_cdclk_freq = 691200;
drivers/gpu/drm/i915/display/intel_cdclk.c
3724
} else if (display->platform.jasperlake || display->platform.elkhartlake) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3725
if (display->cdclk.hw.ref == 24000)
drivers/gpu/drm/i915/display/intel_cdclk.c
3726
display->cdclk.max_cdclk_freq = 552000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3728
display->cdclk.max_cdclk_freq = 556800;
drivers/gpu/drm/i915/display/intel_cdclk.c
3729
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3730
if (display->cdclk.hw.ref == 24000)
drivers/gpu/drm/i915/display/intel_cdclk.c
3731
display->cdclk.max_cdclk_freq = 648000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3733
display->cdclk.max_cdclk_freq = 652800;
drivers/gpu/drm/i915/display/intel_cdclk.c
3734
} else if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3735
display->cdclk.max_cdclk_freq = 316800;
drivers/gpu/drm/i915/display/intel_cdclk.c
3736
} else if (display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3737
display->cdclk.max_cdclk_freq = 624000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3738
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3739
u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
374
else if (display->platform.g33)
drivers/gpu/drm/i915/display/intel_cdclk.c
3742
vco = display->cdclk.skl_preferred_vco_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
3743
drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
drivers/gpu/drm/i915/display/intel_cdclk.c
3759
display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
3760
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3767
if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
drivers/gpu/drm/i915/display/intel_cdclk.c
3768
display->cdclk.max_cdclk_freq = 450000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3769
else if (display->platform.broadwell_ulx)
drivers/gpu/drm/i915/display/intel_cdclk.c
3770
display->cdclk.max_cdclk_freq = 450000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3771
else if (display->platform.broadwell_ult)
drivers/gpu/drm/i915/display/intel_cdclk.c
3772
display->cdclk.max_cdclk_freq = 540000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3774
display->cdclk.max_cdclk_freq = 675000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3775
} else if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3776
display->cdclk.max_cdclk_freq = 320000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3777
} else if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
3778
display->cdclk.max_cdclk_freq = 400000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3781
display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
drivers/gpu/drm/i915/display/intel_cdclk.c
3784
display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3786
drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
3787
display->cdclk.max_cdclk_freq);
drivers/gpu/drm/i915/display/intel_cdclk.c
3789
drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
379
tmp = intel_mchbar_read(display, display->platform.pineview ||
drivers/gpu/drm/i915/display/intel_cdclk.c
3790
display->cdclk.max_dotclk_freq);
drivers/gpu/drm/i915/display/intel_cdclk.c
3799
void intel_update_cdclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
380
display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
drivers/gpu/drm/i915/display/intel_cdclk.c
3801
intel_cdclk_get_cdclk(display, &display->cdclk.hw);
drivers/gpu/drm/i915/display/intel_cdclk.c
3809
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_cdclk.c
3810
intel_de_write(display, GMBUSFREQ_VLV,
drivers/gpu/drm/i915/display/intel_cdclk.c
3811
DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
drivers/gpu/drm/i915/display/intel_cdclk.c
3814
static int dg1_rawclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3820
intel_de_write(display, PCH_RAWCLK_FREQ,
drivers/gpu/drm/i915/display/intel_cdclk.c
3826
static int cnp_rawclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3831
if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
drivers/gpu/drm/i915/display/intel_cdclk.c
384
drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
drivers/gpu/drm/i915/display/intel_cdclk.c
3847
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_cdclk.c
3851
intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3855
static int pch_rawclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3857
return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3860
static int i9xx_hrawclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3863
return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4);
drivers/gpu/drm/i915/display/intel_cdclk.c
387
drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
drivers/gpu/drm/i915/display/intel_cdclk.c
3873
u32 intel_read_rawclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3877
if (INTEL_PCH_TYPE(display) >= PCH_MTL)
drivers/gpu/drm/i915/display/intel_cdclk.c
3884
else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
drivers/gpu/drm/i915/display/intel_cdclk.c
3885
freq = dg1_rawclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3886
else if (INTEL_PCH_TYPE(display) >= PCH_CNP)
drivers/gpu/drm/i915/display/intel_cdclk.c
3887
freq = cnp_rawclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3888
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_cdclk.c
3889
freq = pch_rawclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3890
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_cdclk.c
3891
freq = vlv_clock_get_hrawclk(display->drm);
drivers/gpu/drm/i915/display/intel_cdclk.c
3892
else if (DISPLAY_VER(display) >= 3)
drivers/gpu/drm/i915/display/intel_cdclk.c
3893
freq = i9xx_hrawclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
3903
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_cdclk.c
3905
seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
3906
seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
drivers/gpu/drm/i915/display/intel_cdclk.c
3907
seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
drivers/gpu/drm/i915/display/intel_cdclk.c
3914
void intel_cdclk_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
3916
debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,
drivers/gpu/drm/i915/display/intel_cdclk.c
3917
display, &i915_cdclk_info_fops);
drivers/gpu/drm/i915/display/intel_cdclk.c
392
static void g33_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
395
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
404
cdclk_config->vco = intel_hpll_vco(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
4067
void intel_init_cdclk_hooks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
4069
if (DISPLAY_VER(display) >= 35) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4070
display->cdclk.funcs = &xe3lpd_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4071
display->cdclk.table = xe3p_lpd_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4072
} else if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4073
display->cdclk.funcs = &xe3lpd_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4074
display->cdclk.table = xe3lpd_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4075
} else if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4076
display->cdclk.funcs = &rplu_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4077
display->cdclk.table = xe2lpd_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4078
} else if (DISPLAY_VERx100(display) >= 1401) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4079
display->cdclk.funcs = &rplu_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4080
display->cdclk.table = xe2hpd_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4081
} else if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4082
display->cdclk.funcs = &rplu_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4083
display->cdclk.table = mtl_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4084
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4085
display->cdclk.funcs = &tgl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4086
display->cdclk.table = dg2_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4087
} else if (display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4089
if (intel_display_wa(display, INTEL_DISPLAY_WA_22011320316)) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4090
display->cdclk.table = adlp_a_step_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4091
display->cdclk.funcs = &tgl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4092
} else if (display->platform.alderlake_p_raptorlake_u) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4093
display->cdclk.table = rplu_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4094
display->cdclk.funcs = &rplu_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4096
display->cdclk.table = adlp_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4097
display->cdclk.funcs = &tgl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4099
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4100
display->cdclk.funcs = &tgl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4101
display->cdclk.table = rkl_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4102
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4103
display->cdclk.funcs = &tgl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4104
display->cdclk.table = icl_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4105
} else if (display->platform.jasperlake || display->platform.elkhartlake) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4106
display->cdclk.funcs = &ehl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4107
display->cdclk.table = icl_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4108
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4109
display->cdclk.funcs = &icl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4110
display->cdclk.table = icl_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4111
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4112
display->cdclk.funcs = &bxt_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4113
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_cdclk.c
4114
display->cdclk.table = glk_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4116
display->cdclk.table = bxt_cdclk_table;
drivers/gpu/drm/i915/display/intel_cdclk.c
4117
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4118
display->cdclk.funcs = &skl_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4119
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4120
display->cdclk.funcs = &bdw_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4121
} else if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4122
display->cdclk.funcs = &hsw_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4123
} else if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4124
display->cdclk.funcs = &chv_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4125
} else if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4126
display->cdclk.funcs = &vlv_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4127
} else if (display->platform.sandybridge || display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4128
display->cdclk.funcs = &fixed_400mhz_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4129
} else if (display->platform.ironlake) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4130
display->cdclk.funcs = &ilk_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4131
} else if (display->platform.gm45) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4132
display->cdclk.funcs = &gm45_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4133
} else if (display->platform.g45) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4134
display->cdclk.funcs = &g33_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4135
} else if (display->platform.i965gm) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4136
display->cdclk.funcs = &i965gm_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4137
} else if (display->platform.i965g) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4138
display->cdclk.funcs = &fixed_400mhz_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4139
} else if (display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4140
display->cdclk.funcs = &pnv_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4141
} else if (display->platform.g33) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4142
display->cdclk.funcs = &g33_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4143
} else if (display->platform.i945gm) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4144
display->cdclk.funcs = &i945gm_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4145
} else if (display->platform.i945g) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4146
display->cdclk.funcs = &fixed_400mhz_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4147
} else if (display->platform.i915gm) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4148
display->cdclk.funcs = &i915gm_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4149
} else if (display->platform.i915g) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4150
display->cdclk.funcs = &i915g_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4151
} else if (display->platform.i865g) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4152
display->cdclk.funcs = &i865g_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4153
} else if (display->platform.i85x) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4154
display->cdclk.funcs = &i85x_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4155
} else if (display->platform.i845g) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4156
display->cdclk.funcs = &i845g_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4157
} else if (display->platform.i830) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4158
display->cdclk.funcs = &i830_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4161
if (drm_WARN(display->drm, !display->cdclk.funcs,
drivers/gpu/drm/i915/display/intel_cdclk.c
4163
display->cdclk.funcs = &i830_cdclk_funcs;
drivers/gpu/drm/i915/display/intel_cdclk.c
4206
void intel_cdclk_read_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
4210
cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
drivers/gpu/drm/i915/display/intel_cdclk.c
4212
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
4213
intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
drivers/gpu/drm/i915/display/intel_cdclk.c
4214
cdclk_state->actual = display->cdclk.hw;
drivers/gpu/drm/i915/display/intel_cdclk.c
4215
cdclk_state->logical = display->cdclk.hw;
drivers/gpu/drm/i915/display/intel_cdclk.c
4220
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
4222
if (DISPLAY_VER(display) >= 10 || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4223
return bxt_calc_cdclk(display, min_cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
4224
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4227
vco = display->cdclk.skl_preferred_vco_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
4232
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4234
} else if (display->platform.cherryview || display->platform.valleyview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
4235
return vlv_calc_cdclk(display, min_cdclk);
drivers/gpu/drm/i915/display/intel_cdclk.c
4237
return display->cdclk.max_cdclk_freq;
drivers/gpu/drm/i915/display/intel_cdclk.c
4244
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
4245
int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
drivers/gpu/drm/i915/display/intel_cdclk.c
4282
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cdclk.c
4284
int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
drivers/gpu/drm/i915/display/intel_cdclk.c
435
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
441
static void pnv_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
444
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
463
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
475
static void i965gm_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
478
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
486
cdclk_config->vco = intel_hpll_vco(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
514
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
520
static void gm45_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
523
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_cdclk.c
527
cdclk_config->vco = intel_hpll_vco(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
543
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
551
static void hsw_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
554
u32 lcpll = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
559
else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
drivers/gpu/drm/i915/display/intel_cdclk.c
563
else if (display->platform.haswell_ult)
drivers/gpu/drm/i915/display/intel_cdclk.c
569
static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
571
int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ?
drivers/gpu/drm/i915/display/intel_cdclk.c
579
if (display->platform.valleyview && min_cdclk > freq_320)
drivers/gpu/drm/i915/display/intel_cdclk.c
589
static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
drivers/gpu/drm/i915/display/intel_cdclk.c
591
if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/intel_cdclk.c
604
return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1;
drivers/gpu/drm/i915/display/intel_cdclk.c
608
static void vlv_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
613
cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm);
drivers/gpu/drm/i915/display/intel_cdclk.c
614
cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm);
drivers/gpu/drm/i915/display/intel_cdclk.c
616
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
617
val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);
drivers/gpu/drm/i915/display/intel_cdclk.c
618
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
620
if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_cdclk.c
628
static void vlv_program_pfi_credits(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cdclk.c
632
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_cdclk.c
637
if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) {
drivers/gpu/drm/i915/display/intel_cdclk.c
639
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_cdclk.c
651
intel_de_write(display, GCI_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
654
intel_de_write(display, GCI_CONTROL,
drivers/gpu/drm/i915/display/intel_cdclk.c
661
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
662
intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
drivers/gpu/drm/i915/display/intel_cdclk.c
665
static void vlv_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
692
wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
drivers/gpu/drm/i915/display/intel_cdclk.c
694
intel_parent_vlv_iosf_get(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
699
val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);
drivers/gpu/drm/i915/display/intel_cdclk.c
702
vlv_punit_write(display, PUNIT_REG_DSPSSPM, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
704
ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM),
drivers/gpu/drm/i915/display/intel_cdclk.c
708
drm_err(display->drm, "timed out waiting for CDCLK change\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
713
divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1,
drivers/gpu/drm/i915/display/intel_cdclk.c
717
val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL);
drivers/gpu/drm/i915/display/intel_cdclk.c
720
vlv_cck_write(display, CCK_DISPLAY_CLOCK_CONTROL, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
722
ret = poll_timeout_us(val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL),
drivers/gpu/drm/i915/display/intel_cdclk.c
726
drm_err(display->drm, "timed out waiting for CDCLK change\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
730
val = vlv_bunit_read(display, BUNIT_REG_BISOC);
drivers/gpu/drm/i915/display/intel_cdclk.c
741
vlv_bunit_write(display, BUNIT_REG_BISOC, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
743
intel_parent_vlv_iosf_put(display,
drivers/gpu/drm/i915/display/intel_cdclk.c
748
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
750
vlv_program_pfi_credits(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
752
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_cdclk.c
755
static void chv_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
781
wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
drivers/gpu/drm/i915/display/intel_cdclk.c
783
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
784
val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);
drivers/gpu/drm/i915/display/intel_cdclk.c
787
vlv_punit_write(display, PUNIT_REG_DSPSSPM, val);
drivers/gpu/drm/i915/display/intel_cdclk.c
789
ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM),
drivers/gpu/drm/i915/display/intel_cdclk.c
793
drm_err(display->drm, "timed out waiting for CDCLK change\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
795
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
797
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
799
vlv_program_pfi_credits(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
801
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_cdclk.c
831
static void bdw_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
834
u32 lcpll = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
839
else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
drivers/gpu/drm/i915/display/intel_cdclk.c
875
static void bdw_set_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
882
if (drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
883
(intel_de_read(display, LCPLL_CTL) &
drivers/gpu/drm/i915/display/intel_cdclk.c
891
ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
drivers/gpu/drm/i915/display/intel_cdclk.c
893
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.c
898
intel_de_rmw(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
905
ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
908
drm_err(display->drm, "Switching to FCLK failed\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
910
intel_de_rmw(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
913
intel_de_rmw(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
916
ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_cdclk.c
919
drm_err(display->drm, "Switching back to LCPLL failed\n");
drivers/gpu/drm/i915/display/intel_cdclk.c
921
intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
drivers/gpu/drm/i915/display/intel_cdclk.c
924
intel_de_write(display, CDCLK_FREQ,
drivers/gpu/drm/i915/display/intel_cdclk.c
927
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_cdclk.c
965
static void skl_dpll0_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.c
973
val = intel_de_read(display, LCPLL1_CTL);
drivers/gpu/drm/i915/display/intel_cdclk.c
977
if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
drivers/gpu/drm/i915/display/intel_cdclk.c
980
val = intel_de_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_cdclk.c
982
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_cdclk.h
25
void intel_cdclk_init_hw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
26
void intel_cdclk_uninit_hw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
27
void intel_init_cdclk_hooks(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
28
void intel_update_max_cdclk(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
29
void intel_update_cdclk(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
30
u32 intel_read_rawclk(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
33
int intel_mdclk_cdclk_ratio(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.h
38
void intel_cdclk_dump_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.h
41
void intel_cdclk_get_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cdclk.h
47
void intel_cdclk_update_hw_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
61
int intel_cdclk_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
62
void intel_cdclk_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cdclk.h
70
void intel_cdclk_read_hw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cmtg.c
101
static void intel_cmtg_get_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cmtg.c
106
val = intel_de_read(display, TRANS_CMTG_CTL_A);
drivers/gpu/drm/i915/display/intel_cmtg.c
109
if (intel_cmtg_has_cmtg_b(display)) {
drivers/gpu/drm/i915/display/intel_cmtg.c
110
val = intel_de_read(display, TRANS_CMTG_CTL_B);
drivers/gpu/drm/i915/display/intel_cmtg.c
114
cmtg_config->trans_a_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_A);
drivers/gpu/drm/i915/display/intel_cmtg.c
115
cmtg_config->trans_b_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_B);
drivers/gpu/drm/i915/display/intel_cmtg.c
118
static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cmtg.c
121
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_cmtg.c
127
static void intel_cmtg_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cmtg.c
134
intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A),
drivers/gpu/drm/i915/display/intel_cmtg.c
138
intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B),
drivers/gpu/drm/i915/display/intel_cmtg.c
142
drm_dbg_kms(display->drm, "Disabling CMTG A\n");
drivers/gpu/drm/i915/display/intel_cmtg.c
143
intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_cmtg.c
149
drm_dbg_kms(display->drm, "Disabling CMTG B\n");
drivers/gpu/drm/i915/display/intel_cmtg.c
150
intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_cmtg.c
155
if (intel_cmtg_has_clock_sel(display) && clk_sel_clr)
drivers/gpu/drm/i915/display/intel_cmtg.c
156
intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
drivers/gpu/drm/i915/display/intel_cmtg.c
167
void intel_cmtg_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cmtg.c
171
if (!HAS_CMTG(display))
drivers/gpu/drm/i915/display/intel_cmtg.c
174
intel_cmtg_get_config(display, &cmtg_config);
drivers/gpu/drm/i915/display/intel_cmtg.c
175
intel_cmtg_dump_config(display, &cmtg_config);
drivers/gpu/drm/i915/display/intel_cmtg.c
183
if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
drivers/gpu/drm/i915/display/intel_cmtg.c
186
intel_cmtg_disable(display, &cmtg_config);
drivers/gpu/drm/i915/display/intel_cmtg.c
63
static bool intel_cmtg_has_cmtg_b(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cmtg.c
65
return DISPLAY_VER(display) >= 20;
drivers/gpu/drm/i915/display/intel_cmtg.c
68
static bool intel_cmtg_has_clock_sel(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cmtg.c
70
return DISPLAY_VER(display) >= 14;
drivers/gpu/drm/i915/display/intel_cmtg.c
73
static void intel_cmtg_dump_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cmtg.c
76
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cmtg.c
79
intel_cmtg_has_cmtg_b(display) ? str_enabled_disabled(cmtg_config->cmtg_b_enable) : "n/a",
drivers/gpu/drm/i915/display/intel_cmtg.c
84
static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cmtg.c
90
if (!HAS_TRANSCODER(display, trans))
drivers/gpu/drm/i915/display/intel_cmtg.c
95
with_intel_display_power_if_enabled(display, power_domain)
drivers/gpu/drm/i915/display/intel_cmtg.c
96
val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));
drivers/gpu/drm/i915/display/intel_cmtg.h
11
void intel_cmtg_sanitize(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_color.c
1038
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1043
intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),
drivers/gpu/drm/i915/display/intel_color.c
1051
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1053
intel_de_write(display, GAMMA_MODE(crtc->pipe),
drivers/gpu/drm/i915/display/intel_color.c
1056
intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),
drivers/gpu/drm/i915/display/intel_color.c
1062
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1064
return intel_de_read(display, GAMMA_MODE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
1069
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1071
return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
1076
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1082
tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));
drivers/gpu/drm/i915/display/intel_color.c
1087
if (!HAS_GMCH(display) && tmp & DISP_PIPE_CSC_ENABLE)
drivers/gpu/drm/i915/display/intel_color.c
1103
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1110
color = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
1111
if (DISPLAY_VER(display) < 35) {
drivers/gpu/drm/i915/display/intel_color.c
1141
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1153
intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), val);
drivers/gpu/drm/i915/display/intel_color.c
1155
intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
drivers/gpu/drm/i915/display/intel_color.c
1157
intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
drivers/gpu/drm/i915/display/intel_color.c
1163
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1167
intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), crtc_state->hw.background_color);
drivers/gpu/drm/i915/display/intel_color.c
1169
intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
drivers/gpu/drm/i915/display/intel_color.c
1171
intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
drivers/gpu/drm/i915/display/intel_color.c
1176
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1193
intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
1197
create_linear_lut(struct intel_display *display, int lut_size)
drivers/gpu/drm/i915/display/intel_color.c
1203
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
1231
create_resized_lut(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_color.c
1240
blob_out = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
1268
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1279
intel_de_write_fw(display, PALETTE(display, pipe, i),
drivers/gpu/drm/i915/display/intel_color.c
1286
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1292
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
1293
PALETTE(display, pipe, 2 * i + 0),
drivers/gpu/drm/i915/display/intel_color.c
1295
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
1296
PALETTE(display, pipe, 2 * i + 1),
drivers/gpu/drm/i915/display/intel_color.c
1322
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1328
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
1329
PALETTE(display, pipe, 2 * i + 0),
drivers/gpu/drm/i915/display/intel_color.c
1331
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
1332
PALETTE(display, pipe, 2 * i + 1),
drivers/gpu/drm/i915/display/intel_color.c
1336
intel_de_write_fw(display, PIPEGCMAX(display, pipe, 0), lut[i].red);
drivers/gpu/drm/i915/display/intel_color.c
1337
intel_de_write_fw(display, PIPEGCMAX(display, pipe, 1), lut[i].green);
drivers/gpu/drm/i915/display/intel_color.c
1338
intel_de_write_fw(display, PIPEGCMAX(display, pipe, 2), lut[i].blue);
drivers/gpu/drm/i915/display/intel_color.c
1362
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1367
intel_de_write_fw(display, reg, val);
drivers/gpu/drm/i915/display/intel_color.c
1373
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1378
intel_de_write_fw(display, reg, val);
drivers/gpu/drm/i915/display/intel_color.c
1595
static int glk_degamma_lut_size(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_color.c
1597
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_color.c
1629
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1661
DISPLAY_VER(display) >= 14 ?
drivers/gpu/drm/i915/display/intel_color.c
1666
while (i++ < glk_degamma_lut_size(display))
drivers/gpu/drm/i915/display/intel_color.c
1668
DISPLAY_VER(display) >= 14 ?
drivers/gpu/drm/i915/display/intel_color.c
1869
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1875
intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0),
drivers/gpu/drm/i915/display/intel_color.c
1877
intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1),
drivers/gpu/drm/i915/display/intel_color.c
1903
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
1909
intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 0),
drivers/gpu/drm/i915/display/intel_color.c
1911
intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 1),
drivers/gpu/drm/i915/display/intel_color.c
1918
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1934
intel_de_write_fw(display, CGM_PIPE_MODE(crtc->pipe),
drivers/gpu/drm/i915/display/intel_color.c
1940
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1945
display->color.funcs->load_luts(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1951
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1953
if (display->color.funcs->color_commit_noarm)
drivers/gpu/drm/i915/display/intel_color.c
1954
display->color.funcs->color_commit_noarm(dsb, crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1960
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1962
display->color.funcs->color_commit_arm(dsb, crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1967
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1969
if (display->color.funcs->color_post_update)
drivers/gpu/drm/i915/display/intel_color.c
1970
display->color.funcs->color_post_update(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1975
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1981
if (DISPLAY_VER(display) < 9) {
drivers/gpu/drm/i915/display/intel_color.c
1997
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
1999
return crtc_state->dsb_color && !HAS_DOUBLE_BUFFERED_LUT(display);
drivers/gpu/drm/i915/display/intel_color.c
2004
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2006
return crtc_state->dsb_color && HAS_DOUBLE_BUFFERED_LUT(display);
drivers/gpu/drm/i915/display/intel_color.c
2012
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
2026
if (HAS_DOUBLE_BUFFERED_LUT(display))
drivers/gpu/drm/i915/display/intel_color.c
2034
display->color.funcs->load_luts(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2066
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
2070
if (HAS_DOUBLE_BUFFERED_LUT(display))
drivers/gpu/drm/i915/display/intel_color.c
2109
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
2124
drm_dbg_kms(display->drm, "New background not completely opaque\n");
drivers/gpu/drm/i915/display/intel_color.c
2131
return display->color.funcs->color_check(state, crtc);
drivers/gpu/drm/i915/display/intel_color.c
2136
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2138
display->color.funcs->get_config(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2140
display->color.funcs->read_luts(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2142
if (display->color.funcs->read_csc)
drivers/gpu/drm/i915/display/intel_color.c
2143
display->color.funcs->read_csc(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2151
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2160
return display->color.funcs->lut_equal(crtc_state, blob1, blob2,
drivers/gpu/drm/i915/display/intel_color.c
2167
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_color.c
2175
(DISPLAY_VER(display) < 9 && plane->id == PLANE_PRIMARY);
drivers/gpu/drm/i915/display/intel_color.c
2182
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
2197
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_color.c
2212
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_color.c
2221
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2227
return DISPLAY_INFO(display)->color.gamma_lut_tests;
drivers/gpu/drm/i915/display/intel_color.c
2232
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2234
return DISPLAY_INFO(display)->color.degamma_lut_tests;
drivers/gpu/drm/i915/display/intel_color.c
2239
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2245
return DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
2250
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2252
return DISPLAY_INFO(display)->color.degamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
2258
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
2266
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2278
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
228
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_color.c
2286
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
231
intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_HI(pipe),
drivers/gpu/drm/i915/display/intel_color.c
233
intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_ME(pipe),
drivers/gpu/drm/i915/display/intel_color.c
2331
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
2340
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
235
intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_LO(pipe),
drivers/gpu/drm/i915/display/intel_color.c
2351
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2354
if (DISPLAY_VER(display) >= 11 || HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/intel_color.c
2355
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2357
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2359
} else if (DISPLAY_VER(display) == 10) {
drivers/gpu/drm/i915/display/intel_color.c
2360
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2363
crtc_state->pre_csc_lut != display->color.glk_linear_degamma_lut);
drivers/gpu/drm/i915/display/intel_color.c
2364
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2369
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2372
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
238
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RY_GY(pipe),
drivers/gpu/drm/i915/display/intel_color.c
2390
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
240
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BY(pipe),
drivers/gpu/drm/i915/display/intel_color.c
2405
if (DISPLAY_VER(display) < 4 &&
drivers/gpu/drm/i915/display/intel_color.c
243
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RU_GU(pipe),
drivers/gpu/drm/i915/display/intel_color.c
245
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BU(pipe),
drivers/gpu/drm/i915/display/intel_color.c
248
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RV_GV(pipe),
drivers/gpu/drm/i915/display/intel_color.c
250
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BV(pipe),
drivers/gpu/drm/i915/display/intel_color.c
253
if (DISPLAY_VER(display) < 7)
drivers/gpu/drm/i915/display/intel_color.c
256
intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_HI(pipe),
drivers/gpu/drm/i915/display/intel_color.c
2574
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2579
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
drivers/gpu/drm/i915/display/intel_color.c
258
intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_ME(pipe),
drivers/gpu/drm/i915/display/intel_color.c
260
intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_LO(pipe),
drivers/gpu/drm/i915/display/intel_color.c
2613
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
2623
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2631
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
267
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
2686
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2692
drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
drivers/gpu/drm/i915/display/intel_color.c
2693
drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
drivers/gpu/drm/i915/display/intel_color.c
2695
degamma_lut = create_resized_lut(display, crtc_state->hw.degamma_lut, 512,
drivers/gpu/drm/i915/display/intel_color.c
2700
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut, 512,
drivers/gpu/drm/i915/display/intel_color.c
271
csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2719
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
272
csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_PREOFF_ME(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2729
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
273
csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_PREOFF_LO(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2737
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
2745
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
275
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));
drivers/gpu/drm/i915/display/intel_color.c
278
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2792
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
2797
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
drivers/gpu/drm/i915/display/intel_color.c
2798
DISPLAY_INFO(display)->color.degamma_lut_size,
drivers/gpu/drm/i915/display/intel_color.c
281
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2814
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
drivers/gpu/drm/i915/display/intel_color.c
2837
display->color.glk_linear_degamma_lut);
drivers/gpu/drm/i915/display/intel_color.c
284
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2856
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_color.c
2867
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
287
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2875
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
290
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));
drivers/gpu/drm/i915/display/intel_color.c
2914
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
293
if (DISPLAY_VER(display) < 7)
drivers/gpu/drm/i915/display/intel_color.c
2932
else if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_color.c
296
csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_HI(pipe));
drivers/gpu/drm/i915/display/intel_color.c
297
csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_ME(pipe));
drivers/gpu/drm/i915/display/intel_color.c
298
csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_LO(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3313
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3319
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3328
u32 val = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
3329
PALETTE(display, pipe, i));
drivers/gpu/drm/i915/display/intel_color.c
3339
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
334
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_color.c
3340
u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
3347
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3355
ldw = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
3356
PALETTE(display, pipe, 2 * i + 0));
drivers/gpu/drm/i915/display/intel_color.c
3357
udw = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
3358
PALETTE(display, pipe, 2 * i + 1));
drivers/gpu/drm/i915/display/intel_color.c
337
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_HI(pipe),
drivers/gpu/drm/i915/display/intel_color.c
339
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_ME(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3390
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3391
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
3396
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3405
u32 ldw = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
3406
PALETTE(display, pipe, 2 * i + 0));
drivers/gpu/drm/i915/display/intel_color.c
3407
u32 udw = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_color.c
3408
PALETTE(display, pipe, 2 * i + 1));
drivers/gpu/drm/i915/display/intel_color.c
341
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_LO(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3413
lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 0)));
drivers/gpu/drm/i915/display/intel_color.c
3414
lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 1)));
drivers/gpu/drm/i915/display/intel_color.c
3415
lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 2)));
drivers/gpu/drm/i915/display/intel_color.c
344
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3442
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3443
int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
3448
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3457
u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));
drivers/gpu/drm/i915/display/intel_color.c
3458
u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));
drivers/gpu/drm/i915/display/intel_color.c
346
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3468
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3469
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
3474
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3483
u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));
drivers/gpu/drm/i915/display/intel_color.c
3484
u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));
drivers/gpu/drm/i915/display/intel_color.c
349
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3494
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
3497
crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_color.c
351
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3517
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3523
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3532
u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));
drivers/gpu/drm/i915/display/intel_color.c
354
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3542
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3543
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
3548
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3557
u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));
drivers/gpu/drm/i915/display/intel_color.c
356
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
drivers/gpu/drm/i915/display/intel_color.c
359
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3605
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
361
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3611
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3622
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3624
val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3629
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
363
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3670
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3676
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
3684
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3686
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3691
u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3696
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
370
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3735
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3736
int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
374
csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3741
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
375
csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3754
intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3756
intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
376
csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3761
u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3763
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_color.c
3769
intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
378
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3801
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
3802
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
3807
blob = drm_property_create_blob(display->drm,
drivers/gpu/drm/i915/display/intel_color.c
381
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3815
intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3817
intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
3822
u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3823
u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3828
intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),
drivers/gpu/drm/i915/display/intel_color.c
384
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
drivers/gpu/drm/i915/display/intel_color.c
387
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3870
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
3880
if (!icl_is_hdr_plane(display, plane) || !blob)
drivers/gpu/drm/i915/display/intel_color.c
390
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3928
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 0),
drivers/gpu/drm/i915/display/intel_color.c
393
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3930
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 1),
drivers/gpu/drm/i915/display/intel_color.c
3933
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 2),
drivers/gpu/drm/i915/display/intel_color.c
3935
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 3),
drivers/gpu/drm/i915/display/intel_color.c
3938
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 4),
drivers/gpu/drm/i915/display/intel_color.c
3940
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane, 5),
drivers/gpu/drm/i915/display/intel_color.c
3943
intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
drivers/gpu/drm/i915/display/intel_color.c
3944
intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
drivers/gpu/drm/i915/display/intel_color.c
3945
intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
drivers/gpu/drm/i915/display/intel_color.c
3950
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
3953
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
3956
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
396
csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3965
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
397
csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3972
if (icl_is_hdr_plane(display, plane)) {
drivers/gpu/drm/i915/display/intel_color.c
3975
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
398
csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));
drivers/gpu/drm/i915/display/intel_color.c
3983
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
3991
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
3999
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4004
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4010
intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
drivers/gpu/drm/i915/display/intel_color.c
4018
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
4025
if (icl_is_hdr_plane(display, plane)) {
drivers/gpu/drm/i915/display/intel_color.c
4026
intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),
drivers/gpu/drm/i915/display/intel_color.c
4029
intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),
drivers/gpu/drm/i915/display/intel_color.c
4036
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4043
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4053
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4058
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4064
intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
drivers/gpu/drm/i915/display/intel_color.c
4065
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_color.c
4091
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_color.c
4096
if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
drivers/gpu/drm/i915/display/intel_color.c
4097
drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
drivers/gpu/drm/i915/display/intel_color.c
4102
intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), LUT_3D_AUTO_INCREMENT);
drivers/gpu/drm/i915/display/intel_color.c
4104
intel_de_write_dsb(display, dsb, LUT_3D_DATA(pipe), glk_3dlut_10(&lut[i]));
drivers/gpu/drm/i915/display/intel_color.c
4105
intel_de_write_dsb(display, dsb, LUT_3D_INDEX(pipe), 0);
drivers/gpu/drm/i915/display/intel_color.c
4110
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
4114
if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
drivers/gpu/drm/i915/display/intel_color.c
4115
drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not committing change\n",
drivers/gpu/drm/i915/display/intel_color.c
4123
intel_de_write_dsb(display, dsb, LUT_3D_CTL(pipe), val);
drivers/gpu/drm/i915/display/intel_color.c
419
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
422
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_color.c
4258
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
426
if (DISPLAY_VER(display) < 7 || display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_color.c
4261
if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
drivers/gpu/drm/i915/display/intel_color.c
4269
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
4271
if (display->color.funcs->load_plane_csc_matrix)
drivers/gpu/drm/i915/display/intel_color.c
4272
display->color.funcs->load_plane_csc_matrix(dsb, plane_state);
drivers/gpu/drm/i915/display/intel_color.c
4279
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
4281
if (display->color.funcs->load_plane_luts)
drivers/gpu/drm/i915/display/intel_color.c
4282
display->color.funcs->load_plane_luts(dsb, plane_state);
drivers/gpu/drm/i915/display/intel_color.c
4286
intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_color.c
4288
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_color.c
4298
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_color.c
4301
if (crtc && intel_color_crtc_has_3dlut(display, crtc->pipe))
drivers/gpu/drm/i915/display/intel_color.c
4318
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
4324
gamma_lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
4325
degamma_lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
drivers/gpu/drm/i915/display/intel_color.c
4326
has_ctm = DISPLAY_VER(display) >= 5;
drivers/gpu/drm/i915/display/intel_color.c
4336
if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)
drivers/gpu/drm/i915/display/intel_color.c
434
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
4343
int intel_color_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_color.c
4347
if (DISPLAY_VER(display) != 10)
drivers/gpu/drm/i915/display/intel_color.c
4350
blob = create_linear_lut(display,
drivers/gpu/drm/i915/display/intel_color.c
4351
DISPLAY_INFO(display)->color.degamma_lut_size);
drivers/gpu/drm/i915/display/intel_color.c
4355
display->color.glk_linear_degamma_lut = blob;
drivers/gpu/drm/i915/display/intel_color.c
4360
void intel_color_init_hooks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_color.c
4362
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/intel_color.c
4363
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_color.c
4364
display->color.funcs = &chv_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4365
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_color.c
4366
display->color.funcs = &vlv_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4367
else if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_color.c
4368
display->color.funcs = &i965_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4370
display->color.funcs = &i9xx_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4372
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_color.c
4373
display->color.funcs = &tgl_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4374
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_color.c
4375
display->color.funcs = &icl_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4376
else if (DISPLAY_VER(display) == 10)
drivers/gpu/drm/i915/display/intel_color.c
4377
display->color.funcs = &glk_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4378
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_color.c
4379
display->color.funcs = &skl_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4380
else if (DISPLAY_VER(display) == 8)
drivers/gpu/drm/i915/display/intel_color.c
4381
display->color.funcs = &bdw_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4382
else if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_color.c
4383
display->color.funcs = &hsw_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4384
else if (DISPLAY_VER(display) == 7)
drivers/gpu/drm/i915/display/intel_color.c
4385
display->color.funcs = &ivb_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
4387
display->color.funcs = &ilk_color_funcs;
drivers/gpu/drm/i915/display/intel_color.c
442
if (DISPLAY_VER(display) == 10)
drivers/gpu/drm/i915/display/intel_color.c
457
static void ilk_csc_copy(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_color.c
463
if (DISPLAY_VER(display) < 7)
drivers/gpu/drm/i915/display/intel_color.c
471
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
479
ilk_csc_copy(display, csc, &ilk_csc_matrix_limited_range);
drivers/gpu/drm/i915/display/intel_color.c
481
ilk_csc_copy(display, csc, &ilk_csc_matrix_identity);
drivers/gpu/drm/i915/display/intel_color.c
529
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
533
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
drivers/gpu/drm/i915/display/intel_color.c
537
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
drivers/gpu/drm/i915/display/intel_color.c
539
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);
drivers/gpu/drm/i915/display/intel_color.c
541
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
drivers/gpu/drm/i915/display/intel_color.c
543
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_limited_range);
drivers/gpu/drm/i915/display/intel_color.c
551
drm_WARN_ON(display->drm, !display->platform.geminilake);
drivers/gpu/drm/i915/display/intel_color.c
553
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);
drivers/gpu/drm/i915/display/intel_color.c
570
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
573
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);
drivers/gpu/drm/i915/display/intel_color.c
577
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);
drivers/gpu/drm/i915/display/intel_color.c
583
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
drivers/gpu/drm/i915/display/intel_color.c
585
ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);
drivers/gpu/drm/i915/display/intel_color.c
587
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
drivers/gpu/drm/i915/display/intel_color.c
589
ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);
drivers/gpu/drm/i915/display/intel_color.c
591
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);
drivers/gpu/drm/i915/display/intel_color.c
651
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
654
intel_de_write_fw(display, PIPE_WGC_C01_C00(display, pipe),
drivers/gpu/drm/i915/display/intel_color.c
656
intel_de_write_fw(display, PIPE_WGC_C02(display, pipe),
drivers/gpu/drm/i915/display/intel_color.c
659
intel_de_write_fw(display, PIPE_WGC_C11_C10(display, pipe),
drivers/gpu/drm/i915/display/intel_color.c
661
intel_de_write_fw(display, PIPE_WGC_C12(display, pipe),
drivers/gpu/drm/i915/display/intel_color.c
664
intel_de_write_fw(display, PIPE_WGC_C21_C20(display, pipe),
drivers/gpu/drm/i915/display/intel_color.c
666
intel_de_write_fw(display, PIPE_WGC_C22(display, pipe),
drivers/gpu/drm/i915/display/intel_color.c
673
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
677
tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));
drivers/gpu/drm/i915/display/intel_color.c
681
tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));
drivers/gpu/drm/i915/display/intel_color.c
684
tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));
drivers/gpu/drm/i915/display/intel_color.c
688
tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));
drivers/gpu/drm/i915/display/intel_color.c
691
tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));
drivers/gpu/drm/i915/display/intel_color.c
695
tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));
drivers/gpu/drm/i915/display/intel_color.c
709
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
712
drm_WARN_ON(display->drm, !crtc_state->wgc_enable);
drivers/gpu/drm/i915/display/intel_color.c
716
drm_WARN_ON(display->drm, crtc_state->wgc_enable);
drivers/gpu/drm/i915/display/intel_color.c
753
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
756
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF01(pipe),
drivers/gpu/drm/i915/display/intel_color.c
758
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF23(pipe),
drivers/gpu/drm/i915/display/intel_color.c
760
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF45(pipe),
drivers/gpu/drm/i915/display/intel_color.c
762
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF67(pipe),
drivers/gpu/drm/i915/display/intel_color.c
764
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF8(pipe),
drivers/gpu/drm/i915/display/intel_color.c
771
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_color.c
775
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));
drivers/gpu/drm/i915/display/intel_color.c
779
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));
drivers/gpu/drm/i915/display/intel_color.c
783
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));
drivers/gpu/drm/i915/display/intel_color.c
787
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));
drivers/gpu/drm/i915/display/intel_color.c
791
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));
drivers/gpu/drm/i915/display/intel_color.c
805
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_color.c
807
drm_WARN_ON(display->drm, crtc_state->wgc_enable);
drivers/gpu/drm/i915/display/intel_color.c
810
drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
drivers/gpu/drm/i915/display/intel_color.c
814
drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
drivers/gpu/drm/i915/display/intel_color.h
20
void intel_color_init_hooks(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_color.h
21
int intel_color_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_color.h
49
bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_color_pipeline.c
118
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_color_pipeline.c
126
if (plane_has_3dlut(display, pipe, plane)) {
drivers/gpu/drm/i915/display/intel_color_pipeline.c
159
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_color_pipeline.c
166
if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
drivers/gpu/drm/i915/display/intel_color_pipeline.c
46
static bool plane_has_3dlut(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_color_pipeline.c
49
return (DISPLAY_VER(display) >= 35 &&
drivers/gpu/drm/i915/display/intel_color_pipeline.c
50
intel_color_crtc_has_3dlut(display, pipe) &&
drivers/gpu/drm/i915/display/intel_combo_phy.c
101
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_combo_phy.c
112
static bool icl_verify_procmon_ref_values(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_combo_phy.c
118
procmon = icl_get_procmon_ref_values(display, phy);
drivers/gpu/drm/i915/display/intel_combo_phy.c
120
ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
122
ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
124
ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
130
static bool has_phy_misc(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_combo_phy.c
141
if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_combo_phy.c
143
else if ((display->platform.jasperlake || display->platform.elkhartlake) ||
drivers/gpu/drm/i915/display/intel_combo_phy.c
144
display->platform.rocketlake ||
drivers/gpu/drm/i915/display/intel_combo_phy.c
145
display->platform.dg1)
drivers/gpu/drm/i915/display/intel_combo_phy.c
151
static bool icl_combo_phy_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_combo_phy.c
155
if (!has_phy_misc(display, phy))
drivers/gpu/drm/i915/display/intel_combo_phy.c
156
return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
drivers/gpu/drm/i915/display/intel_combo_phy.c
158
return !(intel_de_read(display, ICL_PHY_MISC(phy)) &
drivers/gpu/drm/i915/display/intel_combo_phy.c
160
(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
drivers/gpu/drm/i915/display/intel_combo_phy.c
163
static bool ehl_vbt_ddi_d_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_combo_phy.c
165
bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);
drivers/gpu/drm/i915/display/intel_combo_phy.c
166
bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);
drivers/gpu/drm/i915/display/intel_combo_phy.c
167
bool dsi_present = intel_bios_is_dsi_present(display, NULL);
drivers/gpu/drm/i915/display/intel_combo_phy.c
184
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_combo_phy.c
190
static bool phy_is_master(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_combo_phy.c
210
else if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_combo_phy.c
212
else if (display->platform.dg1 || display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_combo_phy.c
218
static bool icl_combo_phy_verify_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_combo_phy.c
224
if (!icl_combo_phy_enabled(display, phy))
drivers/gpu/drm/i915/display/intel_combo_phy.c
227
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
228
ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
234
ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
238
ret &= icl_verify_procmon_ref_values(display, phy);
drivers/gpu/drm/i915/display/intel_combo_phy.c
240
if (phy_is_master(display, phy)) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
241
ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
244
if (display->platform.jasperlake || display->platform.elkhartlake) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
245
if (ehl_vbt_ddi_d_present(display))
drivers/gpu/drm/i915/display/intel_combo_phy.c
248
ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
254
ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
260
void intel_combo_phy_power_up_lanes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_combo_phy.c
267
drm_WARN_ON(display->drm, lane_reversal);
drivers/gpu/drm/i915/display/intel_combo_phy.c
305
intel_de_rmw(display, ICL_PORT_CL_DW10(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
309
static void icl_combo_phys_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_combo_phy.c
313
for_each_combo_phy(display, phy) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
317
if (icl_combo_phy_verify_state(display, phy))
drivers/gpu/drm/i915/display/intel_combo_phy.c
320
procmon = icl_get_procmon_ref_values(display, phy);
drivers/gpu/drm/i915/display/intel_combo_phy.c
322
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_combo_phy.c
326
if (!has_phy_misc(display, phy))
drivers/gpu/drm/i915/display/intel_combo_phy.c
337
val = intel_de_read(display, ICL_PHY_MISC(phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
338
if ((display->platform.jasperlake || display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_combo_phy.c
342
if (ehl_vbt_ddi_d_present(display))
drivers/gpu/drm/i915/display/intel_combo_phy.c
347
intel_de_write(display, ICL_PHY_MISC(phy), val);
drivers/gpu/drm/i915/display/intel_combo_phy.c
350
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
351
val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
355
intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);
drivers/gpu/drm/i915/display/intel_combo_phy.c
357
val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
360
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
drivers/gpu/drm/i915/display/intel_combo_phy.c
363
icl_set_procmon_ref_values(display, phy);
drivers/gpu/drm/i915/display/intel_combo_phy.c
365
if (phy_is_master(display, phy))
drivers/gpu/drm/i915/display/intel_combo_phy.c
366
intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
369
intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
drivers/gpu/drm/i915/display/intel_combo_phy.c
370
intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
375
static void icl_combo_phys_uninit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_combo_phy.c
379
for_each_combo_phy_reverse(display, phy) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
381
!icl_combo_phy_verify_state(display, phy)) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
382
if (display->platform.tigerlake || display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_combo_phy.c
388
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_combo_phy.c
392
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_combo_phy.c
398
if (!has_phy_misc(display, phy))
drivers/gpu/drm/i915/display/intel_combo_phy.c
401
intel_de_rmw(display, ICL_PHY_MISC(phy), 0,
drivers/gpu/drm/i915/display/intel_combo_phy.c
405
intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);
drivers/gpu/drm/i915/display/intel_combo_phy.c
409
void intel_combo_phy_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_combo_phy.c
411
icl_combo_phys_init(display);
drivers/gpu/drm/i915/display/intel_combo_phy.c
414
void intel_combo_phy_uninit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_combo_phy.c
416
icl_combo_phys_uninit(display);
drivers/gpu/drm/i915/display/intel_combo_phy.c
58
icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_combo_phy.c
62
val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));
drivers/gpu/drm/i915/display/intel_combo_phy.c
80
static void icl_set_procmon_ref_values(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_combo_phy.c
85
procmon = icl_get_procmon_ref_values(display, phy);
drivers/gpu/drm/i915/display/intel_combo_phy.c
87
intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),
drivers/gpu/drm/i915/display/intel_combo_phy.c
90
intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);
drivers/gpu/drm/i915/display/intel_combo_phy.c
91
intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);
drivers/gpu/drm/i915/display/intel_combo_phy.c
94
static bool check_phy_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_combo_phy.c
98
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_combo_phy.h
14
void intel_combo_phy_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_combo_phy.h
15
void intel_combo_phy_uninit(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_combo_phy.h
16
void intel_combo_phy_power_up_lanes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_connector.c
198
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_connector.c
200
drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_connector.c
257
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_connector.c
260
prop = display->properties.force_audio;
drivers/gpu/drm/i915/display/intel_connector.c
262
prop = drm_property_create_enum(display->drm, 0,
drivers/gpu/drm/i915/display/intel_connector.c
269
display->properties.force_audio = prop;
drivers/gpu/drm/i915/display/intel_connector.c
283
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_connector.c
286
prop = display->properties.broadcast_rgb;
drivers/gpu/drm/i915/display/intel_connector.c
288
prop = drm_property_create_enum(display->drm, DRM_MODE_PROP_ENUM,
drivers/gpu/drm/i915/display/intel_connector.c
295
display->properties.broadcast_rgb = prop;
drivers/gpu/drm/i915/display/intel_connector.c
327
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_connector.c
334
if (!HAS_GMCH(display) || connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
drivers/gpu/drm/i915/display/intel_connector.c
45
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_connector.c
47
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id,
drivers/gpu/drm/i915/display/intel_connector.c
51
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_connector.c
57
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_connector.c
66
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_connector.c
69
if (!queue_work(display->wq.unordered, &connector->modeset_retry_work))
drivers/gpu/drm/i915/display/intel_crt.c
101
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_crt.c
1010
void intel_crt_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_crt.c
1018
if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_crt.c
1020
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_crt.c
1025
adpa = intel_de_read(display, adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
1035
intel_de_write(display, adpa_reg,
drivers/gpu/drm/i915/display/intel_crt.c
1039
if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_crt.c
1041
intel_de_write(display, adpa_reg, adpa);
drivers/gpu/drm/i915/display/intel_crt.c
1054
ddc_pin = display->vbt.crt_ddc_pin;
drivers/gpu/drm/i915/display/intel_crt.c
1056
drm_connector_init_with_ddc(display->drm, &connector->base,
drivers/gpu/drm/i915/display/intel_crt.c
1059
intel_gmbus_get_adapter(display, ddc_pin));
drivers/gpu/drm/i915/display/intel_crt.c
1061
drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
drivers/gpu/drm/i915/display/intel_crt.c
1068
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_crt.c
1073
if (DISPLAY_VER(display) != 2)
drivers/gpu/drm/i915/display/intel_crt.c
1080
if (HAS_HOTPLUG(display) &&
drivers/gpu/drm/i915/display/intel_crt.c
1090
if (HAS_DDI(display)) {
drivers/gpu/drm/i915/display/intel_crt.c
1091
assert_port_valid(display, PORT_E);
drivers/gpu/drm/i915/display/intel_crt.c
1108
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_crt.c
112
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
1130
if (HAS_PCH_LPT(display)) {
drivers/gpu/drm/i915/display/intel_crt.c
1134
display->fdi.rx_config = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
117
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_crt.c
122
ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
drivers/gpu/drm/i915/display/intel_crt.c
124
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_crt.c
131
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
135
tmp = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
180
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
186
if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_crt.c
197
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_crt.c
199
else if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_crt.c
204
if (!HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_crt.c
205
intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_crt.c
222
intel_de_write(display, crt->adpa_reg, adpa);
drivers/gpu/drm/i915/display/intel_crt.c
253
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
255
drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_crt.c
257
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/intel_crt.c
265
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
284
drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_crt.c
286
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/intel_crt.c
294
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
296
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_crt.c
298
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/intel_crt.c
306
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
310
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_crt.c
312
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_crt.c
324
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
328
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_crt.c
342
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_crt.c
343
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/intel_crt.c
358
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
359
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_crt.c
363
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_crt.c
370
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_crt.c
372
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_crt.c
378
else if (IS_DISPLAY_VER(display, 3, 4))
drivers/gpu/drm/i915/display/intel_crt.c
389
if (HAS_PCH_LPT(display) &&
drivers/gpu/drm/i915/display/intel_crt.c
439
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_crt.c
458
if (HAS_PCH_LPT(display)) {
drivers/gpu/drm/i915/display/intel_crt.c
461
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
481
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
488
bool turn_off_dac = HAS_PCH_SPLIT(display);
drivers/gpu/drm/i915/display/intel_crt.c
493
save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
494
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
501
intel_de_write(display, crt->adpa_reg, adpa);
drivers/gpu/drm/i915/display/intel_crt.c
503
if (intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_crt.c
507
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
511
intel_de_write(display, crt->adpa_reg, save_adpa);
drivers/gpu/drm/i915/display/intel_crt.c
512
intel_de_posting_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
517
adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
522
drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
drivers/gpu/drm/i915/display/intel_crt.c
530
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
550
save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
551
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
556
intel_de_write(display, crt->adpa_reg, adpa);
drivers/gpu/drm/i915/display/intel_crt.c
558
if (intel_de_wait_for_clear_ms(display, crt->adpa_reg,
drivers/gpu/drm/i915/display/intel_crt.c
560
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
562
intel_de_write(display, crt->adpa_reg, save_adpa);
drivers/gpu/drm/i915/display/intel_crt.c
566
adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
572
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
582
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
587
if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_crt.c
590
if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_crt.c
598
if (display->platform.g45)
drivers/gpu/drm/i915/display/intel_crt.c
605
i915_hotplug_interrupt_update(display,
drivers/gpu/drm/i915/display/intel_crt.c
609
if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display),
drivers/gpu/drm/i915/display/intel_crt.c
611
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
615
stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
drivers/gpu/drm/i915/display/intel_crt.c
620
intel_de_write(display, PORT_HOTPLUG_STAT(display),
drivers/gpu/drm/i915/display/intel_crt.c
623
i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0);
drivers/gpu/drm/i915/display/intel_crt.c
666
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
679
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
682
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
687
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
696
static bool intel_crt_sense_above_threshold(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_crt.c
698
return intel_vga_read(display, VGA_IS0_R, true) & (1 << 4);
drivers/gpu/drm/i915/display/intel_crt.c
704
struct intel_display *display = to_intel_display(&crt->base);
drivers/gpu/drm/i915/display/intel_crt.c
714
drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
drivers/gpu/drm/i915/display/intel_crt.c
716
save_bclrpat = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
717
BCLRPAT(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_crt.c
718
save_vtotal = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
719
TRANS_VTOTAL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_crt.c
720
vblank = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
721
TRANS_VBLANK(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_crt.c
730
intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
drivers/gpu/drm/i915/display/intel_crt.c
732
if (DISPLAY_VER(display) != 2) {
drivers/gpu/drm/i915/display/intel_crt.c
733
u32 transconf = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
734
TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_crt.c
736
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_crt.c
738
intel_de_posting_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
739
TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_crt.c
744
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
drivers/gpu/drm/i915/display/intel_crt.c
746
status = intel_crt_sense_above_threshold(display) ?
drivers/gpu/drm/i915/display/intel_crt.c
750
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_crt.c
761
u32 vsync = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_crt.c
762
TRANS_VSYNC(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_crt.c
766
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_crt.c
767
TRANS_VBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_crt.c
781
while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
drivers/gpu/drm/i915/display/intel_crt.c
783
while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
drivers/gpu/drm/i915/display/intel_crt.c
792
if (intel_crt_sense_above_threshold(display))
drivers/gpu/drm/i915/display/intel_crt.c
794
} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
drivers/gpu/drm/i915/display/intel_crt.c
798
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_crt.c
799
TRANS_VBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_crt.c
813
intel_de_write(display, BCLRPAT(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_crt.c
850
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
857
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
drivers/gpu/drm/i915/display/intel_crt.c
861
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_crt.c
864
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_crt.c
867
if (display->params.load_detect_test) {
drivers/gpu/drm/i915/display/intel_crt.c
868
wakeref = intel_display_power_get(display, encoder->power_domain);
drivers/gpu/drm/i915/display/intel_crt.c
876
wakeref = intel_display_power_get(display, encoder->power_domain);
drivers/gpu/drm/i915/display/intel_crt.c
878
if (HAS_HOTPLUG(display)) {
drivers/gpu/drm/i915/display/intel_crt.c
884
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
889
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_crt.c
902
if (HAS_HOTPLUG(display)) {
drivers/gpu/drm/i915/display/intel_crt.c
922
else if (DISPLAY_VER(display) < 4)
drivers/gpu/drm/i915/display/intel_crt.c
925
else if (display->params.load_detect_test)
drivers/gpu/drm/i915/display/intel_crt.c
93
bool intel_crt_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crt.c
933
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_crt.c
940
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_crt.c
947
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_crt.c
950
wakeref = intel_display_power_get(display, encoder->power_domain);
drivers/gpu/drm/i915/display/intel_crt.c
953
if (ret || !display->platform.g4x)
drivers/gpu/drm/i915/display/intel_crt.c
957
ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
drivers/gpu/drm/i915/display/intel_crt.c
961
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_crt.c
968
struct intel_display *display = to_intel_display(encoder->dev);
drivers/gpu/drm/i915/display/intel_crt.c
971
if (DISPLAY_VER(display) >= 5) {
drivers/gpu/drm/i915/display/intel_crt.c
974
adpa = intel_de_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
977
intel_de_write(display, crt->adpa_reg, adpa);
drivers/gpu/drm/i915/display/intel_crt.c
978
intel_de_posting_read(display, crt->adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
98
val = intel_de_read(display, adpa_reg);
drivers/gpu/drm/i915/display/intel_crt.c
980
drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
drivers/gpu/drm/i915/display/intel_crt.h
16
bool intel_crt_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crt.h
18
void intel_crt_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_crt.h
21
static inline bool intel_crt_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crt.h
26
static inline void intel_crt_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_crtc.c
101
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_crtc.c
117
if (display->platform.i965gm &&
drivers/gpu/drm/i915/display/intel_crtc.c
121
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_crtc.c
123
else if (DISPLAY_VER(display) >= 3)
drivers/gpu/drm/i915/display/intel_crtc.c
150
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_crtc.c
165
flush_work(&display->irq.vblank_notify_work);
drivers/gpu/drm/i915/display/intel_crtc.c
316
static void add_crtc_to_pipe_list(struct intel_display *display, struct intel_crtc *crtc)
drivers/gpu/drm/i915/display/intel_crtc.c
320
list_for_each_entry(iter, &display->pipe_list, pipe_head) {
drivers/gpu/drm/i915/display/intel_crtc.c
327
list_add_tail(&crtc->pipe_head, &display->pipe_list);
drivers/gpu/drm/i915/display/intel_crtc.c
330
static int __intel_crtc_init(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_crtc.c
342
crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe];
drivers/gpu/drm/i915/display/intel_crtc.c
344
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_crtc.c
345
primary = skl_universal_plane_create(display, pipe, PLANE_1);
drivers/gpu/drm/i915/display/intel_crtc.c
347
primary = intel_primary_plane_create(display, pipe);
drivers/gpu/drm/i915/display/intel_crtc.c
354
intel_init_fifo_underrun_reporting(display, crtc, false);
drivers/gpu/drm/i915/display/intel_crtc.c
356
for_each_sprite(display, pipe, sprite) {
drivers/gpu/drm/i915/display/intel_crtc.c
359
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_crtc.c
360
plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite);
drivers/gpu/drm/i915/display/intel_crtc.c
362
plane = intel_sprite_plane_create(display, pipe, sprite);
drivers/gpu/drm/i915/display/intel_crtc.c
370
cursor = intel_cursor_plane_create(display, pipe);
drivers/gpu/drm/i915/display/intel_crtc.c
377
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/intel_crtc.c
378
if (display->platform.cherryview ||
drivers/gpu/drm/i915/display/intel_crtc.c
379
display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_crtc.c
380
display->platform.g4x)
drivers/gpu/drm/i915/display/intel_crtc.c
382
else if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/intel_crtc.c
384
else if (display->platform.i945gm ||
drivers/gpu/drm/i915/display/intel_crtc.c
385
display->platform.i915gm)
drivers/gpu/drm/i915/display/intel_crtc.c
387
else if (DISPLAY_VER(display) == 3)
drivers/gpu/drm/i915/display/intel_crtc.c
392
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_crtc.c
398
ret = drm_crtc_init_with_planes(display->drm, &crtc->base,
drivers/gpu/drm/i915/display/intel_crtc.c
404
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_crtc.c
409
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_crtc.c
41
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_crtc.c
418
if (HAS_CASF(display) && crtc->num_scalers >= 2)
drivers/gpu/drm/i915/display/intel_crtc.c
421
add_crtc_to_pipe_list(display, crtc);
drivers/gpu/drm/i915/display/intel_crtc.c
43
if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0,
drivers/gpu/drm/i915/display/intel_crtc.c
431
#define HAS_PIPE(display, pipe) (DISPLAY_RUNTIME_INFO(display)->pipe_mask & BIT(pipe))
drivers/gpu/drm/i915/display/intel_crtc.c
441
static enum pipe reorder_pipe(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_crtc.c
443
if (!display->platform.dgfx || !HAS_PIPE(display, PIPE_B) || !HAS_PIPE(display, PIPE_C))
drivers/gpu/drm/i915/display/intel_crtc.c
456
int intel_crtc_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_crtc.c
461
drm_dbg_kms(display->drm, "%d display pipe%s available.\n",
drivers/gpu/drm/i915/display/intel_crtc.c
462
INTEL_NUM_PIPES(display), str_plural(INTEL_NUM_PIPES(display)));
drivers/gpu/drm/i915/display/intel_crtc.c
464
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_crtc.c
465
ret = __intel_crtc_init(display, reorder_pipe(display, pipe));
drivers/gpu/drm/i915/display/intel_crtc.c
49
struct intel_crtc *intel_first_crtc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_crtc.c
492
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_crtc.c
498
!HAS_DOUBLE_BUFFERED_LUT(display)) &&
drivers/gpu/drm/i915/display/intel_crtc.c
51
return to_intel_crtc(drm_crtc_from_index(display->drm, 0));
drivers/gpu/drm/i915/display/intel_crtc.c
54
struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crtc.c
59
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_crtc.c
590
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_crtc.c
598
drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
drivers/gpu/drm/i915/display/intel_crtc.c
626
if (drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base)))
drivers/gpu/drm/i915/display/intel_crtc.c
72
void intel_wait_for_vblank_if_active(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crtc.c
729
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_crtc.c
737
drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
drivers/gpu/drm/i915/display/intel_crtc.c
748
if (DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/intel_crtc.c
75
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_crtc.c
803
if (intel_parent_vgpu_active(display))
drivers/gpu/drm/i915/display/intel_crtc.c
808
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_crtc.c
873
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_crtc.c
888
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_crtc.c
898
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_crtc.c
900
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_crtc.h
40
int intel_crtc_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_crtc.h
54
struct intel_crtc *intel_first_crtc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_crtc.h
55
struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crtc.h
57
void intel_wait_for_vblank_if_active(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
140
ilk_dump_csc(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
156
if (DISPLAY_VER(display) < 7)
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
180
struct intel_display *display = to_intel_display(pipe_config);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
191
p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
265
intel_dump_infoframe(display, &pipe_config->infoframes.avi);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
268
intel_dump_infoframe(display, &pipe_config->infoframes.spd);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
271
intel_dump_infoframe(display, &pipe_config->infoframes.hdmi);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
274
intel_dump_infoframe(display, &pipe_config->infoframes.drm);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
277
intel_dump_infoframe(display, &pipe_config->infoframes.drm);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
330
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
341
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
361
intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
363
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
374
display->color.glk_linear_degamma_lut ? "(linear) " : "",
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
380
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
381
ilk_dump_csc(display, &p, "output csc", &pipe_config->output_csc);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
383
if (!HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
384
ilk_dump_csc(display, &p, "pipe csc", &pipe_config->csc);
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
385
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
387
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
46
intel_dump_infoframe(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
52
hdmi_infoframe_log(KERN_DEBUG, display->drm->dev, frame);
drivers/gpu/drm/i915/display/intel_cursor.c
1003
intel_cursor_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cursor.c
1019
if (display->platform.i845g || display->platform.i865g) {
drivers/gpu/drm/i915/display/intel_cursor.c
1029
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_cursor.c
1031
else if (display->platform.i85x)
drivers/gpu/drm/i915/display/intel_cursor.c
1036
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/intel_cursor.c
1047
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_cursor.c
1055
if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display))
drivers/gpu/drm/i915/display/intel_cursor.c
1058
modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE);
drivers/gpu/drm/i915/display/intel_cursor.c
1060
ret = drm_universal_plane_init(display->drm, &cursor->base,
drivers/gpu/drm/i915/display/intel_cursor.c
1073
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_cursor.c
108
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cursor.c
1081
zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1;
drivers/gpu/drm/i915/display/intel_cursor.c
1084
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_cursor.c
1097
void intel_cursor_mode_config_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cursor.c
1099
struct drm_mode_config *mode_config = &display->drm->mode_config;
drivers/gpu/drm/i915/display/intel_cursor.c
1101
if (display->platform.i845g) {
drivers/gpu/drm/i915/display/intel_cursor.c
1104
} else if (display->platform.i865g) {
drivers/gpu/drm/i915/display/intel_cursor.c
1107
} else if (display->platform.i830 || display->platform.i85x ||
drivers/gpu/drm/i915/display/intel_cursor.c
1108
display->platform.i915g || display->platform.i915gm) {
drivers/gpu/drm/i915/display/intel_cursor.c
122
if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) {
drivers/gpu/drm/i915/display/intel_cursor.c
140
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_cursor.c
148
drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n",
drivers/gpu/drm/i915/display/intel_cursor.c
229
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_cursor.c
244
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cursor.c
252
drm_WARN_ON(display->drm, plane_state->uapi.visible &&
drivers/gpu/drm/i915/display/intel_cursor.c
262
drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n",
drivers/gpu/drm/i915/display/intel_cursor.c
279
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
301
intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);
drivers/gpu/drm/i915/display/intel_cursor.c
302
intel_de_write_fw(display, CURBASE(display, PIPE_A), base);
drivers/gpu/drm/i915/display/intel_cursor.c
303
intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);
drivers/gpu/drm/i915/display/intel_cursor.c
304
intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);
drivers/gpu/drm/i915/display/intel_cursor.c
305
intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);
drivers/gpu/drm/i915/display/intel_cursor.c
311
intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);
drivers/gpu/drm/i915/display/intel_cursor.c
325
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
331
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_cursor.c
335
ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;
drivers/gpu/drm/i915/display/intel_cursor.c
339
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_cursor.c
371
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
373
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/intel_cursor.c
381
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cursor.c
385
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_cursor.c
394
if (DISPLAY_VER(display) < 5 && !display->platform.g4x)
drivers/gpu/drm/i915/display/intel_cursor.c
402
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_cursor.c
405
if (display->platform.sandybridge || display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_cursor.c
427
if (intel_display_wa(display, INTEL_DISPLAY_WA_22012358565))
drivers/gpu/drm/i915/display/intel_cursor.c
435
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_cursor.c
458
if (HAS_CUR_FBC(display) &&
drivers/gpu/drm/i915/display/intel_cursor.c
473
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_cursor.c
489
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cursor.c
497
drm_WARN_ON(display->drm, plane_state->uapi.visible &&
drivers/gpu/drm/i915/display/intel_cursor.c
502
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cursor.c
519
if (display->platform.cherryview && pipe == PIPE_C &&
drivers/gpu/drm/i915/display/intel_cursor.c
521
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cursor.c
536
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
542
intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
drivers/gpu/drm/i915/display/intel_cursor.c
550
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
558
intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);
drivers/gpu/drm/i915/display/intel_cursor.c
560
intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe),
drivers/gpu/drm/i915/display/intel_cursor.c
569
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
580
intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);
drivers/gpu/drm/i915/display/intel_cursor.c
583
intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);
drivers/gpu/drm/i915/display/intel_cursor.c
620
struct intel_display *display = to_intel_display(plane->base.dev);
drivers/gpu/drm/i915/display/intel_cursor.c
628
for (level = 0; level < display->wm.num_levels; level++)
drivers/gpu/drm/i915/display/intel_cursor.c
629
intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),
drivers/gpu/drm/i915/display/intel_cursor.c
632
intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),
drivers/gpu/drm/i915/display/intel_cursor.c
635
if (HAS_HW_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/intel_cursor.c
638
intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),
drivers/gpu/drm/i915/display/intel_cursor.c
640
intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),
drivers/gpu/drm/i915/display/intel_cursor.c
644
intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),
drivers/gpu/drm/i915/display/intel_cursor.c
654
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
665
if (DISPLAY_VER(display) < 14 && width != height)
drivers/gpu/drm/i915/display/intel_cursor.c
692
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_cursor.c
703
if (HAS_CUR_FBC(display))
drivers/gpu/drm/i915/display/intel_cursor.c
704
intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl);
drivers/gpu/drm/i915/display/intel_cursor.c
705
intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl);
drivers/gpu/drm/i915/display/intel_cursor.c
706
intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);
drivers/gpu/drm/i915/display/intel_cursor.c
707
intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);
drivers/gpu/drm/i915/display/intel_cursor.c
713
intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);
drivers/gpu/drm/i915/display/intel_cursor.c
714
intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);
drivers/gpu/drm/i915/display/intel_cursor.c
728
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
740
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_cursor.c
744
val = intel_de_read(display, CURCNTR(display, plane->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
748
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_cursor.c
753
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_cursor.c
762
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
764
error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
765
error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
766
error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
773
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
775
error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
776
error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_cursor.c
811
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
86
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_cursor.c
915
if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
drivers/gpu/drm/i915/display/intel_cursor.c
982
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_cursor.c
983
const struct drm_mode_config *config = &display->drm->mode_config;
drivers/gpu/drm/i915/display/intel_cursor.c
991
if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints)))
drivers/gpu/drm/i915/display/intel_cursor.h
15
intel_cursor_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cursor.h
20
void intel_cursor_mode_config_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
111
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
116
wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
124
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
128
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
134
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
136
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
137
XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
143
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
147
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
150
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
153
drm_err_once(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
165
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
169
if (intel_de_wait_ms(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
173
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
177
if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
179
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
188
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
197
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1987
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1990
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2010
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2016
drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <
drivers/gpu/drm/i915/display/intel_cx0_phy.c
211
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2126
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2132
drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2141
drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2154
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
217
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2178
drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&hw_state->cx0pll.c10));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2185
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2191
lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
220
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2208
max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2211
if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0))
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2229
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2231
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2239
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2269
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2276
static void intel_c10_pll_program(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
228
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2352
static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2358
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2361
} else if (display->platform.battlemage) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2363
} else if (display->platform.meteorlake_u ||
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2375
static int intel_c20_compute_hdmi_tmds_pll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2416
pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
244
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2448
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2452
if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2454
if (DISPLAY_VERx100(display) == 1401)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2458
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2460
else if (DISPLAY_VERx100(display) == 1401)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
253
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
257
assert_dc_off(display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2591
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2593
drm_WARN_ON(display->drm, vdr->custom_width & ~PHY_C20_CUSTOM_WIDTH_MASK);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2598
drm_WARN_ON(display->drm, vdr->serdes_rate & ~PHY_C20_SERDES_RATE_MASK);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2606
drm_WARN_ON(display->drm, vdr->hdmi_rate & ~PHY_C20_HDMI_RATE_MASK);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2616
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2627
drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2656
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
267
drm_err_once(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2673
err = intel_c20_compute_hdmi_tmds_pll(display, crtc_state->port_clock,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2682
drm_WARN_ON(display->drm, is_dp != c20pll_state_is_dp(&hw_state->cx0pll.c20));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2702
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2722
PHY_C20_B_TX_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2726
PHY_C20_A_TX_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2734
PHY_C20_B_CMN_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2738
PHY_C20_A_CMN_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2747
PHY_C20_B_MPLLB_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2751
PHY_C20_A_MPLLB_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2759
PHY_C20_B_MPLLA_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2763
PHY_C20_A_MPLLA_CNTX_CFG(display, i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2825
static void intel_c20_pll_program(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
284
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2853
PHY_C20_A_TX_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2857
PHY_C20_B_TX_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2865
PHY_C20_A_CMN_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2869
PHY_C20_B_CMN_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2878
PHY_C20_A_MPLLB_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2882
PHY_C20_B_MPLLB_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2889
PHY_C20_A_MPLLA_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2893
PHY_C20_B_MPLLA_CNTX_CFG(display, i),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
290
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2924
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2928
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
293
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2938
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2940
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2949
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2951
XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2980
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2983
intel_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2986
intel_de_rmw(display, buf_ctl2_reg,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2992
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2995
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3001
intel_de_rmw(display, buf_ctl2_reg,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3006
if (intel_de_wait_for_clear_ms(display, buf_ctl2_reg,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3009
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
301
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3016
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3019
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3022
intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3054
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3067
if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL1(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3070
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3074
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3077
if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
308
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3080
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3084
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3088
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3092
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3100
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3102
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3105
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
311
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3171
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3190
drm_WARN_ON(display->drm, lane_reversal && intel_tc_port_in_dp_alt_mode(dig_port));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
321
} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3216
intel_c10_pll_program(display, encoder, &pll_state->c10);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3218
intel_c20_pll_program(display, encoder, &pll_state->c20);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
323
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3235
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3241
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3246
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3250
drm_warn(display->drm, "Port %c PLL not locked\n",
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3283
bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3296
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3299
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3301
clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3303
drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3304
drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3305
drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3326
static int intel_mtl_tbt_clock_select(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3339
if (DISPLAY_VER(display) < 30) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3340
drm_WARN_ON(display->drm, "UHBR10 not supported for the platform\n");
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3345
if (DISPLAY_VER(display) < 30) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3346
drm_WARN_ON(display->drm, "UHBR20 not supported for the platform\n");
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3358
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
336
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3368
mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3369
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3370
intel_mtl_tbt_clock_select(display, port_clock));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3375
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3379
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3390
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3393
if (intel_de_wait_for_set_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3395
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3407
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3435
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3440
if (DISPLAY_VER(display) < 20 ||
drivers/gpu/drm/i915/display/intel_cx0_phy.c
345
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3467
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3472
if ((display->platform.battlemage && encoder->port == PORT_A) ||
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3473
(DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3481
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
349
assert_dc_off(display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3498
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3503
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3508
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3512
drm_warn(display->drm, "Port %c PLL not unlocked\n",
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3521
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3522
XELPDP_DDI_CLOCK_SELECT_MASK(display), 0);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3523
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3531
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3535
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3541
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3552
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3556
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3558
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3569
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3570
XELPDP_DDI_CLOCK_SELECT_MASK(display) |
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3574
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
359
drm_err_once(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3594
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3601
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3602
clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3701
void intel_cx0_pll_power_save_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3705
if (DISPLAY_VER(display) != 30)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3708
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3726
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3731
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3740
static void intel_c10pll_verify_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
375
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3754
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3763
p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
377
assert_dc_off(display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3771
static void intel_c10pll_verify_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3776
intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c10, true);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3783
intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3786
static void intel_c20pll_verify_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3800
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3809
p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3817
static void intel_c20pll_verify_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3822
intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c20, true);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3827
if (intel_c20_compute_hdmi_tmds_pll(display, pll_params->clock_rate, &pll_state) != 0)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3830
intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3833
static void intel_cx0pll_verify_tables(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3840
intel_c10pll_verify_params(display, &tables[i]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3842
intel_c20pll_verify_params(display, &tables[i]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3846
void intel_cx0pll_verify_plls(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3849
intel_cx0pll_verify_tables(display, mtl_c10_edp_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3850
intel_cx0pll_verify_tables(display, mtl_c10_dp_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3851
intel_cx0pll_verify_tables(display, mtl_c10_hdmi_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3854
intel_cx0pll_verify_tables(display, xe2hpd_c20_edp_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3855
intel_cx0pll_verify_tables(display, mtl_c20_dp_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3856
intel_cx0pll_verify_tables(display, xe2hpd_c20_dp_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3857
intel_cx0pll_verify_tables(display, xe3lpd_c20_dp_edp_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3858
intel_cx0pll_verify_tables(display, mtl_c20_hdmi_tables);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
389
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
39
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
392
assert_dc_off(display);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
42
if (display->platform.pantherlake) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
43
if (display->platform.pantherlake_wildcatlake)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
481
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
49
if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
496
if (drm_WARN_ON_ONCE(display->drm, !trans)) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
80
assert_dc_off(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
84
enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
85
drm_WARN_ON(display->drm, !enabled);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
90
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
94
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
95
XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
drivers/gpu/drm/i915/display/intel_cx0_phy.h
76
bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_cx0_phy.h
81
void intel_cx0pll_verify_plls(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cx0_phy.h
82
void intel_cx0_pll_power_save_wa(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
201
#define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
203
#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
206
#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
103
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
104
unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
111
for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
120
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
141
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
149
int intel_dbuf_bw_min_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
155
for_each_dbuf_slice(display, slice) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
164
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
181
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
189
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
198
if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
213
if (intel_dbuf_bw_state_changed(display, old_dbuf_bw_state, new_dbuf_bw_state)) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
220
intel_dbuf_bw_min_cdclk(display, old_dbuf_bw_state),
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
221
intel_dbuf_bw_min_cdclk(display, new_dbuf_bw_state),
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
229
void intel_dbuf_bw_update_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
232
to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
235
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
238
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
248
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
250
to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
253
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
282
int intel_dbuf_bw_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
290
intel_atomic_global_obj_init(display, &display->dbuf_bw.obj,
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
31
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
34
dbuf_bw_state = intel_atomic_get_old_global_obj_state(state, &display->dbuf_bw.obj);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
42
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
45
dbuf_bw_state = intel_atomic_get_new_global_obj_state(state, &display->dbuf_bw.obj);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
53
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
56
dbuf_bw_state = intel_atomic_get_global_obj_state(state, &display->dbuf_bw.obj);
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
63
static bool intel_dbuf_bw_changed(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
69
for_each_dbuf_slice(display, slice) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
78
static bool intel_dbuf_bw_state_changed(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
84
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_dbuf_bw.c
90
if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))
drivers/gpu/drm/i915/display/intel_dbuf_bw.h
29
int intel_dbuf_bw_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dbuf_bw.h
32
int intel_dbuf_bw_min_cdclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dbuf_bw.h
34
void intel_dbuf_bw_update_hw_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_ddi.c
1002
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_ddi.c
1011
intel_display_power_put(display, domain, wf);
drivers/gpu/drm/i915/display/intel_ddi.c
1017
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1025
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
1032
drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
1033
dig_port->ddi_io_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_ddi.c
1043
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
1051
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_ddi.c
1053
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
1058
intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_ddi.c
1063
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
1070
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
1075
intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_ddi.c
1078
static void _skl_ddi_set_iboost(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi.c
1083
tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);
drivers/gpu/drm/i915/display/intel_ddi.c
1089
intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp);
drivers/gpu/drm/i915/display/intel_ddi.c
1096
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1110
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1118
drm_err(display->drm, "Invalid I_boost value %u\n", iboost);
drivers/gpu/drm/i915/display/intel_ddi.c
1122
_skl_ddi_set_iboost(display, encoder->port, iboost);
drivers/gpu/drm/i915/display/intel_ddi.c
1125
_skl_ddi_set_iboost(display, PORT_E, iboost);
drivers/gpu/drm/i915/display/intel_ddi.c
1131
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
1137
if (drm_WARN_ON(display->drm, n_entries < 1))
drivers/gpu/drm/i915/display/intel_ddi.c
1139
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
1172
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1179
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1187
intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val,
drivers/gpu/drm/i915/display/intel_ddi.c
119
static bool has_buf_trans_select(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_ddi.c
1192
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1199
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
drivers/gpu/drm/i915/display/intel_ddi.c
1205
intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
121
return DISPLAY_VER(display) < 10 && !display->platform.broxton;
drivers/gpu/drm/i915/display/intel_ddi.c
1217
intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1228
intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1237
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
124
static bool has_iboost(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_ddi.c
1247
val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1252
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
drivers/gpu/drm/i915/display/intel_ddi.c
126
return DISPLAY_VER(display) == 9 && !display->platform.broxton;
drivers/gpu/drm/i915/display/intel_ddi.c
1262
intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1268
intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1272
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1274
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
drivers/gpu/drm/i915/display/intel_ddi.c
1280
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1282
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
drivers/gpu/drm/i915/display/intel_ddi.c
1288
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1297
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1301
intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1303
intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1313
intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1319
intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1330
intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1339
intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1355
intel_de_rmw(display, MG_CLKHUB(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1362
intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1369
intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
137
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1379
intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1381
intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),
drivers/gpu/drm/i915/display/intel_ddi.c
1389
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1398
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1405
if (intel_display_wa(display, INTEL_DISPLAY_WA_16011342517)) {
drivers/gpu/drm/i915/display/intel_ddi.c
1410
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
1413
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
1418
intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
drivers/gpu/drm/i915/display/intel_ddi.c
1422
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
1432
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
144
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1440
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
1443
if (display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/intel_ddi.c
1459
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
1470
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
148
if (has_iboost(display) &&
drivers/gpu/drm/i915/display/intel_ddi.c
1483
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_ddi.c
1510
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1515
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1524
if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))
drivers/gpu/drm/i915/display/intel_ddi.c
153
intel_de_write(display, DDI_BUF_TRANS_LO(port, i),
drivers/gpu/drm/i915/display/intel_ddi.c
1534
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1540
if (has_iboost(display))
drivers/gpu/drm/i915/display/intel_ddi.c
1549
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
drivers/gpu/drm/i915/display/intel_ddi.c
155
intel_de_write(display, DDI_BUF_TRANS_HI(port, i),
drivers/gpu/drm/i915/display/intel_ddi.c
1555
intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);
drivers/gpu/drm/i915/display/intel_ddi.c
1556
intel_de_posting_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1559
static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_ddi.c
1562
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1564
intel_de_rmw(display, reg, clk_sel_mask, clk_sel);
drivers/gpu/drm/i915/display/intel_ddi.c
1570
intel_de_rmw(display, reg, clk_off, 0);
drivers/gpu/drm/i915/display/intel_ddi.c
1572
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1575
static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_ddi.c
1578
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1580
intel_de_rmw(display, reg, 0, clk_off);
drivers/gpu/drm/i915/display/intel_ddi.c
1582
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1585
static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_ddi.c
1588
return !(intel_de_read(display, reg) & clk_off);
drivers/gpu/drm/i915/display/intel_ddi.c
1592
_icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_ddi.c
1597
id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
drivers/gpu/drm/i915/display/intel_ddi.c
1599
return intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_ddi.c
1605
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1609
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1612
_icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1620
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1623
_icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1629
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1632
return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1638
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1641
return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1649
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1653
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1656
_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1664
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1667
_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1673
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1676
return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
168
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1682
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1685
return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1693
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1697
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1704
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
1709
_icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1717
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1720
_icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1726
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1729
return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1735
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1740
val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
drivers/gpu/drm/i915/display/intel_ddi.c
1753
return intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_ddi.c
1759
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
176
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_ddi.c
1763
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1766
_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1774
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1777
_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1783
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1786
return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1792
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1795
return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
180
if (has_iboost(display) &&
drivers/gpu/drm/i915/display/intel_ddi.c
1803
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1807
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1814
intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
drivers/gpu/drm/i915/display/intel_ddi.c
1821
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1826
intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
drivers/gpu/drm/i915/display/intel_ddi.c
1831
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1835
tmp = intel_de_read(display, DDI_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1846
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
185
intel_de_write(display, DDI_BUF_TRANS_LO(port, 9),
drivers/gpu/drm/i915/display/intel_ddi.c
1851
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1854
intel_de_write(display, DDI_CLK_SEL(port),
drivers/gpu/drm/i915/display/intel_ddi.c
1857
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1859
intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1862
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1867
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
187
intel_de_write(display, DDI_BUF_TRANS_HI(port, 9),
drivers/gpu/drm/i915/display/intel_ddi.c
1871
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1873
intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
drivers/gpu/drm/i915/display/intel_ddi.c
1876
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1878
intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
drivers/gpu/drm/i915/display/intel_ddi.c
1883
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1888
tmp = intel_de_read(display, DDI_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1893
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
drivers/gpu/drm/i915/display/intel_ddi.c
1900
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1906
tmp = intel_de_read(display, DDI_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
191
static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
1925
return intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_ddi.c
193
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
1930
struct intel_display *display = to_intel_display(encoder->base.dev);
drivers/gpu/drm/i915/display/intel_ddi.c
194
return XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
1948
return intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_ddi.c
1954
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1958
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1961
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1963
intel_de_rmw(display, DPLL_CTRL2,
drivers/gpu/drm/i915/display/intel_ddi.c
1969
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1974
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
1977
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1979
intel_de_rmw(display, DPLL_CTRL2,
drivers/gpu/drm/i915/display/intel_ddi.c
1982
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_ddi.c
1987
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
199
void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
1994
return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
drivers/gpu/drm/i915/display/intel_ddi.c
1999
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2004
tmp = intel_de_read(display, DPLL_CTRL2);
drivers/gpu/drm/i915/display/intel_ddi.c
2016
return intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_ddi.c
2022
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2026
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
2029
intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
drivers/gpu/drm/i915/display/intel_ddi.c
2034
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2037
intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
drivers/gpu/drm/i915/display/intel_ddi.c
2042
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2045
return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
drivers/gpu/drm/i915/display/intel_ddi.c
2050
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2055
tmp = intel_de_read(display, PORT_CLK_SEL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
2083
return intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_ddi.c
209
if (display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_ddi.c
2101
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2121
if (drm_WARN_ON(display->drm, is_mst))
drivers/gpu/drm/i915/display/intel_ddi.c
2136
for_each_intel_encoder(display->drm, other_encoder) {
drivers/gpu/drm/i915/display/intel_ddi.c
2140
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
215
if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port),
drivers/gpu/drm/i915/display/intel_ddi.c
2155
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
2163
tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi.c
2166
if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
drivers/gpu/drm/i915/display/intel_ddi.c
2167
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
drivers/gpu/drm/i915/display/intel_ddi.c
2168
if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
drivers/gpu/drm/i915/display/intel_ddi.c
2169
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
drivers/gpu/drm/i915/display/intel_ddi.c
217
drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",
drivers/gpu/drm/i915/display/intel_ddi.c
2176
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
2182
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
2189
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
2190
ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
drivers/gpu/drm/i915/display/intel_ddi.c
2191
ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
drivers/gpu/drm/i915/display/intel_ddi.c
2193
ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
drivers/gpu/drm/i915/display/intel_ddi.c
2194
ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
drivers/gpu/drm/i915/display/intel_ddi.c
2206
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
223
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2251
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
2252
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
drivers/gpu/drm/i915/display/intel_ddi.c
2253
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
drivers/gpu/drm/i915/display/intel_ddi.c
2255
if (IS_DISPLAY_VER(display, 12, 13))
drivers/gpu/drm/i915/display/intel_ddi.c
2256
tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
drivers/gpu/drm/i915/display/intel_ddi.c
2259
intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
drivers/gpu/drm/i915/display/intel_ddi.c
2260
intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
drivers/gpu/drm/i915/display/intel_ddi.c
2276
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2278
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
2279
return TGL_DP_TP_CTL(display,
drivers/gpu/drm/i915/display/intel_ddi.c
2288
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2290
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
2291
return TGL_DP_TP_STATUS(display,
drivers/gpu/drm/i915/display/intel_ddi.c
2300
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2302
intel_de_write(display, dp_tp_status_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2309
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2311
if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2313
drm_err(display->drm, "Timed out waiting for ACT sent\n");
drivers/gpu/drm/i915/display/intel_ddi.c
2320
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
2327
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
2336
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
234
if (DISPLAY_VER(display) < 10) {
drivers/gpu/drm/i915/display/intel_ddi.c
2343
drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",
drivers/gpu/drm/i915/display/intel_ddi.c
2349
drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");
drivers/gpu/drm/i915/display/intel_ddi.c
2354
struct intel_display *display = to_intel_display(aux->drm_dev);
drivers/gpu/drm/i915/display/intel_ddi.c
2366
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
2379
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2387
ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2390
ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2394
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
240
if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port),
drivers/gpu/drm/i915/display/intel_ddi.c
2415
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
242
drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",
drivers/gpu/drm/i915/display/intel_ddi.c
2422
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2425
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/intel_ddi.c
2433
drm_dbg_kms(display->drm, "Retry FEC enabling\n");
drivers/gpu/drm/i915/display/intel_ddi.c
2435
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2442
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2450
drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n");
drivers/gpu/drm/i915/display/intel_ddi.c
2456
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2461
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
2463
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
2469
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2475
intel_combo_phy_power_up_lanes(display, phy, false,
drivers/gpu/drm/i915/display/intel_ddi.c
2485
static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_ddi.c
2487
if (DISPLAY_VER(display) > 20)
drivers/gpu/drm/i915/display/intel_ddi.c
2489
else if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_ddi.c
2498
struct intel_display *display = to_intel_display(pipe_config);
drivers/gpu/drm/i915/display/intel_ddi.c
2503
if (!HAS_MSO(display))
drivers/gpu/drm/i915/display/intel_ddi.c
2506
dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_ddi.c
2512
if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {
drivers/gpu/drm/i915/display/intel_ddi.c
2519
drm_WARN(display->drm, true,
drivers/gpu/drm/i915/display/intel_ddi.c
2535
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
2540
if (!HAS_MSO(display))
drivers/gpu/drm/i915/display/intel_ddi.c
2552
intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
drivers/gpu/drm/i915/display/intel_ddi.c
2560
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2566
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_ddi.c
2569
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_ddi.c
2574
reg = XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
2579
intel_de_rmw(display, reg, 0, set_bits);
drivers/gpu/drm/i915/display/intel_ddi.c
2581
ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100);
drivers/gpu/drm/i915/display/intel_ddi.c
2583
drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
drivers/gpu/drm/i915/display/intel_ddi.c
2591
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2606
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
drivers/gpu/drm/i915/display/intel_ddi.c
2613
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2619
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
drivers/gpu/drm/i915/display/intel_ddi.c
2743
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2788
drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
2789
dig_port->ddi_io_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_ddi.c
2890
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2896
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_ddi.c
2897
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
2900
drm_WARN_ON(display->drm, is_mst && port == PORT_A);
drivers/gpu/drm/i915/display/intel_ddi.c
2917
drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
2918
dig_port->ddi_io_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_ddi.c
2924
if (has_buf_trans_select(display))
drivers/gpu/drm/i915/display/intel_ddi.c
2940
if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&
drivers/gpu/drm/i915/display/intel_ddi.c
2957
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2959
if (HAS_DP20(display))
drivers/gpu/drm/i915/display/intel_ddi.c
2966
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
2968
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
2985
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
2992
drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
2993
dig_port->ddi_io_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3028
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_ddi.c
3032
drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3034
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_ddi.c
3057
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3063
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_ddi.c
3066
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_ddi.c
3071
reg = XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
3076
intel_de_rmw(display, reg, clr_bits, 0);
drivers/gpu/drm/i915/display/intel_ddi.c
3078
ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100);
drivers/gpu/drm/i915/display/intel_ddi.c
3080
drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
drivers/gpu/drm/i915/display/intel_ddi.c
3086
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3089
intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);
drivers/gpu/drm/i915/display/intel_ddi.c
3090
intel_de_posting_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
3098
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3101
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_ddi.c
3103
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
3104
intel_wait_ddi_buf_idle(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
3109
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
3115
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_ddi.c
3116
intel_wait_ddi_buf_idle(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
3126
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3143
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
3147
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3148
TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
3168
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
3177
intel_display_power_put(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3184
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
3185
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
drivers/gpu/drm/i915/display/intel_ddi.c
3194
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3202
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_ddi.c
3207
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
3212
intel_display_power_put(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3226
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3231
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
drivers/gpu/drm/i915/display/intel_ddi.c
3247
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
3258
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
drivers/gpu/drm/i915/display/intel_ddi.c
3264
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_ddi.c
3366
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3371
if (port == PORT_A && DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_ddi.c
3386
gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
3396
drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);
drivers/gpu/drm/i915/display/intel_ddi.c
3398
if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))
drivers/gpu/drm/i915/display/intel_ddi.c
3401
return CHICKEN_TRANS(display, trans[port]);
drivers/gpu/drm/i915/display/intel_ddi.c
3409
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3418
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
3422
if (has_buf_trans_select(display))
drivers/gpu/drm/i915/display/intel_ddi.c
3431
if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_ddi.c
3438
intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
3441
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_ddi.c
3450
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_ddi.c
3451
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_ddi.c
3462
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_ddi.c
3483
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_ddi.c
3491
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
drivers/gpu/drm/i915/display/intel_ddi.c
3496
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_ddi.c
3498
} else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
drivers/gpu/drm/i915/display/intel_ddi.c
3499
drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port));
drivers/gpu/drm/i915/display/intel_ddi.c
3511
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3521
intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
3523
intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
3537
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
drivers/gpu/drm/i915/display/intel_ddi.c
3548
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
drivers/gpu/drm/i915/display/intel_ddi.c
356
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3592
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3597
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
3661
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3667
if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)
drivers/gpu/drm/i915/display/intel_ddi.c
3670
for_each_intel_crtc_in_pipe_mask(display, pipe_crtc,
drivers/gpu/drm/i915/display/intel_ddi.c
3686
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
369
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_ddi.c
3705
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_ddi.c
3714
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
3720
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3725
intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
drivers/gpu/drm/i915/display/intel_ddi.c
3732
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
3741
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3743
drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
drivers/gpu/drm/i915/display/intel_ddi.c
3755
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
drivers/gpu/drm/i915/display/intel_ddi.c
3756
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
376
if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
drivers/gpu/drm/i915/display/intel_ddi.c
3768
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_ddi.c
3790
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
3795
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3797
drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
drivers/gpu/drm/i915/display/intel_ddi.c
3808
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
drivers/gpu/drm/i915/display/intel_ddi.c
3809
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3811
if (display->platform.alderlake_p &&
drivers/gpu/drm/i915/display/intel_ddi.c
382
if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
drivers/gpu/drm/i915/display/intel_ddi.c
3823
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
3827
temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
drivers/gpu/drm/i915/display/intel_ddi.c
3848
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);
drivers/gpu/drm/i915/display/intel_ddi.c
3854
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_ddi.c
3858
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_ddi.c
3868
if (port == PORT_A && DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_ddi.c
3871
if (intel_de_wait_for_set_ms(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3874
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
3878
static bool intel_ddi_is_audio_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi.c
3884
if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO))
drivers/gpu/drm/i915/display/intel_ddi.c
3887
return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &
drivers/gpu/drm/i915/display/intel_ddi.c
389
static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
391
u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
drivers/gpu/drm/i915/display/intel_ddi.c
3917
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
3919
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
3921
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
3923
else if (display->platform.jasperlake || display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_ddi.c
3925
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_ddi.c
3929
static enum transcoder bdw_transcoder_master_readout(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi.c
3934
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_ddi.c
3935
u32 ctl2 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3936
TRANS_DDI_FUNC_CTL2(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
3943
u32 ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3944
TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
3960
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
3966
bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3968
for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) {
drivers/gpu/drm/i915/display/intel_ddi.c
3973
trans_wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_ddi.c
3979
if (bdw_transcoder_master_readout(display, cpu_transcoder) ==
drivers/gpu/drm/i915/display/intel_ddi.c
3983
intel_display_power_put(display, power_domain, trans_wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
3986
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
3995
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
3998
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
4029
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4033
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
drivers/gpu/drm/i915/display/intel_ddi.c
4041
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4053
if (DISPLAY_VER(display) >= 12 &&
drivers/gpu/drm/i915/display/intel_ddi.c
4062
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
drivers/gpu/drm/i915/display/intel_ddi.c
4065
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_ddi.c
4067
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
4082
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4090
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
4096
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_ddi.c
4098
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
4108
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4112
ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
4147
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
drivers/gpu/drm/i915/display/intel_ddi.c
4153
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
drivers/gpu/drm/i915/display/intel_ddi.c
4175
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4179
if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)))
drivers/gpu/drm/i915/display/intel_ddi.c
4187
intel_ddi_is_audio_enabled(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4194
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_ddi.c
4215
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_ddi.c
423
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4231
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4236
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4240
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4241
drm_WARN_ON(display->drm, !pll_active);
drivers/gpu/drm/i915/display/intel_ddi.c
4245
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
drivers/gpu/drm/i915/display/intel_ddi.c
4259
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4265
pll = intel_get_dpll_by_id(display, pll_id);
drivers/gpu/drm/i915/display/intel_ddi.c
4267
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4271
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4272
drm_WARN_ON(display->drm, !pll_active);
drivers/gpu/drm/i915/display/intel_ddi.c
4279
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
drivers/gpu/drm/i915/display/intel_ddi.c
4294
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4297
mtl_port_to_pll_id(display, encoder->port));
drivers/gpu/drm/i915/display/intel_ddi.c
430
drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
4303
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4310
mtl_port_to_pll_id(display, encoder->port));
drivers/gpu/drm/i915/display/intel_ddi.c
4354
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4357
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4380
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4385
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4396
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4397
drm_WARN_ON(display->drm, !pll_active);
drivers/gpu/drm/i915/display/intel_ddi.c
4402
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
drivers/gpu/drm/i915/display/intel_ddi.c
4404
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
drivers/gpu/drm/i915/display/intel_ddi.c
4451
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4455
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
drivers/gpu/drm/i915/display/intel_ddi.c
4490
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4495
if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
drivers/gpu/drm/i915/display/intel_ddi.c
4510
if (display->platform.haswell && crtc->pipe == PIPE_A &&
drivers/gpu/drm/i915/display/intel_ddi.c
4516
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_ddi.c
453
drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
drivers/gpu/drm/i915/display/intel_ddi.c
4567
struct intel_display *display = to_intel_display(ref_crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4581
if (!IS_DISPLAY_VER(display, 9, 20))
drivers/gpu/drm/i915/display/intel_ddi.c
4613
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4624
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_ddi.c
4652
struct intel_display *display = to_intel_display(encoder->dev);
drivers/gpu/drm/i915/display/intel_ddi.c
4658
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_ddi.c
4696
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_ddi.c
4705
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
4723
privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL);
drivers/gpu/drm/i915/display/intel_ddi.c
4728
drm_warn(display->drm, "Error getting privacy-screen\n");
drivers/gpu/drm/i915/display/intel_ddi.c
4747
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
476
intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
4760
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
drivers/gpu/drm/i915/display/intel_ddi.c
4777
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
4793
drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
drivers/gpu/drm/i915/display/intel_ddi.c
4813
return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);
drivers/gpu/drm/i915/display/intel_ddi.c
4818
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4822
drm_WARN_ON(display->drm, !dig_port->dp.attached_connector);
drivers/gpu/drm/i915/display/intel_ddi.c
4885
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4886
u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_ddi.c
4888
return intel_de_read(display, SDEISR) & bit;
drivers/gpu/drm/i915/display/intel_ddi.c
4893
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4894
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_ddi.c
4896
return intel_de_read(display, DEISR) & bit;
drivers/gpu/drm/i915/display/intel_ddi.c
4901
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
4902
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_ddi.c
4904
return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;
drivers/gpu/drm/i915/display/intel_ddi.c
492
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4933
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_ddi.c
4944
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_ddi.c
4953
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_ddi.c
4957
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_ddi.c
496
if (!HAS_DP20(display))
drivers/gpu/drm/i915/display/intel_ddi.c
4961
if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_ddi.c
4974
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
4983
static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
4993
static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5001
static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5009
static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5011
if (HAS_PCH_TGP(display))
drivers/gpu/drm/i915/display/intel_ddi.c
5012
return tgl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
502
intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_ddi.c
5020
static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5028
static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5033
if (HAS_PCH_TGP(display))
drivers/gpu/drm/i915/display/intel_ddi.c
5034
return icl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5039
static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5041
if (HAS_PCH_TGP(display))
drivers/gpu/drm/i915/display/intel_ddi.c
5042
return icl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5047
static bool intel_ddi_is_tc(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5049
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
5051
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_ddi.c
5094
static bool port_strap_detected(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5097
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_ddi.c
5102
return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5104
return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5106
return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5108
return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
drivers/gpu/drm/i915/display/intel_ddi.c
5122
static bool assert_has_icl_dsi(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_ddi.c
5124
return !drm_WARN(display->drm, !display->platform.alderlake_p &&
drivers/gpu/drm/i915/display/intel_ddi.c
5125
!display->platform.tigerlake && DISPLAY_VER(display) != 11,
drivers/gpu/drm/i915/display/intel_ddi.c
5129
static bool port_in_use(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5133
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_ddi.c
5142
static const char *intel_ddi_encoder_name(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi.c
5146
if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) {
drivers/gpu/drm/i915/display/intel_ddi.c
515
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
5150
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
5151
enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5158
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_ddi.c
5159
enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5170
drm_WARN_ON(display->drm, seq_buf_has_overflowed(s));
drivers/gpu/drm/i915/display/intel_ddi.c
5175
void intel_ddi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi.c
5190
if (!port_strap_detected(display, port)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5191
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
5196
if (!assert_port_valid(display, port))
drivers/gpu/drm/i915/display/intel_ddi.c
5199
if (port_in_use(display, port)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5200
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
5207
if (!assert_has_icl_dsi(display))
drivers/gpu/drm/i915/display/intel_ddi.c
5210
icl_dsi_init(display, devdata);
drivers/gpu/drm/i915/display/intel_ddi.c
5214
phy = intel_port_to_phy(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5222
if (intel_hti_uses_phy(display, phy)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5223
drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n",
drivers/gpu/drm/i915/display/intel_ddi.c
524
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
5240
drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n",
drivers/gpu/drm/i915/display/intel_ddi.c
5245
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
5251
if (intel_phy_is_snps(display, phy) &&
drivers/gpu/drm/i915/display/intel_ddi.c
5252
display->snps.phy_failed_calibration & BIT(phy)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5253
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
5265
drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs,
drivers/gpu/drm/i915/display/intel_ddi.c
5267
intel_ddi_encoder_name(display, port, phy, &encoder_name));
drivers/gpu/drm/i915/display/intel_ddi.c
5292
encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5297
if (HAS_LT_PHY(display)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5305
} else if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_ddi.c
5313
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_ddi.c
5317
} else if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_ddi.c
5322
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_ddi.c
5327
} else if (display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_ddi.c
5332
} else if (display->platform.jasperlake || display->platform.elkhartlake) {
drivers/gpu/drm/i915/display/intel_ddi.c
5333
if (intel_ddi_is_tc(display, port)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5345
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_ddi.c
5346
if (intel_ddi_is_tc(display, port)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5358
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_ddi.c
5361
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_ddi.c
5366
} else if (display->platform.broadwell || display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_ddi.c
5373
if (HAS_LT_PHY(display)) {
drivers/gpu/drm/i915/display/intel_ddi.c
5375
} else if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_ddi.c
5377
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_ddi.c
5379
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
5384
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_ddi.c
5389
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_ddi.c
5397
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_ddi.c
5398
encoder->hpd_pin = xelpd_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5399
else if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_ddi.c
5400
encoder->hpd_pin = dg1_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5401
else if (display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_ddi.c
5402
encoder->hpd_pin = rkl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5403
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_ddi.c
5404
encoder->hpd_pin = tgl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5405
else if (display->platform.jasperlake || display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_ddi.c
5406
encoder->hpd_pin = ehl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5407
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_ddi.c
5408
encoder->hpd_pin = icl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5409
else if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
drivers/gpu/drm/i915/display/intel_ddi.c
5410
encoder->hpd_pin = skl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5414
ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
5419
dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;
drivers/gpu/drm/i915/display/intel_ddi.c
5448
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
5465
drm_WARN_ON(display->drm, port > PORT_I);
drivers/gpu/drm/i915/display/intel_ddi.c
5466
dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5468
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_ddi.c
5473
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_ddi.c
5475
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_ddi.c
5477
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_ddi.c
5482
} else if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_ddi.c
5498
encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display);
drivers/gpu/drm/i915/display/intel_ddi.c
586
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_ddi.c
599
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
603
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
613
if (IS_DISPLAY_VER(display, 8, 10) &&
drivers/gpu/drm/i915/display/intel_ddi.c
628
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
631
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_ddi.c
643
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_ddi.c
644
TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
648
intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
662
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
670
intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
682
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_ddi.c
687
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_ddi.c
688
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_ddi.c
689
TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
692
ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
693
TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
699
if (IS_DISPLAY_VER(display, 8, 10))
drivers/gpu/drm/i915/display/intel_ddi.c
703
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
712
intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
718
if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
drivers/gpu/drm/i915/display/intel_ddi.c
720
drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");
drivers/gpu/drm/i915/display/intel_ddi.c
730
struct intel_display *display = to_intel_display(intel_encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
734
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_ddi.c
736
if (drm_WARN_ON(display->drm, !wakeref))
drivers/gpu/drm/i915/display/intel_ddi.c
739
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
741
intel_display_power_put(display, intel_encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
747
struct intel_display *display = to_intel_display(intel_connector);
drivers/gpu/drm/i915/display/intel_ddi.c
757
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_ddi.c
768
if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
drivers/gpu/drm/i915/display/intel_ddi.c
773
ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
drivers/gpu/drm/i915/display/intel_ddi.c
779
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
drivers/gpu/drm/i915/display/intel_ddi.c
784
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
drivers/gpu/drm/i915/display/intel_ddi.c
790
} else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {
drivers/gpu/drm/i915/display/intel_ddi.c
798
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
806
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi.c
816
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_ddi.c
821
tmp = intel_de_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
825
if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {
drivers/gpu/drm/i915/display/intel_ddi.c
826
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
827
TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/display/intel_ddi.c
848
for_each_pipe(display, p) {
drivers/gpu/drm/i915/display/intel_ddi.c
853
trans_wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_ddi.c
858
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi.c
866
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_ddi.c
867
TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_ddi.c
868
intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_ddi.c
878
else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
drivers/gpu/drm/i915/display/intel_ddi.c
885
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
908
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
916
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
924
if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) {
drivers/gpu/drm/i915/display/intel_ddi.c
925
tmp = intel_de_read(display, BXT_PHY_CTL(port));
drivers/gpu/drm/i915/display/intel_ddi.c
929
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_ddi.c
934
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
957
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_ddi.c
973
return intel_display_power_aux_io_domain(display, dig_port->aux_ch);
drivers/gpu/drm/i915/display/intel_ddi.c
974
else if (DISPLAY_VER(display) < 14 &&
drivers/gpu/drm/i915/display/intel_ddi.c
986
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_ddi.c
990
drm_WARN_ON(display->drm, dig_port->aux_wakeref);
drivers/gpu/drm/i915/display/intel_ddi.c
995
dig_port->aux_wakeref = intel_display_power_get(display, domain);
drivers/gpu/drm/i915/display/intel_ddi.h
56
void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_ddi.h
57
void intel_ddi_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1474
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1477
if (display->platform.tigerlake_uy) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1789
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1791
if (HAS_LT_PHY(display)) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1793
} else if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1798
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1800
} else if (display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1805
} else if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1807
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1809
} else if (display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1811
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1816
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1817
if (display->platform.jasperlake)
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1819
else if (display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1825
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1827
} else if (display->platform.cometlake_ulx ||
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1828
display->platform.coffeelake_ulx ||
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1829
display->platform.kabylake_ulx) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1831
} else if (display->platform.cometlake_ult ||
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1832
display->platform.coffeelake_ult ||
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1833
display->platform.kabylake_ult) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1835
} else if (display->platform.cometlake ||
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1836
display->platform.coffeelake ||
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1837
display->platform.kabylake) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1839
} else if (display->platform.skylake_ulx) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1841
} else if (display->platform.skylake_ult) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1843
} else if (display->platform.skylake) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1845
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1847
} else if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
1850
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_de.c
103
int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
109
intel_dmc_wl_get(display, reg);
drivers/gpu/drm/i915/display/intel_de.c
111
ret = intel_de_wait_for_register(display, reg, mask, value,
drivers/gpu/drm/i915/display/intel_de.c
116
intel_dmc_wl_put(display, reg);
drivers/gpu/drm/i915/display/intel_de.c
12
static int __intel_de_wait_for_register(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_de.c
121
int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
125
return intel_de_wait_for_register(display, reg, mask, value,
drivers/gpu/drm/i915/display/intel_de.c
131
int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
135
return intel_de_wait_for_register(display, reg, mask, value,
drivers/gpu/drm/i915/display/intel_de.c
141
int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
144
return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
drivers/gpu/drm/i915/display/intel_de.c
147
int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
15
u32 (*read)(struct intel_display *display, intel_reg_t reg),
drivers/gpu/drm/i915/display/intel_de.c
150
return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
drivers/gpu/drm/i915/display/intel_de.c
153
int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
156
return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
drivers/gpu/drm/i915/display/intel_de.c
159
int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
162
return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
drivers/gpu/drm/i915/display/intel_de.c
165
u8 intel_de_read8(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.c
168
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
drivers/gpu/drm/i915/display/intel_de.c
170
return intel_uncore_read8(__to_uncore(display), reg);
drivers/gpu/drm/i915/display/intel_de.c
173
void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val)
drivers/gpu/drm/i915/display/intel_de.c
175
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
drivers/gpu/drm/i915/display/intel_de.c
177
intel_uncore_write8(__to_uncore(display), reg, val);
drivers/gpu/drm/i915/display/intel_de.c
180
u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.c
183
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 6);
drivers/gpu/drm/i915/display/intel_de.c
185
return intel_uncore_read16(__to_uncore(display), reg);
drivers/gpu/drm/i915/display/intel_de.c
37
reg_value = read(display, reg);
drivers/gpu/drm/i915/display/intel_de.c
63
static int intel_de_wait_for_register(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_de.c
67
u32 (*read)(struct intel_display *display, intel_reg_t reg),
drivers/gpu/drm/i915/display/intel_de.c
73
ret = __intel_de_wait_for_register(display, reg, mask, value,
drivers/gpu/drm/i915/display/intel_de.c
78
ret = __intel_de_wait_for_register(display, reg, mask, value,
drivers/gpu/drm/i915/display/intel_de.c
85
int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.c
91
intel_dmc_wl_get(display, reg);
drivers/gpu/drm/i915/display/intel_de.c
93
ret = intel_de_wait_for_register(display, reg, mask, value,
drivers/gpu/drm/i915/display/intel_de.c
98
intel_dmc_wl_put(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
102
int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
105
int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
108
int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
111
int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
114
int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
116
int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
118
int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
120
int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
drivers/gpu/drm/i915/display/intel_de.h
132
intel_de_read_fw(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.h
136
val = intel_uncore_read_fw(__to_uncore(display), reg);
drivers/gpu/drm/i915/display/intel_de.h
143
intel_de_write_fw(struct intel_display *display, intel_reg_t reg, u32 val)
drivers/gpu/drm/i915/display/intel_de.h
146
intel_uncore_write_fw(__to_uncore(display), reg, val);
drivers/gpu/drm/i915/display/intel_de.h
15
static inline struct intel_uncore *__to_uncore(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_de.h
150
intel_de_rmw_fw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
drivers/gpu/drm/i915/display/intel_de.h
154
old = intel_de_read_fw(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
156
intel_de_write_fw(display, reg, val);
drivers/gpu/drm/i915/display/intel_de.h
162
intel_de_read_notrace(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.h
164
return intel_uncore_read_notrace(__to_uncore(display), reg);
drivers/gpu/drm/i915/display/intel_de.h
168
intel_de_write_notrace(struct intel_display *display, intel_reg_t reg, u32 val)
drivers/gpu/drm/i915/display/intel_de.h
17
return to_intel_uncore(display->drm);
drivers/gpu/drm/i915/display/intel_de.h
170
intel_uncore_write_notrace(__to_uncore(display), reg, val);
drivers/gpu/drm/i915/display/intel_de.h
174
intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
drivers/gpu/drm/i915/display/intel_de.h
180
intel_de_write_fw(display, reg, val);
drivers/gpu/drm/i915/display/intel_de.h
20
u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_de.h
21
void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
drivers/gpu/drm/i915/display/intel_de.h
22
u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_de.h
25
intel_de_read(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.h
29
intel_dmc_wl_get(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
31
val = intel_uncore_read(__to_uncore(display), reg);
drivers/gpu/drm/i915/display/intel_de.h
33
intel_dmc_wl_put(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
39
intel_de_read64_2x32_volatile(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_de.h
44
intel_dmc_wl_get(display, lower_reg);
drivers/gpu/drm/i915/display/intel_de.h
45
intel_dmc_wl_get(display, upper_reg);
drivers/gpu/drm/i915/display/intel_de.h
47
val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
drivers/gpu/drm/i915/display/intel_de.h
50
intel_dmc_wl_put(display, upper_reg);
drivers/gpu/drm/i915/display/intel_de.h
51
intel_dmc_wl_put(display, lower_reg);
drivers/gpu/drm/i915/display/intel_de.h
57
intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.h
62
lower = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
63
upper = intel_de_read(display, upper_reg);
drivers/gpu/drm/i915/display/intel_de.h
69
intel_de_posting_read(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_de.h
71
intel_dmc_wl_get(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
73
intel_uncore_posting_read(__to_uncore(display), reg);
drivers/gpu/drm/i915/display/intel_de.h
75
intel_dmc_wl_put(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
79
intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
drivers/gpu/drm/i915/display/intel_de.h
81
intel_dmc_wl_get(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
83
intel_uncore_write(__to_uncore(display), reg, val);
drivers/gpu/drm/i915/display/intel_de.h
85
intel_dmc_wl_put(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
89
intel_de_rmw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
drivers/gpu/drm/i915/display/intel_de.h
93
intel_dmc_wl_get(display, reg);
drivers/gpu/drm/i915/display/intel_de.h
95
val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
drivers/gpu/drm/i915/display/intel_de.h
97
intel_dmc_wl_put(display, reg);
drivers/gpu/drm/i915/display/intel_display.c
1040
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
1047
intel_frontbuffer_flip(display, new_crtc_state->fb_bits);
drivers/gpu/drm/i915/display/intel_display.c
1050
intel_update_watermarks(display);
drivers/gpu/drm/i915/display/intel_display.c
1056
intel_async_flip_vtd_wa(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1060
skl_wa_827(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1064
icl_wa_scalerclkgating(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1068
icl_wa_cursorclkgating(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1076
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503117)) {
drivers/gpu/drm/i915/display/intel_display.c
1172
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
1203
intel_async_flip_vtd_wa(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1208
skl_wa_827(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1213
icl_wa_scalerclkgating(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1218
icl_wa_cursorclkgating(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1229
if (HAS_GMCH(display) && old_crtc_state->hw.active &&
drivers/gpu/drm/i915/display/intel_display.c
1230
new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))
drivers/gpu/drm/i915/display/intel_display.c
1240
if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
drivers/gpu/drm/i915/display/intel_display.c
1241
new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
drivers/gpu/drm/i915/display/intel_display.c
1265
intel_update_watermarks(display);
drivers/gpu/drm/i915/display/intel_display.c
1276
if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
drivers/gpu/drm/i915/display/intel_display.c
1277
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1290
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
1312
intel_frontbuffer_flip(display, fb_bits);
drivers/gpu/drm/i915/display/intel_display.c
1317
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
1325
if (display->dpll.mgr) {
drivers/gpu/drm/i915/display/intel_display.c
149
skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)
drivers/gpu/drm/i915/display/intel_display.c
151
intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
drivers/gpu/drm/i915/display/intel_display.c
1515
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
1520
if (drm_WARN_ON(display->drm, crtc->active))
drivers/gpu/drm/i915/display/intel_display.c
1533
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1534
intel_set_pch_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1547
assert_fdi_tx_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
1548
assert_fdi_rx_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
1569
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_display.c
158
icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_display.c
1582
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1583
intel_set_pch_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1589
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
1591
return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
drivers/gpu/drm/i915/display/intel_display.c
1596
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
1599
intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),
drivers/gpu/drm/i915/display/intel_display.c
1605
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
1608
intel_de_write(display, WM_LINETIME(crtc->pipe),
drivers/gpu/drm/i915/display/intel_display.c
161
intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
drivers/gpu/drm/i915/display/intel_display.c
1615
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
1617
intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
1624
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
1641
intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
1652
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
1658
if (drm_WARN_ON(display->drm, crtc->active))
drivers/gpu/drm/i915/display/intel_display.c
1660
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) {
drivers/gpu/drm/i915/display/intel_display.c
1674
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) {
drivers/gpu/drm/i915/display/intel_display.c
168
icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_display.c
1680
if (HAS_UNCOMPRESSED_JOINER(display))
drivers/gpu/drm/i915/display/intel_display.c
1685
if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_display.c
1692
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) {
drivers/gpu/drm/i915/display/intel_display.c
1701
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display.c
171
intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
drivers/gpu/drm/i915/display/intel_display.c
1714
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display.c
1722
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state) {
drivers/gpu/drm/i915/display/intel_display.c
1737
if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {
drivers/gpu/drm/i915/display/intel_display.c
1739
intel_crtc_for_pipe(display, hsw_workaround_pipe);
drivers/gpu/drm/i915/display/intel_display.c
1750
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
1760
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1761
intel_set_pch_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
1779
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1780
intel_set_pch_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
1786
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
1802
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
drivers/gpu/drm/i915/display/intel_display.c
1811
bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_display.c
1815
else if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_display.c
1817
else if (display->platform.dg1 || display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_display.c
1819
else if (display->platform.jasperlake || display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_display.c
1821
else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))
drivers/gpu/drm/i915/display/intel_display.c
1843
bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_display.c
1849
if (display->platform.dgfx)
drivers/gpu/drm/i915/display/intel_display.c
1852
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_display.c
1854
else if (display->platform.tigerlake)
drivers/gpu/drm/i915/display/intel_display.c
1856
else if (display->platform.icelake)
drivers/gpu/drm/i915/display/intel_display.c
1863
bool intel_phy_is_snps(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_display.c
1869
return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;
drivers/gpu/drm/i915/display/intel_display.c
1873
enum phy intel_port_to_phy(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display.c
1875
if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)
drivers/gpu/drm/i915/display/intel_display.c
1877
else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)
drivers/gpu/drm/i915/display/intel_display.c
1879
else if (display->platform.alderlake_s && port >= PORT_TC1)
drivers/gpu/drm/i915/display/intel_display.c
1881
else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)
drivers/gpu/drm/i915/display/intel_display.c
1883
else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_display.c
1896
enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display.c
1898
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display.c
1909
enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display.c
1911
if (!intel_phy_is_tc(display, intel_port_to_phy(display, port)))
drivers/gpu/drm/i915/display/intel_display.c
1914
return intel_port_to_tc(display, port);
drivers/gpu/drm/i915/display/intel_display.c
1919
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
1921
return intel_port_to_phy(display, encoder->port);
drivers/gpu/drm/i915/display/intel_display.c
1926
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
1928
return intel_phy_is_combo(display, intel_encoder_to_phy(encoder));
drivers/gpu/drm/i915/display/intel_display.c
1933
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
1935
return intel_phy_is_snps(display, intel_encoder_to_phy(encoder));
drivers/gpu/drm/i915/display/intel_display.c
1940
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
1946
return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
drivers/gpu/drm/i915/display/intel_display.c
1951
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
1953
return intel_tc_phy_port_to_tc(display, encoder->port);
drivers/gpu/drm/i915/display/intel_display.c
1959
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_display.c
1962
return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);
drivers/gpu/drm/i915/display/intel_display.c
1964
return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
drivers/gpu/drm/i915/display/intel_display.c
1970
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
1987
drm_for_each_encoder_mask(encoder, display->drm,
drivers/gpu/drm/i915/display/intel_display.c
1994
if (HAS_DDI(display) && crtc_state->has_audio)
drivers/gpu/drm/i915/display/intel_display.c
2007
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2024
intel_display_power_get_in_set(display,
drivers/gpu/drm/i915/display/intel_display.c
2032
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2034
intel_display_power_put_mask_in_set(display,
drivers/gpu/drm/i915/display/intel_display.c
2059
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2064
if (drm_WARN_ON(display->drm, crtc->active))
drivers/gpu/drm/i915/display/intel_display.c
2071
intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0);
drivers/gpu/drm/i915/display/intel_display.c
2073
if (display->platform.cherryview && pipe == PIPE_B) {
drivers/gpu/drm/i915/display/intel_display.c
2074
intel_de_write(display, CHV_BLEND(display, pipe),
drivers/gpu/drm/i915/display/intel_display.c
2076
intel_de_write(display, CHV_CANVAS(display, pipe), 0);
drivers/gpu/drm/i915/display/intel_display.c
2081
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
2085
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
2107
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2112
if (drm_WARN_ON(display->drm, crtc->active))
drivers/gpu/drm/i915/display/intel_display.c
2121
if (DISPLAY_VER(display) != 2)
drivers/gpu/drm/i915/display/intel_display.c
2122
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
2133
intel_update_watermarks(display);
drivers/gpu/drm/i915/display/intel_display.c
2141
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_display.c
2148
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
2157
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_display.c
2171
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
2172
chv_disable_pll(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
2173
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_display.c
2174
vlv_disable_pll(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
2181
if (DISPLAY_VER(display) != 2)
drivers/gpu/drm/i915/display/intel_display.c
2182
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
2184
if (!display->wm.funcs->initial_watermarks)
drivers/gpu/drm/i915/display/intel_display.c
2185
intel_update_watermarks(display);
drivers/gpu/drm/i915/display/intel_display.c
2188
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_display.c
2189
i830_enable_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
2202
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2205
return HAS_DOUBLE_WIDE(display) &&
drivers/gpu/drm/i915/display/intel_display.c
2206
(crtc->pipe == PIPE_A || display->platform.i915g);
drivers/gpu/drm/i915/display/intel_display.c
2253
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2255
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_display.c
2366
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2379
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
2386
intel_is_dual_link_lvds(display)) {
drivers/gpu/drm/i915/display/intel_display.c
2387
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
2399
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2403
int clock_limit = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_display.c
2418
if (DISPLAY_VER(display) < 4) {
drivers/gpu/drm/i915/display/intel_display.c
2419
clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;
drivers/gpu/drm/i915/display/intel_display.c
2427
clock_limit = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_display.c
2433
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
2446
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2449
if (!HAS_DSB(display))
drivers/gpu/drm/i915/display/intel_display.c
2461
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
2473
drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n",
drivers/gpu/drm/i915/display/intel_display.c
2569
void intel_panel_sanitize_ssc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
2577
if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_display.c
2578
bool bios_lvds_use_ssc = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2582
if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
drivers/gpu/drm/i915/display/intel_display.c
2583
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
2586
str_enabled_disabled(display->vbt.lvds_use_ssc));
drivers/gpu/drm/i915/display/intel_display.c
2587
display->vbt.lvds_use_ssc = bios_lvds_use_ssc;
drivers/gpu/drm/i915/display/intel_display.c
2599
void intel_set_m_n(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
2604
intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
drivers/gpu/drm/i915/display/intel_display.c
2605
intel_de_write(display, data_n_reg, m_n->data_n);
drivers/gpu/drm/i915/display/intel_display.c
2606
intel_de_write(display, link_m_reg, m_n->link_m);
drivers/gpu/drm/i915/display/intel_display.c
2611
intel_de_write(display, link_n_reg, m_n->link_n);
drivers/gpu/drm/i915/display/intel_display.c
2614
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
2617
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display.c
2620
return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
drivers/gpu/drm/i915/display/intel_display.c
2627
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2630
if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_display.c
2631
intel_set_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_display.c
2632
PIPE_DATA_M1(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2633
PIPE_DATA_N1(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2634
PIPE_LINK_M1(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2635
PIPE_LINK_N1(display, transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2637
intel_set_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_display.c
2646
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2648
if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
drivers/gpu/drm/i915/display/intel_display.c
2651
intel_set_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_display.c
2652
PIPE_DATA_M2(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2653
PIPE_DATA_N2(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2654
PIPE_LINK_M2(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2655
PIPE_LINK_N2(display, transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2661
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2664
return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
drivers/gpu/drm/i915/display/intel_display.c
2669
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2677
drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2704
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_display.c
2705
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_display.c
2706
TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2714
} else if (DISPLAY_VER(display) == 12) {
drivers/gpu/drm/i915/display/intel_display.c
2719
if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
drivers/gpu/drm/i915/display/intel_display.c
2720
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_display.c
2721
TRANS_VSYNCSHIFT(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2724
intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2727
intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2730
intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2740
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_display.c
2743
intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2746
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2749
intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2757
if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
drivers/gpu/drm/i915/display/intel_display.c
2759
intel_de_write(display, TRANS_VTOTAL(display, pipe),
drivers/gpu/drm/i915/display/intel_display.c
2763
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_display.c
2772
intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2779
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2784
drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2797
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_display.c
2798
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_display.c
2799
TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2807
} else if (DISPLAY_VER(display) == 12) {
drivers/gpu/drm/i915/display/intel_display.c
2816
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2825
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_display.c
2832
intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
2842
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2851
intel_de_write(display, PIPESRC(display, pipe),
drivers/gpu/drm/i915/display/intel_display.c
2857
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2860
if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_display.c
2863
if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_display.c
2864
display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display.c
2865
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2866
TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
drivers/gpu/drm/i915/display/intel_display.c
2868
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2869
TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
drivers/gpu/drm/i915/display/intel_display.c
2875
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2880
tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2885
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2886
TRANS_HBLANK(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2891
tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2895
tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2901
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2902
TRANS_VBLANK(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2906
tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2916
if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
drivers/gpu/drm/i915/display/intel_display.c
2918
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2919
TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
2923
} else if (DISPLAY_VER(display) == 12) {
drivers/gpu/drm/i915/display/intel_display.c
2935
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_display.c
2936
pipe_config->min_hblank = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
2960
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
2963
tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
2974
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
2983
if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))
drivers/gpu/drm/i915/display/intel_display.c
2990
if (display->platform.g4x || display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_display.c
2991
display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_display.c
3015
if (DISPLAY_VER(display) < 4 ||
drivers/gpu/drm/i915/display/intel_display.c
3024
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_display.c
3035
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_display.c
3036
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3042
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3045
tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
3053
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/intel_display.c
3054
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3068
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3076
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_display.c
3080
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3089
if (display->platform.g4x || display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_display.c
3090
display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_display.c
3107
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_display.c
3115
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_display.c
3121
if (HAS_DOUBLE_WIDE(display))
drivers/gpu/drm/i915/display/intel_display.c
3131
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_display.c
3136
} else if (display->platform.i945g || display->platform.i945gm ||
drivers/gpu/drm/i915/display/intel_display.c
3137
display->platform.g33 || display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_display.c
3149
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
3151
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_display.c
3167
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_display.c
3174
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
3216
drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
drivers/gpu/drm/i915/display/intel_display.c
3231
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_display.c
3232
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3237
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
3248
if (display->platform.haswell && crtc_state->dither)
drivers/gpu/drm/i915/display/intel_display.c
3251
if (DISPLAY_VER(display) < 35) {
drivers/gpu/drm/i915/display/intel_display.c
3258
if (display->platform.haswell &&
drivers/gpu/drm/i915/display/intel_display.c
3262
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_display.c
3263
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3269
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
3285
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_display.c
3301
val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :
drivers/gpu/drm/i915/display/intel_display.c
3304
if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))
drivers/gpu/drm/i915/display/intel_display.c
3307
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display.c
3311
if (display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_display.c
3314
intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
drivers/gpu/drm/i915/display/intel_display.c
3319
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3322
tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
3342
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_display.c
3362
void intel_get_m_n(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3367
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3368
m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3369
m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3370
m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
drivers/gpu/drm/i915/display/intel_display.c
3371
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
drivers/gpu/drm/i915/display/intel_display.c
3378
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3381
if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_display.c
3382
intel_get_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_display.c
3383
PIPE_DATA_M1(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
3384
PIPE_DATA_N1(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
3385
PIPE_LINK_M1(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
3386
PIPE_LINK_N1(display, transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3388
intel_get_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_display.c
3397
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3399
if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
drivers/gpu/drm/i915/display/intel_display.c
340
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
3402
intel_get_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_display.c
3403
PIPE_DATA_M2(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
3404
PIPE_DATA_N2(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
3405
PIPE_LINK_M2(display, transcoder),
drivers/gpu/drm/i915/display/intel_display.c
3406
PIPE_LINK_N2(display, transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3412
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3420
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_display.c
3424
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
343
return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));
drivers/gpu/drm/i915/display/intel_display.c
3482
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_display.c
3487
static u8 joiner_pipes(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
3491
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display.c
3493
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display.c
3498
return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;
drivers/gpu/drm/i915/display/intel_display.c
3501
static bool transcoder_ddi_func_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3509
with_intel_display_power_if_enabled(display, power_domain)
drivers/gpu/drm/i915/display/intel_display.c
351
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
3510
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3511
TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3516
static void enabled_uncompressed_joiner_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3524
if (!HAS_UNCOMPRESSED_JOINER(display))
drivers/gpu/drm/i915/display/intel_display.c
3527
for_each_intel_crtc_in_pipe_mask(display, crtc,
drivers/gpu/drm/i915/display/intel_display.c
3528
joiner_pipes(display)) {
drivers/gpu/drm/i915/display/intel_display.c
3533
with_intel_display_power_if_enabled(display, power_domain) {
drivers/gpu/drm/i915/display/intel_display.c
3534
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_display.c
354
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_display.c
3544
static void enabled_bigjoiner_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3552
if (!HAS_BIGJOINER(display))
drivers/gpu/drm/i915/display/intel_display.c
3555
for_each_intel_crtc_in_pipe_mask(display, crtc,
drivers/gpu/drm/i915/display/intel_display.c
3556
joiner_pipes(display)) {
drivers/gpu/drm/i915/display/intel_display.c
3561
with_intel_display_power_if_enabled(display, power_domain) {
drivers/gpu/drm/i915/display/intel_display.c
3562
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_display.c
358
if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
360
drm_WARN(display->drm, 1, "pipe_off wait timed out\n");
drivers/gpu/drm/i915/display/intel_display.c
3613
static void enabled_ultrajoiner_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3621
if (!HAS_ULTRAJOINER(display))
drivers/gpu/drm/i915/display/intel_display.c
3624
for_each_intel_crtc_in_pipe_mask(display, crtc,
drivers/gpu/drm/i915/display/intel_display.c
3625
joiner_pipes(display)) {
drivers/gpu/drm/i915/display/intel_display.c
3630
with_intel_display_power_if_enabled(display, power_domain) {
drivers/gpu/drm/i915/display/intel_display.c
3631
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
drivers/gpu/drm/i915/display/intel_display.c
3644
static void enabled_joiner_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3655
enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes,
drivers/gpu/drm/i915/display/intel_display.c
366
void assert_transcoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3662
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3669
drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);
drivers/gpu/drm/i915/display/intel_display.c
3671
enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes,
drivers/gpu/drm/i915/display/intel_display.c
3674
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3677
enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes,
drivers/gpu/drm/i915/display/intel_display.c
3680
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3688
drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,
drivers/gpu/drm/i915/display/intel_display.c
3692
drm_WARN(display->drm, secondary_ultrajoiner_pipes !=
drivers/gpu/drm/i915/display/intel_display.c
3698
drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,
drivers/gpu/drm/i915/display/intel_display.c
3702
drm_WARN(display->drm, secondary_bigjoiner_pipes !=
drivers/gpu/drm/i915/display/intel_display.c
3708
drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=
drivers/gpu/drm/i915/display/intel_display.c
3722
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3737
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
374
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_display.c
3752
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3763
static u8 hsw_panel_transcoders(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
3767
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display.c
3775
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3776
u8 panel_transcoder_mask = hsw_panel_transcoders(display);
drivers/gpu/drm/i915/display/intel_display.c
378
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_display.c
3785
for_each_cpu_transcoder_masked(display, cpu_transcoder,
drivers/gpu/drm/i915/display/intel_display.c
3792
with_intel_display_power_if_enabled(display, power_domain)
drivers/gpu/drm/i915/display/intel_display.c
3793
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3794
TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
380
u32 val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3801
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_display.c
381
TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3826
if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
drivers/gpu/drm/i915/display/intel_display.c
3830
enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);
drivers/gpu/drm/i915/display/intel_display.c
3833
if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
drivers/gpu/drm/i915/display/intel_display.c
384
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_display.c
3858
static void assert_enabled_transcoders(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
3862
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3868
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
3877
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3885
assert_enabled_transcoders(display, enabled_transcoders);
drivers/gpu/drm/i915/display/intel_display.c
389
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_display.c
3894
if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
drivers/gpu/drm/i915/display/intel_display.c
3898
if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {
drivers/gpu/drm/i915/display/intel_display.c
3899
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3900
TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3906
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
3907
TRANSCONF(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
3916
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3927
if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
drivers/gpu/drm/i915/display/intel_display.c
3938
if (!bxt_dsi_pll_is_enabled(display))
drivers/gpu/drm/i915/display/intel_display.c
3942
tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
drivers/gpu/drm/i915/display/intel_display.c
3946
tmp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/intel_display.c
3959
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
3964
enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes);
drivers/gpu/drm/i915/display/intel_display.c
397
struct intel_display *display = to_intel_display(plane->base.dev);
drivers/gpu/drm/i915/display/intel_display.c
3975
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
3979
if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
drivers/gpu/drm/i915/display/intel_display.c
3985
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/intel_display.c
3987
drm_WARN_ON(display->drm, active);
drivers/gpu/drm/i915/display/intel_display.c
3999
tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
4012
DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display.c
4020
if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display.c
4021
u32 tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
4022
TRANSCONF(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
403
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_display.c
4037
tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
drivers/gpu/drm/i915/display/intel_display.c
4039
if (display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display.c
4043
if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
drivers/gpu/drm/i915/display/intel_display.c
4045
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display.c
4056
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_display.c
4057
TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;
drivers/gpu/drm/i915/display/intel_display.c
4063
intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
drivers/gpu/drm/i915/display/intel_display.c
4070
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
4073
if (!display->modeset.funcs->get_pipe_config(crtc, crtc_state))
drivers/gpu/drm/i915/display/intel_display.c
4133
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
414
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
4142
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
417
for_each_intel_plane_on_crtc(display->drm, crtc, plane)
drivers/gpu/drm/i915/display/intel_display.c
423
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
4232
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
4244
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/intel_display.c
4245
skl_watermark_ipc_enabled(display))
drivers/gpu/drm/i915/display/intel_display.c
4254
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
4259
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display.c
4280
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
4285
if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&
drivers/gpu/drm/i915/display/intel_display.c
429
drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
drivers/gpu/drm/i915/display/intel_display.c
4302
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
4308
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_display.c
4321
if (HAS_IPS(display)) {
drivers/gpu/drm/i915/display/intel_display.c
4327
if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_display.c
4328
display->platform.broadwell || display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display.c
4363
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
438
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/intel_display.c
4385
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
440
assert_dsi_pll_enabled(display);
drivers/gpu/drm/i915/display/intel_display.c
4404
int intel_display_max_pipe_bpp(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
4406
if (display->platform.g4x || display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_display.c
4407
display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
4409
else if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_display.c
4419
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
442
assert_pll_enabled(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
4426
crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);
drivers/gpu/drm/i915/display/intel_display.c
4445
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
4456
drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display.c
446
assert_fdi_rx_pll_enabled(display,
drivers/gpu/drm/i915/display/intel_display.c
4463
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_display.c
4479
drm_WARN_ON(display->drm, !connector_state->crtc);
drivers/gpu/drm/i915/display/intel_display.c
448
assert_fdi_tx_pll_enabled(display,
drivers/gpu/drm/i915/display/intel_display.c
4483
if (drm_WARN_ON(display->drm, !HAS_DDI(display)))
drivers/gpu/drm/i915/display/intel_display.c
455
if (intel_display_wa(display, INTEL_DISPLAY_WA_22012358565))
drivers/gpu/drm/i915/display/intel_display.c
456
intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
drivers/gpu/drm/i915/display/intel_display.c
459
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_display.c
463
if (DISPLAY_VER(display) == 14)
drivers/gpu/drm/i915/display/intel_display.c
4636
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
466
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
4669
if (display->platform.g4x ||
drivers/gpu/drm/i915/display/intel_display.c
4670
display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
4686
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
470
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
4719
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
473
drm_WARN_ON(display->drm, !display->platform.i830);
drivers/gpu/drm/i915/display/intel_display.c
4749
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
478
if (DISPLAY_VER(display) >= 13 &&
drivers/gpu/drm/i915/display/intel_display.c
4791
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",
drivers/gpu/drm/i915/display/intel_display.c
4807
drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",
drivers/gpu/drm/i915/display/intel_display.c
4818
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
485
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
487
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
4953
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
4968
hdmi_infoframe_log(loglevel, display->drm->dev, a);
drivers/gpu/drm/i915/display/intel_display.c
4970
hdmi_infoframe_log(loglevel, display->drm->dev, b);
drivers/gpu/drm/i915/display/intel_display.c
502
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
5039
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
5044
intel_dpll_dump_hw_state(display, p, a);
drivers/gpu/drm/i915/display/intel_display.c
5046
intel_dpll_dump_hw_state(display, p, b);
drivers/gpu/drm/i915/display/intel_display.c
5051
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
5063
return HAS_LRR(display) &&
drivers/gpu/drm/i915/display/intel_display.c
5064
(old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
drivers/gpu/drm/i915/display/intel_display.c
5073
struct intel_display *display = to_intel_display(current_config);
drivers/gpu/drm/i915/display/intel_display.c
508
drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));
drivers/gpu/drm/i915/display/intel_display.c
5080
p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
drivers/gpu/drm/i915/display/intel_display.c
5082
p = drm_err_printer(display->drm, NULL);
drivers/gpu/drm/i915/display/intel_display.c
516
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_display.c
5173
if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \
drivers/gpu/drm/i915/display/intel_display.c
528
if (!display->platform.i830)
drivers/gpu/drm/i915/display/intel_display.c
5307
if (HAS_DOUBLE_BUFFERED_M_N(display)) {
drivers/gpu/drm/i915/display/intel_display.c
532
if (DISPLAY_VER(display) >= 13 &&
drivers/gpu/drm/i915/display/intel_display.c
5341
if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||
drivers/gpu/drm/i915/display/intel_display.c
5342
display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
5358
if (DISPLAY_VER(display) < 4)
drivers/gpu/drm/i915/display/intel_display.c
536
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_display.c
538
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display.c
5381
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display.c
539
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
5403
if (display->dpll.mgr)
drivers/gpu/drm/i915/display/intel_display.c
5407
if (display->dpll.mgr || HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_display.c
5413
if (display->platform.g4x || DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_display.c
546
u32 intel_plane_fb_max_stride(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
5503
if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
drivers/gpu/drm/i915/display/intel_display.c
5541
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5545
drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
drivers/gpu/drm/i915/display/intel_display.c
558
crtc = intel_first_crtc(display);
drivers/gpu/drm/i915/display/intel_display.c
5585
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5588
for_each_intel_crtc_in_pipe_mask(display, crtc, mask) {
drivers/gpu/drm/i915/display/intel_display.c
5632
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5635
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display.c
5661
int intel_modeset_commit_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
5669
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_display.c
5676
for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) {
drivers/gpu/drm/i915/display/intel_display.c
5703
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
571
struct intel_display *display = to_intel_display(drm);
drivers/gpu/drm/i915/display/intel_display.c
573
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display.c
5730
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display.c
576
return intel_plane_fb_max_stride(display,
drivers/gpu/drm/i915/display/intel_display.c
5790
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5794
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display.c
5815
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
5823
drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
drivers/gpu/drm/i915/display/intel_display.c
5846
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5855
drm_dbg_atomic(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
5900
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5909
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
5913
if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {
drivers/gpu/drm/i915/display/intel_display.c
5914
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
5918
primary_crtc_state->joiner_pipes, joiner_pipes(display));
drivers/gpu/drm/i915/display/intel_display.c
5922
for_each_intel_crtc_in_pipe_mask(display, secondary_crtc,
drivers/gpu/drm/i915/display/intel_display.c
5933
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
5941
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
5960
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
5965
for_each_intel_crtc_in_pipe_mask(display, secondary_crtc,
drivers/gpu/drm/i915/display/intel_display.c
597
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
5999
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6011
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6018
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6029
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6048
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6055
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6067
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
608
drm_for_each_plane_mask(plane, display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6080
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6087
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6094
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6110
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6127
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6144
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6152
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6160
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6168
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6176
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
618
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
6184
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6191
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6199
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6206
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6213
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6221
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6233
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
624
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
6264
for_each_intel_crtc_in_pipe_mask(display, crtc, affected_pipes) {
drivers/gpu/drm/i915/display/intel_display.c
6270
for_each_intel_crtc_in_pipe_mask(display, crtc, modeset_pipes) {
drivers/gpu/drm/i915/display/intel_display.c
6300
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6322
if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
drivers/gpu/drm/i915/display/intel_display.c
6341
if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
drivers/gpu/drm/i915/display/intel_display.c
6405
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_display.c
6411
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_display.c
6458
drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);
drivers/gpu/drm/i915/display/intel_display.c
650
if (HAS_GMCH(display) &&
drivers/gpu/drm/i915/display/intel_display.c
651
intel_set_memory_cxsr(display, false))
drivers/gpu/drm/i915/display/intel_display.c
6525
drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n");
drivers/gpu/drm/i915/display/intel_display.c
6575
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
658
if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)
drivers/gpu/drm/i915/display/intel_display.c
659
intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);
drivers/gpu/drm/i915/display/intel_display.c
6618
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display.c
6620
if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
drivers/gpu/drm/i915/display/intel_display.c
6621
intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
6627
intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);
drivers/gpu/drm/i915/display/intel_display.c
6634
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
6648
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_display.c
6651
} else if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_display.c
6666
if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_display.c
6667
display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display.c
6681
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6688
drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
drivers/gpu/drm/i915/display/intel_display.c
6698
if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_display.c
6713
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6718
drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
drivers/gpu/drm/i915/display/intel_display.c
6725
if (DISPLAY_VER(display) >= 9 && !modeset)
drivers/gpu/drm/i915/display/intel_display.c
6731
HAS_DOUBLE_BUFFERED_LUT(display))
drivers/gpu/drm/i915/display/intel_display.c
6741
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6749
for_each_intel_crtc_in_pipe_mask_reverse(display, pipe_crtc,
drivers/gpu/drm/i915/display/intel_display.c
6760
display->modeset.funcs->crtc_enable(state, crtc);
drivers/gpu/drm/i915/display/intel_display.c
6771
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
678
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
6780
if (HAS_DPT(display))
drivers/gpu/drm/i915/display/intel_display.c
6794
if (DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/intel_display.c
6805
drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));
drivers/gpu/drm/i915/display/intel_display.c
683
tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
drivers/gpu/drm/i915/display/intel_display.c
6878
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6887
for_each_intel_crtc_in_pipe_mask(display, pipe_crtc,
drivers/gpu/drm/i915/display/intel_display.c
6893
display->modeset.funcs->crtc_disable(state, crtc);
drivers/gpu/drm/i915/display/intel_display.c
6895
for_each_intel_crtc_in_pipe_mask(display, pipe_crtc,
drivers/gpu/drm/i915/display/intel_display.c
6910
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
6975
drm_WARN_ON(display->drm, disable_pipes);
drivers/gpu/drm/i915/display/intel_display.c
7001
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
703
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_display.c
705
else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))
drivers/gpu/drm/i915/display/intel_display.c
709
if (intel_display_wa(display, INTEL_DISPLAY_WA_14010547955))
drivers/gpu/drm/i915/display/intel_display.c
712
intel_de_write(display, PIPE_CHICKEN(pipe), tmp);
drivers/gpu/drm/i915/display/intel_display.c
7141
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
715
bool intel_has_pending_fb_unpin(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
7151
drm_WARN_ON(display->drm, modeset_pipes);
drivers/gpu/drm/i915/display/intel_display.c
7152
drm_WARN_ON(display->drm, update_pipes);
drivers/gpu/drm/i915/display/intel_display.c
7197
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
720
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display.c
7204
drm_atomic_helper_cleanup_planes(display->drm, &state->base);
drivers/gpu/drm/i915/display/intel_display.c
7211
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
7248
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/intel_display.c
7255
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
7267
intel_flipq_supported(display) &&
drivers/gpu/drm/i915/display/intel_display.c
7278
(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
drivers/gpu/drm/i915/display/intel_display.c
7288
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
7362
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display.c
741
void intel_display_flush_cleanup_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
7425
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_display.c
7426
struct intel_uncore *uncore = to_intel_uncore(display->drm);
drivers/gpu/drm/i915/display/intel_display.c
7437
intel_td_flush(display);
drivers/gpu/drm/i915/display/intel_display.c
745
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display.c
7478
wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
drivers/gpu/drm/i915/display/intel_display.c
7503
drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);
drivers/gpu/drm/i915/display/intel_display.c
7518
spin_lock_irq(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_display.c
7521
spin_unlock_irq(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_display.c
7537
display->modeset.funcs->commit_modeset_enables(state);
drivers/gpu/drm/i915/display/intel_display.c
7553
drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);
drivers/gpu/drm/i915/display/intel_display.c
7584
if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
drivers/gpu/drm/i915/display/intel_display.c
7585
intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
drivers/gpu/drm/i915/display/intel_display.c
7613
intel_check_cpu_fifo_underruns(display);
drivers/gpu/drm/i915/display/intel_display.c
7614
intel_check_pch_fifo_underruns(display);
drivers/gpu/drm/i915/display/intel_display.c
7639
intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
drivers/gpu/drm/i915/display/intel_display.c
7640
intel_display_rpm_put(display, state->wakeref);
drivers/gpu/drm/i915/display/intel_display.c
7651
queue_work(display->wq.cleanup, &state->cleanup_work);
drivers/gpu/drm/i915/display/intel_display.c
7710
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_display.c
7714
state->wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_display.c
7733
if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {
drivers/gpu/drm/i915/display/intel_display.c
7745
drm_dbg_atomic(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
7747
intel_display_rpm_put(display, state->wakeref);
drivers/gpu/drm/i915/display/intel_display.c
7757
intel_display_rpm_put(display, state->wakeref);
drivers/gpu/drm/i915/display/intel_display.c
7765
queue_work(display->wq.modeset, &state->base.commit_work);
drivers/gpu/drm/i915/display/intel_display.c
7767
queue_work(display->wq.flip, &state->base.commit_work);
drivers/gpu/drm/i915/display/intel_display.c
7770
flush_workqueue(display->wq.modeset);
drivers/gpu/drm/i915/display/intel_display.c
7779
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
7783
for_each_intel_encoder(display->drm, source_encoder) {
drivers/gpu/drm/i915/display/intel_display.c
7793
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display.c
7797
for_each_intel_crtc_in_pipe_mask(display, crtc, encoder->pipe_mask)
drivers/gpu/drm/i915/display/intel_display.c
7803
static bool ilk_has_edp_a(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
7805
if (!display->platform.mobile)
drivers/gpu/drm/i915/display/intel_display.c
7808
if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)
drivers/gpu/drm/i915/display/intel_display.c
7811
if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))
drivers/gpu/drm/i915/display/intel_display.c
7817
static bool intel_ddi_crt_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
7819
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display.c
7822
if (display->platform.haswell_ult || display->platform.broadwell_ult)
drivers/gpu/drm/i915/display/intel_display.c
7825
if (HAS_PCH_LPT_H(display) &&
drivers/gpu/drm/i915/display/intel_display.c
7826
intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
drivers/gpu/drm/i915/display/intel_display.c
7830
if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_display.c
7833
if (!display->vbt.int_crt_support)
drivers/gpu/drm/i915/display/intel_display.c
7839
bool assert_port_valid(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display.c
7841
return !drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
7842
!(port >= 0 && DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
drivers/gpu/drm/i915/display/intel_display.c
7846
void intel_setup_outputs(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
7851
intel_pps_unlock_regs_wa(display);
drivers/gpu/drm/i915/display/intel_display.c
7853
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display.c
7856
if (HAS_DDI(display)) {
drivers/gpu/drm/i915/display/intel_display.c
7857
if (intel_ddi_crt_present(display))
drivers/gpu/drm/i915/display/intel_display.c
7858
intel_crt_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7860
intel_bios_for_each_encoder(display, intel_ddi_init);
drivers/gpu/drm/i915/display/intel_display.c
7862
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display.c
7863
vlv_dsi_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7864
} else if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_display.c
7872
intel_lvds_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7873
intel_crt_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7875
dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7877
if (ilk_has_edp_a(display))
drivers/gpu/drm/i915/display/intel_display.c
7878
g4x_dp_init(display, DP_A, PORT_A);
drivers/gpu/drm/i915/display/intel_display.c
7880
if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {
drivers/gpu/drm/i915/display/intel_display.c
7882
found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7884
g4x_hdmi_init(display, PCH_HDMIB, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7885
if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))
drivers/gpu/drm/i915/display/intel_display.c
7886
g4x_dp_init(display, PCH_DP_B, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7889
if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7890
g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7892
if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7893
g4x_hdmi_init(display, PCH_HDMID, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7895
if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7896
g4x_dp_init(display, PCH_DP_C, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7898
if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)
drivers/gpu/drm/i915/display/intel_display.c
7899
g4x_dp_init(display, PCH_DP_D, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7900
} else if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_display.c
7903
if (display->platform.valleyview && display->vbt.int_crt_support)
drivers/gpu/drm/i915/display/intel_display.c
7904
intel_crt_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7921
has_edp = intel_dp_is_port_edp(display, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7922
has_port = intel_bios_is_port_present(display, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7923
if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7924
has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7925
if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
drivers/gpu/drm/i915/display/intel_display.c
7926
g4x_hdmi_init(display, VLV_HDMIB, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7928
has_edp = intel_dp_is_port_edp(display, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7929
has_port = intel_bios_is_port_present(display, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7930
if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7931
has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7932
if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
drivers/gpu/drm/i915/display/intel_display.c
7933
g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7935
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_display.c
7940
has_port = intel_bios_is_port_present(display, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7941
if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7942
g4x_dp_init(display, CHV_DP_D, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7943
if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)
drivers/gpu/drm/i915/display/intel_display.c
7944
g4x_hdmi_init(display, CHV_HDMID, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7947
vlv_dsi_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7948
} else if (display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_display.c
7949
intel_lvds_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7950
intel_crt_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7951
} else if (IS_DISPLAY_VER(display, 3, 4)) {
drivers/gpu/drm/i915/display/intel_display.c
7954
if (display->platform.mobile)
drivers/gpu/drm/i915/display/intel_display.c
7955
intel_lvds_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7957
intel_crt_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7959
if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
drivers/gpu/drm/i915/display/intel_display.c
7960
drm_dbg_kms(display->drm, "probing SDVOB\n");
drivers/gpu/drm/i915/display/intel_display.c
7961
found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7962
if (!found && display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_display.c
7963
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
7965
g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7968
if (!found && display->platform.g4x)
drivers/gpu/drm/i915/display/intel_display.c
7969
g4x_dp_init(display, DP_B, PORT_B);
drivers/gpu/drm/i915/display/intel_display.c
7974
if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
drivers/gpu/drm/i915/display/intel_display.c
7975
drm_dbg_kms(display->drm, "probing SDVOC\n");
drivers/gpu/drm/i915/display/intel_display.c
7976
found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7979
if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {
drivers/gpu/drm/i915/display/intel_display.c
7981
if (display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_display.c
7982
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
7984
g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7986
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_display.c
7987
g4x_dp_init(display, DP_C, PORT_C);
drivers/gpu/drm/i915/display/intel_display.c
7990
if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))
drivers/gpu/drm/i915/display/intel_display.c
7991
g4x_dp_init(display, DP_D, PORT_D);
drivers/gpu/drm/i915/display/intel_display.c
7993
if (SUPPORTS_TV(display))
drivers/gpu/drm/i915/display/intel_display.c
7994
intel_tv_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7995
} else if (DISPLAY_VER(display) == 2) {
drivers/gpu/drm/i915/display/intel_display.c
7996
if (display->platform.i85x)
drivers/gpu/drm/i915/display/intel_display.c
7997
intel_lvds_init(display);
drivers/gpu/drm/i915/display/intel_display.c
7999
intel_crt_init(display);
drivers/gpu/drm/i915/display/intel_display.c
8000
intel_dvo_init(display);
drivers/gpu/drm/i915/display/intel_display.c
8003
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_display.c
8010
intel_init_pch_refclk(display);
drivers/gpu/drm/i915/display/intel_display.c
8012
drm_helper_move_panel_connectors_to_head(display->drm);
drivers/gpu/drm/i915/display/intel_display.c
8015
int intel_max_uncompressed_dotclock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
8017
int max_dotclock = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_display.c
8020
if (DISPLAY_VERx100(display) == 3002)
drivers/gpu/drm/i915/display/intel_display.c
8022
else if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_display.c
8034
static int max_dotclock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
8036
int max_dotclock = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_display.c
8038
if (HAS_ULTRAJOINER(display))
drivers/gpu/drm/i915/display/intel_display.c
8040
else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))
drivers/gpu/drm/i915/display/intel_display.c
8049
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_display.c
806
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
8086
if (mode->clock > max_dotclock(display))
drivers/gpu/drm/i915/display/intel_display.c
8090
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display.c
8095
} else if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_display.c
8096
display->platform.broadwell || display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display.c
8101
} else if (DISPLAY_VER(display) >= 3) {
drivers/gpu/drm/i915/display/intel_display.c
812
if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_display.c
8136
enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
8143
if (DISPLAY_VER(display) >= 5) {
drivers/gpu/drm/i915/display/intel_display.c
8162
if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
drivers/gpu/drm/i915/display/intel_display.c
8170
intel_mode_valid_max_plane_size(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
8180
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_display.c
8188
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_display.c
8191
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display.c
820
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
823
if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display.c
8257
void intel_init_display_hooks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
8259
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_display.c
8260
display->modeset.funcs = &skl_display_funcs;
drivers/gpu/drm/i915/display/intel_display.c
8261
} else if (HAS_DDI(display)) {
drivers/gpu/drm/i915/display/intel_display.c
8262
display->modeset.funcs = &ddi_display_funcs;
drivers/gpu/drm/i915/display/intel_display.c
8263
} else if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_display.c
8264
display->modeset.funcs = &pch_split_display_funcs;
drivers/gpu/drm/i915/display/intel_display.c
8265
} else if (display->platform.cherryview ||
drivers/gpu/drm/i915/display/intel_display.c
8266
display->platform.valleyview) {
drivers/gpu/drm/i915/display/intel_display.c
8267
display->modeset.funcs = &vlv_display_funcs;
drivers/gpu/drm/i915/display/intel_display.c
8269
display->modeset.funcs = &i9xx_display_funcs;
drivers/gpu/drm/i915/display/intel_display.c
8273
int intel_initial_commit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
8280
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_display.c
8290
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display.c
831
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
8317
for_each_intel_encoder_mask(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_display.c
8347
void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_display.c
8349
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
836
DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display.c
8362
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8365
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8377
intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
8379
intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
8381
intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
8383
intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
8385
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
8387
intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_display.c
8389
intel_de_write(display, PIPESRC(display, pipe),
drivers/gpu/drm/i915/display/intel_display.c
8392
intel_de_write(display, FP0(pipe), fp);
drivers/gpu/drm/i915/display/intel_display.c
8393
intel_de_write(display, FP1(pipe), fp);
drivers/gpu/drm/i915/display/intel_display.c
8400
intel_de_write(display, DPLL(display, pipe),
drivers/gpu/drm/i915/display/intel_display.c
8402
intel_de_write(display, DPLL(display, pipe), dpll);
drivers/gpu/drm/i915/display/intel_display.c
8405
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_display.c
8413
intel_de_write(display, DPLL(display, pipe), dpll);
drivers/gpu/drm/i915/display/intel_display.c
8417
intel_de_write(display, DPLL(display, pipe), dpll);
drivers/gpu/drm/i915/display/intel_display.c
8418
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_display.c
842
static void intel_async_flip_vtd_wa(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.c
8422
intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8423
intel_de_posting_read(display, TRANSCONF(display, pipe));
drivers/gpu/drm/i915/display/intel_display.c
8428
void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_display.c
8430
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display.c
8432
drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
drivers/gpu/drm/i915/display/intel_display.c
8435
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8436
intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8437
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8438
intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8439
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8440
intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
drivers/gpu/drm/i915/display/intel_display.c
8441
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8442
intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
drivers/gpu/drm/i915/display/intel_display.c
8443
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display.c
8444
intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
drivers/gpu/drm/i915/display/intel_display.c
8446
intel_de_write(display, TRANSCONF(display, pipe), 0);
drivers/gpu/drm/i915/display/intel_display.c
8447
intel_de_posting_read(display, TRANSCONF(display, pipe));
drivers/gpu/drm/i915/display/intel_display.c
845
if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_display.c
8451
intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
drivers/gpu/drm/i915/display/intel_display.c
8452
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_display.c
8455
bool intel_scanout_needs_vtd_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display.c
8457
return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display);
drivers/gpu/drm/i915/display/intel_display.c
850
intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
drivers/gpu/drm/i915/display/intel_display.c
855
intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
drivers/gpu/drm/i915/display/intel_display.c
863
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_display.c
865
return crtc_state->uapi.async_flip && intel_display_vtd_active(display) &&
drivers/gpu/drm/i915/display/intel_display.c
866
(DISPLAY_VER(display) == 9 || display->platform.broadwell ||
drivers/gpu/drm/i915/display/intel_display.c
867
display->platform.haswell);
drivers/gpu/drm/i915/display/intel_display.h
215
#define for_each_intel_crtc(display, crtc) \
drivers/gpu/drm/i915/display/intel_display.h
217
&(display)->pipe_list, \
drivers/gpu/drm/i915/display/intel_display.h
220
#define for_each_intel_crtc_reverse(display, crtc) \
drivers/gpu/drm/i915/display/intel_display.h
222
&(display)->pipe_list, \
drivers/gpu/drm/i915/display/intel_display.h
225
#define for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) \
drivers/gpu/drm/i915/display/intel_display.h
226
for_each_intel_crtc((display), (crtc)) \
drivers/gpu/drm/i915/display/intel_display.h
229
#define for_each_intel_crtc_in_pipe_mask_reverse(display, crtc, pipe_mask) \
drivers/gpu/drm/i915/display/intel_display.h
230
for_each_intel_crtc_reverse((display), (crtc)) \
drivers/gpu/drm/i915/display/intel_display.h
328
#define __for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \
drivers/gpu/drm/i915/display/intel_display.h
330
(i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
drivers/gpu/drm/i915/display/intel_display.h
334
#define __for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \
drivers/gpu/drm/i915/display/intel_display.h
336
(i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
drivers/gpu/drm/i915/display/intel_display.h
340
#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state) \
drivers/gpu/drm/i915/display/intel_display.h
341
__for_each_crtc_in_masks(display, crtc, \
drivers/gpu/drm/i915/display/intel_display.h
346
#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state) \
drivers/gpu/drm/i915/display/intel_display.h
347
__for_each_crtc_in_masks_reverse(display, crtc, \
drivers/gpu/drm/i915/display/intel_display.h
361
u32 intel_plane_fb_max_stride(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
367
intel_mode_valid_max_plane_size(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
371
intel_cpu_transcoder_mode_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
373
enum phy intel_port_to_phy(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_display.h
397
void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_display.h
398
void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_display.h
399
bool intel_has_pending_fb_unpin(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
400
void intel_display_flush_cleanup_work(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
406
bool intel_phy_is_combo(struct intel_display *display, enum phy phy);
drivers/gpu/drm/i915/display/intel_display.h
407
bool intel_phy_is_tc(struct intel_display *display, enum phy phy);
drivers/gpu/drm/i915/display/intel_display.h
408
bool intel_phy_is_snps(struct intel_display *display, enum phy phy);
drivers/gpu/drm/i915/display/intel_display.h
409
enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_display.h
410
enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_display.h
423
void intel_set_m_n(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
427
void intel_get_m_n(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
431
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
447
int intel_max_uncompressed_dotclock(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
470
int intel_display_max_pipe_bpp(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
477
int intel_modeset_commit_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
486
void intel_init_display_hooks(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
487
void intel_setup_outputs(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
488
int intel_initial_commit(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
489
void intel_panel_sanitize_ssc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display.h
496
void assert_transcoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display.h
501
bool assert_port_valid(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_display.h
518
bool intel_scanout_needs_vtd_wa(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
104
intel_de_write(display, GEN9_CLKGATE_DIS_0,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
105
intel_de_read(display, GEN9_CLKGATE_DIS_0) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
114
intel_de_write(display, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
120
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
123
void intel_display_glk_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
125
intel_display_gen9_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
132
intel_de_write(display, GEN9_CLKGATE_DIS_0,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
133
intel_de_read(display, GEN9_CLKGATE_DIS_0) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
137
void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
140
intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
143
void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
148
intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
15
static void intel_display_gen9_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
150
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
152
intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
157
void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
160
intel_de_rmw(display, CHICKEN_PAR2_1, 0,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
164
void intel_display_hsw_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
169
intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
172
intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
174
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
176
intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
18
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
181
void intel_display_disable_trickle_feed(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
185
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
186
intel_de_rmw(display, DSPCNTR(display, pipe), 0,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
189
intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
190
intel_de_posting_read(display, DSPSURF(display, pipe));
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
194
void intel_display_ilk_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
206
intel_de_write(display, ILK_DISPLAY_CHICKEN2,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
207
intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
21
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
210
intel_de_write(display, DISP_ARB_CTL,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
211
intel_de_read(display, DISP_ARB_CTL) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
214
if (display->platform.ironlake && display->platform.mobile) {
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
216
intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
217
intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
220
intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
221
intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
223
intel_display_disable_trickle_feed(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
226
void intel_display_gen6_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
230
intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
231
intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
233
intel_de_write(display, ILK_DISPLAY_CHICKEN1,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
234
intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
236
intel_de_write(display, ILK_DISPLAY_CHICKEN2,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
237
intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
239
intel_de_write(display, ILK_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
240
intel_de_read(display, ILK_DSPCLK_GATE_D) |
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
244
intel_display_disable_trickle_feed(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
247
void intel_display_ivb_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
249
intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
250
intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
253
void intel_display_g4x_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
259
if (display->platform.gm45)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
262
intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
264
intel_display_disable_trickle_feed(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
267
void intel_display_i965gm_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
269
intel_de_write(display, DSPCLK_GATE_D, 0);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
27
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
30
void intel_display_skl_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
39
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
41
intel_display_gen9_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
47
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
50
void intel_display_kbl_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
59
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
61
intel_display_gen9_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
67
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
70
void intel_display_cfl_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
85
intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
87
intel_display_gen9_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
93
intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
96
void intel_display_bxt_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_clock_gating.c
98
intel_display_gen9_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
11
void intel_display_skl_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
12
void intel_display_kbl_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
13
void intel_display_cfl_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
14
void intel_display_bxt_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
15
void intel_display_glk_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
16
void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
17
void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
18
void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
19
void intel_display_hsw_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
20
void intel_display_disable_trickle_feed(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
21
void intel_display_ilk_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
22
void intel_display_gen6_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
23
void intel_display_ivb_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
24
void intel_display_g4x_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_clock_gating.h
25
void intel_display_i965gm_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_conversion.c
20
return d->display;
drivers/gpu/drm/i915/display/intel_display_core.h
83
void (*update_wm)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_core.h
93
void (*get_hw_state)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_core.h
94
void (*sanitize)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
100
display->platform.i945g || display->platform.i945gm)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
101
sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1018
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
102
else if (display->platform.i915gm)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1027
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
103
sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
104
else if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1040
out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
105
sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
106
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
107
sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1084
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
109
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1093
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1107
out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1151
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1160
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1175
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
118
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1186
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1195
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1202
drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
drivers/gpu/drm/i915/display/intel_display_debugfs.c
122
fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1275
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1293
if (HAS_ULTRAJOINER(display)) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1331
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
1347
if (DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/intel_display_debugfs.c
135
mutex_lock(&display->drm->mode_config.fb_lock);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
136
drm_for_each_fb(drm_fb, display->drm) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
151
mutex_unlock(&display->drm->mode_config.fb_lock);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
158
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
160
intel_display_power_debug(display, m);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
180
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
187
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
399
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
402
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
546
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
575
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
588
for_each_intel_encoder_mask(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
603
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
609
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
61
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
611
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
615
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
621
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
626
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
628
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
635
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
64
drm_printf(&p, "PCH type: %d\n", INTEL_PCH_TYPE(display));
drivers/gpu/drm/i915/display/intel_display_debugfs.c
640
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
643
display->dpll.ref_clks.nssc,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
644
display->dpll.ref_clks.ssc);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
646
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
653
intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
655
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
66
intel_display_device_info_print(DISPLAY_INFO(display),
drivers/gpu/drm/i915/display/intel_display_debugfs.c
662
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
666
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
669
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
67
DISPLAY_RUNTIME_INFO(display), &p);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
673
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
68
intel_display_params_dump(&display->params, display->drm->driver->name, &p);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
693
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
699
intel_lpsp_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
704
with_intel_display_rpm(display)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
705
is_enabled = intel_display_power_well_is_enabled(display,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
713
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
716
if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
717
lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
718
} else if (IS_DISPLAY_VER(display, 11, 12)) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
719
lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
720
} else if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
721
lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
734
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
740
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
75
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
768
struct intel_display *display = filp->private_data;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
77
spin_lock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
780
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
797
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
80
display->fb_tracking.busy_bits);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
810
intel_fbc_reset_underrun(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
82
spin_unlock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
835
void intel_display_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
837
struct dentry *debugfs_root = display->drm->debugfs_root;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
840
display, &i915_fifo_underrun_reset_ops);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
844
debugfs_root, display->drm->primary);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
846
intel_bios_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
847
intel_cdclk_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
848
intel_display_reset_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
849
intel_dmc_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
850
intel_dp_test_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
851
intel_fbc_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
852
intel_hpd_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
853
intel_opregion_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
854
intel_psr_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
855
intel_wm_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
856
intel_display_debugfs_params(display);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
862
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
873
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
875
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
882
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
885
else if (IS_DISPLAY_VER(display, 9, 10))
drivers/gpu/drm/i915/display/intel_display_debugfs.c
89
struct intel_display *display = node_to_intel_display(m->private);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
890
else if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
902
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
914
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
93
wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
95
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display_debugfs.c
97
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_display_debugfs.c
975
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
98
sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
984
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
99
else if (display->platform.i965gm || display->platform.g4x ||
drivers/gpu/drm/i915/display/intel_display_debugfs.c
991
drm_dbg(display->drm, "Got %s for DSC Enable\n",
drivers/gpu/drm/i915/display/intel_display_debugfs.h
14
void intel_display_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_debugfs.h
18
static inline void intel_display_debugfs_register(struct intel_display *display) {}
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
154
void intel_display_debugfs_params(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
156
struct dentry *debugfs_root = display->drm->debugfs_root;
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
160
snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
174
dir, #x, mode, &display->params.x);
drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
11
void intel_display_debugfs_params(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_device.c
1509
const struct intel_display_device_info *display;
drivers/gpu/drm/i915/display/intel_display_device.c
1520
probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *ip_ver)
drivers/gpu/drm/i915/display/intel_display_device.c
1522
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_display_device.c
1530
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_device.c
1539
drm_dbg_kms(display->drm, "Device doesn't have display\n");
drivers/gpu/drm/i915/display/intel_display_device.c
1551
return gmdid_display_map[i].display;
drivers/gpu/drm/i915/display/intel_display_device.c
1555
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_device.c
1587
static enum intel_step get_pre_gmdid_step(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_device.c
1591
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_display_device.c
1610
drm_warn(display->drm, "Unknown revision 0x%02x\n", revision);
drivers/gpu/drm/i915/display/intel_display_device.c
1624
drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n",
drivers/gpu/drm/i915/display/intel_display_device.c
1628
drm_dbg_kms(display->drm, "Using future display stepping\n");
drivers/gpu/drm/i915/display/intel_display_device.c
1633
drm_WARN_ON(display->drm, step == STEP_NONE);
drivers/gpu/drm/i915/display/intel_display_device.c
1659
static void initialize_step(struct intel_display *display, enum intel_step step)
drivers/gpu/drm/i915/display/intel_display_device.c
1665
DISPLAY_RUNTIME_INFO(display)->step = step;
drivers/gpu/drm/i915/display/intel_display_device.c
1669
strscpy(DISPLAY_RUNTIME_INFO(display)->step_name, step_names[step]);
drivers/gpu/drm/i915/display/intel_display_device.c
1682
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_display_device.c
1689
display = kzalloc_obj(*display);
drivers/gpu/drm/i915/display/intel_display_device.c
1690
if (!display)
drivers/gpu/drm/i915/display/intel_display_device.c
1694
display->drm = pci_get_drvdata(pdev);
drivers/gpu/drm/i915/display/intel_display_device.c
1696
display->parent = parent;
drivers/gpu/drm/i915/display/intel_display_device.c
1698
intel_display_params_copy(&display->params);
drivers/gpu/drm/i915/display/intel_display_device.c
1701
drm_dbg_kms(display->drm, "Device doesn't have display\n");
drivers/gpu/drm/i915/display/intel_display_device.c
1707
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_device.c
1715
info = probe_gmdid_display(display, &ip_ver);
drivers/gpu/drm/i915/display/intel_display_device.c
1719
DISPLAY_INFO(display) = info;
drivers/gpu/drm/i915/display/intel_display_device.c
1721
memcpy(DISPLAY_RUNTIME_INFO(display),
drivers/gpu/drm/i915/display/intel_display_device.c
1722
&DISPLAY_INFO(display)->__runtime_defaults,
drivers/gpu/drm/i915/display/intel_display_device.c
1723
sizeof(*DISPLAY_RUNTIME_INFO(display)));
drivers/gpu/drm/i915/display/intel_display_device.c
1725
drm_WARN_ON(display->drm, !desc->name ||
drivers/gpu/drm/i915/display/intel_display_device.c
1728
display->platform = desc->platforms;
drivers/gpu/drm/i915/display/intel_display_device.c
1732
drm_WARN_ON(display->drm, !subdesc->name ||
drivers/gpu/drm/i915/display/intel_display_device.c
1735
display_platforms_or(&display->platform, &subdesc->platforms);
drivers/gpu/drm/i915/display/intel_display_device.c
1738
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_device.c
1739
display_platforms_weight(&display->platform) !=
drivers/gpu/drm/i915/display/intel_display_device.c
1745
DISPLAY_RUNTIME_INFO(display)->ip = ip_ver;
drivers/gpu/drm/i915/display/intel_display_device.c
1748
drm_dbg_kms(display->drm, "Using future display stepping\n");
drivers/gpu/drm/i915/display/intel_display_device.c
1752
step = get_pre_gmdid_step(display, &desc->step_info,
drivers/gpu/drm/i915/display/intel_display_device.c
1756
initialize_step(display, step);
drivers/gpu/drm/i915/display/intel_display_device.c
1758
drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n",
drivers/gpu/drm/i915/display/intel_display_device.c
1760
pdev->device, display->platform.dgfx ? "discrete" : "integrated",
drivers/gpu/drm/i915/display/intel_display_device.c
1761
DISPLAY_RUNTIME_INFO(display)->ip.ver,
drivers/gpu/drm/i915/display/intel_display_device.c
1762
DISPLAY_RUNTIME_INFO(display)->ip.rel,
drivers/gpu/drm/i915/display/intel_display_device.c
1763
step_name(DISPLAY_RUNTIME_INFO(display)));
drivers/gpu/drm/i915/display/intel_display_device.c
1765
return display;
drivers/gpu/drm/i915/display/intel_display_device.c
1768
DISPLAY_INFO(display) = &no_display;
drivers/gpu/drm/i915/display/intel_display_device.c
1770
return display;
drivers/gpu/drm/i915/display/intel_display_device.c
1773
void intel_display_device_remove(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_device.c
1775
if (!display)
drivers/gpu/drm/i915/display/intel_display_device.c
1778
intel_display_params_free(&display->params);
drivers/gpu/drm/i915/display/intel_display_device.c
1779
kfree(display);
drivers/gpu/drm/i915/display/intel_display_device.c
1782
static void __intel_display_device_info_runtime_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_device.c
1784
struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display);
drivers/gpu/drm/i915/display/intel_display_device.c
1792
if (display->platform.haswell_ult || display->platform.broadwell_ult)
drivers/gpu/drm/i915/display/intel_display_device.c
1795
if (display->platform.icelake_port_f)
drivers/gpu/drm/i915/display/intel_display_device.c
1799
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011765242))
drivers/gpu/drm/i915/display/intel_display_device.c
1800
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1802
else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_device.c
1803
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1805
} else if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_display_device.c
1811
if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))
drivers/gpu/drm/i915/display/intel_display_device.c
1812
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1814
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display_device.c
1815
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1817
else if (DISPLAY_VER(display) == 10)
drivers/gpu/drm/i915/display/intel_display_device.c
1818
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1820
else if (display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_device.c
1833
} else if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_display_device.c
1834
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1836
} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_display_device.c
1837
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1841
if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) &&
drivers/gpu/drm/i915/display/intel_display_device.c
1842
!(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) {
drivers/gpu/drm/i915/display/intel_display_device.c
1843
drm_info(display->drm, "Display not present, disabling\n");
drivers/gpu/drm/i915/display/intel_display_device.c
1847
if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_display_device.c
1848
u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
drivers/gpu/drm/i915/display/intel_display_device.c
1849
u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);
drivers/gpu/drm/i915/display/intel_display_device.c
1862
(HAS_PCH_CPT(display) &&
drivers/gpu/drm/i915/display/intel_display_device.c
1864
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_display_device.c
1868
drm_info(display->drm, "PipeC fused off\n");
drivers/gpu/drm/i915/display/intel_display_device.c
1872
} else if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_display_device.c
1873
u32 dfsm = intel_de_read(display, SKL_DFSM);
drivers/gpu/drm/i915/display/intel_display_device.c
1891
if (DISPLAY_VER(display) >= 12 &&
drivers/gpu/drm/i915/display/intel_display_device.c
1904
if (display->platform.dg2 || DISPLAY_VER(display) < 13) {
drivers/gpu/drm/i915/display/intel_display_device.c
1909
if (DISPLAY_VER(display) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
drivers/gpu/drm/i915/display/intel_display_device.c
1912
if (IS_DISPLAY_VER(display, 10, 12) &&
drivers/gpu/drm/i915/display/intel_display_device.c
1916
if (DISPLAY_VER(display) >= 20 &&
drivers/gpu/drm/i915/display/intel_display_device.c
1921
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_display_device.c
1922
u32 cap = intel_de_read(display, XE2LPD_DE_CAP);
drivers/gpu/drm/i915/display/intel_display_device.c
1930
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_device.c
1936
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_display_device.c
1938
intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;
drivers/gpu/drm/i915/display/intel_display_device.c
1940
display_runtime->rawclk_freq = intel_read_rawclk(display);
drivers/gpu/drm/i915/display/intel_display_device.c
1941
drm_dbg_kms(display->drm, "rawclk rate: %d kHz\n",
drivers/gpu/drm/i915/display/intel_display_device.c
1950
void intel_display_device_info_runtime_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_device.c
1952
if (HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_device.c
1953
__intel_display_device_info_runtime_init(display);
drivers/gpu/drm/i915/display/intel_display_device.c
1956
if (!HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_display_device.c
1957
display->drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
drivers/gpu/drm/i915/display/intel_display_device.c
1958
display->info.__device_info = &no_display;
drivers/gpu/drm/i915/display/intel_display_device.c
1962
if (!display->params.nuclear_pageflip &&
drivers/gpu/drm/i915/display/intel_display_device.c
1963
DISPLAY_VER(display) < 5 && !display->platform.g4x)
drivers/gpu/drm/i915/display/intel_display_device.c
1964
display->drm->driver_features &= ~DRIVER_ATOMIC;
drivers/gpu/drm/i915/display/intel_display_device.c
1992
bool intel_display_device_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_device.c
1994
return display && HAS_DISPLAY(display);
drivers/gpu/drm/i915/display/intel_display_device.c
2006
bool intel_display_device_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_device.c
2009
drm_WARN_ON(display->drm, !HAS_DISPLAY(display));
drivers/gpu/drm/i915/display/intel_display_device.c
2011
return !display->params.disable_display &&
drivers/gpu/drm/i915/display/intel_display_device.c
2012
!intel_opregion_headless_sku(display);
drivers/gpu/drm/i915/display/intel_display_device.h
266
#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe) \
drivers/gpu/drm/i915/display/intel_display_device.h
267
(DISPLAY_INFO((display))->pipe_offsets[(pipe)] - \
drivers/gpu/drm/i915/display/intel_display_device.h
268
DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \
drivers/gpu/drm/i915/display/intel_display_device.h
269
DISPLAY_MMIO_BASE((display)))
drivers/gpu/drm/i915/display/intel_display_device.h
271
#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \
drivers/gpu/drm/i915/display/intel_display_device.h
272
(DISPLAY_INFO((display))->trans_offsets[(trans)] - \
drivers/gpu/drm/i915/display/intel_display_device.h
273
DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \
drivers/gpu/drm/i915/display/intel_display_device.h
274
DISPLAY_MMIO_BASE((display)))
drivers/gpu/drm/i915/display/intel_display_device.h
276
#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \
drivers/gpu/drm/i915/display/intel_display_device.h
277
(DISPLAY_INFO((display))->cursor_offsets[(pipe)] - \
drivers/gpu/drm/i915/display/intel_display_device.h
278
DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \
drivers/gpu/drm/i915/display/intel_display_device.h
279
DISPLAY_MMIO_BASE((display)))
drivers/gpu/drm/i915/display/intel_display_device.h
281
#define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset)
drivers/gpu/drm/i915/display/intel_display_device.h
341
bool intel_display_device_present(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_device.h
342
bool intel_display_device_enabled(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_device.h
345
void intel_display_device_remove(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_device.h
346
void intel_display_device_info_runtime_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.c
114
static void intel_mode_config_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
116
struct drm_mode_config *mode_config = &display->drm->mode_config;
drivers/gpu/drm/i915/display/intel_display_driver.c
118
drm_mode_config_init(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
119
INIT_LIST_HEAD(&display->global.obj_list);
drivers/gpu/drm/i915/display/intel_display_driver.c
120
INIT_LIST_HEAD(&display->pipe_list);
drivers/gpu/drm/i915/display/intel_display_driver.c
131
mode_config->async_page_flip = HAS_ASYNC_FLIPS(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
137
if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/intel_display_driver.c
140
} else if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_display_driver.c
143
} else if (DISPLAY_VER(display) == 3) {
drivers/gpu/drm/i915/display/intel_display_driver.c
151
intel_cursor_mode_config_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
154
static void intel_mode_config_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
156
intel_atomic_global_obj_cleanup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
157
drm_mode_config_cleanup(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
160
static void intel_plane_possible_crtcs_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
164
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/intel_display_driver.c
165
struct intel_crtc *crtc = intel_crtc_for_pipe(display,
drivers/gpu/drm/i915/display/intel_display_driver.c
172
void intel_display_driver_early_probe(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
175
intel_pch_detect(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
177
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
180
spin_lock_init(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_display_driver.c
181
mutex_init(&display->backlight.lock);
drivers/gpu/drm/i915/display/intel_display_driver.c
182
mutex_init(&display->audio.mutex);
drivers/gpu/drm/i915/display/intel_display_driver.c
183
mutex_init(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/intel_display_driver.c
184
mutex_init(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_display_driver.c
185
mutex_init(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_display_driver.c
187
intel_display_irq_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
188
intel_dkl_phy_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
189
intel_color_init_hooks(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
190
intel_init_cdclk_hooks(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
191
intel_audio_hooks_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
192
intel_dpll_init_clock_hook(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
193
intel_init_display_hooks(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
194
intel_fdi_init_hook(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
195
intel_dmc_wl_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
199
int intel_display_driver_probe_noirq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
203
if (HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_display_driver.c
204
ret = drm_vblank_init(display->drm,
drivers/gpu/drm/i915/display/intel_display_driver.c
205
INTEL_NUM_PIPES(display));
drivers/gpu/drm/i915/display/intel_display_driver.c
210
intel_bios_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
212
intel_psr_dc5_dc6_wa_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
215
ret = intel_display_power_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
219
intel_pmdemand_init_early(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
221
intel_display_power_init_hw(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
223
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
226
display->hotplug.dp_wq = alloc_ordered_workqueue("intel-dp", 0);
drivers/gpu/drm/i915/display/intel_display_driver.c
227
if (!display->hotplug.dp_wq) {
drivers/gpu/drm/i915/display/intel_display_driver.c
232
display->wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
drivers/gpu/drm/i915/display/intel_display_driver.c
233
if (!display->wq.modeset) {
drivers/gpu/drm/i915/display/intel_display_driver.c
238
display->wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
drivers/gpu/drm/i915/display/intel_display_driver.c
240
if (!display->wq.flip) {
drivers/gpu/drm/i915/display/intel_display_driver.c
245
display->wq.cleanup = alloc_workqueue("i915_cleanup", WQ_HIGHPRI | WQ_PERCPU, 0);
drivers/gpu/drm/i915/display/intel_display_driver.c
246
if (!display->wq.cleanup) {
drivers/gpu/drm/i915/display/intel_display_driver.c
251
display->wq.unordered = alloc_workqueue("display_unordered", WQ_PERCPU, 0);
drivers/gpu/drm/i915/display/intel_display_driver.c
252
if (!display->wq.unordered) {
drivers/gpu/drm/i915/display/intel_display_driver.c
257
intel_dmc_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
259
intel_mode_config_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
261
ret = intel_cdclk_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
265
ret = intel_color_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
269
ret = intel_dbuf_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
273
ret = intel_dbuf_bw_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
277
ret = intel_bw_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
281
ret = intel_pmdemand_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
285
intel_init_quirks(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
287
intel_fbc_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
292
destroy_workqueue(display->wq.unordered);
drivers/gpu/drm/i915/display/intel_display_driver.c
294
destroy_workqueue(display->wq.cleanup);
drivers/gpu/drm/i915/display/intel_display_driver.c
296
destroy_workqueue(display->wq.flip);
drivers/gpu/drm/i915/display/intel_display_driver.c
298
destroy_workqueue(display->wq.modeset);
drivers/gpu/drm/i915/display/intel_display_driver.c
300
destroy_workqueue(display->hotplug.dp_wq);
drivers/gpu/drm/i915/display/intel_display_driver.c
302
intel_dmc_fini(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
303
intel_display_power_driver_remove(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
305
intel_bios_driver_remove(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
311
static void set_display_access(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_driver.c
319
err = drm_modeset_lock_all_ctx(display->drm, &ctx);
drivers/gpu/drm/i915/display/intel_display_driver.c
323
display->access.any_task_allowed = any_task_allowed;
drivers/gpu/drm/i915/display/intel_display_driver.c
324
display->access.allowed_task = allowed_task;
drivers/gpu/drm/i915/display/intel_display_driver.c
327
drm_WARN_ON(display->drm, err);
drivers/gpu/drm/i915/display/intel_display_driver.c
340
void intel_display_driver_enable_user_access(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
342
set_display_access(display, true, NULL);
drivers/gpu/drm/i915/display/intel_display_driver.c
344
intel_hpd_enable_detection_work(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
364
void intel_display_driver_disable_user_access(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
366
intel_hpd_disable_detection_work(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
368
set_display_access(display, false, current);
drivers/gpu/drm/i915/display/intel_display_driver.c
383
void intel_display_driver_suspend_access(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
385
set_display_access(display, false, NULL);
drivers/gpu/drm/i915/display/intel_display_driver.c
402
void intel_display_driver_resume_access(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
404
set_display_access(display, false, current);
drivers/gpu/drm/i915/display/intel_display_driver.c
418
bool intel_display_driver_check_access(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
423
if (display->access.any_task_allowed ||
drivers/gpu/drm/i915/display/intel_display_driver.c
424
display->access.allowed_task == current)
drivers/gpu/drm/i915/display/intel_display_driver.c
430
if (display->access.allowed_task)
drivers/gpu/drm/i915/display/intel_display_driver.c
432
display->access.allowed_task->comm,
drivers/gpu/drm/i915/display/intel_display_driver.c
433
task_pid_vnr(display->access.allowed_task));
drivers/gpu/drm/i915/display/intel_display_driver.c
435
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_driver.c
443
int intel_display_driver_probe_nogem(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
447
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
450
intel_wm_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
452
intel_panel_sanitize_ssc(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
454
intel_pps_setup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
456
intel_gmbus_setup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
458
ret = intel_crtc_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
462
intel_plane_possible_crtcs_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
463
intel_dpll_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
464
intel_fdi_pll_freq_update(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
466
intel_display_driver_init_hw(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
467
intel_dpll_update_ref_clks(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
469
if (display->cdclk.max_cdclk_freq == 0)
drivers/gpu/drm/i915/display/intel_display_driver.c
470
intel_update_max_cdclk(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
472
intel_hti_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
474
intel_setup_outputs(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
476
ret = intel_dp_tunnel_mgr_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
480
intel_display_driver_disable_user_access(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
482
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
483
intel_modeset_setup_hw_state(display, display->drm->mode_config.acquire_ctx);
drivers/gpu/drm/i915/display/intel_display_driver.c
484
intel_acpi_assign_connector_fwnodes(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
485
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
487
intel_initial_plane_config(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
494
if (!HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
495
ilk_wm_sanitize(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
500
intel_hdcp_component_fini(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
502
intel_mode_config_cleanup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
508
int intel_display_driver_probe(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
512
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
520
intel_hdcp_component_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
522
intel_flipq_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
530
ret = intel_initial_commit(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
532
drm_dbg_kms(display->drm, "Initial modeset failed, %d\n", ret);
drivers/gpu/drm/i915/display/intel_display_driver.c
534
intel_overlay_setup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
537
intel_hpd_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
539
skl_watermark_ipc_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
544
void intel_display_driver_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
546
struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,
drivers/gpu/drm/i915/display/intel_display_driver.c
549
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
552
intel_vga_register(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
555
intel_opregion_register(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
556
intel_acpi_video_register(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
558
intel_audio_init(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
560
intel_display_driver_enable_user_access(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
562
intel_audio_register(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
564
intel_display_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
571
drm_kms_helper_poll_init(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
572
intel_hpd_poll_disable(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
574
intel_fbdev_setup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
576
intel_display_device_info_print(DISPLAY_INFO(display),
drivers/gpu/drm/i915/display/intel_display_driver.c
577
DISPLAY_RUNTIME_INFO(display), &p);
drivers/gpu/drm/i915/display/intel_display_driver.c
583
void intel_display_driver_remove(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
585
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
588
flush_workqueue(display->wq.flip);
drivers/gpu/drm/i915/display/intel_display_driver.c
589
flush_workqueue(display->wq.modeset);
drivers/gpu/drm/i915/display/intel_display_driver.c
590
flush_workqueue(display->wq.cleanup);
drivers/gpu/drm/i915/display/intel_display_driver.c
591
flush_workqueue(display->wq.unordered);
drivers/gpu/drm/i915/display/intel_display_driver.c
598
intel_dp_mst_suspend(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
602
void intel_display_driver_remove_noirq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
604
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
607
intel_display_driver_suspend_access(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
613
intel_hpd_poll_fini(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
618
flush_workqueue(display->wq.unordered);
drivers/gpu/drm/i915/display/intel_display_driver.c
620
intel_hdcp_component_fini(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
622
intel_mode_config_cleanup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
624
intel_dp_tunnel_mgr_cleanup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
626
intel_overlay_cleanup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
628
intel_gmbus_teardown(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
630
destroy_workqueue(display->hotplug.dp_wq);
drivers/gpu/drm/i915/display/intel_display_driver.c
631
destroy_workqueue(display->wq.flip);
drivers/gpu/drm/i915/display/intel_display_driver.c
632
destroy_workqueue(display->wq.modeset);
drivers/gpu/drm/i915/display/intel_display_driver.c
633
destroy_workqueue(display->wq.cleanup);
drivers/gpu/drm/i915/display/intel_display_driver.c
634
destroy_workqueue(display->wq.unordered);
drivers/gpu/drm/i915/display/intel_display_driver.c
636
intel_fbc_cleanup(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
640
void intel_display_driver_remove_nogem(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
642
intel_dmc_fini(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
644
intel_display_power_driver_remove(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
646
intel_bios_driver_remove(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
649
void intel_display_driver_unregister(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
651
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
656
drm_client_dev_unregister(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
663
drm_kms_helper_poll_fini(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
665
intel_display_driver_disable_user_access(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
667
intel_audio_deinit(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
669
drm_atomic_helper_shutdown(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
672
intel_opregion_unregister(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
674
intel_vga_unregister(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
681
int intel_display_driver_suspend(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
686
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
689
state = drm_atomic_helper_suspend(display->drm);
drivers/gpu/drm/i915/display/intel_display_driver.c
692
drm_err(display->drm, "Suspending crtc's failed with %i\n",
drivers/gpu/drm/i915/display/intel_display_driver.c
695
display->restore.modeset_state = state;
drivers/gpu/drm/i915/display/intel_display_driver.c
698
flush_workqueue(display->wq.cleanup);
drivers/gpu/drm/i915/display/intel_display_driver.c
700
intel_dp_mst_suspend(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
706
__intel_display_driver_resume(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_driver.c
714
intel_modeset_setup_hw_state(display, ctx);
drivers/gpu/drm/i915/display/intel_display_driver.c
734
if (!HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
739
drm_WARN_ON(display->drm, ret == -EDEADLK);
drivers/gpu/drm/i915/display/intel_display_driver.c
744
void intel_display_driver_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
746
struct drm_atomic_commit *state = display->restore.modeset_state;
drivers/gpu/drm/i915/display/intel_display_driver.c
750
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
754
intel_dp_mst_resume(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
756
display->restore.modeset_state = NULL;
drivers/gpu/drm/i915/display/intel_display_driver.c
763
ret = drm_modeset_lock_all_ctx(display->drm, &ctx);
drivers/gpu/drm/i915/display/intel_display_driver.c
771
ret = __intel_display_driver_resume(display, state, &ctx);
drivers/gpu/drm/i915/display/intel_display_driver.c
773
skl_watermark_ipc_update(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
778
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_driver.c
89
void intel_display_driver_init_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_driver.c
91
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_driver.c
94
intel_cdclk_read_hw(display);
drivers/gpu/drm/i915/display/intel_display_driver.c
96
intel_display_wa_apply(display);
drivers/gpu/drm/i915/display/intel_display_driver.h
17
void intel_display_driver_init_hw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
18
void intel_display_driver_early_probe(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
19
int intel_display_driver_probe_noirq(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
20
int intel_display_driver_probe_nogem(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
21
int intel_display_driver_probe(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
22
void intel_display_driver_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
23
void intel_display_driver_remove(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
24
void intel_display_driver_remove_noirq(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
25
void intel_display_driver_remove_nogem(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
26
void intel_display_driver_unregister(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
27
int intel_display_driver_suspend(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
28
void intel_display_driver_resume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
31
int __intel_display_driver_resume(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_driver.h
35
void intel_display_driver_enable_user_access(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
36
void intel_display_driver_disable_user_access(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
37
void intel_display_driver_suspend_access(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
38
void intel_display_driver_resume_access(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_driver.h
39
bool intel_display_driver_check_access(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1008
if (!HAS_PCH_NOP(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1009
*sde_ier = intel_de_read_fw(display, SDEIER);
drivers/gpu/drm/i915/display/intel_display_irq.c
1010
intel_de_write_fw(display, SDEIER, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1016
void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier)
drivers/gpu/drm/i915/display/intel_display_irq.c
1018
intel_de_write_fw(display, DEIER, de_ier);
drivers/gpu/drm/i915/display/intel_display_irq.c
1021
intel_de_write_fw(display, SDEIER, sde_ier);
drivers/gpu/drm/i915/display/intel_display_irq.c
1024
static bool ilk_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1030
de_iir = intel_de_read_fw(display, DEIIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1032
intel_de_write_fw(display, DEIIR, de_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1033
if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/intel_display_irq.c
1034
_ivb_display_irq_handler(display, de_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1036
_ilk_display_irq_handler(display, de_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1043
static u32 gen8_de_port_aux_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1047
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_display_irq.c
1049
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_irq.c
1052
else if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_display_irq.c
1062
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_irq.c
1074
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display_irq.c
1079
if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/intel_display_irq.c
108
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1087
static u32 gen8_de_pipe_fault_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1089
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_display_irq.c
1097
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_irq.c
1107
else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
1115
else if (DISPLAY_VER(display) == 12)
drivers/gpu/drm/i915/display/intel_display_irq.c
1125
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display_irq.c
1134
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display_irq.c
1148
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1150
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1159
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1161
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1170
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1172
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
118
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1234
gen8_pipe_fault_handlers(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1236
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_irq.c
1238
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_irq.c
1240
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display_irq.c
1242
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display_irq.c
1248
static void intel_pmdemand_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1250
wake_up_all(&display->pmdemand.waitqueue);
drivers/gpu/drm/i915/display/intel_display_irq.c
1254
gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
1258
if (HAS_DBUF_OVERLAP_DETECTION(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1260
drm_warn(display->drm, "DBuf overlap detected\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
1265
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1269
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
127
static void intel_pipe_fault_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1272
intel_pmdemand_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1277
u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);
drivers/gpu/drm/i915/display/intel_display_irq.c
1278
drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val);
drivers/gpu/drm/i915/display/intel_display_irq.c
1282
intel_opregion_asle_intr(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1291
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1294
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_irq.c
1295
iir_reg = TRANS_PSR_IIR(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1300
psr_iir = intel_de_rmw(display, iir_reg, 0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1308
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_display_irq.c
131
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1314
drm_err(display->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1317
static void gen11_dsi_te_interrupt_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1329
val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));
drivers/gpu/drm/i915/display/intel_display_irq.c
1341
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
drivers/gpu/drm/i915/display/intel_display_irq.c
1345
drm_err(display->drm, "DSI trancoder not configured in command mode\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
1350
val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));
drivers/gpu/drm/i915/display/intel_display_irq.c
1362
drm_err(display->drm, "Invalid PIPE\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
1366
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1370
intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1373
static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1375
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display_irq.c
1381
static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
1386
*pch_iir = intel_de_read(display, SDEIIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1396
drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL);
drivers/gpu/drm/i915/display/intel_display_irq.c
1398
pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1399
*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1400
intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1403
intel_de_write(display, SDEIIR, *pch_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1406
intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
drivers/gpu/drm/i915/display/intel_display_irq.c
1409
static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
drivers/gpu/drm/i915/display/intel_display_irq.c
1414
drm_WARN_ON_ONCE(display->drm, !HAS_DISPLAY(display));
drivers/gpu/drm/i915/display/intel_display_irq.c
1417
iir = intel_de_read(display, GEN8_DE_MISC_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1419
intel_de_write(display, GEN8_DE_MISC_IIR, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1420
gen8_de_misc_irq_handler(display, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1422
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1427
if (DISPLAY_VER(display) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1428
iir = intel_de_read(display, GEN11_DE_HPD_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1430
intel_de_write(display, GEN11_DE_HPD_IIR, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1431
gen11_hpd_irq_handler(display, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1433
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1439
iir = intel_de_read(display, GEN8_DE_PORT_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1443
intel_de_write(display, GEN8_DE_PORT_IIR, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1445
if (iir & gen8_de_port_aux_mask(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1446
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1450
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1454
bxt_hpd_irq_handler(display, hotplug_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
1457
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1461
ilk_hpd_irq_handler(display, hotplug_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
1466
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/intel_display_irq.c
1468
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
147
intel_handle_vblank(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
1472
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1476
gen11_dsi_te_interrupt_handler(display, te_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
1482
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1485
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
149
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1490
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1496
iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
1498
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1504
intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1507
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1509
if (iir & gen8_de_pipe_flip_done_mask(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
1510
flip_done_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1512
if (HAS_DSB(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1514
intel_dsb_irq_handler(display, pipe, INTEL_DSB_0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1517
intel_dsb_irq_handler(display, pipe, INTEL_DSB_1);
drivers/gpu/drm/i915/display/intel_display_irq.c
1520
intel_dsb_irq_handler(display, pipe, INTEL_DSB_2);
drivers/gpu/drm/i915/display/intel_display_irq.c
1523
if (HAS_PIPEDMC(display) && iir & GEN12_PIPEDMC_INTERRUPT)
drivers/gpu/drm/i915/display/intel_display_irq.c
1524
intel_pipedmc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1527
hsw_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1530
intel_cpu_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
1532
fault_errors = iir & gen8_de_pipe_fault_mask(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1534
intel_pipe_fault_irq_handler(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1535
gen8_pipe_fault_handlers(display),
drivers/gpu/drm/i915/display/intel_display_irq.c
1539
if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) &&
drivers/gpu/drm/i915/display/intel_display_irq.c
1548
gen8_read_and_ack_pch_irqs(display, &iir, &pica_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1551
xelpdp_pica_irq_handler(display, pica_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1553
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_display_irq.c
1554
icp_irq_handler(display, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1555
else if (INTEL_PCH_TYPE(display) >= PCH_SPT)
drivers/gpu/drm/i915/display/intel_display_irq.c
1556
spt_irq_handler(display, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1558
cpt_irq_handler(display, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1564
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
1570
static bool gen8_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1573
gen8_de_irq_handler(display, state->master_ctl);
drivers/gpu/drm/i915/display/intel_display_irq.c
1578
u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
drivers/gpu/drm/i915/display/intel_display_irq.c
1585
intel_display_rpm_assert_block(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1587
iir = intel_de_read(display, GEN11_GU_MISC_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1589
intel_de_write(display, GEN11_GU_MISC_IIR, iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1591
intel_display_rpm_assert_unblock(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1596
void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
1599
intel_opregion_asle_intr(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
160
void ilk_update_display_irq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1602
static bool gen11_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1607
intel_display_rpm_assert_block(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1612
disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);
drivers/gpu/drm/i915/display/intel_display_irq.c
1614
intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1615
gen8_de_irq_handler(display, disp_ctl);
drivers/gpu/drm/i915/display/intel_display_irq.c
1616
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
drivers/gpu/drm/i915/display/intel_display_irq.c
1618
intel_display_rpm_assert_unblock(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1623
static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1625
lockdep_assert_held(&display->drm->vblank_time_lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
1633
if (display->irq.vblank_enabled++ == 0)
drivers/gpu/drm/i915/display/intel_display_irq.c
1634
intel_de_write(display, SCPD0,
drivers/gpu/drm/i915/display/intel_display_irq.c
1638
static void i915gm_irq_cstate_wa_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1640
lockdep_assert_held(&display->drm->vblank_time_lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
1642
if (--display->irq.vblank_enabled == 0)
drivers/gpu/drm/i915/display/intel_display_irq.c
1643
intel_de_write(display, SCPD0,
drivers/gpu/drm/i915/display/intel_display_irq.c
1647
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/intel_display_irq.c
1649
spin_lock_irq(&display->drm->vblank_time_lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
165
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
1652
i915gm_irq_cstate_wa_enable(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1654
i915gm_irq_cstate_wa_disable(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1656
spin_unlock_irq(&display->drm->vblank_time_lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
166
drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
1661
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
1665
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1666
i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
1667
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1674
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
1678
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1679
i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
168
new_val = display->irq.ilk_de_imr_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
1680
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1685
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
1687
i915gm_irq_cstate_wa_enable(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1694
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
1698
i915gm_irq_cstate_wa_disable(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1703
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
1707
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1708
i915_enable_pipestat(display, pipe,
drivers/gpu/drm/i915/display/intel_display_irq.c
1710
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1717
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
172
if (new_val != display->irq.ilk_de_imr_mask &&
drivers/gpu/drm/i915/display/intel_display_irq.c
1721
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1722
i915_disable_pipestat(display, pipe,
drivers/gpu/drm/i915/display/intel_display_irq.c
1724
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1729
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
173
!drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1732
u32 bit = DISPLAY_VER(display) >= 7 ?
drivers/gpu/drm/i915/display/intel_display_irq.c
1735
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1736
ilk_enable_display_irq(display, bit);
drivers/gpu/drm/i915/display/intel_display_irq.c
1737
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
174
display->irq.ilk_de_imr_mask = new_val;
drivers/gpu/drm/i915/display/intel_display_irq.c
1742
if (HAS_PSR(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
175
intel_de_write(display, DEIMR, display->irq.ilk_de_imr_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
1750
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_irq.c
1753
u32 bit = DISPLAY_VER(display) >= 7 ?
drivers/gpu/drm/i915/display/intel_display_irq.c
1756
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1757
ilk_disable_display_irq(display, bit);
drivers/gpu/drm/i915/display/intel_display_irq.c
1758
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
176
intel_de_posting_read(display, DEIMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1764
struct intel_display *display = to_intel_display(intel_crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1777
intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT);
drivers/gpu/drm/i915/display/intel_display_irq.c
1779
intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1786
struct intel_display *display =
drivers/gpu/drm/i915/display/intel_display_irq.c
1787
container_of(work, typeof(*display), irq.vblank_notify_work);
drivers/gpu/drm/i915/display/intel_display_irq.c
1788
int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count);
drivers/gpu/drm/i915/display/intel_display_irq.c
1791
if (display->irq.vblank_status_last_notified != vblank_status) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1792
intel_psr_notify_vblank_enable_disable(display, vblank_status);
drivers/gpu/drm/i915/display/intel_display_irq.c
1793
display->irq.vblank_status_last_notified = vblank_status;
drivers/gpu/drm/i915/display/intel_display_irq.c
180
void ilk_enable_display_irq(struct intel_display *display, u32 bits)
drivers/gpu/drm/i915/display/intel_display_irq.c
1800
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1807
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1808
if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0)
drivers/gpu/drm/i915/display/intel_display_irq.c
1809
schedule_work(&display->irq.vblank_notify_work);
drivers/gpu/drm/i915/display/intel_display_irq.c
1811
bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);
drivers/gpu/drm/i915/display/intel_display_irq.c
1812
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1817
if (HAS_PSR(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
182
ilk_update_display_irq(display, bits, bits);
drivers/gpu/drm/i915/display/intel_display_irq.c
1826
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_irq.c
1833
spin_lock_irqsave(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1834
bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);
drivers/gpu/drm/i915/display/intel_display_irq.c
1835
spin_unlock_irqrestore(&display->irq.lock, irqflags);
drivers/gpu/drm/i915/display/intel_display_irq.c
1837
if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0)
drivers/gpu/drm/i915/display/intel_display_irq.c
1838
schedule_work(&display->irq.vblank_notify_work);
drivers/gpu/drm/i915/display/intel_display_irq.c
185
void ilk_disable_display_irq(struct intel_display *display, u32 bits)
drivers/gpu/drm/i915/display/intel_display_irq.c
187
ilk_update_display_irq(display, bits, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1880
static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt)
drivers/gpu/drm/i915/display/intel_display_irq.c
1884
tmp = intel_de_read(display, DPINVGTT);
drivers/gpu/drm/i915/display/intel_display_irq.c
1900
intel_de_write(display, DPINVGTT, status);
drivers/gpu/drm/i915/display/intel_display_irq.c
1901
intel_de_write(display, DPINVGTT, enable << 16);
drivers/gpu/drm/i915/display/intel_display_irq.c
1904
static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt)
drivers/gpu/drm/i915/display/intel_display_irq.c
1908
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1913
intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers,
drivers/gpu/drm/i915/display/intel_display_irq.c
1918
static void vlv_display_error_irq_ack(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1923
*eir = intel_de_read(display, VLV_EIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1926
vlv_page_table_error_irq_ack(display, dpinvgtt);
drivers/gpu/drm/i915/display/intel_display_irq.c
1928
intel_de_write(display, VLV_EIR, *eir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1935
emr = intel_de_read(display, VLV_EMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
1936
intel_de_write(display, VLV_EMR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
1937
intel_de_write(display, VLV_EMR, emr);
drivers/gpu/drm/i915/display/intel_display_irq.c
1940
static void vlv_display_error_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1943
drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
drivers/gpu/drm/i915/display/intel_display_irq.c
1946
vlv_page_table_error_irq_handler(display, dpinvgtt);
drivers/gpu/drm/i915/display/intel_display_irq.c
1949
static void _vlv_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1951
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display_irq.c
1952
intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
drivers/gpu/drm/i915/display/intel_display_irq.c
1954
intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
drivers/gpu/drm/i915/display/intel_display_irq.c
1956
error_reset(display, VLV_ERROR_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
1958
i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1959
intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
196
void bdw_update_port_irq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
1961
i9xx_pipestat_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1963
irq_reset(display, VLV_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
1964
display->irq.vlv_imr_mask = ~0u;
drivers/gpu/drm/i915/display/intel_display_irq.c
1967
static void vlv_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1969
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
1970
if (display->irq.vlv_display_irqs_enabled)
drivers/gpu/drm/i915/display/intel_display_irq.c
1971
_vlv_display_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1972
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
1975
static void i9xx_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1977
if (HAS_HOTPLUG(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
1978
i915_hotplug_interrupt_update(display, 0xffffffff, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1979
intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
1982
i9xx_pipestat_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
1985
u32 i9xx_display_irq_enable_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
1992
if (DISPLAY_VER(display) >= 3)
drivers/gpu/drm/i915/display/intel_display_irq.c
1995
if (HAS_HOTPLUG(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2001
static void i915_display_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2007
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2008
i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2009
i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2010
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2012
i915_enable_asle_pipestat(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2015
static void i965_display_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
202
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2021
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2022
i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2023
i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2024
i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2025
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2027
i915_enable_asle_pipestat(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2030
static void i9xx_display_irq_ack(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2034
state->hotplug_status = i9xx_hpd_irq_ack(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2037
i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
drivers/gpu/drm/i915/display/intel_display_irq.c
204
drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
2040
static bool i965_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2044
i9xx_hpd_irq_handler(display, state->hotplug_status);
drivers/gpu/drm/i915/display/intel_display_irq.c
2046
i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
drivers/gpu/drm/i915/display/intel_display_irq.c
2051
static bool i915_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2055
i9xx_hpd_irq_handler(display, state->hotplug_status);
drivers/gpu/drm/i915/display/intel_display_irq.c
2057
i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
drivers/gpu/drm/i915/display/intel_display_irq.c
206
if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)))
drivers/gpu/drm/i915/display/intel_display_irq.c
2068
static void _vlv_display_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2074
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display_irq.c
2075
intel_de_write(display, DPINVGTT,
drivers/gpu/drm/i915/display/intel_display_irq.c
2079
intel_de_write(display, DPINVGTT,
drivers/gpu/drm/i915/display/intel_display_irq.c
2083
error_init(display, VLV_ERROR_REGS, ~vlv_error_mask());
drivers/gpu/drm/i915/display/intel_display_irq.c
2087
i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2088
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
2089
i915_enable_pipestat(display, pipe, pipestat_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
209
old_val = intel_de_read(display, GEN8_DE_PORT_IMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2098
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display_irq.c
2102
drm_WARN_ON(display->drm, display->irq.vlv_imr_mask != ~0u);
drivers/gpu/drm/i915/display/intel_display_irq.c
2104
display->irq.vlv_imr_mask = ~enable_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
2106
irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
2109
static void vlv_display_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2111
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2112
if (display->irq.vlv_display_irqs_enabled)
drivers/gpu/drm/i915/display/intel_display_irq.c
2113
_vlv_display_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2114
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2117
static u32 vlv_lpe_irq_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2119
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display_irq.c
2126
static void vlv_display_irq_ack(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2130
state->hotplug_status = i9xx_hpd_irq_ack(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2133
vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
drivers/gpu/drm/i915/display/intel_display_irq.c
2136
i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
drivers/gpu/drm/i915/display/intel_display_irq.c
2139
if (state->iir & vlv_lpe_irq_mask(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2140
intel_lpe_audio_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2143
static bool vlv_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2147
i9xx_hpd_irq_handler(display, state->hotplug_status);
drivers/gpu/drm/i915/display/intel_display_irq.c
2150
vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
drivers/gpu/drm/i915/display/intel_display_irq.c
2152
valleyview_pipestat_irq_handler(display, state->pipe_stats);
drivers/gpu/drm/i915/display/intel_display_irq.c
2157
static void ibx_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2159
if (HAS_PCH_NOP(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
216
intel_de_write(display, GEN8_DE_PORT_IMR, new_val);
drivers/gpu/drm/i915/display/intel_display_irq.c
2162
irq_reset(display, SDE_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2164
if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2165
intel_de_write(display, SERR_INT, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2168
static void ilk_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
217
intel_de_posting_read(display, GEN8_DE_PORT_IMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2170
irq_reset(display, DE_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2171
display->irq.ilk_de_imr_mask = ~0u;
drivers/gpu/drm/i915/display/intel_display_irq.c
2173
if (DISPLAY_VER(display) == 7)
drivers/gpu/drm/i915/display/intel_display_irq.c
2174
intel_de_write(display, GEN7_ERR_INT, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2176
if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2177
intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2178
intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2181
ibx_display_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2184
static void gen8_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2188
intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2189
intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2191
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
2192
if (intel_display_power_is_enabled(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2194
irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
2196
irq_reset(display, GEN8_DE_PORT_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2197
irq_reset(display, GEN8_DE_MISC_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2199
if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2200
ibx_display_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2203
static void gen11_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2209
intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
2211
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2214
for_each_cpu_transcoder_masked(display, trans, trans_mask) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2218
if (!intel_display_power_is_enabled(display, domain))
drivers/gpu/drm/i915/display/intel_display_irq.c
2221
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2222
TRANS_PSR_IMR(display, trans),
drivers/gpu/drm/i915/display/intel_display_irq.c
2224
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2225
TRANS_PSR_IIR(display, trans),
drivers/gpu/drm/i915/display/intel_display_irq.c
2229
intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2230
intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2233
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
2234
if (intel_display_power_is_enabled(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2236
irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
2238
irq_reset(display, GEN8_DE_PORT_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2239
irq_reset(display, GEN8_DE_MISC_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2241
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_irq.c
2242
irq_reset(display, PICAINTERRUPT_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2244
irq_reset(display, GEN11_DE_HPD_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2246
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_display_irq.c
2247
irq_reset(display, SDE_IRQ_REGS);
drivers/gpu/drm/i915/display/intel_display_irq.c
2250
void gen8_irq_power_well_post_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2254
gen8_de_pipe_flip_done_mask(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2257
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2259
if (!intel_parent_irq_enabled(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2260
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2264
for_each_pipe_masked(display, pipe, pipe_mask)
drivers/gpu/drm/i915/display/intel_display_irq.c
2265
irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
drivers/gpu/drm/i915/display/intel_display_irq.c
2266
display->irq.de_pipe_imr_mask[pipe],
drivers/gpu/drm/i915/display/intel_display_irq.c
2267
~display->irq.de_pipe_imr_mask[pipe] | extra_ier);
drivers/gpu/drm/i915/display/intel_display_irq.c
2269
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2272
void gen8_irq_power_well_pre_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2277
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2279
if (!intel_parent_irq_enabled(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
228
static void bdw_update_pipe_irq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2280
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2284
for_each_pipe_masked(display, pipe, pipe_mask)
drivers/gpu/drm/i915/display/intel_display_irq.c
2285
irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
2287
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2290
intel_parent_irq_synchronize(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2304
static void ibx_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2308
if (HAS_PCH_NOP(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2311
if (HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2313
else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2318
irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2321
void valleyview_enable_display_irqs(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2323
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2325
if (display->irq.vlv_display_irqs_enabled)
drivers/gpu/drm/i915/display/intel_display_irq.c
2328
display->irq.vlv_display_irqs_enabled = true;
drivers/gpu/drm/i915/display/intel_display_irq.c
2330
if (intel_parent_irq_enabled(display)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2331
_vlv_display_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2332
_vlv_display_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2336
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2339
void valleyview_disable_display_irqs(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
234
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2341
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2343
if (!display->irq.vlv_display_irqs_enabled)
drivers/gpu/drm/i915/display/intel_display_irq.c
2346
display->irq.vlv_display_irqs_enabled = false;
drivers/gpu/drm/i915/display/intel_display_irq.c
2348
if (intel_parent_irq_enabled(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2349
_vlv_display_irq_reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2351
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2354
static void ilk_de_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2358
if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/intel_display_irq.c
236
drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
2379
if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display_irq.c
238
if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)))
drivers/gpu/drm/i915/display/intel_display_irq.c
2380
assert_iir_is_zero(display, EDP_PSR_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2384
if (display->platform.ironlake && display->platform.mobile)
drivers/gpu/drm/i915/display/intel_display_irq.c
2387
display->irq.ilk_de_imr_mask = ~display_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
2389
ibx_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2391
irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask,
drivers/gpu/drm/i915/display/intel_display_irq.c
2395
static void mtp_irq_postinstall(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2396
static void icp_irq_postinstall(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2398
static void gen8_de_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2400
u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
drivers/gpu/drm/i915/display/intel_display_irq.c
2403
u32 de_port_masked = gen8_de_port_aux_mask(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
241
new_val = display->irq.de_pipe_imr_mask[pipe];
drivers/gpu/drm/i915/display/intel_display_irq.c
2410
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2413
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_irq.c
2414
mtp_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2415
else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_display_irq.c
2416
icp_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2417
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2418
ibx_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2420
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_display_irq.c
2423
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_irq.c
2426
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2429
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2432
if (intel_bios_is_dsi_present(display, &port))
drivers/gpu/drm/i915/display/intel_display_irq.c
2436
if (HAS_DBUF_OVERLAP_DETECTION(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2439
if (HAS_DSB(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2445
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_display_irq.c
245
if (new_val != display->irq.de_pipe_imr_mask[pipe]) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2450
gen8_de_pipe_flip_done_mask(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2453
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_irq.c
2455
else if (display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_display_irq.c
2458
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_display_irq.c
246
display->irq.de_pipe_imr_mask[pipe] = new_val;
drivers/gpu/drm/i915/display/intel_display_irq.c
2461
for_each_cpu_transcoder_masked(display, trans, trans_mask) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2465
if (!intel_display_power_is_enabled(display, domain))
drivers/gpu/drm/i915/display/intel_display_irq.c
2468
assert_iir_is_zero(display, TRANS_PSR_IIR(display, trans));
drivers/gpu/drm/i915/display/intel_display_irq.c
247
intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_pipe_imr_mask[pipe]);
drivers/gpu/drm/i915/display/intel_display_irq.c
2471
assert_iir_is_zero(display, EDP_PSR_IIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2474
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2475
display->irq.de_pipe_imr_mask[pipe] = ~de_pipe_masked;
drivers/gpu/drm/i915/display/intel_display_irq.c
2477
if (intel_display_power_is_enabled(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2479
irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),
drivers/gpu/drm/i915/display/intel_display_irq.c
248
intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
2480
display->irq.de_pipe_imr_mask[pipe],
drivers/gpu/drm/i915/display/intel_display_irq.c
2484
irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
drivers/gpu/drm/i915/display/intel_display_irq.c
2485
irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
drivers/gpu/drm/i915/display/intel_display_irq.c
2487
if (IS_DISPLAY_VER(display, 11, 13)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
2492
irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables);
drivers/gpu/drm/i915/display/intel_display_irq.c
2496
u32 xelpdp_pica_aux_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2500
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_display_irq.c
2506
static void mtp_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2509
u32 de_hpd_mask = xelpdp_pica_aux_mask(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2513
irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables);
drivers/gpu/drm/i915/display/intel_display_irq.c
2515
irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2518
static void icp_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
252
void bdw_enable_pipe_irq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2522
irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
2525
static void gen11_de_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2527
gen8_de_irq_postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2529
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
drivers/gpu/drm/i915/display/intel_display_irq.c
2533
void (*reset)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2534
void (*postinstall)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2535
void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
drivers/gpu/drm/i915/display/intel_display_irq.c
2536
bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
drivers/gpu/drm/i915/display/intel_display_irq.c
255
bdw_update_pipe_irq(display, pipe, bits, bits);
drivers/gpu/drm/i915/display/intel_display_irq.c
2578
void intel_display_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
258
void bdw_disable_pipe_irq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2580
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2583
display->irq.funcs->reset(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2586
void intel_display_irq_postinstall(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2588
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2591
display->irq.funcs->postinstall(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2594
void intel_display_irq_ack(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2597
if (!HAS_DISPLAY(display) || !display->irq.funcs->ack)
drivers/gpu/drm/i915/display/intel_display_irq.c
2600
display->irq.funcs->ack(display, state);
drivers/gpu/drm/i915/display/intel_display_irq.c
2603
bool intel_display_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
2606
if (!HAS_DISPLAY(display) || !display->irq.funcs->handler)
drivers/gpu/drm/i915/display/intel_display_irq.c
2609
return display->irq.funcs->handler(display, state);
drivers/gpu/drm/i915/display/intel_display_irq.c
261
bdw_update_pipe_irq(display, pipe, bits, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
2612
void intel_display_irq_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2614
spin_lock_init(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
2616
display->drm->vblank_disable_immediate = true;
drivers/gpu/drm/i915/display/intel_display_irq.c
2618
intel_hotplug_irq_init(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
2620
INIT_WORK(&display->irq.vblank_notify_work,
drivers/gpu/drm/i915/display/intel_display_irq.c
2623
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display_irq.c
2624
display->irq.funcs = &gen11_display_irq_funcs;
drivers/gpu/drm/i915/display/intel_display_irq.c
2625
else if (display->platform.cherryview || display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_display_irq.c
2626
display->irq.funcs = &vlv_display_irq_funcs;
drivers/gpu/drm/i915/display/intel_display_irq.c
2627
else if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_display_irq.c
2628
display->irq.funcs = &gen8_display_irq_funcs;
drivers/gpu/drm/i915/display/intel_display_irq.c
2629
else if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_display_irq.c
2630
display->irq.funcs = &ilk_display_irq_funcs;
drivers/gpu/drm/i915/display/intel_display_irq.c
2631
else if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/intel_display_irq.c
2632
display->irq.funcs = &i965_display_irq_funcs;
drivers/gpu/drm/i915/display/intel_display_irq.c
2634
display->irq.funcs = &i915_display_irq_funcs;
drivers/gpu/drm/i915/display/intel_display_irq.c
2643
intel_display_irq_snapshot_capture(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
2651
if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
2652
snapshot->derrmr = intel_de_read(display, DERRMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
2654
if (DISPLAY_VER(display) == 7)
drivers/gpu/drm/i915/display/intel_display_irq.c
2655
snapshot->err_int = intel_de_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_display_irq.c
270
void ibx_display_interrupt_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
274
u32 sdeimr = intel_de_read(display, SDEIMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
279
drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
281
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
283
if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)))
drivers/gpu/drm/i915/display/intel_display_irq.c
286
intel_de_write(display, SDEIMR, sdeimr);
drivers/gpu/drm/i915/display/intel_display_irq.c
287
intel_de_posting_read(display, SDEIMR);
drivers/gpu/drm/i915/display/intel_display_irq.c
290
void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)
drivers/gpu/drm/i915/display/intel_display_irq.c
292
ibx_display_interrupt_update(display, bits, bits);
drivers/gpu/drm/i915/display/intel_display_irq.c
295
void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)
drivers/gpu/drm/i915/display/intel_display_irq.c
297
ibx_display_interrupt_update(display, bits, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
300
u32 i915_pipestat_enable_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
303
u32 status_mask = display->irq.pipestat_irq_mask[pipe];
drivers/gpu/drm/i915/display/intel_display_irq.c
306
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
308
if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_display_irq.c
315
if (drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
322
if (drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
335
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
34
static void irq_reset(struct intel_display *display, struct intel_irq_regs regs)
drivers/gpu/drm/i915/display/intel_display_irq.c
344
void i915_enable_pipestat(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
347
intel_reg_t reg = PIPESTAT(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
350
drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
drivers/gpu/drm/i915/display/intel_display_irq.c
354
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
355
drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display));
drivers/gpu/drm/i915/display/intel_display_irq.c
357
if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)
drivers/gpu/drm/i915/display/intel_display_irq.c
36
intel_de_write(display, regs.imr, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
360
display->irq.pipestat_irq_mask[pipe] |= status_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
361
enable_mask = i915_pipestat_enable_mask(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
363
intel_de_write(display, reg, enable_mask | status_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
364
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_irq.c
367
void i915_disable_pipestat(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
37
intel_de_posting_read(display, regs.imr);
drivers/gpu/drm/i915/display/intel_display_irq.c
370
intel_reg_t reg = PIPESTAT(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
373
drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
drivers/gpu/drm/i915/display/intel_display_irq.c
377
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
378
drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display));
drivers/gpu/drm/i915/display/intel_display_irq.c
380
if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0)
drivers/gpu/drm/i915/display/intel_display_irq.c
383
display->irq.pipestat_irq_mask[pipe] &= ~status_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
384
enable_mask = i915_pipestat_enable_mask(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
386
intel_de_write(display, reg, enable_mask | status_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
387
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_irq.c
39
intel_de_write(display, regs.ier, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
390
static bool i915_has_legacy_blc_interrupt(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
392
if (display->platform.i85x)
drivers/gpu/drm/i915/display/intel_display_irq.c
395
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_display_irq.c
398
return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile;
drivers/gpu/drm/i915/display/intel_display_irq.c
402
static void i915_enable_asle_pipestat(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
404
if (!intel_opregion_asle_present(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
407
if (!i915_has_legacy_blc_interrupt(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
410
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
412
i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
drivers/gpu/drm/i915/display/intel_display_irq.c
413
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_display_irq.c
414
i915_enable_pipestat(display, PIPE_A,
drivers/gpu/drm/i915/display/intel_display_irq.c
417
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
42
intel_de_write(display, regs.iir, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
421
static void display_pipe_crc_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
427
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
43
intel_de_posting_read(display, regs.iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
44
intel_de_write(display, regs.iir, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
443
(DISPLAY_VER(display) >= 8 && pipe_crc->skipped == 1)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
45
intel_de_posting_read(display, regs.iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
456
display_pipe_crc_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
463
static void flip_done_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
466
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
468
spin_lock(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
476
spin_unlock(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
479
static void hsw_pipe_crc_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
482
display_pipe_crc_irq_handler(display, pipe,
drivers/gpu/drm/i915/display/intel_display_irq.c
483
intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
487
static void ivb_pipe_crc_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
490
display_pipe_crc_irq_handler(display, pipe,
drivers/gpu/drm/i915/display/intel_display_irq.c
491
intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
492
intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
493
intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
494
intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
495
intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));
drivers/gpu/drm/i915/display/intel_display_irq.c
498
static void i9xx_pipe_crc_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
503
if (DISPLAY_VER(display) >= 3)
drivers/gpu/drm/i915/display/intel_display_irq.c
504
res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
508
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_display_irq.c
509
res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));
drivers/gpu/drm/i915/display/intel_display_irq.c
51
static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_display_irq.c
513
display_pipe_crc_irq_handler(display, pipe,
drivers/gpu/drm/i915/display/intel_display_irq.c
514
intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
515
intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
516
intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),
drivers/gpu/drm/i915/display/intel_display_irq.c
520
static void i9xx_pipestat_irq_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
524
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
525
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_display_irq.c
526
PIPESTAT(display, pipe),
drivers/gpu/drm/i915/display/intel_display_irq.c
529
display->irq.pipestat_irq_mask[pipe] = 0;
drivers/gpu/drm/i915/display/intel_display_irq.c
53
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_irq.c
533
static void i9xx_pipestat_irq_ack(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
538
spin_lock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
540
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_display_irq.c
541
!display->irq.vlv_display_irqs_enabled) {
drivers/gpu/drm/i915/display/intel_display_irq.c
542
spin_unlock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
546
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
574
status_mask |= display->irq.pipestat_irq_mask[pipe];
drivers/gpu/drm/i915/display/intel_display_irq.c
579
reg = PIPESTAT(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
58
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_display_irq.c
580
pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
drivers/gpu/drm/i915/display/intel_display_irq.c
581
enable_mask = i915_pipestat_enable_mask(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
593
intel_de_write(display, reg, pipe_stats[pipe]);
drivers/gpu/drm/i915/display/intel_display_irq.c
594
intel_de_write(display, reg, enable_mask);
drivers/gpu/drm/i915/display/intel_display_irq.c
597
spin_unlock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_irq.c
600
static void i915_pipestat_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
606
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
608
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
61
intel_de_write(display, reg, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
614
i9xx_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
617
intel_cpu_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
62
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_irq.c
621
intel_opregion_asle_intr(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
624
static void i965_pipestat_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
63
intel_de_write(display, reg, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
630
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
632
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
638
i9xx_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
64
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_irq.c
641
intel_cpu_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
645
intel_opregion_asle_intr(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
648
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
651
static void valleyview_pipestat_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.c
656
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
658
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
661
flip_done_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
664
i9xx_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
667
intel_cpu_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
67
static void irq_init(struct intel_display *display, struct intel_irq_regs regs,
drivers/gpu/drm/i915/display/intel_display_irq.c
671
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
674
static void ibx_irq_handler(struct intel_display *display, u32 pch_iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
679
ibx_hpd_irq_handler(display, hotplug_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
684
drm_dbg(display->drm, "PCH audio power change on port %d\n",
drivers/gpu/drm/i915/display/intel_display_irq.c
689
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
692
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
695
drm_dbg(display->drm, "PCH HDCP audio interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
698
drm_dbg(display->drm, "PCH transcoder audio interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
70
assert_iir_is_zero(display, regs.iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
701
drm_err(display->drm, "PCH poison interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
704
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
705
drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",
drivers/gpu/drm/i915/display/intel_display_irq.c
707
intel_de_read(display, FDI_RX_IIR(pipe)));
drivers/gpu/drm/i915/display/intel_display_irq.c
711
drm_dbg(display->drm, "PCH transcoder CRC done interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
714
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_display_irq.c
718
intel_pch_fifo_underrun_irq_handler(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_display_irq.c
72
intel_de_write(display, regs.ier, ier_val);
drivers/gpu/drm/i915/display/intel_display_irq.c
721
intel_pch_fifo_underrun_irq_handler(display, PIPE_B);
drivers/gpu/drm/i915/display/intel_display_irq.c
73
intel_de_write(display, regs.imr, imr_val);
drivers/gpu/drm/i915/display/intel_display_irq.c
74
intel_de_posting_read(display, regs.imr);
drivers/gpu/drm/i915/display/intel_display_irq.c
757
static void ivb_err_int_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
759
u32 err_int = intel_de_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_display_irq.c
763
drm_err(display->drm, "Poison interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
766
drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
769
drm_err_ratelimited(display->drm, "Invalid PTE data\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
77
static void error_reset(struct intel_display *display, struct intel_error_regs regs)
drivers/gpu/drm/i915/display/intel_display_irq.c
771
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
775
intel_cpu_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
778
if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_display_irq.c
779
ivb_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
781
hsw_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
786
intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers,
drivers/gpu/drm/i915/display/intel_display_irq.c
79
intel_de_write(display, regs.emr, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
790
intel_de_write(display, GEN7_ERR_INT, err_int);
drivers/gpu/drm/i915/display/intel_display_irq.c
793
static void cpt_serr_int_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
795
u32 serr_int = intel_de_read(display, SERR_INT);
drivers/gpu/drm/i915/display/intel_display_irq.c
799
drm_err(display->drm, "PCH poison interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
80
intel_de_posting_read(display, regs.emr);
drivers/gpu/drm/i915/display/intel_display_irq.c
801
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
803
intel_pch_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
805
intel_de_write(display, SERR_INT, serr_int);
drivers/gpu/drm/i915/display/intel_display_irq.c
808
static void cpt_irq_handler(struct intel_display *display, u32 pch_iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
813
ibx_hpd_irq_handler(display, hotplug_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
818
drm_dbg(display->drm, "PCH audio power change on port %c\n",
drivers/gpu/drm/i915/display/intel_display_irq.c
82
intel_de_write(display, regs.eir, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
823
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
826
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
829
drm_dbg(display->drm, "Audio CP request interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
83
intel_de_posting_read(display, regs.eir);
drivers/gpu/drm/i915/display/intel_display_irq.c
832
drm_dbg(display->drm, "Audio CP change interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
835
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_irq.c
836
drm_dbg(display->drm, " pipe %c FDI IIR: 0x%08x\n",
drivers/gpu/drm/i915/display/intel_display_irq.c
838
intel_de_read(display, FDI_RX_IIR(pipe)));
drivers/gpu/drm/i915/display/intel_display_irq.c
84
intel_de_write(display, regs.eir, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
842
cpt_serr_int_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
85
intel_de_posting_read(display, regs.eir);
drivers/gpu/drm/i915/display/intel_display_irq.c
871
static void ilk_gtt_fault_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_irq.c
876
gtt_fault = intel_de_read(display, ILK_GTT_FAULT);
drivers/gpu/drm/i915/display/intel_display_irq.c
877
intel_de_write(display, ILK_GTT_FAULT, gtt_fault);
drivers/gpu/drm/i915/display/intel_display_irq.c
88
static void error_init(struct intel_display *display, struct intel_error_regs regs,
drivers/gpu/drm/i915/display/intel_display_irq.c
880
drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
883
drm_err_ratelimited(display->drm, "Invalid PTE data\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
885
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
890
intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers,
drivers/gpu/drm/i915/display/intel_display_irq.c
895
static void _ilk_display_irq_handler(struct intel_display *display, u32 de_iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
901
ilk_hpd_irq_handler(display, hotplug_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
904
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
907
intel_opregion_asle_intr(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
91
intel_de_write(display, regs.eir, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
910
drm_err(display->drm, "Poison interrupt\n");
drivers/gpu/drm/i915/display/intel_display_irq.c
913
ilk_gtt_fault_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
915
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
917
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
92
intel_de_posting_read(display, regs.eir);
drivers/gpu/drm/i915/display/intel_display_irq.c
920
flip_done_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
923
intel_cpu_fifo_underrun_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
926
i9xx_pipe_crc_irq_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
93
intel_de_write(display, regs.eir, 0xffffffff);
drivers/gpu/drm/i915/display/intel_display_irq.c
931
u32 pch_iir = intel_de_read(display, SDEIIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
933
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_display_irq.c
934
cpt_irq_handler(display, pch_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
936
ibx_irq_handler(display, pch_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
939
intel_de_write(display, SDEIIR, pch_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
94
intel_de_posting_read(display, regs.eir);
drivers/gpu/drm/i915/display/intel_display_irq.c
942
if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT)
drivers/gpu/drm/i915/display/intel_display_irq.c
943
ilk_display_rps_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
946
static void _ivb_display_irq_handler(struct intel_display *display, u32 de_iir)
drivers/gpu/drm/i915/display/intel_display_irq.c
952
ilk_hpd_irq_handler(display, hotplug_trigger);
drivers/gpu/drm/i915/display/intel_display_irq.c
955
ivb_err_int_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
96
intel_de_write(display, regs.emr, emr_val);
drivers/gpu/drm/i915/display/intel_display_irq.c
960
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_display_irq.c
964
psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0);
drivers/gpu/drm/i915/display/intel_display_irq.c
97
intel_de_posting_read(display, regs.emr);
drivers/gpu/drm/i915/display/intel_display_irq.c
971
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
974
intel_opregion_asle_intr(display);
drivers/gpu/drm/i915/display/intel_display_irq.c
976
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_irq.c
978
intel_handle_vblank(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
981
flip_done_handler(display, pipe);
drivers/gpu/drm/i915/display/intel_display_irq.c
985
if (!HAS_PCH_NOP(display) && (de_iir & DE_PCH_EVENT_IVB)) {
drivers/gpu/drm/i915/display/intel_display_irq.c
986
u32 pch_iir = intel_de_read(display, SDEIIR);
drivers/gpu/drm/i915/display/intel_display_irq.c
988
cpt_irq_handler(display, pch_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
991
intel_de_write(display, SDEIIR, pch_iir);
drivers/gpu/drm/i915/display/intel_display_irq.c
995
void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier)
drivers/gpu/drm/i915/display/intel_display_irq.c
998
*de_ier = intel_de_read_fw(display, DEIER);
drivers/gpu/drm/i915/display/intel_display_irq.c
999
intel_de_write_fw(display, DEIER, *de_ier & ~DE_MASTER_IRQ_CONTROL);
drivers/gpu/drm/i915/display/intel_display_irq.h
19
u32 xelpdp_pica_aux_mask(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
21
void valleyview_enable_display_irqs(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
22
void valleyview_disable_display_irqs(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
24
void ilk_update_display_irq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.h
26
void ilk_enable_display_irq(struct intel_display *display, u32 bits);
drivers/gpu/drm/i915/display/intel_display_irq.h
27
void ilk_disable_display_irq(struct intel_display *display, u32 bits);
drivers/gpu/drm/i915/display/intel_display_irq.h
29
void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);
drivers/gpu/drm/i915/display/intel_display_irq.h
30
void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);
drivers/gpu/drm/i915/display/intel_display_irq.h
31
void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);
drivers/gpu/drm/i915/display/intel_display_irq.h
33
void ibx_display_interrupt_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_irq.h
35
void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);
drivers/gpu/drm/i915/display/intel_display_irq.h
36
void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);
drivers/gpu/drm/i915/display/intel_display_irq.h
38
void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask);
drivers/gpu/drm/i915/display/intel_display_irq.h
39
void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask);
drivers/gpu/drm/i915/display/intel_display_irq.h
52
void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
drivers/gpu/drm/i915/display/intel_display_irq.h
53
void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
drivers/gpu/drm/i915/display/intel_display_irq.h
55
u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
drivers/gpu/drm/i915/display/intel_display_irq.h
56
void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
drivers/gpu/drm/i915/display/intel_display_irq.h
67
void intel_display_irq_reset(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
68
void intel_display_irq_postinstall(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
69
void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
drivers/gpu/drm/i915/display/intel_display_irq.h
70
bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
drivers/gpu/drm/i915/display/intel_display_irq.h
72
u32 i9xx_display_irq_enable_mask(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
74
u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_display_irq.h
75
void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
drivers/gpu/drm/i915/display/intel_display_irq.h
76
void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
drivers/gpu/drm/i915/display/intel_display_irq.h
78
void intel_display_irq_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_irq.h
80
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
drivers/gpu/drm/i915/display/intel_display_irq.h
82
struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.c
1015
drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);
drivers/gpu/drm/i915/display/intel_display_power.c
1027
int intel_display_power_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1029
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1031
display->params.disable_power_well =
drivers/gpu/drm/i915/display/intel_display_power.c
1032
sanitize_disable_power_well_option(display->params.disable_power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
1034
get_allowed_dc_mask(display, display->params.enable_dc);
drivers/gpu/drm/i915/display/intel_display_power.c
1037
sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
drivers/gpu/drm/i915/display/intel_display_power.c
1053
void intel_display_power_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1055
intel_display_power_map_cleanup(&display->power.domains);
drivers/gpu/drm/i915/display/intel_display_power.c
1058
static void intel_power_domains_sync_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1060
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1064
for_each_power_well(display, power_well)
drivers/gpu/drm/i915/display/intel_display_power.c
1065
intel_power_well_sync_hw(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
1069
static void gen9_dbuf_slice_set(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
1075
intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
drivers/gpu/drm/i915/display/intel_display_power.c
1077
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_display_power.c
1080
state = intel_de_read(display, reg) & DBUF_POWER_STATE;
drivers/gpu/drm/i915/display/intel_display_power.c
1081
drm_WARN(display->drm, enable != state,
drivers/gpu/drm/i915/display/intel_display_power.c
1086
void gen9_dbuf_slices_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
1089
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1090
u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;
drivers/gpu/drm/i915/display/intel_display_power.c
1093
drm_WARN(display->drm, req_slices & ~slice_mask,
drivers/gpu/drm/i915/display/intel_display_power.c
1097
drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n",
drivers/gpu/drm/i915/display/intel_display_power.c
1109
for_each_dbuf_slice(display, slice)
drivers/gpu/drm/i915/display/intel_display_power.c
1110
gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));
drivers/gpu/drm/i915/display/intel_display_power.c
1112
display->dbuf.enabled_slices = req_slices;
drivers/gpu/drm/i915/display/intel_display_power.c
1117
static void gen9_dbuf_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1121
display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1123
slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
drivers/gpu/drm/i915/display/intel_display_power.c
1125
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_power.c
1126
intel_pmdemand_program_dbuf(display, slices_mask);
drivers/gpu/drm/i915/display/intel_display_power.c
1132
gen9_dbuf_slices_update(display, slices_mask);
drivers/gpu/drm/i915/display/intel_display_power.c
1135
static void gen9_dbuf_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1137
gen9_dbuf_slices_update(display, 0);
drivers/gpu/drm/i915/display/intel_display_power.c
1139
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_power.c
1140
intel_pmdemand_program_dbuf(display, 0);
drivers/gpu/drm/i915/display/intel_display_power.c
1143
static void gen12_dbuf_slices_config(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1147
for_each_dbuf_slice(display, slice)
drivers/gpu/drm/i915/display/intel_display_power.c
1148
intel_de_rmw(display, DBUF_CTL_S(slice),
drivers/gpu/drm/i915/display/intel_display_power.c
1153
static void icl_mbus_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1155
unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;
drivers/gpu/drm/i915/display/intel_display_power.c
1158
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_power.c
1175
if (DISPLAY_VER(display) == 12)
drivers/gpu/drm/i915/display/intel_display_power.c
1179
intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1182
static void hsw_assert_cdclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1184
u32 val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1193
drm_err(display->drm, "CDCLK source is not LCPLL\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1196
drm_err(display->drm, "LCPLL is disabled\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1199
drm_err(display->drm, "LCPLL not using non-SSC reference\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1202
static void assert_can_disable_lcpll(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1206
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/intel_display_power.c
1207
INTEL_DISPLAY_STATE_WARN(display, crtc->active,
drivers/gpu/drm/i915/display/intel_display_power.c
1211
INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),
drivers/gpu/drm/i915/display/intel_display_power.c
1213
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1214
intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1216
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1217
intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1219
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1220
intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1222
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1223
intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
drivers/gpu/drm/i915/display/intel_display_power.c
1225
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1226
intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1228
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display_power.c
1229
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1230
intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1232
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1233
intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1235
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1236
(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
drivers/gpu/drm/i915/display/intel_display_power.c
1238
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1239
intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,
drivers/gpu/drm/i915/display/intel_display_power.c
1248
INTEL_DISPLAY_STATE_WARN(display, intel_parent_irq_enabled(display),
drivers/gpu/drm/i915/display/intel_display_power.c
1252
static u32 hsw_read_dcomp(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1254
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display_power.c
1255
return intel_mchbar_read(display, D_COMP_HSW);
drivers/gpu/drm/i915/display/intel_display_power.c
1257
return intel_de_read(display, D_COMP_BDW);
drivers/gpu/drm/i915/display/intel_display_power.c
1260
static void hsw_write_dcomp(struct intel_display *display, u32 val)
drivers/gpu/drm/i915/display/intel_display_power.c
1262
if (display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display_power.c
1263
if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val))
drivers/gpu/drm/i915/display/intel_display_power.c
1264
drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1266
intel_de_write(display, D_COMP_BDW, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1267
intel_de_posting_read(display, D_COMP_BDW);
drivers/gpu/drm/i915/display/intel_display_power.c
1279
static void hsw_disable_lcpll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
1285
assert_can_disable_lcpll(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1287
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1291
intel_de_write(display, LCPLL_CTL, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1293
ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_display_power.c
1296
drm_err(display->drm, "Switching to FCLK failed\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1298
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1302
intel_de_write(display, LCPLL_CTL, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1303
intel_de_posting_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1305
if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
drivers/gpu/drm/i915/display/intel_display_power.c
1306
drm_err(display->drm, "LCPLL still locked\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1308
val = hsw_read_dcomp(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1310
hsw_write_dcomp(display, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1313
ret = poll_timeout_us(val = hsw_read_dcomp(display),
drivers/gpu/drm/i915/display/intel_display_power.c
1317
drm_err(display->drm, "D_COMP RCOMP still in progress\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1320
intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
drivers/gpu/drm/i915/display/intel_display_power.c
1321
intel_de_posting_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1329
static void hsw_restore_lcpll(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1334
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1344
intel_parent_pc8_block(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1348
intel_de_write(display, LCPLL_CTL, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1349
intel_de_posting_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1352
val = hsw_read_dcomp(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1355
hsw_write_dcomp(display, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1357
val = intel_de_read(display, LCPLL_CTL);
drivers/gpu/drm/i915/display/intel_display_power.c
1359
intel_de_write(display, LCPLL_CTL, val);
drivers/gpu/drm/i915/display/intel_display_power.c
1361
if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
drivers/gpu/drm/i915/display/intel_display_power.c
1362
drm_err(display->drm, "LCPLL not locked yet\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1365
intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
drivers/gpu/drm/i915/display/intel_display_power.c
1367
ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
drivers/gpu/drm/i915/display/intel_display_power.c
1370
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
1374
intel_parent_pc8_unblock(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1376
intel_update_cdclk(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1377
intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
drivers/gpu/drm/i915/display/intel_display_power.c
1403
static void hsw_enable_pc8(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1405
drm_dbg_kms(display->drm, "Enabling package C8+\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1407
if (HAS_PCH_LPT_LP(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1408
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_display_power.c
1411
lpt_disable_clkout_dp(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1412
hsw_disable_lcpll(display, true, true);
drivers/gpu/drm/i915/display/intel_display_power.c
1415
static void hsw_disable_pc8(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1417
drm_dbg_kms(display->drm, "Disabling package C8+\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1419
hsw_restore_lcpll(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1420
intel_init_pch_refclk(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1423
intel_clock_gating_init(display->drm);
drivers/gpu/drm/i915/display/intel_display_power.c
1426
static void intel_pch_reset_handshake(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
1432
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_display_power.c
1435
if (display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_display_power.c
1443
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_power.c
1446
intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);
drivers/gpu/drm/i915/display/intel_display_power.c
1449
static void skl_display_core_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
1452
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1455
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power.c
1458
intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
drivers/gpu/drm/i915/display/intel_display_power.c
1460
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1466
well = lookup_power_well(display, SKL_DISP_PW_1);
drivers/gpu/drm/i915/display/intel_display_power.c
1467
intel_power_well_enable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1469
well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);
drivers/gpu/drm/i915/display/intel_display_power.c
1470
intel_power_well_enable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1474
intel_cdclk_init_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1476
gen9_dbuf_enable(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1479
intel_dmc_load_program(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1482
static void skl_display_core_uninit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1484
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1487
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1490
gen9_disable_dc_states(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1493
gen9_dbuf_disable(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1495
intel_cdclk_uninit_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1508
well = lookup_power_well(display, SKL_DISP_PW_1);
drivers/gpu/drm/i915/display/intel_display_power.c
1509
intel_power_well_disable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1516
static void bxt_display_core_init(struct intel_display *display, bool resume)
drivers/gpu/drm/i915/display/intel_display_power.c
1518
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1521
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power.c
1529
intel_pch_reset_handshake(display, false);
drivers/gpu/drm/i915/display/intel_display_power.c
1531
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1537
well = lookup_power_well(display, SKL_DISP_PW_1);
drivers/gpu/drm/i915/display/intel_display_power.c
1538
intel_power_well_enable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1542
intel_cdclk_init_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1544
gen9_dbuf_enable(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1547
intel_dmc_load_program(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1550
static void bxt_display_core_uninit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1552
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1555
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1558
gen9_disable_dc_states(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1561
gen9_dbuf_disable(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1563
intel_cdclk_uninit_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1574
well = lookup_power_well(display, SKL_DISP_PW_1);
drivers/gpu/drm/i915/display/intel_display_power.c
1575
intel_power_well_disable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1612
static void tgl_bw_buddy_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1614
const struct dram_info *dram_info = intel_dram_info(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1616
unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
drivers/gpu/drm/i915/display/intel_display_power.c
1620
if (display->platform.dgfx && !display->platform.dg1)
drivers/gpu/drm/i915/display/intel_display_power.c
1623
if (intel_display_wa(display, INTEL_DISPLAY_WA_1409767108))
drivers/gpu/drm/i915/display/intel_display_power.c
1635
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
1638
intel_de_write(display, BW_BUDDY_CTL(i),
drivers/gpu/drm/i915/display/intel_display_power.c
1642
intel_de_write(display, BW_BUDDY_PAGE_MASK(i),
drivers/gpu/drm/i915/display/intel_display_power.c
1646
if (intel_display_wa(display, INTEL_DISPLAY_WA_22010178259))
drivers/gpu/drm/i915/display/intel_display_power.c
1647
intel_de_rmw(display, BW_BUDDY_CTL(i),
drivers/gpu/drm/i915/display/intel_display_power.c
1654
static void icl_display_core_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
1657
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1660
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power.c
1663
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011294188))
drivers/gpu/drm/i915/display/intel_display_power.c
1664
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
drivers/gpu/drm/i915/display/intel_display_power.c
1668
intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
drivers/gpu/drm/i915/display/intel_display_power.c
1670
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1674
intel_combo_phy_init(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1681
well = lookup_power_well(display, SKL_DISP_PW_1);
drivers/gpu/drm/i915/display/intel_display_power.c
1682
intel_power_well_enable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1685
if (DISPLAY_VER(display) == 14)
drivers/gpu/drm/i915/display/intel_display_power.c
1686
intel_de_rmw(display, DC_STATE_EN,
drivers/gpu/drm/i915/display/intel_display_power.c
1690
intel_cdclk_init_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1692
if (DISPLAY_VER(display) == 12 || display->platform.dg2)
drivers/gpu/drm/i915/display/intel_display_power.c
1693
gen12_dbuf_slices_config(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1696
gen9_dbuf_enable(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1699
icl_mbus_init(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1702
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_power.c
1703
tgl_bw_buddy_init(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1706
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_display_power.c
1707
intel_snps_phy_wait_for_calibration(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1710
if (DISPLAY_VERx100(display) == 1401)
drivers/gpu/drm/i915/display/intel_display_power.c
1711
intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
drivers/gpu/drm/i915/display/intel_display_power.c
1714
intel_dmc_load_program(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1717
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011508470))
drivers/gpu/drm/i915/display/intel_display_power.c
1718
intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0,
drivers/gpu/drm/i915/display/intel_display_power.c
1723
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503030))
drivers/gpu/drm/i915/display/intel_display_power.c
1724
intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
drivers/gpu/drm/i915/display/intel_display_power.c
1727
if (intel_display_wa(display, INTEL_DISPLAY_WA_15013987218)) {
drivers/gpu/drm/i915/display/intel_display_power.c
1728
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_display_power.c
1730
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_display_power.c
1735
static void icl_display_core_uninit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1737
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1740
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
1743
gen9_disable_dc_states(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1744
intel_dmc_disable_program(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1749
gen9_dbuf_disable(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1752
intel_cdclk_uninit_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1754
if (DISPLAY_VER(display) == 14)
drivers/gpu/drm/i915/display/intel_display_power.c
1755
intel_de_rmw(display, DC_STATE_EN, 0,
drivers/gpu/drm/i915/display/intel_display_power.c
1764
well = lookup_power_well(display, SKL_DISP_PW_1);
drivers/gpu/drm/i915/display/intel_display_power.c
1765
intel_power_well_disable(display, well);
drivers/gpu/drm/i915/display/intel_display_power.c
1769
intel_combo_phy_uninit(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1772
static void chv_phy_control_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1775
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
drivers/gpu/drm/i915/display/intel_display_power.c
1777
lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
drivers/gpu/drm/i915/display/intel_display_power.c
1786
display->power.chv_phy_control =
drivers/gpu/drm/i915/display/intel_display_power.c
1800
if (intel_power_well_is_enabled(display, cmn_bc)) {
drivers/gpu/drm/i915/display/intel_display_power.c
1801
u32 status = intel_de_read(display, DPLL(display, PIPE_A));
drivers/gpu/drm/i915/display/intel_display_power.c
1808
display->power.chv_phy_control |=
drivers/gpu/drm/i915/display/intel_display_power.c
1811
display->power.chv_phy_control |=
drivers/gpu/drm/i915/display/intel_display_power.c
1818
display->power.chv_phy_control |=
drivers/gpu/drm/i915/display/intel_display_power.c
1821
display->power.chv_phy_control |=
drivers/gpu/drm/i915/display/intel_display_power.c
1824
display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
drivers/gpu/drm/i915/display/intel_display_power.c
1826
display->power.chv_phy_assert[DPIO_PHY0] = false;
drivers/gpu/drm/i915/display/intel_display_power.c
1828
display->power.chv_phy_assert[DPIO_PHY0] = true;
drivers/gpu/drm/i915/display/intel_display_power.c
1831
if (intel_power_well_is_enabled(display, cmn_d)) {
drivers/gpu/drm/i915/display/intel_display_power.c
1832
u32 status = intel_de_read(display, DPIO_PHY_STATUS);
drivers/gpu/drm/i915/display/intel_display_power.c
1840
display->power.chv_phy_control |=
drivers/gpu/drm/i915/display/intel_display_power.c
1843
display->power.chv_phy_control |=
drivers/gpu/drm/i915/display/intel_display_power.c
1846
display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
drivers/gpu/drm/i915/display/intel_display_power.c
1848
display->power.chv_phy_assert[DPIO_PHY1] = false;
drivers/gpu/drm/i915/display/intel_display_power.c
1850
display->power.chv_phy_assert[DPIO_PHY1] = true;
drivers/gpu/drm/i915/display/intel_display_power.c
1853
drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n",
drivers/gpu/drm/i915/display/intel_display_power.c
1854
display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power.c
1859
static void vlv_cmnlane_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1862
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
drivers/gpu/drm/i915/display/intel_display_power.c
1864
lookup_power_well(display, VLV_DISP_PW_DISP2D);
drivers/gpu/drm/i915/display/intel_display_power.c
1867
if (intel_power_well_is_enabled(display, cmn) &&
drivers/gpu/drm/i915/display/intel_display_power.c
1868
intel_power_well_is_enabled(display, disp2d) &&
drivers/gpu/drm/i915/display/intel_display_power.c
1869
intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)
drivers/gpu/drm/i915/display/intel_display_power.c
1872
drm_dbg_kms(display->drm, "toggling display PHY side reset\n");
drivers/gpu/drm/i915/display/intel_display_power.c
1875
intel_power_well_enable(display, disp2d);
drivers/gpu/drm/i915/display/intel_display_power.c
1884
intel_power_well_disable(display, cmn);
drivers/gpu/drm/i915/display/intel_display_power.c
1887
static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)
drivers/gpu/drm/i915/display/intel_display_power.c
1891
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1892
ret = (vlv_punit_read(display, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
drivers/gpu/drm/i915/display/intel_display_power.c
1893
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1898
static void assert_ved_power_gated(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1900
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
1901
!vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0),
drivers/gpu/drm/i915/display/intel_display_power.c
1905
static void assert_isp_power_gated(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1913
drm_WARN(display->drm, !pci_dev_present(isp_ids) &&
drivers/gpu/drm/i915/display/intel_display_power.c
1914
!vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0),
drivers/gpu/drm/i915/display/intel_display_power.c
1918
static void intel_power_domains_verify_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.c
1920
static void __intel_display_power_init_hw(struct intel_display *display, bool resume)
drivers/gpu/drm/i915/display/intel_display_power.c
1922
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
1926
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_power.c
1927
icl_display_core_init(display, resume);
drivers/gpu/drm/i915/display/intel_display_power.c
1928
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_power.c
1929
bxt_display_core_init(display, resume);
drivers/gpu/drm/i915/display/intel_display_power.c
1930
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_display_power.c
1931
skl_display_core_init(display, resume);
drivers/gpu/drm/i915/display/intel_display_power.c
1932
} else if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_display_power.c
1934
chv_phy_control_init(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1936
assert_isp_power_gated(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1937
} else if (display->platform.valleyview) {
drivers/gpu/drm/i915/display/intel_display_power.c
1939
vlv_cmnlane_wa(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1941
assert_ved_power_gated(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1942
assert_isp_power_gated(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1943
} else if (display->platform.broadwell || display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_display_power.c
1944
hsw_assert_cdclk(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1945
intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
drivers/gpu/drm/i915/display/intel_display_power.c
1946
} else if (display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_display_power.c
1947
intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
drivers/gpu/drm/i915/display/intel_display_power.c
1956
drm_WARN_ON(display->drm, power_domains->init_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
1958
intel_display_power_get(display, POWER_DOMAIN_INIT);
drivers/gpu/drm/i915/display/intel_display_power.c
1961
if (!display->params.disable_power_well) {
drivers/gpu/drm/i915/display/intel_display_power.c
1962
drm_WARN_ON(display->drm, power_domains->disable_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
1963
display->power.domains.disable_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_display_power.c
1966
intel_power_domains_sync_hw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
1986
void intel_display_power_init_hw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
1988
__intel_display_power_init_hw(display, false);
drivers/gpu/drm/i915/display/intel_display_power.c
2002
void intel_display_power_driver_remove(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2005
fetch_and_zero(&display->power.domains.init_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2008
if (!display->params.disable_power_well)
drivers/gpu/drm/i915/display/intel_display_power.c
2009
intel_display_power_put(display, POWER_DOMAIN_INIT,
drivers/gpu/drm/i915/display/intel_display_power.c
2010
fetch_and_zero(&display->power.domains.disable_wakeref));
drivers/gpu/drm/i915/display/intel_display_power.c
2012
intel_display_power_flush_work_sync(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2014
intel_power_domains_verify_state(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2017
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2030
void intel_display_power_sanitize_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2032
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2037
for_each_power_well_reverse(display, power_well) {
drivers/gpu/drm/i915/display/intel_display_power.c
2039
!intel_power_well_is_enabled(display, power_well))
drivers/gpu/drm/i915/display/intel_display_power.c
2042
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
2045
intel_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
2063
void intel_display_power_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2066
fetch_and_zero(&display->power.domains.init_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2068
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2069
intel_power_domains_verify_state(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2079
void intel_display_power_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
208
static bool __intel_display_power_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
2081
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2083
drm_WARN_ON(display->drm, power_domains->init_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2085
intel_display_power_get(display, POWER_DOMAIN_INIT);
drivers/gpu/drm/i915/display/intel_display_power.c
2087
intel_power_domains_verify_state(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2101
static void intel_power_domains_suspend(struct intel_display *display, bool s2idle)
drivers/gpu/drm/i915/display/intel_display_power.c
2103
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2107
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2117
intel_dmc_has_payload(display)) {
drivers/gpu/drm/i915/display/intel_display_power.c
2118
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2119
intel_power_domains_verify_state(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2127
if (!display->params.disable_power_well)
drivers/gpu/drm/i915/display/intel_display_power.c
2128
intel_display_power_put(display, POWER_DOMAIN_INIT,
drivers/gpu/drm/i915/display/intel_display_power.c
2129
fetch_and_zero(&display->power.domains.disable_wakeref));
drivers/gpu/drm/i915/display/intel_display_power.c
2131
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2132
intel_power_domains_verify_state(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2134
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display_power.c
2135
icl_display_core_uninit(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2136
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power.c
2137
bxt_display_core_uninit(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2138
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_display_power.c
2139
skl_display_core_uninit(display);
drivers/gpu/drm/i915/display/intel_display_power.c
214
if (intel_display_rpm_suspended(display))
drivers/gpu/drm/i915/display/intel_display_power.c
2154
static void intel_power_domains_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2156
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2159
__intel_display_power_init_hw(display, true);
drivers/gpu/drm/i915/display/intel_display_power.c
2162
drm_WARN_ON(display->drm, power_domains->init_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
2164
intel_display_power_get(display, POWER_DOMAIN_INIT);
drivers/gpu/drm/i915/display/intel_display_power.c
2170
static void intel_power_domains_dump_info(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2172
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2175
for_each_power_well(display, power_well) {
drivers/gpu/drm/i915/display/intel_display_power.c
2178
drm_dbg_kms(display->drm, "%-25s %d\n",
drivers/gpu/drm/i915/display/intel_display_power.c
2182
drm_dbg_kms(display->drm, " %-23s %d\n",
drivers/gpu/drm/i915/display/intel_display_power.c
219
for_each_power_domain_well_reverse(display, power_well, domain) {
drivers/gpu/drm/i915/display/intel_display_power.c
2198
static void intel_power_domains_verify_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2200
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2209
for_each_power_well(display, power_well) {
drivers/gpu/drm/i915/display/intel_display_power.c
2214
enabled = intel_power_well_is_enabled(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
2218
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
2228
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
2242
intel_power_domains_dump_info(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2252
static void intel_power_domains_verify_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2258
void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)
drivers/gpu/drm/i915/display/intel_display_power.c
2260
intel_power_domains_suspend(display, s2idle);
drivers/gpu/drm/i915/display/intel_display_power.c
2262
if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
drivers/gpu/drm/i915/display/intel_display_power.c
2263
display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_power.c
2264
bxt_enable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2265
} else if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_display_power.c
2266
hsw_enable_pc8(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2270
if (intel_display_wa(display, INTEL_DISPLAY_WA_14010685332))
drivers/gpu/drm/i915/display/intel_display_power.c
2271
intel_de_rmw(display, SOUTH_CHICKEN1,
drivers/gpu/drm/i915/display/intel_display_power.c
2275
void intel_display_power_resume_early(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2277
if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
drivers/gpu/drm/i915/display/intel_display_power.c
2278
display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_power.c
2279
gen9_sanitize_dc_state(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2280
bxt_disable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2281
} else if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_display_power.c
2282
hsw_disable_pc8(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2286
if (intel_display_wa(display, INTEL_DISPLAY_WA_14010685332))
drivers/gpu/drm/i915/display/intel_display_power.c
2287
intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
drivers/gpu/drm/i915/display/intel_display_power.c
2289
intel_power_domains_resume(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2292
void intel_display_power_runtime_suspend(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2294
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_power.c
2295
icl_display_core_uninit(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2296
bxt_enable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2297
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_power.c
2298
bxt_display_core_uninit(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2299
bxt_enable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2300
} else if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_display_power.c
2301
hsw_enable_pc8(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2305
void intel_display_power_runtime_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
2307
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2309
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_power.c
2310
bxt_disable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2311
icl_display_core_init(display, true);
drivers/gpu/drm/i915/display/intel_display_power.c
2312
if (intel_dmc_has_payload(display)) {
drivers/gpu/drm/i915/display/intel_display_power.c
2314
skl_enable_dc6(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2316
gen9_enable_dc5(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2318
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_display_power.c
2319
bxt_disable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2320
bxt_display_core_init(display, true);
drivers/gpu/drm/i915/display/intel_display_power.c
2321
if (intel_dmc_has_payload(display) &&
drivers/gpu/drm/i915/display/intel_display_power.c
2323
gen9_enable_dc5(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2324
} else if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_display_power.c
2325
hsw_disable_pc8(display);
drivers/gpu/drm/i915/display/intel_display_power.c
2329
void intel_display_power_debug(struct intel_display *display, struct seq_file *m)
drivers/gpu/drm/i915/display/intel_display_power.c
2331
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2479
intel_port_domains_for_platform(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
2483
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_display_power.c
2486
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_display_power.c
2489
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_display_power.c
249
bool intel_display_power_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
2499
intel_port_domains_for_port(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display_power.c
2505
intel_port_domains_for_platform(display, &domains, &domains_size);
drivers/gpu/drm/i915/display/intel_display_power.c
2514
intel_display_power_ddi_io_domain(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display_power.c
2516
const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
drivers/gpu/drm/i915/display/intel_display_power.c
2518
if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
drivers/gpu/drm/i915/display/intel_display_power.c
252
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
2525
intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_display_power.c
2527
const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
drivers/gpu/drm/i915/display/intel_display_power.c
2529
if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
drivers/gpu/drm/i915/display/intel_display_power.c
2536
intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch)
drivers/gpu/drm/i915/display/intel_display_power.c
2542
intel_port_domains_for_platform(display, &domains, &domains_size);
drivers/gpu/drm/i915/display/intel_display_power.c
2551
intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch)
drivers/gpu/drm/i915/display/intel_display_power.c
2553
const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
drivers/gpu/drm/i915/display/intel_display_power.c
2555
if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
drivers/gpu/drm/i915/display/intel_display_power.c
256
ret = __intel_display_power_is_enabled(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
2562
intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch)
drivers/gpu/drm/i915/display/intel_display_power.c
2564
const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
drivers/gpu/drm/i915/display/intel_display_power.c
2566
if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
drivers/gpu/drm/i915/display/intel_display_power.c
2573
intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch)
drivers/gpu/drm/i915/display/intel_display_power.c
2575
const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
drivers/gpu/drm/i915/display/intel_display_power.c
2577
if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
drivers/gpu/drm/i915/display/intel_display_power.c
263
sanitize_target_dc_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
266
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
297
void intel_display_power_set_target_dc_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
302
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
305
power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
drivers/gpu/drm/i915/display/intel_display_power.c
307
if (drm_WARN_ON(display->drm, !power_well))
drivers/gpu/drm/i915/display/intel_display_power.c
310
state = sanitize_target_dc_state(display, state);
drivers/gpu/drm/i915/display/intel_display_power.c
315
dc_off_enabled = intel_power_well_is_enabled(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
321
intel_power_well_enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
326
intel_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
340
u32 intel_display_power_get_current_dc_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
343
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
347
power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
drivers/gpu/drm/i915/display/intel_display_power.c
349
if (drm_WARN_ON(display->drm, !power_well))
drivers/gpu/drm/i915/display/intel_display_power.c
352
current_dc_state = intel_power_well_is_enabled(display, power_well) ?
drivers/gpu/drm/i915/display/intel_display_power.c
375
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power.c
379
return !drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
388
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power.c
397
err |= drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
402
err |= drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
411
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power.c
416
drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
drivers/gpu/drm/i915/display/intel_display_power.c
418
drm_dbg_kms(display->drm, "%s use_count %d\n",
drivers/gpu/drm/i915/display/intel_display_power.c
426
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power.c
430
drm_dbg_kms(display->drm, "async_put_wakeref: %s\n",
drivers/gpu/drm/i915/display/intel_display_power.c
491
intel_display_power_grab_async_put_ref(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
494
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
511
intel_display_rpm_put_raw(display,
drivers/gpu/drm/i915/display/intel_display_power.c
520
__intel_display_power_get_domain(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
523
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
526
if (intel_display_power_grab_async_put_ref(display, domain))
drivers/gpu/drm/i915/display/intel_display_power.c
529
for_each_power_domain_well(display, power_well, domain)
drivers/gpu/drm/i915/display/intel_display_power.c
530
intel_power_well_get(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
547
struct ref_tracker *intel_display_power_get(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
550
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
553
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_display_power.c
556
__intel_display_power_get_domain(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
575
intel_display_power_get_if_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
578
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
582
wakeref = intel_display_rpm_get_if_in_use(display);
drivers/gpu/drm/i915/display/intel_display_power.c
588
if (__intel_display_power_is_enabled(display, domain)) {
drivers/gpu/drm/i915/display/intel_display_power.c
589
__intel_display_power_get_domain(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
598
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
606
__intel_display_power_put_domain(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
609
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
614
drm_WARN(display->drm, !power_domains->domain_use_count[domain],
drivers/gpu/drm/i915/display/intel_display_power.c
618
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
625
for_each_power_domain_well_reverse(display, power_well, domain)
drivers/gpu/drm/i915/display/intel_display_power.c
626
intel_power_well_put(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power.c
629
static void __intel_display_power_put(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
632
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
635
__intel_display_power_put_domain(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
644
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power.c
647
drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
649
drm_WARN_ON(display->drm, !queue_delayed_work(system_dfl_wq,
drivers/gpu/drm/i915/display/intel_display_power.c
658
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power.c
664
wakeref = intel_display_rpm_get_noresume(display);
drivers/gpu/drm/i915/display/intel_display_power.c
669
__intel_display_power_put_domain(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
672
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
678
struct intel_display *display = container_of(work, struct intel_display,
drivers/gpu/drm/i915/display/intel_display_power.c
680
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
683
new_work_wakeref = intel_display_rpm_get_raw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
723
intel_display_rpm_put_raw(display, old_work_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
725
intel_display_rpm_put_raw(display, new_work_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
741
void __intel_display_power_put_async(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
746
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
749
work_wakeref = intel_display_rpm_get_raw(display);
drivers/gpu/drm/i915/display/intel_display_power.c
756
__intel_display_power_put_domain(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
761
drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1);
drivers/gpu/drm/i915/display/intel_display_power.c
781
intel_display_rpm_put_raw(display, work_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
783
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
798
void intel_display_power_flush_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
800
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
820
intel_display_rpm_put_raw(display, work_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
831
intel_display_power_flush_work_sync(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power.c
833
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power.c
835
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_display_power.c
840
drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
854
void intel_display_power_put(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
858
__intel_display_power_put(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
859
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_display_power.c
875
void intel_display_power_put_unchecked(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
878
__intel_display_power_put(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
879
intel_display_rpm_put_unchecked(display);
drivers/gpu/drm/i915/display/intel_display_power.c
884
intel_display_power_get_in_set(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
890
drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
drivers/gpu/drm/i915/display/intel_display_power.c
892
wf = intel_display_power_get(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
900
intel_display_power_get_in_set_if_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
906
drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
drivers/gpu/drm/i915/display/intel_display_power.c
908
wf = intel_display_power_get_if_enabled(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.c
921
intel_display_power_put_mask_in_set(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.c
927
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
936
intel_display_power_put(display, domain, wf);
drivers/gpu/drm/i915/display/intel_display_power.c
950
static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
drivers/gpu/drm/i915/display/intel_display_power.c
956
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power.c
959
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_display_power.c
961
else if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_display_power.c
963
else if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_display_power.c
965
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_power.c
967
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power.c
969
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_display_power.c
979
mask = display->platform.geminilake || display->platform.broxton ||
drivers/gpu/drm/i915/display/intel_display_power.c
980
DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0;
drivers/gpu/drm/i915/display/intel_display_power.c
982
if (!display->params.disable_power_well)
drivers/gpu/drm/i915/display/intel_display_power.c
990
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.c
995
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power.h
172
int intel_display_power_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
173
void intel_display_power_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
174
void intel_display_power_init_hw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
175
void intel_display_power_driver_remove(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
176
void intel_display_power_enable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
177
void intel_display_power_disable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
178
void intel_display_power_sanitize_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
180
void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
drivers/gpu/drm/i915/display/intel_display_power.h
181
void intel_display_power_resume_early(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
182
void intel_display_power_set_target_dc_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
184
u32 intel_display_power_get_current_dc_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
186
void intel_display_power_runtime_suspend(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
187
void intel_display_power_runtime_resume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
189
bool intel_display_power_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
191
struct ref_tracker *intel_display_power_get(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
194
intel_display_power_get_if_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
196
void __intel_display_power_put_async(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
200
void intel_display_power_flush_work(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power.h
202
void intel_display_power_put(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
206
intel_display_power_put_async(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
210
__intel_display_power_put_async(display, domain, wakeref, -1);
drivers/gpu/drm/i915/display/intel_display_power.h
214
intel_display_power_put_async_delay(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
219
__intel_display_power_put_async(display, domain, wakeref, delay_ms);
drivers/gpu/drm/i915/display/intel_display_power.h
222
void intel_display_power_put_unchecked(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
226
intel_display_power_put(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
230
intel_display_power_put_unchecked(display, domain);
drivers/gpu/drm/i915/display/intel_display_power.h
234
intel_display_power_put_async(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
238
__intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1);
drivers/gpu/drm/i915/display/intel_display_power.h
242
intel_display_power_put_async_delay(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
247
__intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms);
drivers/gpu/drm/i915/display/intel_display_power.h
252
intel_display_power_get_in_set(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
257
intel_display_power_get_in_set_if_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
262
intel_display_power_put_mask_in_set(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
267
intel_display_power_put_all_in_set(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
270
intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask);
drivers/gpu/drm/i915/display/intel_display_power.h
273
void intel_display_power_debug(struct intel_display *display, struct seq_file *m);
drivers/gpu/drm/i915/display/intel_display_power.h
276
intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_display_power.h
278
intel_display_power_ddi_io_domain(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_display_power.h
280
intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch);
drivers/gpu/drm/i915/display/intel_display_power.h
282
intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch);
drivers/gpu/drm/i915/display/intel_display_power.h
284
intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch);
drivers/gpu/drm/i915/display/intel_display_power.h
298
void gen9_dbuf_slices_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power.h
301
#define __with_intel_display_power(display, domain, wf) \
drivers/gpu/drm/i915/display/intel_display_power.h
302
for (struct ref_tracker *(wf) = intel_display_power_get((display), (domain)); (wf); \
drivers/gpu/drm/i915/display/intel_display_power.h
303
intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL)
drivers/gpu/drm/i915/display/intel_display_power.h
305
#define with_intel_display_power(display, domain) \
drivers/gpu/drm/i915/display/intel_display_power.h
306
__with_intel_display_power(display, domain, __UNIQUE_ID(wakeref))
drivers/gpu/drm/i915/display/intel_display_power.h
308
#define __with_intel_display_power_if_enabled(display, domain, wf) \
drivers/gpu/drm/i915/display/intel_display_power.h
309
for (struct ref_tracker *(wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \
drivers/gpu/drm/i915/display/intel_display_power.h
310
intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL)
drivers/gpu/drm/i915/display/intel_display_power.h
312
#define with_intel_display_power_if_enabled(display, domain) \
drivers/gpu/drm/i915/display/intel_display_power.h
313
__with_intel_display_power_if_enabled(display, domain, __UNIQUE_ID(wakeref))
drivers/gpu/drm/i915/display/intel_display_power_map.c
1798
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power_map.c
1823
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_map.c
1834
drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8);
drivers/gpu/drm/i915/display/intel_display_power_map.c
1835
drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id));
drivers/gpu/drm/i915/display/intel_display_power_map.c
1856
struct intel_display *display = container_of(power_domains,
drivers/gpu/drm/i915/display/intel_display_power_map.c
1863
if (!HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_display_power_map.c
1868
if (DISPLAY_VERx100(display) == 3002)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1870
else if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1872
else if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1874
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1876
else if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1878
else if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1880
else if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1882
else if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1884
else if (display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1886
else if (DISPLAY_VER(display) == 12)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1888
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1890
else if (display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1892
else if (display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1894
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1896
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1898
else if (display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1900
else if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1902
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1904
else if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1000
static void bxt_dpio_cmn_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1003
bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1006
static void bxt_dpio_cmn_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1009
bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1012
static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1015
return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1018
static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1022
power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1024
bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1026
power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1028
bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1030
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
1031
power_well = lookup_power_well(display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1034
bxt_dpio_phy_verify_state(display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1039
static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1042
return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
1043
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1046
static void gen9_assert_dbuf_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1048
u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1049
u8 enabled_dbuf_slices = display->dbuf.enabled_slices;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1051
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1058
void gen9_disable_dc_states(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1060
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1065
tgl_disable_dc3co(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1069
if (HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
1070
intel_dmc_wl_get_noreg(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1071
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1072
intel_dmc_wl_put_noreg(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1074
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1080
intel_dmc_wl_disable(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1082
intel_cdclk_get_cdclk(display, &cdclk_config);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1084
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1085
intel_cdclk_clock_changed(&display->cdclk.hw,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1088
gen9_assert_dbuf_enabled(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
109
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1090
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1091
bxt_verify_dpio_phy_power_wells(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1093
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1099
intel_combo_phy_init(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1102
static void gen9_dc_off_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1105
gen9_disable_dc_states(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1108
static void gen9_dc_off_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1111
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1113
if (!intel_dmc_has_payload(display))
drivers/gpu/drm/i915/display/intel_display_power_well.c
1118
tgl_enable_dc3co(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
112
return &display->power.domains.power_wells[0];
drivers/gpu/drm/i915/display/intel_display_power_well.c
1121
skl_enable_dc6(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1124
gen9_enable_dc5(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1129
static void i9xx_power_well_sync_hw_noop(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1134
static void i9xx_always_on_power_well_noop(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1139
static bool i9xx_always_on_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1145
static void i830_pipes_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1148
if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1149
i830_enable_pipe(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_display_power_well.c
115
void intel_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1150
if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1151
i830_enable_pipe(display, PIPE_B);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1154
static void i830_pipes_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1157
i830_disable_pipe(display, PIPE_B);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1158
i830_disable_pipe(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1161
static bool i830_pipes_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1164
return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
1165
intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1168
static void i830_pipes_power_well_sync_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1172
i830_pipes_power_well_enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1174
i830_pipes_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1177
static void vlv_set_power_well(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
118
drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well));
drivers/gpu/drm/i915/display/intel_display_power_well.c
119
power_well->desc->ops->enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1191
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1193
val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1197
ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1200
vlv_punit_write(display, PUNIT_REG_PWRGT_CTRL, ctrl);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1202
ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS),
drivers/gpu/drm/i915/display/intel_display_power_well.c
1206
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1209
vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL));
drivers/gpu/drm/i915/display/intel_display_power_well.c
1212
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1215
static void vlv_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1218
vlv_set_power_well(display, power_well, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1221
static void vlv_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1224
vlv_set_power_well(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1227
static bool vlv_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
123
void intel_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1239
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1241
state = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS) & mask;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1246
drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
1255
ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL) & mask;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1256
drm_WARN_ON(display->drm, ctrl != state);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1258
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
126
drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well));
drivers/gpu/drm/i915/display/intel_display_power_well.c
1263
static void vlv_init_display_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1271
intel_de_rmw(display, VLV_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1277
intel_de_write(display, MI_ARB_VLV,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1279
intel_de_write(display, CBR1_VLV, 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
128
power_well->desc->ops->disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1281
drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1282
intel_de_write(display, RAWCLK_FREQ_VLV,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1283
DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1287
static void vlv_display_power_well_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1300
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
1301
u32 val = intel_de_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_display_power_well.c
1307
intel_de_write(display, DPLL(display, pipe), val);
drivers/gpu/drm/i915/display/intel_display_power_well.c
131
void intel_power_well_sync_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1310
vlv_init_display_clock_gating(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1312
valleyview_enable_display_irqs(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1318
if (display->power.domains.initializing)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1321
intel_hpd_init(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1322
intel_hpd_poll_disable(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1325
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
1330
intel_vga_disable(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1332
intel_pps_unlock_regs_wa(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1335
static void vlv_display_power_well_deinit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1337
valleyview_disable_display_irqs(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
134
power_well->desc->ops->sync_hw(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1340
intel_parent_irq_synchronize(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1342
vlv_pps_reset_all(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1345
if (!display->drm->dev->power.is_suspended)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1346
intel_hpd_poll_enable(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1349
static void vlv_display_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
135
power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1352
vlv_set_power_well(display, power_well, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1354
vlv_display_power_well_init(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1357
static void vlv_display_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1360
vlv_display_power_well_deinit(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1362
vlv_set_power_well(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1365
static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1371
vlv_set_power_well(display, power_well, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
138
void intel_power_well_get(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1384
intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1387
static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1392
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1393
assert_pll_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1396
intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1398
vlv_set_power_well(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1403
static void assert_chv_phy_status(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1406
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1408
lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1409
u32 phy_control = display->power.chv_phy_control;
drivers/gpu/drm/i915/display/intel_display_power_well.c
142
intel_power_well_enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1421
if (!display->power.chv_phy_assert[DPIO_PHY0])
drivers/gpu/drm/i915/display/intel_display_power_well.c
1429
if (!display->power.chv_phy_assert[DPIO_PHY1])
drivers/gpu/drm/i915/display/intel_display_power_well.c
1434
if (intel_power_well_is_enabled(display, cmn_bc)) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
145
void intel_power_well_put(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1457
(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1475
if (intel_power_well_is_enabled(display, cmn_d)) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
148
drm_WARN(display->drm, !power_well->count,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1500
if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1502
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1504
val & phy_status_mask, phy_status, display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1509
static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1516
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1527
vlv_set_power_well(display, power_well, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
153
intel_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1530
if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1532
drm_err(display->drm, "Display PHY %d is not power up\n",
drivers/gpu/drm/i915/display/intel_display_power_well.c
1535
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1538
tmp = vlv_dpio_read(display, phy, CHV_CMN_DW28);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1541
vlv_dpio_write(display, phy, CHV_CMN_DW28, tmp);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1544
tmp = vlv_dpio_read(display, phy, CHV_CMN_DW6_CH1);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1546
vlv_dpio_write(display, phy, CHV_CMN_DW6_CH1, tmp);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1553
tmp = vlv_dpio_read(display, phy, CHV_CMN_DW30);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1555
vlv_dpio_write(display, phy, CHV_CMN_DW30, tmp);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1558
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
156
bool intel_power_well_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1560
display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1561
intel_de_write(display, DISPLAY_PHY_CONTROL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1562
display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1564
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1566
phy, display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1568
assert_chv_phy_status(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1571
static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1577
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1583
assert_pll_disabled(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1584
assert_pll_disabled(display, PIPE_B);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1587
assert_pll_disabled(display, PIPE_C);
drivers/gpu/drm/i915/display/intel_display_power_well.c
159
return power_well->desc->ops->is_enabled(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1590
display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1591
intel_de_write(display, DISPLAY_PHY_CONTROL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1592
display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1594
vlv_set_power_well(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1596
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1598
phy, display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1601
display->power.chv_phy_assert[phy] = true;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1603
assert_chv_phy_status(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1606
static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1618
if (!display->power.chv_phy_assert[phy])
drivers/gpu/drm/i915/display/intel_display_power_well.c
1626
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1627
val = vlv_dpio_read(display, phy, reg);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1628
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1661
drm_WARN(display->drm, actual != expected,
drivers/gpu/drm/i915/display/intel_display_power_well.c
167
bool intel_display_power_well_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1670
bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1673
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1678
was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1684
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1686
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1688
intel_de_write(display, DISPLAY_PHY_CONTROL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1689
display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1691
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1693
phy, ch, display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1695
assert_chv_phy_status(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1706
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1707
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power_well.c
1713
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1714
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1717
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1719
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
172
power_well = lookup_power_well(display, power_well_id);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1721
intel_de_write(display, DISPLAY_PHY_CONTROL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1722
display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1724
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1726
phy, ch, mask, display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1728
assert_chv_phy_status(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1730
assert_chv_phy_powergate(display, phy, ch, override, mask);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1735
static bool chv_pipe_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
174
return intel_power_well_is_enabled(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1742
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1744
state = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1749
drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
1757
ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1758
drm_WARN_ON(display->drm, ctrl << 16 != state);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1760
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1765
static void chv_set_pipe_power_well(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1776
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1778
ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1784
vlv_punit_write(display, PUNIT_REG_DSPSSPM, ctrl);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1786
ret = poll_timeout_us(ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM),
drivers/gpu/drm/i915/display/intel_display_power_well.c
1790
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1793
vlv_punit_read(display, PUNIT_REG_DSPSSPM));
drivers/gpu/drm/i915/display/intel_display_power_well.c
1798
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1801
static void chv_pipe_power_well_sync_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1804
intel_de_write(display, DISPLAY_PHY_CONTROL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1805
display->power.chv_phy_control);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1808
static void chv_pipe_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1811
chv_set_pipe_power_well(display, power_well, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1813
vlv_display_power_well_init(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1816
static void chv_pipe_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1819
vlv_display_power_well_deinit(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1821
chv_set_pipe_power_well(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1825
tgl_tc_cold_request(struct intel_display *display, bool block)
drivers/gpu/drm/i915/display/intel_display_power_well.c
1843
ret = intel_parent_pcode_read(display, TGL_PCODE_TCCOLD, &low_val, &high_val);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1859
drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un");
drivers/gpu/drm/i915/display/intel_display_power_well.c
1861
drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n",
drivers/gpu/drm/i915/display/intel_display_power_well.c
1866
tgl_tc_cold_off_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1869
tgl_tc_cold_request(display, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1873
tgl_tc_cold_off_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1876
tgl_tc_cold_request(display, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1880
tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1884
tgl_tc_cold_off_power_well_enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1886
tgl_tc_cold_off_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1890
tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1900
static void xelpdp_aux_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1904
enum phy phy = icl_aux_pw_to_phy(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1906
if (icl_aux_pw_is_tc_phy(display, power_well))
drivers/gpu/drm/i915/display/intel_display_power_well.c
1907
icl_tc_port_assert_ref_held(display, power_well,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1908
aux_ch_to_digital_port(display, aux_ch));
drivers/gpu/drm/i915/display/intel_display_power_well.c
1910
intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
drivers/gpu/drm/i915/display/intel_display_power_well.c
1914
if (HAS_LT_PHY(display)) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
1915
if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
drivers/gpu/drm/i915/display/intel_display_power_well.c
1917
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1931
static void xelpdp_aux_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1935
enum phy phy = icl_aux_pw_to_phy(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1937
intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
drivers/gpu/drm/i915/display/intel_display_power_well.c
1941
if (HAS_LT_PHY(display)) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
1942
if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
drivers/gpu/drm/i915/display/intel_display_power_well.c
1944
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1952
static bool xelpdp_aux_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1957
return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
1961
static void xe2lpd_pica_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1964
intel_de_write(display, XE2LPD_PICA_PW_CTL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1967
if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1969
drm_dbg_kms(display->drm, "pica power well enable timeout\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
1971
drm_WARN(display->drm, 1, "Power well PICA timeout when enabled");
drivers/gpu/drm/i915/display/intel_display_power_well.c
1975
static void xe2lpd_pica_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1978
intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
1980
if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1982
drm_dbg_kms(display->drm, "pica power well disable timeout\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
1984
drm_WARN(display->drm, 1, "Power well PICA timeout when disabled");
drivers/gpu/drm/i915/display/intel_display_power_well.c
1988
static bool xe2lpd_pica_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
1991
return intel_de_read(display, XE2LPD_PICA_PW_CTL) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
213
static void dss_pipe_gating_enable_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
231
intel_de_rmw(display, CLKGATE_DIS_DSSDSC, clear, set);
drivers/gpu/drm/i915/display/intel_display_power_well.c
233
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
236
intel_de_read(display, CLKGATE_DIS_DSSDSC));
drivers/gpu/drm/i915/display/intel_display_power_well.c
245
static void hsw_power_well_post_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
249
gen8_irq_power_well_post_enable(display, irq_pipe_mask);
drivers/gpu/drm/i915/display/intel_display_power_well.c
251
if (intel_display_wa(display, INTEL_DISPLAY_WA_22021048059))
drivers/gpu/drm/i915/display/intel_display_power_well.c
252
dss_pipe_gating_enable_disable(display, irq_pipe_mask, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
256
static void hsw_power_well_pre_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
260
if (intel_display_wa(display, INTEL_DISPLAY_WA_22021048059))
drivers/gpu/drm/i915/display/intel_display_power_well.c
261
dss_pipe_gating_enable_disable(display, irq_pipe_mask, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
263
gen8_irq_power_well_pre_disable(display, irq_pipe_mask);
drivers/gpu/drm/i915/display/intel_display_power_well.c
285
aux_ch_to_digital_port(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
290
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
307
icl_aux_pw_to_encoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
311
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
323
static enum phy icl_aux_pw_to_phy(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
326
struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
331
static bool icl_aux_pw_is_tc_phy(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
334
struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
339
static void hsw_wait_for_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
352
if (display->platform.dg2 && power_well->desc->fixed_enable_delay) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
358
if (intel_de_wait_for_set_ms(display, regs->driver,
drivers/gpu/drm/i915/display/intel_display_power_well.c
360
drm_dbg_kms(display->drm, "%s power well enable timeout\n",
drivers/gpu/drm/i915/display/intel_display_power_well.c
363
drm_WARN_ON(display->drm, !timeout_expected);
drivers/gpu/drm/i915/display/intel_display_power_well.c
368
static u32 hsw_power_well_requesters(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
375
ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
376
ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
378
ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
379
ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;
drivers/gpu/drm/i915/display/intel_display_power_well.c
384
static void hsw_wait_for_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
401
reqs = hsw_power_well_requesters(display, regs, pw_idx);
drivers/gpu/drm/i915/display/intel_display_power_well.c
403
ret = intel_de_wait_for_clear_ms(display, regs->driver,
drivers/gpu/drm/i915/display/intel_display_power_well.c
411
reqs = hsw_power_well_requesters(display, regs, pw_idx);
drivers/gpu/drm/i915/display/intel_display_power_well.c
413
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
419
static void gen9_wait_for_power_well_fuses(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
423
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
424
intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS,
drivers/gpu/drm/i915/display/intel_display_power_well.c
428
static void hsw_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
437
pg = pw_idx_to_pg(display, pw_idx);
drivers/gpu/drm/i915/display/intel_display_power_well.c
44
static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx)
drivers/gpu/drm/i915/display/intel_display_power_well.c
440
if (display->platform.alderlake_p && pg == SKL_PG1)
drivers/gpu/drm/i915/display/intel_display_power_well.c
441
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
drivers/gpu/drm/i915/display/intel_display_power_well.c
451
gen9_wait_for_power_well_fuses(display, SKL_PG0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
454
intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
drivers/gpu/drm/i915/display/intel_display_power_well.c
456
hsw_wait_for_power_well_enable(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
46
int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1;
drivers/gpu/drm/i915/display/intel_display_power_well.c
461
pg = pw_idx_to_pg(display, pw_idx);
drivers/gpu/drm/i915/display/intel_display_power_well.c
463
gen9_wait_for_power_well_fuses(display, pg);
drivers/gpu/drm/i915/display/intel_display_power_well.c
466
hsw_power_well_post_enable(display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
470
static void hsw_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
476
hsw_power_well_pre_disable(display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
479
intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
480
hsw_wait_for_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
483
static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch)
drivers/gpu/drm/i915/display/intel_display_power_well.c
485
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
491
icl_combo_phy_aux_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
497
drm_WARN_ON(display->drm, !display->platform.icelake);
drivers/gpu/drm/i915/display/intel_display_power_well.c
499
intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
drivers/gpu/drm/i915/display/intel_display_power_well.c
505
intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
drivers/gpu/drm/i915/display/intel_display_power_well.c
508
hsw_wait_for_power_well_enable(display, power_well, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
512
!intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx)))
drivers/gpu/drm/i915/display/intel_display_power_well.c
513
intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),
drivers/gpu/drm/i915/display/intel_display_power_well.c
518
icl_combo_phy_aux_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
524
drm_WARN_ON(display->drm, !display->platform.icelake);
drivers/gpu/drm/i915/display/intel_display_power_well.c
530
intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
drivers/gpu/drm/i915/display/intel_display_power_well.c
533
intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
535
hsw_wait_for_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
540
static void icl_tc_port_assert_ref_held(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
544
if (drm_WARN_ON(display->drm, !dig_port))
drivers/gpu/drm/i915/display/intel_display_power_well.c
547
if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
drivers/gpu/drm/i915/display/intel_display_power_well.c
550
drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));
drivers/gpu/drm/i915/display/intel_display_power_well.c
555
static void icl_tc_port_assert_ref_held(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
565
static void icl_tc_cold_exit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
570
ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
581
drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" :
drivers/gpu/drm/i915/display/intel_display_power_well.c
586
icl_tc_phy_aux_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
590
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
drivers/gpu/drm/i915/display/intel_display_power_well.c
597
icl_tc_port_assert_ref_held(display, power_well, dig_port);
drivers/gpu/drm/i915/display/intel_display_power_well.c
599
intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),
drivers/gpu/drm/i915/display/intel_display_power_well.c
602
intel_de_rmw(display, regs->driver,
drivers/gpu/drm/i915/display/intel_display_power_well.c
612
if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
drivers/gpu/drm/i915/display/intel_display_power_well.c
613
icl_tc_cold_exit(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
615
hsw_wait_for_power_well_enable(display, power_well, timeout_expected);
drivers/gpu/drm/i915/display/intel_display_power_well.c
617
if (DISPLAY_VER(display) >= 12 && !is_tbt) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
622
ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),
drivers/gpu/drm/i915/display/intel_display_power_well.c
626
drm_warn(display->drm, "Timeout waiting TC uC health\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
631
icl_aux_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
634
if (icl_aux_pw_is_tc_phy(display, power_well))
drivers/gpu/drm/i915/display/intel_display_power_well.c
635
return icl_tc_phy_aux_power_well_enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
636
else if (display->platform.icelake)
drivers/gpu/drm/i915/display/intel_display_power_well.c
637
return icl_combo_phy_aux_power_well_enable(display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
640
return hsw_power_well_enable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
644
icl_aux_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
647
if (icl_aux_pw_is_tc_phy(display, power_well))
drivers/gpu/drm/i915/display/intel_display_power_well.c
648
return hsw_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
649
else if (display->platform.icelake)
drivers/gpu/drm/i915/display/intel_display_power_well.c
650
return icl_combo_phy_aux_power_well_disable(display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
653
return hsw_power_well_disable(display, power_well);
drivers/gpu/drm/i915/display/intel_display_power_well.c
66
void (*sync_hw)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
661
static bool hsw_power_well_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
671
val = intel_de_read(display, regs->driver);
drivers/gpu/drm/i915/display/intel_display_power_well.c
679
if (DISPLAY_VER(display) == 9 && !display->platform.broxton &&
drivers/gpu/drm/i915/display/intel_display_power_well.c
681
val |= intel_de_read(display, regs->bios);
drivers/gpu/drm/i915/display/intel_display_power_well.c
686
static void assert_can_enable_dc9(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
688
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
689
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),
drivers/gpu/drm/i915/display/intel_display_power_well.c
691
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
692
intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
695
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
696
intel_de_read(display, HSW_PWR_WELL_CTL2) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
699
drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display),
drivers/gpu/drm/i915/display/intel_display_power_well.c
711
static void assert_can_disable_dc9(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
713
drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display),
drivers/gpu/drm/i915/display/intel_display_power_well.c
715
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
716
intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
729
static void gen9_write_dc_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
73
void (*enable)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
736
intel_de_write(display, DC_STATE_EN, state);
drivers/gpu/drm/i915/display/intel_display_power_well.c
744
v = intel_de_read(display, DC_STATE_EN);
drivers/gpu/drm/i915/display/intel_display_power_well.c
747
intel_de_write(display, DC_STATE_EN, state);
drivers/gpu/drm/i915/display/intel_display_power_well.c
757
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
763
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
768
static u32 gen9_dc_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
774
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_display_power_well.c
777
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display_power_well.c
779
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power_well.c
787
void gen9_sanitize_dc_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
789
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power_well.c
79
void (*disable)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
792
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power_well.c
795
val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
797
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
82
bool (*is_enabled)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
826
void gen9_set_dc_state(struct intel_display *display, u32 state)
drivers/gpu/drm/i915/display/intel_display_power_well.c
828
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_display_power_well.c
833
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_display_power_well.c
836
if (drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
841
intel_psr_notify_dc5_dc6(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
843
val = intel_de_read(display, DC_STATE_EN);
drivers/gpu/drm/i915/display/intel_display_power_well.c
844
mask = gen9_dc_mask(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
845
drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n",
drivers/gpu/drm/i915/display/intel_display_power_well.c
850
drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
drivers/gpu/drm/i915/display/intel_display_power_well.c
856
intel_dmc_update_dc6_allowed_count(display, true);
drivers/gpu/drm/i915/display/intel_display_power_well.c
861
gen9_write_dc_state(display, val);
drivers/gpu/drm/i915/display/intel_display_power_well.c
864
intel_dmc_update_dc6_allowed_count(display, false);
drivers/gpu/drm/i915/display/intel_display_power_well.c
869
static void tgl_enable_dc3co(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
871
drm_dbg_kms(display->drm, "Enabling DC3CO\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
872
gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
drivers/gpu/drm/i915/display/intel_display_power_well.c
875
static void tgl_disable_dc3co(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
877
drm_dbg_kms(display->drm, "Disabling DC3CO\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
878
intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
drivers/gpu/drm/i915/display/intel_display_power_well.c
879
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power_well.c
886
static void assert_can_enable_dc5(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
891
if (DISPLAY_VER(display) == 12)
drivers/gpu/drm/i915/display/intel_display_power_well.c
896
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
897
intel_display_power_well_is_enabled(display, high_pg),
drivers/gpu/drm/i915/display/intel_display_power_well.c
900
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
901
(intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
905
assert_display_rpm_held(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
907
assert_main_dmc_loaded(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
910
void gen9_enable_dc5(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
912
assert_can_enable_dc5(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
914
drm_dbg_kms(display->drm, "Enabling DC5\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
917
if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power_well.c
918
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
drivers/gpu/drm/i915/display/intel_display_power_well.c
921
intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5);
drivers/gpu/drm/i915/display/intel_display_power_well.c
923
gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5);
drivers/gpu/drm/i915/display/intel_display_power_well.c
926
static void assert_can_enable_dc6(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
928
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
929
(intel_de_read(display, UTIL_PIN_CTL) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
93
lookup_power_well(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
933
drm_WARN_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_display_power_well.c
934
(intel_de_read(display, DC_STATE_EN) &
drivers/gpu/drm/i915/display/intel_display_power_well.c
938
assert_main_dmc_loaded(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
941
void skl_enable_dc6(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
943
assert_can_enable_dc6(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
945
drm_dbg_kms(display->drm, "Enabling DC6\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
948
if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
drivers/gpu/drm/i915/display/intel_display_power_well.c
949
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
drivers/gpu/drm/i915/display/intel_display_power_well.c
952
intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
drivers/gpu/drm/i915/display/intel_display_power_well.c
954
gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
drivers/gpu/drm/i915/display/intel_display_power_well.c
957
void bxt_enable_dc9(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
959
assert_can_enable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
961
drm_dbg_kms(display->drm, "Enabling DC9\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
966
if (display->platform.broxton || display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_display_power_well.c
967
bxt_pps_reset_all(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
968
gen9_set_dc_state(display, DC_STATE_EN_DC9);
drivers/gpu/drm/i915/display/intel_display_power_well.c
971
void bxt_disable_dc9(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_power_well.c
973
assert_can_disable_dc9(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
975
drm_dbg_kms(display->drm, "Disabling DC9\n");
drivers/gpu/drm/i915/display/intel_display_power_well.c
977
gen9_set_dc_state(display, DC_STATE_DISABLE);
drivers/gpu/drm/i915/display/intel_display_power_well.c
979
intel_pps_unlock_regs_wa(display);
drivers/gpu/drm/i915/display/intel_display_power_well.c
98
for_each_power_well(display, power_well)
drivers/gpu/drm/i915/display/intel_display_power_well.c
982
static void hsw_power_well_sync_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.c
988
u32 bios_req = intel_de_read(display, regs->bios);
drivers/gpu/drm/i915/display/intel_display_power_well.c
992
u32 drv_req = intel_de_read(display, regs->driver);
drivers/gpu/drm/i915/display/intel_display_power_well.c
995
intel_de_write(display, regs->driver, drv_req | mask);
drivers/gpu/drm/i915/display/intel_display_power_well.c
996
intel_de_write(display, regs->bios, bios_req & ~mask);
drivers/gpu/drm/i915/display/intel_display_power_well.h
127
struct i915_power_well *lookup_power_well(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
130
void intel_power_well_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
132
void intel_power_well_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
134
void intel_power_well_sync_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
136
void intel_power_well_get(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
138
void intel_power_well_put(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
140
bool intel_power_well_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
143
bool intel_display_power_well_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_power_well.h
152
bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
drivers/gpu/drm/i915/display/intel_display_power_well.h
155
void gen9_enable_dc5(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power_well.h
156
void skl_enable_dc6(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power_well.h
157
void gen9_sanitize_dc_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power_well.h
158
void gen9_set_dc_state(struct intel_display *display, u32 state);
drivers/gpu/drm/i915/display/intel_display_power_well.h
159
void gen9_disable_dc_states(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power_well.h
160
void bxt_enable_dc9(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_power_well.h
161
void bxt_disable_dc9(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
73
#define _MMIO_PIPE2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_PIPE_OFFSET((display), (pipe)) + (reg))
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
74
#define _MMIO_TRANS2(display, trans, reg) _MMIO(INTEL_DISPLAY_DEVICE_TRANS_OFFSET((display), (trans)) + (reg))
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
75
#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_CURSOR_OFFSET((display), (pipe)) + (reg))
drivers/gpu/drm/i915/display/intel_display_regs.h
1694
#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
drivers/gpu/drm/i915/display/intel_display_reset.c
100
intel_pps_unlock_regs_wa(display);
drivers/gpu/drm/i915/display/intel_display_reset.c
101
intel_display_driver_init_hw(display);
drivers/gpu/drm/i915/display/intel_display_reset.c
102
intel_clock_gating_init(display->drm);
drivers/gpu/drm/i915/display/intel_display_reset.c
103
intel_cx0_pll_power_save_wa(display);
drivers/gpu/drm/i915/display/intel_display_reset.c
104
intel_hpd_init(display);
drivers/gpu/drm/i915/display/intel_display_reset.c
106
ret = __intel_display_driver_resume(display, state, ctx);
drivers/gpu/drm/i915/display/intel_display_reset.c
108
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_reset.c
111
intel_hpd_poll_disable(display);
drivers/gpu/drm/i915/display/intel_display_reset.c
118
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_display_reset.c
121
void intel_display_reset_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_reset.c
124
display->drm->debugfs_root,
drivers/gpu/drm/i915/display/intel_display_reset.c
125
&display->reset.count);
drivers/gpu/drm/i915/display/intel_display_reset.c
21
bool intel_display_reset_supported(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_reset.c
23
return display && HAS_DISPLAY(display);
drivers/gpu/drm/i915/display/intel_display_reset.c
26
bool intel_display_reset_test(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_reset.c
28
return display && HAS_DISPLAY(display) &&
drivers/gpu/drm/i915/display/intel_display_reset.c
29
display->params.force_reset_modeset_test;
drivers/gpu/drm/i915/display/intel_display_reset.c
32
void intel_display_reset_prepare(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_reset.c
34
struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;
drivers/gpu/drm/i915/display/intel_display_reset.c
42
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_display_reset.c
45
ret = drm_modeset_lock_all_ctx(display->drm, ctx);
drivers/gpu/drm/i915/display/intel_display_reset.c
55
state = drm_atomic_helper_duplicate_state(display->drm, ctx);
drivers/gpu/drm/i915/display/intel_display_reset.c
58
drm_err(display->drm, "Duplicating state failed with %i\n",
drivers/gpu/drm/i915/display/intel_display_reset.c
63
ret = drm_atomic_helper_disable_all(display->drm, ctx);
drivers/gpu/drm/i915/display/intel_display_reset.c
65
drm_err(display->drm, "Suspending crtc's failed with %i\n",
drivers/gpu/drm/i915/display/intel_display_reset.c
71
display->reset.count++;
drivers/gpu/drm/i915/display/intel_display_reset.c
72
display->restore.modeset_state = state;
drivers/gpu/drm/i915/display/intel_display_reset.c
76
void intel_display_reset_finish(struct intel_display *display, bool test_only)
drivers/gpu/drm/i915/display/intel_display_reset.c
78
struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;
drivers/gpu/drm/i915/display/intel_display_reset.c
82
state = fetch_and_zero(&display->restore.modeset_state);
drivers/gpu/drm/i915/display/intel_display_reset.c
91
drm_WARN_ON(display->drm, ret == -EDEADLK);
drivers/gpu/drm/i915/display/intel_display_reset.c
92
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_display_reset.h
13
bool intel_display_reset_supported(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_reset.h
14
bool intel_display_reset_test(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_reset.h
15
void intel_display_reset_prepare(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_reset.h
16
void intel_display_reset_finish(struct intel_display *display, bool test_only);
drivers/gpu/drm/i915/display/intel_display_reset.h
18
void intel_display_reset_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.c
11
return display->parent->rpm->get_raw(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
14
void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref)
drivers/gpu/drm/i915/display/intel_display_rpm.c
16
display->parent->rpm->put_raw(display->drm, wakeref);
drivers/gpu/drm/i915/display/intel_display_rpm.c
19
struct ref_tracker *intel_display_rpm_get(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
21
return display->parent->rpm->get(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
24
struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
26
return display->parent->rpm->get_if_in_use(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
29
struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
31
return display->parent->rpm->get_noresume(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
34
void intel_display_rpm_put(struct intel_display *display, struct ref_tracker *wakeref)
drivers/gpu/drm/i915/display/intel_display_rpm.c
36
display->parent->rpm->put(display->drm, wakeref);
drivers/gpu/drm/i915/display/intel_display_rpm.c
39
void intel_display_rpm_put_unchecked(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
41
display->parent->rpm->put_unchecked(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
44
bool intel_display_rpm_suspended(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
46
return display->parent->rpm->suspended(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
49
void assert_display_rpm_held(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
51
display->parent->rpm->assert_held(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
54
void intel_display_rpm_assert_block(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
56
display->parent->rpm->assert_block(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
59
void intel_display_rpm_assert_unblock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.c
61
display->parent->rpm->assert_unblock(display->drm);
drivers/gpu/drm/i915/display/intel_display_rpm.c
9
struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rpm.h
12
struct ref_tracker *intel_display_rpm_get(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
13
void intel_display_rpm_put(struct intel_display *display, struct ref_tracker *wakeref);
drivers/gpu/drm/i915/display/intel_display_rpm.h
23
bool intel_display_rpm_suspended(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
25
void assert_display_rpm_held(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
26
void intel_display_rpm_assert_block(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
27
void intel_display_rpm_assert_unblock(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
30
struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
31
void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref);
drivers/gpu/drm/i915/display/intel_display_rpm.h
33
struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
34
struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rpm.h
35
void intel_display_rpm_put_unchecked(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rps.c
101
spin_lock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_rps.c
102
ilk_disable_display_irq(display, DE_PCU_EVENT);
drivers/gpu/drm/i915/display/intel_display_rps.c
103
spin_unlock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_rps.c
106
void ilk_display_rps_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rps.c
108
intel_parent_rps_ilk_irq_handler(display);
drivers/gpu/drm/i915/display/intel_display_rps.c
29
struct intel_display *display = to_intel_display(wait->crtc->dev);
drivers/gpu/drm/i915/display/intel_display_rps.c
36
intel_parent_rps_boost_if_not_started(display, wait->fence);
drivers/gpu/drm/i915/display/intel_display_rps.c
50
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_display_rps.c
53
if (!intel_parent_rps_available(display))
drivers/gpu/drm/i915/display/intel_display_rps.c
56
if (DISPLAY_VER(display) < 6)
drivers/gpu/drm/i915/display/intel_display_rps.c
77
void intel_display_rps_mark_interactive(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_rps.c
81
if (!intel_parent_rps_available(display))
drivers/gpu/drm/i915/display/intel_display_rps.c
87
intel_parent_rps_mark_interactive(display, interactive);
drivers/gpu/drm/i915/display/intel_display_rps.c
92
void ilk_display_rps_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rps.c
94
spin_lock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_rps.c
95
ilk_enable_display_irq(display, DE_PCU_EVENT);
drivers/gpu/drm/i915/display/intel_display_rps.c
96
spin_unlock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_display_rps.c
99
void ilk_display_rps_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_rps.h
18
void intel_display_rps_mark_interactive(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_rps.h
21
void ilk_display_rps_enable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rps.h
22
void ilk_display_rps_disable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_rps.h
23
void ilk_display_rps_irq_handler(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_snapshot.c
17
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_display_snapshot.c
26
struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_snapshot.c
34
snapshot->display = display;
drivers/gpu/drm/i915/display/intel_display_snapshot.c
36
memcpy(&snapshot->info, DISPLAY_INFO(display), sizeof(snapshot->info));
drivers/gpu/drm/i915/display/intel_display_snapshot.c
37
memcpy(&snapshot->runtime_info, DISPLAY_RUNTIME_INFO(display),
drivers/gpu/drm/i915/display/intel_display_snapshot.c
42
snapshot->irq = intel_display_irq_snapshot_capture(display);
drivers/gpu/drm/i915/display/intel_display_snapshot.c
43
snapshot->dmc = intel_dmc_snapshot_capture(display);
drivers/gpu/drm/i915/display/intel_display_snapshot.c
51
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_display_snapshot.c
56
display = snapshot->display;
drivers/gpu/drm/i915/display/intel_display_snapshot.c
59
intel_display_params_dump(&snapshot->params, display->drm->driver->name, p);
drivers/gpu/drm/i915/display/intel_display_snapshot.h
11
struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_trace.h
110
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_trace.h
117
for_each_intel_crtc(display, it__) {
drivers/gpu/drm/i915/display/intel_display_trace.h
180
TP_PROTO(struct intel_display *display, enum pipe pipe),
drivers/gpu/drm/i915/display/intel_display_trace.h
181
TP_ARGS(display, pipe),
drivers/gpu/drm/i915/display/intel_display_trace.h
184
__string(dev, __dev_name_display(display))
drivers/gpu/drm/i915/display/intel_display_trace.h
191
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display_trace.h
204
TP_PROTO(struct intel_display *display, enum pipe pch_transcoder),
drivers/gpu/drm/i915/display/intel_display_trace.h
205
TP_ARGS(display, pch_transcoder),
drivers/gpu/drm/i915/display/intel_display_trace.h
208
__string(dev, __dev_name_display(display))
drivers/gpu/drm/i915/display/intel_display_trace.h
216
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_display_trace.h
229
TP_PROTO(struct intel_display *display, bool old, bool new),
drivers/gpu/drm/i915/display/intel_display_trace.h
230
TP_ARGS(display, old, new),
drivers/gpu/drm/i915/display/intel_display_trace.h
233
__string(dev, __dev_name_display(display))
drivers/gpu/drm/i915/display/intel_display_trace.h
247
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_display_trace.h
27
#define __dev_name_display(display) dev_name((display)->drm->dev)
drivers/gpu/drm/i915/display/intel_display_trace.h
520
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_display_trace.h
521
struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
drivers/gpu/drm/i915/display/intel_display_trace.h
613
struct intel_display *display = to_intel_display(plane->base.dev);
drivers/gpu/drm/i915/display/intel_display_trace.h
614
struct intel_crtc *crtc = intel_crtc_for_pipe(display,
drivers/gpu/drm/i915/display/intel_display_trace.h
641
struct intel_display *display = to_intel_display(plane->base.dev);
drivers/gpu/drm/i915/display/intel_display_trace.h
642
struct intel_crtc *crtc = intel_crtc_for_pipe(display,
drivers/gpu/drm/i915/display/intel_display_trace.h
669
struct intel_display *display = to_intel_display(plane->base.dev);
drivers/gpu/drm/i915/display/intel_display_trace.h
670
struct intel_crtc *crtc = intel_crtc_for_pipe(display,
drivers/gpu/drm/i915/display/intel_display_trace.h
80
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_display_trace.h
810
TP_PROTO(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_trace.h
812
TP_ARGS(display, frontbuffer_bits, origin),
drivers/gpu/drm/i915/display/intel_display_trace.h
815
__string(dev, __dev_name_display(display))
drivers/gpu/drm/i915/display/intel_display_trace.h
831
TP_PROTO(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_display_trace.h
833
TP_ARGS(display, frontbuffer_bits, origin),
drivers/gpu/drm/i915/display/intel_display_trace.h
836
__string(dev, __dev_name_display(display))
drivers/gpu/drm/i915/display/intel_display_trace.h
856
#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/display
drivers/gpu/drm/i915/display/intel_display_trace.h
87
for_each_intel_crtc(display, it__) {
drivers/gpu/drm/i915/display/intel_display_utils.c
15
bool intel_display_run_as_guest(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_utils.c
25
bool intel_display_vtd_active(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_utils.c
27
if (device_iommu_mapped(display->drm->dev))
drivers/gpu/drm/i915/display/intel_display_utils.c
31
return intel_display_run_as_guest(display);
drivers/gpu/drm/i915/display/intel_display_utils.h
24
bool intel_display_run_as_guest(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_utils.h
25
bool intel_display_vtd_active(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_wa.c
101
return (IS_DISPLAY_VERx100(display, 1200, 1300));
drivers/gpu/drm/i915/display/intel_display_wa.c
103
return display->platform.alderlake_s &&
drivers/gpu/drm/i915/display/intel_display_wa.c
104
IS_DISPLAY_STEP(display, STEP_A0, STEP_A2);
drivers/gpu/drm/i915/display/intel_display_wa.c
106
return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER);
drivers/gpu/drm/i915/display/intel_display_wa.c
108
return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0);
drivers/gpu/drm/i915/display/intel_display_wa.c
110
return DISPLAY_VERx100(display) == 3000 ||
drivers/gpu/drm/i915/display/intel_display_wa.c
111
DISPLAY_VERx100(display) == 2000 ||
drivers/gpu/drm/i915/display/intel_display_wa.c
112
DISPLAY_VERx100(display) == 1401;
drivers/gpu/drm/i915/display/intel_display_wa.c
114
return DISPLAY_VER(display) == 35;
drivers/gpu/drm/i915/display/intel_display_wa.c
116
return DISPLAY_VER(display) == 20;
drivers/gpu/drm/i915/display/intel_display_wa.c
118
return display->platform.battlemage;
drivers/gpu/drm/i915/display/intel_display_wa.c
121
return display->platform.alderlake_p &&
drivers/gpu/drm/i915/display/intel_display_wa.c
122
IS_DISPLAY_STEP(display, STEP_A0, STEP_B0);
drivers/gpu/drm/i915/display/intel_display_wa.c
124
return display->platform.rocketlake || display->platform.alderlake_s ||
drivers/gpu/drm/i915/display/intel_display_wa.c
125
display->platform.dg2;
drivers/gpu/drm/i915/display/intel_display_wa.c
127
return display->platform.alderlake_p &&
drivers/gpu/drm/i915/display/intel_display_wa.c
128
IS_DISPLAY_STEP(display, STEP_A0, STEP_D0);
drivers/gpu/drm/i915/display/intel_display_wa.c
130
return DISPLAY_VER(display) >= 11;
drivers/gpu/drm/i915/display/intel_display_wa.c
132
return intel_display_needs_wa_16023588340(display);
drivers/gpu/drm/i915/display/intel_display_wa.c
134
return intel_display_needs_wa_16025573575(display);
drivers/gpu/drm/i915/display/intel_display_wa.c
136
return DISPLAY_VER(display) == 20 &&
drivers/gpu/drm/i915/display/intel_display_wa.c
137
IS_DISPLAY_VERx100_STEP(display, 3000,
drivers/gpu/drm/i915/display/intel_display_wa.c
14
static void gen11_display_wa_apply(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.c
140
return DISPLAY_VER(display) >= 35;
drivers/gpu/drm/i915/display/intel_display_wa.c
142
return DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_display_wa.c
143
(display->platform.pantherlake &&
drivers/gpu/drm/i915/display/intel_display_wa.c
144
IS_DISPLAY_STEP(display, STEP_A0, STEP_B0));
drivers/gpu/drm/i915/display/intel_display_wa.c
146
return DISPLAY_VER(display) == 12;
drivers/gpu/drm/i915/display/intel_display_wa.c
148
return display->platform.alderlake_p;
drivers/gpu/drm/i915/display/intel_display_wa.c
150
return display->platform.alderlake_p &&
drivers/gpu/drm/i915/display/intel_display_wa.c
151
IS_DISPLAY_STEP(display, STEP_A0, STEP_E0);
drivers/gpu/drm/i915/display/intel_display_wa.c
153
return IS_DISPLAY_VERx100(display, 1100, 1400);
drivers/gpu/drm/i915/display/intel_display_wa.c
155
return IS_DISPLAY_VER(display, 14, 35);
drivers/gpu/drm/i915/display/intel_display_wa.c
157
drm_WARN(display->drm, 1, "Missing Wa: %s\n", name);
drivers/gpu/drm/i915/display/intel_display_wa.c
17
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
drivers/gpu/drm/i915/display/intel_display_wa.c
20
static void xe_d_display_wa_apply(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.c
23
intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
drivers/gpu/drm/i915/display/intel_display_wa.c
26
static void adlp_display_wa_apply(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.c
29
intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
drivers/gpu/drm/i915/display/intel_display_wa.c
32
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
drivers/gpu/drm/i915/display/intel_display_wa.c
35
static void xe3plpd_display_wa_apply(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.c
38
intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS);
drivers/gpu/drm/i915/display/intel_display_wa.c
41
void intel_display_wa_apply(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.c
43
if (DISPLAY_VER(display) == 35)
drivers/gpu/drm/i915/display/intel_display_wa.c
44
xe3plpd_display_wa_apply(display);
drivers/gpu/drm/i915/display/intel_display_wa.c
45
else if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_display_wa.c
46
adlp_display_wa_apply(display);
drivers/gpu/drm/i915/display/intel_display_wa.c
47
else if (DISPLAY_VER(display) == 12)
drivers/gpu/drm/i915/display/intel_display_wa.c
48
xe_d_display_wa_apply(display);
drivers/gpu/drm/i915/display/intel_display_wa.c
49
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_display_wa.c
50
gen11_display_wa_apply(display);
drivers/gpu/drm/i915/display/intel_display_wa.c
58
static bool intel_display_needs_wa_16025573575(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.c
60
return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
drivers/gpu/drm/i915/display/intel_display_wa.c
61
DISPLAY_VERx100(display) == 3500;
drivers/gpu/drm/i915/display/intel_display_wa.c
70
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
drivers/gpu/drm/i915/display/intel_display_wa.c
74
return IS_DISPLAY_VER(display, 11, 12);
drivers/gpu/drm/i915/display/intel_display_wa.c
76
return (display->platform.alderlake_s ||
drivers/gpu/drm/i915/display/intel_display_wa.c
77
(display->platform.rocketlake &&
drivers/gpu/drm/i915/display/intel_display_wa.c
78
IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)));
drivers/gpu/drm/i915/display/intel_display_wa.c
80
return DISPLAY_VERx100(display) == 3000 ||
drivers/gpu/drm/i915/display/intel_display_wa.c
81
DISPLAY_VERx100(display) == 3500;
drivers/gpu/drm/i915/display/intel_display_wa.c
83
return display->platform.dg1 || display->platform.rocketlake ||
drivers/gpu/drm/i915/display/intel_display_wa.c
84
(display->platform.tigerlake &&
drivers/gpu/drm/i915/display/intel_display_wa.c
85
IS_DISPLAY_STEP(display, STEP_A0, STEP_D0));
drivers/gpu/drm/i915/display/intel_display_wa.c
87
return (IS_DISPLAY_VER(display, 10, 12));
drivers/gpu/drm/i915/display/intel_display_wa.c
89
return display->platform.dg2;
drivers/gpu/drm/i915/display/intel_display_wa.c
91
return INTEL_PCH_TYPE(display) >= PCH_CNP &&
drivers/gpu/drm/i915/display/intel_display_wa.c
92
INTEL_PCH_TYPE(display) < PCH_DG1;
drivers/gpu/drm/i915/display/intel_display_wa.c
94
return INTEL_PCH_TYPE(display) >= PCH_TGP &&
drivers/gpu/drm/i915/display/intel_display_wa.c
95
INTEL_PCH_TYPE(display) < PCH_DG1;
drivers/gpu/drm/i915/display/intel_display_wa.c
99
return DISPLAY_VER(display) == 13;
drivers/gpu/drm/i915/display/intel_display_wa.h
13
void intel_display_wa_apply(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_wa.h
16
static inline bool intel_display_needs_wa_16023588340(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_display_wa.h
21
bool intel_display_needs_wa_16023588340(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_display_wa.h
66
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
109
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
drivers/gpu/drm/i915/display/intel_dkl_phy.c
111
spin_lock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
113
dkl_phy_set_hip_idx(display, reg);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
114
intel_de_posting_read(display, DKL_REG_MMIO(reg));
drivers/gpu/drm/i915/display/intel_dkl_phy.c
116
spin_unlock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
18
void intel_dkl_phy_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dkl_phy.c
20
spin_lock_init(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
24
dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
drivers/gpu/drm/i915/display/intel_dkl_phy.c
28
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dkl_phy.c
32
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_dkl_phy.c
47
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
drivers/gpu/drm/i915/display/intel_dkl_phy.c
51
spin_lock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
53
dkl_phy_set_hip_idx(display, reg);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
54
val = intel_de_read(display, DKL_REG_MMIO(reg));
drivers/gpu/drm/i915/display/intel_dkl_phy.c
56
spin_unlock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
70
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
drivers/gpu/drm/i915/display/intel_dkl_phy.c
72
spin_lock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
74
dkl_phy_set_hip_idx(display, reg);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
75
intel_de_write(display, DKL_REG_MMIO(reg), val);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
77
spin_unlock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
91
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
drivers/gpu/drm/i915/display/intel_dkl_phy.c
93
spin_lock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
95
dkl_phy_set_hip_idx(display, reg);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
96
intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
drivers/gpu/drm/i915/display/intel_dkl_phy.c
98
spin_unlock(&display->dkl.phy_lock);
drivers/gpu/drm/i915/display/intel_dkl_phy.h
15
void intel_dkl_phy_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dkl_phy.h
17
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
drivers/gpu/drm/i915/display/intel_dkl_phy.h
19
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
drivers/gpu/drm/i915/display/intel_dkl_phy.h
21
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
drivers/gpu/drm/i915/display/intel_dkl_phy.h
23
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
drivers/gpu/drm/i915/display/intel_dmc.c
1004
drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
1026
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.c
1036
} else if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_dmc.c
1039
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dmc.c
1043
drm_warn(display->drm, "Unknown mmio range for sanity check");
drivers/gpu/drm/i915/display/intel_dmc.c
1059
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.c
1107
drm_err(display->drm, "Unknown DMC fw header version: %u\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1113
drm_err(display->drm, "DMC firmware has wrong dmc header length "
drivers/gpu/drm/i915/display/intel_dmc.c
1120
drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
drivers/gpu/drm/i915/display/intel_dmc.c
1126
drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1130
drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
1142
if (!fixup_dmc_evt(display, dmc_id,
drivers/gpu/drm/i915/display/intel_dmc.c
1147
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dmc.c
1151
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dmc.c
1158
drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1160
is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
drivers/gpu/drm/i915/display/intel_dmc.c
1161
is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
drivers/gpu/drm/i915/display/intel_dmc.c
1162
disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],
drivers/gpu/drm/i915/display/intel_dmc.c
1176
drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);
drivers/gpu/drm/i915/display/intel_dmc.c
1191
drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1201
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.c
1214
drm_err(display->drm, "DMC firmware has unknown header version %u\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1228
drm_err(display->drm, "DMC firmware has wrong package header length "
drivers/gpu/drm/i915/display/intel_dmc.c
1246
drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1255
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.c
1258
drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1264
drm_err(display->drm, "DMC firmware has wrong CSS header length "
drivers/gpu/drm/i915/display/intel_dmc.c
1277
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.c
1289
initialize_stepping_info(display, &si);
drivers/gpu/drm/i915/display/intel_dmc.c
1313
drm_err(display->drm, "Reading beyond the fw_size\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1321
if (!intel_dmc_has_payload(display)) {
drivers/gpu/drm/i915/display/intel_dmc.c
1322
drm_err(display->drm, "DMC firmware main program not found\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1329
static void intel_dmc_runtime_pm_get(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1331
drm_WARN_ON(display->drm, display->dmc.wakeref);
drivers/gpu/drm/i915/display/intel_dmc.c
1332
display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
drivers/gpu/drm/i915/display/intel_dmc.c
1335
static void intel_dmc_runtime_pm_put(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1338
fetch_and_zero(&display->dmc.wakeref);
drivers/gpu/drm/i915/display/intel_dmc.c
1340
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
drivers/gpu/drm/i915/display/intel_dmc.c
1343
static const char *dmc_fallback_path(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1345
if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_dmc.c
1354
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.c
1359
err = request_firmware(&fw, dmc->fw_path, display->drm->dev);
drivers/gpu/drm/i915/display/intel_dmc.c
1361
if (err == -ENOENT && !dmc_firmware_param(display)) {
drivers/gpu/drm/i915/display/intel_dmc.c
1362
fallback_path = dmc_fallback_path(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1364
drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1366
err = request_firmware(&fw, fallback_path, display->drm->dev);
drivers/gpu/drm/i915/display/intel_dmc.c
1373
drm_notice(display->drm,
drivers/gpu/drm/i915/display/intel_dmc.c
1376
drm_notice(display->drm, "DMC firmware homepage: %s",
drivers/gpu/drm/i915/display/intel_dmc.c
1383
drm_notice(display->drm,
drivers/gpu/drm/i915/display/intel_dmc.c
1389
intel_dmc_load_program(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1390
intel_dmc_runtime_pm_put(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1392
drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1407
void intel_dmc_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1411
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1422
intel_dmc_runtime_pm_get(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1428
dmc->display = display;
drivers/gpu/drm/i915/display/intel_dmc.c
1432
dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);
drivers/gpu/drm/i915/display/intel_dmc.c
1434
if (dmc_firmware_param_disabled(display)) {
drivers/gpu/drm/i915/display/intel_dmc.c
1435
drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");
drivers/gpu/drm/i915/display/intel_dmc.c
1439
if (dmc_firmware_param(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1440
dmc->fw_path = dmc_firmware_param(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1443
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dmc.c
1448
display->dmc.dmc = dmc;
drivers/gpu/drm/i915/display/intel_dmc.c
1450
drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);
drivers/gpu/drm/i915/display/intel_dmc.c
1451
queue_work(display->wq.unordered, &dmc->work);
drivers/gpu/drm/i915/display/intel_dmc.c
1467
void intel_dmc_suspend(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1469
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1471
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1478
if (!intel_dmc_has_payload(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1479
intel_dmc_runtime_pm_put(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1482
void intel_dmc_wait_fw_load(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1484
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1486
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1500
void intel_dmc_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1502
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1509
if (!intel_dmc_has_payload(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1510
intel_dmc_runtime_pm_get(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1520
void intel_dmc_fini(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1522
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1525
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1528
intel_dmc_suspend(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1529
drm_WARN_ON(display->drm, display->dmc.wakeref);
drivers/gpu/drm/i915/display/intel_dmc.c
1536
display->dmc.dmc = NULL;
drivers/gpu/drm/i915/display/intel_dmc.c
1546
struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1548
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1551
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1559
snapshot->loaded = intel_dmc_has_payload(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1579
void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
1582
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1585
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_dmc.c
1588
dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
drivers/gpu/drm/i915/display/intel_dmc.c
1596
static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
drivers/gpu/drm/i915/display/intel_dmc.c
1598
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_dmc.c
1599
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1602
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_dmc.c
1608
intel_dmc_update_dc6_allowed_count(display, false);
drivers/gpu/drm/i915/display/intel_dmc.c
1618
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_dmc.c
1619
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1624
if (!HAS_DMC(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1627
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1631
str_yes_no(intel_dmc_has_payload(display)));
drivers/gpu/drm/i915/display/intel_dmc.c
1634
str_yes_no(DISPLAY_VER(display) >= 12));
drivers/gpu/drm/i915/display/intel_dmc.c
1636
str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));
drivers/gpu/drm/i915/display/intel_dmc.c
1638
str_yes_no(display->platform.alderlake_p ||
drivers/gpu/drm/i915/display/intel_dmc.c
1639
DISPLAY_VER(display) >= 14));
drivers/gpu/drm/i915/display/intel_dmc.c
1641
str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));
drivers/gpu/drm/i915/display/intel_dmc.c
1643
if (!intel_dmc_has_payload(display))
drivers/gpu/drm/i915/display/intel_dmc.c
1649
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dmc.c
1652
if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_dmc.c
1662
intel_de_read(display, dc3co_reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1664
dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT :
drivers/gpu/drm/i915/display/intel_dmc.c
1666
if (!display->platform.geminilake && !display->platform.broxton)
drivers/gpu/drm/i915/display/intel_dmc.c
1670
seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1672
if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
drivers/gpu/drm/i915/display/intel_dmc.c
1677
intel_de_read(display, dc6_reg));
drivers/gpu/drm/i915/display/intel_dmc.c
1680
intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
drivers/gpu/drm/i915/display/intel_dmc.c
1684
intel_de_read(display, DMC_SSP_BASE));
drivers/gpu/drm/i915/display/intel_dmc.c
1685
seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));
drivers/gpu/drm/i915/display/intel_dmc.c
1687
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_dmc.c
1694
void intel_dmc_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
1696
debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root,
drivers/gpu/drm/i915/display/intel_dmc.c
1697
display, &intel_dmc_debugfs_status_fops);
drivers/gpu/drm/i915/display/intel_dmc.c
1700
void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dmc.c
1702
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_dmc.c
1705
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_dmc.c
1706
tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
drivers/gpu/drm/i915/display/intel_dmc.c
1707
intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
drivers/gpu/drm/i915/display/intel_dmc.c
1710
spin_lock(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_dmc.c
1723
spin_unlock(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_dmc.c
1727
drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1730
drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1733
drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1737
int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;
drivers/gpu/drm/i915/display/intel_dmc.c
1739
drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n",
drivers/gpu/drm/i915/display/intel_dmc.c
1746
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dmc.c
1749
dmc_configure_event(display, dmc_id, event, true);
drivers/gpu/drm/i915/display/intel_dmc.c
1755
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dmc.c
1758
dmc_configure_event(display, dmc_id, event, false);
drivers/gpu/drm/i915/display/intel_dmc.c
1763
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dmc.c
1764
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
1772
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dmc.c
1775
intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
drivers/gpu/drm/i915/display/intel_dmc.c
1781
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dmc.c
1784
intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
drivers/gpu/drm/i915/display/intel_dmc.c
186
static const char *dmc_firmware_default(struct intel_display *display, u32 *size)
drivers/gpu/drm/i915/display/intel_dmc.c
191
if (DISPLAY_VERx100(display) == 3500) {
drivers/gpu/drm/i915/display/intel_dmc.c
194
} else if (DISPLAY_VERx100(display) == 3002) {
drivers/gpu/drm/i915/display/intel_dmc.c
197
} else if (DISPLAY_VERx100(display) == 3000) {
drivers/gpu/drm/i915/display/intel_dmc.c
200
} else if (DISPLAY_VERx100(display) == 2000) {
drivers/gpu/drm/i915/display/intel_dmc.c
203
} else if (DISPLAY_VERx100(display) == 1401) {
drivers/gpu/drm/i915/display/intel_dmc.c
206
} else if (DISPLAY_VERx100(display) == 1400) {
drivers/gpu/drm/i915/display/intel_dmc.c
209
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_dmc.c
212
} else if (display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/intel_dmc.c
215
} else if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_dmc.c
218
} else if (display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_dmc.c
221
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_dmc.c
224
} else if (display->platform.tigerlake) {
drivers/gpu/drm/i915/display/intel_dmc.c
227
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/intel_dmc.c
230
} else if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_dmc.c
233
} else if (display->platform.kabylake ||
drivers/gpu/drm/i915/display/intel_dmc.c
234
display->platform.coffeelake ||
drivers/gpu/drm/i915/display/intel_dmc.c
235
display->platform.cometlake) {
drivers/gpu/drm/i915/display/intel_dmc.c
238
} else if (display->platform.skylake) {
drivers/gpu/drm/i915/display/intel_dmc.c
241
} else if (display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_dmc.c
408
static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)
drivers/gpu/drm/i915/display/intel_dmc.c
410
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
415
bool intel_dmc_has_payload(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
417
return has_dmc_id_fw(display, DMC_FW_MAIN);
drivers/gpu/drm/i915/display/intel_dmc.c
420
static void initialize_stepping_info(struct intel_display *display, struct stepping_info *si)
drivers/gpu/drm/i915/display/intel_dmc.c
422
const char *step_name = DISPLAY_RUNTIME_INFO(display)->step_name;
drivers/gpu/drm/i915/display/intel_dmc.c
428
static void gen9_set_dc_state_debugmask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
431
intel_de_rmw(display, DC_STATE_DEBUG, 0,
drivers/gpu/drm/i915/display/intel_dmc.c
433
intel_de_posting_read(display, DC_STATE_DEBUG);
drivers/gpu/drm/i915/display/intel_dmc.c
436
static void disable_event_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
439
intel_de_write(display, ctl_reg,
drivers/gpu/drm/i915/display/intel_dmc.c
444
intel_de_write(display, htp_reg, 0);
drivers/gpu/drm/i915/display/intel_dmc.c
447
static void disable_all_event_handlers(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
453
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_dmc.c
456
if (!has_dmc_id_fw(display, dmc_id))
drivers/gpu/drm/i915/display/intel_dmc.c
460
disable_event_handler(display,
drivers/gpu/drm/i915/display/intel_dmc.c
461
DMC_EVT_CTL(display, dmc_id, handler),
drivers/gpu/drm/i915/display/intel_dmc.c
462
DMC_EVT_HTP(display, dmc_id, handler));
drivers/gpu/drm/i915/display/intel_dmc.c
465
static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/intel_dmc.c
478
intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
drivers/gpu/drm/i915/display/intel_dmc.c
482
intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
drivers/gpu/drm/i915/display/intel_dmc.c
486
static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
493
intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
drivers/gpu/drm/i915/display/intel_dmc.c
498
static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/intel_dmc.c
500
if (display->platform.meteorlake && enable)
drivers/gpu/drm/i915/display/intel_dmc.c
501
mtl_pipedmc_clock_gating_wa(display);
drivers/gpu/drm/i915/display/intel_dmc.c
502
else if (DISPLAY_VER(display) == 13)
drivers/gpu/drm/i915/display/intel_dmc.c
503
adlp_pipedmc_clock_gating_wa(display, enable);
drivers/gpu/drm/i915/display/intel_dmc.c
506
static u32 pipedmc_interrupt_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
512
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_dmc.c
540
static bool is_dmc_evt_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
544
u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
drivers/gpu/drm/i915/display/intel_dmc.c
545
u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
drivers/gpu/drm/i915/display/intel_dmc.c
550
static bool is_dmc_evt_htp_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
554
u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
drivers/gpu/drm/i915/display/intel_dmc.c
555
u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
drivers/gpu/drm/i915/display/intel_dmc.c
560
static bool is_event_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
565
return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&
drivers/gpu/drm/i915/display/intel_dmc.c
569
static bool fixup_dmc_evt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
574
if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))
drivers/gpu/drm/i915/display/intel_dmc.c
577
if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp))
drivers/gpu/drm/i915/display/intel_dmc.c
581
if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=
drivers/gpu/drm/i915/display/intel_dmc.c
582
intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))
drivers/gpu/drm/i915/display/intel_dmc.c
589
if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN &&
drivers/gpu/drm/i915/display/intel_dmc.c
590
is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {
drivers/gpu/drm/i915/display/intel_dmc.c
603
if ((display->platform.tigerlake || display->platform.alderlake_s) &&
drivers/gpu/drm/i915/display/intel_dmc.c
604
is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {
drivers/gpu/drm/i915/display/intel_dmc.c
614
static bool disable_dmc_evt(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
618
if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
drivers/gpu/drm/i915/display/intel_dmc.c
626
if (display->platform.tigerlake &&
drivers/gpu/drm/i915/display/intel_dmc.c
627
is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))
drivers/gpu/drm/i915/display/intel_dmc.c
63
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_dmc.c
631
if ((display->platform.tigerlake || display->platform.alderlake_s) &&
drivers/gpu/drm/i915/display/intel_dmc.c
632
is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data))
drivers/gpu/drm/i915/display/intel_dmc.c
638
static u32 dmc_mmiodata(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
642
if (disable_dmc_evt(display, dmc_id,
drivers/gpu/drm/i915/display/intel_dmc.c
650
static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id)
drivers/gpu/drm/i915/display/intel_dmc.c
652
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
656
intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
drivers/gpu/drm/i915/display/intel_dmc.c
657
dmc_mmiodata(display, dmc, dmc_id, i));
drivers/gpu/drm/i915/display/intel_dmc.c
661
static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id)
drivers/gpu/drm/i915/display/intel_dmc.c
663
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
666
disable_all_event_handlers(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
671
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/intel_dmc.c
678
dmc_load_mmio(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
681
static void assert_dmc_loaded(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
684
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
688
if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
drivers/gpu/drm/i915/display/intel_dmc.c
691
found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));
drivers/gpu/drm/i915/display/intel_dmc.c
694
drm_WARN(display->drm, found != expected,
drivers/gpu/drm/i915/display/intel_dmc.c
701
found = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_dmc.c
702
expected = dmc_mmiodata(display, dmc, dmc_id, i);
drivers/gpu/drm/i915/display/intel_dmc.c
704
drm_WARN(display->drm, found != expected,
drivers/gpu/drm/i915/display/intel_dmc.c
710
void assert_main_dmc_loaded(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
712
assert_dmc_loaded(display, DMC_FW_MAIN);
drivers/gpu/drm/i915/display/intel_dmc.c
715
static bool need_pipedmc_load_program(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
718
return DISPLAY_VER(display) == 12;
drivers/gpu/drm/i915/display/intel_dmc.c
721
static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dmc.c
728
if (IS_DISPLAY_VER(display, 30, 35))
drivers/gpu/drm/i915/display/intel_dmc.c
737
if (DISPLAY_VER(display) == 20)
drivers/gpu/drm/i915/display/intel_dmc.c
744
if (display->platform.battlemage)
drivers/gpu/drm/i915/display/intel_dmc.c
753
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_dmc.c
761
if (IS_DISPLAY_VER(display, 13, 14))
drivers/gpu/drm/i915/display/intel_dmc.c
769
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dmc.c
776
if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)
drivers/gpu/drm/i915/display/intel_dmc.c
784
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dmc.c
789
if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
drivers/gpu/drm/i915/display/intel_dmc.c
797
if (need_pipedmc_load_program(display))
drivers/gpu/drm/i915/display/intel_dmc.c
798
dmc_load_program(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
799
else if (need_pipedmc_load_mmio(display, pipe))
drivers/gpu/drm/i915/display/intel_dmc.c
800
dmc_load_mmio(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
802
assert_dmc_loaded(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
804
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_dmc.c
805
intel_flipq_reset(display, pipe);
drivers/gpu/drm/i915/display/intel_dmc.c
807
intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
drivers/gpu/drm/i915/display/intel_dmc.c
808
intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));
drivers/gpu/drm/i915/display/intel_dmc.c
811
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dmc.c
812
intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
drivers/gpu/drm/i915/display/intel_dmc.c
814
intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
drivers/gpu/drm/i915/display/intel_dmc.c
819
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dmc.c
824
if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
drivers/gpu/drm/i915/display/intel_dmc.c
827
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dmc.c
828
intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
drivers/gpu/drm/i915/display/intel_dmc.c
830
intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dmc.c
832
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_dmc.c
833
intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
drivers/gpu/drm/i915/display/intel_dmc.c
834
intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
drivers/gpu/drm/i915/display/intel_dmc.c
836
intel_flipq_reset(display, pipe);
drivers/gpu/drm/i915/display/intel_dmc.c
840
static void dmc_configure_event(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
845
struct intel_dmc *dmc = display_to_dmc(display);
drivers/gpu/drm/i915/display/intel_dmc.c
85
static struct intel_dmc *display_to_dmc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
853
if (!is_event_handler(display, dmc_id, event_id, reg, data))
drivers/gpu/drm/i915/display/intel_dmc.c
856
intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data));
drivers/gpu/drm/i915/display/intel_dmc.c
860
drm_WARN_ONCE(display->drm, num_handlers != 1,
drivers/gpu/drm/i915/display/intel_dmc.c
865
void intel_dmc_configure_dc_balance_event(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
87
return display->dmc.dmc;
drivers/gpu/drm/i915/display/intel_dmc.c
870
dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
drivers/gpu/drm/i915/display/intel_dmc.c
882
void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_dmc.c
885
intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe),
drivers/gpu/drm/i915/display/intel_dmc.c
90
static const char *dmc_firmware_param(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
900
void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.c
905
dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable);
drivers/gpu/drm/i915/display/intel_dmc.c
916
void intel_dmc_load_program(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
918
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_dmc.c
92
const char *p = display->params.dmc_firmware_path;
drivers/gpu/drm/i915/display/intel_dmc.c
921
if (!intel_dmc_has_payload(display))
drivers/gpu/drm/i915/display/intel_dmc.c
924
assert_display_rpm_held(display);
drivers/gpu/drm/i915/display/intel_dmc.c
926
pipedmc_clock_gating_wa(display, true);
drivers/gpu/drm/i915/display/intel_dmc.c
929
dmc_load_program(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
930
assert_dmc_loaded(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
933
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_dmc.c
934
intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,
drivers/gpu/drm/i915/display/intel_dmc.c
942
gen9_set_dc_state_debugmask(display);
drivers/gpu/drm/i915/display/intel_dmc.c
944
pipedmc_clock_gating_wa(display, false);
drivers/gpu/drm/i915/display/intel_dmc.c
954
void intel_dmc_disable_program(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
958
if (!intel_dmc_has_payload(display))
drivers/gpu/drm/i915/display/intel_dmc.c
961
pipedmc_clock_gating_wa(display, true);
drivers/gpu/drm/i915/display/intel_dmc.c
964
disable_all_event_handlers(display, dmc_id);
drivers/gpu/drm/i915/display/intel_dmc.c
966
pipedmc_clock_gating_wa(display, false);
drivers/gpu/drm/i915/display/intel_dmc.c
97
static bool dmc_firmware_param_disabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc.c
99
const char *p = dmc_firmware_param(display);
drivers/gpu/drm/i915/display/intel_dmc.c
996
struct intel_display *display = dmc->display;
drivers/gpu/drm/i915/display/intel_dmc.h
20
void intel_dmc_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
21
void intel_dmc_load_program(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
22
void intel_dmc_wait_fw_load(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
23
void intel_dmc_disable_program(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
26
void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_dmc.h
28
void intel_dmc_configure_dc_balance_event(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.h
30
void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc.h
32
void intel_dmc_fini(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
33
void intel_dmc_suspend(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
34
void intel_dmc_resume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
35
bool intel_dmc_has_payload(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
36
void intel_dmc_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
38
struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
40
void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
drivers/gpu/drm/i915/display/intel_dmc.h
42
void assert_main_dmc_loaded(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc.h
44
void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dmc.h
54
void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
162
static void __intel_dmc_wl_release(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
164
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
168
queue_delayed_work(display->wq.unordered, &wl->work,
drivers/gpu/drm/i915/display/intel_dmc_wl.c
176
struct intel_display *display =
drivers/gpu/drm/i915/display/intel_dmc_wl.c
189
intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
191
if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,
drivers/gpu/drm/i915/display/intel_dmc_wl.c
204
static void __intel_dmc_wl_take(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
206
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
217
intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, 0, DMC_WAKELOCK_CTL_REQ);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
223
if (intel_de_wait_fw_us_atomic(display, DMC_WAKELOCK1_CTL,
drivers/gpu/drm/i915/display/intel_dmc_wl.c
249
static bool intel_dmc_wl_check_range(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dmc_wl.c
255
if (display->params.enable_dmc_wl == ENABLE_DMC_WL_ANY_REGISTER)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
287
static bool __intel_dmc_wl_supported(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
289
return display->params.enable_dmc_wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
292
static void intel_dmc_wl_sanitize_param(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
296
if (DISPLAY_VER(display) < 20) {
drivers/gpu/drm/i915/display/intel_dmc_wl.c
297
display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
298
} else if (display->params.enable_dmc_wl < 0) {
drivers/gpu/drm/i915/display/intel_dmc_wl.c
299
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
300
display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
302
display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
303
} else if (display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX) {
drivers/gpu/drm/i915/display/intel_dmc_wl.c
304
display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
307
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dmc_wl.c
308
display->params.enable_dmc_wl < 0 ||
drivers/gpu/drm/i915/display/intel_dmc_wl.c
309
display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
311
switch (display->params.enable_dmc_wl) {
drivers/gpu/drm/i915/display/intel_dmc_wl.c
329
drm_dbg_kms(display->drm, "Sanitized enable_dmc_wl value: %d (%s)\n",
drivers/gpu/drm/i915/display/intel_dmc_wl.c
330
display->params.enable_dmc_wl, desc);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
333
void intel_dmc_wl_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
335
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
337
intel_dmc_wl_sanitize_param(display);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
339
if (!display->params.enable_dmc_wl)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
345
display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
349
void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
351
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
354
if (!__intel_dmc_wl_supported(display))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
361
if (drm_WARN_ON(display->drm, wl->enabled))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
369
intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
388
__intel_dmc_wl_take(display);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
395
void intel_dmc_wl_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
397
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
400
if (!__intel_dmc_wl_supported(display))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
403
intel_dmc_wl_flush_release_work(display);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
407
if (drm_WARN_ON(display->drm, !wl->enabled))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
411
intel_de_rmw_fw(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
423
intel_de_rmw_fw(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
431
void intel_dmc_wl_flush_release_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
433
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
435
if (!__intel_dmc_wl_supported(display))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
441
void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
443
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
446
if (!__intel_dmc_wl_supported(display))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
452
!intel_dmc_wl_check_range(display, reg, wl->dc_state))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
468
__intel_dmc_wl_take(display);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
474
void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
476
struct intel_dmc_wl *wl = &display->wl;
drivers/gpu/drm/i915/display/intel_dmc_wl.c
479
if (!__intel_dmc_wl_supported(display))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
485
!intel_dmc_wl_check_range(display, reg, wl->dc_state))
drivers/gpu/drm/i915/display/intel_dmc_wl.c
496
__intel_dmc_wl_release(display);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
505
void intel_dmc_wl_get_noreg(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
507
intel_dmc_wl_get(display, INVALID_MMIO_REG);
drivers/gpu/drm/i915/display/intel_dmc_wl.c
510
void intel_dmc_wl_put_noreg(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dmc_wl.c
512
intel_dmc_wl_put(display, INVALID_MMIO_REG);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
32
void intel_dmc_wl_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
33
void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
34
void intel_dmc_wl_disable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
35
void intel_dmc_wl_flush_release_work(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
36
void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
37
void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
38
void intel_dmc_wl_get_noreg(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dmc_wl.h
39
void intel_dmc_wl_put_noreg(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.c
1048
if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
drivers/gpu/drm/i915/display/intel_dp.c
1053
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
1071
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
1098
if (!intel_dsc_get_slice_config(display,
drivers/gpu/drm/i915/display/intel_dp.c
1121
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
1147
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1159
return !HAS_GMCH(display) && !display->platform.ironlake;
drivers/gpu/drm/i915/display/intel_dp.c
1163
return DISPLAY_VER(display) >= 11;
drivers/gpu/drm/i915/display/intel_dp.c
1223
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
1235
drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
drivers/gpu/drm/i915/display/intel_dp.c
1249
drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
drivers/gpu/drm/i915/display/intel_dp.c
1284
static bool intel_dp_hdisplay_bad(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
1300
return hdisplay == 4096 && !HAS_DDI(display);
drivers/gpu/drm/i915/display/intel_dp.c
1412
int intel_dp_max_hdisplay_per_pipe(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
1414
return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
drivers/gpu/drm/i915/display/intel_dp.c
1419
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
1421
if (!HAS_DSC(display))
drivers/gpu/drm/i915/display/intel_dp.c
1424
if (connector->mst.dp && !HAS_DSC_MST(display))
drivers/gpu/drm/i915/display/intel_dp.c
1441
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1450
return HAS_BIGJOINER(display) ||
drivers/gpu/drm/i915/display/intel_dp.c
1451
HAS_UNCOMPRESSED_JOINER(display);
drivers/gpu/drm/i915/display/intel_dp.c
1453
return HAS_ULTRAJOINER(display);
drivers/gpu/drm/i915/display/intel_dp.c
1459
bool intel_dp_dotclk_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
1465
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_dp.c
1471
target_clock = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,
drivers/gpu/drm/i915/display/intel_dp.c
1477
intel_max_uncompressed_dotclock(display) * num_joined_pipes;
drivers/gpu/drm/i915/display/intel_dp.c
1488
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
1526
status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
drivers/gpu/drm/i915/display/intel_dp.c
1568
if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
drivers/gpu/drm/i915/display/intel_dp.c
1578
status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
drivers/gpu/drm/i915/display/intel_dp.c
1585
if (!intel_dp_dotclk_valid(display,
drivers/gpu/drm/i915/display/intel_dp.c
160
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1608
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_dp.c
1615
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_dp.c
1625
if (intel_dp_hdisplay_bad(display, mode->hdisplay))
drivers/gpu/drm/i915/display/intel_dp.c
1662
bool intel_dp_source_supports_tps3(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
1664
return DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_dp.c
1665
display->platform.broadwell || display->platform.haswell;
drivers/gpu/drm/i915/display/intel_dp.c
1668
bool intel_dp_source_supports_tps4(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
1670
return DISPLAY_VER(display) >= 10;
drivers/gpu/drm/i915/display/intel_dp.c
1683
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1690
drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));
drivers/gpu/drm/i915/display/intel_dp.c
1694
drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));
drivers/gpu/drm/i915/display/intel_dp.c
1698
drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
drivers/gpu/drm/i915/display/intel_dp.c
1735
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1739
if (drm_WARN_ON(display->drm, i < 0))
drivers/gpu/drm/i915/display/intel_dp.c
174
if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))
drivers/gpu/drm/i915/display/intel_dp.c
1748
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1751
if (display->platform.g4x && port_clock == 268800)
drivers/gpu/drm/i915/display/intel_dp.c
1775
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1778
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dp.c
1781
if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
drivers/gpu/drm/i915/display/intel_dp.c
1846
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
1872
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
1884
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
1890
return HAS_DOUBLE_BUFFERED_M_N(display) &&
drivers/gpu/drm/i915/display/intel_dp.c
1957
int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
1960
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dp.c
1962
if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/intel_dp.c
2005
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2008
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
drivers/gpu/drm/i915/display/intel_dp.c
2018
static int intel_dp_source_dsc_version_minor(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
2020
return DISPLAY_VER(display) >= 14 ? 2 : 1;
drivers/gpu/drm/i915/display/intel_dp.c
2054
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2077
min(intel_dp_source_dsc_version_minor(display),
drivers/gpu/drm/i915/display/intel_dp.c
2087
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2102
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2113
if (min(intel_dp_source_dsc_version_minor(display),
drivers/gpu/drm/i915/display/intel_dp.c
2266
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2281
if (DISPLAY_VER(display) < 13)
drivers/gpu/drm/i915/display/intel_dp.c
2292
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2295
if (DISPLAY_VER(display) < 14 || !incr)
drivers/gpu/drm/i915/display/intel_dp.c
2312
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2314
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_dp.c
2329
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2331
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_dp.c
2334
drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));
drivers/gpu/drm/i915/display/intel_dp.c
2346
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2352
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_dp.c
2353
drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));
drivers/gpu/drm/i915/display/intel_dp.c
2371
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2405
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2433
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2442
drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
drivers/gpu/drm/i915/display/intel_dp.c
2447
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2517
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2543
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2556
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2566
drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
drivers/gpu/drm/i915/display/intel_dp.c
2629
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2636
joiner_max_bpp = get_max_compressed_bpp_with_joiner(display,
drivers/gpu/drm/i915/display/intel_dp.c
2653
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
267
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2708
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2743
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2766
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
2769
int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
drivers/gpu/drm/i915/display/intel_dp.c
277
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2779
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2800
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2834
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2844
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Invalid pipe bpp range: %d-%d\n",
drivers/gpu/drm/i915/display/intel_dp.c
2870
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
2912
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
292
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
2921
return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
drivers/gpu/drm/i915/display/intel_dp.c
2931
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
2944
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
drivers/gpu/drm/i915/display/intel_dp.c
2968
!intel_dp_dotclk_valid(display,
drivers/gpu/drm/i915/display/intel_dp.c
2977
drm_dbg_kms(display->drm, "DSC required but not available\n");
drivers/gpu/drm/i915/display/intel_dp.c
2984
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3002
if (!intel_dp_dotclk_valid(display,
drivers/gpu/drm/i915/display/intel_dp.c
3010
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
306
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3106
static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_dp.c
3108
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_dp.c
3110
if (DISPLAY_VER(display) < 12 && port == PORT_A)
drivers/gpu/drm/i915/display/intel_dp.c
3120
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp.c
3197
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3345
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
3355
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3368
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
3386
if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder))
drivers/gpu/drm/i915/display/intel_dp.c
339
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
3398
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
341
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3411
if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))
drivers/gpu/drm/i915/display/intel_dp.c
3416
if (display->platform.ironlake || display->platform.sandybridge ||
drivers/gpu/drm/i915/display/intel_dp.c
3417
display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_dp.c
3439
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
3445
if (!intel_dp_port_has_audio(display, encoder->port))
drivers/gpu/drm/i915/display/intel_dp.c
3482
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
3495
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3562
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp.c
3580
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/intel_dp.c
3593
drm_dbg(display->drm, "failed to calculate dsc slice count\n");
drivers/gpu/drm/i915/display/intel_dp.c
3634
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3653
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
3676
if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))
drivers/gpu/drm/i915/display/intel_dp.c
3718
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3786
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp.c
3792
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/intel_dp.c
3802
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
3807
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/intel_dp.c
3850
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
3854
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3863
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
3872
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3881
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp.c
3906
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3953
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp.c
3958
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
3984
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp.c
3989
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4004
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4018
drm_dbg_kms(display->drm, "Failed to read source OUI\n");
drivers/gpu/drm/i915/display/intel_dp.c
4027
drm_dbg_kms(display->drm, "Failed to write source OUI\n");
drivers/gpu/drm/i915/display/intel_dp.c
4041
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4044
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4056
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4093
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4137
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
4147
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4162
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4170
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4182
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4194
drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
drivers/gpu/drm/i915/display/intel_dp.c
4197
drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
drivers/gpu/drm/i915/display/intel_dp.c
4269
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4277
drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
drivers/gpu/drm/i915/display/intel_dp.c
4280
drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
drivers/gpu/drm/i915/display/intel_dp.c
4289
drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
drivers/gpu/drm/i915/display/intel_dp.c
4326
drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
drivers/gpu/drm/i915/display/intel_dp.c
4329
drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
drivers/gpu/drm/i915/display/intel_dp.c
4369
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4384
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4390
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4393
drm_dbg(display->drm, "FRL training Completed\n");
drivers/gpu/drm/i915/display/intel_dp.c
4443
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4493
drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
drivers/gpu/drm/i915/display/intel_dp.c
4499
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4514
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4550
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4557
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4623
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
4646
drm_dbg_kms(display->drm, "Could not read FEC DPCD register\n");
drivers/gpu/drm/i915/display/intel_dp.c
4650
drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
drivers/gpu/drm/i915/display/intel_dp.c
4683
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4686
if (!HAS_DSC(display))
drivers/gpu/drm/i915/display/intel_dp.c
4701
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
4717
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4725
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
4743
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4752
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4761
drm_err(display->drm, "Failed to read MSO cap\n");
drivers/gpu/drm/i915/display/intel_dp.c
4768
drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
drivers/gpu/drm/i915/display/intel_dp.c
4773
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4777
if (!HAS_MSO(display)) {
drivers/gpu/drm/i915/display/intel_dp.c
4778
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4808
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4821
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
4846
intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))
drivers/gpu/drm/i915/display/intel_dp.c
4869
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4873
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
drivers/gpu/drm/i915/display/intel_dp.c
4897
drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
drivers/gpu/drm/i915/display/intel_dp.c
4944
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
4955
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5026
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5028
if (!display->params.enable_dp_mst)
drivers/gpu/drm/i915/display/intel_dp.c
5044
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
505
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5053
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5058
str_yes_no(display->params.enable_dp_mst),
drivers/gpu/drm/i915/display/intel_dp.c
5084
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5089
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5117
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5125
if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) {
drivers/gpu/drm/i915/display/intel_dp.c
518
return DISPLAY_VER(display) >= 12 ||
drivers/gpu/drm/i915/display/intel_dp.c
519
(DISPLAY_VER(display) == 11 &&
drivers/gpu/drm/i915/display/intel_dp.c
5198
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5205
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5282
intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
5299
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5305
drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
drivers/gpu/drm/i915/display/intel_dp.c
5363
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
5377
len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
drivers/gpu/drm/i915/display/intel_dp.c
5390
if (drm_WARN_ON(display->drm, len < 0))
drivers/gpu/drm/i915/display/intel_dp.c
5401
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
5402
intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_dp.c
5407
if (HAS_AS_SDP(display))
drivers/gpu/drm/i915/display/intel_dp.c
5410
u32 val = intel_de_read(display, reg) & ~dip_enable;
drivers/gpu/drm/i915/display/intel_dp.c
5413
if (!enable && HAS_DSC(display))
drivers/gpu/drm/i915/display/intel_dp.c
5423
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_dp.c
5424
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_dp.c
548
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
552
display->platform.pantherlake_wildcatlake)
drivers/gpu/drm/i915/display/intel_dp.c
5545
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
555
if (DISPLAY_VERx100(display) == 1401)
drivers/gpu/drm/i915/display/intel_dp.c
5560
drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
drivers/gpu/drm/i915/display/intel_dp.c
5613
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
5628
drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
drivers/gpu/drm/i915/display/intel_dp.c
5635
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
5652
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5682
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5697
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5737
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5748
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5755
drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
drivers/gpu/drm/i915/display/intel_dp.c
5763
drm_WARN_ON(display->drm, ack[1] & ~INTEL_DP_DEVICE_SERVICE_IRQ_MASK_MST);
drivers/gpu/drm/i915/display/intel_dp.c
5764
drm_WARN_ON(display->drm, ack[3] & ~INTEL_DP_LINK_SERVICE_IRQ_MASK_MST);
drivers/gpu/drm/i915/display/intel_dp.c
5767
drm_dbg_kms(display->drm, "Failed to ack ESI\n");
drivers/gpu/drm/i915/display/intel_dp.c
5786
drm_dbg_kms(display->drm, "DPRX ESI not clearing, device may be stuck\n");
drivers/gpu/drm/i915/display/intel_dp.c
5892
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5905
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_dp.c
5917
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
5919
drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp.c
5924
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5933
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
5940
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp.c
5960
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
5991
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
5999
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
drivers/gpu/drm/i915/display/intel_dp.c
6017
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
6022
ret = intel_modeset_commit_pipes(display, pipe_mask, ctx);
drivers/gpu/drm/i915/display/intel_dp.c
6029
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
6062
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6064
drm_WARN_ON(display->drm, irq_mask & ~INTEL_DP_DEVICE_SERVICE_IRQ_MASK_SST);
drivers/gpu/drm/i915/display/intel_dp.c
6073
drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
drivers/gpu/drm/i915/display/intel_dp.c
6083
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6088
drm_WARN_ON(display->drm, irq_mask & ~(INTEL_DP_LINK_SERVICE_IRQ_MASK_SST |
drivers/gpu/drm/i915/display/intel_dp.c
609
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6103
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
6109
drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
drivers/gpu/drm/i915/display/intel_dp.c
614
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
617
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_dp.c
618
if (display->platform.battlemage) {
drivers/gpu/drm/i915/display/intel_dp.c
6186
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6191
if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
drivers/gpu/drm/i915/display/intel_dp.c
6236
drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
drivers/gpu/drm/i915/display/intel_dp.c
626
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_dp.c
6278
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
6283
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) {
drivers/gpu/drm/i915/display/intel_dp.c
629
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_dp.c
631
else if (display->platform.alderlake_p || display->platform.alderlake_s ||
drivers/gpu/drm/i915/display/intel_dp.c
632
display->platform.dg1 || display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_dp.c
6325
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
634
else if (display->platform.jasperlake || display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_dp.c
6349
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
638
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_dp.c
6382
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6400
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
641
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_dp.c
6411
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6424
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
drivers/gpu/drm/i915/display/intel_dp.c
644
} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
drivers/gpu/drm/i915/display/intel_dp.c
645
display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_dp.c
6501
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
6503
intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
drivers/gpu/drm/i915/display/intel_dp.c
6543
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_dp.c
6551
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_dp.c
6553
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
6554
!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
drivers/gpu/drm/i915/display/intel_dp.c
6556
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_dp.c
6559
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_dp.c
6692
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
6695
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_dp.c
6698
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_dp.c
6713
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_dp.c
6731
mode = drm_dp_downstream_mode(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
6747
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
6756
drm_dbg_kms(display->drm, "registering %s bus for %s\n",
drivers/gpu/drm/i915/display/intel_dp.c
6793
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
6796
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
6846
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp.c
6851
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp.c
6887
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp.c
6893
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_dp.c
6920
drm_WARN_ON(display->drm, transcoders != 0);
drivers/gpu/drm/i915/display/intel_dp.c
6956
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
6986
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_dp.c
7002
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
7008
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_dp.c
7009
if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
drivers/gpu/drm/i915/display/intel_dp.c
7010
display->hotplug.event_bits |= BIT(hpd_pin);
drivers/gpu/drm/i915/display/intel_dp.c
7013
&display->hotplug.oob_hotplug_last_state,
drivers/gpu/drm/i915/display/intel_dp.c
7017
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_dp.c
7020
intel_hpd_schedule_detection(display);
drivers/gpu/drm/i915/display/intel_dp.c
7046
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp.c
7052
intel_display_rpm_suspended(display) ||
drivers/gpu/drm/i915/display/intel_dp.c
7060
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7068
drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
drivers/gpu/drm/i915/display/intel_dp.c
7102
static bool _intel_dp_is_port_edp(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
7110
if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_dp.c
7113
if (DISPLAY_VER(display) < 9 && port == PORT_A)
drivers/gpu/drm/i915/display/intel_dp.c
7119
bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_dp.c
7122
intel_bios_encoder_data_lookup(display, port);
drivers/gpu/drm/i915/display/intel_dp.c
7124
return _intel_dp_is_port_edp(display, devdata, port);
drivers/gpu/drm/i915/display/intel_dp.c
7130
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp.c
7136
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_dp.c
7142
if (display->platform.haswell || display->platform.broadwell ||
drivers/gpu/drm/i915/display/intel_dp.c
7143
DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_dp.c
7153
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
7159
if (!display->platform.g4x && port != PORT_A)
drivers/gpu/drm/i915/display/intel_dp.c
7163
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_dp.c
7165
else if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_dp.c
7179
if (HAS_VRR(display))
drivers/gpu/drm/i915/display/intel_dp.c
7186
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
7194
display->vbt.orientation,
drivers/gpu/drm/i915/display/intel_dp.c
7202
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
7205
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dp.c
7214
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
7229
if (intel_get_lvds_encoder(display)) {
drivers/gpu/drm/i915/display/intel_dp.c
7230
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7231
!(HAS_PCH_IBX(display) || HAS_PCH_CPT(display)));
drivers/gpu/drm/i915/display/intel_dp.c
7232
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7238
intel_bios_init_panel_early(display, &connector->panel,
drivers/gpu/drm/i915/display/intel_dp.c
7242
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7269
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7292
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7304
if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
drivers/gpu/drm/i915/display/intel_dp.c
7307
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7314
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_dp.c
7320
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7335
intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,
drivers/gpu/drm/i915/display/intel_dp.c
7351
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_dp.c
7354
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
736
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
7381
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp.c
7397
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/intel_dp.c
7400
if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {
drivers/gpu/drm/i915/display/intel_dp.c
7406
DISPLAY_VER(display) < 30);
drivers/gpu/drm/i915/display/intel_dp.c
7411
if (drm_WARN_ON(dev, (display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_dp.c
7412
display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_dp.c
742
if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
drivers/gpu/drm/i915/display/intel_dp.c
7422
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dp.c
7428
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
7437
if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_dp.c
7446
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_dp.c
7466
if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
drivers/gpu/drm/i915/display/intel_dp.c
7469
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
747
if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
drivers/gpu/drm/i915/display/intel_dp.c
7481
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_dp.c
7490
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
7493
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_dp.c
7500
void intel_dp_mst_suspend(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
7504
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_dp.c
7507
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_dp.c
7523
void intel_dp_mst_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
7527
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_dp.c
7530
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_dp.c
7553
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp.c
7558
drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
drivers/gpu/drm/i915/display/intel_dp.c
7633
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.c
7639
if (hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
drivers/gpu/drm/i915/display/intel_dp.c
771
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
774
if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
drivers/gpu/drm/i915/display/intel_dp.c
804
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp.c
808
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp.c
824
if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
drivers/gpu/drm/i915/display/intel_dp.c
890
small_joiner_ram_size_bits(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
892
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_dp.c
894
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_dp.c
928
static int bigjoiner_interface_bits(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp.c
930
return DISPLAY_VER(display) >= 14 ? 36 : 24;
drivers/gpu/drm/i915/display/intel_dp.c
933
static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
drivers/gpu/drm/i915/display/intel_dp.c
941
max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
drivers/gpu/drm/i915/display/intel_dp.c
950
static u32 small_joiner_ram_max_bpp(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
957
max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
drivers/gpu/drm/i915/display/intel_dp.c
976
u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.c
980
u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
drivers/gpu/drm/i915/display/intel_dp.c
983
max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
drivers/gpu/drm/i915/display/intel_dp.c
994
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp.h
103
void intel_dp_mst_suspend(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.h
104
void intel_dp_mst_resume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.h
121
bool intel_dp_source_supports_tps3(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.h
122
bool intel_dp_source_supports_tps4(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.h
133
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.h
216
int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.h
230
int intel_dp_max_hdisplay_per_pipe(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp.h
231
bool intel_dp_dotclk_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp.h
96
bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_dp_aux.c
102
return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 2000);
drivers/gpu/drm/i915/display/intel_dp_aux.c
107
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
120
freq = display->cdclk.hw.cdclk;
drivers/gpu/drm/i915/display/intel_dp_aux.c
122
freq = DISPLAY_RUNTIME_INFO(display)->rawclk_freq;
drivers/gpu/drm/i915/display/intel_dp_aux.c
128
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
131
if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(display)) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
194
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
198
if (display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_dp_aux.c
218
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
23
static const char *aux_ch_name(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp_aux.c
244
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dp_aux.c
256
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
26
if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD)
drivers/gpu/drm/i915/display/intel_dp_aux.c
28
else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1)
drivers/gpu/drm/i915/display/intel_dp_aux.c
287
aux_wakeref = intel_display_power_get(display, aux_domain);
drivers/gpu/drm/i915/display/intel_dp_aux.c
300
display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dp_aux.c
327
status = intel_de_read_notrace(display, ch_ctl);
drivers/gpu/drm/i915/display/intel_dp_aux.c
336
const u32 status = intel_de_read(display, ch_ctl);
drivers/gpu/drm/i915/display/intel_dp_aux.c
339
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_dp_aux.c
350
if (drm_WARN_ON(display->drm, send_bytes > 20 || recv_size > 20)) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
366
intel_de_write(display, ch_data[i >> 2],
drivers/gpu/drm/i915/display/intel_dp_aux.c
371
intel_de_write(display, ch_ctl, send_ctl);
drivers/gpu/drm/i915/display/intel_dp_aux.c
376
intel_de_write(display, ch_ctl,
drivers/gpu/drm/i915/display/intel_dp_aux.c
400
drm_err(display->drm, "%s: not done (status 0x%08x)\n",
drivers/gpu/drm/i915/display/intel_dp_aux.c
412
drm_err(display->drm, "%s: receive error (status 0x%08x)\n",
drivers/gpu/drm/i915/display/intel_dp_aux.c
423
drm_dbg_kms(display->drm, "%s: timeout (status 0x%08x)\n",
drivers/gpu/drm/i915/display/intel_dp_aux.c
438
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux.c
449
intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]),
drivers/gpu/drm/i915/display/intel_dp_aux.c
462
intel_display_power_put_async(display, aux_domain, aux_wakeref);
drivers/gpu/drm/i915/display/intel_dp_aux.c
500
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
515
if (drm_WARN_ON(display->drm, txsize > 20))
drivers/gpu/drm/i915/display/intel_dp_aux.c
518
drm_WARN_ON(display->drm, !msg->buffer != !msg->size);
drivers/gpu/drm/i915/display/intel_dp_aux.c
543
if (drm_WARN_ON(display->drm, rxsize > 20))
drivers/gpu/drm/i915/display/intel_dp_aux.c
61
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
68
if (intel_parent_irq_enabled(display)) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
69
#define C (((status = intel_de_read_notrace(display, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
drivers/gpu/drm/i915/display/intel_dp_aux.c
70
done = wait_event_timeout(display->gmbus.wait_queue, C,
drivers/gpu/drm/i915/display/intel_dp_aux.c
75
ret = intel_de_wait_ms(display, ch_ctl,
drivers/gpu/drm/i915/display/intel_dp_aux.c
753
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
764
return XELPDP_DP_AUX_CH_CTL(display, aux_ch);
drivers/gpu/drm/i915/display/intel_dp_aux.c
767
return XELPDP_DP_AUX_CH_CTL(display, AUX_CH_A);
drivers/gpu/drm/i915/display/intel_dp_aux.c
773
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
784
return XELPDP_DP_AUX_CH_DATA(display, aux_ch, index);
drivers/gpu/drm/i915/display/intel_dp_aux.c
787
return XELPDP_DP_AUX_CH_DATA(display, AUX_CH_A, index);
drivers/gpu/drm/i915/display/intel_dp_aux.c
801
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.c
807
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
810
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
813
} else if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
816
} else if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
819
} else if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
827
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_dp_aux.c
829
else if (display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_dp_aux.c
831
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_dp_aux.c
836
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_dp_aux.c
84
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux.c
841
intel_dp->aux.drm_dev = display->drm;
drivers/gpu/drm/i915/display/intel_dp_aux.c
846
aux_ch_name(display, buf, sizeof(buf), aux_ch),
drivers/gpu/drm/i915/display/intel_dp_aux.c
857
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_aux.c
860
if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E)
drivers/gpu/drm/i915/display/intel_dp_aux.c
870
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_aux.c
873
for_each_intel_encoder(display->drm, other) {
drivers/gpu/drm/i915/display/intel_dp_aux.c
889
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_aux.c
910
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux.c
913
aux_ch_name(display, buf, sizeof(buf), aux_ch),
drivers/gpu/drm/i915/display/intel_dp_aux.c
918
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux.c
921
aux_ch_name(display, buf, sizeof(buf), aux_ch), source);
drivers/gpu/drm/i915/display/intel_dp_aux.c
926
void intel_dp_aux_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp_aux.c
928
wake_up_all(&display->gmbus.wait_queue);
drivers/gpu/drm/i915/display/intel_dp_aux.c
93
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_aux.h
21
void intel_dp_aux_irq_handler(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
114
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
127
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
147
if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
150
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
176
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
183
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
202
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
248
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
265
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
275
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
286
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
306
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
318
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
342
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
384
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
399
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
407
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
413
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
421
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
438
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
532
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
549
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
554
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
565
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
605
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
643
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
649
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
658
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
685
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
694
switch (display->params.enable_dpcd_backlight) {
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
102
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
112
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
123
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
132
struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
140
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
152
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
156
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
168
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
174
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
186
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
193
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
205
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
217
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
230
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
240
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
260
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
267
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
279
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
283
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
346
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
355
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
401
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
434
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
518
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
572
drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
585
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
61
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
69
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
701
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
714
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
717
ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
750
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
759
drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
768
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
785
if (intel_de_wait_ms(display, HDCP_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
788
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
800
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
811
if (DISPLAY_VER(display) < 30) {
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
812
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
813
HDCP2_AUTH_STREAM(display, cpu_transcoder, port));
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
815
drm_WARN_ON(display->drm, enable &&
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
824
if (intel_de_wait_ms(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
828
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
833
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
834
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
835
HDCP2_STREAM_STATUS(display, cpu_transcoder, port));
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
837
drm_WARN_ON(display->drm, enable &&
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
85
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
892
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
897
if (!is_hdcp_supported(display, port))
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
96
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1269
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1288
if (!display->hotplug.ignore_long_hpd &&
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1780
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1828
if (display->hotplug.ignore_long_hpd) {
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1870
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1877
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1885
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1941
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1950
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1957
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1968
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1975
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1983
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2043
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2052
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2059
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2070
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2074
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2080
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2089
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2093
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2099
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2108
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2112
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2118
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2126
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2133
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2139
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2150
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2154
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2160
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2168
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
217
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2172
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2178
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2191
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2195
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
2201
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
226
if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_dp_link_training.c
257
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
265
(DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {
drivers/gpu/drm/i915/display/intel_dp_link_training.c
328
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
331
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_dp_link_training.c
341
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
353
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_dp_link_training.c
363
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
375
drm_WARN_ON_ONCE(display->drm,
drivers/gpu/drm/i915/display/intel_dp_link_training.c
385
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
388
DISPLAY_VER(display) >= 10 || display->platform.broxton;
drivers/gpu/drm/i915/display/intel_dp_link_training.c
799
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
812
source_tps4 = intel_dp_source_supports_tps4(display);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
830
source_tps3 = intel_dp_source_supports_tps3(display);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1056
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1075
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream &&
drivers/gpu/drm/i915/display/intel_dp_mst.c
1078
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
1091
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_dp_mst.c
1092
TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
drivers/gpu/drm/i915/display/intel_dp_mst.c
1105
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
1111
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1136
if (DISPLAY_VER(display) < 12 || !last_mst_stream)
drivers/gpu/drm/i915/display/intel_dp_mst.c
121
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1212
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_mst.c
123
drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
1230
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && first_mst_stream &&
drivers/gpu/drm/i915/display/intel_dp_mst.c
1259
if (DISPLAY_VER(display) < 12 || !first_mst_stream)
drivers/gpu/drm/i915/display/intel_dp_mst.c
126
if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0))
drivers/gpu/drm/i915/display/intel_dp_mst.c
1262
if (DISPLAY_VER(display) >= 13 && !first_mst_stream)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1271
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1275
if (!display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1278
if (!IS_DISPLAY_STEP(display, STEP_D0, STEP_FOREVER))
drivers/gpu/drm/i915/display/intel_dp_mst.c
1286
if (intel_display_wa(display, INTEL_DISPLAY_WA_14014143976)) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
1299
intel_de_rmw(display, CHICKEN_MISC_3, clear, set);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1307
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1318
drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1325
intel_de_write(display, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
drivers/gpu/drm/i915/display/intel_dp_mst.c
1327
intel_de_write(display, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
drivers/gpu/drm/i915/display/intel_dp_mst.c
1339
intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0,
drivers/gpu/drm/i915/display/intel_dp_mst.c
134
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1354
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1355
intel_de_rmw(display, CHICKEN_TRANS(display, trans),
drivers/gpu/drm/i915/display/intel_dp_mst.c
136
drm_dbg_kms(display->drm, "active MST streams %d -> %d\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
1361
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
1400
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1408
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_dp_mst.c
146
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1471
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1490
*status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_dp_mst.c
150
if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1577
if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
1587
*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1595
if (!intel_dp_dotclk_valid(display,
drivers/gpu/drm/i915/display/intel_dp_mst.c
1628
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1631
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_dp_mst.c
1637
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_dp_mst.c
1682
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1686
display->drm->mode_config.path_property, 0);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1688
display->drm->mode_config.tile_property, 0);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1729
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1767
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
1780
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1796
ret = drm_connector_dynamic_init(display->drm, &connector->base, &mst_connector_funcs,
drivers/gpu/drm/i915/display/intel_dp_mst.c
1808
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
1823
drm_dbg_kms(display->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
1854
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1868
drm_encoder_init(display->drm, &encoder->base, &mst_stream_encoder_funcs,
drivers/gpu/drm/i915/display/intel_dp_mst.c
1908
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1912
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1920
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_dp_mst.c
1925
if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp))
drivers/gpu/drm/i915/display/intel_dp_mst.c
1928
if (DISPLAY_VER(display) < 12 && port == PORT_A)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1931
if (DISPLAY_VER(display) < 11 && port == PORT_E)
drivers/gpu/drm/i915/display/intel_dp_mst.c
1938
ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst.mgr, display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
1940
INTEL_NUM_PIPES(display), conn_base_id);
drivers/gpu/drm/i915/display/intel_dp_mst.c
2172
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
2186
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
253
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
266
drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) ||
drivers/gpu/drm/i915/display/intel_dp_mst.c
272
drm_WARN_ON(display->drm, min_bpp_x16 != max_bpp_x16);
drivers/gpu/drm/i915/display/intel_dp_mst.c
306
drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (" FXP_Q4_FMT " -> " FXP_Q4_FMT ")\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
311
drm_dbg_kms(display->drm, "Looking for slots in range min bpp " FXP_Q4_FMT " max bpp " FXP_Q4_FMT "\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
317
drm_dbg_kms(display->drm, "Can't get valid DSC slice count\n");
drivers/gpu/drm/i915/display/intel_dp_mst.c
323
drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16);
drivers/gpu/drm/i915/display/intel_dp_mst.c
329
drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16));
drivers/gpu/drm/i915/display/intel_dp_mst.c
333
drm_WARN_ON(display->drm, !is_mst);
drivers/gpu/drm/i915/display/intel_dp_mst.c
394
drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
drivers/gpu/drm/i915/display/intel_dp_mst.c
419
drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);
drivers/gpu/drm/i915/display/intel_dp_mst.c
426
drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
436
drm_dbg_kms(display->drm, "Got %d slots for pipe bpp " FXP_Q4_FMT " dsc %d\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
465
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_mst.c
470
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
524
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_mst.c
533
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
540
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
553
drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate);
drivers/gpu/drm/i915/display/intel_dp_mst.c
563
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_mst.c
604
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_mst.c
616
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
drivers/gpu/drm/i915/display/intel_dp_mst.c
630
!intel_dp_dotclk_valid(display,
drivers/gpu/drm/i915/display/intel_dp_mst.c
639
drm_dbg_kms(display->drm, "DSC required but not available\n");
drivers/gpu/drm/i915/display/intel_dp_mst.c
647
drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
drivers/gpu/drm/i915/display/intel_dp_mst.c
661
drm_WARN(display->drm, intel_dp->force_dsc_bpc,
drivers/gpu/drm/i915/display/intel_dp_mst.c
667
drm_dbg_kms(display->drm, "Trying to find VCPI slots in DSC mode\n");
drivers/gpu/drm/i915/display/intel_dp_mst.c
682
if (!intel_dp_dotclk_valid(display,
drivers/gpu/drm/i915/display/intel_dp_mst.c
704
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_mst.c
752
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_dp_mst.c
776
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_mst.c
782
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_dp_mst.c
836
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_mst.c
844
for_each_intel_crtc_in_pipe_mask(display, crtc, mst_pipe_mask) {
drivers/gpu/drm/i915/display/intel_dp_mst.c
849
if (drm_WARN_ON(display->drm, !crtc_state))
drivers/gpu/drm/i915/display/intel_dp_mst.c
959
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dp_mst.c
967
drm_connector_list_iter_begin(display->drm, &connector_list_iter);
drivers/gpu/drm/i915/display/intel_dp_test.c
115
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
125
drm_dbg_kms(display->drm, "Test pattern read failed\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
134
drm_dbg_kms(display->drm, "H Width read failed\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
141
drm_dbg_kms(display->drm, "V Height read failed\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
148
drm_dbg_kms(display->drm, "TEST MISC read failed\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
177
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
193
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
207
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
223
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
233
drm_dbg_kms(display->drm, "Disable Phy Test Pattern\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
234
intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);
drivers/gpu/drm/i915/display/intel_dp_test.c
235
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_dp_test.c
236
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_dp_test.c
241
drm_dbg_kms(display->drm, "Set D10.2 Phy Test Pattern\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
242
intel_de_write(display, DDI_DP_COMP_CTL(pipe),
drivers/gpu/drm/i915/display/intel_dp_test.c
246
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
248
intel_de_write(display, DDI_DP_COMP_CTL(pipe),
drivers/gpu/drm/i915/display/intel_dp_test.c
253
drm_dbg_kms(display->drm, "Set PRBS7 Phy Test Pattern\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
254
intel_de_write(display, DDI_DP_COMP_CTL(pipe),
drivers/gpu/drm/i915/display/intel_dp_test.c
263
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
266
intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
drivers/gpu/drm/i915/display/intel_dp_test.c
268
intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
drivers/gpu/drm/i915/display/intel_dp_test.c
270
intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
drivers/gpu/drm/i915/display/intel_dp_test.c
271
intel_de_write(display, DDI_DP_COMP_CTL(pipe),
drivers/gpu/drm/i915/display/intel_dp_test.c
281
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
284
intel_de_write(display, DDI_DP_COMP_CTL(pipe),
drivers/gpu/drm/i915/display/intel_dp_test.c
289
if (DISPLAY_VER(display) < 10) {
drivers/gpu/drm/i915/display/intel_dp_test.c
290
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
294
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
296
intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);
drivers/gpu/drm/i915/display/intel_dp_test.c
297
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
drivers/gpu/drm/i915/display/intel_dp_test.c
302
drm_warn(display->drm, "Invalid Phy Test Pattern\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
309
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
316
drm_dbg_kms(display->drm, "failed to get link status\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
337
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
342
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
35
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
355
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
362
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
369
drm_dbg_kms(display->drm, "LINK_TRAINING test requested\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
373
drm_dbg_kms(display->drm, "TEST_PATTERN test requested\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
377
drm_dbg_kms(display->drm, "EDID test requested\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
381
drm_dbg_kms(display->drm, "PHY_PATTERN test requested\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
385
drm_dbg_kms(display->drm, "Invalid test request '%02x'\n",
drivers/gpu/drm/i915/display/intel_dp_test.c
396
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
406
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
413
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp_test.c
433
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
45
drm_dbg_kms(display->drm, "Setting pipe_bpp to %d\n", bpp);
drivers/gpu/drm/i915/display/intel_dp_test.c
453
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dp_test.c
459
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
drivers/gpu/drm/i915/display/intel_dp_test.c
471
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] PHY test\n",
drivers/gpu/drm/i915/display/intel_dp_test.c
474
for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) {
drivers/gpu/drm/i915/display/intel_dp_test.c
479
if (DISPLAY_VER(display) >= 12 &&
drivers/gpu/drm/i915/display/intel_dp_test.c
525
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
530
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
533
drm_kms_helper_hotplug_event(display->drm);
drivers/gpu/drm/i915/display/intel_dp_test.c
536
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_test.c
555
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_dp_test.c
570
drm_dbg_kms(display->drm, "Copied %d bytes from user\n", (unsigned int)len);
drivers/gpu/drm/i915/display/intel_dp_test.c
572
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp_test.c
589
drm_dbg_kms(display->drm, "Got %d for test active\n", val);
drivers/gpu/drm/i915/display/intel_dp_test.c
610
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_dp_test.c
615
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp_test.c
660
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_dp_test.c
665
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp_test.c
714
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_dp_test.c
719
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_dp_test.c
753
void intel_dp_test_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp_test.c
760
display->drm->debugfs_root,
drivers/gpu/drm/i915/display/intel_dp_test.c
761
display,
drivers/gpu/drm/i915/display/intel_dp_test.c
77
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_test.c
89
drm_dbg_kms(display->drm, "Lane count read failed\n");
drivers/gpu/drm/i915/display/intel_dp_test.c
97
drm_dbg_kms(display->drm, "Link Rate read failed\n");
drivers/gpu/drm/i915/display/intel_dp_test.h
21
void intel_dp_test_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
103
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
143
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
149
for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) {
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
156
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
167
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
200
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
208
tunnel = drm_dp_tunnel_detect(display->dp_tunnel_mgr,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
220
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
309
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
311
if (DISPLAY_VER(display) < 35)
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
325
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
332
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
355
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
367
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
408
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
430
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
435
drm_WARN_ON(display->drm, old_tunnel != tunnel);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
454
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
482
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
501
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
507
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
518
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
527
drm_WARN_ON(display->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1));
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
565
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
573
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
644
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
653
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
67
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
73
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
776
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
784
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
840
int intel_dp_tunnel_mgr_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
847
drm_connector_list_iter_begin(display->drm, &connector_list_iter);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
856
tunnel_mgr = drm_dp_tunnel_mgr_create(display->drm, dp_connectors);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
860
display->dp_tunnel_mgr = tunnel_mgr;
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
871
void intel_dp_tunnel_mgr_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
873
drm_dp_tunnel_mgr_destroy(display->dp_tunnel_mgr);
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
874
display->dp_tunnel_mgr = NULL;
drivers/gpu/drm/i915/display/intel_dp_tunnel.c
93
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_dp_tunnel.h
133
intel_dp_tunnel_mgr_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dp_tunnel.h
138
static inline void intel_dp_tunnel_mgr_cleanup(struct intel_display *display) {}
drivers/gpu/drm/i915/display/intel_dp_tunnel.h
57
int intel_dp_tunnel_mgr_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dp_tunnel.h
58
void intel_dp_tunnel_mgr_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1001
vlv_dpio_write(display, phy, VLV_PCS23_DW11(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1004
vlv_dpio_write(display, phy, VLV_PCS01_DW12(ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1012
vlv_dpio_write(display, phy, VLV_PCS23_DW12(ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1023
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1028
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1032
chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1040
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1045
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1049
val = vlv_dpio_read(display, phy, CHV_CMN_DW5_CH0);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1051
vlv_dpio_write(display, phy, CHV_CMN_DW5_CH0, val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1053
val = vlv_dpio_read(display, phy, CHV_CMN_DW1_CH1);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1055
vlv_dpio_write(display, phy, CHV_CMN_DW1_CH1, val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1058
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1077
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1082
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1084
vlv_dpio_write(display, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1085
vlv_dpio_write(display, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1086
vlv_dpio_write(display, phy, VLV_TX_DW2_GRP(ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1088
vlv_dpio_write(display, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1091
vlv_dpio_write(display, phy, VLV_TX_DW4(ch, 3), tx3_demph);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1093
vlv_dpio_write(display, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1094
vlv_dpio_write(display, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1095
vlv_dpio_write(display, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1097
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1103
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1109
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1111
vlv_dpio_write(display, phy, VLV_PCS_DW0_GRP(ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1114
vlv_dpio_write(display, phy, VLV_PCS_DW1_GRP(ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1121
vlv_dpio_write(display, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1122
vlv_dpio_write(display, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1123
vlv_dpio_write(display, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1125
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1131
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1140
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1147
vlv_dpio_write(display, phy, VLV_PCS_DW8_GRP(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1150
vlv_dpio_write(display, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1151
vlv_dpio_write(display, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1153
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1159
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1164
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1165
vlv_dpio_write(display, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1166
vlv_dpio_write(display, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1167
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1173
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1184
dpll_reg = DPLL(display, 0);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1188
dpll_reg = DPLL(display, 0);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1197
if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask, 1000, &val))
drivers/gpu/drm/i915/display/intel_dpio_phy.c
1198
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
225
bxt_get_phy_list(struct intel_display *display, int *count)
drivers/gpu/drm/i915/display/intel_dpio_phy.c
227
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_dpio_phy.c
237
bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.c
241
bxt_get_phy_list(display, &count);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
246
void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
252
phys = bxt_get_phy_list(display, &count);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
271
drm_WARN(display->drm, 1, "PHY not found for PORT %c",
drivers/gpu/drm/i915/display/intel_dpio_phy.c
281
static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
288
old = intel_de_read(display, reg_single);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
290
intel_de_write(display, reg_group, val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
298
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
305
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_dpio_phy.c
308
bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
314
bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
321
intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
331
intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
336
val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
338
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
345
intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
350
bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
355
bool bxt_dpio_phy_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
360
phy_info = bxt_get_phy_info(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
362
if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
drivers/gpu/drm/i915/display/intel_dpio_phy.c
365
if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &
drivers/gpu/drm/i915/display/intel_dpio_phy.c
367
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
373
if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
drivers/gpu/drm/i915/display/intel_dpio_phy.c
374
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
383
static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.c
385
u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
390
static void bxt_phy_wait_grc_done(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
393
if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
drivers/gpu/drm/i915/display/intel_dpio_phy.c
394
drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
397
static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.c
402
phy_info = bxt_get_phy_info(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
404
if (bxt_dpio_phy_is_enabled(display, phy)) {
drivers/gpu/drm/i915/display/intel_dpio_phy.c
407
display->state.bxt_phy_grc = bxt_get_grc(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
409
if (bxt_dpio_phy_verify_state(display, phy)) {
drivers/gpu/drm/i915/display/intel_dpio_phy.c
410
drm_dbg(display->drm, "DDI PHY %d already enabled, "
drivers/gpu/drm/i915/display/intel_dpio_phy.c
415
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
420
intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
430
if (intel_de_wait_ms(display, BXT_PORT_CL1CM_DW0(phy),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
432
drm_err(display->drm, "timeout during PHY%d power on\n",
drivers/gpu/drm/i915/display/intel_dpio_phy.c
436
intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
439
intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
443
intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
447
intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
453
bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
460
val = bxt_get_grc(display, phy_info->rcomp_phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
461
display->state.bxt_phy_grc = val;
drivers/gpu/drm/i915/display/intel_dpio_phy.c
466
intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
467
intel_de_rmw(display, BXT_PORT_REF_DW8(phy),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
474
intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
477
void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.c
481
phy_info = bxt_get_phy_info(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
483
intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
485
intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
488
void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.c
490
const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
494
lockdep_assert_held(&display->power.domains.lock);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
498
was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
505
_bxt_dpio_phy_init(display, rcomp_phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
507
_bxt_dpio_phy_init(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
510
bxt_dpio_phy_uninit(display, rcomp_phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
514
__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
522
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
530
drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
drivers/gpu/drm/i915/display/intel_dpio_phy.c
540
bool bxt_dpio_phy_verify_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
547
phy_info = bxt_get_phy_info(display, phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
550
__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \
drivers/gpu/drm/i915/display/intel_dpio_phy.c
553
if (!bxt_dpio_phy_is_enabled(display, phy))
drivers/gpu/drm/i915/display/intel_dpio_phy.c
577
u32 grc_code = display->state.bxt_phy_grc;
drivers/gpu/drm/i915/display/intel_dpio_phy.c
616
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
622
bxt_port_to_phy_channel(display, port, &phy, &ch);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
629
intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),
drivers/gpu/drm/i915/display/intel_dpio_phy.c
638
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
645
bxt_port_to_phy_channel(display, port, &phy, &ch);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
649
u32 val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpio_phy.c
720
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
727
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
730
val = vlv_dpio_read(display, phy, VLV_PCS01_DW10(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
734
vlv_dpio_write(display, phy, VLV_PCS01_DW10(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
737
val = vlv_dpio_read(display, phy, VLV_PCS23_DW10(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
741
vlv_dpio_write(display, phy, VLV_PCS23_DW10(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
744
val = vlv_dpio_read(display, phy, VLV_PCS01_DW9(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
747
vlv_dpio_write(display, phy, VLV_PCS01_DW9(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
750
val = vlv_dpio_read(display, phy, VLV_PCS23_DW9(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
753
vlv_dpio_write(display, phy, VLV_PCS23_DW9(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
758
val = vlv_dpio_read(display, phy, CHV_TX_DW4(ch, i));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
761
vlv_dpio_write(display, phy, CHV_TX_DW4(ch, i), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
766
val = vlv_dpio_read(display, phy, CHV_TX_DW2(ch, i));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
779
vlv_dpio_write(display, phy, CHV_TX_DW2(ch, i), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
789
val = vlv_dpio_read(display, phy, CHV_TX_DW3(ch, i));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
794
vlv_dpio_write(display, phy, CHV_TX_DW3(ch, i), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
798
val = vlv_dpio_read(display, phy, VLV_PCS01_DW10(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
800
vlv_dpio_write(display, phy, VLV_PCS01_DW10(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
803
val = vlv_dpio_read(display, phy, VLV_PCS23_DW10(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
805
vlv_dpio_write(display, phy, VLV_PCS23_DW10(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
808
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
815
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
821
val = vlv_dpio_read(display, phy, VLV_PCS01_DW0(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
826
vlv_dpio_write(display, phy, VLV_PCS01_DW0(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
829
val = vlv_dpio_read(display, phy, VLV_PCS23_DW0(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
834
vlv_dpio_write(display, phy, VLV_PCS23_DW0(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
837
val = vlv_dpio_read(display, phy, VLV_PCS01_DW1(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
843
vlv_dpio_write(display, phy, VLV_PCS01_DW1(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
846
val = vlv_dpio_read(display, phy, VLV_PCS23_DW1(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
852
vlv_dpio_write(display, phy, VLV_PCS23_DW1(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
860
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
862
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
864
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
870
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
886
!chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
890
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
897
val = vlv_dpio_read(display, phy, CHV_CMN_DW5_CH0);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
903
vlv_dpio_write(display, phy, CHV_CMN_DW5_CH0, val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
905
val = vlv_dpio_read(display, phy, CHV_CMN_DW1_CH1);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
911
vlv_dpio_write(display, phy, CHV_CMN_DW1_CH1, val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
915
val = vlv_dpio_read(display, phy, VLV_PCS01_DW8(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
921
vlv_dpio_write(display, phy, VLV_PCS01_DW8(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
924
val = vlv_dpio_read(display, phy, VLV_PCS23_DW8(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
930
vlv_dpio_write(display, phy, VLV_PCS23_DW8(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
938
val = vlv_dpio_read(display, phy, CHV_CMN_DW19(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
943
vlv_dpio_write(display, phy, CHV_CMN_DW19(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
945
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
951
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
959
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
962
val = vlv_dpio_read(display, phy, VLV_PCS01_DW11(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
964
vlv_dpio_write(display, phy, VLV_PCS01_DW11(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
967
val = vlv_dpio_read(display, phy, VLV_PCS23_DW11(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
969
vlv_dpio_write(display, phy, VLV_PCS23_DW11(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
979
vlv_dpio_write(display, phy, CHV_TX_DW14(ch, i), data);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
994
val = vlv_dpio_read(display, phy, VLV_PCS01_DW11(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.c
996
vlv_dpio_write(display, phy, VLV_PCS01_DW11(ch), val);
drivers/gpu/drm/i915/display/intel_dpio_phy.c
999
val = vlv_dpio_read(display, phy, VLV_PCS23_DW11(ch));
drivers/gpu/drm/i915/display/intel_dpio_phy.h
30
void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
drivers/gpu/drm/i915/display/intel_dpio_phy.h
34
void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.h
35
void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);
drivers/gpu/drm/i915/display/intel_dpio_phy.h
36
bool bxt_dpio_phy_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.h
38
bool bxt_dpio_phy_verify_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.h
78
static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
drivers/gpu/drm/i915/display/intel_dpio_phy.h
86
static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.h
89
static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
drivers/gpu/drm/i915/display/intel_dpio_phy.h
92
static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpio_phy.h
97
static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll.c
1007
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1017
if (display->platform.i945g || display->platform.i945gm ||
drivers/gpu/drm/i915/display/intel_dpll.c
1018
display->platform.g33 || display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_dpll.c
1031
if (display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_dpll.c
1034
} else if (display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_dpll.c
1058
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_dpll.c
1064
intel_panel_use_ssc(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1076
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1079
if (display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_dpll.c
1089
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_dpll.c
1097
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1127
if (display->platform.i830 ||
drivers/gpu/drm/i915/display/intel_dpll.c
1132
intel_panel_use_ssc(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1155
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1162
if (DISPLAY_VER(display) < 11 &&
drivers/gpu/drm/i915/display/intel_dpll.c
1184
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1190
if (DISPLAY_VER(display) < 11 &&
drivers/gpu/drm/i915/display/intel_dpll.c
1217
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1220
((intel_panel_use_ssc(display) && display->vbt.lvds_ssc_freq == 100000) ||
drivers/gpu/drm/i915/display/intel_dpll.c
1221
(HAS_PCH_IBX(display) && intel_is_dual_link_lvds(display))))
drivers/gpu/drm/i915/display/intel_dpll.c
1250
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1284
if (INTEL_NUM_PIPES(display) == 3 &&
drivers/gpu/drm/i915/display/intel_dpll.c
1310
intel_panel_use_ssc(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1334
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1346
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_dpll.c
1347
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
1349
display->vbt.lvds_ssc_freq);
drivers/gpu/drm/i915/display/intel_dpll.c
1350
refclk = display->vbt.lvds_ssc_freq;
drivers/gpu/drm/i915/display/intel_dpll.c
1353
if (intel_is_dual_link_lvds(display)) {
drivers/gpu/drm/i915/display/intel_dpll.c
1510
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1517
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_dpll.c
1518
refclk = display->vbt.lvds_ssc_freq;
drivers/gpu/drm/i915/display/intel_dpll.c
1519
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
1524
if (intel_is_dual_link_lvds(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1559
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1566
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_dpll.c
1567
refclk = display->vbt.lvds_ssc_freq;
drivers/gpu/drm/i915/display/intel_dpll.c
1568
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
1597
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1604
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_dpll.c
1605
refclk = display->vbt.lvds_ssc_freq;
drivers/gpu/drm/i915/display/intel_dpll.c
1606
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
1637
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1644
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_dpll.c
1645
refclk = display->vbt.lvds_ssc_freq;
drivers/gpu/drm/i915/display/intel_dpll.c
1646
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
1725
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1730
drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
drivers/gpu/drm/i915/display/intel_dpll.c
1738
ret = display->dpll.funcs->crtc_compute_clock(state, crtc);
drivers/gpu/drm/i915/display/intel_dpll.c
1740
drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
drivers/gpu/drm/i915/display/intel_dpll.c
1751
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll.c
1756
drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
drivers/gpu/drm/i915/display/intel_dpll.c
1757
drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);
drivers/gpu/drm/i915/display/intel_dpll.c
1762
if (!display->dpll.funcs->crtc_get_dpll)
drivers/gpu/drm/i915/display/intel_dpll.c
1765
ret = display->dpll.funcs->crtc_get_dpll(state, crtc);
drivers/gpu/drm/i915/display/intel_dpll.c
1767
drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
drivers/gpu/drm/i915/display/intel_dpll.c
1776
intel_dpll_init_clock_hook(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll.c
1778
if (HAS_LT_PHY(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1779
display->dpll.funcs = &xe3plpd_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1780
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dpll.c
1781
display->dpll.funcs = &mtl_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1782
else if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_dpll.c
1783
display->dpll.funcs = &dg2_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1784
else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1785
display->dpll.funcs = &hsw_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1786
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1787
display->dpll.funcs = &ilk_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1788
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dpll.c
1789
display->dpll.funcs = &chv_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1790
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_dpll.c
1791
display->dpll.funcs = &vlv_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1792
else if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_dpll.c
1793
display->dpll.funcs = &g4x_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1794
else if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_dpll.c
1795
display->dpll.funcs = &pnv_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1796
else if (DISPLAY_VER(display) != 2)
drivers/gpu/drm/i915/display/intel_dpll.c
1797
display->dpll.funcs = &i9xx_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1799
display->dpll.funcs = &i8xx_dpll_funcs;
drivers/gpu/drm/i915/display/intel_dpll.c
1802
static bool i9xx_has_pps(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll.c
1804
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_dpll.c
1807
return display->platform.pineview || display->platform.mobile;
drivers/gpu/drm/i915/display/intel_dpll.c
1812
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1818
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_dpll.c
1821
if (i9xx_has_pps(display))
drivers/gpu/drm/i915/display/intel_dpll.c
1822
assert_pps_unlocked(display, pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
1824
intel_de_write(display, FP0(pipe), hw_state->fp0);
drivers/gpu/drm/i915/display/intel_dpll.c
1825
intel_de_write(display, FP1(pipe), hw_state->fp1);
drivers/gpu/drm/i915/display/intel_dpll.c
1832
intel_de_write(display, DPLL(display, pipe),
drivers/gpu/drm/i915/display/intel_dpll.c
1834
intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll.c
1837
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
1840
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_dpll.c
1841
intel_de_write(display, DPLL_MD(display, pipe),
drivers/gpu/drm/i915/display/intel_dpll.c
1849
intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll.c
1854
intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll.c
1855
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
1860
static void vlv_pllb_recal_opamp(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll.c
1869
tmp = vlv_dpio_read(display, phy, VLV_PLL_DW17(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
1872
vlv_dpio_write(display, phy, VLV_PLL_DW17(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1874
tmp = vlv_dpio_read(display, phy, VLV_REF_DW11);
drivers/gpu/drm/i915/display/intel_dpll.c
1877
vlv_dpio_write(display, phy, VLV_REF_DW11, tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1879
tmp = vlv_dpio_read(display, phy, VLV_PLL_DW17(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
1881
vlv_dpio_write(display, phy, VLV_PLL_DW17(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1883
tmp = vlv_dpio_read(display, phy, VLV_REF_DW11);
drivers/gpu/drm/i915/display/intel_dpll.c
1886
vlv_dpio_write(display, phy, VLV_REF_DW11, tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1891
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1899
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpll.c
1905
vlv_pllb_recal_opamp(display, phy, ch);
drivers/gpu/drm/i915/display/intel_dpll.c
1908
vlv_dpio_write(display, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
drivers/gpu/drm/i915/display/intel_dpll.c
1911
tmp = vlv_dpio_read(display, phy, VLV_PLL_DW16(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
1913
vlv_dpio_write(display, phy, VLV_PLL_DW16(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1916
vlv_dpio_write(display, phy, VLV_CMN_DW0, 0x610);
drivers/gpu/drm/i915/display/intel_dpll.c
1932
vlv_dpio_write(display, phy, VLV_PLL_DW3(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1935
vlv_dpio_write(display, phy, VLV_PLL_DW3(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
1941
vlv_dpio_write(display, phy, VLV_PLL_DW18(ch), 0x009f0003);
drivers/gpu/drm/i915/display/intel_dpll.c
1943
vlv_dpio_write(display, phy, VLV_PLL_DW18(ch), 0x00d0000f);
drivers/gpu/drm/i915/display/intel_dpll.c
1948
vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df40000);
drivers/gpu/drm/i915/display/intel_dpll.c
1950
vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df70000);
drivers/gpu/drm/i915/display/intel_dpll.c
1954
vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df70000);
drivers/gpu/drm/i915/display/intel_dpll.c
1956
vlv_dpio_write(display, phy, VLV_PLL_DW5(ch), 0x0df40000);
drivers/gpu/drm/i915/display/intel_dpll.c
1959
coreclk = vlv_dpio_read(display, phy, VLV_PLL_DW7(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
1963
vlv_dpio_write(display, phy, VLV_PLL_DW7(ch), coreclk);
drivers/gpu/drm/i915/display/intel_dpll.c
1965
vlv_dpio_write(display, phy, VLV_PLL_DW19(ch), 0x87871000);
drivers/gpu/drm/i915/display/intel_dpll.c
1967
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpll.c
1972
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1977
intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll.c
1978
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
1981
if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
drivers/gpu/drm/i915/display/intel_dpll.c
1982
drm_err(display->drm, "DPLL %d failed to lock\n", pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
1987
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
1992
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_dpll.c
1995
assert_pps_unlocked(display, pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
1998
intel_de_write(display, DPLL(display, pipe),
drivers/gpu/drm/i915/display/intel_dpll.c
2006
intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md);
drivers/gpu/drm/i915/display/intel_dpll.c
2007
intel_de_posting_read(display, DPLL_MD(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
2012
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
2022
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpll.c
2025
vlv_dpio_write(display, phy, CHV_CMN_DW13(ch),
drivers/gpu/drm/i915/display/intel_dpll.c
2032
vlv_dpio_write(display, phy, CHV_PLL_DW0(ch),
drivers/gpu/drm/i915/display/intel_dpll.c
2036
vlv_dpio_write(display, phy, CHV_PLL_DW1(ch),
drivers/gpu/drm/i915/display/intel_dpll.c
2041
vlv_dpio_write(display, phy, CHV_PLL_DW2(ch),
drivers/gpu/drm/i915/display/intel_dpll.c
2045
tmp = vlv_dpio_read(display, phy, CHV_PLL_DW3(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
2050
vlv_dpio_write(display, phy, CHV_PLL_DW3(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
2053
tmp = vlv_dpio_read(display, phy, CHV_PLL_DW9(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
2059
vlv_dpio_write(display, phy, CHV_PLL_DW9(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
2084
vlv_dpio_write(display, phy, CHV_PLL_DW6(ch), loopfilter);
drivers/gpu/drm/i915/display/intel_dpll.c
2086
tmp = vlv_dpio_read(display, phy, CHV_PLL_DW8(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
2089
vlv_dpio_write(display, phy, CHV_PLL_DW8(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
2092
vlv_dpio_write(display, phy, CHV_CMN_DW14(ch),
drivers/gpu/drm/i915/display/intel_dpll.c
2093
vlv_dpio_read(display, phy, CHV_CMN_DW14(ch)) |
drivers/gpu/drm/i915/display/intel_dpll.c
2096
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpll.c
2101
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
2109
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpll.c
2112
tmp = vlv_dpio_read(display, phy, CHV_CMN_DW14(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
2114
vlv_dpio_write(display, phy, CHV_CMN_DW14(ch), tmp);
drivers/gpu/drm/i915/display/intel_dpll.c
2116
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpll.c
2124
intel_de_write(display, DPLL(display, pipe), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll.c
2127
if (intel_de_wait_for_set_ms(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))
drivers/gpu/drm/i915/display/intel_dpll.c
2128
drm_err(display->drm, "PLL %d failed to lock\n", pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2133
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
2138
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_dpll.c
2141
assert_pps_unlocked(display, pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2144
intel_de_write(display, DPLL(display, pipe),
drivers/gpu/drm/i915/display/intel_dpll.c
2159
intel_de_write(display, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
2160
intel_de_write(display, DPLL_MD(display, PIPE_B),
drivers/gpu/drm/i915/display/intel_dpll.c
2162
intel_de_write(display, CBR4_VLV, 0);
drivers/gpu/drm/i915/display/intel_dpll.c
2163
display->state.chv_dpll_md[pipe] = hw_state->dpll_md;
drivers/gpu/drm/i915/display/intel_dpll.c
2169
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
2170
(intel_de_read(display, DPLL(display, PIPE_B)) &
drivers/gpu/drm/i915/display/intel_dpll.c
2173
intel_de_write(display, DPLL_MD(display, pipe),
drivers/gpu/drm/i915/display/intel_dpll.c
2175
intel_de_posting_read(display, DPLL_MD(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
2189
int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_dpll.c
2192
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2204
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_dpll.c
2217
void vlv_disable_pll(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dpll.c
2222
assert_transcoder_disabled(display, (enum transcoder)pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2229
intel_de_write(display, DPLL(display, pipe), val);
drivers/gpu/drm/i915/display/intel_dpll.c
2230
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
2233
void chv_disable_pll(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dpll.c
2240
assert_transcoder_disabled(display, (enum transcoder)pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2247
intel_de_write(display, DPLL(display, pipe), val);
drivers/gpu/drm/i915/display/intel_dpll.c
2248
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
2250
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpll.c
2253
val = vlv_dpio_read(display, phy, CHV_CMN_DW14(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
2255
vlv_dpio_write(display, phy, CHV_CMN_DW14(ch), val);
drivers/gpu/drm/i915/display/intel_dpll.c
2257
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpll.c
2262
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
2267
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_dpll.c
2271
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_dpll.c
2273
intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
drivers/gpu/drm/i915/display/intel_dpll.c
2274
intel_de_posting_read(display, DPLL(display, pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
2286
void vlv_force_pll_off(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dpll.c
2288
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dpll.c
2289
chv_disable_pll(display, pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2291
vlv_disable_pll(display, pipe);
drivers/gpu/drm/i915/display/intel_dpll.c
2295
static void assert_pll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll.c
2300
cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
drivers/gpu/drm/i915/display/intel_dpll.c
2301
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_dpll.c
2306
void assert_pll_enabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dpll.c
2308
assert_pll(display, pipe, true);
drivers/gpu/drm/i915/display/intel_dpll.c
2311
void assert_pll_disabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_dpll.c
2313
assert_pll(display, pipe, false);
drivers/gpu/drm/i915/display/intel_dpll.c
378
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
382
return display->vbt.lvds_ssc_freq;
drivers/gpu/drm/i915/display/intel_dpll.c
383
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_dpll.c
385
else if (DISPLAY_VER(display) != 2)
drivers/gpu/drm/i915/display/intel_dpll.c
394
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpll.c
397
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_dpll.c
401
if (display->platform.cherryview && crtc->pipe != PIPE_A)
drivers/gpu/drm/i915/display/intel_dpll.c
402
tmp = display->state.chv_dpll_md[crtc->pipe];
drivers/gpu/drm/i915/display/intel_dpll.c
404
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll.c
405
DPLL_MD(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
410
hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
412
if (!display->platform.valleyview && !display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_dpll.c
413
hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
414
hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));
drivers/gpu/drm/i915/display/intel_dpll.c
426
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
441
if (display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_dpll.c
449
if (DISPLAY_VER(display) != 2) {
drivers/gpu/drm/i915/display/intel_dpll.c
450
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_dpll.c
467
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll.c
473
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_dpll.c
480
if (display->platform.i85x &&
drivers/gpu/drm/i915/display/intel_dpll.c
481
intel_lvds_port_enabled(display, LVDS, &lvds_pipe) &&
drivers/gpu/drm/i915/display/intel_dpll.c
483
u32 lvds = intel_de_read(display, LVDS);
drivers/gpu/drm/i915/display/intel_dpll.c
518
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
531
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpll.c
532
tmp = vlv_dpio_read(display, phy, VLV_PLL_DW3(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
533
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpll.c
546
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
559
vlv_dpio_get(display);
drivers/gpu/drm/i915/display/intel_dpll.c
560
cmn_dw13 = vlv_dpio_read(display, phy, CHV_CMN_DW13(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
561
pll_dw0 = vlv_dpio_read(display, phy, CHV_PLL_DW0(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
562
pll_dw1 = vlv_dpio_read(display, phy, CHV_PLL_DW1(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
563
pll_dw2 = vlv_dpio_read(display, phy, CHV_PLL_DW2(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
564
pll_dw3 = vlv_dpio_read(display, phy, CHV_PLL_DW3(ch));
drivers/gpu/drm/i915/display/intel_dpll.c
565
vlv_dpio_put(display);
drivers/gpu/drm/i915/display/intel_dpll.c
582
static bool intel_pll_is_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll.c
595
if (!display->platform.pineview &&
drivers/gpu/drm/i915/display/intel_dpll.c
596
!display->platform.valleyview && !display->platform.cherryview &&
drivers/gpu/drm/i915/display/intel_dpll.c
597
!display->platform.broxton && !display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_dpll.c
601
if (!display->platform.valleyview && !display->platform.cherryview &&
drivers/gpu/drm/i915/display/intel_dpll.c
602
!display->platform.broxton && !display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_dpll.c
625
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
633
if (intel_is_dual_link_lvds(display))
drivers/gpu/drm/i915/display/intel_dpll.c
661
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
682
if (!intel_pll_is_valid(display,
drivers/gpu/drm/i915/display/intel_dpll.c
719
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
738
if (!intel_pll_is_valid(display,
drivers/gpu/drm/i915/display/intel_dpll.c
775
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
799
if (!intel_pll_is_valid(display,
drivers/gpu/drm/i915/display/intel_dpll.c
822
static bool vlv_PLL_is_optimal(struct intel_display *display, int target_freq,
drivers/gpu/drm/i915/display/intel_dpll.c
832
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_dpll.c
838
if (drm_WARN_ON_ONCE(display->drm, !target_freq))
drivers/gpu/drm/i915/display/intel_dpll.c
869
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
893
if (!intel_pll_is_valid(display,
drivers/gpu/drm/i915/display/intel_dpll.c
898
if (!vlv_PLL_is_optimal(display, target,
drivers/gpu/drm/i915/display/intel_dpll.c
926
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll.c
961
if (!intel_pll_is_valid(display, limit, &clock))
drivers/gpu/drm/i915/display/intel_dpll.c
964
if (!vlv_PLL_is_optimal(display, target, &clock, best_clock,
drivers/gpu/drm/i915/display/intel_dpll.h
19
void intel_dpll_init_clock_hook(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpll.h
31
int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_dpll.h
33
void vlv_force_pll_off(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dpll.h
36
void chv_disable_pll(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dpll.h
38
void vlv_disable_pll(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dpll.h
49
void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dpll.h
50
void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1015
static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1027
if (display->platform.haswell && !display->platform.haswell_ult) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1028
refclk = display->dpll.ref_clks.nssc;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1038
refclk = display->dpll.ref_clks.ssc;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1060
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1073
crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1095
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1104
drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1113
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1133
pll = intel_get_dpll_by_id(display, pll_id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1141
static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1158
drm_WARN(display->drm, 1, "bad port clock sel\n");
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
117
void (*update_ref_clks)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1193
static int hsw_ddi_spll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1211
drm_WARN(display->drm, 1, "bad spll freq\n");
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
125
intel_atomic_duplicate_dpll_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1261
static void hsw_update_dpll_ref_clks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1263
display->dpll.ref_clks.ssc = 135000;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1265
if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1266
display->dpll.ref_clks.nssc = 24000;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1268
display->dpll.ref_clks.nssc = 135000;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1304
static void hsw_ddi_lcpll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1310
static void hsw_ddi_lcpll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1315
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
132
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1383
static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1389
intel_de_rmw(display, DPLL_CTRL1,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1394
intel_de_posting_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1397
static void skl_ddi_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
140
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1405
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1407
intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1408
intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1409
intel_de_posting_read(display, regs[id].cfgcr1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1410
intel_de_posting_read(display, regs[id].cfgcr2);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1413
intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1415
if (intel_de_wait_for_set_ms(display, DPLL_STATUS, DPLL_LOCK(id), 5))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1416
drm_err(display->drm, "DPLL %d not locked\n", id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1419
static void skl_ddi_dpll0_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1425
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1428
static void skl_ddi_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1435
intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1436
intel_de_posting_read(display, regs[id].ctl);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1439
static void skl_ddi_dpll0_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1444
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1455
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1462
val = intel_de_read(display, regs[id].ctl);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1466
val = intel_de_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
147
intel_atomic_duplicate_dpll_state(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1471
hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1472
hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1477
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1482
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1493
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1501
val = intel_de_read(display, regs[id].ctl);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1502
if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE)))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1505
val = intel_de_read(display, DPLL_CTRL1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1511
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
163
intel_get_dpll_by_id(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
169
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1755
static int skl_ddi_wrpll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1760
int ref_clock = display->dpll.ref_clks.nssc;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1787
drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
179
void assert_dpll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1821
if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1829
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1835
display->dpll.ref_clks.nssc, &wrpll_params);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1859
crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
186
if (drm_WARN(display->drm, !pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
190
cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1903
static int skl_ddi_lcpll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
191
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1931
drm_WARN(display->drm, 1, "Unsupported link rate\n");
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1982
static int skl_ddi_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1993
return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1995
return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1998
static void skl_update_dpll_ref_clks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2001
display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2057
static void bxt_ddi_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2068
bxt_port_to_phy_channel(display, port, &phy, &ch);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
207
enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2071
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2073
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2074
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2077
ret = intel_de_wait_for_set_us(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2081
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2086
intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2090
intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2094
intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2098
intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
210
return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2102
intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2106
intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2110
temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2115
intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2118
intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2121
intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2124
temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2128
intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2131
temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2133
intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2136
intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2139
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2140
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2142
ret = intel_de_wait_for_set_us(display, BXT_PORT_PLL_ENABLE(port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2145
drm_err(display->drm, "PLL %d not locked\n", port);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2147
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2148
temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2150
intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2157
temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2161
intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2164
static void bxt_ddi_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2170
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2171
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2173
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2174
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2177
ret = intel_de_wait_for_clear_us(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2181
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2186
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2198
bxt_port_to_phy_channel(display, port, &phy, &ch);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2200
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2207
val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2211
hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2214
hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2217
hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2220
hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2223
hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2226
hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2229
hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2234
hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2237
hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
224
intel_combo_pll_enable_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2240
hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2249
hw_state->pcsdw12 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2251
if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2252
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2255
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2262
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
227
if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2283
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
229
else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2293
drm_WARN_ON(display->drm, clk_div->m1 != 2);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2301
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2312
chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2314
drm_WARN_ON(display->drm, clk_div->vco == 0 ||
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2321
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2345
drm_err(display->drm, "Invalid VCO\n");
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
237
intel_tc_pll_enable_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2386
static int bxt_ddi_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2402
return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2418
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2428
crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
243
if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2453
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2461
pll = intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2463
drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2474
static void bxt_update_dpll_ref_clks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2476
display->dpll.ref_clks.ssc = 100000;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2477
display->dpll.ref_clks.nssc = 100000;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
249
static void _intel_enable_shared_dpll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
253
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
255
pll->info->funcs->enable(display, pll, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
259
static void _intel_disable_shared_dpll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
262
pll->info->funcs->disable(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2629
ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2631
return ((display->platform.elkhartlake &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2632
IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2633
DISPLAY_VER(display) >= 12) &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2634
display->dpll.ref_clks.nssc == 38400;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
266
intel_display_power_put(display, pll->info->power_domain, pll->wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2726
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2728
display->dpll.ref_clks.nssc == 24000 ?
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2748
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2750
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2751
switch (display->dpll.ref_clks.nssc) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2753
MISSING_CASE(display->dpll.ref_clks.nssc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2764
switch (display->dpll.ref_clks.nssc) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2766
MISSING_CASE(display->dpll.ref_clks.nssc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
277
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2781
static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2789
drm_WARN_ON(display->drm, 1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2794
static int icl_wrpll_ref_clock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2796
int ref_clock = display->dpll.ref_clks.nssc;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2812
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2813
int ref_clock = icl_wrpll_ref_clock(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
283
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2852
static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2857
int ref_clock = icl_wrpll_ref_clock(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
286
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
289
if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
290
drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2903
if (ehl_combo_pll_div_frac_wa_needed(display))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2908
if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2914
static void icl_calc_dpll_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2921
if (ehl_combo_pll_div_frac_wa_needed(display))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2932
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2937
if (display->vbt.override_afc_startup)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2938
hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
295
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
301
drm_WARN_ON(display->drm, !pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
302
assert_dpll_enabled(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3024
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3026
int refclk_khz = display->dpll.ref_clks.nssc;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3036
bool is_dkl = DISPLAY_VER(display) >= 12;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
305
drm_WARN_ON(display->drm, pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
307
drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
309
_intel_enable_shared_dpll(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
312
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3134
if (display->vbt.override_afc_startup) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3135
u8 val = display->vbt.override_afc_startup_val;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3225
static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
323
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3233
ref_clock = display->dpll.ref_clks.nssc;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3235
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
329
if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3340
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
335
mutex_lock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3357
icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
336
if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3362
crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3372
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3380
if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3386
} else if (display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3396
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3401
} else if ((display->platform.jasperlake ||
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3402
display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
341
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3413
dpll_mask &= ~intel_hti_dpll_mask(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3432
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3447
icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
346
assert_dpll_enabled(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3461
crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
347
drm_WARN_ON(display->drm, !pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3520
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3525
enum intel_dpll_id pll_id = mtl_port_to_pll_id(display, encoder->port);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
353
drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
355
_intel_disable_shared_dpll(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
358
mutex_unlock(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3595
static bool mg_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3606
intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3608
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3613
val = intel_de_read(display, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3617
hw_state->mg_refclkin_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
362
intel_dpll_mask_all(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3622
intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3627
intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3634
hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3635
hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3636
hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3637
hw_state->mg_pll_frac_lock = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3639
hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3641
hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3643
intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3645
if (display->dpll.ref_clks.nssc == 38400) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3658
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3662
static bool dkl_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3673
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3678
val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
368
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3686
hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
369
drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3691
intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3699
intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3703
hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3705
if (display->vbt.override_afc_startup)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3709
hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3713
hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3719
hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3724
intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3730
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3734
static bool icl_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3745
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3750
val = intel_de_read(display, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3754
if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3755
hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3756
hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3757
} else if (display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3758
hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3759
hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3760
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3761
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3763
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3765
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3766
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3768
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3770
if (display->vbt.override_afc_startup) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3771
hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3775
if ((display->platform.jasperlake || display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3777
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3779
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3782
hw_state->cfgcr0 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3784
hw_state->cfgcr1 = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3791
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3795
static bool combo_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3799
intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3801
return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3804
static bool icl_tbt_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3808
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3811
static void icl_dpll_write(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3818
if (display->platform.alderlake_s) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3821
} else if (display->platform.dg1) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3824
} else if (display->platform.rocketlake) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3827
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
383
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3832
if ((display->platform.jasperlake || display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
384
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3842
intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3843
intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3844
drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3846
if (display->vbt.override_afc_startup &&
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3848
intel_de_rmw(display, div0_reg,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3850
intel_de_posting_read(display, cfgcr1_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3853
static void icl_mg_pll_write(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3865
intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3868
intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3872
intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3879
intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3880
intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3881
intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3882
intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3884
intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3886
intel_de_rmw(display, MG_PLL_BIAS(tc_port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3889
intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3893
intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3896
static void dkl_pll_write(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3908
val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
391
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3911
intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3913
val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3916
intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3918
val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3924
intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3927
if (display->vbt.override_afc_startup)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3929
intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3932
val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3936
intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3938
val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3944
intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3946
val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3950
intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3952
val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3956
intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3958
intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
396
pll = intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3961
static void icl_pll_power_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3965
intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3971
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_POWER_STATE, 1))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3972
drm_err(display->drm, "PLL %d Power not enabled\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3976
static void icl_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3980
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3983
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3984
drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3987
static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3991
if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4005
val = intel_de_read(display, TRANS_CMTG_CHICKEN);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4006
val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4007
if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4008
drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4011
static void combo_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4016
intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4018
icl_pll_power_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4020
icl_dpll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4028
icl_pll_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4030
adlp_cmtg_clock_gating_wa(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4035
static void icl_tbt_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4041
icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4043
icl_dpll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4051
icl_pll_enable(display, pll, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4056
static void mg_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4061
intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4063
icl_pll_power_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4065
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4066
dkl_pll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4068
icl_mg_pll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4076
icl_pll_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4081
static void icl_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4093
intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4096
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4097
drm_err(display->drm, "PLL %d locked\n", pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
410
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4101
intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4107
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_POWER_STATE, 1))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4108
drm_err(display->drm, "PLL %d Power not disabled\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4112
static void combo_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4115
intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4117
icl_pll_disable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4120
static void icl_tbt_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4123
icl_pll_disable(display, pll, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4126
static void mg_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4129
intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4131
icl_pll_disable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4134
static void icl_update_dpll_ref_clks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4137
display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
422
drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4356
static struct intel_encoder *get_intel_encoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4362
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4363
mtl_id = mtl_port_to_pll_id(display, encoder->port);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4372
static bool mtl_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4376
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4384
static int mtl_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4388
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4390
if (drm_WARN_ON(display->drm, !encoder))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4396
static void mtl_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4400
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4402
if (drm_WARN_ON(display->drm, !encoder))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4408
static void mtl_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4411
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4413
if (drm_WARN_ON(display->drm, !encoder))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4426
static void mtl_tbt_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4432
static void mtl_tbt_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4437
static int mtl_tbt_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
444
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4445
drm_WARN_ON(display->drm, 1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
446
drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
450
drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4574
static bool xe3plpd_pll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4578
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4586
static int xe3plpd_pll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4590
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4592
if (drm_WARN_ON(display->drm, !encoder))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4595
return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4598
static void xe3plpd_pll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4602
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4604
if (drm_WARN_ON(display->drm, !encoder))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4610
static void xe3plpd_pll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4613
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4615
if (drm_WARN_ON(display->drm, !encoder))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4651
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4665
crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4674
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4697
crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4744
void intel_dpll_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4750
mutex_init(&display->dpll.lock);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4752
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4755
else if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4757
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4759
else if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4761
else if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4763
else if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4765
else if (display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4767
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4769
else if (display->platform.jasperlake || display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4771
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4773
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4775
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4777
else if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4779
else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4788
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4789
i >= ARRAY_SIZE(display->dpll.dplls)))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4793
if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4796
display->dpll.dplls[i].info = &dpll_info[i];
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4797
display->dpll.dplls[i].index = i;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4800
display->dpll.mgr = dpll_mgr;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4801
display->dpll.num_dpll = i;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4808
intel_cx0pll_verify_plls(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4809
intel_lt_phy_verify_plls(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
483
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4830
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4831
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4833
if (drm_WARN_ON(display->drm, !dpll_mgr))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
485
drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4863
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4864
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4866
if (drm_WARN_ON(display->drm, !dpll_mgr))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4886
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4887
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
489
drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4915
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4916
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4918
if (drm_WARN_ON(display->drm, !dpll_mgr))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4932
int intel_dpll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4936
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4939
return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4950
bool intel_dpll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4954
return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4957
static void readout_dpll_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4962
pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4965
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4968
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4977
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4982
void intel_dpll_update_ref_clks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4984
if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4985
display->dpll.mgr->update_ref_clks(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4988
void intel_dpll_readout_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4993
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4994
readout_dpll_hw_state(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4997
static void sanitize_dpll_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5003
adlp_cmtg_clock_gating_wa(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5008
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5012
_intel_disable_shared_dpll(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5015
void intel_dpll_sanitize_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5020
intel_cx0_pll_power_save_wa(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5022
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5023
sanitize_dpll_state(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5034
void intel_dpll_dump_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5038
if (display->dpll.mgr) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5039
display->dpll.mgr->dump_hw_state(p, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5058
bool intel_dpll_compare_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5062
if (display->dpll.mgr) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5063
return display->dpll.mgr->compare_hw_state(a, b);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5073
verify_single_dpll_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5083
active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5086
INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5089
INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5092
INTEL_DISPLAY_STATE_WARN(display, pll->on != active,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5098
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5109
INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5113
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5117
INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5122
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5124
if (HAS_LT_PHY(display))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5132
if (INTEL_DISPLAY_STATE_WARN(display, pll_mismatch,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5135
struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5138
intel_dpll_dump_hw_state(display, &p, &dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5140
intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5154
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5161
verify_single_dpll_state(display, new_crtc_state->intel_dpll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5169
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5174
INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->intel_dpll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5184
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5188
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5189
verify_single_dpll_state(display, pll, NULL, NULL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
533
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
541
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
545
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
554
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
559
val = intel_de_read(display, PCH_DPLL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
561
hw_state->fp0 = intel_de_read(display, PCH_FP0(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
562
hw_state->fp1 = intel_de_read(display, PCH_FP1(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
564
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
569
static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
574
val = intel_de_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
577
INTEL_DISPLAY_STATE_WARN(display, !enabled,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
581
static void ibx_pch_dpll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
589
ibx_assert_pch_refclk_enabled(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
591
intel_de_write(display, PCH_FP0(id), hw_state->fp0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
592
intel_de_write(display, PCH_FP1(id), hw_state->fp1);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
594
intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
597
intel_de_posting_read(display, PCH_DPLL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
605
intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
606
intel_de_posting_read(display, PCH_DPLL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
610
static void ibx_pch_dpll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
615
intel_de_write(display, PCH_DPLL(id), 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
616
intel_de_posting_read(display, PCH_DPLL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
631
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
637
if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
640
pll = intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
642
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
711
static void hsw_ddi_wrpll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
718
intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
719
intel_de_posting_read(display, WRPLL_CTL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
723
static void hsw_ddi_spll_enable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
729
intel_de_write(display, SPLL_CTL, hw_state->spll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
73
void (*enable)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
730
intel_de_posting_read(display, SPLL_CTL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
734
static void hsw_ddi_wrpll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
739
intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
740
intel_de_posting_read(display, WRPLL_CTL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
746
if (display->dpll.pch_ssc_use & BIT(id))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
747
intel_init_pch_refclk(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
750
static void hsw_ddi_spll_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
755
intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
756
intel_de_posting_read(display, SPLL_CTL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
762
if (display->dpll.pch_ssc_use & BIT(id))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
763
intel_init_pch_refclk(display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
766
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
775
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
780
val = intel_de_read(display, WRPLL_CTL(id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
783
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
788
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
796
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
801
val = intel_de_read(display, SPLL_CTL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
804
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
82
void (*disable)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
90
bool (*get_hw_state)(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
407
intel_get_dpll_by_id(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
409
void assert_dpll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
430
int intel_dpll_get_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
433
bool intel_dpll_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
439
void intel_dpll_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
440
void intel_dpll_update_ref_clks(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
441
void intel_dpll_readout_hw_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
442
void intel_dpll_sanitize_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
444
void intel_dpll_dump_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
447
bool intel_dpll_compare_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
451
enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_dpt.c
15
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_dpt.c
17
if (DISPLAY_VER(display) == 14) {
drivers/gpu/drm/i915/display/intel_dpt.c
25
intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_dpt.c
27
display->params.enable_dpt ? 0 :
drivers/gpu/drm/i915/display/intel_dpt.c
30
} else if (DISPLAY_VER(display) == 13) {
drivers/gpu/drm/i915/display/intel_dpt.c
31
intel_de_rmw(display, CHICKEN_MISC_2,
drivers/gpu/drm/i915/display/intel_dpt.c
33
display->params.enable_dpt ? 0 :
drivers/gpu/drm/i915/display/intel_dpt.c
48
void intel_dpt_suspend(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpt.c
52
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_dpt.c
55
mutex_lock(&display->drm->mode_config.fb_lock);
drivers/gpu/drm/i915/display/intel_dpt.c
57
drm_for_each_fb(drm_fb, display->drm) {
drivers/gpu/drm/i915/display/intel_dpt.c
61
intel_parent_dpt_suspend(display, fb->dpt);
drivers/gpu/drm/i915/display/intel_dpt.c
64
mutex_unlock(&display->drm->mode_config.fb_lock);
drivers/gpu/drm/i915/display/intel_dpt.c
79
void intel_dpt_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dpt.c
83
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_dpt.c
86
mutex_lock(&display->drm->mode_config.fb_lock);
drivers/gpu/drm/i915/display/intel_dpt.c
87
drm_for_each_fb(drm_fb, display->drm) {
drivers/gpu/drm/i915/display/intel_dpt.c
91
intel_parent_dpt_resume(display, fb->dpt);
drivers/gpu/drm/i915/display/intel_dpt.c
93
mutex_unlock(&display->drm->mode_config.fb_lock);
drivers/gpu/drm/i915/display/intel_dpt.h
13
void intel_dpt_suspend(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dpt.h
14
void intel_dpt_resume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dram.c
104
static unsigned int chv_mem_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
108
vlv_cck_get(display);
drivers/gpu/drm/i915/display/intel_dram.c
109
val = vlv_cck_read(display, CCK_FUSE_REG);
drivers/gpu/drm/i915/display/intel_dram.c
110
vlv_cck_put(display);
drivers/gpu/drm/i915/display/intel_dram.c
120
static unsigned int vlv_mem_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
124
vlv_punit_get(display);
drivers/gpu/drm/i915/display/intel_dram.c
125
val = vlv_punit_read(display, PUNIT_REG_GPU_FREQ_STS);
drivers/gpu/drm/i915/display/intel_dram.c
126
vlv_punit_put(display);
drivers/gpu/drm/i915/display/intel_dram.c
141
unsigned int intel_mem_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
143
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_dram.c
144
return pnv_mem_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
145
else if (DISPLAY_VER(display) == 5)
drivers/gpu/drm/i915/display/intel_dram.c
146
return ilk_mem_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
147
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dram.c
148
return chv_mem_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
149
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_dram.c
150
return vlv_mem_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
155
static unsigned int i9xx_fsb_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
167
fsb = intel_mchbar_read(display, CLKCFG) & CLKCFG_FSB_MASK;
drivers/gpu/drm/i915/display/intel_dram.c
169
if (display->platform.pineview || display->platform.mobile) {
drivers/gpu/drm/i915/display/intel_dram.c
210
static unsigned int ilk_fsb_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
214
fsb = intel_mchbar_read16(display, CSIPLL0) & 0x3ff;
drivers/gpu/drm/i915/display/intel_dram.c
232
drm_dbg_kms(display->drm, "unknown fsb frequency 0x%04x\n", fsb);
drivers/gpu/drm/i915/display/intel_dram.c
237
unsigned int intel_fsb_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
239
if (DISPLAY_VER(display) == 5)
drivers/gpu/drm/i915/display/intel_dram.c
240
return ilk_fsb_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
241
else if (IS_DISPLAY_VER(display, 3, 4))
drivers/gpu/drm/i915/display/intel_dram.c
242
return i9xx_fsb_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
247
static int i915_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
249
dram_info->fsb_freq = intel_fsb_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
251
drm_dbg_kms(display->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq);
drivers/gpu/drm/i915/display/intel_dram.c
253
dram_info->mem_freq = intel_mem_freq(display);
drivers/gpu/drm/i915/display/intel_dram.c
255
drm_dbg_kms(display->drm, "DDR speed: %d kHz\n", dram_info->mem_freq);
drivers/gpu/drm/i915/display/intel_dram.c
257
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_dram.c
258
dram_info->type = pnv_dram_type(display);
drivers/gpu/drm/i915/display/intel_dram.c
394
skl_dram_print_dimm_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dram.c
398
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dram.c
405
skl_dram_get_dimm_l_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dram.c
409
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_dram.c
419
skl_dram_print_dimm_info(display, dimm, channel, 'L');
drivers/gpu/drm/i915/display/intel_dram.c
423
skl_dram_get_dimm_s_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dram.c
427
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_dram.c
437
skl_dram_print_dimm_info(display, dimm, channel, 'S');
drivers/gpu/drm/i915/display/intel_dram.c
441
skl_dram_get_channel_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dram.c
445
skl_dram_get_dimm_l_info(display, &ch->dimm_l, channel, val);
drivers/gpu/drm/i915/display/intel_dram.c
446
skl_dram_get_dimm_s_info(display, &ch->dimm_s, channel, val);
drivers/gpu/drm/i915/display/intel_dram.c
449
drm_dbg_kms(display->drm, "CH%u not populated\n", channel);
drivers/gpu/drm/i915/display/intel_dram.c
463
drm_dbg_kms(display->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n",
drivers/gpu/drm/i915/display/intel_dram.c
479
skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
488
val = intel_mchbar_read(display, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
drivers/gpu/drm/i915/display/intel_dram.c
489
ret = skl_dram_get_channel_info(display, &ch0, 0, val);
drivers/gpu/drm/i915/display/intel_dram.c
493
val = intel_mchbar_read(display, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
drivers/gpu/drm/i915/display/intel_dram.c
494
ret = skl_dram_get_channel_info(display, &ch1, 1, val);
drivers/gpu/drm/i915/display/intel_dram.c
499
drm_info(display->drm, "Number of memory channels is zero\n");
drivers/gpu/drm/i915/display/intel_dram.c
504
drm_info(display->drm, "couldn't get memory rank information\n");
drivers/gpu/drm/i915/display/intel_dram.c
512
drm_dbg_kms(display->drm, "Memory configuration is symmetric? %s\n",
drivers/gpu/drm/i915/display/intel_dram.c
515
drm_dbg_kms(display->drm, "16Gb+ DIMMs: %s\n",
drivers/gpu/drm/i915/display/intel_dram.c
522
skl_get_dram_type(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
526
val = intel_mchbar_read(display, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
drivers/gpu/drm/i915/display/intel_dram.c
544
skl_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
548
dram_info->type = skl_get_dram_type(display);
drivers/gpu/drm/i915/display/intel_dram.c
550
ret = skl_dram_get_channels_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
59
static enum intel_dram_type pnv_dram_type(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
61
return intel_mchbar_read(display, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ?
drivers/gpu/drm/i915/display/intel_dram.c
635
static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
648
val = intel_mchbar_read(display, BXT_D_CR_DRP0_DUNIT(i));
drivers/gpu/drm/i915/display/intel_dram.c
65
static unsigned int pnv_mem_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
657
drm_WARN_ON(display->drm, type != INTEL_DRAM_UNKNOWN &&
drivers/gpu/drm/i915/display/intel_dram.c
661
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dram.c
674
drm_info(display->drm, "couldn't get memory information\n");
drivers/gpu/drm/i915/display/intel_dram.c
681
static int icl_pcode_read_mem_global_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dram.c
687
ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
drivers/gpu/drm/i915/display/intel_dram.c
69
tmp = intel_mchbar_read(display, CLKCFG);
drivers/gpu/drm/i915/display/intel_dram.c
692
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_dram.c
743
static int gen11_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
747
ret = skl_dram_get_channels_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
751
return icl_pcode_read_mem_global_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
754
static int gen12_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
756
return icl_pcode_read_mem_global_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
759
static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
drivers/gpu/drm/i915/display/intel_dram.c
761
u32 val = intel_de_read(display, MTL_MEM_SS_INFO_GLOBAL);
drivers/gpu/drm/i915/display/intel_dram.c
783
drm_WARN_ON(display->drm, !display->platform.dgfx);
drivers/gpu/drm/i915/display/intel_dram.c
787
drm_WARN_ON(display->drm, !display->platform.dgfx);
drivers/gpu/drm/i915/display/intel_dram.c
799
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_dram.c
805
int intel_dram_detect(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
810
if (display->platform.dg2 || !HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_dram.c
813
dram_info = drmm_kzalloc(display->drm, sizeof(*dram_info), GFP_KERNEL);
drivers/gpu/drm/i915/display/intel_dram.c
817
display->dram.info = dram_info;
drivers/gpu/drm/i915/display/intel_dram.c
819
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dram.c
820
ret = xelpdp_get_dram_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
821
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_dram.c
822
ret = gen12_get_dram_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
823
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_dram.c
824
ret = gen11_get_dram_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
825
else if (display->platform.broxton || display->platform.geminilake)
drivers/gpu/drm/i915/display/intel_dram.c
826
ret = bxt_get_dram_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
827
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_dram.c
828
ret = skl_get_dram_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
83
static unsigned int ilk_mem_freq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
830
ret = i915_get_dram_info(display, dram_info);
drivers/gpu/drm/i915/display/intel_dram.c
832
drm_dbg_kms(display->drm, "DRAM type: %s\n",
drivers/gpu/drm/i915/display/intel_dram.c
835
drm_dbg_kms(display->drm, "DRAM channels: %u\n", dram_info->num_channels);
drivers/gpu/drm/i915/display/intel_dram.c
837
drm_dbg_kms(display->drm, "Num QGV points %u\n", dram_info->num_qgv_points);
drivers/gpu/drm/i915/display/intel_dram.c
838
drm_dbg_kms(display->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points);
drivers/gpu/drm/i915/display/intel_dram.c
852
const struct dram_info *intel_dram_info(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dram.c
854
return display->dram.info;
drivers/gpu/drm/i915/display/intel_dram.c
87
ddrpll = intel_mchbar_read16(display, DDRMPLL1);
drivers/gpu/drm/i915/display/intel_dram.c
98
drm_dbg_kms(display->drm, "unknown memory frequency 0x%02x\n",
drivers/gpu/drm/i915/display/intel_dram.h
37
int intel_dram_detect(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dram.h
38
unsigned int intel_fsb_freq(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dram.h
39
unsigned int intel_mem_freq(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dram.h
40
const struct dram_info *intel_dram_info(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_drrs.c
112
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_drrs.c
117
if (intel_cpu_transcoder_has_m2_n2(display, crtc->drrs.cpu_transcoder))
drivers/gpu/drm/i915/display/intel_drrs.c
127
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_drrs.c
129
mod_delayed_work(display->wq.unordered, &crtc->drrs.work, msecs_to_jiffies(1000));
drivers/gpu/drm/i915/display/intel_drrs.c
134
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_drrs.c
140
for_each_intel_crtc_in_pipe_mask(display, crtc,
drivers/gpu/drm/i915/display/intel_drrs.c
224
static void intel_drrs_frontbuffer_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_drrs.c
230
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_drrs.c
272
void intel_drrs_invalidate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_drrs.c
275
intel_drrs_frontbuffer_update(display, frontbuffer_bits, true);
drivers/gpu/drm/i915/display/intel_drrs.c
290
void intel_drrs_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_drrs.c
293
intel_drrs_frontbuffer_update(display, frontbuffer_bits, false);
drivers/gpu/drm/i915/display/intel_drrs.c
314
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_drrs.c
327
str_yes_no(intel_cpu_transcoder_has_drrs(display,
drivers/gpu/drm/i915/display/intel_drrs.c
355
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_drrs.c
377
drm_dbg_kms(display->drm, "Manually %sactivating DRRS\n", val ? "" : "de");
drivers/gpu/drm/i915/display/intel_drrs.c
69
bool intel_cpu_transcoder_has_drrs(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_drrs.c
72
if (HAS_DOUBLE_BUFFERED_M_N(display))
drivers/gpu/drm/i915/display/intel_drrs.c
75
return intel_cpu_transcoder_has_m2_n2(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_drrs.c
82
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_drrs.c
86
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_drrs.c
91
intel_de_rmw(display, TRANSCONF(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_drrs.h
19
bool intel_cpu_transcoder_has_drrs(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_drrs.h
25
void intel_drrs_invalidate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_drrs.h
27
void intel_drrs_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dsb.c
101
return display->parent->dsb->read(dsb->dsb_buf, idx);
drivers/gpu/drm/i915/display/intel_dsb.c
1020
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dsb.c
1026
if (!HAS_DSB(display))
drivers/gpu/drm/i915/display/intel_dsb.c
1029
if (!display->params.enable_dsb)
drivers/gpu/drm/i915/display/intel_dsb.c
1036
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_dsb.c
1041
dsb_buf = dsb_buffer_create(display, size);
drivers/gpu/drm/i915/display/intel_dsb.c
1047
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_dsb.c
106
struct intel_display *display = to_intel_display(dsb->crtc);
drivers/gpu/drm/i915/display/intel_dsb.c
1060
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_dsb.c
1063
drm_info_once(display->drm,
drivers/gpu/drm/i915/display/intel_dsb.c
108
display->parent->dsb->fill(dsb->dsb_buf, idx, val, size);
drivers/gpu/drm/i915/display/intel_dsb.c
1083
void intel_dsb_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dsb.c
1086
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_dsb.c
1089
tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));
drivers/gpu/drm/i915/display/intel_dsb.c
1090
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp);
drivers/gpu/drm/i915/display/intel_dsb.c
1093
spin_lock(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_dsb.c
1106
spin_unlock(&display->drm->event_lock);
drivers/gpu/drm/i915/display/intel_dsb.c
1109
errors = tmp & dsb_error_int_status(display);
drivers/gpu/drm/i915/display/intel_dsb.c
111
static struct intel_dsb_buffer *dsb_buffer_create(struct intel_display *display, size_t size)
drivers/gpu/drm/i915/display/intel_dsb.c
1111
drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n",
drivers/gpu/drm/i915/display/intel_dsb.c
1114
drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n",
drivers/gpu/drm/i915/display/intel_dsb.c
1117
drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n",
drivers/gpu/drm/i915/display/intel_dsb.c
1120
drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n",
drivers/gpu/drm/i915/display/intel_dsb.c
1123
drm_err(display->drm, "[CRTC:%d:%s] DSB %d GOSUB programming error\n",
drivers/gpu/drm/i915/display/intel_dsb.c
113
return display->parent->dsb->create(display->drm, size);
drivers/gpu/drm/i915/display/intel_dsb.c
118
struct intel_display *display = to_intel_display(dsb->crtc);
drivers/gpu/drm/i915/display/intel_dsb.c
120
display->parent->dsb->cleanup(dsb->dsb_buf);
drivers/gpu/drm/i915/display/intel_dsb.c
125
struct intel_display *display = to_intel_display(dsb->crtc);
drivers/gpu/drm/i915/display/intel_dsb.c
127
display->parent->dsb->flush_map(dsb->dsb_buf);
drivers/gpu/drm/i915/display/intel_dsb.c
185
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_dsb.c
188
unsigned int latency = skl_watermark_max_latency(display, 0);
drivers/gpu/drm/i915/display/intel_dsb.c
244
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
247
return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2,
drivers/gpu/drm/i915/display/intel_dsb.c
255
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
257
return !drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dsb.c
264
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
267
drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n",
drivers/gpu/drm/i915/display/intel_dsb.c
270
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dsb.c
276
drm_dbg_kms(display->drm, "}\n");
drivers/gpu/drm/i915/display/intel_dsb.c
279
static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_dsb.c
282
return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
drivers/gpu/drm/i915/display/intel_dsb.c
609
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
613
if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id))
drivers/gpu/drm/i915/display/intel_dsb.c
674
static u32 dsb_error_int_status(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dsb.c
688
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dsb.c
691
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_dsb.c
697
static u32 dsb_error_int_en(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dsb.c
705
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_dsb.c
712
if (0 && DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_dsb.c
815
struct intel_display *display = to_intel_display(state->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
819
if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
drivers/gpu/drm/i915/display/intel_dsb.c
832
dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
drivers/gpu/drm/i915/display/intel_dsb.c
833
dsb_error_int_en(display) | DSB_PROG_INT_EN);
drivers/gpu/drm/i915/display/intel_dsb.c
85
struct intel_display *display = to_intel_display(dsb->crtc);
drivers/gpu/drm/i915/display/intel_dsb.c
87
return display->parent->dsb->ggtt_offset(dsb->dsb_buf);
drivers/gpu/drm/i915/display/intel_dsb.c
92
struct intel_display *display = to_intel_display(dsb->crtc);
drivers/gpu/drm/i915/display/intel_dsb.c
932
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
938
if (is_dsb_busy(display, pipe, dsb->id)) {
drivers/gpu/drm/i915/display/intel_dsb.c
939
drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",
drivers/gpu/drm/i915/display/intel_dsb.c
94
display->parent->dsb->write(dsb->dsb_buf, idx, val);
drivers/gpu/drm/i915/display/intel_dsb.c
944
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
947
intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
950
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
951
dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
drivers/gpu/drm/i915/display/intel_dsb.c
952
dsb_error_int_en(display) | DSB_PROG_INT_EN);
drivers/gpu/drm/i915/display/intel_dsb.c
954
intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), 0);
drivers/gpu/drm/i915/display/intel_dsb.c
956
intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
959
intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
966
struct intel_display *display = to_intel_display(crtc->base.dev);
drivers/gpu/drm/i915/display/intel_dsb.c
971
ret = poll_timeout_us(is_busy = is_dsb_busy(display, pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
977
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
980
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsb.c
983
intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,
drivers/gpu/drm/i915/display/intel_dsb.c
984
intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset,
drivers/gpu/drm/i915/display/intel_dsb.c
985
intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset);
drivers/gpu/drm/i915/display/intel_dsb.c
99
struct intel_display *display = to_intel_display(dsb->crtc);
drivers/gpu/drm/i915/display/intel_dsb.c
996
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0);
drivers/gpu/drm/i915/display/intel_dsb.c
998
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
drivers/gpu/drm/i915/display/intel_dsb.c
999
dsb_error_int_status(display) | DSB_PROG_INT_STATUS);
drivers/gpu/drm/i915/display/intel_dsb.h
74
void intel_dsb_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dsi.c
119
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dsi.c
126
orientation = display->vbt.orientation;
drivers/gpu/drm/i915/display/intel_dsi.c
64
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_dsi.c
66
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_dsi.c
70
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/intel_dsi.c
79
return intel_mode_valid_max_plane_size(display, mode, 1);
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
166
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
176
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
104
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
122
if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port]))
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
127
drm_dbg_kms(display->drm, "no dsi device for port %c\n",
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
140
drm_dbg_kms(display->drm, "DSI packet: Port %c (seq %u), Flags 0x%02x, VC %u, %s, Type 0x%02x, Length %u, Data %*ph\n",
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
180
drm_err(display->drm, "DSI send packet failed with %pe\n", ERR_PTR(ret));
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
182
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
193
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
196
drm_dbg_kms(display->drm, "%d usecs\n", delay);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
207
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
215
gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
218
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
253
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
258
drm_dbg_kms(display->drm, "SC gpio not supported\n");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
262
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
275
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
295
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
301
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
331
static void icl_native_gpio_set_value(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
336
if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2))
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
353
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
354
intel_de_rmw(display, SHOTPLUG_CTL_DDI,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
358
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
364
intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
371
intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
378
intel_de_rmw(display, GPIO(display, index),
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
387
intel_de_rmw(display, GPIO(display, index),
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
399
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
404
bool native = DISPLAY_VER(display) >= 11;
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
425
drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
429
icl_native_gpio_set_value(display, gpio_number, value);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
430
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
432
else if (display->platform.valleyview)
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
434
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
472
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
473
struct acpi_device *adev = ACPI_COMPANION(display->drm->dev);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
493
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
503
drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n",
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
513
drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
531
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
544
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
546
drm_dbg_kms(display->drm, "Skipping SPI element execution\n");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
553
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
569
drm_err(display->drm, "%s failed, error: %d\n", __func__, ret);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
571
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
621
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
626
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
634
drm_WARN_ON(display->drm, *data != seq_id);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
636
drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n",
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
666
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
672
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
678
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
704
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
705
struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
765
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
773
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
821
drm_err(display->drm, "Burst mode target is not set\n");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
838
drm_err(display->drm, "Burst mode freq is less than computed\n");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
902
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
912
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
918
if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) {
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
927
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
930
pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0");
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
932
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
940
intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
942
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
950
devm_gpiod_get(display->drm->dev, "backlight", flags);
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
952
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_dvo.c
133
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_dvo.c
139
tmp = intel_de_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
150
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dvo.c
154
tmp = intel_de_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
164
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dvo.c
170
tmp = intel_de_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
190
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dvo.c
196
intel_de_rmw(display, DVO(port), DVO_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_dvo.c
197
intel_de_posting_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
205
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dvo.c
213
intel_de_rmw(display, DVO(port), 0, DVO_ENABLE);
drivers/gpu/drm/i915/display/intel_dvo.c
214
intel_de_posting_read(display, DVO(port));
drivers/gpu/drm/i915/display/intel_dvo.c
223
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_dvo.c
226
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_dvo.c
230
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_dvo.c
277
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_dvo.c
285
dvo_val = intel_de_read(display, DVO(port)) &
drivers/gpu/drm/i915/display/intel_dvo.c
298
intel_de_write(display, DVO_SRCDIM(port),
drivers/gpu/drm/i915/display/intel_dvo.c
301
intel_de_write(display, DVO(port), dvo_val);
drivers/gpu/drm/i915/display/intel_dvo.c
307
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_dvo.c
311
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_dvo.c
314
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_dvo.c
317
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_dvo.c
325
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_dvo.c
329
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_dvo.c
402
static bool intel_dvo_init_dev(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dvo.c
417
if (intel_gmbus_is_valid_pin(display, dvo->gpio))
drivers/gpu/drm/i915/display/intel_dvo.c
429
i2c = intel_gmbus_get_adapter(display, gpio);
drivers/gpu/drm/i915/display/intel_dvo.c
445
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_dvo.c
446
dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,
drivers/gpu/drm/i915/display/intel_dvo.c
452
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_dvo.c
453
intel_de_write(display, DPLL(display, pipe), dpll[pipe]);
drivers/gpu/drm/i915/display/intel_dvo.c
461
static bool intel_dvo_probe(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_dvo.c
468
if (intel_dvo_init_dev(display, intel_dvo,
drivers/gpu/drm/i915/display/intel_dvo.c
476
void intel_dvo_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_dvo.c
504
if (!intel_dvo_probe(display, intel_dvo)) {
drivers/gpu/drm/i915/display/intel_dvo.c
510
assert_port_valid(display, intel_dvo->dev.port);
drivers/gpu/drm/i915/display/intel_dvo.c
521
drm_encoder_init(display->drm, &encoder->base,
drivers/gpu/drm/i915/display/intel_dvo.c
526
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] detected %s\n",
drivers/gpu/drm/i915/display/intel_dvo.c
535
drm_connector_init_with_ddc(display->drm, &connector->base,
drivers/gpu/drm/i915/display/intel_dvo.c
538
intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));
drivers/gpu/drm/i915/display/intel_dvo.h
12
void intel_dvo_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_dvo.h
14
static inline void intel_dvo_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_encoder.c
100
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_encoder.c
102
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_encoder.c
35
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_encoder.c
37
mod_delayed_work(display->wq.unordered,
drivers/gpu/drm/i915/display/intel_encoder.c
41
void intel_encoder_unblock_all_hpds(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_encoder.c
45
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_encoder.c
48
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_encoder.c
52
void intel_encoder_block_all_hpds(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_encoder.c
56
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_encoder.c
59
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_encoder.c
63
void intel_encoder_suspend_all(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_encoder.c
67
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_encoder.c
74
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_encoder.c
75
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_encoder.c
78
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_encoder.c
80
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_encoder.c
85
void intel_encoder_shutdown_all(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_encoder.c
89
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_encoder.c
96
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_encoder.c
97
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_encoder.h
18
void intel_encoder_suspend_all(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_encoder.h
19
void intel_encoder_shutdown_all(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_encoder.h
21
void intel_encoder_block_all_hpds(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_encoder.h
22
void intel_encoder_unblock_all_hpds(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fb.c
1012
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
1015
drm_WARN_ON(display->drm, new_offset > old_offset);
drivers/gpu/drm/i915/display/intel_fb.c
1021
tile_size = intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
1071
static u32 intel_compute_aligned_offset(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fb.c
1086
tile_size = intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
1130
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fb.c
1137
return intel_compute_aligned_offset(display, x, y, fb, color_plane,
drivers/gpu/drm/i915/display/intel_fb.c
1146
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
1150
alignment = intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
1155
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1167
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1187
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
1221
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1235
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fb.c
1250
if (DISPLAY_VER(display) < 4)
drivers/gpu/drm/i915/display/intel_fb.c
1266
unsigned int alignment = intel_tile_size(display) - 1;
drivers/gpu/drm/i915/display/intel_fb.c
1279
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1281
return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&
drivers/gpu/drm/i915/display/intel_fb.c
1287
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fb.c
1290
return intel_plane_needs_fence(display) ||
drivers/gpu/drm/i915/display/intel_fb.c
1336
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1342
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1363
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1374
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1375
unsigned int tile_size = intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
1378
offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane,
drivers/gpu/drm/i915/display/intel_fb.c
1429
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1432
if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) &&
drivers/gpu/drm/i915/display/intel_fb.c
1462
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1468
return DIV_ROUND_UP(size, intel_tile_size(display));
drivers/gpu/drm/i915/display/intel_fb.c
1471
#define assign_chk_ovf(display, var, val) ({ \
drivers/gpu/drm/i915/display/intel_fb.c
1472
drm_WARN_ON((display)->drm, overflows_type(val, var)); \
drivers/gpu/drm/i915/display/intel_fb.c
1476
#define assign_bfld_chk_ovf(display, var, val) ({ \
drivers/gpu/drm/i915/display/intel_fb.c
1478
drm_WARN_ON((display)->drm, (var) != (val)); \
drivers/gpu/drm/i915/display/intel_fb.c
1487
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1492
unsigned int tile_size = intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
1496
assign_bfld_chk_ovf(display, remap_info->offset, obj_offset);
drivers/gpu/drm/i915/display/intel_fb.c
1501
assign_chk_ovf(display, remap_info->size,
drivers/gpu/drm/i915/display/intel_fb.c
1506
assign_chk_ovf(display, remap_info->src_stride,
drivers/gpu/drm/i915/display/intel_fb.c
1508
assign_chk_ovf(display, remap_info->width,
drivers/gpu/drm/i915/display/intel_fb.c
1510
assign_chk_ovf(display, remap_info->height,
drivers/gpu/drm/i915/display/intel_fb.c
1515
drm_WARN_ON(display->drm, remap_info->linear);
drivers/gpu/drm/i915/display/intel_fb.c
1516
check_array_bounds(display, view->gtt.rotated.plane, color_plane);
drivers/gpu/drm/i915/display/intel_fb.c
1518
assign_chk_ovf(display, remap_info->dst_stride,
drivers/gpu/drm/i915/display/intel_fb.c
1539
drm_WARN_ON(display->drm, !i915_gtt_view_is_remapped(&view->gtt));
drivers/gpu/drm/i915/display/intel_fb.c
1541
check_array_bounds(display, view->gtt.remapped.plane, color_plane);
drivers/gpu/drm/i915/display/intel_fb.c
1575
assign_chk_ovf(display, remap_info->dst_stride, dst_stride);
drivers/gpu/drm/i915/display/intel_fb.c
1633
static void intel_fb_view_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fb.c
1648
struct intel_display *display = to_intel_display(fb->base.dev);
drivers/gpu/drm/i915/display/intel_fb.c
1650
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_fb.c
1659
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
1663
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/intel_fb.c
1671
drm_WARN_ON(display->drm, plane_min_alignment &&
drivers/gpu/drm/i915/display/intel_fb.c
1685
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
1689
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/intel_fb.c
1699
int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb)
drivers/gpu/drm/i915/display/intel_fb.c
1706
unsigned int tile_size = intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
1708
intel_fb_view_init(display, &fb->normal_view,
drivers/gpu/drm/i915/display/intel_fb.c
1711
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1716
intel_fb_view_init(display, &fb->rotated_view,
drivers/gpu/drm/i915/display/intel_fb.c
1719
intel_fb_view_init(display, &fb->remapped_view,
drivers/gpu/drm/i915/display/intel_fb.c
1739
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1746
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1792
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
1837
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fb.c
1846
intel_fb_view_init(display, &plane_state->view,
drivers/gpu/drm/i915/display/intel_fb.c
1856
drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier));
drivers/gpu/drm/i915/display/intel_fb.c
1977
u32 intel_fb_max_stride(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fb.c
1987
if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) ||
drivers/gpu/drm/i915/display/intel_fb.c
1988
intel_fb_modifier_uses_dpt(display, modifier))
drivers/gpu/drm/i915/display/intel_fb.c
1989
return intel_plane_fb_max_stride(display, info, modifier);
drivers/gpu/drm/i915/display/intel_fb.c
1990
else if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/intel_fb.c
1999
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
2003
unsigned int max_stride = intel_plane_fb_max_stride(display,
drivers/gpu/drm/i915/display/intel_fb.c
2013
return intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
2024
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_fb.c
2035
else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) &&
drivers/gpu/drm/i915/display/intel_fb.c
2044
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fb.c
2066
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2110
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
2116
intel_parent_dpt_destroy(display, intel_fb->dpt);
drivers/gpu/drm/i915/display/intel_fb.c
2120
intel_parent_frontbuffer_put(display, intel_fb->frontbuffer);
drivers/gpu/drm/i915/display/intel_fb.c
2131
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_fb.c
2134
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2217
struct intel_display *display = to_intel_display(obj->dev);
drivers/gpu/drm/i915/display/intel_fb.c
2223
intel_fb->panic = intel_parent_panic_alloc(display);
drivers/gpu/drm/i915/display/intel_fb.c
2231
intel_fb->frontbuffer = intel_parent_frontbuffer_get(display, obj);
drivers/gpu/drm/i915/display/intel_fb.c
2241
if (!drm_any_plane_has_format(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2244
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2251
max_stride = intel_fb_max_stride(display, info, mode_cmd->modifier[0]);
drivers/gpu/drm/i915/display/intel_fb.c
2253
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2264
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2271
drm_helper_mode_fill_fb_struct(display->drm, fb, info, mode_cmd);
drivers/gpu/drm/i915/display/intel_fb.c
2277
drm_dbg_kms(display->drm, "bad plane %d handle\n", i);
drivers/gpu/drm/i915/display/intel_fb.c
2284
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2295
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fb.c
2306
ret = intel_fill_fb_info(display, intel_fb);
drivers/gpu/drm/i915/display/intel_fb.c
2318
dpt = intel_parent_dpt_create(display, obj, size);
drivers/gpu/drm/i915/display/intel_fb.c
2320
drm_dbg_kms(display->drm, "failed to create DPT\n");
drivers/gpu/drm/i915/display/intel_fb.c
2328
ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs);
drivers/gpu/drm/i915/display/intel_fb.c
2330
drm_err(display->drm, "framebuffer init failed %d\n", ret);
drivers/gpu/drm/i915/display/intel_fb.c
2338
intel_parent_dpt_destroy(display, intel_fb->dpt);
drivers/gpu/drm/i915/display/intel_fb.c
2342
intel_parent_frontbuffer_put(display, intel_fb->frontbuffer);
drivers/gpu/drm/i915/display/intel_fb.c
2355
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_fb.c
2360
obj = intel_bo_framebuffer_lookup(display, filp, &mode_cmd);
drivers/gpu/drm/i915/display/intel_fb.c
24
#define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
drivers/gpu/drm/i915/display/intel_fb.c
549
static bool plane_has_modifier(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fb.c
553
if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until))
drivers/gpu/drm/i915/display/intel_fb.c
564
intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
drivers/gpu/drm/i915/display/intel_fb.c
568
(DISPLAY_VER(display) < 14 || !display->platform.dgfx))
drivers/gpu/drm/i915/display/intel_fb.c
572
(DISPLAY_VER(display) < 20 || display->platform.dgfx))
drivers/gpu/drm/i915/display/intel_fb.c
587
u64 *intel_fb_plane_get_modifiers(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fb.c
595
if (plane_has_modifier(display, plane_caps, &intel_modifiers[i]))
drivers/gpu/drm/i915/display/intel_fb.c
600
if (drm_WARN_ON(display->drm, !list))
drivers/gpu/drm/i915/display/intel_fb.c
605
if (plane_has_modifier(display, plane_caps, &intel_modifiers[i]))
drivers/gpu/drm/i915/display/intel_fb.c
761
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
765
else if (DISPLAY_VER(display) < 11 &&
drivers/gpu/drm/i915/display/intel_fb.c
772
unsigned int intel_tile_size(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fb.c
774
return DISPLAY_VER(display) == 2 ? 2048 : 4096;
drivers/gpu/drm/i915/display/intel_fb.c
780
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
785
return intel_tile_size(display);
drivers/gpu/drm/i915/display/intel_fb.c
787
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_fb.c
817
if (HAS_128B_Y_TILING(display))
drivers/gpu/drm/i915/display/intel_fb.c
848
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
850
return intel_tile_size(display) /
drivers/gpu/drm/i915/display/intel_fb.c
893
bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier)
drivers/gpu/drm/i915/display/intel_fb.c
895
return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR;
drivers/gpu/drm/i915/display/intel_fb.c
900
struct intel_display *display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/intel_fb.c
902
return display->params.enable_dpt &&
drivers/gpu/drm/i915/display/intel_fb.c
903
intel_fb_modifier_uses_dpt(display, fb->modifier);
drivers/gpu/drm/i915/display/intel_fb.h
119
bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier);
drivers/gpu/drm/i915/display/intel_fb.h
46
u64 *intel_fb_plane_get_modifiers(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fb.h
63
unsigned int intel_tile_size(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fb.h
87
int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb);
drivers/gpu/drm/i915/display/intel_fbc.c
1003
static int fbc_sys_cache_limit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
1005
if (DISPLAY_VER(display) == 35)
drivers/gpu/drm/i915/display/intel_fbc.c
1013
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
1014
struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
drivers/gpu/drm/i915/display/intel_fbc.c
1018
if (!HAS_FBC_SYS_CACHE(display))
drivers/gpu/drm/i915/display/intel_fbc.c
1021
range = fbc_sys_cache_limit(display) / (64 * 1024);
drivers/gpu/drm/i915/display/intel_fbc.c
1023
offset = intel_parent_stolen_node_offset(display, fbc->compressed_fb) / (4 * 1024);
drivers/gpu/drm/i915/display/intel_fbc.c
1031
fbc_sys_cache_update_config(display, cfg, fbc->id);
drivers/gpu/drm/i915/display/intel_fbc.c
1037
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
1042
if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb))
drivers/gpu/drm/i915/display/intel_fbc.c
1043
intel_parent_stolen_remove_node(display, fbc->compressed_llb);
drivers/gpu/drm/i915/display/intel_fbc.c
1044
if (intel_parent_stolen_node_allocated(display, fbc->compressed_fb))
drivers/gpu/drm/i915/display/intel_fbc.c
1045
intel_parent_stolen_remove_node(display, fbc->compressed_fb);
drivers/gpu/drm/i915/display/intel_fbc.c
1048
void intel_fbc_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
1053
for_each_intel_fbc(display, fbc, fbc_id) {
drivers/gpu/drm/i915/display/intel_fbc.c
1058
intel_parent_stolen_node_free(display, fbc->compressed_fb);
drivers/gpu/drm/i915/display/intel_fbc.c
1059
intel_parent_stolen_node_free(display, fbc->compressed_llb);
drivers/gpu/drm/i915/display/intel_fbc.c
1064
mutex_lock(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
1065
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
1066
display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE);
drivers/gpu/drm/i915/display/intel_fbc.c
1067
mutex_unlock(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
1113
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1115
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_fbc.c
1117
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_fbc.c
1119
else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
1121
else if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/intel_fbc.c
1129
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1139
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_fbc.c
1149
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1158
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
1219
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1221
if (HAS_PIXEL_NORMALIZER(display) &&
drivers/gpu/drm/i915/display/intel_fbc.c
1230
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1232
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/intel_fbc.c
1234
else if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_fbc.c
1236
else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
1266
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1268
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_fbc.c
1270
else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
1276
static void intel_fbc_max_surface_size(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
1279
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/intel_fbc.c
1282
} else if (DISPLAY_VER(display) >= 10) {
drivers/gpu/drm/i915/display/intel_fbc.c
1285
} else if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/intel_fbc.c
1288
} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_fbc.c
129
static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fbc.c
1305
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1308
intel_fbc_max_surface_size(display, &max_w, &max_h);
drivers/gpu/drm/i915/display/intel_fbc.c
131
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_fbc.c
1318
static void intel_fbc_max_plane_size(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
1321
if (DISPLAY_VER(display) >= 10) {
drivers/gpu/drm/i915/display/intel_fbc.c
1324
} else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_fbc.c
1327
} else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_fbc.c
1338
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1341
intel_fbc_max_plane_size(display, &max_w, &max_h);
drivers/gpu/drm/i915/display/intel_fbc.c
136
if (drm_WARN_ON(display->drm, !primary))
drivers/gpu/drm/i915/display/intel_fbc.c
1363
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1365
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_fbc.c
1383
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
1385
drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0);
drivers/gpu/drm/i915/display/intel_fbc.c
1387
intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
1409
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_fbc.c
1412
if (!HAS_FBC_DIRTY_RECT(display))
drivers/gpu/drm/i915/display/intel_fbc.c
1443
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_fbc.c
1461
drm_WARN_ON(display->drm, plane_state->fence_id >= 0 &&
drivers/gpu/drm/i915/display/intel_fbc.c
1462
!intel_fbc_has_fences(display));
drivers/gpu/drm/i915/display/intel_fbc.c
1473
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1487
return DISPLAY_VER(display) >= 9 || plane_state->fence_id >= 0;
drivers/gpu/drm/i915/display/intel_fbc.c
1492
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1498
intel_parent_stolen_node_size(display, fbc->compressed_fb);
drivers/gpu/drm/i915/display/intel_fbc.c
1538
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_fbc.c
1545
if (!HAS_FBC_DIRTY_RECT(display))
drivers/gpu/drm/i915/display/intel_fbc.c
1566
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1569
if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_fbc.c
1579
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_fbc.c
1590
if (!intel_parent_stolen_initialized(display)) {
drivers/gpu/drm/i915/display/intel_fbc.c
1595
if (intel_parent_vgpu_active(display)) {
drivers/gpu/drm/i915/display/intel_fbc.c
1600
if (!display->params.enable_fbc) {
drivers/gpu/drm/i915/display/intel_fbc.c
1610
if (intel_display_wa(display, INTEL_DISPLAY_WA_16023588340)) {
drivers/gpu/drm/i915/display/intel_fbc.c
1620
if (intel_display_wa(display, INTEL_DISPLAY_WA_15018326506)) {
drivers/gpu/drm/i915/display/intel_fbc.c
1626
if (intel_display_vtd_active(display) &&
drivers/gpu/drm/i915/display/intel_fbc.c
1627
(display->platform.skylake || display->platform.broxton)) {
drivers/gpu/drm/i915/display/intel_fbc.c
1656
if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) {
drivers/gpu/drm/i915/display/intel_fbc.c
1662
if ((IS_DISPLAY_VER(display, 12, 13) ||
drivers/gpu/drm/i915/display/intel_fbc.c
1663
IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) &&
drivers/gpu/drm/i915/display/intel_fbc.c
1689
if (DISPLAY_VER(display) < 20 &&
drivers/gpu/drm/i915/display/intel_fbc.c
1711
if (IS_DISPLAY_VER(display, 9, 12) &&
drivers/gpu/drm/i915/display/intel_fbc.c
1718
if (IS_DISPLAY_VER(display, 9, 12) &&
drivers/gpu/drm/i915/display/intel_fbc.c
172
static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
1725
if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) {
drivers/gpu/drm/i915/display/intel_fbc.c
1737
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_fbc.c
1751
if (min_cdclk > display->cdclk.max_cdclk_freq)
drivers/gpu/drm/i915/display/intel_fbc.c
1806
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_fbc.c
1832
if (fbc->activated && DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_fbc.c
186
if (intel_display_wa(display, INTEL_DISPLAY_WA_16011863758))
drivers/gpu/drm/i915/display/intel_fbc.c
1866
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
1870
drm_WARN_ON(display->drm, fbc->active);
drivers/gpu/drm/i915/display/intel_fbc.c
1872
drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_fbc.c
1882
if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_fbc.c
1950
void intel_fbc_invalidate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
1957
for_each_intel_fbc(display, fbc, fbc_id)
drivers/gpu/drm/i915/display/intel_fbc.c
1989
void intel_fbc_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
1996
for_each_intel_fbc(display, fbc, fbc_id)
drivers/gpu/drm/i915/display/intel_fbc.c
200
static unsigned int _intel_fbc_cfb_stride(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
2021
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_fbc.c
2040
drm_WARN_ON(display->drm, fbc->active);
drivers/gpu/drm/i915/display/intel_fbc.c
2062
drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_fbc.c
2068
if (HAS_FBC_DIRTY_RECT(display))
drivers/gpu/drm/i915/display/intel_fbc.c
2085
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fbc.c
2088
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/intel_fbc.c
209
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_fbc.c
210
return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width));
drivers/gpu/drm/i915/display/intel_fbc.c
2133
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
2141
drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n");
drivers/gpu/drm/i915/display/intel_fbc.c
2146
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));
drivers/gpu/drm/i915/display/intel_fbc.c
2154
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
2161
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
217
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
2177
void intel_fbc_reset_underrun(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
2182
for_each_intel_fbc(display, fbc, fbc_id)
drivers/gpu/drm/i915/display/intel_fbc.c
2188
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
2201
queue_work(display->wq.unordered, &fbc->underrun_work);
drivers/gpu/drm/i915/display/intel_fbc.c
2218
void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
222
return _intel_fbc_cfb_stride(display, cpp, width, stride);
drivers/gpu/drm/i915/display/intel_fbc.c
2223
for_each_intel_fbc(display, fbc, fbc_id)
drivers/gpu/drm/i915/display/intel_fbc.c
2237
void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
2240
struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_fbc.c
2246
val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
drivers/gpu/drm/i915/display/intel_fbc.c
2250
intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
drivers/gpu/drm/i915/display/intel_fbc.c
2253
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
2267
static int intel_sanitize_fbc_option(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
2269
if (display->params.enable_fbc >= 0)
drivers/gpu/drm/i915/display/intel_fbc.c
2270
return !!display->params.enable_fbc;
drivers/gpu/drm/i915/display/intel_fbc.c
2272
if (!HAS_FBC(display))
drivers/gpu/drm/i915/display/intel_fbc.c
2275
if (display->platform.broadwell || DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_fbc.c
2286
static struct intel_fbc *intel_fbc_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
2295
fbc->compressed_fb = intel_parent_stolen_node_alloc(display);
drivers/gpu/drm/i915/display/intel_fbc.c
2298
fbc->compressed_llb = intel_parent_stolen_node_alloc(display);
drivers/gpu/drm/i915/display/intel_fbc.c
230
static unsigned int intel_fbc_max_cfb_height(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
2303
fbc->display = display;
drivers/gpu/drm/i915/display/intel_fbc.c
2307
if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/intel_fbc.c
2309
else if (DISPLAY_VER(display) == 6)
drivers/gpu/drm/i915/display/intel_fbc.c
2311
else if (DISPLAY_VER(display) == 5)
drivers/gpu/drm/i915/display/intel_fbc.c
2313
else if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
2315
else if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/intel_fbc.c
232
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_fbc.c
2323
intel_parent_stolen_node_free(display, fbc->compressed_llb);
drivers/gpu/drm/i915/display/intel_fbc.c
2324
intel_parent_stolen_node_free(display, fbc->compressed_fb);
drivers/gpu/drm/i915/display/intel_fbc.c
2336
void intel_fbc_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
234
else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
2340
display->params.enable_fbc = intel_sanitize_fbc_option(display);
drivers/gpu/drm/i915/display/intel_fbc.c
2341
drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n",
drivers/gpu/drm/i915/display/intel_fbc.c
2342
display->params.enable_fbc);
drivers/gpu/drm/i915/display/intel_fbc.c
2344
for_each_fbc_id(display, fbc_id)
drivers/gpu/drm/i915/display/intel_fbc.c
2345
display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
drivers/gpu/drm/i915/display/intel_fbc.c
2347
mutex_init(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
2348
display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
drivers/gpu/drm/i915/display/intel_fbc.c
2359
void intel_fbc_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
2364
for_each_intel_fbc(display, fbc, fbc_id) {
drivers/gpu/drm/i915/display/intel_fbc.c
2370
mutex_lock(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
2371
fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);
drivers/gpu/drm/i915/display/intel_fbc.c
2372
mutex_unlock(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
2378
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
2382
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_fbc.c
2384
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_fbc.c
2392
mutex_lock(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
2394
str_yes_no(display->fbc.sys_cache.id == fbc->id));
drivers/gpu/drm/i915/display/intel_fbc.c
2395
mutex_unlock(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
240
static unsigned int _intel_fbc_cfb_size(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.c
2400
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/intel_fbc.c
2414
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_fbc.c
2416
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_fbc.c
243
return min(height, intel_fbc_max_cfb_height(display)) * stride;
drivers/gpu/drm/i915/display/intel_fbc.c
2473
void intel_fbc_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
2477
fbc = display->fbc.instances[INTEL_FBC_A];
drivers/gpu/drm/i915/display/intel_fbc.c
2479
intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
drivers/gpu/drm/i915/display/intel_fbc.c
248
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
251
return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state));
drivers/gpu/drm/i915/display/intel_fbc.c
256
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_fbc.c
271
(DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) ||
drivers/gpu/drm/i915/display/intel_fbc.c
272
display->platform.battlemage)
drivers/gpu/drm/i915/display/intel_fbc.c
278
static bool intel_fbc_has_fences(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
280
return intel_parent_has_fenced_regions(display);
drivers/gpu/drm/i915/display/intel_fbc.c
285
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
293
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_fbc.c
302
if (display->platform.i945gm)
drivers/gpu/drm/i915/display/intel_fbc.c
327
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
331
fbc_ctl = intel_de_read(display, FBC_CONTROL);
drivers/gpu/drm/i915/display/intel_fbc.c
336
intel_de_write(display, FBC_CONTROL, fbc_ctl);
drivers/gpu/drm/i915/display/intel_fbc.c
339
if (intel_de_wait_for_clear_ms(display, FBC_STATUS,
drivers/gpu/drm/i915/display/intel_fbc.c
341
drm_dbg_kms(display->drm, "FBC idle timed out\n");
drivers/gpu/drm/i915/display/intel_fbc.c
348
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
354
intel_de_write(display, FBC_TAG(i), 0);
drivers/gpu/drm/i915/display/intel_fbc.c
356
if (DISPLAY_VER(display) == 4) {
drivers/gpu/drm/i915/display/intel_fbc.c
357
intel_de_write(display, FBC_CONTROL2,
drivers/gpu/drm/i915/display/intel_fbc.c
359
intel_de_write(display, FBC_FENCE_OFF,
drivers/gpu/drm/i915/display/intel_fbc.c
363
intel_de_write(display, FBC_CONTROL,
drivers/gpu/drm/i915/display/intel_fbc.c
369
return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;
drivers/gpu/drm/i915/display/intel_fbc.c
374
return intel_de_read(fbc->display, FBC_STATUS) &
drivers/gpu/drm/i915/display/intel_fbc.c
380
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
384
intel_de_write_fw(display, DSPADDR(display, i9xx_plane),
drivers/gpu/drm/i915/display/intel_fbc.c
385
intel_de_read_fw(display, DSPADDR(display, i9xx_plane)));
drivers/gpu/drm/i915/display/intel_fbc.c
390
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
392
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
393
range_end_overflows_t(u64, intel_parent_stolen_area_address(display),
drivers/gpu/drm/i915/display/intel_fbc.c
394
intel_parent_stolen_node_offset(display, fbc->compressed_fb),
drivers/gpu/drm/i915/display/intel_fbc.c
396
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
397
range_end_overflows_t(u64, intel_parent_stolen_area_address(display),
drivers/gpu/drm/i915/display/intel_fbc.c
398
intel_parent_stolen_node_offset(display, fbc->compressed_llb),
drivers/gpu/drm/i915/display/intel_fbc.c
400
intel_de_write(display, FBC_CFB_BASE,
drivers/gpu/drm/i915/display/intel_fbc.c
401
intel_parent_stolen_node_address(display, fbc->compressed_fb));
drivers/gpu/drm/i915/display/intel_fbc.c
402
intel_de_write(display, FBC_LL_BASE,
drivers/gpu/drm/i915/display/intel_fbc.c
403
intel_parent_stolen_node_address(display, fbc->compressed_llb));
drivers/gpu/drm/i915/display/intel_fbc.c
417
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
421
intel_de_write_fw(display, DSPSURF(display, i9xx_plane),
drivers/gpu/drm/i915/display/intel_fbc.c
422
intel_de_read_fw(display, DSPSURF(display, i9xx_plane)));
drivers/gpu/drm/i915/display/intel_fbc.c
451
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
458
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
464
if (DISPLAY_VER(display) < 6)
drivers/gpu/drm/i915/display/intel_fbc.c
473
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
476
intel_de_write(display, DPFC_FENCE_YOFF,
drivers/gpu/drm/i915/display/intel_fbc.c
479
intel_de_write(display, DPFC_CONTROL,
drivers/gpu/drm/i915/display/intel_fbc.c
485
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
489
dpfc_ctl = intel_de_read(display, DPFC_CONTROL);
drivers/gpu/drm/i915/display/intel_fbc.c
492
intel_de_write(display, DPFC_CONTROL, dpfc_ctl);
drivers/gpu/drm/i915/display/intel_fbc.c
498
return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;
drivers/gpu/drm/i915/display/intel_fbc.c
503
return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
drivers/gpu/drm/i915/display/intel_fbc.c
508
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
510
intel_de_write(display, DPFC_CB_BASE,
drivers/gpu/drm/i915/display/intel_fbc.c
511
intel_parent_stolen_node_offset(display, fbc->compressed_fb));
drivers/gpu/drm/i915/display/intel_fbc.c
525
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
528
intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
531
intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
538
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
540
if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_fbc.c
541
intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS,
drivers/gpu/drm/i915/display/intel_fbc.c
543
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_fbc.c
544
intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
551
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
554
if (HAS_FBC_DIRTY_RECT(display))
drivers/gpu/drm/i915/display/intel_fbc.c
555
intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
drivers/gpu/drm/i915/display/intel_fbc.c
558
dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
drivers/gpu/drm/i915/display/intel_fbc.c
561
intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
drivers/gpu/drm/i915/display/intel_fbc.c
567
return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
drivers/gpu/drm/i915/display/intel_fbc.c
572
return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
drivers/gpu/drm/i915/display/intel_fbc.c
577
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
579
intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
580
intel_parent_stolen_node_offset(display, fbc->compressed_fb));
drivers/gpu/drm/i915/display/intel_fbc.c
594
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
601
intel_de_write(display, SNB_DPFC_CTL_SA, ctl);
drivers/gpu/drm/i915/display/intel_fbc.c
602
intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
drivers/gpu/drm/i915/display/intel_fbc.c
614
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
616
intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
drivers/gpu/drm/i915/display/intel_fbc.c
617
intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id));
drivers/gpu/drm/i915/display/intel_fbc.c
631
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
639
intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val);
drivers/gpu/drm/i915/display/intel_fbc.c
644
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
653
intel_de_rmw(display, CHICKEN_MISC_4,
drivers/gpu/drm/i915/display/intel_fbc.c
660
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
666
if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_fbc.c
669
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_fbc.c
683
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
686
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_fbc.c
688
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_fbc.c
691
if (intel_fbc_has_fences(display))
drivers/gpu/drm/i915/display/intel_fbc.c
696
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_fbc.c
697
intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
drivers/gpu/drm/i915/display/intel_fbc.c
699
if (HAS_FBC_DIRTY_RECT(display))
drivers/gpu/drm/i915/display/intel_fbc.c
700
intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
703
intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
709
return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
drivers/gpu/drm/i915/display/intel_fbc.c
715
intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
760
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
763
drm_WARN_ON(display->drm, fbc->flip_pending);
drivers/gpu/drm/i915/display/intel_fbc.c
772
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
777
if (fbc->active && !intel_fbc_has_fences(display))
drivers/gpu/drm/i915/display/intel_fbc.c
783
drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));
drivers/gpu/drm/i915/display/intel_fbc.c
801
static u64 intel_fbc_cfb_base_max(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
803
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
809
static u64 intel_fbc_stolen_end(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
811
u64 end = intel_fbc_cfb_base_max(display);
drivers/gpu/drm/i915/display/intel_fbc.c
819
if (display->platform.broadwell ||
drivers/gpu/drm/i915/display/intel_fbc.c
820
(DISPLAY_VER(display) == 9 && !display->platform.broxton)) {
drivers/gpu/drm/i915/display/intel_fbc.c
821
u64 stolen_area_size = intel_parent_stolen_area_size(display);
drivers/gpu/drm/i915/display/intel_fbc.c
828
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
844
static int intel_fbc_max_limit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbc.c
847
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_fbc.c
860
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
861
u64 end = intel_fbc_stolen_end(display);
drivers/gpu/drm/i915/display/intel_fbc.c
867
ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb,
drivers/gpu/drm/i915/display/intel_fbc.c
872
for (; limit <= intel_fbc_max_limit(display); limit <<= 1) {
drivers/gpu/drm/i915/display/intel_fbc.c
873
ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb,
drivers/gpu/drm/i915/display/intel_fbc.c
885
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
888
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
889
intel_parent_stolen_node_allocated(display, fbc->compressed_fb));
drivers/gpu/drm/i915/display/intel_fbc.c
890
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
891
intel_parent_stolen_node_allocated(display, fbc->compressed_llb));
drivers/gpu/drm/i915/display/intel_fbc.c
893
if (DISPLAY_VER(display) < 5 && !display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_fbc.c
894
ret = intel_parent_stolen_insert_node(display, fbc->compressed_llb, 4096, 4096);
drivers/gpu/drm/i915/display/intel_fbc.c
903
drm_info_once(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
908
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
910
intel_parent_stolen_node_size(display, fbc->compressed_fb), fbc->limit);
drivers/gpu/drm/i915/display/intel_fbc.c
914
if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb))
drivers/gpu/drm/i915/display/intel_fbc.c
915
intel_parent_stolen_remove_node(display, fbc->compressed_llb);
drivers/gpu/drm/i915/display/intel_fbc.c
917
if (intel_parent_stolen_initialized(display))
drivers/gpu/drm/i915/display/intel_fbc.c
918
drm_info_once(display->drm,
drivers/gpu/drm/i915/display/intel_fbc.c
930
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
932
if (display->platform.skylake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_fbc.c
937
intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
941
if (display->platform.skylake || display->platform.kabylake ||
drivers/gpu/drm/i915/display/intel_fbc.c
942
display->platform.coffeelake || display->platform.cometlake) {
drivers/gpu/drm/i915/display/intel_fbc.c
947
intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
95
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_fbc.c
952
if (intel_display_wa(display, INTEL_DISPLAY_WA_1409120013))
drivers/gpu/drm/i915/display/intel_fbc.c
953
intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
960
if (intel_display_wa(display, INTEL_DISPLAY_WA_22014263786))
drivers/gpu/drm/i915/display/intel_fbc.c
961
intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
drivers/gpu/drm/i915/display/intel_fbc.c
965
if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_fbc.c
969
static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg,
drivers/gpu/drm/i915/display/intel_fbc.c
972
if (!HAS_FBC_SYS_CACHE(display))
drivers/gpu/drm/i915/display/intel_fbc.c
975
lockdep_assert_held(&display->fbc.sys_cache.lock);
drivers/gpu/drm/i915/display/intel_fbc.c
982
if (!intel_display_wa(display, INTEL_DISPLAY_WA_14025769978))
drivers/gpu/drm/i915/display/intel_fbc.c
986
intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
drivers/gpu/drm/i915/display/intel_fbc.c
988
display->fbc.sys_cache.id = id;
drivers/gpu/drm/i915/display/intel_fbc.c
993
struct intel_display *display = fbc->display;
drivers/gpu/drm/i915/display/intel_fbc.c
994
struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
drivers/gpu/drm/i915/display/intel_fbc.c
999
fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);
drivers/gpu/drm/i915/display/intel_fbc.h
37
void intel_fbc_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbc.h
38
void intel_fbc_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbc.h
39
void intel_fbc_sanitize(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbc.h
43
void intel_fbc_invalidate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.h
46
void intel_fbc_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.h
49
void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbc.h
50
void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbc.h
52
void intel_fbc_reset_underrun(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbc.h
54
void intel_fbc_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbdev.c
135
struct intel_display *display = to_intel_display(fb_helper->client.dev);
drivers/gpu/drm/i915/display/intel_fbdev.c
145
intel_parent_fb_pin_ggtt_unpin(display, ifbdev->vma, -1);
drivers/gpu/drm/i915/display/intel_fbdev.c
208
static void intel_fbdev_fill_mode_cmd(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbdev.c
220
mode_cmd->pitches[0] = intel_bo_fbdev_pitch_align(display, mode_cmd->width * DIV_ROUND_UP(sizes->surface_bpp, 8));
drivers/gpu/drm/i915/display/intel_fbdev.c
227
__intel_fbdev_fb_alloc(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbdev.c
235
intel_fbdev_fill_mode_cmd(display, sizes, &mode_cmd);
drivers/gpu/drm/i915/display/intel_fbdev.c
240
obj = intel_bo_fbdev_create(display, size);
drivers/gpu/drm/i915/display/intel_fbdev.c
247
drm_get_format_info(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
268
struct intel_display *display = to_intel_display(helper->dev);
drivers/gpu/drm/i915/display/intel_fbdev.c
285
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
294
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_fbdev.c
296
if (!fb || drm_WARN_ON(display->drm, !intel_fb_bo(&fb->base))) {
drivers/gpu/drm/i915/display/intel_fbdev.c
297
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
300
fb = __intel_fbdev_fb_alloc(display, sizes);
drivers/gpu/drm/i915/display/intel_fbdev.c
306
drm_dbg_kms(display->drm, "re-using BIOS fb\n");
drivers/gpu/drm/i915/display/intel_fbdev.c
323
pin_params.needs_low_address = intel_plane_needs_low_address(display);
drivers/gpu/drm/i915/display/intel_fbdev.c
325
ret = intel_parent_fb_pin_ggtt_pin(display, obj, &pin_params,
drivers/gpu/drm/i915/display/intel_fbdev.c
339
drm_fb_helper_fill_info(info, display->drm->fb_helper, sizes);
drivers/gpu/drm/i915/display/intel_fbdev.c
350
drm_dbg_kms(display->drm, "allocated %dx%d fb\n", fb->base.width, fb->base.height);
drivers/gpu/drm/i915/display/intel_fbdev.c
354
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_fbdev.c
359
intel_parent_fb_pin_ggtt_unpin(display, vma, -1);
drivers/gpu/drm/i915/display/intel_fbdev.c
361
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_fbdev.c
375
static bool intel_fbdev_init_bios(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fbdev.c
383
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_fbdev.c
393
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
400
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
407
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
416
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
422
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_fbdev.c
430
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
436
drm_dbg_kms(display->drm, "checking [PLANE:%d:%s] for BIOS fb\n",
drivers/gpu/drm/i915/display/intel_fbdev.c
447
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
458
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
467
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
475
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
482
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fbdev.c
492
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_fbdev.c
503
drm_WARN(display->drm, !plane_state->uapi.fb,
drivers/gpu/drm/i915/display/intel_fbdev.c
509
drm_dbg_kms(display->drm, "using BIOS fb for initial console\n");
drivers/gpu/drm/i915/display/intel_fbdev.c
534
void intel_fbdev_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbdev.c
539
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_fbdev.c
542
ifbdev = drmm_kzalloc(display->drm, sizeof(*ifbdev), GFP_KERNEL);
drivers/gpu/drm/i915/display/intel_fbdev.c
546
display->fbdev.fbdev = ifbdev;
drivers/gpu/drm/i915/display/intel_fbdev.c
547
if (intel_fbdev_init_bios(display, ifbdev))
drivers/gpu/drm/i915/display/intel_fbdev.c
552
drm_client_setup_with_color_mode(display->drm, preferred_bpp);
drivers/gpu/drm/i915/display/intel_fbdev.c
563
void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map)
drivers/gpu/drm/i915/display/intel_fbdev.c
565
struct intel_fbdev *fbdev = display->fbdev.fbdev;
drivers/gpu/drm/i915/display/intel_fbdev.c
567
intel_parent_fb_pin_get_map(display, fbdev->vma, map);
drivers/gpu/drm/i915/display/intel_fbdev.c
68
struct intel_display *display = to_intel_display(fb_helper->client.dev);
drivers/gpu/drm/i915/display/intel_fbdev.c
70
return display->fbdev.fbdev;
drivers/gpu/drm/i915/display/intel_fbdev.h
23
void intel_fbdev_setup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fbdev.h
25
void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map);
drivers/gpu/drm/i915/display/intel_fbdev.h
29
static inline void intel_fbdev_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fbdev.h
36
static inline void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map)
drivers/gpu/drm/i915/display/intel_fdi.c
100
static void assert_fdi_rx_pll(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fdi.c
1004
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1007
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
drivers/gpu/drm/i915/display/intel_fdi.c
1008
intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
1010
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1014
intel_de_rmw(display, reg, 0, FDI_PCDCLK);
drivers/gpu/drm/i915/display/intel_fdi.c
1015
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1020
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1022
intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
1024
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1031
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
1035
intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
1038
intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
1039
intel_de_posting_read(display, FDI_TX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
1043
intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
1044
intel_de_posting_read(display, FDI_RX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
105
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
1050
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
1056
intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
1057
intel_de_posting_read(display, FDI_TX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
106
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_fdi.c
1060
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1062
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
drivers/gpu/drm/i915/display/intel_fdi.c
1063
intel_de_write(display, reg, temp & ~FDI_RX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
1065
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1069
if (HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/intel_fdi.c
1070
intel_de_write(display, FDI_RX_CHICKEN(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
1074
intel_de_rmw(display, FDI_TX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
1078
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1079
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_fdi.c
1088
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
drivers/gpu/drm/i915/display/intel_fdi.c
1089
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
1091
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
1108
intel_fdi_init_hook(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fdi.c
111
void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
1110
if (display->platform.ironlake) {
drivers/gpu/drm/i915/display/intel_fdi.c
1111
display->fdi.funcs = &ilk_funcs;
drivers/gpu/drm/i915/display/intel_fdi.c
1112
} else if (display->platform.sandybridge) {
drivers/gpu/drm/i915/display/intel_fdi.c
1113
display->fdi.funcs = &gen6_funcs;
drivers/gpu/drm/i915/display/intel_fdi.c
1114
} else if (display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_fdi.c
1116
display->fdi.funcs = &ivb_funcs;
drivers/gpu/drm/i915/display/intel_fdi.c
113
assert_fdi_rx_pll(display, pipe, true);
drivers/gpu/drm/i915/display/intel_fdi.c
116
void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
118
assert_fdi_rx_pll(display, pipe, false);
drivers/gpu/drm/i915/display/intel_fdi.c
124
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
126
display->fdi.funcs->fdi_link_train(crtc, crtc_state);
drivers/gpu/drm/i915/display/intel_fdi.c
142
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_fdi.c
147
if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3)
drivers/gpu/drm/i915/display/intel_fdi.c
150
crtc = intel_crtc_for_pipe(display, PIPE_C);
drivers/gpu/drm/i915/display/intel_fdi.c
162
crtc = intel_crtc_for_pipe(display, PIPE_B);
drivers/gpu/drm/i915/display/intel_fdi.c
185
static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_fdi.c
195
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
199
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
205
if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_fdi.c
207
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
216
if (INTEL_NUM_PIPES(display) == 2)
drivers/gpu/drm/i915/display/intel_fdi.c
227
other_crtc = intel_crtc_for_pipe(display, PIPE_C);
drivers/gpu/drm/i915/display/intel_fdi.c
234
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
242
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
248
other_crtc = intel_crtc_for_pipe(display, PIPE_B);
drivers/gpu/drm/i915/display/intel_fdi.c
255
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
269
void intel_fdi_pll_freq_update(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fdi.c
271
if (display->platform.ironlake) {
drivers/gpu/drm/i915/display/intel_fdi.c
274
fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
drivers/gpu/drm/i915/display/intel_fdi.c
276
display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000;
drivers/gpu/drm/i915/display/intel_fdi.c
277
} else if (display->platform.sandybridge || display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_fdi.c
278
display->fdi.pll_freq = 270000;
drivers/gpu/drm/i915/display/intel_fdi.c
283
drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq);
drivers/gpu/drm/i915/display/intel_fdi.c
286
int intel_fdi_link_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fdi.c
289
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_fdi.c
29
static void assert_fdi_tx(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fdi.c
292
return display->fdi.pll_freq;
drivers/gpu/drm/i915/display/intel_fdi.c
298
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
309
link_bw = intel_fdi_link_freq(display, pipe_config);
drivers/gpu/drm/i915/display/intel_fdi.c
332
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
336
ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,
drivers/gpu/drm/i915/display/intel_fdi.c
34
if (HAS_DDI(display)) {
drivers/gpu/drm/i915/display/intel_fdi.c
388
static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/intel_fdi.c
392
temp = intel_de_read(display, SOUTH_CHICKEN1);
drivers/gpu/drm/i915/display/intel_fdi.c
396
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
397
intel_de_read(display, FDI_RX_CTL(PIPE_B)) &
drivers/gpu/drm/i915/display/intel_fdi.c
399
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
400
intel_de_read(display, FDI_RX_CTL(PIPE_C)) &
drivers/gpu/drm/i915/display/intel_fdi.c
407
drm_dbg_kms(display->drm, "%sabling fdi C rx\n",
drivers/gpu/drm/i915/display/intel_fdi.c
409
intel_de_write(display, SOUTH_CHICKEN1, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
410
intel_de_posting_read(display, SOUTH_CHICKEN1);
drivers/gpu/drm/i915/display/intel_fdi.c
415
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_fdi.c
42
cur_state = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_fdi.c
423
cpt_set_fdi_bc_bifurcation(display, false);
drivers/gpu/drm/i915/display/intel_fdi.c
425
cpt_set_fdi_bc_bifurcation(display, true);
drivers/gpu/drm/i915/display/intel_fdi.c
429
cpt_set_fdi_bc_bifurcation(display, true);
drivers/gpu/drm/i915/display/intel_fdi.c
43
TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
439
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
446
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
447
if (display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_fdi.c
45
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
454
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
457
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
458
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_fdi.c
465
intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
468
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
47
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_fdi.c
472
if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_fdi.c
473
intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
480
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
489
intel_de_write(display, FDI_RX_TUSIZE1(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
490
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
drivers/gpu/drm/i915/display/intel_fdi.c
493
assert_transcoder_enabled(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_fdi.c
498
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
501
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
502
intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
507
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
512
intel_de_write(display, reg, temp | FDI_TX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
515
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
518
intel_de_write(display, reg, temp | FDI_RX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
52
void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
520
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
524
intel_de_write(display, FDI_RX_CHICKEN(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
526
intel_de_write(display, FDI_RX_CHICKEN(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
531
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
532
drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
drivers/gpu/drm/i915/display/intel_fdi.c
535
drm_dbg_kms(display->drm, "FDI train 1 done.\n");
drivers/gpu/drm/i915/display/intel_fdi.c
536
intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK);
drivers/gpu/drm/i915/display/intel_fdi.c
54
assert_fdi_tx(display, pipe, true);
drivers/gpu/drm/i915/display/intel_fdi.c
541
drm_err(display->drm, "FDI train 1 fail!\n");
drivers/gpu/drm/i915/display/intel_fdi.c
544
intel_de_rmw(display, FDI_TX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
546
intel_de_rmw(display, FDI_RX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
548
intel_de_posting_read(display, FDI_RX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
553
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
554
drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
drivers/gpu/drm/i915/display/intel_fdi.c
557
intel_de_write(display, reg,
drivers/gpu/drm/i915/display/intel_fdi.c
559
drm_dbg_kms(display->drm, "FDI train 2 done.\n");
drivers/gpu/drm/i915/display/intel_fdi.c
564
drm_err(display->drm, "FDI train 2 fail!\n");
drivers/gpu/drm/i915/display/intel_fdi.c
566
drm_dbg_kms(display->drm, "FDI train done\n");
drivers/gpu/drm/i915/display/intel_fdi.c
57
void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
581
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
59
assert_fdi_tx(display, pipe, false);
drivers/gpu/drm/i915/display/intel_fdi.c
590
intel_de_write(display, FDI_RX_TUSIZE1(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
591
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
drivers/gpu/drm/i915/display/intel_fdi.c
596
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
599
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
601
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
606
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
614
intel_de_write(display, reg, temp | FDI_TX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
616
intel_de_write(display, FDI_RX_MISC(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
62
static void assert_fdi_rx(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fdi.c
620
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
621
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_fdi.c
628
intel_de_write(display, reg, temp | FDI_RX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
630
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
634
intel_de_rmw(display, FDI_TX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
636
intel_de_posting_read(display, FDI_TX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
641
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
642
drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
drivers/gpu/drm/i915/display/intel_fdi.c
644
intel_de_write(display, reg,
drivers/gpu/drm/i915/display/intel_fdi.c
646
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
656
drm_err(display->drm, "FDI train 1 fail!\n");
drivers/gpu/drm/i915/display/intel_fdi.c
660
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
663
if (display->platform.sandybridge) {
drivers/gpu/drm/i915/display/intel_fdi.c
668
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
67
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
671
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
672
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_fdi.c
679
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
68
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/intel_fdi.c
681
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
685
intel_de_rmw(display, FDI_TX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
687
intel_de_posting_read(display, FDI_TX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
692
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
693
drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
drivers/gpu/drm/i915/display/intel_fdi.c
695
intel_de_write(display, reg,
drivers/gpu/drm/i915/display/intel_fdi.c
697
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
707
drm_err(display->drm, "FDI train 2 fail!\n");
drivers/gpu/drm/i915/display/intel_fdi.c
709
drm_dbg_kms(display->drm, "FDI train done.\n");
drivers/gpu/drm/i915/display/intel_fdi.c
716
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fdi.c
727
intel_de_write(display, FDI_RX_TUSIZE1(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
728
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
drivers/gpu/drm/i915/display/intel_fdi.c
73
void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
733
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
736
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
738
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
741
drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n",
drivers/gpu/drm/i915/display/intel_fdi.c
742
intel_de_read(display, FDI_RX_IIR(pipe)));
drivers/gpu/drm/i915/display/intel_fdi.c
748
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
75
assert_fdi_rx(display, pipe, true);
drivers/gpu/drm/i915/display/intel_fdi.c
751
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
754
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
758
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_fdi.c
762
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
769
intel_de_write(display, reg, temp | FDI_TX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
771
intel_de_write(display, FDI_RX_MISC(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
775
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
778
intel_de_write(display, reg, temp | FDI_RX_ENABLE);
drivers/gpu/drm/i915/display/intel_fdi.c
78
void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
780
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
785
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
786
drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
drivers/gpu/drm/i915/display/intel_fdi.c
789
(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {
drivers/gpu/drm/i915/display/intel_fdi.c
790
intel_de_write(display, reg,
drivers/gpu/drm/i915/display/intel_fdi.c
792
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
80
assert_fdi_rx(display, pipe, false);
drivers/gpu/drm/i915/display/intel_fdi.c
800
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
806
intel_de_rmw(display, FDI_TX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
809
intel_de_rmw(display, FDI_RX_CTL(pipe),
drivers/gpu/drm/i915/display/intel_fdi.c
812
intel_de_posting_read(display, FDI_RX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_fdi.c
817
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_fdi.c
818
drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);
drivers/gpu/drm/i915/display/intel_fdi.c
821
(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {
drivers/gpu/drm/i915/display/intel_fdi.c
822
intel_de_write(display, reg,
drivers/gpu/drm/i915/display/intel_fdi.c
824
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
83
void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_fdi.c
832
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
837
drm_dbg_kms(display->drm, "FDI train done.\n");
drivers/gpu/drm/i915/display/intel_fdi.c
851
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_fdi.c
866
intel_de_write(display, FDI_RX_MISC(PIPE_A),
drivers/gpu/drm/i915/display/intel_fdi.c
873
rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
drivers/gpu/drm/i915/display/intel_fdi.c
876
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
drivers/gpu/drm/i915/display/intel_fdi.c
877
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
drivers/gpu/drm/i915/display/intel_fdi.c
88
if (display->platform.ironlake)
drivers/gpu/drm/i915/display/intel_fdi.c
882
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
drivers/gpu/drm/i915/display/intel_fdi.c
885
drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);
drivers/gpu/drm/i915/display/intel_fdi.c
892
intel_de_write(display, DP_TP_CTL(PORT_E),
drivers/gpu/drm/i915/display/intel_fdi.c
902
intel_de_write(display, DDI_BUF_CTL(PORT_E),
drivers/gpu/drm/i915/display/intel_fdi.c
906
intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
drivers/gpu/drm/i915/display/intel_fdi.c
911
intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
drivers/gpu/drm/i915/display/intel_fdi.c
915
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
drivers/gpu/drm/i915/display/intel_fdi.c
916
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
drivers/gpu/drm/i915/display/intel_fdi.c
92
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_fdi.c
922
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
drivers/gpu/drm/i915/display/intel_fdi.c
924
intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
drivers/gpu/drm/i915/display/intel_fdi.c
929
temp = intel_de_read(display, DP_TP_STATUS(PORT_E));
drivers/gpu/drm/i915/display/intel_fdi.c
931
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_fdi.c
941
drm_err(display->drm, "FDI link training failed!\n");
drivers/gpu/drm/i915/display/intel_fdi.c
946
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
drivers/gpu/drm/i915/display/intel_fdi.c
947
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
drivers/gpu/drm/i915/display/intel_fdi.c
949
intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
95
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;
drivers/gpu/drm/i915/display/intel_fdi.c
950
intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
drivers/gpu/drm/i915/display/intel_fdi.c
953
intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
954
intel_de_posting_read(display, DP_TP_CTL(PORT_E));
drivers/gpu/drm/i915/display/intel_fdi.c
956
intel_wait_ddi_buf_idle(display, PORT_E);
drivers/gpu/drm/i915/display/intel_fdi.c
959
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
drivers/gpu/drm/i915/display/intel_fdi.c
96
INTEL_DISPLAY_STATE_WARN(display, !cur_state,
drivers/gpu/drm/i915/display/intel_fdi.c
962
intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
drivers/gpu/drm/i915/display/intel_fdi.c
966
intel_de_write(display, DP_TP_CTL(PORT_E),
drivers/gpu/drm/i915/display/intel_fdi.c
975
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_fdi.c
983
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
984
intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
985
intel_wait_ddi_buf_idle(display, PORT_E);
drivers/gpu/drm/i915/display/intel_fdi.c
987
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
drivers/gpu/drm/i915/display/intel_fdi.c
990
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
991
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_fdi.c
996
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_fdi.h
21
int intel_fdi_link_freq(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fdi.h
31
void intel_fdi_init_hook(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fdi.h
35
void intel_fdi_pll_freq_update(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fdi.h
40
void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fdi.h
41
void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fdi.h
42
void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fdi.h
43
void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fdi.h
44
void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fdi.h
45
void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fdi.h
46
void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
101
log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
103
log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
107
static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
109
u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
114
intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
117
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
124
static void read_underrun_dbg_pkgc(struct intel_display *display, bool log)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
126
u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
135
intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
138
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
142
static void read_underrun_dbg_info(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
146
if (!HAS_UNDERRUN_DBG_INFO(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
149
read_underrun_dbg1(display, pipe, log);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
150
read_underrun_dbg2(display, pipe, log);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
151
intel_fbc_read_underrun_dbg_info(display, pipe, log);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
152
read_underrun_dbg_pkgc(display, log);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
155
static bool ivb_can_enable_err_int(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
160
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
162
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
163
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
172
static bool cpt_can_enable_serr_int(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
177
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
179
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
180
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
191
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
192
intel_reg_t reg = PIPESTAT(display, crtc->pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
195
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
197
if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
200
enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
201
intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
202
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
204
trace_intel_cpu_fifo_underrun(display, crtc->pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
205
drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
208
static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
212
intel_reg_t reg = PIPESTAT(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
214
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
217
u32 enable_mask = i915_pipestat_enable_mask(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
219
intel_de_write(display, reg,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
221
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
223
if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
224
drm_err(display->drm, "pipe %c underrun\n",
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
229
static void ilk_set_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
236
ilk_enable_display_irq(display, bit);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
238
ilk_disable_display_irq(display, bit);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
243
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
245
u32 err_int = intel_de_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
247
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
252
intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
253
intel_de_posting_read(display, GEN7_ERR_INT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
255
trace_intel_cpu_fifo_underrun(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
256
drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
259
static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
264
intel_de_write(display, GEN7_ERR_INT,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
267
if (!ivb_can_enable_err_int(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
270
ilk_enable_display_irq(display, DE_ERR_INT_IVB);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
272
ilk_disable_display_irq(display, DE_ERR_INT_IVB);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
275
intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
276
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
283
static void bdw_set_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
287
bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
289
bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
292
static void ibx_set_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
300
ibx_enable_display_interrupt(display, bit);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
302
ibx_disable_display_interrupt(display, bit);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
307
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
309
u32 serr_int = intel_de_read(display, SERR_INT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
311
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
316
intel_de_write(display, SERR_INT,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
318
intel_de_posting_read(display, SERR_INT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
320
trace_intel_pch_fifo_underrun(display, pch_transcoder);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
321
drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
325
static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
330
intel_de_write(display, SERR_INT,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
333
if (!cpt_can_enable_serr_int(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
336
ibx_enable_display_interrupt(display, SDE_ERROR_CPT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
338
ibx_disable_display_interrupt(display, SDE_ERROR_CPT);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
340
if (old && intel_de_read(display, SERR_INT) &
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
342
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
349
static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
352
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
355
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
369
read_underrun_dbg_info(display, pipe, false);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
371
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
372
i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
373
else if (display->platform.ironlake || display->platform.sandybridge)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
374
ilk_set_fifo_underrun_reporting(display, pipe, enable);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
375
else if (DISPLAY_VER(display) == 7)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
376
ivb_set_fifo_underrun_reporting(display, pipe, enable, old);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
377
else if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
378
bdw_set_fifo_underrun_reporting(display, pipe, enable);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
399
bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
405
spin_lock_irqsave(&display->irq.lock, flags);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
406
ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
407
spin_unlock_irqrestore(&display->irq.lock, flags);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
426
bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
430
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
443
spin_lock_irqsave(&display->irq.lock, flags);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
448
if (HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
449
ibx_set_fifo_underrun_reporting(display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
453
cpt_set_fifo_underrun_reporting(display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
457
spin_unlock_irqrestore(&display->irq.lock, flags);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
470
void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
473
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
480
if (HAS_GMCH(display) &&
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
484
if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
485
trace_intel_cpu_fifo_underrun(display, pipe);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
487
drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
489
read_underrun_dbg_info(display, pipe, true);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
492
intel_fbc_handle_fifo_underrun_irq(display);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
504
void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
507
if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
509
trace_intel_pch_fifo_underrun(display, pch_transcoder);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
510
drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
524
void intel_check_cpu_fifo_underruns(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
528
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
530
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
534
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
536
else if (DISPLAY_VER(display) == 7)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
540
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
551
void intel_check_pch_fifo_underruns(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
555
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
557
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
561
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
565
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
568
void intel_init_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
583
if (intel_has_pch_trancoder(display, crtc->pipe))
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
63
static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe,
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
79
drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n",
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
82
drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
85
static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log)
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
87
u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
92
intel_de_write(display, UNDERRUN_DBG1(pipe), val);
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
97
log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
99
log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
15
void intel_init_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
17
bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
19
bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
22
void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
24
void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
26
void intel_check_cpu_fifo_underruns(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
27
void intel_check_pch_fifo_underruns(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_flipq.c
108
drm_dbg_kms(display->drm, "[CRTC:%d:%s] FQ %d: start 0x%x\n",
drivers/gpu/drm/i915/display/intel_flipq.c
114
bool intel_flipq_supported(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_flipq.c
116
if (!display->params.enable_flipq)
drivers/gpu/drm/i915/display/intel_flipq.c
119
if (!display->dmc.dmc)
drivers/gpu/drm/i915/display/intel_flipq.c
122
if (DISPLAY_VER(display) == 20)
drivers/gpu/drm/i915/display/intel_flipq.c
126
return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display);
drivers/gpu/drm/i915/display/intel_flipq.c
129
void intel_flipq_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_flipq.c
133
intel_dmc_wait_fw_load(display);
drivers/gpu/drm/i915/display/intel_flipq.c
135
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/intel_flipq.c
139
static int cdclk_factor(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_flipq.c
141
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_flipq.c
147
int intel_flipq_exec_time_us(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_flipq.c
150
DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) +
drivers/gpu/drm/i915/display/intel_flipq.c
151
display->sagv.block_time_us;
drivers/gpu/drm/i915/display/intel_flipq.c
154
static int intel_flipq_preempt_timeout_ms(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_flipq.c
156
return DIV_ROUND_UP(intel_flipq_exec_time_us(display), 1000);
drivers/gpu/drm/i915/display/intel_flipq.c
161
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
163
intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),
drivers/gpu/drm/i915/display/intel_flipq.c
167
intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_flipq.c
170
intel_flipq_preempt_timeout_ms(display)))
drivers/gpu/drm/i915/display/intel_flipq.c
171
drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt timeout\n",
drivers/gpu/drm/i915/display/intel_flipq.c
177
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
179
return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));
drivers/gpu/drm/i915/display/intel_flipq.c
184
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
186
intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),
drivers/gpu/drm/i915/display/intel_flipq.c
196
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
198
intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);
drivers/gpu/drm/i915/display/intel_flipq.c
203
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_flipq.c
206
intel_flipq_exec_time_us(display));
drivers/gpu/drm/i915/display/intel_flipq.c
212
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
216
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_flipq.c
222
intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));
drivers/gpu/drm/i915/display/intel_flipq.c
227
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_flipq.c
230
intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),
drivers/gpu/drm/i915/display/intel_flipq.c
231
intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));
drivers/gpu/drm/i915/display/intel_flipq.c
233
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_flipq.c
238
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_flipq.c
241
intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));
drivers/gpu/drm/i915/display/intel_flipq.c
243
tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));
drivers/gpu/drm/i915/display/intel_flipq.c
245
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_flipq.c
255
void intel_flipq_reset(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_flipq.c
257
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_flipq.c
260
intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
262
intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
263
intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
268
intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
269
intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
274
intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
277
static enum pipedmc_event_id flipq_event_id(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_flipq.c
279
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_flipq.c
287
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_flipq.c
293
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_flipq.c
297
intel_de_write(display, PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr),
drivers/gpu/drm/i915/display/intel_flipq.c
299
intel_de_write(display, PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr),
drivers/gpu/drm/i915/display/intel_flipq.c
303
intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),
drivers/gpu/drm/i915/display/intel_flipq.c
305
intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),
drivers/gpu/drm/i915/display/intel_flipq.c
309
intel_pipedmc_enable_event(crtc, flipq_event_id(display));
drivers/gpu/drm/i915/display/intel_flipq.c
311
intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);
drivers/gpu/drm/i915/display/intel_flipq.c
316
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_flipq.c
321
intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
323
intel_pipedmc_disable_event(crtc, flipq_event_id(display));
drivers/gpu/drm/i915/display/intel_flipq.c
325
intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
326
intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_flipq.c
332
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
338
return !drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_flipq.c
345
static void intel_flipq_write(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_flipq.c
348
intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail *
drivers/gpu/drm/i915/display/intel_flipq.c
352
static void lnl_flipq_add(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_flipq.c
362
intel_flipq_write(display, flipq, pts, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
363
intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
drivers/gpu/drm/i915/display/intel_flipq.c
364
intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT |
drivers/gpu/drm/i915/display/intel_flipq.c
367
intel_flipq_write(display, flipq, 0, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
368
intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */
drivers/gpu/drm/i915/display/intel_flipq.c
369
intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */
drivers/gpu/drm/i915/display/intel_flipq.c
374
intel_flipq_write(display, flipq, pts, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
375
intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
drivers/gpu/drm/i915/display/intel_flipq.c
376
intel_flipq_write(display, flipq, LNL_FQ_INTERRUPT |
drivers/gpu/drm/i915/display/intel_flipq.c
379
intel_flipq_write(display, flipq, 0, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
387
static void ptl_flipq_add(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_flipq.c
397
intel_flipq_write(display, flipq, pts, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
398
intel_flipq_write(display, flipq, 0, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
399
intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT |
drivers/gpu/drm/i915/display/intel_flipq.c
402
intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
drivers/gpu/drm/i915/display/intel_flipq.c
403
intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */
drivers/gpu/drm/i915/display/intel_flipq.c
404
intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */
drivers/gpu/drm/i915/display/intel_flipq.c
409
intel_flipq_write(display, flipq, pts, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
410
intel_flipq_write(display, flipq, 0, i++);
drivers/gpu/drm/i915/display/intel_flipq.c
411
intel_flipq_write(display, flipq, PTL_FQ_INTERRUPT |
drivers/gpu/drm/i915/display/intel_flipq.c
414
intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
drivers/gpu/drm/i915/display/intel_flipq.c
428
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
434
pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));
drivers/gpu/drm/i915/display/intel_flipq.c
438
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_flipq.c
439
ptl_flipq_add(display, flipq, pts, dsb_id, dsb);
drivers/gpu/drm/i915/display/intel_flipq.c
441
lnl_flipq_add(display, flipq, pts, dsb_id, dsb);
drivers/gpu/drm/i915/display/intel_flipq.c
453
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
455
if (intel_display_wa(display, INTEL_DISPLAY_WA_18034343758))
drivers/gpu/drm/i915/display/intel_flipq.c
461
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.c
463
if (intel_display_wa(display, INTEL_DISPLAY_WA_18034343758))
drivers/gpu/drm/i915/display/intel_flipq.c
99
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_flipq.h
19
bool intel_flipq_supported(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_flipq.h
20
void intel_flipq_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_flipq.h
21
void intel_flipq_reset(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_flipq.h
31
int intel_flipq_exec_time_us(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
100
intel_psr_flush(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
101
intel_fbc_flush(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
115
void intel_frontbuffer_flip(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_frontbuffer.c
118
spin_lock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
120
display->fb_tracking.busy_bits &= ~frontbuffer_bits;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
121
spin_unlock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
123
frontbuffer_flush(display, frontbuffer_bits, ORIGIN_FLIP);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
130
struct intel_display *display = front->display;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
133
spin_lock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
134
display->fb_tracking.busy_bits |= frontbuffer_bits;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
135
spin_unlock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
138
trace_intel_frontbuffer_invalidate(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
141
intel_psr_invalidate(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
142
intel_drrs_invalidate(display, frontbuffer_bits);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
143
intel_fbc_invalidate(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
150
struct intel_display *display = front->display;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
153
intel_parent_frontbuffer_flush_for_display(display, front);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
156
spin_lock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
158
frontbuffer_bits &= display->fb_tracking.busy_bits;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
159
display->fb_tracking.busy_bits &= ~frontbuffer_bits;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
160
spin_unlock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
164
frontbuffer_flush(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
173
intel_parent_frontbuffer_put(front->display, front);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
188
intel_parent_frontbuffer_ref(front->display, front);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
190
intel_parent_frontbuffer_put(front->display, front);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
195
front->display = to_intel_display(drm);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
202
drm_WARN_ON(front->display->drm, atomic_read(&front->bits));
drivers/gpu/drm/i915/display/intel_frontbuffer.c
231
drm_WARN_ON(old->display->drm,
drivers/gpu/drm/i915/display/intel_frontbuffer.c
237
drm_WARN_ON(new->display->drm,
drivers/gpu/drm/i915/display/intel_frontbuffer.c
83
static void frontbuffer_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_frontbuffer.c
88
spin_lock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
89
frontbuffer_bits &= ~display->fb_tracking.busy_bits;
drivers/gpu/drm/i915/display/intel_frontbuffer.c
90
spin_unlock(&display->fb_tracking.lock);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
95
trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
98
intel_td_flush(display);
drivers/gpu/drm/i915/display/intel_frontbuffer.c
99
intel_drrs_flush(display, frontbuffer_bits);
drivers/gpu/drm/i915/display/intel_frontbuffer.h
44
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_frontbuffer.h
66
void intel_frontbuffer_flip(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_global_state.c
111
void intel_atomic_global_obj_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_global_state.c
124
list_add_tail(&obj->head, &display->global.obj_list);
drivers/gpu/drm/i915/display/intel_global_state.c
127
void intel_atomic_global_obj_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_global_state.c
131
list_for_each_entry_safe(obj, next, &display->global.obj_list, head) {
drivers/gpu/drm/i915/display/intel_global_state.c
134
drm_WARN_ON(display->drm, kref_read(&obj->state->ref) != 1);
drivers/gpu/drm/i915/display/intel_global_state.c
139
static void assert_global_state_write_locked(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_global_state.c
143
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/intel_global_state.c
162
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_global_state.c
166
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_global_state.c
171
drm_WARN(display->drm, 1, "Global state not read locked\n");
drivers/gpu/drm/i915/display/intel_global_state.c
178
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_global_state.c
220
drm_dbg_atomic(display->drm, "Added new global object %p state %p to %p\n",
drivers/gpu/drm/i915/display/intel_global_state.c
254
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_global_state.c
261
drm_WARN_ON(display->drm, obj->state != old_obj_state);
drivers/gpu/drm/i915/display/intel_global_state.c
270
assert_global_state_write_locked(display);
drivers/gpu/drm/i915/display/intel_global_state.c
301
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_global_state.c
304
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_global_state.c
334
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_global_state.c
337
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/intel_global_state.c
380
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_global_state.c
394
drm_err(display->drm, "global state timed out\n");
drivers/gpu/drm/i915/display/intel_global_state.h
38
void intel_atomic_global_obj_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_global_state.h
42
void intel_atomic_global_obj_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_gmbus.c
1003
mutex_unlock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
1013
void intel_gmbus_teardown(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
1017
for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
drivers/gpu/drm/i915/display/intel_gmbus.c
1020
bus = display->gmbus.bus[pin];
drivers/gpu/drm/i915/display/intel_gmbus.c
1027
display->gmbus.bus[pin] = NULL;
drivers/gpu/drm/i915/display/intel_gmbus.c
1031
void intel_gmbus_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
1033
wake_up_all(&display->gmbus.wait_queue);
drivers/gpu/drm/i915/display/intel_gmbus.c
154
static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
160
if (INTEL_PCH_TYPE(display) >= PCH_MTL) {
drivers/gpu/drm/i915/display/intel_gmbus.c
163
} else if (INTEL_PCH_TYPE(display) >= PCH_DG2) {
drivers/gpu/drm/i915/display/intel_gmbus.c
166
} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {
drivers/gpu/drm/i915/display/intel_gmbus.c
169
} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {
drivers/gpu/drm/i915/display/intel_gmbus.c
172
} else if (HAS_PCH_CNP(display)) {
drivers/gpu/drm/i915/display/intel_gmbus.c
175
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_gmbus.c
178
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_gmbus.c
181
} else if (display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_gmbus.c
195
bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
drivers/gpu/drm/i915/display/intel_gmbus.c
197
return get_gmbus_pin(display, pin);
drivers/gpu/drm/i915/display/intel_gmbus.c
211
intel_gmbus_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
213
intel_de_write(display, GMBUS0(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
214
intel_de_write(display, GMBUS4(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
217
static void pnv_gmbus_clock_gating(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
221
intel_de_rmw(display, DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_gmbus.c
226
static void pch_gmbus_clock_gating(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
229
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_gmbus.c
234
static void bxt_gmbus_clock_gating(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
237
intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
drivers/gpu/drm/i915/display/intel_gmbus.c
243
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
246
if (display->platform.i830 || display->platform.i845g)
drivers/gpu/drm/i915/display/intel_gmbus.c
253
if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575))
drivers/gpu/drm/i915/display/intel_gmbus.c
257
return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits;
drivers/gpu/drm/i915/display/intel_gmbus.c
263
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
266
intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
drivers/gpu/drm/i915/display/intel_gmbus.c
267
intel_de_write_notrace(display, bus->gpio_reg, reserved);
drivers/gpu/drm/i915/display/intel_gmbus.c
269
return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
drivers/gpu/drm/i915/display/intel_gmbus.c
275
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
278
intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
drivers/gpu/drm/i915/display/intel_gmbus.c
279
intel_de_write_notrace(display, bus->gpio_reg, reserved);
drivers/gpu/drm/i915/display/intel_gmbus.c
281
return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
drivers/gpu/drm/i915/display/intel_gmbus.c
287
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
297
intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
drivers/gpu/drm/i915/display/intel_gmbus.c
298
intel_de_posting_read(display, bus->gpio_reg);
drivers/gpu/drm/i915/display/intel_gmbus.c
304
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
314
intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
drivers/gpu/drm/i915/display/intel_gmbus.c
315
intel_de_posting_read(display, bus->gpio_reg);
drivers/gpu/drm/i915/display/intel_gmbus.c
321
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
322
u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);
drivers/gpu/drm/i915/display/intel_gmbus.c
330
intel_de_write_notrace(display, bus->gpio_reg, reg_val);
drivers/gpu/drm/i915/display/intel_gmbus.c
331
intel_de_posting_read(display, bus->gpio_reg);
drivers/gpu/drm/i915/display/intel_gmbus.c
338
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
340
intel_gmbus_reset(display);
drivers/gpu/drm/i915/display/intel_gmbus.c
342
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_gmbus.c
343
pnv_gmbus_clock_gating(display, false);
drivers/gpu/drm/i915/display/intel_gmbus.c
345
if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575))
drivers/gpu/drm/i915/display/intel_gmbus.c
358
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
363
if (display->platform.pineview)
drivers/gpu/drm/i915/display/intel_gmbus.c
364
pnv_gmbus_clock_gating(display, true);
drivers/gpu/drm/i915/display/intel_gmbus.c
366
if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575))
drivers/gpu/drm/i915/display/intel_gmbus.c
390
static bool has_gmbus_irq(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
396
return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display);
drivers/gpu/drm/i915/display/intel_gmbus.c
399
static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
drivers/gpu/drm/i915/display/intel_gmbus.c
409
if (!has_gmbus_irq(display))
drivers/gpu/drm/i915/display/intel_gmbus.c
412
add_wait_queue(&display->gmbus.wait_queue, &wait);
drivers/gpu/drm/i915/display/intel_gmbus.c
413
intel_de_write_fw(display, GMBUS4(display), irq_en);
drivers/gpu/drm/i915/display/intel_gmbus.c
417
ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
drivers/gpu/drm/i915/display/intel_gmbus.c
421
ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
drivers/gpu/drm/i915/display/intel_gmbus.c
425
intel_de_write_fw(display, GMBUS4(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
426
remove_wait_queue(&display->gmbus.wait_queue, &wait);
drivers/gpu/drm/i915/display/intel_gmbus.c
435
gmbus_wait_idle(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
443
if (has_gmbus_irq(display))
drivers/gpu/drm/i915/display/intel_gmbus.c
446
add_wait_queue(&display->gmbus.wait_queue, &wait);
drivers/gpu/drm/i915/display/intel_gmbus.c
447
intel_de_write_fw(display, GMBUS4(display), irq_enable);
drivers/gpu/drm/i915/display/intel_gmbus.c
449
ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);
drivers/gpu/drm/i915/display/intel_gmbus.c
451
intel_de_write_fw(display, GMBUS4(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
452
remove_wait_queue(&display->gmbus.wait_queue, &wait);
drivers/gpu/drm/i915/display/intel_gmbus.c
457
static unsigned int gmbus_max_xfer_size(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
459
return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
drivers/gpu/drm/i915/display/intel_gmbus.c
464
gmbus_xfer_read_chunk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
469
bool burst_read = len > gmbus_max_xfer_size(display);
drivers/gpu/drm/i915/display/intel_gmbus.c
482
intel_de_write_fw(display, GMBUS0(display),
drivers/gpu/drm/i915/display/intel_gmbus.c
486
intel_de_write_fw(display, GMBUS1(display),
drivers/gpu/drm/i915/display/intel_gmbus.c
492
ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
drivers/gpu/drm/i915/display/intel_gmbus.c
496
val = intel_de_read_fw(display, GMBUS3(display));
drivers/gpu/drm/i915/display/intel_gmbus.c
509
intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
drivers/gpu/drm/i915/display/intel_gmbus.c
526
gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
drivers/gpu/drm/i915/display/intel_gmbus.c
53
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_gmbus.c
535
if (HAS_GMBUS_BURST_READ(display))
drivers/gpu/drm/i915/display/intel_gmbus.c
538
len = min(rx_size, gmbus_max_xfer_size(display));
drivers/gpu/drm/i915/display/intel_gmbus.c
540
ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
drivers/gpu/drm/i915/display/intel_gmbus.c
553
gmbus_xfer_write_chunk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
566
intel_de_write_fw(display, GMBUS3(display), val);
drivers/gpu/drm/i915/display/intel_gmbus.c
567
intel_de_write_fw(display, GMBUS1(display),
drivers/gpu/drm/i915/display/intel_gmbus.c
577
intel_de_write_fw(display, GMBUS3(display), val);
drivers/gpu/drm/i915/display/intel_gmbus.c
579
ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
drivers/gpu/drm/i915/display/intel_gmbus.c
588
gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
drivers/gpu/drm/i915/display/intel_gmbus.c
597
len = min(tx_size, gmbus_max_xfer_size(display));
drivers/gpu/drm/i915/display/intel_gmbus.c
599
ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
drivers/gpu/drm/i915/display/intel_gmbus.c
626
gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
drivers/gpu/drm/i915/display/intel_gmbus.c
642
intel_de_write_fw(display, GMBUS5(display), gmbus5);
drivers/gpu/drm/i915/display/intel_gmbus.c
645
ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
drivers/gpu/drm/i915/display/intel_gmbus.c
648
ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
drivers/gpu/drm/i915/display/intel_gmbus.c
652
intel_de_write_fw(display, GMBUS5(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
662
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
667
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_gmbus.c
668
bxt_gmbus_clock_gating(display, false);
drivers/gpu/drm/i915/display/intel_gmbus.c
669
else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))
drivers/gpu/drm/i915/display/intel_gmbus.c
670
pch_gmbus_clock_gating(display, false);
drivers/gpu/drm/i915/display/intel_gmbus.c
673
intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
drivers/gpu/drm/i915/display/intel_gmbus.c
678
ret = gmbus_index_xfer(display, &msgs[i],
drivers/gpu/drm/i915/display/intel_gmbus.c
682
ret = gmbus_xfer_read(display, &msgs[i],
drivers/gpu/drm/i915/display/intel_gmbus.c
685
ret = gmbus_xfer_write(display, &msgs[i], 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
689
ret = gmbus_wait(display,
drivers/gpu/drm/i915/display/intel_gmbus.c
701
intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
drivers/gpu/drm/i915/display/intel_gmbus.c
707
if (gmbus_wait_idle(display)) {
drivers/gpu/drm/i915/display/intel_gmbus.c
708
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_gmbus.c
713
intel_de_write_fw(display, GMBUS0(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
732
if (gmbus_wait_idle(display)) {
drivers/gpu/drm/i915/display/intel_gmbus.c
733
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_gmbus.c
743
intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
drivers/gpu/drm/i915/display/intel_gmbus.c
744
intel_de_write_fw(display, GMBUS1(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
745
intel_de_write_fw(display, GMBUS0(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
747
drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
drivers/gpu/drm/i915/display/intel_gmbus.c
758
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_gmbus.c
767
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_gmbus.c
770
intel_de_write_fw(display, GMBUS0(display), 0);
drivers/gpu/drm/i915/display/intel_gmbus.c
780
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_gmbus.c
781
bxt_gmbus_clock_gating(display, true);
drivers/gpu/drm/i915/display/intel_gmbus.c
782
else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))
drivers/gpu/drm/i915/display/intel_gmbus.c
783
pch_gmbus_clock_gating(display, true);
drivers/gpu/drm/i915/display/intel_gmbus.c
792
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
796
wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);
drivers/gpu/drm/i915/display/intel_gmbus.c
808
intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
drivers/gpu/drm/i915/display/intel_gmbus.c
816
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
836
wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);
drivers/gpu/drm/i915/display/intel_gmbus.c
837
mutex_lock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
846
mutex_unlock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
847
intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
drivers/gpu/drm/i915/display/intel_gmbus.c
870
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
872
mutex_lock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
879
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
881
return mutex_trylock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
888
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
890
mutex_unlock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
903
int intel_gmbus_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gmbus.c
905
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_gmbus.c
909
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_gmbus.c
910
display->gmbus.mmio_base = VLV_DISPLAY_BASE;
drivers/gpu/drm/i915/display/intel_gmbus.c
911
else if (!HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_gmbus.c
916
display->gmbus.mmio_base = PCH_DISPLAY_BASE;
drivers/gpu/drm/i915/display/intel_gmbus.c
918
mutex_init(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
919
init_waitqueue_head(&display->gmbus.wait_queue);
drivers/gpu/drm/i915/display/intel_gmbus.c
921
for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
drivers/gpu/drm/i915/display/intel_gmbus.c
925
gmbus_pin = get_gmbus_pin(display, pin);
drivers/gpu/drm/i915/display/intel_gmbus.c
941
bus->display = display;
drivers/gpu/drm/i915/display/intel_gmbus.c
956
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_gmbus.c
959
intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
drivers/gpu/drm/i915/display/intel_gmbus.c
967
display->gmbus.bus[pin] = bus;
drivers/gpu/drm/i915/display/intel_gmbus.c
970
intel_gmbus_reset(display);
drivers/gpu/drm/i915/display/intel_gmbus.c
975
intel_gmbus_teardown(display);
drivers/gpu/drm/i915/display/intel_gmbus.c
980
struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_gmbus.c
983
if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
drivers/gpu/drm/i915/display/intel_gmbus.c
984
!display->gmbus.bus[pin]))
drivers/gpu/drm/i915/display/intel_gmbus.c
987
return &display->gmbus.bus[pin]->adapter;
drivers/gpu/drm/i915/display/intel_gmbus.c
993
struct intel_display *display = bus->display;
drivers/gpu/drm/i915/display/intel_gmbus.c
995
mutex_lock(&display->gmbus.mutex);
drivers/gpu/drm/i915/display/intel_gmbus.c
998
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_gmbus.h
37
int intel_gmbus_setup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_gmbus.h
38
void intel_gmbus_teardown(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_gmbus.h
39
bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);
drivers/gpu/drm/i915/display/intel_gmbus.h
43
intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);
drivers/gpu/drm/i915/display/intel_gmbus.h
46
void intel_gmbus_reset(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_gmbus.h
48
void intel_gmbus_irq_handler(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_gvt_api.c
12
u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_gvt_api.c
14
return INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe);
drivers/gpu/drm/i915/display/intel_gvt_api.c
18
u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans)
drivers/gpu/drm/i915/display/intel_gvt_api.c
20
return INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans);
drivers/gpu/drm/i915/display/intel_gvt_api.c
24
u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_gvt_api.c
26
return INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe);
drivers/gpu/drm/i915/display/intel_gvt_api.c
30
u32 intel_display_device_mmio_base(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_gvt_api.c
32
return DISPLAY_MMIO_BASE(display);
drivers/gpu/drm/i915/display/intel_gvt_api.c
36
bool intel_display_device_pipe_valid(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_gvt_api.c
41
return DISPLAY_RUNTIME_INFO(display)->pipe_mask & BIT(pipe);
drivers/gpu/drm/i915/display/intel_gvt_api.h
15
u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_gvt_api.h
16
u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans);
drivers/gpu/drm/i915/display/intel_gvt_api.h
17
u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_gvt_api.h
18
u32 intel_display_device_mmio_base(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_gvt_api.h
19
bool intel_display_device_pipe_valid(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_hdcp.c
1000
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1006
drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1010
drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1022
intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
1023
if (intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
1024
HDCP_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
1026
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1031
repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder,
drivers/gpu/drm/i915/display/intel_hdcp.c
1033
intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
1037
drm_err(display->drm, "Failed to disable HDCP signalling\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1041
drm_dbg_kms(display->drm, "HDCP is disabled\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1047
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1051
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1054
if (!hdcp_key_loadable(display)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
1055
drm_err(display->drm, "HDCP key Load is not possible\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1060
ret = intel_hdcp_load_keys(display);
drivers/gpu/drm/i915/display/intel_hdcp.c
1063
intel_hdcp_clear_keys(display);
drivers/gpu/drm/i915/display/intel_hdcp.c
1066
drm_err(display->drm, "Could not load HDCP keys, (%d)\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1081
drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1087
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1100
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1104
drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex));
drivers/gpu/drm/i915/display/intel_hdcp.c
1109
drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex));
drivers/gpu/drm/i915/display/intel_hdcp.c
1112
if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0))
drivers/gpu/drm/i915/display/intel_hdcp.c
1121
if (!queue_work(display->wq.unordered, &hdcp->prop_work))
drivers/gpu/drm/i915/display/intel_hdcp.c
1129
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
114
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_hdcp.c
1148
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1149
!intel_hdcp_in_use(display, cpu_transcoder, port))) {
drivers/gpu/drm/i915/display/intel_hdcp.c
1150
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1153
intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)));
drivers/gpu/drm/i915/display/intel_hdcp.c
1169
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1175
drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1184
drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1202
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1204
drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);
drivers/gpu/drm/i915/display/intel_hdcp.c
1217
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1222
bool is_hdcp_supported(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_hdcp.c
1224
return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&
drivers/gpu/drm/i915/display/intel_hdcp.c
1225
(DISPLAY_VER(display) >= 12 || port < PORT_E);
drivers/gpu/drm/i915/display/intel_hdcp.c
1232
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1238
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1239
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1242
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1248
drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1250
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1262
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1268
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1269
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1272
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1280
drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1282
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1290
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1296
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1297
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1300
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1306
drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1307
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
131
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hdcp.c
1316
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1322
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1323
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1326
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1332
drm_dbg_kms(display->drm, "Store pairing info failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1334
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1343
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1349
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1350
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1353
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1359
drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1361
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1370
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1376
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1377
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1380
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1386
drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1388
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1396
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1402
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1403
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1406
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1412
drm_dbg_kms(display->drm, "Get session key failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1414
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1425
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1431
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1432
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1435
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1444
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1446
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1455
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1461
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1462
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1465
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1471
drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1472
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1479
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
148
if (drm_WARN_ON(display->drm, data->k >= INTEL_NUM_PIPES(display)))
drivers/gpu/drm/i915/display/intel_hdcp.c
1485
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1486
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1489
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1495
drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1497
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1504
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1509
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1510
arbiter = display->hdcp.arbiter;
drivers/gpu/drm/i915/display/intel_hdcp.c
1513
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1519
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
1532
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1595
drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1601
if (drm_hdcp_check_ksvs_revoked(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1604
drm_err(display->drm, "Receiver ID is revoked\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
161
if (drm_WARN_ON(display->drm, !data->k))
drivers/gpu/drm/i915/display/intel_hdcp.c
1755
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1776
drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1789
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1799
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1806
drm_dbg_kms(display->drm, "Seq_num_v %s\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1813
if (drm_hdcp_check_ksvs_revoked(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1816
drm_err(display->drm, "Revoked receiver ID(s) is in list\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1837
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1844
drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1850
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1857
drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret);
drivers/gpu/drm/i915/display/intel_hdcp.c
1872
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1883
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1891
if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1893
drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1902
drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1906
drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
1914
drm_dbg_kms(display->drm, "Port deauth failed.\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
1924
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1931
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1932
intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1938
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1945
if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1948
intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
1951
ret = intel_de_wait_for_set_ms(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
1952
HDCP2_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
1962
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
1969
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
1970
!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
1973
intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
1976
ret = intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
1977
HDCP2_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
1981
drm_dbg_kms(display->drm, "Disable Encryption Timedout");
drivers/gpu/drm/i915/display/intel_hdcp.c
1987
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2000
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2013
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2018
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2029
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2038
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2046
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2055
drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2060
drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2063
drm_dbg_kms(display->drm, "Port deauth failed.\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2074
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2077
drm_dbg_kms(display->drm, "Port deauth failed.\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
209
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdcp.c
2090
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2094
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2102
drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2107
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2118
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2124
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2130
drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2134
drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2144
drm_dbg_kms(display->drm, "Port deauth failed.\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2156
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2174
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2175
!intel_hdcp2_in_use(display, cpu_transcoder, port))) {
drivers/gpu/drm/i915/display/intel_hdcp.c
2176
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2178
intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)));
drivers/gpu/drm/i915/display/intel_hdcp.c
2201
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
221
drm_dbg_kms(display->drm, "Bksv is invalid\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2212
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2217
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2224
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2246
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2252
queue_delayed_work(display->wq.unordered, &hdcp->check_work,
drivers/gpu/drm/i915/display/intel_hdcp.c
2255
queue_delayed_work(display->wq.unordered, &hdcp->check_work,
drivers/gpu/drm/i915/display/intel_hdcp.c
2262
struct intel_display *display = to_intel_display(drv_kdev);
drivers/gpu/drm/i915/display/intel_hdcp.c
2264
drm_dbg(display->drm, "I915 HDCP comp bind\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2265
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2266
display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data;
drivers/gpu/drm/i915/display/intel_hdcp.c
2267
display->hdcp.arbiter->hdcp_dev = mei_kdev;
drivers/gpu/drm/i915/display/intel_hdcp.c
2268
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2276
struct intel_display *display = to_intel_display(drv_kdev);
drivers/gpu/drm/i915/display/intel_hdcp.c
2278
drm_dbg(display->drm, "I915 HDCP comp unbind\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2279
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2280
display->hdcp.arbiter = NULL;
drivers/gpu/drm/i915/display/intel_hdcp.c
2281
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2315
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2319
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_hdcp.c
2340
INTEL_NUM_PIPES(display));
drivers/gpu/drm/i915/display/intel_hdcp.c
2342
drm_err(display->drm, "Out of Memory\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2349
static bool is_hdcp2_supported(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp.c
2351
if (USE_HDCP_GSC(display))
drivers/gpu/drm/i915/display/intel_hdcp.c
2357
return DISPLAY_VER(display) >= 10 ||
drivers/gpu/drm/i915/display/intel_hdcp.c
2358
display->platform.kabylake ||
drivers/gpu/drm/i915/display/intel_hdcp.c
2359
display->platform.coffeelake ||
drivers/gpu/drm/i915/display/intel_hdcp.c
2360
display->platform.cometlake;
drivers/gpu/drm/i915/display/intel_hdcp.c
2363
void intel_hdcp_component_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp.c
2367
if (!is_hdcp2_supported(display))
drivers/gpu/drm/i915/display/intel_hdcp.c
2370
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2371
drm_WARN_ON(display->drm, display->hdcp.comp_added);
drivers/gpu/drm/i915/display/intel_hdcp.c
2373
display->hdcp.comp_added = true;
drivers/gpu/drm/i915/display/intel_hdcp.c
2374
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2375
if (USE_HDCP_GSC(display))
drivers/gpu/drm/i915/display/intel_hdcp.c
2376
ret = intel_hdcp_gsc_init(display);
drivers/gpu/drm/i915/display/intel_hdcp.c
2378
ret = component_add_typed(display->drm->dev, &i915_hdcp_ops,
drivers/gpu/drm/i915/display/intel_hdcp.c
2382
drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
2384
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2385
display->hdcp.comp_added = false;
drivers/gpu/drm/i915/display/intel_hdcp.c
2386
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2395
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2401
drm_dbg_kms(display->drm, "Mei hdcp data init failed\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2412
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2419
if (is_hdcp2_supported(display))
drivers/gpu/drm/i915/display/intel_hdcp.c
2444
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdcp.c
2457
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
2469
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_hdcp.c
2485
drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
2497
queue_delayed_work(display->wq.unordered, &hdcp->check_work,
drivers/gpu/drm/i915/display/intel_hdcp.c
2568
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2595
if (!queue_work(display->wq.unordered, &hdcp->prop_work))
drivers/gpu/drm/i915/display/intel_hdcp.c
260
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2613
if (!queue_work(display->wq.unordered, &hdcp->prop_work))
drivers/gpu/drm/i915/display/intel_hdcp.c
2632
void intel_hdcp_component_fini(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp.c
2634
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2635
if (!display->hdcp.comp_added) {
drivers/gpu/drm/i915/display/intel_hdcp.c
2636
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2640
display->hdcp.comp_added = false;
drivers/gpu/drm/i915/display/intel_hdcp.c
2641
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2643
if (USE_HDCP_GSC(display))
drivers/gpu/drm/i915/display/intel_hdcp.c
2644
intel_hdcp_gsc_fini(display);
drivers/gpu/drm/i915/display/intel_hdcp.c
2646
component_del(display->drm->dev, &i915_hdcp_ops);
drivers/gpu/drm/i915/display/intel_hdcp.c
268
if (USE_HDCP_GSC(display)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
269
if (!intel_parent_hdcp_gsc_check_status(display))
drivers/gpu/drm/i915/display/intel_hdcp.c
2736
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
274
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2744
queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
275
if (!display->hdcp.comp_added || !display->hdcp.arbiter) {
drivers/gpu/drm/i915/display/intel_hdcp.c
276
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2789
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
279
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2792
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2807
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2839
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
2848
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
2861
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_hdcp.c
315
static bool intel_hdcp_in_use(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hdcp.c
318
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
319
HDCP_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
323
static bool intel_hdcp2_in_use(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hdcp.c
326
return intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
327
HDCP2_STATUS(display, cpu_transcoder, port)) &
drivers/gpu/drm/i915/display/intel_hdcp.c
349
static bool hdcp_key_loadable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp.c
358
if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_hdcp.c
364
with_intel_display_rpm(display)
drivers/gpu/drm/i915/display/intel_hdcp.c
365
enabled = intel_display_power_well_is_enabled(display, id);
drivers/gpu/drm/i915/display/intel_hdcp.c
376
static void intel_hdcp_clear_keys(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp.c
378
intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
drivers/gpu/drm/i915/display/intel_hdcp.c
379
intel_de_write(display, HDCP_KEY_STATUS,
drivers/gpu/drm/i915/display/intel_hdcp.c
383
static int intel_hdcp_load_keys(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp.c
388
val = intel_de_read(display, HDCP_KEY_STATUS);
drivers/gpu/drm/i915/display/intel_hdcp.c
396
if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_hdcp.c
397
if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
drivers/gpu/drm/i915/display/intel_hdcp.c
408
if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
drivers/gpu/drm/i915/display/intel_hdcp.c
409
ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1);
drivers/gpu/drm/i915/display/intel_hdcp.c
411
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
417
intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
drivers/gpu/drm/i915/display/intel_hdcp.c
421
ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE,
drivers/gpu/drm/i915/display/intel_hdcp.c
429
intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
drivers/gpu/drm/i915/display/intel_hdcp.c
435
static int intel_write_sha_text(struct intel_display *display, u32 sha_text)
drivers/gpu/drm/i915/display/intel_hdcp.c
437
intel_de_write(display, HDCP_SHA_TEXT, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
438
if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
439
drm_err(display->drm, "Timed out waiting for SHA1 ready\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
446
u32 intel_hdcp_get_repeater_ctl(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hdcp.c
449
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_hdcp.c
464
drm_err(display->drm, "Unknown transcoder %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
48
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdcp.c
482
drm_err(display->drm, "Unknown port %d\n", port);
drivers/gpu/drm/i915/display/intel_hdcp.c
492
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
504
intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime);
drivers/gpu/drm/i915/display/intel_hdcp.c
520
rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port);
drivers/gpu/drm/i915/display/intel_hdcp.c
521
intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
drivers/gpu/drm/i915/display/intel_hdcp.c
533
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
540
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
557
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
56
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_hdcp.c
57
rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_hdcp.c
573
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
575
ret = intel_write_sha_text(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
582
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
584
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
59
} else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) ||
drivers/gpu/drm/i915/display/intel_hdcp.c
590
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
592
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
599
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
60
IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
604
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
61
rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_hdcp.c
610
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
612
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
618
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
620
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
627
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
63
} else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
630
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
636
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
639
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
64
rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_hdcp.c
649
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
652
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
658
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
661
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
667
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
669
ret = intel_write_sha_text(display, bstatus[1]);
drivers/gpu/drm/i915/display/intel_hdcp.c
675
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
677
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
683
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
685
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
69
intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit);
drivers/gpu/drm/i915/display/intel_hdcp.c
690
drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
695
intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
drivers/gpu/drm/i915/display/intel_hdcp.c
698
ret = intel_write_sha_text(display, 0);
drivers/gpu/drm/i915/display/intel_hdcp.c
710
ret = intel_write_sha_text(display, sha_text);
drivers/gpu/drm/i915/display/intel_hdcp.c
715
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
717
if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
719
drm_err(display->drm, "Timed out waiting for SHA1 complete\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
722
if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
drivers/gpu/drm/i915/display/intel_hdcp.c
723
drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
734
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
742
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
75
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_hdcp.c
753
drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
766
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
773
drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
781
if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo,
drivers/gpu/drm/i915/display/intel_hdcp.c
783
drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
801
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
806
drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
817
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.c
851
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
859
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
860
HDCP_ANINIT(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
862
intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
866
if (intel_de_wait_for_set_ms(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
867
HDCP_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
869
drm_err(display->drm, "Timed out waiting for An\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
87
drm_dbg_kms(display->drm, "MST topology still not created\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
873
an.reg[0] = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
874
HDCP_ANLO(display, cpu_transcoder, port));
drivers/gpu/drm/i915/display/intel_hdcp.c
875
an.reg[1] = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
876
HDCP_ANHI(display, cpu_transcoder, port));
drivers/gpu/drm/i915/display/intel_hdcp.c
889
if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) {
drivers/gpu/drm/i915/display/intel_hdcp.c
890
drm_err(display->drm, "BKSV is revoked\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
894
intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
896
intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
903
intel_de_write(display, HDCP_REP_CTL,
drivers/gpu/drm/i915/display/intel_hdcp.c
904
intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port));
drivers/gpu/drm/i915/display/intel_hdcp.c
910
intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
914
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
drivers/gpu/drm/i915/display/intel_hdcp.c
918
drm_err(display->drm, "Timed out waiting for R0 ready\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
93
drm_dbg_kms(display->drm, "MST Payload not present\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
944
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
945
HDCP_RPRIME(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
949
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
drivers/gpu/drm/i915/display/intel_hdcp.c
957
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdcp.c
963
if (intel_de_wait_for_set_ms(display,
drivers/gpu/drm/i915/display/intel_hdcp.c
964
HDCP_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdcp.c
967
drm_err(display->drm, "Timed out waiting for encryption\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
975
drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
979
drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n",
drivers/gpu/drm/i915/display/intel_hdcp.c
986
drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n");
drivers/gpu/drm/i915/display/intel_hdcp.c
992
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdcp.h
41
bool is_hdcp_supported(struct intel_display *display, enum port port);
drivers/gpu/drm/i915/display/intel_hdcp.h
42
void intel_hdcp_component_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hdcp.h
43
void intel_hdcp_component_fini(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
108
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
112
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
117
drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
145
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
151
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
152
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
156
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
170
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
174
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
179
drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
194
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
200
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
201
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
205
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
220
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
224
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
229
drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. Status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
23
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
246
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
252
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
253
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
257
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
268
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
272
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
277
drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
29
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
295
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
30
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
301
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
302
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
306
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
321
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
325
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
330
drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
34
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
347
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
353
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
354
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
358
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
369
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
373
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
378
drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
402
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
408
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
409
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
413
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
434
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
438
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
443
drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
464
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
47
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
471
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
472
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
476
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
503
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
508
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
51
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
513
drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
528
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
534
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
535
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
539
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
551
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
555
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
56
drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
560
drm_dbg_kms(display->drm, "FW cmd 0x%08X failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
574
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
580
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
581
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
585
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
597
byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context,
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
601
drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
606
drm_dbg_kms(display->drm, "Session Close Failed. status: 0x%X\n",
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
630
int intel_hdcp_gsc_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
640
mutex_lock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
642
gsc_context = intel_parent_hdcp_gsc_context_alloc(display);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
649
display->hdcp.arbiter = arbiter;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
650
display->hdcp.arbiter->hdcp_dev = display->drm->dev;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
651
display->hdcp.arbiter->ops = &gsc_hdcp_ops;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
652
display->hdcp.gsc_context = gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
655
mutex_unlock(&display->hdcp.hdcp_mutex);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
660
void intel_hdcp_gsc_fini(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
662
intel_parent_hdcp_gsc_context_free(display, display->hdcp.gsc_context);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
663
display->hdcp.gsc_context = NULL;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
664
kfree(display->hdcp.arbiter);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
665
display->hdcp.arbiter = NULL;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
81
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
87
display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
88
if (!display) {
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
92
gsc_context = display->hdcp.gsc_context;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h
11
int intel_hdcp_gsc_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h
12
void intel_hdcp_gsc_fini(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hdmi.c
1004
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
1005
reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1006
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_hdmi.c
1008
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
101
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1013
intel_de_write(display, reg, crtc_state->infoframes.gcp);
drivers/gpu/drm/i915/display/intel_hdmi.c
102
intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
drivers/gpu/drm/i915/display/intel_hdmi.c
1021
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1029
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
1030
reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1031
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_hdmi.c
1033
else if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
1038
crtc_state->infoframes.gcp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1045
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1047
if (display->platform.g4x || !crtc_state->has_infoframe)
drivers/gpu/drm/i915/display/intel_hdmi.c
1068
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1073
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1087
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1088
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1093
drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
drivers/gpu/drm/i915/display/intel_hdmi.c
1108
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1109
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1127
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1131
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1144
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1145
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1157
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1158
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1176
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1180
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1194
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1195
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1200
drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
drivers/gpu/drm/i915/display/intel_hdmi.c
1215
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1216
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1233
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1234
intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
1236
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1245
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1246
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1258
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1259
intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
1261
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1263
assert_hdmi_transcoder_func_disabled(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
1272
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1273
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1280
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
1281
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1299
struct intel_display *display = to_intel_display(hdmi);
drivers/gpu/drm/i915/display/intel_hdmi.c
1305
drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1308
drm_dp_dual_mode_set_tmds_output(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1374
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1382
drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1389
drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);
drivers/gpu/drm/i915/display/intel_hdmi.c
1398
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1404
drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1413
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1419
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1429
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1435
drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1447
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1453
drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1462
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1468
drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1480
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1485
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1496
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1505
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1514
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
1521
scanline = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
1522
PIPEDSL(display, crtc->pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
1531
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1539
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1552
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1564
drm_err(display->drm, "%s HDCP signalling failed (%d)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1573
if (display->platform.kabylake && enable)
drivers/gpu/drm/i915/display/intel_hdmi.c
1584
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1597
intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
1600
ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display, cpu_transcoder, port),
drivers/gpu/drm/i915/display/intel_hdmi.c
1603
drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1604
intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,
drivers/gpu/drm/i915/display/intel_hdmi.c
1671
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1677
drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
1698
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
1712
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1734
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
1751
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
1760
drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
177
hsw_dip_data_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hdmi.c
1826
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
1829
if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_hdmi.c
1831
else if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_hdmi.c
1833
else if (DISPLAY_VER(display) >= 8 || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_hdmi.c
1835
else if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_hdmi.c
184
return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
186
return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
188
return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
1891
struct intel_display *display = to_intel_display(hdmi);
drivers/gpu/drm/i915/display/intel_hdmi.c
190
return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
1901
if (display->platform.geminilake && clock > 446666 && clock < 480000)
drivers/gpu/drm/i915/display/intel_hdmi.c
1905
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/intel_hdmi.c
1910
if (display->platform.cherryview && clock > 216000 && clock < 240000)
drivers/gpu/drm/i915/display/intel_hdmi.c
192
return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
1939
static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)
drivers/gpu/drm/i915/display/intel_hdmi.c
194
return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
1943
return !HAS_GMCH(display);
drivers/gpu/drm/i915/display/intel_hdmi.c
1945
return DISPLAY_VER(display) >= 11;
drivers/gpu/drm/i915/display/intel_hdmi.c
196
return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
198
return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_hdmi.c
1993
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2006
if (!intel_hdmi_source_bpc_possible(display, bpc))
drivers/gpu/drm/i915/display/intel_hdmi.c
2019
drm_WARN_ON(display->drm, status == MODE_OK);
drivers/gpu/drm/i915/display/intel_hdmi.c
205
static int hsw_dip_data_size(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hdmi.c
2054
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2062
status = intel_pfit_mode_valid(display, mode, sink_format, 0);
drivers/gpu/drm/i915/display/intel_hdmi.c
2074
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2079
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_hdmi.c
2082
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_hdmi.c
2121
return intel_mode_valid_max_plane_size(display, mode, 1);
drivers/gpu/drm/i915/display/intel_hdmi.c
2146
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_hdmi.c
2150
if (!intel_hdmi_source_bpc_possible(display, bpc))
drivers/gpu/drm/i915/display/intel_hdmi.c
2155
bpc == 10 && DISPLAY_VER(display) == 11 &&
drivers/gpu/drm/i915/display/intel_hdmi.c
216
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_hdmi.c
2202
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2225
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
230
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2306
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2318
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
232
u32 val = intel_de_read(display, VIDEO_DIP_CTL);
drivers/gpu/drm/i915/display/intel_hdmi.c
235
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
drivers/gpu/drm/i915/display/intel_hdmi.c
2378
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2414
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
243
intel_de_write(display, VIDEO_DIP_CTL, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
2449
drm_dbg_kms(display->drm, "bad AVI infoframe\n");
drivers/gpu/drm/i915/display/intel_hdmi.c
2454
drm_dbg_kms(display->drm, "bad SPD infoframe\n");
drivers/gpu/drm/i915/display/intel_hdmi.c
2459
drm_dbg_kms(display->drm, "bad HDMI infoframe\n");
drivers/gpu/drm/i915/display/intel_hdmi.c
246
intel_de_write(display, VIDEO_DIP_DATA, *data);
drivers/gpu/drm/i915/display/intel_hdmi.c
2464
drm_dbg_kms(display->drm, "bad DRM infoframe\n");
drivers/gpu/drm/i915/display/intel_hdmi.c
2499
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2505
type = drm_dp_dual_mode_detect(display->drm, ddc);
drivers/gpu/drm/i915/display/intel_hdmi.c
251
intel_de_write(display, VIDEO_DIP_DATA, 0);
drivers/gpu/drm/i915/display/intel_hdmi.c
2519
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
2532
drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);
drivers/gpu/drm/i915/display/intel_hdmi.c
2534
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
2540
if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) &&
drivers/gpu/drm/i915/display/intel_hdmi.c
2542
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
2552
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2559
wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);
drivers/gpu/drm/i915/display/intel_hdmi.c
2564
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
257
intel_de_write(display, VIDEO_DIP_CTL, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
258
intel_de_posting_read(display, VIDEO_DIP_CTL);
drivers/gpu/drm/i915/display/intel_hdmi.c
2582
intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
drivers/gpu/drm/i915/display/intel_hdmi.c
2594
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2600
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
2603
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
2606
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
2609
wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);
drivers/gpu/drm/i915/display/intel_hdmi.c
2611
if (DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/intel_hdmi.c
2621
intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
drivers/gpu/drm/i915/display/intel_hdmi.c
2633
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2635
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_hdmi.c
2638
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
266
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2697
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_hdmi.c
2699
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
270
intel_de_rmw(display, VIDEO_DIP_CTL,
drivers/gpu/drm/i915/display/intel_hdmi.c
2715
struct intel_display *display = to_intel_display(intel_hdmi);
drivers/gpu/drm/i915/display/intel_hdmi.c
2724
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_hdmi.c
2727
if (!HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
274
*data++ = intel_de_read(display, VIDEO_DIP_DATA);
drivers/gpu/drm/i915/display/intel_hdmi.c
2755
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2762
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
280
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
281
u32 val = intel_de_read(display, VIDEO_DIP_CTL);
drivers/gpu/drm/i915/display/intel_hdmi.c
2843
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2851
drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port));
drivers/gpu/drm/i915/display/intel_hdmi.c
2880
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2891
if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)
drivers/gpu/drm/i915/display/intel_hdmi.c
2899
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2902
drm_WARN_ON(display->drm, encoder->port == PORT_A);
drivers/gpu/drm/i915/display/intel_hdmi.c
2910
if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C)
drivers/gpu/drm/i915/display/intel_hdmi.c
2962
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2965
if (display->platform.alderlake_s)
drivers/gpu/drm/i915/display/intel_hdmi.c
2967
else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
drivers/gpu/drm/i915/display/intel_hdmi.c
2969
else if (display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_hdmi.c
2971
else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
2973
else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
drivers/gpu/drm/i915/display/intel_hdmi.c
2974
HAS_PCH_TGP(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
2976
else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_hdmi.c
2978
else if (HAS_PCH_CNP(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
298
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2980
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_hdmi.c
2982
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_hdmi.c
2993
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
2996
for_each_intel_encoder(display->drm, other) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3007
if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
drivers/gpu/drm/i915/display/intel_hdmi.c
3016
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
302
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
3029
if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3030
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
3038
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
3045
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
305
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
drivers/gpu/drm/i915/display/intel_hdmi.c
3055
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
3057
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3062
} else if (display->platform.g4x) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3067
} else if (HAS_DDI(display)) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3079
} else if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3095
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hdmi.c
3104
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
3108
if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))
drivers/gpu/drm/i915/display/intel_hdmi.c
3124
intel_gmbus_get_adapter(display, ddc_pin));
drivers/gpu/drm/i915/display/intel_hdmi.c
3128
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_hdmi.c
313
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
3133
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_hdmi.c
3139
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
3149
if (is_hdcp_supported(display, port)) {
drivers/gpu/drm/i915/display/intel_hdmi.c
3153
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
316
intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
drivers/gpu/drm/i915/display/intel_hdmi.c
3163
drm_dbg_kms(display->drm, "CEC notifier get failed\n");
drivers/gpu/drm/i915/display/intel_hdmi.c
322
intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_hdmi.c
328
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
329
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
337
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
342
intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
drivers/gpu/drm/i915/display/intel_hdmi.c
346
*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
352
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
355
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
373
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
377
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
380
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
drivers/gpu/drm/i915/display/intel_hdmi.c
391
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
394
intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
drivers/gpu/drm/i915/display/intel_hdmi.c
400
intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_hdmi.c
406
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
407
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
415
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
420
intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
drivers/gpu/drm/i915/display/intel_hdmi.c
424
*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
430
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
432
u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
447
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
451
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
454
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
drivers/gpu/drm/i915/display/intel_hdmi.c
462
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
465
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
471
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
478
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
479
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
487
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
492
intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),
drivers/gpu/drm/i915/display/intel_hdmi.c
496
*data++ = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
503
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
505
u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));
drivers/gpu/drm/i915/display/intel_hdmi.c
523
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
526
intel_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
529
u32 val = intel_de_read(display, ctl_reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
531
data_size = hsw_dip_data_size(display, type);
drivers/gpu/drm/i915/display/intel_hdmi.c
533
drm_WARN_ON(display->drm, len > data_size);
drivers/gpu/drm/i915/display/intel_hdmi.c
536
intel_de_write(display, ctl_reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
539
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
540
hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
drivers/gpu/drm/i915/display/intel_hdmi.c
546
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
547
hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
drivers/gpu/drm/i915/display/intel_hdmi.c
551
if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
drivers/gpu/drm/i915/display/intel_hdmi.c
558
intel_de_write(display, ctl_reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
559
intel_de_posting_read(display, ctl_reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
566
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
572
*data++ = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
573
hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2));
drivers/gpu/drm/i915/display/intel_hdmi.c
579
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
580
u32 val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hdmi.c
581
HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_hdmi.c
588
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_hdmi.c
591
if (HAS_AS_SDP(display))
drivers/gpu/drm/i915/display/intel_hdmi.c
623
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
634
if (HAS_DDI(display)) {
drivers/gpu/drm/i915/display/intel_hdmi.c
787
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_hdmi.c
797
if (display->platform.dgfx)
drivers/gpu/drm/i915/display/intel_hdmi.c
849
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
853
if (DISPLAY_VER(display) < 10)
drivers/gpu/drm/i915/display/intel_hdmi.c
867
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
87
struct intel_display *display = to_intel_display(intel_hdmi);
drivers/gpu/drm/i915/display/intel_hdmi.c
873
if (drm_WARN_ON(display->drm, ret))
drivers/gpu/drm/i915/display/intel_hdmi.c
884
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hdmi.c
888
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
90
enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
drivers/gpu/drm/i915/display/intel_hdmi.c
908
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
915
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
916
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
92
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
922
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hdmi.c
93
intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,
drivers/gpu/drm/i915/display/intel_hdmi.c
935
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_hdmi.c
936
intel_de_posting_read(display, reg);
drivers/gpu/drm/i915/display/intel_hdmi.c
98
assert_hdmi_transcoder_func_disabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hdmi.c
996
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug.c
1001
blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
1006
switch (display->hotplug.stats[pin].state) {
drivers/gpu/drm/i915/display/intel_hotplug.c
1014
MISSING_CASE(display->hotplug.stats[pin].state);
drivers/gpu/drm/i915/display/intel_hotplug.c
1022
queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);
drivers/gpu/drm/i915/display/intel_hotplug.c
1025
static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
1027
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1029
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1036
static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
1038
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1040
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1042
if (drm_WARN_ON(display->drm, hotplug->stats[pin].blocked_count == 0))
drivers/gpu/drm/i915/display/intel_hotplug.c
1076
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug.c
1077
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1083
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1085
if (block_hpd_pin(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
1088
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1090
if (do_flush && hpd_pin_has_pulse(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
1105
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug.c
1110
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1112
if (unblock_hpd_pin(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
1113
queue_work_for_missed_irqs(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
1115
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1128
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug.c
1129
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1135
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1137
if (unblock_hpd_pin(display, pin)) {
drivers/gpu/drm/i915/display/intel_hotplug.c
1144
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1147
void intel_hpd_enable_detection_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
1149
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1150
display->hotplug.detection_work_enabled = true;
drivers/gpu/drm/i915/display/intel_hotplug.c
1151
queue_work_for_missed_irqs(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
1152
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1155
void intel_hpd_disable_detection_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
1157
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1158
display->hotplug.detection_work_enabled = false;
drivers/gpu/drm/i915/display/intel_hotplug.c
1159
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1161
cancel_all_detection_work(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
1164
bool intel_hpd_schedule_detection(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
1169
spin_lock_irqsave(&display->irq.lock, flags);
drivers/gpu/drm/i915/display/intel_hotplug.c
1170
ret = queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0);
drivers/gpu/drm/i915/display/intel_hotplug.c
1171
spin_unlock_irqrestore(&display->irq.lock, flags);
drivers/gpu/drm/i915/display/intel_hotplug.c
1178
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_hotplug.c
1179
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1184
intel_parent_irq_synchronize(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
1185
flush_work(&display->hotplug.dig_port_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
1186
flush_delayed_work(&display->hotplug.hotplug_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
1200
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_hotplug.c
1201
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1226
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
1230
drm_dbg_kms(display->drm, "Disabling HPD storm detection\n");
drivers/gpu/drm/i915/display/intel_hotplug.c
1232
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1237
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1240
flush_delayed_work(&display->hotplug.reenable_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
1261
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_hotplug.c
1264
str_yes_no(display->hotplug.hpd_short_storm_enabled));
drivers/gpu/drm/i915/display/intel_hotplug.c
1281
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_hotplug.c
1282
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
1303
new_state = !HAS_DP_MST(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
1307
drm_dbg_kms(display->drm, "%sabling HPD short storm detection\n",
drivers/gpu/drm/i915/display/intel_hotplug.c
1310
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1315
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
1318
flush_delayed_work(&display->hotplug.reenable_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
1332
void intel_hpd_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
1334
struct dentry *debugfs_root = display->drm->debugfs_root;
drivers/gpu/drm/i915/display/intel_hotplug.c
1337
display, &i915_hpd_storm_ctl_fops);
drivers/gpu/drm/i915/display/intel_hotplug.c
1339
display, &i915_hpd_short_storm_ctl_fops);
drivers/gpu/drm/i915/display/intel_hotplug.c
1341
&display->hotplug.ignore_long_hpd);
drivers/gpu/drm/i915/display/intel_hotplug.c
152
static bool intel_hpd_irq_storm_detect(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug.c
155
struct intel_hotplug *hpd = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
163
(!long_hpd && !display->hotplug.hpd_short_storm_enabled))
drivers/gpu/drm/i915/display/intel_hotplug.c
174
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
178
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
187
static bool detection_work_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
189
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
191
return display->hotplug.detection_work_enabled;
drivers/gpu/drm/i915/display/intel_hotplug.c
195
mod_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)
drivers/gpu/drm/i915/display/intel_hotplug.c
197
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
199
if (!detection_work_enabled(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
202
return mod_delayed_work(display->wq.unordered, work, delay);
drivers/gpu/drm/i915/display/intel_hotplug.c
206
queue_delayed_detection_work(struct intel_display *display, struct delayed_work *work, int delay)
drivers/gpu/drm/i915/display/intel_hotplug.c
208
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
210
if (!detection_work_enabled(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
213
return queue_delayed_work(display->wq.unordered, work, delay);
drivers/gpu/drm/i915/display/intel_hotplug.c
217
queue_detection_work(struct intel_display *display, struct work_struct *work)
drivers/gpu/drm/i915/display/intel_hotplug.c
219
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
221
if (!detection_work_enabled(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
224
return queue_work(display->wq.unordered, work);
drivers/gpu/drm/i915/display/intel_hotplug.c
228
intel_hpd_irq_storm_switch_to_polling(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
234
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
236
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hotplug.c
245
display->hotplug.stats[pin].state != HPD_MARK_DISABLED)
drivers/gpu/drm/i915/display/intel_hotplug.c
248
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
253
display->hotplug.stats[pin].state = HPD_DISABLED;
drivers/gpu/drm/i915/display/intel_hotplug.c
262
drm_kms_helper_poll_reschedule(display->drm);
drivers/gpu/drm/i915/display/intel_hotplug.c
263
mod_delayed_detection_work(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
264
&display->hotplug.reenable_work,
drivers/gpu/drm/i915/display/intel_hotplug.c
271
struct intel_display *display =
drivers/gpu/drm/i915/display/intel_hotplug.c
272
container_of(work, typeof(*display), hotplug.reenable_work.work);
drivers/gpu/drm/i915/display/intel_hotplug.c
278
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
280
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
282
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hotplug.c
286
display->hotplug.stats[pin].state != HPD_DISABLED)
drivers/gpu/drm/i915/display/intel_hotplug.c
290
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
298
if (display->hotplug.stats[pin].state == HPD_DISABLED)
drivers/gpu/drm/i915/display/intel_hotplug.c
299
display->hotplug.stats[pin].state = HPD_ENABLED;
drivers/gpu/drm/i915/display/intel_hotplug.c
302
intel_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
304
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
306
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_hotplug.c
355
static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
359
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_hotplug.c
370
static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
372
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
374
return display->hotplug.stats[pin].blocked_count;
drivers/gpu/drm/i915/display/intel_hotplug.c
377
static u32 get_blocked_hpd_pin_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
383
if (hpd_pin_is_blocked(display, pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
392
struct intel_display *display =
drivers/gpu/drm/i915/display/intel_hotplug.c
394
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
400
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
402
blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
408
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
410
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_hotplug.c
435
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
436
display->hotplug.event_bits |= old_bits;
drivers/gpu/drm/i915/display/intel_hotplug.c
437
queue_delayed_detection_work(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
438
&display->hotplug.hotplug_work, 0);
drivers/gpu/drm/i915/display/intel_hotplug.c
439
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
452
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_hotplug.c
453
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
456
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
459
if (!hpd_pin_is_blocked(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
462
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
470
struct intel_display *display =
drivers/gpu/drm/i915/display/intel_hotplug.c
472
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
482
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
483
drm_dbg_kms(display->drm, "running encoder hotplug functions\n");
drivers/gpu/drm/i915/display/intel_hotplug.c
485
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
487
blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
494
intel_hpd_irq_storm_switch_to_polling(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
496
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
499
if (display->hotplug.ignore_long_hpd) {
drivers/gpu/drm/i915/display/intel_hotplug.c
500
drm_dbg_kms(display->drm, "Ignore HPD flag on - skip encoder hotplug handlers\n");
drivers/gpu/drm/i915/display/intel_hotplug.c
501
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
505
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hotplug.c
524
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
547
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
552
drm_kms_helper_hotplug_event(display->drm);
drivers/gpu/drm/i915/display/intel_hotplug.c
560
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
561
display->hotplug.retry_bits |= retry;
drivers/gpu/drm/i915/display/intel_hotplug.c
563
mod_delayed_detection_work(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
564
&display->hotplug.hotplug_work,
drivers/gpu/drm/i915/display/intel_hotplug.c
566
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
587
void intel_hpd_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug.c
600
spin_lock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
608
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_hotplug.c
620
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
625
if (!hpd_pin_is_blocked(display, pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
630
display->hotplug.long_hpd_pin_mask |= BIT(pin);
drivers/gpu/drm/i915/display/intel_hotplug.c
633
display->hotplug.short_hpd_pin_mask |= BIT(pin);
drivers/gpu/drm/i915/display/intel_hotplug.c
644
if (display->hotplug.stats[pin].state == HPD_DISABLED) {
drivers/gpu/drm/i915/display/intel_hotplug.c
651
drm_WARN_ONCE(display->drm, !HAS_GMCH(display),
drivers/gpu/drm/i915/display/intel_hotplug.c
657
if (display->hotplug.stats[pin].state != HPD_ENABLED)
drivers/gpu/drm/i915/display/intel_hotplug.c
668
display->hotplug.event_bits |= BIT(pin);
drivers/gpu/drm/i915/display/intel_hotplug.c
671
if (!hpd_pin_is_blocked(display, pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
675
if (intel_hpd_irq_storm_detect(display, pin, long_hpd)) {
drivers/gpu/drm/i915/display/intel_hotplug.c
676
display->hotplug.event_bits &= ~BIT(pin);
drivers/gpu/drm/i915/display/intel_hotplug.c
687
intel_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
696
queue_work(display->hotplug.dp_wq, &display->hotplug.dig_port_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
698
queue_delayed_detection_work(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
699
&display->hotplug.hotplug_work, 0);
drivers/gpu/drm/i915/display/intel_hotplug.c
701
spin_unlock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
718
void intel_hpd_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
722
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
726
display->hotplug.stats[i].count = 0;
drivers/gpu/drm/i915/display/intel_hotplug.c
727
display->hotplug.stats[i].state = HPD_ENABLED;
drivers/gpu/drm/i915/display/intel_hotplug.c
734
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
735
intel_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
736
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
739
static void i915_hpd_poll_detect_connectors(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
746
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
748
if (!display->drm->mode_config.poll_enabled)
drivers/gpu/drm/i915/display/intel_hotplug.c
751
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hotplug.c
769
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
777
drm_kms_helper_hotplug_event(display->drm);
drivers/gpu/drm/i915/display/intel_hotplug.c
784
struct intel_display *display =
drivers/gpu/drm/i915/display/intel_hotplug.c
785
container_of(work, typeof(*display), hotplug.poll_init_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
791
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
793
enabled = READ_ONCE(display->hotplug.poll_enabled);
drivers/gpu/drm/i915/display/intel_hotplug.c
801
wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
803
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug.c
804
READ_ONCE(display->hotplug.poll_enabled));
drivers/gpu/drm/i915/display/intel_hotplug.c
805
cancel_work(&display->hotplug.poll_init_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
808
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
810
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hotplug.c
818
if (display->hotplug.stats[pin].state == HPD_DISABLED)
drivers/gpu/drm/i915/display/intel_hotplug.c
829
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
832
drm_kms_helper_poll_reschedule(display->drm);
drivers/gpu/drm/i915/display/intel_hotplug.c
834
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_hotplug.c
841
i915_hpd_poll_detect_connectors(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
843
intel_display_power_put(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
865
void intel_hpd_poll_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
867
if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
870
WRITE_ONCE(display->hotplug.poll_enabled, true);
drivers/gpu/drm/i915/display/intel_hotplug.c
878
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
879
queue_detection_work(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
880
&display->hotplug.poll_init_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
881
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
903
void intel_hpd_poll_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
907
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
910
for_each_intel_dp(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_hotplug.c
913
WRITE_ONCE(display->hotplug.poll_enabled, false);
drivers/gpu/drm/i915/display/intel_hotplug.c
915
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
916
queue_detection_work(display,
drivers/gpu/drm/i915/display/intel_hotplug.c
917
&display->hotplug.poll_init_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
918
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
921
void intel_hpd_poll_fini(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
927
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_hotplug.c
935
void intel_hpd_init_early(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
937
INIT_DELAYED_WORK(&display->hotplug.hotplug_work,
drivers/gpu/drm/i915/display/intel_hotplug.c
939
INIT_WORK(&display->hotplug.dig_port_work, i915_digport_work_func);
drivers/gpu/drm/i915/display/intel_hotplug.c
940
INIT_WORK(&display->hotplug.poll_init_work, i915_hpd_poll_init_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
941
INIT_DELAYED_WORK(&display->hotplug.reenable_work,
drivers/gpu/drm/i915/display/intel_hotplug.c
944
display->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
drivers/gpu/drm/i915/display/intel_hotplug.c
951
display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(display);
drivers/gpu/drm/i915/display/intel_hotplug.c
954
static bool cancel_all_detection_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
958
if (cancel_delayed_work_sync(&display->hotplug.hotplug_work))
drivers/gpu/drm/i915/display/intel_hotplug.c
960
if (cancel_work_sync(&display->hotplug.poll_init_work))
drivers/gpu/drm/i915/display/intel_hotplug.c
962
if (cancel_delayed_work_sync(&display->hotplug.reenable_work))
drivers/gpu/drm/i915/display/intel_hotplug.c
968
void intel_hpd_cancel_work(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
970
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
973
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
975
display->hotplug.long_hpd_pin_mask = 0;
drivers/gpu/drm/i915/display/intel_hotplug.c
976
display->hotplug.short_hpd_pin_mask = 0;
drivers/gpu/drm/i915/display/intel_hotplug.c
977
display->hotplug.event_bits = 0;
drivers/gpu/drm/i915/display/intel_hotplug.c
978
display->hotplug.retry_bits = 0;
drivers/gpu/drm/i915/display/intel_hotplug.c
980
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.c
982
cancel_work_sync(&display->hotplug.dig_port_work);
drivers/gpu/drm/i915/display/intel_hotplug.c
988
if (cancel_all_detection_work(display))
drivers/gpu/drm/i915/display/intel_hotplug.c
989
drm_dbg_kms(display->drm, "Hotplug detection work still active\n");
drivers/gpu/drm/i915/display/intel_hotplug.c
992
static void queue_work_for_missed_irqs(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug.c
994
struct intel_hotplug *hotplug = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug.c
999
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug.h
17
void intel_hpd_poll_enable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
18
void intel_hpd_poll_disable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
19
void intel_hpd_poll_fini(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
22
void intel_hpd_irq_handler(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug.h
25
void intel_hpd_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
26
void intel_hpd_init_early(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
27
void intel_hpd_cancel_work(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
32
void intel_hpd_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
34
void intel_hpd_enable_detection_work(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
35
void intel_hpd_disable_detection_work(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug.h
36
bool intel_hpd_schedule_detection(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1000
static void mtp_ddi_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1002
intel_de_rmw(display, SHOTPLUG_CTL_DDI,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1003
intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1004
intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1009
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1011
intel_de_rmw(display, SHOTPLUG_CTL_DDI,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1016
static void mtp_tc_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1018
intel_de_rmw(display, SHOTPLUG_CTL_TC,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1019
intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1020
intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1025
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1027
intel_de_rmw(display, SHOTPLUG_CTL_TC,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1032
static void mtp_hpd_invert(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1043
intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1048
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1050
mtp_hpd_invert(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1055
static void mtp_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1059
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1060
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1066
intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1068
mtp_hpd_invert(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1069
ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1071
mtp_ddi_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1072
mtp_tc_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1075
static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1079
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1080
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1082
ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1084
mtp_ddi_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1085
mtp_tc_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1093
static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1102
intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1108
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1110
_xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1113
static void xelpdp_pica_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1121
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1125
_xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1134
static void xelpdp_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1138
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1139
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1141
intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1143
intel_de_posting_read(display, PICAINTERRUPT_IMR);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1145
xelpdp_pica_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1147
if (INTEL_PCH_TYPE(display) >= PCH_LNL)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1148
xe2lpd_sde_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1149
else if (INTEL_PCH_TYPE(display) >= PCH_MTL)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1150
mtp_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1189
static void spt_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1192
if (HAS_PCH_CNP(display)) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1193
intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1198
intel_de_rmw(display, PCH_PORT_HOTPLUG,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1199
intel_hpd_hotplug_mask(display, spt_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1200
intel_hpd_hotplug_enables(display, spt_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1202
intel_de_rmw(display, PCH_PORT_HOTPLUG2,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1203
intel_hpd_hotplug_mask(display, spt_hotplug2_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1204
intel_hpd_hotplug_enables(display, spt_hotplug2_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1209
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1212
if (HAS_PCH_CNP(display)) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1213
intel_de_rmw(display, SOUTH_CHICKEN1,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1218
intel_de_rmw(display, PCH_PORT_HOTPLUG,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1222
intel_de_rmw(display, PCH_PORT_HOTPLUG2,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1227
static void spt_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1231
if (INTEL_PCH_TYPE(display) >= PCH_CNP)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1232
intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1234
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1235
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1237
ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1239
spt_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1264
static void ilk_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1271
intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1272
intel_hpd_hotplug_mask(display, ilk_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1273
intel_hpd_hotplug_enables(display, ilk_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1278
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1280
intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1287
static void ilk_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1291
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1292
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1294
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1295
bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1297
ilk_update_display_irq(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1299
ilk_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1301
ibx_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1343
static void bxt_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1345
intel_de_rmw(display, PCH_PORT_HOTPLUG,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1346
intel_hpd_hotplug_mask(display, bxt_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1347
intel_hpd_hotplug_enables(display, bxt_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1352
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1354
intel_de_rmw(display, PCH_PORT_HOTPLUG,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1359
static void bxt_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
136
static void intel_hpd_init_pins(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1363
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1364
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1366
bdw_update_port_irq(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1368
bxt_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1371
static void g45_hpd_peg_band_gap_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1378
intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
138
struct intel_hotplug *hpd = &display->hotplug;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1383
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1386
if (display->platform.g45)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1387
g45_hpd_peg_band_gap_wa(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1390
i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1393
static void i915_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1397
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
140
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1403
hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1408
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
141
if (display->platform.g4x || display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1412
if (display->platform.g45)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1413
g45_hpd_peg_band_gap_wa(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1416
i915_hotplug_interrupt_update_locked(display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
142
display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1425
void (*hpd_irq_setup)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1448
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1450
if (display->hotplug.funcs)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1451
display->hotplug.funcs->hpd_enable_detection(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1454
void intel_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1456
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1457
!display->irq.vlv_display_irqs_enabled)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1460
if (display->hotplug.funcs)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1461
display->hotplug.funcs->hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1464
void intel_hotplug_irq_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1466
intel_hpd_init_pins(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1468
intel_hpd_init_early(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1470
if (HAS_GMCH(display)) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1471
if (HAS_HOTPLUG(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1472
display->hotplug.funcs = &i915_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1474
if (HAS_PCH_DG2(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1475
display->hotplug.funcs = &icp_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1476
else if (HAS_PCH_DG1(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1477
display->hotplug.funcs = &dg1_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1478
else if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1479
display->hotplug.funcs = &xelpdp_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1480
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1481
display->hotplug.funcs = &gen11_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1482
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1483
display->hotplug.funcs = &bxt_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1484
else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1485
display->hotplug.funcs = &icp_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1486
else if (INTEL_PCH_TYPE(display) >= PCH_SPT)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1487
display->hotplug.funcs = &spt_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1489
display->hotplug.funcs = &ilk_hpd_funcs;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
149
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
151
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
153
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
155
else if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
157
else if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
159
else if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
164
if ((INTEL_PCH_TYPE(display) < PCH_DG1) &&
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
165
(!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display)))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
168
if (INTEL_PCH_TYPE(display) >= PCH_MTL)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
170
else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
172
else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
174
else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
176
else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
178
else if (HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
181
MISSING_CASE(INTEL_PCH_TYPE(display));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
185
void i915_hotplug_interrupt_update_locked(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
188
lockdep_assert_held(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
189
drm_WARN_ON(display->drm, bits & ~mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
191
intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
206
void i915_hotplug_interrupt_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
210
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
211
i915_hotplug_interrupt_update_locked(display, mask, bits);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
212
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
343
static void intel_get_hpd_pins(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
363
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
368
static u32 intel_hpd_enabled_irqs(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
374
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
375
if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
381
static u32 intel_hpd_hotplug_irqs(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
387
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
393
static u32 intel_hpd_hotplug_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
405
static u32 intel_hpd_hotplug_enables(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
411
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
417
u32 i9xx_hpd_irq_ack(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
422
if (!HAS_HOTPLUG(display))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
425
if (display->platform.g4x ||
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
426
display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
442
u32 tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
443
PORT_HOTPLUG_STAT(display)) & hotplug_status_mask;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
449
intel_de_write(display, PORT_HOTPLUG_STAT(display),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
453
drm_WARN_ONCE(display->drm, 1,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
455
intel_de_read(display, PORT_HOTPLUG_STAT(display)));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
460
void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
465
if (display->platform.g4x ||
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
466
display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
472
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
474
display->hotplug.hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
477
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
480
if ((display->platform.g4x ||
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
481
display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
483
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
486
void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
496
dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
505
intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
509
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
511
display->hotplug.pch_hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
514
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
517
void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
521
u32 trigger_aux = iir & xelpdp_pica_aux_mask(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
527
if (!(display->hotplug.hpd[pin] & hotplug_trigger))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
532
val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
533
intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
540
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
544
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
548
intel_dp_aux_irq_handler(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
551
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
555
void icp_irq_handler(struct intel_display *display, u32 pch_iir)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
565
spin_lock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
566
dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
567
spin_unlock(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
569
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
571
display->hotplug.pch_hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
578
dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
580
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
582
display->hotplug.pch_hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
587
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
590
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
593
void spt_irq_handler(struct intel_display *display, u32 pch_iir)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
603
dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
605
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
607
display->hotplug.pch_hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
614
dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
616
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
618
display->hotplug.pch_hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
623
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
626
intel_gmbus_irq_handler(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
629
void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
633
dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
635
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
637
display->hotplug.hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
640
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
643
void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
647
dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
649
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
651
display->hotplug.hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
654
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
657
void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
666
dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
668
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
670
display->hotplug.hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
677
dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
679
intel_get_hpd_pins(display, &pin_mask, &long_mask,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
681
display->hotplug.hpd,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
686
intel_hpd_irq_handler(display, pin_mask, long_mask);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
688
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
710
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
718
return HAS_PCH_LPT_LP(display) ?
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
734
static void ibx_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
741
intel_de_rmw(display, PCH_PORT_HOTPLUG,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
742
intel_hpd_hotplug_mask(display, ibx_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
743
intel_hpd_hotplug_enables(display, ibx_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
748
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
750
intel_de_rmw(display, PCH_PORT_HOTPLUG,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
755
static void ibx_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
759
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
760
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
762
ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
764
ibx_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
805
static void icp_ddi_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
807
intel_de_rmw(display, SHOTPLUG_CTL_DDI,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
808
intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
809
intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
814
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
816
intel_de_rmw(display, SHOTPLUG_CTL_DDI,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
821
static void icp_tc_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
823
intel_de_rmw(display, SHOTPLUG_CTL_TC,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
824
intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
825
intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
830
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
832
intel_de_rmw(display, SHOTPLUG_CTL_TC,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
843
static void icp_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
847
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
848
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
854
intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
856
ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
858
icp_ddi_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
859
icp_tc_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
882
static void dg1_hpd_invert(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
888
intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
893
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
895
dg1_hpd_invert(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
899
static void dg1_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
901
dg1_hpd_invert(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
902
icp_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
905
static void gen11_tc_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
907
intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
908
intel_hpd_hotplug_mask(display, gen11_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
909
intel_hpd_hotplug_enables(display, gen11_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
914
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
916
intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
921
static void gen11_tbt_hpd_detection_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
923
intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
924
intel_hpd_hotplug_mask(display, gen11_hotplug_mask),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
925
intel_hpd_hotplug_enables(display, gen11_hotplug_enables));
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
930
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
932
intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
939
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
944
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
948
static void gen11_hpd_irq_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
952
enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
953
hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
955
intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs,
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
957
intel_de_posting_read(display, GEN11_DE_HPD_IMR);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
959
gen11_tc_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
960
gen11_tbt_hpd_detection_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
962
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
963
icp_hpd_irq_setup(display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
14
u32 i9xx_hpd_irq_ack(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
16
void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
17
void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
18
void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
19
void gen11_hpd_irq_handler(struct intel_display *display, u32 iir);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
20
void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
21
void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
22
void icp_irq_handler(struct intel_display *display, u32 pch_iir);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
23
void spt_irq_handler(struct intel_display *display, u32 pch_iir);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
25
void i915_hotplug_interrupt_update_locked(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
27
void i915_hotplug_interrupt_update(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
31
void intel_hpd_irq_setup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hotplug_irq.h
33
void intel_hotplug_irq_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hti.c
14
void intel_hti_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hti.c
20
if (DISPLAY_INFO(display)->has_hti)
drivers/gpu/drm/i915/display/intel_hti.c
21
display->hti.state = intel_de_read(display, HDPORT_STATE);
drivers/gpu/drm/i915/display/intel_hti.c
24
bool intel_hti_uses_phy(struct intel_display *display, enum phy phy)
drivers/gpu/drm/i915/display/intel_hti.c
26
if (drm_WARN_ON(display->drm, phy == PHY_NONE))
drivers/gpu/drm/i915/display/intel_hti.c
29
return display->hti.state & HDPORT_ENABLED &&
drivers/gpu/drm/i915/display/intel_hti.c
30
display->hti.state & HDPORT_DDI_USED(phy);
drivers/gpu/drm/i915/display/intel_hti.c
33
u32 intel_hti_dpll_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_hti.c
35
if (!(display->hti.state & HDPORT_ENABLED))
drivers/gpu/drm/i915/display/intel_hti.c
42
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state);
drivers/gpu/drm/i915/display/intel_hti.h
14
void intel_hti_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_hti.h
15
bool intel_hti_uses_phy(struct intel_display *display, enum phy phy);
drivers/gpu/drm/i915/display/intel_hti.h
16
u32 intel_hti_dpll_mask(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_initial_plane.c
100
if (intel_fb_modifier_uses_dpt(display, fb->modifier)) {
drivers/gpu/drm/i915/display/intel_initial_plane.c
101
drm_dbg_kms(display->drm, "DPT not supported for initial FB\n");
drivers/gpu/drm/i915/display/intel_initial_plane.c
110
drm_dbg_kms(display->drm, "90/270 degree rotation not supported for initial FB\n");
drivers/gpu/drm/i915/display/intel_initial_plane.c
114
return display->parent->initial_plane->alloc_obj(display->drm, plane_config);
drivers/gpu/drm/i915/display/intel_initial_plane.c
121
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_initial_plane.c
137
if (intel_alloc_initial_plane_obj(display, plane_config)) {
drivers/gpu/drm/i915/display/intel_initial_plane.c
155
ret = display->parent->initial_plane->setup(plane->base.state, plane_config, fb, vma);
drivers/gpu/drm/i915/display/intel_initial_plane.c
190
static void plane_config_fini(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_initial_plane.c
203
display->parent->initial_plane->config_fini(plane_config);
drivers/gpu/drm/i915/display/intel_initial_plane.c
206
void intel_initial_plane_config(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_initial_plane.c
211
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_initial_plane.c
227
display->modeset.funcs->get_initial_plane_config(crtc, plane_config);
drivers/gpu/drm/i915/display/intel_initial_plane.c
235
if (display->modeset.funcs->fixup_initial_plane_config(crtc, plane_config))
drivers/gpu/drm/i915/display/intel_initial_plane.c
238
plane_config_fini(display, plane_config);
drivers/gpu/drm/i915/display/intel_initial_plane.c
27
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_initial_plane.c
32
if (intel_parent_irq_enabled(display)) {
drivers/gpu/drm/i915/display/intel_initial_plane.c
37
start_ts = intel_de_read(display, PIPE_FRMTMSTMP(crtc->pipe));
drivers/gpu/drm/i915/display/intel_initial_plane.c
39
ret = poll_timeout_us(end_ts = intel_de_read(display, PIPE_FRMTMSTMP(crtc->pipe)),
drivers/gpu/drm/i915/display/intel_initial_plane.c
42
drm_warn(display->drm, "[CRTC:%d:%s] early vblank wait timed out\n",
drivers/gpu/drm/i915/display/intel_initial_plane.c
50
struct intel_display *display = to_intel_display(this);
drivers/gpu/drm/i915/display/intel_initial_plane.c
53
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_initial_plane.c
76
intel_alloc_initial_plane_obj(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_initial_plane.c
87
if (intel_parent_has_fenced_regions(display))
drivers/gpu/drm/i915/display/intel_initial_plane.c
91
drm_dbg_kms(display->drm, "Unsupported modifier for initial FB: 0x%llx\n",
drivers/gpu/drm/i915/display/intel_initial_plane.h
12
void intel_initial_plane_config(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_link_bw.c
106
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_link_bw.c
111
for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) {
drivers/gpu/drm/i915/display/intel_link_bw.c
220
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_link_bw.c
229
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_link_bw.c
262
assert_link_limit_change_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_link_bw.c
270
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_link_bw.c
275
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_link_bw.c
277
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_link_bw.c
288
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_link_bw.c
316
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_link_bw.c
324
if (!assert_link_limit_change_valid(display, &old_limits, new_limits))
drivers/gpu/drm/i915/display/intel_link_bw.c
419
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_link_bw.c
426
return HAS_DSC_MST(display);
drivers/gpu/drm/i915/display/intel_link_bw.c
428
return HAS_DSC(display);
drivers/gpu/drm/i915/display/intel_link_bw.c
439
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_link_bw.c
456
bpp_x16 > fxp_q4_from_int(intel_display_max_pipe_bpp(display))))
drivers/gpu/drm/i915/display/intel_link_bw.c
459
err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_link_bw.c
465
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_link_bw.c
475
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_link_bw.c
487
if (HAS_FDI(display))
drivers/gpu/drm/i915/display/intel_link_bw.c
56
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_link_bw.c
61
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_link_bw.c
62
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_load_detect.c
114
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_load_detect.c
121
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_load_detect.c
122
restore_state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_load_detect.c
167
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_load_detect.c
175
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_load_detect.c
207
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_load_detect.c
213
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_load_detect.c
222
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_load_detect.c
52
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_load_detect.c
57
struct drm_mode_config *config = &display->drm->mode_config;
drivers/gpu/drm/i915/display/intel_load_detect.c
63
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_load_detect.c
67
drm_WARN_ON(display->drm, !drm_modeset_is_locked(&config->connection_mutex));
drivers/gpu/drm/i915/display/intel_load_detect.c
92
for_each_intel_crtc(display, possible_crtc) {
drivers/gpu/drm/i915/display/intel_lpe_audio.c
100
rsc[0].start = display->audio.lpe.irq;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
101
rsc[0].end = display->audio.lpe.irq;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
112
pinfo.parent = display->drm->dev;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
121
pdata->num_pipes = INTEL_NUM_PIPES(display);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
122
pdata->num_ports = display->platform.cherryview ? 3 : 2; /* B,C,D or B,C */
drivers/gpu/drm/i915/display/intel_lpe_audio.c
133
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
143
static void lpe_audio_platdev_destroy(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
153
platform_device_unregister(display->audio.lpe.platdev);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
170
static int lpe_audio_irq_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
172
int irq = display->audio.lpe.irq;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
181
static bool lpe_audio_detect(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
185
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_lpe_audio.c
195
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
203
static int lpe_audio_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
207
display->audio.lpe.irq = irq_alloc_desc(0);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
208
if (display->audio.lpe.irq < 0) {
drivers/gpu/drm/i915/display/intel_lpe_audio.c
209
drm_err(display->drm, "Failed to allocate IRQ desc: %d\n",
drivers/gpu/drm/i915/display/intel_lpe_audio.c
210
display->audio.lpe.irq);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
211
ret = display->audio.lpe.irq;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
215
drm_dbg(display->drm, "irq = %d\n", display->audio.lpe.irq);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
217
ret = lpe_audio_irq_init(display);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
220
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
226
display->audio.lpe.platdev = lpe_audio_platdev_create(display);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
228
if (IS_ERR(display->audio.lpe.platdev)) {
drivers/gpu/drm/i915/display/intel_lpe_audio.c
229
ret = PTR_ERR(display->audio.lpe.platdev);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
230
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
239
intel_de_write(display, VLV_AUD_CHICKEN_BIT_REG,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
244
irq_free_desc(display->audio.lpe.irq);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
246
display->audio.lpe.irq = -1;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
247
display->audio.lpe.platdev = NULL;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
258
void intel_lpe_audio_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
262
if (!HAS_LPE_AUDIO(display))
drivers/gpu/drm/i915/display/intel_lpe_audio.c
265
ret = generic_handle_irq(display->audio.lpe.irq);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
267
drm_err_ratelimited(display->drm,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
279
int intel_lpe_audio_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
283
if (lpe_audio_detect(display)) {
drivers/gpu/drm/i915/display/intel_lpe_audio.c
284
ret = lpe_audio_setup(display);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
286
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
299
void intel_lpe_audio_teardown(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
301
if (!HAS_LPE_AUDIO(display))
drivers/gpu/drm/i915/display/intel_lpe_audio.c
304
lpe_audio_platdev_destroy(display);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
306
irq_free_desc(display->audio.lpe.irq);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
308
display->audio.lpe.irq = -1;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
309
display->audio.lpe.platdev = NULL;
drivers/gpu/drm/i915/display/intel_lpe_audio.c
324
void intel_lpe_audio_notify(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lpe_audio.c
333
if (!HAS_LPE_AUDIO(display))
drivers/gpu/drm/i915/display/intel_lpe_audio.c
336
pdata = dev_get_platdata(&display->audio.lpe.platdev->dev);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
341
audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port));
drivers/gpu/drm/i915/display/intel_lpe_audio.c
350
intel_de_write(display, VLV_AUD_PORT_EN_DBG(port),
drivers/gpu/drm/i915/display/intel_lpe_audio.c
359
intel_de_write(display, VLV_AUD_PORT_EN_DBG(port),
drivers/gpu/drm/i915/display/intel_lpe_audio.c
364
pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B);
drivers/gpu/drm/i915/display/intel_lpe_audio.c
79
#define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
82
lpe_audio_platdev_create(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.c
84
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_lpe_audio.h
16
int intel_lpe_audio_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lpe_audio.h
17
void intel_lpe_audio_teardown(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lpe_audio.h
18
void intel_lpe_audio_irq_handler(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lpe_audio.h
19
void intel_lpe_audio_notify(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lpe_audio.h
23
static inline int intel_lpe_audio_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.h
27
static inline void intel_lpe_audio_teardown(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.h
30
static inline void intel_lpe_audio_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lpe_audio.h
33
static inline void intel_lpe_audio_notify(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lspcon.c
108
drm_dbg_kms(display->drm, "Vendor: Mega Chips\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
113
drm_dbg_kms(display->drm, "Vendor: Parade Tech\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
117
drm_err(display->drm, "Invalid/Unknown vendor OUI\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
136
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
144
drm_dbg_kms(display->drm, "HDR capability detection failed\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
147
drm_dbg_kms(display->drm, "LSPCON capable of HDR\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
157
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
162
drm_dbg_kms(display->drm, "Error reading LSPCON mode\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
184
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
193
drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n",
drivers/gpu/drm/i915/display/intel_lspcon.c
202
drm_err(display->drm, "LSPCON mode hasn't settled\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
205
drm_dbg_kms(display->drm, "Current LSPCON mode %s\n",
drivers/gpu/drm/i915/display/intel_lspcon.c
215
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
222
drm_err(display->drm, "Error reading LSPCON mode\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
227
drm_dbg_kms(display->drm, "Current mode = desired LSPCON mode\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
234
drm_err(display->drm, "LSPCON mode change failed\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
239
drm_dbg_kms(display->drm, "LSPCON mode changed done\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
246
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
251
drm_dbg_kms(display->drm, "Native AUX CH down\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
255
drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n",
drivers/gpu/drm/i915/display/intel_lspcon.c
264
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
284
drm_dbg_kms(display->drm, "No LSPCON detected, found %s\n",
drivers/gpu/drm/i915/display/intel_lspcon.c
290
drm_dbg_kms(display->drm, "LSPCON detected\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
300
drm_err(display->drm, "LSPCON mode change to PCON failed\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
310
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
316
drm_dbg_kms(display->drm, "LSPCON recovering in PCON mode after %u ms\n",
drivers/gpu/drm/i915/display/intel_lspcon.c
327
drm_dbg_kms(display->drm, "LSPCON DP descriptor mismatch after resume\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
498
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lspcon.c
513
drm_dbg_kms(display->drm, "Update HDR metadata for lspcon\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
522
drm_err(display->drm, "Failed to write infoframes\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
543
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lspcon.c
553
drm_err(display->drm, "Writing infoframes while LSPCON disabled ?\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
563
drm_err(display->drm, "couldn't fill AVI infoframe\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
604
drm_err(display->drm, "Failed to pack AVI IF\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
645
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lspcon.c
661
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_lspcon.c
662
HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
drivers/gpu/drm/i915/display/intel_lspcon.c
681
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_lspcon.c
690
drm_err(display->drm, "Failed to probe lspcon\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
695
drm_err(display->drm, "LSPCON DPCD read failed\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
700
drm_err(display->drm, "LSPCON vendor detection failed\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
706
drm_dbg_kms(display->drm, "Success: LSPCON init\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
727
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_lspcon.c
736
drm_err(display->drm, "LSPCON init failed on port %c\n",
drivers/gpu/drm/i915/display/intel_lspcon.c
753
drm_err(display->drm, "LSPCON resume failed\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
755
drm_dbg_kms(display->drm, "LSPCON resume success\n");
drivers/gpu/drm/i915/display/intel_lspcon.c
92
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_lspcon.c
97
drm_err(display->drm, "Can't read description\n");
drivers/gpu/drm/i915/display/intel_lt_phy.c
1000
assert_dc_off(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lt_phy.c
1004
enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1005
drm_WARN_ON(display->drm, !enabled);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1013
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1019
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1022
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1029
intel_de_rmw(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 0, 0);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1031
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1042
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1068
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1072
assert_dc_off(display);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1083
drm_err_once(display->drm,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1120
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1136
intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1139
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1146
intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1149
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1153
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1156
drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
1159
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1163
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1166
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1169
drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
1172
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1175
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
1178
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1207
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1210
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1222
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1224
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1228
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1230
XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
drivers/gpu/drm/i915/display/intel_lt_phy.c
1295
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1300
wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1307
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1311
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1335
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1338
if (intel_panel_use_ssc(display)) {
drivers/gpu/drm/i915/display/intel_lt_phy.c
1648
intel_lt_phy_calc_hdmi_port_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1701
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1715
intel_lt_phy_calc_port_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1734
clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1736
drm_WARN_ON(display->drm, "Unsupported LT PHY Mode!\n");
drivers/gpu/drm/i915/display/intel_lt_phy.c
1748
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1759
int clock = intel_lt_phy_calc_port_clock(display, tables[i].state);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1761
drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
drivers/gpu/drm/i915/display/intel_lt_phy.c
1911
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1912
int port_clock = intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1964
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1968
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1971
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
1979
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1982
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1987
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
1990
drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
1997
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2002
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2015
if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2018
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
2022
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2026
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2043
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2064
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2069
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2073
if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2076
drm_warn(display->drm, "PHY %c failed to reset lane\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
2080
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2089
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2093
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2096
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2099
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
drivers/gpu/drm/i915/display/intel_lt_phy.c
2107
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2108
XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_FORWARD_CLOCK_UNGATE, 0);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2111
intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
drivers/gpu/drm/i915/display/intel_lt_phy.c
2120
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2135
if (drm_WARN_ON_ONCE(display->drm, !trans)) {
drivers/gpu/drm/i915/display/intel_lt_phy.c
2214
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2216
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
drivers/gpu/drm/i915/display/intel_lt_phy.c
2220
bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2286
static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2295
clock = intel_lt_phy_calc_port_clock(display, pll_state);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2300
drm_warn(display->drm,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2309
p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2317
static void intel_lt_phy_pll_verify_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2322
intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->state, true);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2330
intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2333
static void intel_lt_phy_pll_verify_tables(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2339
intel_lt_phy_pll_verify_params(display, &tables[i]);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2342
void intel_lt_phy_verify_plls(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lt_phy.c
2344
intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2345
intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
drivers/gpu/drm/i915/display/intel_lt_phy.c
2346
intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
drivers/gpu/drm/i915/display/intel_lt_phy.c
992
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lt_phy.c
994
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_lt_phy.h
30
int intel_lt_phy_calc_port_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.h
39
bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lt_phy.h
51
void intel_lt_phy_verify_plls(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lvds.c
1001
drm_dbg_kms(display->drm, "detected %s-link lvds configuration\n",
drivers/gpu/drm/i915/display/intel_lvds.c
1009
drm_dbg_kms(display->drm, "No LVDS modes found, disabling.\n");
drivers/gpu/drm/i915/display/intel_lvds.c
106
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lvds.c
111
wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain);
drivers/gpu/drm/i915/display/intel_lvds.c
115
ret = intel_lvds_port_enabled(display, lvds_encoder->reg, pipe);
drivers/gpu/drm/i915/display/intel_lvds.c
117
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_lvds.c
125
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lvds.c
131
tmp = intel_de_read(display, lvds_encoder->reg);
drivers/gpu/drm/i915/display/intel_lvds.c
143
if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_lvds.c
148
if (DISPLAY_VER(display) < 4) {
drivers/gpu/drm/i915/display/intel_lvds.c
149
tmp = intel_de_read(display, PFIT_CONTROL(display));
drivers/gpu/drm/i915/display/intel_lvds.c
157
static void intel_lvds_pps_get_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lvds.c
162
pps->powerdown_on_reset = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_lvds.c
163
PP_CONTROL(display, 0)) & PANEL_POWER_RESET;
drivers/gpu/drm/i915/display/intel_lvds.c
165
val = intel_de_read(display, PP_ON_DELAYS(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
170
val = intel_de_read(display, PP_OFF_DELAYS(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
174
val = intel_de_read(display, PP_DIVISOR(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
187
if (DISPLAY_VER(display) < 5 &&
drivers/gpu/drm/i915/display/intel_lvds.c
192
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
203
drm_dbg(display->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d "
drivers/gpu/drm/i915/display/intel_lvds.c
211
static void intel_lvds_pps_init_hw(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lvds.c
216
val = intel_de_read(display, PP_CONTROL(display, 0));
drivers/gpu/drm/i915/display/intel_lvds.c
217
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
221
intel_de_write(display, PP_CONTROL(display, 0), val);
drivers/gpu/drm/i915/display/intel_lvds.c
223
intel_de_write(display, PP_ON_DELAYS(display, 0),
drivers/gpu/drm/i915/display/intel_lvds.c
228
intel_de_write(display, PP_OFF_DELAYS(display, 0),
drivers/gpu/drm/i915/display/intel_lvds.c
232
intel_de_write(display, PP_DIVISOR(display, 0),
drivers/gpu/drm/i915/display/intel_lvds.c
243
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_lvds.c
250
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_lvds.c
251
assert_fdi_rx_pll_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_lvds.c
252
assert_dpll_disabled(display, crtc_state->intel_dpll);
drivers/gpu/drm/i915/display/intel_lvds.c
254
assert_pll_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_lvds.c
257
intel_lvds_pps_init_hw(display, &lvds_encoder->init_pps);
drivers/gpu/drm/i915/display/intel_lvds.c
262
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_lvds.c
297
if (DISPLAY_VER(display) == 4) {
drivers/gpu/drm/i915/display/intel_lvds.c
313
intel_de_write(display, lvds_encoder->reg, temp);
drivers/gpu/drm/i915/display/intel_lvds.c
324
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lvds.c
327
intel_de_rmw(display, lvds_encoder->reg, 0, LVDS_PORT_EN);
drivers/gpu/drm/i915/display/intel_lvds.c
329
intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON);
drivers/gpu/drm/i915/display/intel_lvds.c
330
intel_de_posting_read(display, lvds_encoder->reg);
drivers/gpu/drm/i915/display/intel_lvds.c
332
if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON, 5000))
drivers/gpu/drm/i915/display/intel_lvds.c
333
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
344
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lvds.c
347
intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0);
drivers/gpu/drm/i915/display/intel_lvds.c
348
if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON, 1000))
drivers/gpu/drm/i915/display/intel_lvds.c
349
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
352
intel_de_rmw(display, lvds_encoder->reg, LVDS_PORT_EN, 0);
drivers/gpu/drm/i915/display/intel_lvds.c
353
intel_de_posting_read(display, lvds_encoder->reg);
drivers/gpu/drm/i915/display/intel_lvds.c
385
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lvds.c
387
if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
drivers/gpu/drm/i915/display/intel_lvds.c
388
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
396
struct intel_display *display = to_intel_display(_connector->dev);
drivers/gpu/drm/i915/display/intel_lvds.c
398
int max_pixclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_lvds.c
402
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_lvds.c
420
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_lvds.c
429
if (DISPLAY_VER(display) < 4 && crtc->pipe == 0) {
drivers/gpu/drm/i915/display/intel_lvds.c
430
drm_err(display->drm, "Can't support LVDS on pipe A\n");
drivers/gpu/drm/i915/display/intel_lvds.c
434
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_lvds.c
447
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
775
struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lvds.c
779
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_lvds.c
787
bool intel_is_dual_link_lvds(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lvds.c
789
struct intel_encoder *encoder = intel_get_lvds_encoder(display);
drivers/gpu/drm/i915/display/intel_lvds.c
796
struct intel_display *display = to_intel_display(&lvds_encoder->base);
drivers/gpu/drm/i915/display/intel_lvds.c
803
if (display->params.lvds_channel_mode > 0)
drivers/gpu/drm/i915/display/intel_lvds.c
804
return display->params.lvds_channel_mode == 2;
drivers/gpu/drm/i915/display/intel_lvds.c
819
val = intel_de_read(display, lvds_encoder->reg);
drivers/gpu/drm/i915/display/intel_lvds.c
820
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_lvds.c
842
void intel_lvds_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lvds.c
854
drm_WARN(display->drm, !display->vbt.int_lvds_support,
drivers/gpu/drm/i915/display/intel_lvds.c
859
if (!display->vbt.int_lvds_support) {
drivers/gpu/drm/i915/display/intel_lvds.c
860
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
865
if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_lvds.c
87
bool intel_lvds_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lvds.c
870
lvds = intel_de_read(display, lvds_reg);
drivers/gpu/drm/i915/display/intel_lvds.c
872
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_lvds.c
878
if (!intel_bios_is_lvds_present(display, &ddc_pin)) {
drivers/gpu/drm/i915/display/intel_lvds.c
880
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
884
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_lvds.c
901
drm_connector_init_with_ddc(display->drm, &connector->base,
drivers/gpu/drm/i915/display/intel_lvds.c
904
intel_gmbus_get_adapter(display, ddc_pin));
drivers/gpu/drm/i915/display/intel_lvds.c
906
drm_encoder_init(display->drm, &encoder->base, &intel_lvds_enc_funcs,
drivers/gpu/drm/i915/display/intel_lvds.c
912
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_lvds.c
92
val = intel_de_read(display, lvds_reg);
drivers/gpu/drm/i915/display/intel_lvds.c
930
if (DISPLAY_VER(display) < 4)
drivers/gpu/drm/i915/display/intel_lvds.c
942
intel_lvds_pps_get_hw_state(display, &lvds_encoder->init_pps);
drivers/gpu/drm/i915/display/intel_lvds.c
95
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_lvds.c
957
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_lvds.c
972
intel_bios_init_panel_late(display, &connector->panel, NULL,
drivers/gpu/drm/i915/display/intel_lvds.c
990
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_lvds.h
17
bool intel_lvds_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lvds.h
19
void intel_lvds_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lvds.h
20
struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lvds.h
21
bool intel_is_dual_link_lvds(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_lvds.h
23
static inline bool intel_lvds_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_lvds.h
28
static inline void intel_lvds_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lvds.h
31
static inline struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_lvds.h
35
static inline bool intel_is_dual_link_lvds(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_mchbar.c
14
static bool has_mchbar_mirror(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_mchbar.c
16
return DISPLAY_VER(display) < 14;
drivers/gpu/drm/i915/display/intel_mchbar.c
19
static u32 mchbar_mirror_base(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_mchbar.c
21
if (DISPLAY_VER(display) >= 6)
drivers/gpu/drm/i915/display/intel_mchbar.c
27
static u32 mchbar_mirror_end(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_mchbar.c
29
if (DISPLAY_VER(display) >= 12 && !display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_mchbar.c
31
else if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_mchbar.c
33
else if (DISPLAY_VER(display) >= 6)
drivers/gpu/drm/i915/display/intel_mchbar.c
39
static u32 mchbar_mirror_len(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_mchbar.c
41
return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1;
drivers/gpu/drm/i915/display/intel_mchbar.c
44
static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_mchbar.c
46
return has_mchbar_mirror(display) &&
drivers/gpu/drm/i915/display/intel_mchbar.c
48
mchbar_mirror_base(display),
drivers/gpu/drm/i915/display/intel_mchbar.c
49
mchbar_mirror_len(display));
drivers/gpu/drm/i915/display/intel_mchbar.c
52
static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_mchbar.c
54
drm_WARN(display->drm, !is_mchbar_reg(display, reg),
drivers/gpu/drm/i915/display/intel_mchbar.c
59
u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_mchbar.c
61
assert_is_mchbar_reg(display, reg);
drivers/gpu/drm/i915/display/intel_mchbar.c
63
return intel_de_read16(display, reg);
drivers/gpu/drm/i915/display/intel_mchbar.c
66
u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_mchbar.c
68
assert_is_mchbar_reg(display, reg);
drivers/gpu/drm/i915/display/intel_mchbar.c
70
return intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_mchbar.c
73
u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg)
drivers/gpu/drm/i915/display/intel_mchbar.c
75
assert_is_mchbar_reg(display, reg);
drivers/gpu/drm/i915/display/intel_mchbar.c
77
return intel_de_read64_2x32(display, reg);
drivers/gpu/drm/i915/display/intel_mchbar.h
17
u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_mchbar.h
18
u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_mchbar.h
19
u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
1000
intel_wm_sanitize(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
1002
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
1008
if (drm_WARN_ON(display->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
drivers/gpu/drm/i915/display/intel_modeset_setup.c
1012
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
1014
intel_display_power_sanitize_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
123
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
125
to_intel_pmdemand_state(display->pmdemand.obj.state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
129
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
135
intel_pmdemand_update_phys_mask(display, encoder,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
148
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
151
for_each_encoder_on_crtc(display->drm, &crtc->base, encoder) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
159
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
161
to_intel_pmdemand_state(display->pmdemand.obj.state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
173
intel_update_watermarks(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
175
intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
182
intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
189
static u8 get_transcoder_pipes(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
195
for_each_intel_crtc(display, temp_crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
219
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
238
*master_pipe_mask = get_transcoder_pipes(display, BIT(master_transcoder));
drivers/gpu/drm/i915/display/intel_modeset_setup.c
239
drm_WARN_ON(display->drm, !is_power_of_2(*master_pipe_mask));
drivers/gpu/drm/i915/display/intel_modeset_setup.c
241
master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
243
*slave_pipes_mask = get_transcoder_pipes(display, master_crtc_state->sync_mode_slaves_mask);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
246
static u8 get_joiner_secondary_pipes(struct intel_display *display, u8 primary_pipes_mask)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
251
for_each_intel_crtc_in_pipe_mask(display, primary_crtc, primary_pipes_mask) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
264
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
272
joiner_secondaries_mask = get_joiner_secondary_pipes(display,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
276
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
281
for_each_intel_crtc_in_pipe_mask(display, temp_crtc, joiner_secondaries_mask)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
284
for_each_intel_crtc_in_pipe_mask(display, temp_crtc, portsync_slaves_mask)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
287
for_each_intel_crtc_in_pipe_mask(display, temp_crtc, portsync_master_mask)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
290
for_each_intel_crtc_in_pipe_mask(display, temp_crtc,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
297
static void intel_modeset_update_connector_atomic_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
302
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
324
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
340
if (DISPLAY_INFO(display)->color.degamma_lut_size) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
355
drm_WARN_ON(display->drm, crtc_state->post_csc_lut &&
drivers/gpu/drm/i915/display/intel_modeset_setup.c
374
intel_sanitize_plane_mapping(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
378
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
381
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
393
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
397
plane_crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
43
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
430
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
435
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
449
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
465
intel_init_fifo_underrun_reporting(display, crtc,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
467
!HAS_GMCH(display));
drivers/gpu/drm/i915/display/intel_modeset_setup.c
473
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
481
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
522
static void intel_sanitize_all_crtcs(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
537
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
54
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
550
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
560
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
572
return display->platform.sandybridge &&
drivers/gpu/drm/i915/display/intel_modeset_setup.c
580
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
586
to_intel_pmdemand_state(display->pmdemand.obj.state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
597
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
605
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
611
intel_pmdemand_update_phys_mask(display, encoder,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
62
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
622
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
64
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
656
if (HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_modeset_setup.c
661
static void readout_plane_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
666
for_each_intel_plane(display->drm, plane) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
675
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
680
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
686
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
694
static void intel_modeset_readout_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
697
to_intel_pmdemand_state(display->pmdemand.obj.state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
704
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
719
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
725
readout_plane_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
727
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
733
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
74
for_each_intel_crtc_in_pipe_mask(display, temp_crtc,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
746
for_each_intel_crtc_in_pipe_mask(display, secondary_crtc,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
755
intel_pmdemand_update_phys_mask(display, encoder,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
759
intel_pmdemand_update_phys_mask(display, encoder,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
769
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
776
intel_dpll_readout_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
778
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
812
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
819
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
83
drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
842
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
858
if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
86
display->modeset.funcs->crtc_disable(to_intel_atomic_state(state), crtc);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
865
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
873
drm_dbg_kms(display->drm, "[CRTC:%d:%s] min_cdclk %d kHz\n",
drivers/gpu/drm/i915/display/intel_modeset_setup.c
876
intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
881
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
882
intel_wm_get_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
884
intel_bw_update_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
885
intel_dbuf_bw_update_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
886
intel_cdclk_update_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
888
intel_pmdemand_init_pmdemand_params(display, pmdemand_state);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
892
get_encoder_power_domains(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
896
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
90
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
914
static void intel_early_display_was(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
920
if (intel_display_wa(display, INTEL_DISPLAY_WA_14010480278))
drivers/gpu/drm/i915/display/intel_modeset_setup.c
921
intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
927
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
928
intel_de_rmw(display, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
930
if (display->platform.kabylake || display->platform.coffeelake ||
drivers/gpu/drm/i915/display/intel_modeset_setup.c
931
display->platform.cometlake) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
933
intel_de_rmw(display, CHICKEN_PAR1_1,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
935
intel_de_rmw(display, CHICKEN_MISC_2,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
941
void intel_modeset_setup_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_modeset_setup.c
948
wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
950
intel_early_display_was(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
951
intel_vga_disable(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
953
intel_modeset_readout_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
956
get_encoder_power_domains(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
958
intel_pch_sanitize(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
960
intel_cmtg_sanitize(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
966
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/intel_modeset_setup.c
980
intel_fbc_sanitize(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
982
intel_sanitize_plane_mapping(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
984
for_each_intel_encoder(display->drm, encoder)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
991
intel_modeset_update_connector_atomic_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
993
intel_sanitize_all_crtcs(display, ctx);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
995
intel_dpll_sanitize_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.c
998
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_modeset_setup.c
999
intel_wm_get_hw_state(display);
drivers/gpu/drm/i915/display/intel_modeset_setup.h
12
void intel_modeset_setup_hw_state(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
106
drm_WARN(display->drm, abs(fdi_dotclock - dotclock) > 1,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
115
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_modeset_verify.c
121
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_modeset_verify.c
125
drm_dbg_kms(display->drm, "[ENCODER:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_modeset_verify.c
140
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
148
INTEL_DISPLAY_STATE_WARN(display, !!encoder->base.crtc != enabled,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
156
INTEL_DISPLAY_STATE_WARN(display, active,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
167
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_modeset_verify.c
178
drm_dbg_kms(display->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
186
if (display->platform.i830 && hw_crtc_state->hw.active)
drivers/gpu/drm/i915/display/intel_modeset_verify.c
189
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
194
INTEL_DISPLAY_STATE_WARN(display, crtc->active != sw_crtc_state->hw.active,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
200
for_each_encoder_on_crtc(display->drm, &primary_crtc->base, encoder) {
drivers/gpu/drm/i915/display/intel_modeset_verify.c
205
INTEL_DISPLAY_STATE_WARN(display, active != sw_crtc_state->hw.active,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
210
INTEL_DISPLAY_STATE_WARN(display, active && primary_crtc->pipe != pipe,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
225
INTEL_DISPLAY_STATE_WARN(display, 1, "pipe state doesn't match!\n");
drivers/gpu/drm/i915/display/intel_modeset_verify.c
32
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_modeset_verify.c
34
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_modeset_verify.c
40
INTEL_DISPLAY_STATE_WARN(display, !crtc_state,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
46
INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
52
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
56
INTEL_DISPLAY_STATE_WARN(display, conn_state->crtc != encoder->base.crtc,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
59
INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
61
INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
70
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_modeset_verify.c
87
INTEL_DISPLAY_STATE_WARN(display, new_conn_state->best_encoder != encoder,
drivers/gpu/drm/i915/display/intel_modeset_verify.c
94
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_modeset_verify.c
97
int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),
drivers/gpu/drm/i915/display/intel_opregion.c
1005
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
1023
if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {
drivers/gpu/drm/i915/display/intel_opregion.c
1024
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
1029
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
1040
display->opregion = NULL;
drivers/gpu/drm/i915/display/intel_opregion.c
1063
intel_opregion_get_panel_type(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1068
ret = swsci(display, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);
drivers/gpu/drm/i915/display/intel_opregion.c
1074
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
1081
drm_dbg_kms(display->drm, "No panel type in OpRegion\n");
drivers/gpu/drm/i915/display/intel_opregion.c
1091
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
1112
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_opregion.c
1113
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1131
drm_dbg_kms(display->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");
drivers/gpu/drm/i915/display/intel_opregion.c
1139
bool intel_opregion_vbt_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1141
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1149
const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size)
drivers/gpu/drm/i915/display/intel_opregion.c
1151
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1162
bool intel_opregion_headless_sku(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1164
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1179
void intel_opregion_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1181
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1192
intel_opregion_resume(display);
drivers/gpu/drm/i915/display/intel_opregion.c
1195
static void intel_opregion_resume_display(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1197
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1200
intel_didl_outputs(display);
drivers/gpu/drm/i915/display/intel_opregion.c
1201
intel_setup_cadls(display);
drivers/gpu/drm/i915/display/intel_opregion.c
1218
intel_dsm_get_bios_data_funcs_supported(display);
drivers/gpu/drm/i915/display/intel_opregion.c
1221
void intel_opregion_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1223
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1228
if (HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_opregion.c
1229
intel_opregion_resume_display(display);
drivers/gpu/drm/i915/display/intel_opregion.c
1231
intel_opregion_notify_adapter(display, PCI_D0);
drivers/gpu/drm/i915/display/intel_opregion.c
1234
static void intel_opregion_suspend_display(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1236
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1247
void intel_opregion_suspend(struct intel_display *display, pci_power_t state)
drivers/gpu/drm/i915/display/intel_opregion.c
1249
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1254
intel_opregion_notify_adapter(display, state);
drivers/gpu/drm/i915/display/intel_opregion.c
1256
if (HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_opregion.c
1257
intel_opregion_suspend_display(display);
drivers/gpu/drm/i915/display/intel_opregion.c
1260
void intel_opregion_unregister(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1262
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1264
intel_opregion_suspend(display, PCI_D1);
drivers/gpu/drm/i915/display/intel_opregion.c
1275
void intel_opregion_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1277
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1286
display->opregion = NULL;
drivers/gpu/drm/i915/display/intel_opregion.c
1291
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_opregion.c
1292
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
1302
void intel_opregion_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
1304
debugfs_create_file("i915_opregion", 0444, display->drm->debugfs_root,
drivers/gpu/drm/i915/display/intel_opregion.c
1305
display, &intel_opregion_fops);
drivers/gpu/drm/i915/display/intel_opregion.c
259
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_opregion.c
275
static int check_swsci_function(struct intel_display *display, u32 function)
drivers/gpu/drm/i915/display/intel_opregion.c
277
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
307
static int swsci(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_opregion.c
311
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_opregion.c
316
ret = check_swsci_function(display, function);
drivers/gpu/drm/i915/display/intel_opregion.c
320
swsci = display->opregion->swsci;
drivers/gpu/drm/i915/display/intel_opregion.c
338
drm_dbg(display->drm, "SWSCI request already in progress\n");
drivers/gpu/drm/i915/display/intel_opregion.c
364
drm_dbg(display->drm, "SWSCI request timed out\n");
drivers/gpu/drm/i915/display/intel_opregion.c
373
drm_dbg(display->drm, "SWSCI request error %u\n", scic);
drivers/gpu/drm/i915/display/intel_opregion.c
393
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_opregion.c
400
if (!HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_opregion.c
404
ret = check_swsci_function(display, SWSCI_SBCB_DISPLAY_POWER_STATE);
drivers/gpu/drm/i915/display/intel_opregion.c
428
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
453
drm_WARN_ONCE(display->drm, 1,
drivers/gpu/drm/i915/display/intel_opregion.c
461
return swsci(display, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL);
drivers/gpu/drm/i915/display/intel_opregion.c
475
int intel_opregion_notify_adapter(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_opregion.c
480
if (!HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_opregion.c
485
return swsci(display, SWSCI_SBCB_ADAPTER_POWER_STATE,
drivers/gpu/drm/i915/display/intel_opregion.c
492
static u32 asle_set_backlight(struct intel_display *display, u32 bclp)
drivers/gpu/drm/i915/display/intel_opregion.c
496
struct opregion_asle *asle = display->opregion->asle;
drivers/gpu/drm/i915/display/intel_opregion.c
498
drm_dbg(display->drm, "bclp = 0x%08x\n", bclp);
drivers/gpu/drm/i915/display/intel_opregion.c
501
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
513
drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);
drivers/gpu/drm/i915/display/intel_opregion.c
519
drm_dbg_kms(display->drm, "updating opregion backlight %d/255\n",
drivers/gpu/drm/i915/display/intel_opregion.c
521
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_opregion.c
527
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_opregion.c
533
static u32 asle_set_als_illum(struct intel_display *display, u32 alsi)
drivers/gpu/drm/i915/display/intel_opregion.c
537
drm_dbg(display->drm, "Illum is not supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
541
static u32 asle_set_pwm_freq(struct intel_display *display, u32 pfmb)
drivers/gpu/drm/i915/display/intel_opregion.c
543
drm_dbg(display->drm, "PWM freq is not supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
547
static u32 asle_set_pfit(struct intel_display *display, u32 pfit)
drivers/gpu/drm/i915/display/intel_opregion.c
551
drm_dbg(display->drm, "Pfit is not supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
555
static u32 asle_set_supported_rotation_angles(struct intel_display *display, u32 srot)
drivers/gpu/drm/i915/display/intel_opregion.c
557
drm_dbg(display->drm, "SROT is not supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
561
static u32 asle_set_button_array(struct intel_display *display, u32 iuer)
drivers/gpu/drm/i915/display/intel_opregion.c
564
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
567
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
570
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
573
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
576
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
579
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
585
static u32 asle_set_convertible(struct intel_display *display, u32 iuer)
drivers/gpu/drm/i915/display/intel_opregion.c
588
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
591
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
597
static u32 asle_set_docking(struct intel_display *display, u32 iuer)
drivers/gpu/drm/i915/display/intel_opregion.c
600
drm_dbg(display->drm, "Docking is not supported (docked)\n");
drivers/gpu/drm/i915/display/intel_opregion.c
602
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
608
static u32 asle_isct_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
610
drm_dbg(display->drm, "ISCT is not supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
618
struct intel_display *display = opregion->display;
drivers/gpu/drm/i915/display/intel_opregion.c
629
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
635
aslc_stat |= asle_set_als_illum(display, asle->alsi);
drivers/gpu/drm/i915/display/intel_opregion.c
638
aslc_stat |= asle_set_backlight(display, asle->bclp);
drivers/gpu/drm/i915/display/intel_opregion.c
641
aslc_stat |= asle_set_pfit(display, asle->pfit);
drivers/gpu/drm/i915/display/intel_opregion.c
644
aslc_stat |= asle_set_pwm_freq(display, asle->pfmb);
drivers/gpu/drm/i915/display/intel_opregion.c
647
aslc_stat |= asle_set_supported_rotation_angles(display,
drivers/gpu/drm/i915/display/intel_opregion.c
651
aslc_stat |= asle_set_button_array(display, asle->iuer);
drivers/gpu/drm/i915/display/intel_opregion.c
654
aslc_stat |= asle_set_convertible(display, asle->iuer);
drivers/gpu/drm/i915/display/intel_opregion.c
657
aslc_stat |= asle_set_docking(display, asle->iuer);
drivers/gpu/drm/i915/display/intel_opregion.c
660
aslc_stat |= asle_isct_state(display);
drivers/gpu/drm/i915/display/intel_opregion.c
665
bool intel_opregion_asle_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
667
return display->opregion && display->opregion->asle;
drivers/gpu/drm/i915/display/intel_opregion.c
670
void intel_opregion_asle_intr(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
672
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
675
queue_work(display->wq.unordered, &opregion->asle_work);
drivers/gpu/drm/i915/display/intel_opregion.c
729
static void intel_didl_outputs(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
731
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
746
intel_acpi_device_id_update(display);
drivers/gpu/drm/i915/display/intel_opregion.c
748
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_opregion.c
756
drm_dbg_kms(display->drm, "%d outputs detected\n", i);
drivers/gpu/drm/i915/display/intel_opregion.c
759
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
768
static void intel_setup_cadls(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
770
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
785
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_opregion.c
798
static void swsci_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
800
struct intel_opregion *opregion = display->opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
809
if (swsci(display, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {
drivers/gpu/drm/i915/display/intel_opregion.c
820
if (swsci(display, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {
drivers/gpu/drm/i915/display/intel_opregion.c
831
if (swsci(display, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {
drivers/gpu/drm/i915/display/intel_opregion.c
841
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
851
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.c
876
int intel_opregion_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.c
879
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_opregion.c
894
drm_dbg(display->drm, "graphic opregion physical addr: 0x%x\n",
drivers/gpu/drm/i915/display/intel_opregion.c
897
drm_dbg(display->drm, "ACPI OpRegion not supported!\n");
drivers/gpu/drm/i915/display/intel_opregion.c
905
opregion->display = display;
drivers/gpu/drm/i915/display/intel_opregion.c
906
display->opregion = opregion;
drivers/gpu/drm/i915/display/intel_opregion.c
919
drm_dbg(display->drm, "opregion signature mismatch\n");
drivers/gpu/drm/i915/display/intel_opregion.c
925
drm_dbg(display->drm, "ACPI OpRegion version %u.%u.%u\n",
drivers/gpu/drm/i915/display/intel_opregion.c
932
drm_dbg(display->drm, "Public ACPI methods supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
947
drm_err(display->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n");
drivers/gpu/drm/i915/display/intel_opregion.c
950
drm_dbg(display->drm, "SWSCI Mailbox #2 present for opregion v2.x\n");
drivers/gpu/drm/i915/display/intel_opregion.c
951
drm_dbg(display->drm, "SWSCI supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
953
swsci_setup(display);
drivers/gpu/drm/i915/display/intel_opregion.c
958
drm_dbg(display->drm, "ASLE supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
965
drm_dbg(display->drm, "ASLE extension supported\n");
drivers/gpu/drm/i915/display/intel_opregion.c
970
drm_dbg(display->drm, "Mailbox #2 for backlight present\n");
drivers/gpu/drm/i915/display/intel_opregion.c
988
drm_WARN_ON(display->drm, rvda < OPREGION_SIZE);
drivers/gpu/drm/i915/display/intel_opregion.c
998
if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {
drivers/gpu/drm/i915/display/intel_opregion.c
999
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_opregion.h
107
intel_opregion_notify_adapter(struct intel_display *display, pci_power_t state)
drivers/gpu/drm/i915/display/intel_opregion.h
112
static inline int intel_opregion_get_panel_type(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
123
static inline bool intel_opregion_vbt_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
129
intel_opregion_get_vbt(struct intel_display *display, size_t *size)
drivers/gpu/drm/i915/display/intel_opregion.h
134
static inline bool intel_opregion_headless_sku(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
139
static inline void intel_opregion_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
37
int intel_opregion_setup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
38
void intel_opregion_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
40
void intel_opregion_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
41
void intel_opregion_unregister(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
43
void intel_opregion_resume(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
44
void intel_opregion_suspend(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_opregion.h
47
bool intel_opregion_asle_present(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
48
void intel_opregion_asle_intr(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
51
int intel_opregion_notify_adapter(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_opregion.h
53
int intel_opregion_get_panel_type(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
56
bool intel_opregion_vbt_present(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
57
const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size);
drivers/gpu/drm/i915/display/intel_opregion.h
59
bool intel_opregion_headless_sku(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
61
void intel_opregion_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_opregion.h
65
static inline int intel_opregion_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
70
static inline void intel_opregion_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
74
static inline void intel_opregion_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
78
static inline void intel_opregion_unregister(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
82
static inline void intel_opregion_resume(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
86
static inline void intel_opregion_suspend(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_opregion.h
91
static inline bool intel_opregion_asle_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_opregion.h
96
static inline void intel_opregion_asle_intr(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_overlay.c
1004
intel_de_write(display, OGAMC0, attrs->gamma0);
drivers/gpu/drm/i915/display/intel_overlay.c
1005
intel_de_write(display, OGAMC1, attrs->gamma1);
drivers/gpu/drm/i915/display/intel_overlay.c
1006
intel_de_write(display, OGAMC2, attrs->gamma2);
drivers/gpu/drm/i915/display/intel_overlay.c
1007
intel_de_write(display, OGAMC3, attrs->gamma3);
drivers/gpu/drm/i915/display/intel_overlay.c
1008
intel_de_write(display, OGAMC4, attrs->gamma4);
drivers/gpu/drm/i915/display/intel_overlay.c
1009
intel_de_write(display, OGAMC5, attrs->gamma5);
drivers/gpu/drm/i915/display/intel_overlay.c
1021
void intel_overlay_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_overlay.c
1026
if (!HAS_OVERLAY(display))
drivers/gpu/drm/i915/display/intel_overlay.c
1033
regs = intel_parent_overlay_setup(display,
drivers/gpu/drm/i915/display/intel_overlay.c
1034
OVERLAY_NEEDS_PHYSICAL(display));
drivers/gpu/drm/i915/display/intel_overlay.c
1038
overlay->display = display;
drivers/gpu/drm/i915/display/intel_overlay.c
1050
display->overlay = overlay;
drivers/gpu/drm/i915/display/intel_overlay.c
1051
drm_info(display->drm, "Initialized overlay support.\n");
drivers/gpu/drm/i915/display/intel_overlay.c
1058
bool intel_overlay_available(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_overlay.c
1060
return display->overlay;
drivers/gpu/drm/i915/display/intel_overlay.c
1063
void intel_overlay_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_overlay.c
1065
if (!display->overlay)
drivers/gpu/drm/i915/display/intel_overlay.c
1068
intel_parent_overlay_cleanup(display);
drivers/gpu/drm/i915/display/intel_overlay.c
1070
kfree(display->overlay);
drivers/gpu/drm/i915/display/intel_overlay.c
1071
display->overlay = NULL;
drivers/gpu/drm/i915/display/intel_overlay.c
180
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_overlay.c
191
void intel_overlay_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_overlay.c
193
struct intel_overlay *overlay = display->overlay;
drivers/gpu/drm/i915/display/intel_overlay.c
202
intel_parent_overlay_reset(display);
drivers/gpu/drm/i915/display/intel_overlay.c
255
static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width)
drivers/gpu/drm/i915/display/intel_overlay.c
259
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_overlay.c
468
struct intel_display *display = overlay->display;
drivers/gpu/drm/i915/display/intel_overlay.c
477
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_overlay.c
478
!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
drivers/gpu/drm/i915/display/intel_overlay.c
480
ret = intel_parent_overlay_release_old_vid(display);
drivers/gpu/drm/i915/display/intel_overlay.c
484
vma = intel_parent_overlay_pin_fb(display, obj, &offset);
drivers/gpu/drm/i915/display/intel_overlay.c
488
if (!intel_parent_overlay_is_active(display)) {
drivers/gpu/drm/i915/display/intel_overlay.c
498
if (DISPLAY_VER(display) == 4)
drivers/gpu/drm/i915/display/intel_overlay.c
504
ret = intel_parent_overlay_on(display, INTEL_FRONTBUFFER_OVERLAY(pipe));
drivers/gpu/drm/i915/display/intel_overlay.c
519
swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width);
drivers/gpu/drm/i915/display/intel_overlay.c
532
tmp_U = calc_swidthsw(display, params->offset_U,
drivers/gpu/drm/i915/display/intel_overlay.c
534
tmp_V = calc_swidthsw(display, params->offset_V,
drivers/gpu/drm/i915/display/intel_overlay.c
558
tmp = intel_de_read(display, DOVSTA);
drivers/gpu/drm/i915/display/intel_overlay.c
560
drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp);
drivers/gpu/drm/i915/display/intel_overlay.c
562
ret = intel_parent_overlay_continue(display, vma, scale_changed);
drivers/gpu/drm/i915/display/intel_overlay.c
569
intel_parent_overlay_unpin_fb(display, vma);
drivers/gpu/drm/i915/display/intel_overlay.c
576
struct intel_display *display = overlay->display;
drivers/gpu/drm/i915/display/intel_overlay.c
579
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_overlay.c
580
!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
drivers/gpu/drm/i915/display/intel_overlay.c
582
ret = intel_parent_overlay_recover_from_interrupt(display);
drivers/gpu/drm/i915/display/intel_overlay.c
586
if (!intel_parent_overlay_is_active(display))
drivers/gpu/drm/i915/display/intel_overlay.c
589
ret = intel_parent_overlay_release_old_vid(display);
drivers/gpu/drm/i915/display/intel_overlay.c
598
return intel_parent_overlay_off(display);
drivers/gpu/drm/i915/display/intel_overlay.c
616
struct intel_display *display = overlay->display;
drivers/gpu/drm/i915/display/intel_overlay.c
622
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_overlay.c
623
u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
drivers/gpu/drm/i915/display/intel_overlay.c
630
if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)
drivers/gpu/drm/i915/display/intel_overlay.c
631
tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));
drivers/gpu/drm/i915/display/intel_overlay.c
633
tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
drivers/gpu/drm/i915/display/intel_overlay.c
678
static int check_overlay_src(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_overlay.c
689
if (display->platform.i845g || display->platform.i830) {
drivers/gpu/drm/i915/display/intel_overlay.c
741
if (display->platform.i830 || display->platform.i845g)
drivers/gpu/drm/i915/display/intel_overlay.c
748
if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512)
drivers/gpu/drm/i915/display/intel_overlay.c
792
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_overlay.c
800
overlay = display->overlay;
drivers/gpu/drm/i915/display/intel_overlay.c
802
drm_dbg(display->drm, "userspace bug: no overlay\n");
drivers/gpu/drm/i915/display/intel_overlay.c
819
obj = intel_parent_overlay_obj_lookup(display, file_priv, params->bo_handle);
drivers/gpu/drm/i915/display/intel_overlay.c
825
ret = intel_parent_overlay_recover_from_interrupt(display);
drivers/gpu/drm/i915/display/intel_overlay.c
868
ret = check_overlay_src(display, params, obj);
drivers/gpu/drm/i915/display/intel_overlay.c
948
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_overlay.c
953
overlay = display->overlay;
drivers/gpu/drm/i915/display/intel_overlay.c
955
drm_dbg(display->drm, "userspace bug: no overlay\n");
drivers/gpu/drm/i915/display/intel_overlay.c
968
if (DISPLAY_VER(display) != 2) {
drivers/gpu/drm/i915/display/intel_overlay.c
969
attrs->gamma0 = intel_de_read(display, OGAMC0);
drivers/gpu/drm/i915/display/intel_overlay.c
970
attrs->gamma1 = intel_de_read(display, OGAMC1);
drivers/gpu/drm/i915/display/intel_overlay.c
971
attrs->gamma2 = intel_de_read(display, OGAMC2);
drivers/gpu/drm/i915/display/intel_overlay.c
972
attrs->gamma3 = intel_de_read(display, OGAMC3);
drivers/gpu/drm/i915/display/intel_overlay.c
973
attrs->gamma4 = intel_de_read(display, OGAMC4);
drivers/gpu/drm/i915/display/intel_overlay.c
974
attrs->gamma5 = intel_de_read(display, OGAMC5);
drivers/gpu/drm/i915/display/intel_overlay.c
992
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_overlay.c
995
if (intel_parent_overlay_is_active(display)) {
drivers/gpu/drm/i915/display/intel_overlay.h
17
void intel_overlay_setup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_overlay.h
18
bool intel_overlay_available(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_overlay.h
19
void intel_overlay_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_overlay.h
25
void intel_overlay_reset(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_panel.c
252
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
261
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_panel.c
272
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
290
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_panel.c
303
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
307
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_panel.c
312
drm_mode_destroy(display->drm, mode);
drivers/gpu/drm/i915/display/intel_panel.c
329
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
340
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s fixed mode: " DRM_MODE_FMT "\n",
drivers/gpu/drm/i915/display/intel_panel.c
349
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
357
drm_mode_duplicate(display->drm, mode),
drivers/gpu/drm/i915/display/intel_panel.c
363
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
371
drm_mode_duplicate(display->drm, mode),
drivers/gpu/drm/i915/display/intel_panel.c
386
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_panel.c
388
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_panel.c
391
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_panel.c
47
bool intel_panel_use_ssc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_panel.c
485
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
49
if (display->params.panel_use_ssc >= 0)
drivers/gpu/drm/i915/display/intel_panel.c
490
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);
drivers/gpu/drm/i915/display/intel_panel.c
50
return display->params.panel_use_ssc != 0;
drivers/gpu/drm/i915/display/intel_panel.c
503
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Panel prepare\n",
drivers/gpu/drm/i915/display/intel_panel.c
509
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
drivers/gpu/drm/i915/display/intel_panel.c
51
return display->vbt.lvds_use_ssc &&
drivers/gpu/drm/i915/display/intel_panel.c
517
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_panel.c
52
!intel_has_quirk(display, QUIRK_LVDS_SSC_DISABLE);
drivers/gpu/drm/i915/display/intel_panel.c
531
if (drm_WARN_ON(display->drm, !dev))
drivers/gpu/drm/i915/display/intel_panel.c
560
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Registered panel device '%s', has fwnode: %s\n",
drivers/gpu/drm/i915/display/intel_panel.h
30
bool intel_panel_use_ssc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.c
102
if (!display->parent->fb_pin->reuse_vma)
drivers/gpu/drm/i915/display/intel_parent.c
105
return display->parent->fb_pin->reuse_vma(old_ggtt_vma, old_obj, old_view,
drivers/gpu/drm/i915/display/intel_parent.c
109
void intel_parent_fb_pin_get_map(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
112
return display->parent->fb_pin->get_map(vma, map);
drivers/gpu/drm/i915/display/intel_parent.c
116
struct intel_frontbuffer *intel_parent_frontbuffer_get(struct intel_display *display, struct drm_gem_object *obj)
drivers/gpu/drm/i915/display/intel_parent.c
118
return display->parent->frontbuffer->get(obj);
drivers/gpu/drm/i915/display/intel_parent.c
121
void intel_parent_frontbuffer_ref(struct intel_display *display, struct intel_frontbuffer *front)
drivers/gpu/drm/i915/display/intel_parent.c
123
display->parent->frontbuffer->ref(front);
drivers/gpu/drm/i915/display/intel_parent.c
126
void intel_parent_frontbuffer_put(struct intel_display *display, struct intel_frontbuffer *front)
drivers/gpu/drm/i915/display/intel_parent.c
128
display->parent->frontbuffer->put(front);
drivers/gpu/drm/i915/display/intel_parent.c
131
void intel_parent_frontbuffer_flush_for_display(struct intel_display *display, struct intel_frontbuffer *front)
drivers/gpu/drm/i915/display/intel_parent.c
133
display->parent->frontbuffer->flush_for_display(front);
drivers/gpu/drm/i915/display/intel_parent.c
137
ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
142
return display->parent->hdcp->gsc_msg_send(gsc_context, msg_in, msg_in_len, msg_out, msg_out_len);
drivers/gpu/drm/i915/display/intel_parent.c
145
bool intel_parent_hdcp_gsc_check_status(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
147
return display->parent->hdcp->gsc_check_status(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
150
struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
152
return display->parent->hdcp->gsc_context_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
155
void intel_parent_hdcp_gsc_context_free(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
158
display->parent->hdcp->gsc_context_free(gsc_context);
drivers/gpu/drm/i915/display/intel_parent.c
162
bool intel_parent_irq_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
164
return display->parent->irq->enabled(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
167
void intel_parent_irq_synchronize(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
169
display->parent->irq->synchronize(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
173
bool intel_parent_overlay_is_active(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
175
return display->parent->overlay->is_active(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
178
int intel_parent_overlay_on(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
181
return display->parent->overlay->overlay_on(display->drm,
drivers/gpu/drm/i915/display/intel_parent.c
185
int intel_parent_overlay_continue(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
189
return display->parent->overlay->overlay_continue(display->drm, vma,
drivers/gpu/drm/i915/display/intel_parent.c
193
int intel_parent_overlay_off(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
195
return display->parent->overlay->overlay_off(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
198
int intel_parent_overlay_recover_from_interrupt(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
200
return display->parent->overlay->recover_from_interrupt(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
203
int intel_parent_overlay_release_old_vid(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
205
return display->parent->overlay->release_old_vid(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
208
void intel_parent_overlay_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
210
display->parent->overlay->reset(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
213
struct i915_vma *intel_parent_overlay_pin_fb(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
217
return display->parent->overlay->pin_fb(display->drm, obj, offset);
drivers/gpu/drm/i915/display/intel_parent.c
220
void intel_parent_overlay_unpin_fb(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
223
return display->parent->overlay->unpin_fb(display->drm, vma);
drivers/gpu/drm/i915/display/intel_parent.c
226
struct drm_gem_object *intel_parent_overlay_obj_lookup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
230
return display->parent->overlay->obj_lookup(display->drm,
drivers/gpu/drm/i915/display/intel_parent.c
234
void __iomem *intel_parent_overlay_setup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
237
if (drm_WARN_ON_ONCE(display->drm, !display->parent->overlay))
drivers/gpu/drm/i915/display/intel_parent.c
240
return display->parent->overlay->setup(display->drm, needs_physical);
drivers/gpu/drm/i915/display/intel_parent.c
243
void intel_parent_overlay_cleanup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
245
display->parent->overlay->cleanup(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
249
struct intel_panic *intel_parent_panic_alloc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
251
return display->parent->panic->alloc();
drivers/gpu/drm/i915/display/intel_parent.c
254
int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb)
drivers/gpu/drm/i915/display/intel_parent.c
256
return display->parent->panic->setup(panic, sb);
drivers/gpu/drm/i915/display/intel_parent.c
259
void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic)
drivers/gpu/drm/i915/display/intel_parent.c
261
display->parent->panic->finish(panic);
drivers/gpu/drm/i915/display/intel_parent.c
265
void intel_parent_pc8_block(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
267
if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8))
drivers/gpu/drm/i915/display/intel_parent.c
270
display->parent->pc8->block(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
273
void intel_parent_pc8_unblock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
275
if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8))
drivers/gpu/drm/i915/display/intel_parent.c
278
display->parent->pc8->unblock(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
28
struct intel_dpt *intel_parent_dpt_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
282
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1)
drivers/gpu/drm/i915/display/intel_parent.c
284
return display->parent->pcode->read(display->drm, mbox, val, val1);
drivers/gpu/drm/i915/display/intel_parent.c
287
int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms)
drivers/gpu/drm/i915/display/intel_parent.c
289
return display->parent->pcode->write(display->drm, mbox, val, timeout_ms);
drivers/gpu/drm/i915/display/intel_parent.c
292
int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val)
drivers/gpu/drm/i915/display/intel_parent.c
294
return intel_parent_pcode_write_timeout(display, mbox, val, 1);
drivers/gpu/drm/i915/display/intel_parent.c
297
int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
drivers/gpu/drm/i915/display/intel_parent.c
300
return display->parent->pcode->request(display->drm, mbox, request, reply_mask, reply, timeout_base_ms);
drivers/gpu/drm/i915/display/intel_parent.c
304
bool intel_parent_rps_available(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
306
return display->parent->rps;
drivers/gpu/drm/i915/display/intel_parent.c
309
void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence)
drivers/gpu/drm/i915/display/intel_parent.c
31
if (display->parent->dpt)
drivers/gpu/drm/i915/display/intel_parent.c
311
if (display->parent->rps)
drivers/gpu/drm/i915/display/intel_parent.c
312
display->parent->rps->boost_if_not_started(fence);
drivers/gpu/drm/i915/display/intel_parent.c
315
void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive)
drivers/gpu/drm/i915/display/intel_parent.c
317
if (display->parent->rps)
drivers/gpu/drm/i915/display/intel_parent.c
318
display->parent->rps->mark_interactive(display->drm, interactive);
drivers/gpu/drm/i915/display/intel_parent.c
32
return display->parent->dpt->create(obj, size);
drivers/gpu/drm/i915/display/intel_parent.c
321
void intel_parent_rps_ilk_irq_handler(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
323
if (display->parent->rps)
drivers/gpu/drm/i915/display/intel_parent.c
324
display->parent->rps->ilk_irq_handler(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
328
int intel_parent_stolen_insert_node_in_range(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
332
return display->parent->stolen->insert_node_in_range(node, size, align, start, end);
drivers/gpu/drm/i915/display/intel_parent.c
335
int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size,
drivers/gpu/drm/i915/display/intel_parent.c
338
if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->insert_node))
drivers/gpu/drm/i915/display/intel_parent.c
341
return display->parent->stolen->insert_node(node, size, align);
drivers/gpu/drm/i915/display/intel_parent.c
344
void intel_parent_stolen_remove_node(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
347
display->parent->stolen->remove_node(node);
drivers/gpu/drm/i915/display/intel_parent.c
350
bool intel_parent_stolen_initialized(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
352
return display->parent->stolen->initialized(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
355
bool intel_parent_stolen_node_allocated(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
358
return display->parent->stolen->node_allocated(node);
drivers/gpu/drm/i915/display/intel_parent.c
361
u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node)
drivers/gpu/drm/i915/display/intel_parent.c
363
return display->parent->stolen->node_offset(node);
drivers/gpu/drm/i915/display/intel_parent.c
366
u64 intel_parent_stolen_area_address(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
368
if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_address))
drivers/gpu/drm/i915/display/intel_parent.c
37
void intel_parent_dpt_destroy(struct intel_display *display, struct intel_dpt *dpt)
drivers/gpu/drm/i915/display/intel_parent.c
371
return display->parent->stolen->area_address(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
374
u64 intel_parent_stolen_area_size(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
376
if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_size))
drivers/gpu/drm/i915/display/intel_parent.c
379
return display->parent->stolen->area_size(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
382
u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node)
drivers/gpu/drm/i915/display/intel_parent.c
384
return display->parent->stolen->node_address(node);
drivers/gpu/drm/i915/display/intel_parent.c
387
u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node)
drivers/gpu/drm/i915/display/intel_parent.c
389
return display->parent->stolen->node_size(node);
drivers/gpu/drm/i915/display/intel_parent.c
39
if (display->parent->dpt)
drivers/gpu/drm/i915/display/intel_parent.c
392
struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
394
return display->parent->stolen->node_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
397
void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node)
drivers/gpu/drm/i915/display/intel_parent.c
399
display->parent->stolen->node_free(node);
drivers/gpu/drm/i915/display/intel_parent.c
40
display->parent->dpt->destroy(dpt);
drivers/gpu/drm/i915/display/intel_parent.c
403
void intel_parent_vlv_iosf_get(struct intel_display *display, unsigned long unit_mask)
drivers/gpu/drm/i915/display/intel_parent.c
405
if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf))
drivers/gpu/drm/i915/display/intel_parent.c
408
display->parent->vlv_iosf->get(display->drm, unit_mask);
drivers/gpu/drm/i915/display/intel_parent.c
411
void intel_parent_vlv_iosf_put(struct intel_display *display, unsigned long unit_mask)
drivers/gpu/drm/i915/display/intel_parent.c
413
if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf))
drivers/gpu/drm/i915/display/intel_parent.c
416
display->parent->vlv_iosf->put(display->drm, unit_mask);
drivers/gpu/drm/i915/display/intel_parent.c
419
u32 intel_parent_vlv_iosf_read(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr)
drivers/gpu/drm/i915/display/intel_parent.c
421
if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf))
drivers/gpu/drm/i915/display/intel_parent.c
424
return display->parent->vlv_iosf->read(display->drm, unit, addr);
drivers/gpu/drm/i915/display/intel_parent.c
427
int intel_parent_vlv_iosf_write(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr, u32 val)
drivers/gpu/drm/i915/display/intel_parent.c
429
if (drm_WARN_ON_ONCE(display->drm, !display->parent->vlv_iosf))
drivers/gpu/drm/i915/display/intel_parent.c
43
void intel_parent_dpt_suspend(struct intel_display *display, struct intel_dpt *dpt)
drivers/gpu/drm/i915/display/intel_parent.c
432
return display->parent->vlv_iosf->write(display->drm, unit, addr, val);
drivers/gpu/drm/i915/display/intel_parent.c
436
void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence)
drivers/gpu/drm/i915/display/intel_parent.c
438
if (display->parent->fence_priority_display)
drivers/gpu/drm/i915/display/intel_parent.c
439
display->parent->fence_priority_display(fence);
drivers/gpu/drm/i915/display/intel_parent.c
442
bool intel_parent_has_auxccs(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
444
return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
447
bool intel_parent_has_fenced_regions(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
449
return display->parent->has_fenced_regions && display->parent->has_fenced_regions(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
45
if (display->parent->dpt)
drivers/gpu/drm/i915/display/intel_parent.c
452
bool intel_parent_vgpu_active(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_parent.c
454
return display->parent->vgpu_active && display->parent->vgpu_active(display->drm);
drivers/gpu/drm/i915/display/intel_parent.c
46
display->parent->dpt->suspend(dpt);
drivers/gpu/drm/i915/display/intel_parent.c
49
void intel_parent_dpt_resume(struct intel_display *display, struct intel_dpt *dpt)
drivers/gpu/drm/i915/display/intel_parent.c
51
if (display->parent->dpt)
drivers/gpu/drm/i915/display/intel_parent.c
52
display->parent->dpt->resume(dpt);
drivers/gpu/drm/i915/display/intel_parent.c
56
int intel_parent_fb_pin_ggtt_pin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
63
return display->parent->fb_pin->ggtt_pin(obj, pin_params,
drivers/gpu/drm/i915/display/intel_parent.c
67
void intel_parent_fb_pin_ggtt_unpin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
71
return display->parent->fb_pin->ggtt_unpin(ggtt_vma, fence_id);
drivers/gpu/drm/i915/display/intel_parent.c
74
int intel_parent_fb_pin_dpt_pin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
82
return display->parent->fb_pin->dpt_pin(obj, dpt, pin_params,
drivers/gpu/drm/i915/display/intel_parent.c
86
void intel_parent_fb_pin_dpt_unpin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.c
91
return display->parent->fb_pin->dpt_unpin(dpt, dpt_vma, ggtt_vma);
drivers/gpu/drm/i915/display/intel_parent.c
94
struct i915_vma *intel_parent_fb_pin_reuse_vma(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
102
void __iomem *intel_parent_overlay_setup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
104
void intel_parent_overlay_cleanup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
107
struct intel_panic *intel_parent_panic_alloc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
108
int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb);
drivers/gpu/drm/i915/display/intel_parent.h
109
void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic);
drivers/gpu/drm/i915/display/intel_parent.h
112
void intel_parent_pc8_block(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
113
void intel_parent_pc8_unblock(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
116
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1);
drivers/gpu/drm/i915/display/intel_parent.h
117
int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms);
drivers/gpu/drm/i915/display/intel_parent.h
118
int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val);
drivers/gpu/drm/i915/display/intel_parent.h
119
int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
drivers/gpu/drm/i915/display/intel_parent.h
123
bool intel_parent_rps_available(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
124
void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence);
drivers/gpu/drm/i915/display/intel_parent.h
125
void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive);
drivers/gpu/drm/i915/display/intel_parent.h
126
void intel_parent_rps_ilk_irq_handler(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
129
int intel_parent_stolen_insert_node_in_range(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
132
int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size,
drivers/gpu/drm/i915/display/intel_parent.h
134
void intel_parent_stolen_remove_node(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
136
bool intel_parent_stolen_initialized(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
137
bool intel_parent_stolen_node_allocated(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
139
u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node);
drivers/gpu/drm/i915/display/intel_parent.h
140
u64 intel_parent_stolen_area_address(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
141
u64 intel_parent_stolen_area_size(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
142
u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node);
drivers/gpu/drm/i915/display/intel_parent.h
143
u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node);
drivers/gpu/drm/i915/display/intel_parent.h
144
struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
145
void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node);
drivers/gpu/drm/i915/display/intel_parent.h
148
void intel_parent_vlv_iosf_get(struct intel_display *display, unsigned long unit_mask);
drivers/gpu/drm/i915/display/intel_parent.h
149
void intel_parent_vlv_iosf_put(struct intel_display *display, unsigned long unit_mask);
drivers/gpu/drm/i915/display/intel_parent.h
150
u32 intel_parent_vlv_iosf_read(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr);
drivers/gpu/drm/i915/display/intel_parent.h
151
int intel_parent_vlv_iosf_write(struct intel_display *display, enum vlv_iosf_sb_unit unit, u32 addr, u32 val);
drivers/gpu/drm/i915/display/intel_parent.h
154
bool intel_parent_has_auxccs(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
155
bool intel_parent_has_fenced_regions(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
156
bool intel_parent_vgpu_active(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
157
void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
drivers/gpu/drm/i915/display/intel_parent.h
26
struct intel_dpt *intel_parent_dpt_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
28
void intel_parent_dpt_destroy(struct intel_display *display, struct intel_dpt *dpt);
drivers/gpu/drm/i915/display/intel_parent.h
29
void intel_parent_dpt_suspend(struct intel_display *display, struct intel_dpt *dpt);
drivers/gpu/drm/i915/display/intel_parent.h
30
void intel_parent_dpt_resume(struct intel_display *display, struct intel_dpt *dpt);
drivers/gpu/drm/i915/display/intel_parent.h
33
int intel_parent_fb_pin_ggtt_pin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
39
void intel_parent_fb_pin_ggtt_unpin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
42
int intel_parent_fb_pin_dpt_pin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
49
void intel_parent_fb_pin_dpt_unpin(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
53
struct i915_vma *intel_parent_fb_pin_reuse_vma(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
60
void intel_parent_fb_pin_get_map(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
64
struct intel_frontbuffer *intel_parent_frontbuffer_get(struct intel_display *display, struct drm_gem_object *obj);
drivers/gpu/drm/i915/display/intel_parent.h
65
void intel_parent_frontbuffer_ref(struct intel_display *display, struct intel_frontbuffer *front);
drivers/gpu/drm/i915/display/intel_parent.h
66
void intel_parent_frontbuffer_put(struct intel_display *display, struct intel_frontbuffer *front);
drivers/gpu/drm/i915/display/intel_parent.h
67
void intel_parent_frontbuffer_flush_for_display(struct intel_display *display, struct intel_frontbuffer *front);
drivers/gpu/drm/i915/display/intel_parent.h
70
ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
74
bool intel_parent_hdcp_gsc_check_status(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
75
struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
76
void intel_parent_hdcp_gsc_context_free(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
80
bool intel_parent_irq_enabled(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
81
void intel_parent_irq_synchronize(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
84
bool intel_parent_overlay_is_active(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
85
int intel_parent_overlay_on(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
87
int intel_parent_overlay_continue(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
90
int intel_parent_overlay_off(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
91
int intel_parent_overlay_recover_from_interrupt(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
92
int intel_parent_overlay_release_old_vid(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
93
void intel_parent_overlay_reset(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_parent.h
94
struct i915_vma *intel_parent_overlay_pin_fb(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
97
void intel_parent_overlay_unpin_fb(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_parent.h
99
struct drm_gem_object *intel_parent_overlay_obj_lookup(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch.c
100
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
101
!display->platform.haswell &&
drivers/gpu/drm/i915/display/intel_pch.c
102
!display->platform.broadwell);
drivers/gpu/drm/i915/display/intel_pch.c
103
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
104
!display->platform.haswell_ult &&
drivers/gpu/drm/i915/display/intel_pch.c
105
!display->platform.broadwell_ult);
drivers/gpu/drm/i915/display/intel_pch.c
108
drm_dbg_kms(display->drm, "Found WildcatPoint PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
109
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
110
!display->platform.haswell &&
drivers/gpu/drm/i915/display/intel_pch.c
111
!display->platform.broadwell);
drivers/gpu/drm/i915/display/intel_pch.c
112
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
113
display->platform.haswell_ult ||
drivers/gpu/drm/i915/display/intel_pch.c
114
display->platform.broadwell_ult);
drivers/gpu/drm/i915/display/intel_pch.c
118
drm_dbg_kms(display->drm, "Found WildcatPoint LP PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
119
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
120
!display->platform.haswell &&
drivers/gpu/drm/i915/display/intel_pch.c
121
!display->platform.broadwell);
drivers/gpu/drm/i915/display/intel_pch.c
122
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
123
!display->platform.haswell_ult &&
drivers/gpu/drm/i915/display/intel_pch.c
124
!display->platform.broadwell_ult);
drivers/gpu/drm/i915/display/intel_pch.c
128
drm_dbg_kms(display->drm, "Found SunrisePoint PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
129
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
130
!display->platform.skylake &&
drivers/gpu/drm/i915/display/intel_pch.c
131
!display->platform.kabylake &&
drivers/gpu/drm/i915/display/intel_pch.c
132
!display->platform.coffeelake);
drivers/gpu/drm/i915/display/intel_pch.c
135
drm_dbg_kms(display->drm, "Found SunrisePoint LP PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
136
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
137
!display->platform.skylake &&
drivers/gpu/drm/i915/display/intel_pch.c
138
!display->platform.kabylake &&
drivers/gpu/drm/i915/display/intel_pch.c
139
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
140
!display->platform.cometlake);
drivers/gpu/drm/i915/display/intel_pch.c
143
drm_dbg_kms(display->drm, "Found Kaby Lake PCH (KBP)\n");
drivers/gpu/drm/i915/display/intel_pch.c
144
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
145
!display->platform.skylake &&
drivers/gpu/drm/i915/display/intel_pch.c
146
!display->platform.kabylake &&
drivers/gpu/drm/i915/display/intel_pch.c
147
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
148
!display->platform.cometlake);
drivers/gpu/drm/i915/display/intel_pch.c
152
drm_dbg_kms(display->drm, "Found Cannon Lake PCH (CNP)\n");
drivers/gpu/drm/i915/display/intel_pch.c
153
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
154
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
155
!display->platform.cometlake);
drivers/gpu/drm/i915/display/intel_pch.c
158
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
160
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
161
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
162
!display->platform.cometlake);
drivers/gpu/drm/i915/display/intel_pch.c
166
drm_dbg_kms(display->drm, "Found Comet Lake PCH (CMP)\n");
drivers/gpu/drm/i915/display/intel_pch.c
167
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
168
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
169
!display->platform.cometlake &&
drivers/gpu/drm/i915/display/intel_pch.c
170
!display->platform.rocketlake);
drivers/gpu/drm/i915/display/intel_pch.c
174
drm_dbg_kms(display->drm, "Found Comet Lake V PCH (CMP-V)\n");
drivers/gpu/drm/i915/display/intel_pch.c
175
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
176
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
177
!display->platform.cometlake);
drivers/gpu/drm/i915/display/intel_pch.c
182
drm_dbg_kms(display->drm, "Found Ice Lake PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
183
drm_WARN_ON(display->drm, !display->platform.icelake);
drivers/gpu/drm/i915/display/intel_pch.c
186
drm_dbg_kms(display->drm, "Found Mule Creek Canyon PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
187
drm_WARN_ON(display->drm, !(display->platform.jasperlake ||
drivers/gpu/drm/i915/display/intel_pch.c
188
display->platform.elkhartlake));
drivers/gpu/drm/i915/display/intel_pch.c
193
drm_dbg_kms(display->drm, "Found Tiger Lake LP PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
194
drm_WARN_ON(display->drm, !display->platform.tigerlake &&
drivers/gpu/drm/i915/display/intel_pch.c
195
!display->platform.rocketlake &&
drivers/gpu/drm/i915/display/intel_pch.c
196
!display->platform.skylake &&
drivers/gpu/drm/i915/display/intel_pch.c
197
!display->platform.kabylake &&
drivers/gpu/drm/i915/display/intel_pch.c
198
!display->platform.coffeelake &&
drivers/gpu/drm/i915/display/intel_pch.c
199
!display->platform.cometlake);
drivers/gpu/drm/i915/display/intel_pch.c
202
drm_dbg_kms(display->drm, "Found Jasper Lake PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
203
drm_WARN_ON(display->drm, !(display->platform.jasperlake ||
drivers/gpu/drm/i915/display/intel_pch.c
204
display->platform.elkhartlake));
drivers/gpu/drm/i915/display/intel_pch.c
211
drm_dbg_kms(display->drm, "Found Alder Lake PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
212
drm_WARN_ON(display->drm, !display->platform.alderlake_s &&
drivers/gpu/drm/i915/display/intel_pch.c
213
!display->platform.alderlake_p);
drivers/gpu/drm/i915/display/intel_pch.c
220
static void intel_pch_ibx_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
227
intel_de_write(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_pch.c
231
static void intel_pch_cpt_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
241
intel_de_write(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_pch.c
245
intel_de_rmw(display, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
drivers/gpu/drm/i915/display/intel_pch.c
250
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/intel_pch.c
251
val = intel_de_read(display, TRANS_CHICKEN2(pipe));
drivers/gpu/drm/i915/display/intel_pch.c
254
if (display->vbt.fdi_rx_polarity_inverted)
drivers/gpu/drm/i915/display/intel_pch.c
258
intel_de_write(display, TRANS_CHICKEN2(pipe), val);
drivers/gpu/drm/i915/display/intel_pch.c
262
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/intel_pch.c
263
intel_de_write(display, TRANS_CHICKEN1(pipe),
drivers/gpu/drm/i915/display/intel_pch.c
267
static void intel_pch_lpt_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
273
if (HAS_PCH_LPT_LP(display))
drivers/gpu/drm/i915/display/intel_pch.c
274
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
drivers/gpu/drm/i915/display/intel_pch.c
278
intel_de_rmw(display, TRANS_CHICKEN1(PIPE_A), 0,
drivers/gpu/drm/i915/display/intel_pch.c
282
static void intel_pch_cnp_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
285
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
drivers/gpu/drm/i915/display/intel_pch.c
289
void intel_pch_init_clock_gating(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
291
switch (INTEL_PCH_TYPE(display)) {
drivers/gpu/drm/i915/display/intel_pch.c
293
intel_pch_ibx_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_pch.c
296
intel_pch_cpt_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_pch.c
300
intel_pch_lpt_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_pch.c
303
intel_pch_cnp_init_clock_gating(display);
drivers/gpu/drm/i915/display/intel_pch.c
321
intel_virt_detect_pch(const struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch.c
333
if (display->platform.alderlake_s || display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_pch.c
335
else if (display->platform.tigerlake || display->platform.rocketlake)
drivers/gpu/drm/i915/display/intel_pch.c
337
else if (display->platform.jasperlake || display->platform.elkhartlake)
drivers/gpu/drm/i915/display/intel_pch.c
339
else if (display->platform.icelake)
drivers/gpu/drm/i915/display/intel_pch.c
341
else if (display->platform.coffeelake ||
drivers/gpu/drm/i915/display/intel_pch.c
342
display->platform.cometlake)
drivers/gpu/drm/i915/display/intel_pch.c
344
else if (display->platform.kabylake || display->platform.skylake)
drivers/gpu/drm/i915/display/intel_pch.c
346
else if (display->platform.haswell_ult ||
drivers/gpu/drm/i915/display/intel_pch.c
347
display->platform.broadwell_ult)
drivers/gpu/drm/i915/display/intel_pch.c
349
else if (display->platform.haswell || display->platform.broadwell)
drivers/gpu/drm/i915/display/intel_pch.c
351
else if (DISPLAY_VER(display) == 6 || display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_pch.c
353
else if (DISPLAY_VER(display) == 5)
drivers/gpu/drm/i915/display/intel_pch.c
357
drm_dbg_kms(display->drm, "Assuming PCH ID %04x\n", id);
drivers/gpu/drm/i915/display/intel_pch.c
359
drm_dbg_kms(display->drm, "Assuming no PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
361
*pch_type = intel_pch_type(display, id);
drivers/gpu/drm/i915/display/intel_pch.c
364
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
371
void intel_pch_detect(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
377
pch_type = intel_pch_fake_for_south_display(display);
drivers/gpu/drm/i915/display/intel_pch.c
379
display->pch_type = pch_type;
drivers/gpu/drm/i915/display/intel_pch.c
380
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
403
pch_type = intel_pch_type(display, id);
drivers/gpu/drm/i915/display/intel_pch.c
405
display->pch_type = pch_type;
drivers/gpu/drm/i915/display/intel_pch.c
409
intel_virt_detect_pch(display, &id, &pch_type);
drivers/gpu/drm/i915/display/intel_pch.c
410
display->pch_type = pch_type;
drivers/gpu/drm/i915/display/intel_pch.c
419
if (pch && !HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_pch.c
420
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
422
display->pch_type = PCH_NOP;
drivers/gpu/drm/i915/display/intel_pch.c
424
if (intel_display_run_as_guest(display) && HAS_DISPLAY(display)) {
drivers/gpu/drm/i915/display/intel_pch.c
425
intel_virt_detect_pch(display, &id, &pch_type);
drivers/gpu/drm/i915/display/intel_pch.c
426
display->pch_type = pch_type;
drivers/gpu/drm/i915/display/intel_pch.c
428
drm_dbg_kms(display->drm, "No PCH found.\n");
drivers/gpu/drm/i915/display/intel_pch.c
51
static enum intel_pch intel_pch_fake_for_south_display(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch.c
55
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_pch.c
57
else if (display->platform.battlemage || display->platform.meteorlake)
drivers/gpu/drm/i915/display/intel_pch.c
59
else if (display->platform.dg2)
drivers/gpu/drm/i915/display/intel_pch.c
61
else if (display->platform.dg1)
drivers/gpu/drm/i915/display/intel_pch.c
69
intel_pch_type(const struct intel_display *display, unsigned short id)
drivers/gpu/drm/i915/display/intel_pch.c
73
drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
74
drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5);
drivers/gpu/drm/i915/display/intel_pch.c
77
drm_dbg_kms(display->drm, "Found CougarPoint PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
78
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
79
DISPLAY_VER(display) != 6 &&
drivers/gpu/drm/i915/display/intel_pch.c
80
!display->platform.ivybridge);
drivers/gpu/drm/i915/display/intel_pch.c
83
drm_dbg_kms(display->drm, "Found PantherPoint PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
84
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
85
DISPLAY_VER(display) != 6 &&
drivers/gpu/drm/i915/display/intel_pch.c
86
!display->platform.ivybridge);
drivers/gpu/drm/i915/display/intel_pch.c
90
drm_dbg_kms(display->drm, "Found LynxPoint PCH\n");
drivers/gpu/drm/i915/display/intel_pch.c
91
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
92
!display->platform.haswell &&
drivers/gpu/drm/i915/display/intel_pch.c
93
!display->platform.broadwell);
drivers/gpu/drm/i915/display/intel_pch.c
94
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pch.c
95
display->platform.haswell_ult ||
drivers/gpu/drm/i915/display/intel_pch.c
96
display->platform.broadwell_ult);
drivers/gpu/drm/i915/display/intel_pch.c
99
drm_dbg_kms(display->drm, "Found LynxPoint LP PCH\n");
drivers/gpu/drm/i915/display/intel_pch.h
38
#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2)
drivers/gpu/drm/i915/display/intel_pch.h
39
#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP)
drivers/gpu/drm/i915/display/intel_pch.h
40
#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1)
drivers/gpu/drm/i915/display/intel_pch.h
41
#define HAS_PCH_TGP(display) (INTEL_PCH_TYPE(display) == PCH_TGP)
drivers/gpu/drm/i915/display/intel_pch.h
42
#define HAS_PCH_ICP(display) (INTEL_PCH_TYPE(display) == PCH_ICP)
drivers/gpu/drm/i915/display/intel_pch.h
43
#define HAS_PCH_CNP(display) (INTEL_PCH_TYPE(display) == PCH_CNP)
drivers/gpu/drm/i915/display/intel_pch.h
44
#define HAS_PCH_SPT(display) (INTEL_PCH_TYPE(display) == PCH_SPT)
drivers/gpu/drm/i915/display/intel_pch.h
45
#define HAS_PCH_LPT_H(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H)
drivers/gpu/drm/i915/display/intel_pch.h
46
#define HAS_PCH_LPT_LP(display) (INTEL_PCH_TYPE(display) == PCH_LPT_LP)
drivers/gpu/drm/i915/display/intel_pch.h
47
#define HAS_PCH_LPT(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H || \
drivers/gpu/drm/i915/display/intel_pch.h
48
INTEL_PCH_TYPE(display) == PCH_LPT_LP)
drivers/gpu/drm/i915/display/intel_pch.h
49
#define HAS_PCH_CPT(display) (INTEL_PCH_TYPE(display) == PCH_CPT)
drivers/gpu/drm/i915/display/intel_pch.h
50
#define HAS_PCH_IBX(display) (INTEL_PCH_TYPE(display) == PCH_IBX)
drivers/gpu/drm/i915/display/intel_pch.h
51
#define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP)
drivers/gpu/drm/i915/display/intel_pch.h
52
#define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE)
drivers/gpu/drm/i915/display/intel_pch.h
54
void intel_pch_detect(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch.h
55
void intel_pch_init_clock_gating(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch_display.c
100
assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC);
drivers/gpu/drm/i915/display/intel_pch_display.c
101
assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID);
drivers/gpu/drm/i915/display/intel_pch_display.c
104
static void assert_pch_transcoder_disabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
110
val = intel_de_read(display, PCH_TRANSCONF(pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
112
INTEL_DISPLAY_STATE_WARN(display, enabled,
drivers/gpu/drm/i915/display/intel_pch_display.c
117
static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
120
u32 val = intel_de_read(display, hdmi_reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
126
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch_display.c
133
intel_de_write(display, hdmi_reg, val);
drivers/gpu/drm/i915/display/intel_pch_display.c
136
static void ibx_sanitize_pch_dp_port(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
139
u32 val = intel_de_read(display, dp_reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
145
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch_display.c
152
intel_de_write(display, dp_reg, val);
drivers/gpu/drm/i915/display/intel_pch_display.c
155
static void ibx_sanitize_pch_ports(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_display.c
168
ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B);
drivers/gpu/drm/i915/display/intel_pch_display.c
169
ibx_sanitize_pch_dp_port(display, PORT_C, PCH_DP_C);
drivers/gpu/drm/i915/display/intel_pch_display.c
170
ibx_sanitize_pch_dp_port(display, PORT_D, PCH_DP_D);
drivers/gpu/drm/i915/display/intel_pch_display.c
173
ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB);
drivers/gpu/drm/i915/display/intel_pch_display.c
174
ibx_sanitize_pch_hdmi_port(display, PORT_C, PCH_HDMIC);
drivers/gpu/drm/i915/display/intel_pch_display.c
175
ibx_sanitize_pch_hdmi_port(display, PORT_D, PCH_HDMID);
drivers/gpu/drm/i915/display/intel_pch_display.c
181
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
184
intel_set_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_pch_display.c
192
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
195
intel_set_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_pch_display.c
203
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
206
intel_get_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_pch_display.c
214
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
217
intel_get_m_n(display, m_n,
drivers/gpu/drm/i915/display/intel_pch_display.c
225
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_display.c
228
intel_de_write(display, PCH_TRANS_HTOTAL(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
229
intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
230
intel_de_write(display, PCH_TRANS_HBLANK(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
231
intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
232
intel_de_write(display, PCH_TRANS_HSYNC(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
233
intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
235
intel_de_write(display, PCH_TRANS_VTOTAL(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
236
intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
237
intel_de_write(display, PCH_TRANS_VBLANK(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
238
intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
239
intel_de_write(display, PCH_TRANS_VSYNC(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
24
bool intel_has_pch_trancoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
240
intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
241
intel_de_write(display, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
drivers/gpu/drm/i915/display/intel_pch_display.c
242
intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));
drivers/gpu/drm/i915/display/intel_pch_display.c
247
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_display.c
254
assert_dpll_enabled(display, crtc_state->intel_dpll);
drivers/gpu/drm/i915/display/intel_pch_display.c
257
assert_fdi_tx_enabled(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
258
assert_fdi_rx_enabled(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
260
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_pch_display.c
262
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
27
return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) ||
drivers/gpu/drm/i915/display/intel_pch_display.c
271
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_pch_display.c
275
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
276
pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
278
if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_pch_display.c
28
(HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A);
drivers/gpu/drm/i915/display/intel_pch_display.c
297
if (HAS_PCH_IBX(display) &&
drivers/gpu/drm/i915/display/intel_pch_display.c
306
intel_de_write(display, reg, val | TRANS_ENABLE);
drivers/gpu/drm/i915/display/intel_pch_display.c
307
if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE, 100))
drivers/gpu/drm/i915/display/intel_pch_display.c
308
drm_err(display->drm, "failed to enable transcoder %c\n",
drivers/gpu/drm/i915/display/intel_pch_display.c
314
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
319
assert_fdi_tx_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
320
assert_fdi_rx_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
323
assert_pch_ports_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
326
intel_de_rmw(display, reg, TRANS_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_pch_display.c
328
if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE, 50))
drivers/gpu/drm/i915/display/intel_pch_display.c
329
drm_err(display->drm, "failed to disable transcoder %c\n",
drivers/gpu/drm/i915/display/intel_pch_display.c
33
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
332
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_pch_display.c
334
intel_de_rmw(display, TRANS_CHICKEN2(pipe),
drivers/gpu/drm/i915/display/intel_pch_display.c
35
if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_pch_display.c
363
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
369
assert_pch_transcoder_disabled(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
378
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_pch_display.c
381
temp = intel_de_read(display, PCH_DPLL_SEL);
drivers/gpu/drm/i915/display/intel_pch_display.c
385
intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
drivers/gpu/drm/i915/display/intel_pch_display.c
389
intel_de_write(display, PCH_DPLL_SEL, temp);
drivers/gpu/drm/i915/display/intel_pch_display.c
404
assert_pps_unlocked(display, pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
41
static void assert_pch_dp_disabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
414
if (HAS_PCH_CPT(display) &&
drivers/gpu/drm/i915/display/intel_pch_display.c
418
u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
drivers/gpu/drm/i915/display/intel_pch_display.c
423
temp = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_pch_display.c
437
drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
drivers/gpu/drm/i915/display/intel_pch_display.c
440
intel_de_write(display, reg, temp);
drivers/gpu/drm/i915/display/intel_pch_display.c
455
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
462
if (HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_pch_display.c
464
intel_de_rmw(display, TRANS_DP_CTL(pipe),
drivers/gpu/drm/i915/display/intel_pch_display.c
469
intel_de_rmw(display, PCH_DPLL_SEL,
drivers/gpu/drm/i915/display/intel_pch_display.c
48
state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
480
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_display.c
491
intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),
drivers/gpu/drm/i915/display/intel_pch_display.c
497
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_display.c
50
INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
drivers/gpu/drm/i915/display/intel_pch_display.c
505
if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_pch_display.c
510
tmp = intel_de_read(display, FDI_RX_CTL(pipe));
drivers/gpu/drm/i915/display/intel_pch_display.c
517
if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_pch_display.c
524
tmp = intel_de_read(display, PCH_DPLL_SEL);
drivers/gpu/drm/i915/display/intel_pch_display.c
531
crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
drivers/gpu/drm/i915/display/intel_pch_display.c
534
pll_active = intel_dpll_get_hw_state(display, pll,
drivers/gpu/drm/i915/display/intel_pch_display.c
536
drm_WARN_ON(display->drm, !pll_active);
drivers/gpu/drm/i915/display/intel_pch_display.c
54
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_pch_display.c
548
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_display.c
55
HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,
drivers/gpu/drm/i915/display/intel_pch_display.c
553
assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder);
drivers/gpu/drm/i915/display/intel_pch_display.c
554
assert_fdi_rx_enabled(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_pch_display.c
556
val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));
drivers/gpu/drm/i915/display/intel_pch_display.c
562
intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);
drivers/gpu/drm/i915/display/intel_pch_display.c
565
pipeconf_val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_pch_display.c
566
TRANSCONF(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_pch_display.c
573
intel_de_write(display, LPT_TRANSCONF, val);
drivers/gpu/drm/i915/display/intel_pch_display.c
574
if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,
drivers/gpu/drm/i915/display/intel_pch_display.c
576
drm_err(display->drm, "Failed to enable PCH transcoder\n");
drivers/gpu/drm/i915/display/intel_pch_display.c
579
static void lpt_disable_pch_transcoder(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_display.c
581
intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_pch_display.c
583
if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,
drivers/gpu/drm/i915/display/intel_pch_display.c
585
drm_err(display->drm, "Failed to disable PCH transcoder\n");
drivers/gpu/drm/i915/display/intel_pch_display.c
588
intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
drivers/gpu/drm/i915/display/intel_pch_display.c
594
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
598
assert_pch_transcoder_disabled(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_pch_display.c
60
static void assert_pch_hdmi_disabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
611
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pch_display.c
613
lpt_disable_pch_transcoder(display);
drivers/gpu/drm/i915/display/intel_pch_display.c
615
lpt_disable_iclkip(display);
drivers/gpu/drm/i915/display/intel_pch_display.c
620
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_display.c
624
if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
drivers/gpu/drm/i915/display/intel_pch_display.c
629
tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));
drivers/gpu/drm/i915/display/intel_pch_display.c
636
crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);
drivers/gpu/drm/i915/display/intel_pch_display.c
639
void intel_pch_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_display.c
641
if (HAS_PCH_IBX(display))
drivers/gpu/drm/i915/display/intel_pch_display.c
642
ibx_sanitize_pch_ports(display);
drivers/gpu/drm/i915/display/intel_pch_display.c
67
state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe);
drivers/gpu/drm/i915/display/intel_pch_display.c
69
INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
drivers/gpu/drm/i915/display/intel_pch_display.c
73
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_pch_display.c
74
HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,
drivers/gpu/drm/i915/display/intel_pch_display.c
79
static void assert_pch_ports_disabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.c
84
assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B);
drivers/gpu/drm/i915/display/intel_pch_display.c
85
assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C);
drivers/gpu/drm/i915/display/intel_pch_display.c
86
assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D);
drivers/gpu/drm/i915/display/intel_pch_display.c
88
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_pch_display.c
89
intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
drivers/gpu/drm/i915/display/intel_pch_display.c
93
INTEL_DISPLAY_STATE_WARN(display,
drivers/gpu/drm/i915/display/intel_pch_display.c
94
intel_lvds_port_enabled(display, PCH_LVDS, &port_pipe) && port_pipe == pipe,
drivers/gpu/drm/i915/display/intel_pch_display.c
99
assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB);
drivers/gpu/drm/i915/display/intel_pch_display.h
19
bool intel_has_pch_trancoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.h
44
void intel_pch_sanitize(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch_display.h
46
static inline bool intel_has_pch_trancoder(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_display.h
93
static inline void intel_pch_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
100
intel_sbi_write(display, 0x21C4, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
102
tmp = intel_sbi_read(display, 0x20EC, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
105
intel_sbi_write(display, 0x20EC, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
107
tmp = intel_sbi_read(display, 0x21EC, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
110
intel_sbi_write(display, 0x21EC, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
113
void lpt_disable_iclkip(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
117
intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
119
intel_sbi_lock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
121
temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
123
intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
125
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
17
static void lpt_fdi_reset_mphy(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
185
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
190
lpt_disable_iclkip(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
193
drm_WARN_ON(display->drm, lpt_iclkip_freq(&p) != clock);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
196
drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
drivers/gpu/drm/i915/display/intel_pch_refclk.c
198
drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
drivers/gpu/drm/i915/display/intel_pch_refclk.c
201
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
205
intel_sbi_lock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
208
temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
21
intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
215
intel_sbi_write(display, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
218
temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
221
intel_sbi_write(display, SBI_SSCAUXDIV6, temp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
224
temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
226
intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
228
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
23
ret = intel_de_wait_for_set_us(display, SOUTH_CHICKEN2,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
233
intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
236
int lpt_get_iclkip(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
241
if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
246
intel_sbi_lock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
248
temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
250
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
254
temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
26
drm_err(display->drm, "FDI mPHY reset assert timeout\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
260
temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
264
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
277
static void lpt_enable_clkout_dp(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
28
intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
282
if (drm_WARN(display->drm, with_fdi && !with_spread,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
285
if (drm_WARN(display->drm, HAS_PCH_LPT_LP(display) &&
drivers/gpu/drm/i915/display/intel_pch_refclk.c
289
intel_sbi_lock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
291
tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
294
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
299
tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
30
ret = intel_de_wait_for_clear_us(display, SOUTH_CHICKEN2,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
301
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
304
lpt_fdi_program_mphy(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
307
reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;
drivers/gpu/drm/i915/display/intel_pch_refclk.c
308
tmp = intel_sbi_read(display, reg, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
310
intel_sbi_write(display, reg, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
312
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
316
void lpt_disable_clkout_dp(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
320
intel_sbi_lock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
322
reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;
drivers/gpu/drm/i915/display/intel_pch_refclk.c
323
tmp = intel_sbi_read(display, reg, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
325
intel_sbi_write(display, reg, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
327
tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
33
drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
331
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
335
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
338
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
37
static void lpt_fdi_program_mphy(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
373
static void lpt_bend_clkout_dp(struct intel_display *display, int steps)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
378
if (drm_WARN_ON(display->drm, steps % 5 != 0))
drivers/gpu/drm/i915/display/intel_pch_refclk.c
381
if (drm_WARN_ON(display->drm, idx >= ARRAY_SIZE(sscdivintphase)))
drivers/gpu/drm/i915/display/intel_pch_refclk.c
384
intel_sbi_lock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
390
intel_sbi_write(display, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
392
tmp = intel_sbi_read(display, SBI_SSCDIVINTPHASE, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
395
intel_sbi_write(display, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
397
intel_sbi_unlock(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
402
static bool spll_uses_pch_ssc(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
404
u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
405
u32 ctl = intel_de_read(display, SPLL_CTL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
41
lpt_fdi_reset_mphy(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
414
if (display->platform.broadwell &&
drivers/gpu/drm/i915/display/intel_pch_refclk.c
421
static bool wrpll_uses_pch_ssc(struct intel_display *display, enum intel_dpll_id id)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
423
u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
424
u32 ctl = intel_de_read(display, WRPLL_CTL(id));
drivers/gpu/drm/i915/display/intel_pch_refclk.c
43
tmp = intel_sbi_read(display, 0x8008, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
432
if ((display->platform.broadwell || display->platform.haswell_ult) &&
drivers/gpu/drm/i915/display/intel_pch_refclk.c
440
static void lpt_init_pch_refclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
445
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
46
intel_sbi_write(display, 0x8008, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
470
display->dpll.pch_ssc_use = 0;
drivers/gpu/drm/i915/display/intel_pch_refclk.c
472
if (spll_uses_pch_ssc(display)) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
473
drm_dbg_kms(display->drm, "SPLL using PCH SSC\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
474
display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
477
if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL1)) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
478
drm_dbg_kms(display->drm, "WRPLL1 using PCH SSC\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
479
display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
48
tmp = intel_sbi_read(display, 0x2008, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
482
if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL2)) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
483
drm_dbg_kms(display->drm, "WRPLL2 using PCH SSC\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
484
display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
487
if (display->dpll.pch_ssc_use)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
491
lpt_bend_clkout_dp(display, 0);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
492
lpt_enable_clkout_dp(display, true, true);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
494
lpt_disable_clkout_dp(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
498
static void ilk_init_pch_refclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
50
intel_sbi_write(display, 0x2008, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
512
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
52
tmp = intel_sbi_read(display, 0x2108, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
528
if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
529
has_ck505 = display->vbt.display_clock_mode;
drivers/gpu/drm/i915/display/intel_pch_refclk.c
537
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
54
intel_sbi_write(display, 0x2108, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
540
temp = intel_de_read(display, PCH_DPLL(pll->info->id));
drivers/gpu/drm/i915/display/intel_pch_refclk.c
552
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
56
tmp = intel_sbi_read(display, 0x206C, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
561
val = intel_de_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
58
intel_sbi_write(display, 0x206C, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
581
if (intel_panel_use_ssc(display) && can_ssc)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
585
if (intel_panel_use_ssc(display) && can_ssc)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
60
tmp = intel_sbi_read(display, 0x216C, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
613
if (intel_panel_use_ssc(display) && can_ssc) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
614
drm_dbg_kms(display->drm, "Using SSC on panel\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
62
intel_sbi_write(display, 0x216C, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
621
intel_de_write(display, PCH_DREF_CONTROL, val);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
622
intel_de_posting_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
629
if (intel_panel_use_ssc(display) && can_ssc) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
630
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
64
tmp = intel_sbi_read(display, 0x2080, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
640
intel_de_write(display, PCH_DREF_CONTROL, val);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
641
intel_de_posting_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
644
drm_dbg_kms(display->drm, "Disabling CPU source output\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
651
intel_de_write(display, PCH_DREF_CONTROL, val);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
652
intel_de_posting_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
656
drm_dbg_kms(display->drm, "Disabling SSC source\n");
drivers/gpu/drm/i915/display/intel_pch_refclk.c
665
intel_de_write(display, PCH_DREF_CONTROL, val);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
666
intel_de_posting_read(display, PCH_DREF_CONTROL);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
67
intel_sbi_write(display, 0x2080, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
671
drm_WARN_ON(display->drm, val != final);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
677
void intel_init_pch_refclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.c
679
if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_pch_refclk.c
680
ilk_init_pch_refclk(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
681
else if (HAS_PCH_LPT(display))
drivers/gpu/drm/i915/display/intel_pch_refclk.c
682
lpt_init_pch_refclk(display);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
69
tmp = intel_sbi_read(display, 0x2180, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
72
intel_sbi_write(display, 0x2180, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
74
tmp = intel_sbi_read(display, 0x208C, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
77
intel_sbi_write(display, 0x208C, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
79
tmp = intel_sbi_read(display, 0x218C, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
82
intel_sbi_write(display, 0x218C, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
84
tmp = intel_sbi_read(display, 0x2098, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
87
intel_sbi_write(display, 0x2098, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
89
tmp = intel_sbi_read(display, 0x2198, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
92
intel_sbi_write(display, 0x2198, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
94
tmp = intel_sbi_read(display, 0x20C4, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
96
intel_sbi_write(display, 0x20C4, tmp, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.c
98
tmp = intel_sbi_read(display, 0x21C4, SBI_MPHY);
drivers/gpu/drm/i915/display/intel_pch_refclk.h
16
void lpt_disable_iclkip(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch_refclk.h
17
int lpt_get_iclkip(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch_refclk.h
20
void intel_init_pch_refclk(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch_refclk.h
21
void lpt_disable_clkout_dp(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pch_refclk.h
26
static inline void lpt_disable_iclkip(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.h
29
static inline int lpt_get_iclkip(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.h
37
static inline void intel_init_pch_refclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pch_refclk.h
40
static inline void lpt_disable_clkout_dp(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pfit.c
110
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
122
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
132
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
145
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
151
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
163
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
175
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
188
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
207
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
21
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
268
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
282
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_pfit.c
33
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
443
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
449
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_pfit.c
455
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
463
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
476
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
493
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
50
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
500
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
519
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_pfit.c
533
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_pfit.c
549
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_pfit.c
559
if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18)
drivers/gpu/drm/i915/display/intel_pfit.c
573
intel_pfit_mode_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pfit.c
578
return skl_scaler_mode_valid(display, mode, output_format,
drivers/gpu/drm/i915/display/intel_pfit.c
585
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
587
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_pfit.c
595
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
61
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
611
if (display->platform.ivybridge || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_pfit.c
612
intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |
drivers/gpu/drm/i915/display/intel_pfit.c
615
intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |
drivers/gpu/drm/i915/display/intel_pfit.c
617
intel_de_write_fw(display, PF_WIN_POS(pipe),
drivers/gpu/drm/i915/display/intel_pfit.c
619
intel_de_write_fw(display, PF_WIN_SZ(pipe),
drivers/gpu/drm/i915/display/intel_pfit.c
625
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
636
intel_de_write_fw(display, PF_CTL(pipe), 0);
drivers/gpu/drm/i915/display/intel_pfit.c
637
intel_de_write_fw(display, PF_WIN_POS(pipe), 0);
drivers/gpu/drm/i915/display/intel_pfit.c
638
intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);
drivers/gpu/drm/i915/display/intel_pfit.c
643
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
648
ctl = intel_de_read(display, PF_CTL(crtc->pipe));
drivers/gpu/drm/i915/display/intel_pfit.c
652
if (display->platform.ivybridge || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_pfit.c
659
pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));
drivers/gpu/drm/i915/display/intel_pfit.c
660
size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));
drivers/gpu/drm/i915/display/intel_pfit.c
673
drm_WARN_ON(display->drm, pipe != crtc->pipe);
drivers/gpu/drm/i915/display/intel_pfit.c
678
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
688
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.c
689
intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);
drivers/gpu/drm/i915/display/intel_pfit.c
690
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_pfit.c
692
intel_de_write(display, PFIT_PGM_RATIOS(display),
drivers/gpu/drm/i915/display/intel_pfit.c
694
intel_de_write(display, PFIT_CONTROL(display),
drivers/gpu/drm/i915/display/intel_pfit.c
701
intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_pfit.c
706
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
711
assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_pfit.c
713
drm_dbg_kms(display->drm, "disabling pfit, current: 0x%08x\n",
drivers/gpu/drm/i915/display/intel_pfit.c
714
intel_de_read(display, PFIT_CONTROL(display)));
drivers/gpu/drm/i915/display/intel_pfit.c
715
intel_de_write(display, PFIT_CONTROL(display), 0);
drivers/gpu/drm/i915/display/intel_pfit.c
718
static bool i9xx_has_pfit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pfit.c
72
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
720
if (display->platform.i830)
drivers/gpu/drm/i915/display/intel_pfit.c
723
return DISPLAY_VER(display) >= 4 ||
drivers/gpu/drm/i915/display/intel_pfit.c
724
display->platform.pineview || display->platform.mobile;
drivers/gpu/drm/i915/display/intel_pfit.c
729
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_pfit.c
734
if (!i9xx_has_pfit(display))
drivers/gpu/drm/i915/display/intel_pfit.c
737
tmp = intel_de_read(display, PFIT_CONTROL(display));
drivers/gpu/drm/i915/display/intel_pfit.c
742
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_pfit.c
752
intel_de_read(display, PFIT_PGM_RATIOS(display));
drivers/gpu/drm/i915/display/intel_pfit.c
78
if (DISPLAY_VER(display) >= 8) {
drivers/gpu/drm/i915/display/intel_pfit.c
81
} else if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/intel_pfit.c
98
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pfit.h
25
intel_pfit_mode_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
117
drm_WARN(display->drm, 1, "nonexisting DP port %c\n",
drivers/gpu/drm/i915/display/intel_pipe_crc.c
126
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
129
static int vlv_pipe_crc_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
137
i9xx_pipe_crc_auto_source(display, pipe, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
152
if (!display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
174
u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
190
intel_de_write(display, PORT_DFT2_G4X(display), tmp);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
196
static int i9xx_pipe_crc_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
202
i9xx_pipe_crc_auto_source(display, pipe, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
209
if (!SUPPORTS_TV(display))
drivers/gpu/drm/i915/display/intel_pipe_crc.c
233
static void vlv_undo_pipe_scramble_reset(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
236
u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
253
intel_de_write(display, PORT_DFT2_G4X(display), tmp);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
285
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
291
if (display->platform.i945gm || display->platform.i915gm)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
292
i915gm_irq_cstate_wa(display, enable);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
296
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
315
if (display->platform.haswell &&
drivers/gpu/drm/i915/display/intel_pipe_crc.c
331
drm_WARN(display->drm, ret,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
337
static int ivb_pipe_crc_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
365
static int skl_pipe_crc_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
408
static int get_new_crc_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
412
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
414
else if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
415
return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
416
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
417
return vlv_pipe_crc_ctl_reg(display, pipe, source, val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
418
else if (display->platform.ironlake || display->platform.sandybridge)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
420
else if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
421
return ivb_pipe_crc_ctl_reg(display, pipe, source, val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
423
return skl_pipe_crc_ctl_reg(display, pipe, source, val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
451
static int i8xx_crc_source_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
463
static int i9xx_crc_source_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
476
static int vlv_crc_source_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
491
static int ilk_crc_source_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
505
static int ivb_crc_source_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
519
static int skl_crc_source_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
539
intel_is_valid_crc_source(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
542
if (DISPLAY_VER(display) == 2)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
543
return i8xx_crc_source_valid(display, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
544
else if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
545
return i9xx_crc_source_valid(display, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
546
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
547
return vlv_crc_source_valid(display, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
548
else if (display->platform.ironlake || display->platform.sandybridge)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
549
return ilk_crc_source_valid(display, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
550
else if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
551
return ivb_crc_source_valid(display, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
553
return skl_crc_source_valid(display, source);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
566
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
570
drm_dbg_kms(display->drm, "unknown source %s\n", source_name);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
575
intel_is_valid_crc_source(display, source) == 0) {
drivers/gpu/drm/i915/display/intel_pipe_crc.c
586
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
597
drm_dbg_kms(display->drm, "unknown source %s\n", source_name);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
602
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
604
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
613
ret = get_new_crc_ctl_reg(display, pipe, &source, &val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
618
intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
619
intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
622
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
623
vlv_undo_pipe_scramble_reset(display, pipe);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
632
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
639
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
647
if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0)
drivers/gpu/drm/i915/display/intel_pipe_crc.c
653
intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
654
intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
659
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
668
intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
669
intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
drivers/gpu/drm/i915/display/intel_pipe_crc.c
670
intel_parent_irq_synchronize(display);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
79
static void i9xx_pipe_crc_auto_source(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pipe_crc.c
89
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_pipe_crc.c
90
for_each_intel_encoder(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_plane.c
1077
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_plane.c
1079
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_plane.c
1090
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
1110
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
1127
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
1142
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
1176
} else if (DISPLAY_VER(display) >= 20 &&
drivers/gpu/drm/i915/display/intel_plane.c
1186
if ((DISPLAY_VERx100(display) == 2000 ||
drivers/gpu/drm/i915/display/intel_plane.c
1187
DISPLAY_VERx100(display) == 3000 ||
drivers/gpu/drm/i915/display/intel_plane.c
1188
DISPLAY_VERx100(display) == 3002) &&
drivers/gpu/drm/i915/display/intel_plane.c
1192
if (DISPLAY_VER(display) == 35)
drivers/gpu/drm/i915/display/intel_plane.c
1203
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
1211
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
1252
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
1265
ggtt_vma = intel_parent_fb_pin_reuse_vma(display,
drivers/gpu/drm/i915/display/intel_plane.c
1282
.needs_low_address = intel_plane_needs_low_address(display),
drivers/gpu/drm/i915/display/intel_plane.c
1284
.needs_fence = intel_plane_needs_fence(display),
drivers/gpu/drm/i915/display/intel_plane.c
1287
ret = intel_parent_fb_pin_ggtt_pin(display, intel_fb_bo(&fb->base),
drivers/gpu/drm/i915/display/intel_plane.c
1297
ret = intel_parent_fb_pin_dpt_pin(display, intel_fb_bo(&fb->base),
drivers/gpu/drm/i915/display/intel_plane.c
1316
struct intel_display *display = to_intel_display(old_plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
1321
intel_parent_fb_pin_ggtt_unpin(display,
drivers/gpu/drm/i915/display/intel_plane.c
1328
intel_parent_fb_pin_dpt_unpin(display, fb->dpt,
drivers/gpu/drm/i915/display/intel_plane.c
1389
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_plane.c
1436
intel_parent_fence_priority_display(display, new_plane_state->uapi.fence);
drivers/gpu/drm/i915/display/intel_plane.c
1449
intel_display_rps_mark_interactive(display, state, true);
drivers/gpu/drm/i915/display/intel_plane.c
1470
struct intel_display *display = to_intel_display(plane->dev);
drivers/gpu/drm/i915/display/intel_plane.c
1480
intel_display_rps_mark_interactive(display, state, false);
drivers/gpu/drm/i915/display/intel_plane.c
1533
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_plane.c
1539
intel_parent_panic_finish(display, fb->panic);
drivers/gpu/drm/i915/display/intel_plane.c
1547
if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {
drivers/gpu/drm/i915/display/intel_plane.c
1550
intel_fbdev_get_map(display, &map);
drivers/gpu/drm/i915/display/intel_plane.c
1595
struct intel_display *display = to_intel_display(plane->dev);
drivers/gpu/drm/i915/display/intel_plane.c
1607
if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {
drivers/gpu/drm/i915/display/intel_plane.c
1608
intel_fbdev_get_map(display, &sb->map[0]);
drivers/gpu/drm/i915/display/intel_plane.c
1620
ret = intel_parent_panic_setup(display, fb->panic, sb);
drivers/gpu/drm/i915/display/intel_plane.c
1670
struct intel_display *display = to_intel_display(uv_plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
1674
drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_plane.c
1706
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_plane.c
1713
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/intel_plane.c
1729
for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {
drivers/gpu/drm/i915/display/intel_plane.c
1730
if (!icl_is_nv12_y_plane(display, y_plane->id))
drivers/gpu/drm/i915/display/intel_plane.c
1744
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
1761
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_plane.c
1764
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_plane.c
1791
static bool active_planes_affects_min_cdclk(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_plane.c
1794
return display->platform.broadwell || display->platform.haswell ||
drivers/gpu/drm/i915/display/intel_plane.c
1795
display->platform.cherryview || display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_plane.c
1796
display->platform.ivybridge;
drivers/gpu/drm/i915/display/intel_plane.c
1824
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_plane.c
1842
for_each_intel_crtc_in_pipe_mask(display, crtc, joined_pipes) {
drivers/gpu/drm/i915/display/intel_plane.c
1875
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_plane.c
1889
drm_dbg_atomic(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
1908
if (!active_planes_affects_min_cdclk(display))
drivers/gpu/drm/i915/display/intel_plane.c
193
bool intel_plane_needs_low_address(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_plane.c
203
return HAS_GMCH(display);
drivers/gpu/drm/i915/display/intel_plane.c
208
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_plane.c
211
DISPLAY_INFO(display)->cursor_needs_physical;
drivers/gpu/drm/i915/display/intel_plane.c
214
bool intel_plane_needs_fence(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_plane.c
220
return DISPLAY_VER(display) < 4;
drivers/gpu/drm/i915/display/intel_plane.c
379
struct intel_display *display = to_intel_display(new_plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
383
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_plane.c
492
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_plane.c
503
drm_WARN_ON(display->drm, plane_state->uapi.visible);
drivers/gpu/drm/i915/display/intel_plane.c
549
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_plane.c
570
return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;
drivers/gpu/drm/i915/display/intel_plane.c
674
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_plane.c
683
if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {
drivers/gpu/drm/i915/display/intel_plane.c
692
if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))
drivers/gpu/drm/i915/display/intel_plane.c
716
drm_dbg_atomic(display->drm,
drivers/gpu/drm/i915/display/intel_plane.c
726
if (HAS_GMCH(display) &&
drivers/gpu/drm/i915/display/intel_plane.c
730
if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&
drivers/gpu/drm/i915/display/intel_plane.c
825
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_plane.c
828
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/intel_plane.c
839
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_plane.c
846
struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
drivers/gpu/drm/i915/display/intel_plane.h
83
bool intel_plane_needs_low_address(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_plane.h
85
bool intel_plane_needs_fence(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pmdemand.c
110
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
113
&display->pmdemand.obj);
drivers/gpu/drm/i915/display/intel_pmdemand.c
121
int intel_pmdemand_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pmdemand.c
129
intel_atomic_global_obj_init(display, &display->pmdemand.obj,
drivers/gpu/drm/i915/display/intel_pmdemand.c
134
if (intel_display_wa(display, INTEL_DISPLAY_WA_14016740474))
drivers/gpu/drm/i915/display/intel_pmdemand.c
135
intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0,
drivers/gpu/drm/i915/display/intel_pmdemand.c
141
void intel_pmdemand_init_early(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pmdemand.c
143
mutex_init(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
144
init_waitqueue_head(&display->pmdemand.waitqueue);
drivers/gpu/drm/i915/display/intel_pmdemand.c
148
intel_pmdemand_update_phys_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
155
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_pmdemand.c
173
intel_pmdemand_update_port_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
177
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_pmdemand.c
184
intel_pmdemand_update_max_ddiclk(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
194
intel_pmdemand_update_port_clock(display, pmdemand_state,
drivers/gpu/drm/i915/display/intel_pmdemand.c
205
intel_pmdemand_update_connector_phys(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
226
intel_pmdemand_update_phys_mask(display, encoder, pmdemand_state,
drivers/gpu/drm/i915/display/intel_pmdemand.c
231
intel_pmdemand_update_active_non_tc_phys(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
246
intel_pmdemand_update_connector_phys(display, state,
drivers/gpu/drm/i915/display/intel_pmdemand.c
251
intel_pmdemand_update_connector_phys(display, state,
drivers/gpu/drm/i915/display/intel_pmdemand.c
262
intel_pmdemand_encoder_has_tc_phy(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
271
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
288
(intel_pmdemand_encoder_has_tc_phy(display, old_encoder) &&
drivers/gpu/drm/i915/display/intel_pmdemand.c
289
intel_pmdemand_encoder_has_tc_phy(display, new_encoder)))
drivers/gpu/drm/i915/display/intel_pmdemand.c
321
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
327
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_pmdemand.c
349
if (DISPLAY_VER(display) < 30) {
drivers/gpu/drm/i915/display/intel_pmdemand.c
356
min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));
drivers/gpu/drm/i915/display/intel_pmdemand.c
368
intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
370
intel_pmdemand_update_active_non_tc_phys(display, state, new_pmdemand_state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
391
static bool intel_pmdemand_check_prev_transaction(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pmdemand.c
393
return !(intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
396
intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
402
intel_pmdemand_init_pmdemand_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
407
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_pmdemand.c
410
mutex_lock(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
411
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pmdemand.c
412
!intel_pmdemand_check_prev_transaction(display))) {
drivers/gpu/drm/i915/display/intel_pmdemand.c
418
reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
drivers/gpu/drm/i915/display/intel_pmdemand.c
420
reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
drivers/gpu/drm/i915/display/intel_pmdemand.c
436
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_pmdemand.c
450
mutex_unlock(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
453
static bool intel_pmdemand_req_complete(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pmdemand.c
455
return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
drivers/gpu/drm/i915/display/intel_pmdemand.c
459
static void intel_pmdemand_poll(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pmdemand.c
465
ret = intel_de_wait_ms(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
drivers/gpu/drm/i915/display/intel_pmdemand.c
470
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_pmdemand.c
475
static void intel_pmdemand_wait(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pmdemand.c
478
if (DISPLAY_VER(display) == 20) {
drivers/gpu/drm/i915/display/intel_pmdemand.c
479
intel_pmdemand_poll(display);
drivers/gpu/drm/i915/display/intel_pmdemand.c
481
if (!wait_event_timeout(display->pmdemand.waitqueue,
drivers/gpu/drm/i915/display/intel_pmdemand.c
482
intel_pmdemand_req_complete(display),
drivers/gpu/drm/i915/display/intel_pmdemand.c
484
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_pmdemand.c
490
void intel_pmdemand_program_dbuf(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
496
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_pmdemand.c
499
mutex_lock(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
500
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pmdemand.c
501
!intel_pmdemand_check_prev_transaction(display)))
drivers/gpu/drm/i915/display/intel_pmdemand.c
504
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
drivers/gpu/drm/i915/display/intel_pmdemand.c
507
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
drivers/gpu/drm/i915/display/intel_pmdemand.c
510
intel_pmdemand_wait(display);
drivers/gpu/drm/i915/display/intel_pmdemand.c
513
mutex_unlock(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
517
intel_pmdemand_update_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
560
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/intel_pmdemand.c
573
intel_pmdemand_program_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.c
582
mutex_lock(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
583
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pmdemand.c
584
!intel_pmdemand_check_prev_transaction(display)))
drivers/gpu/drm/i915/display/intel_pmdemand.c
587
reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
drivers/gpu/drm/i915/display/intel_pmdemand.c
590
reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
drivers/gpu/drm/i915/display/intel_pmdemand.c
593
intel_pmdemand_update_params(display, new, old, &mod_reg1, &mod_reg2,
drivers/gpu/drm/i915/display/intel_pmdemand.c
597
intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
drivers/gpu/drm/i915/display/intel_pmdemand.c
603
intel_de_write(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
drivers/gpu/drm/i915/display/intel_pmdemand.c
612
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pmdemand.c
616
intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
drivers/gpu/drm/i915/display/intel_pmdemand.c
619
intel_pmdemand_wait(display);
drivers/gpu/drm/i915/display/intel_pmdemand.c
622
mutex_unlock(&display->pmdemand.lock);
drivers/gpu/drm/i915/display/intel_pmdemand.c
634
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
640
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_pmdemand.c
650
intel_pmdemand_program_params(display, new_pmdemand_state,
drivers/gpu/drm/i915/display/intel_pmdemand.c
657
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
663
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_pmdemand.c
673
intel_pmdemand_program_params(display, new_pmdemand_state, NULL,
drivers/gpu/drm/i915/display/intel_pmdemand.c
82
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
85
&display->pmdemand.obj);
drivers/gpu/drm/i915/display/intel_pmdemand.c
96
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_pmdemand.c
99
&display->pmdemand.obj);
drivers/gpu/drm/i915/display/intel_pmdemand.h
22
void intel_pmdemand_init_early(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pmdemand.h
23
int intel_pmdemand_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pmdemand.h
24
void intel_pmdemand_init_pmdemand_params(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.h
26
void intel_pmdemand_update_port_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.h
29
void intel_pmdemand_update_phys_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pmdemand.h
33
void intel_pmdemand_program_dbuf(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pps.c
1000
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
1001
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1006
if (IS_DISPLAY_VER(display, 13, 14))
drivers/gpu/drm/i915/display/intel_pps.c
1007
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_pps.c
1010
if (display->platform.ironlake) {
drivers/gpu/drm/i915/display/intel_pps.c
1012
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
1013
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1028
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1033
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
1038
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
drivers/gpu/drm/i915/display/intel_pps.c
104
if (drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1042
drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,
drivers/gpu/drm/i915/display/intel_pps.c
105
intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,
drivers/gpu/drm/i915/display/intel_pps.c
1057
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
1058
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1066
intel_display_power_put(display,
drivers/gpu/drm/i915/display/intel_pps.c
1083
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1100
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
1101
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1108
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
111
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1120
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
1121
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1134
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_pps.c
1144
drm_dbg_kms(display->drm, "panel power control backlight %s\n",
drivers/gpu/drm/i915/display/intel_pps.c
1155
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1158
intel_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1160
drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_pps.c
1162
if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
drivers/gpu/drm/i915/display/intel_pps.c
1176
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1180
intel_de_write(display, pp_on_reg, 0);
drivers/gpu/drm/i915/display/intel_pps.c
1181
intel_de_posting_read(display, pp_on_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1186
static void vlv_steal_power_sequencer(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pps.c
119
DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
drivers/gpu/drm/i915/display/intel_pps.c
1191
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
1193
for_each_intel_dp(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_pps.c
1196
drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,
drivers/gpu/drm/i915/display/intel_pps.c
1204
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1216
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1220
if (g4x_dp_port_enabled(display, intel_dp->output_reg,
drivers/gpu/drm/i915/display/intel_pps.c
124
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pps.c
1265
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_pps.c
1269
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
1271
drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_pps.c
1287
vlv_steal_power_sequencer(display, crtc->pipe);
drivers/gpu/drm/i915/display/intel_pps.c
129
pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
drivers/gpu/drm/i915/display/intel_pps.c
1297
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1319
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1322
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
1333
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1337
drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
drivers/gpu/drm/i915/display/intel_pps.c
1338
intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_pps.c
136
release_cl_override = display->platform.cherryview &&
drivers/gpu/drm/i915/display/intel_pps.c
137
!chv_phy_powergate_ch(display, phy, ch, true);
drivers/gpu/drm/i915/display/intel_pps.c
1370
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1379
if (!HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_pps.c
1380
intel_de_write(display, regs.pp_ctrl, pp_ctl);
drivers/gpu/drm/i915/display/intel_pps.c
1382
pp_on = intel_de_read(display, regs.pp_on);
drivers/gpu/drm/i915/display/intel_pps.c
1383
pp_off = intel_de_read(display, regs.pp_off);
drivers/gpu/drm/i915/display/intel_pps.c
139
if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) {
drivers/gpu/drm/i915/display/intel_pps.c
1394
pp_div = intel_de_read(display, regs.pp_div);
drivers/gpu/drm/i915/display/intel_pps.c
140
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1409
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1411
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1420
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1431
drm_err(display->drm, "PPS state mismatch\n");
drivers/gpu/drm/i915/display/intel_pps.c
1458
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1460
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
1473
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1487
if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {
drivers/gpu/drm/i915/display/intel_pps.c
1489
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1500
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1502
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
1516
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1520
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
153
intel_de_write(display, intel_dp->output_reg, DP);
drivers/gpu/drm/i915/display/intel_pps.c
154
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1548
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1554
drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",
drivers/gpu/drm/i915/display/intel_pps.c
156
intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);
drivers/gpu/drm/i915/display/intel_pps.c
157
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1578
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1580
int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;
drivers/gpu/drm/i915/display/intel_pps.c
1585
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
159
intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);
drivers/gpu/drm/i915/display/intel_pps.c
160
intel_de_posting_read(display, intel_dp->output_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1604
drm_WARN(display->drm, pp & PANEL_POWER_ON,
drivers/gpu/drm/i915/display/intel_pps.c
1608
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1613
intel_de_write(display, regs.pp_ctrl, pp);
drivers/gpu/drm/i915/display/intel_pps.c
1623
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_pps.c
1625
} else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {
drivers/gpu/drm/i915/display/intel_pps.c
163
vlv_force_pll_off(display, pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1644
intel_de_write(display, regs.pp_on, pp_on);
drivers/gpu/drm/i915/display/intel_pps.c
1645
intel_de_write(display, regs.pp_off, pp_off);
drivers/gpu/drm/i915/display/intel_pps.c
1651
intel_de_write(display, regs.pp_div,
drivers/gpu/drm/i915/display/intel_pps.c
1657
intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
drivers/gpu/drm/i915/display/intel_pps.c
166
chv_phy_powergate_ch(display, phy, ch, false);
drivers/gpu/drm/i915/display/intel_pps.c
1661
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1663
intel_de_read(display, regs.pp_on),
drivers/gpu/drm/i915/display/intel_pps.c
1664
intel_de_read(display, regs.pp_off),
drivers/gpu/drm/i915/display/intel_pps.c
1666
intel_de_read(display, regs.pp_div) :
drivers/gpu/drm/i915/display/intel_pps.c
1667
(intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
drivers/gpu/drm/i915/display/intel_pps.c
1672
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1682
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pps.c
170
static enum pipe vlv_find_free_pps(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pps.c
1716
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
1720
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pps.c
1723
if (intel_num_pps(display) < 2)
drivers/gpu/drm/i915/display/intel_pps.c
1726
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1754
void intel_pps_unlock_regs_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pps.c
1759
if (!HAS_DISPLAY(display) || HAS_DDI(display))
drivers/gpu/drm/i915/display/intel_pps.c
1765
pps_num = intel_num_pps(display);
drivers/gpu/drm/i915/display/intel_pps.c
1768
intel_de_rmw(display, PP_CONTROL(display, pps_idx),
drivers/gpu/drm/i915/display/intel_pps.c
1772
void intel_pps_setup(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pps.c
1774
if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_pps.c
1775
display->pps.mmio_base = PCH_PPS_BASE;
drivers/gpu/drm/i915/display/intel_pps.c
1776
else if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pps.c
1777
display->pps.mmio_base = VLV_PPS_BASE;
drivers/gpu/drm/i915/display/intel_pps.c
1779
display->pps.mmio_base = PPS_BASE;
drivers/gpu/drm/i915/display/intel_pps.c
179
for_each_intel_dp(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_pps.c
1815
void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
drivers/gpu/drm/i915/display/intel_pps.c
1822
if (drm_WARN_ON(display->drm, HAS_DDI(display)))
drivers/gpu/drm/i915/display/intel_pps.c
1825
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_pps.c
1828
pp_reg = PP_CONTROL(display, 0);
drivers/gpu/drm/i915/display/intel_pps.c
1829
port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
drivers/gpu/drm/i915/display/intel_pps.c
183
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1834
intel_lvds_port_enabled(display, PCH_LVDS, &panel_pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1837
g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1840
g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1843
g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1849
} else if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_pps.c
1851
pp_reg = PP_CONTROL(display, pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1856
pp_reg = PP_CONTROL(display, 0);
drivers/gpu/drm/i915/display/intel_pps.c
1857
port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
drivers/gpu/drm/i915/display/intel_pps.c
1860
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
1862
intel_lvds_port_enabled(display, LVDS, &panel_pipe);
drivers/gpu/drm/i915/display/intel_pps.c
1865
val = intel_de_read(display, pp_reg);
drivers/gpu/drm/i915/display/intel_pps.c
1870
INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,
drivers/gpu/drm/i915/display/intel_pps.c
191
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
208
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
212
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
215
drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
drivers/gpu/drm/i915/display/intel_pps.c
217
drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
drivers/gpu/drm/i915/display/intel_pps.c
223
pipe = vlv_find_free_pps(display);
drivers/gpu/drm/i915/display/intel_pps.c
229
if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))
drivers/gpu/drm/i915/display/intel_pps.c
232
vlv_steal_power_sequencer(display, pipe);
drivers/gpu/drm/i915/display/intel_pps.c
235
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
256
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
259
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
262
drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
drivers/gpu/drm/i915/display/intel_pps.c
27
static void vlv_steal_power_sequencer(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pps.c
278
typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
drivers/gpu/drm/i915/display/intel_pps.c
280
static bool pps_has_pp_on(struct intel_display *display, int pps_idx)
drivers/gpu/drm/i915/display/intel_pps.c
282
return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;
drivers/gpu/drm/i915/display/intel_pps.c
285
static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)
drivers/gpu/drm/i915/display/intel_pps.c
287
return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;
drivers/gpu/drm/i915/display/intel_pps.c
290
static bool pps_any(struct intel_display *display, int pps_idx)
drivers/gpu/drm/i915/display/intel_pps.c
296
vlv_initial_pps_pipe(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_pps.c
302
u32 port_sel = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_pps.c
303
PP_ON_DELAYS(display, pipe)) &
drivers/gpu/drm/i915/display/intel_pps.c
309
if (!check(display, pipe))
drivers/gpu/drm/i915/display/intel_pps.c
321
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
325
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
329
intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
drivers/gpu/drm/i915/display/intel_pps.c
333
intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
drivers/gpu/drm/i915/display/intel_pps.c
337
intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
drivers/gpu/drm/i915/display/intel_pps.c
342
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
348
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
35
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
354
static int intel_num_pps(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pps.c
356
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pps.c
359
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_pps.c
362
if (INTEL_PCH_TYPE(display) >= PCH_MTL)
drivers/gpu/drm/i915/display/intel_pps.c
365
if (INTEL_PCH_TYPE(display) >= PCH_DG1)
drivers/gpu/drm/i915/display/intel_pps.c
368
if (INTEL_PCH_TYPE(display) >= PCH_ICP)
drivers/gpu/drm/i915/display/intel_pps.c
376
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
379
INTEL_PCH_TYPE(display) >= PCH_ICP &&
drivers/gpu/drm/i915/display/intel_pps.c
38
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_pps.c
380
INTEL_PCH_TYPE(display) <= PCH_ADP)
drivers/gpu/drm/i915/display/intel_pps.c
381
return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
drivers/gpu/drm/i915/display/intel_pps.c
387
bxt_initial_pps_idx(struct intel_display *display, pps_check check)
drivers/gpu/drm/i915/display/intel_pps.c
389
int pps_idx, pps_num = intel_num_pps(display);
drivers/gpu/drm/i915/display/intel_pps.c
392
if (check(display, pps_idx))
drivers/gpu/drm/i915/display/intel_pps.c
402
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
406
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
408
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_pps.c
414
if (intel_num_pps(display) > 1)
drivers/gpu/drm/i915/display/intel_pps.c
419
if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))
drivers/gpu/drm/i915/display/intel_pps.c
424
intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);
drivers/gpu/drm/i915/display/intel_pps.c
427
intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);
drivers/gpu/drm/i915/display/intel_pps.c
430
intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);
drivers/gpu/drm/i915/display/intel_pps.c
432
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
437
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
446
void vlv_pps_reset_all(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pps.c
450
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_pps.c
463
for_each_intel_dp(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_pps.c
466
drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
drivers/gpu/drm/i915/display/intel_pps.c
473
void bxt_pps_reset_all(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_pps.c
477
if (!HAS_DISPLAY(display))
drivers/gpu/drm/i915/display/intel_pps.c
482
for_each_intel_dp(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_pps.c
501
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
506
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_pps.c
508
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/intel_pps.c
513
regs->pp_ctrl = PP_CONTROL(display, pps_idx);
drivers/gpu/drm/i915/display/intel_pps.c
514
regs->pp_stat = PP_STATUS(display, pps_idx);
drivers/gpu/drm/i915/display/intel_pps.c
515
regs->pp_on = PP_ON_DELAYS(display, pps_idx);
drivers/gpu/drm/i915/display/intel_pps.c
516
regs->pp_off = PP_OFF_DELAYS(display, pps_idx);
drivers/gpu/drm/i915/display/intel_pps.c
519
if (display->platform.geminilake || display->platform.broxton ||
drivers/gpu/drm/i915/display/intel_pps.c
520
INTEL_PCH_TYPE(display) >= PCH_CNP)
drivers/gpu/drm/i915/display/intel_pps.c
523
regs->pp_div = PP_DIVISOR(display, pps_idx);
drivers/gpu/drm/i915/display/intel_pps.c
548
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
550
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
552
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_pps.c
556
return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
drivers/gpu/drm/i915/display/intel_pps.c
561
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
563
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
565
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_pps.c
569
return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
drivers/gpu/drm/i915/display/intel_pps.c
574
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
581
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_pps.c
585
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
589
intel_de_read(display, _pp_stat_reg(intel_dp)),
drivers/gpu/drm/i915/display/intel_pps.c
590
intel_de_read(display, _pp_ctrl_reg(intel_dp)));
drivers/gpu/drm/i915/display/intel_pps.c
608
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
614
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
621
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
626
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
627
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
629
ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
633
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
637
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
638
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
642
drm_dbg_kms(display->drm, "Wait complete\n");
drivers/gpu/drm/i915/display/intel_pps.c
647
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
650
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
659
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
662
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
671
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
683
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
71
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
723
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
726
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
728
control = intel_de_read(display, _pp_ctrl_reg(intel_dp));
drivers/gpu/drm/i915/display/intel_pps.c
729
if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&
drivers/gpu/drm/i915/display/intel_pps.c
744
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
753
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
761
drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
drivers/gpu/drm/i915/display/intel_pps.c
762
intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_pps.c
768
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
drivers/gpu/drm/i915/display/intel_pps.c
77
wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
drivers/gpu/drm/i915/display/intel_pps.c
778
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
779
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
78
mutex_lock(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
780
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
784
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
785
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
790
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
809
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
818
INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
drivers/gpu/drm/i915/display/intel_pps.c
826
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
831
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
833
drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);
drivers/gpu/drm/i915/display/intel_pps.c
838
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
drivers/gpu/drm/i915/display/intel_pps.c
848
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
849
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
85
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
852
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_pps.c
856
intel_de_read(display, pp_stat_reg),
drivers/gpu/drm/i915/display/intel_pps.c
857
intel_de_read(display, pp_ctrl_reg));
drivers/gpu/drm/i915/display/intel_pps.c
864
intel_display_power_put(display,
drivers/gpu/drm/i915/display/intel_pps.c
87
mutex_unlock(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
88
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
drivers/gpu/drm/i915/display/intel_pps.c
897
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
913
queue_delayed_work(display->wq.unordered,
drivers/gpu/drm/i915/display/intel_pps.c
924
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
929
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
931
INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
drivers/gpu/drm/i915/display/intel_pps.c
956
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
96
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_pps.c
960
lockdep_assert_held(&display->pps.mutex);
drivers/gpu/drm/i915/display/intel_pps.c
965
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
drivers/gpu/drm/i915/display/intel_pps.c
970
if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),
drivers/gpu/drm/i915/display/intel_pps.c
981
if (display->platform.ironlake) {
drivers/gpu/drm/i915/display/intel_pps.c
984
intel_de_write(display, pp_ctrl_reg, pp);
drivers/gpu/drm/i915/display/intel_pps.c
985
intel_de_posting_read(display, pp_ctrl_reg);
drivers/gpu/drm/i915/display/intel_pps.c
992
if (IS_DISPLAY_VER(display, 13, 14))
drivers/gpu/drm/i915/display/intel_pps.c
993
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/intel_pps.c
997
if (!display->platform.ironlake)
drivers/gpu/drm/i915/display/intel_pps.h
57
void vlv_pps_reset_all(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pps.h
58
void bxt_pps_reset_all(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pps.h
60
void intel_pps_unlock_regs_wa(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pps.h
61
void intel_pps_setup(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_pps.h
65
void assert_pps_unlocked(struct intel_display *display, enum pipe pipe);
drivers/gpu/drm/i915/display/intel_pps_regs.h
16
#define _MMIO_PPS(display, pps_idx, reg) \
drivers/gpu/drm/i915/display/intel_pps_regs.h
17
_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)
drivers/gpu/drm/i915/display/intel_pps_regs.h
20
#define PP_STATUS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_STATUS)
drivers/gpu/drm/i915/display/intel_pps_regs.h
47
#define PP_CONTROL(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_CONTROL)
drivers/gpu/drm/i915/display/intel_pps_regs.h
57
#define PP_ON_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_ON_DELAYS)
drivers/gpu/drm/i915/display/intel_pps_regs.h
68
#define PP_OFF_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_OFF_DELAYS)
drivers/gpu/drm/i915/display/intel_pps_regs.h
73
#define PP_DIVISOR(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_DIVISOR)
drivers/gpu/drm/i915/display/intel_psr.c
1000
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1004
if (display->params.psr_safest_params)
drivers/gpu/drm/i915/display/intel_psr.c
1064
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1077
intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
1086
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
1087
PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
1090
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set);
drivers/gpu/drm/i915/display/intel_psr.c
1095
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1102
if ((DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_psr.c
1103
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
drivers/gpu/drm/i915/display/intel_psr.c
1110
if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_psr.c
1113
if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13)
drivers/gpu/drm/i915/display/intel_psr.c
1120
if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) {
drivers/gpu/drm/i915/display/intel_psr.c
1128
if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) {
drivers/gpu/drm/i915/display/intel_psr.c
1151
} else if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_psr.c
1153
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_psr.c
1156
} else if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_psr.c
1164
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_psr.c
1170
tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
1171
PSR2_MAN_TRK_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
1172
drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
drivers/gpu/drm/i915/display/intel_psr.c
1173
} else if (HAS_PSR2_SEL_FETCH(display)) {
drivers/gpu/drm/i915/display/intel_psr.c
1174
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_psr.c
1175
PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_psr.c
1185
intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val);
drivers/gpu/drm/i915/display/intel_psr.c
1187
intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_psr.c
1191
transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder)
drivers/gpu/drm/i915/display/intel_psr.c
1193
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_psr.c
1195
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_psr.c
1197
else if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_psr.c
1215
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1218
intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
1225
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1228
intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
drivers/gpu/drm/i915/display/intel_psr.c
1233
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1235
intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
drivers/gpu/drm/i915/display/intel_psr.c
1268
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1273
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_psr.c
1283
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1285
struct i915_power_domains *power_domains = &display->power.domains;
drivers/gpu/drm/i915/display/intel_psr.c
1309
if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918))
drivers/gpu/drm/i915/display/intel_psr.c
1319
if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))
drivers/gpu/drm/i915/display/intel_psr.c
1328
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1330
if (!display->params.enable_psr2_sel_fetch &&
drivers/gpu/drm/i915/display/intel_psr.c
1332
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1344
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1377
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_psr.c
1424
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1438
if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
drivers/gpu/drm/i915/display/intel_psr.c
1450
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1456
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1464
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_psr.c
1467
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1471
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1486
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
1492
if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
drivers/gpu/drm/i915/display/intel_psr.c
1496
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/intel_psr.c
1517
if (DISPLAY_VER(display) < 30 &&
drivers/gpu/drm/i915/display/intel_psr.c
1521
if (DISPLAY_VER(display) >= 30 &&
drivers/gpu/drm/i915/display/intel_psr.c
1548
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1560
wake_lines = DISPLAY_VER(display) < 20 ?
drivers/gpu/drm/i915/display/intel_psr.c
1583
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1586
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1593
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1605
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1611
if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
drivers/gpu/drm/i915/display/intel_psr.c
1615
if (display->platform.jasperlake || display->platform.elkhartlake) {
drivers/gpu/drm/i915/display/intel_psr.c
1616
drm_dbg_kms(display->drm, "PSR2 not supported by phy\n");
drivers/gpu/drm/i915/display/intel_psr.c
1621
if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) {
drivers/gpu/drm/i915/display/intel_psr.c
1622
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1627
if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
drivers/gpu/drm/i915/display/intel_psr.c
1628
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1633
if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {
drivers/gpu/drm/i915/display/intel_psr.c
1634
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1646
(DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) {
drivers/gpu/drm/i915/display/intel_psr.c
1647
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1652
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_psr.c
1656
} else if (IS_DISPLAY_VER(display, 12, 14)) {
drivers/gpu/drm/i915/display/intel_psr.c
1660
} else if (IS_DISPLAY_VER(display, 10, 11)) {
drivers/gpu/drm/i915/display/intel_psr.c
1664
} else if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/intel_psr.c
1671
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1679
display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
drivers/gpu/drm/i915/display/intel_psr.c
1680
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1690
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1707
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1709
if (HAS_PSR2_SEL_FETCH(display) &&
drivers/gpu/drm/i915/display/intel_psr.c
1711
!HAS_PSR_HW_TRACKING(display)) {
drivers/gpu/drm/i915/display/intel_psr.c
1712
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1718
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1728
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1734
if (DISPLAY_VER(display) < 14)
drivers/gpu/drm/i915/display/intel_psr.c
1743
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1750
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1756
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1775
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1779
if (!CAN_PSR(intel_dp) || !display->params.enable_psr)
drivers/gpu/drm/i915/display/intel_psr.c
1794
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1820
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1830
drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
drivers/gpu/drm/i915/display/intel_psr.c
1835
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1843
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1862
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1873
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1887
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1889
return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
drivers/gpu/drm/i915/display/intel_psr.c
1897
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1903
if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647))
drivers/gpu/drm/i915/display/intel_psr.c
1911
for_each_intel_crtc(display, crtc)
drivers/gpu/drm/i915/display/intel_psr.c
1924
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
1929
drm_dbg_kms(display->drm, "PSR disabled by flag\n");
drivers/gpu/drm/i915/display/intel_psr.c
1934
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1940
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1951
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
1972
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_psr.c
2005
if (HAS_PSR2_SEL_FETCH(display)) {
drivers/gpu/drm/i915/display/intel_psr.c
2006
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2007
PSR2_MAN_TRK_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
2014
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/intel_psr.c
2015
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2016
TRANS_EXITLINE(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
2025
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2028
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
2029
transcoder_has_psr2(display, cpu_transcoder) &&
drivers/gpu/drm/i915/display/intel_psr.c
2030
intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);
drivers/gpu/drm/i915/display/intel_psr.c
2032
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
2033
intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);
drivers/gpu/drm/i915/display/intel_psr.c
2035
drm_WARN_ON(display->drm, intel_dp->psr.active);
drivers/gpu/drm/i915/display/intel_psr.c
2037
drm_WARN_ON(display->drm, !intel_dp->psr.enabled);
drivers/gpu/drm/i915/display/intel_psr.c
2060
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2065
if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)
drivers/gpu/drm/i915/display/intel_psr.c
2069
if (DISPLAY_VER(display) == 12 &&
drivers/gpu/drm/i915/display/intel_psr.c
2075
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
drivers/gpu/drm/i915/display/intel_psr.c
2078
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
drivers/gpu/drm/i915/display/intel_psr.c
2085
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2093
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/intel_psr.c
2110
if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))
drivers/gpu/drm/i915/display/intel_psr.c
2124
if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult)
drivers/gpu/drm/i915/display/intel_psr.c
2127
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/intel_psr.c
2134
if (IS_DISPLAY_VER(display, 9, 10))
drivers/gpu/drm/i915/display/intel_psr.c
2138
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_psr.c
2142
intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask);
drivers/gpu/drm/i915/display/intel_psr.c
2151
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
2152
TRANS_EXITLINE(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2156
if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))
drivers/gpu/drm/i915/display/intel_psr.c
2157
intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
drivers/gpu/drm/i915/display/intel_psr.c
2168
if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/intel_psr.c
2169
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0,
drivers/gpu/drm/i915/display/intel_psr.c
2179
(IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
drivers/gpu/drm/i915/display/intel_psr.c
2180
display->platform.alderlake_p))
drivers/gpu/drm/i915/display/intel_psr.c
2181
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2186
IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))
drivers/gpu/drm/i915/display/intel_psr.c
2187
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
2188
MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2191
else if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_psr.c
2192
intel_de_rmw(display, CLKGATE_DIS_MISC, 0,
drivers/gpu/drm/i915/display/intel_psr.c
2197
if ((DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_psr.c
2198
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
drivers/gpu/drm/i915/display/intel_psr.c
2200
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
drivers/gpu/drm/i915/display/intel_psr.c
2204
if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display))
drivers/gpu/drm/i915/display/intel_psr.c
2210
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2225
val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
2229
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
2241
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2245
drm_WARN_ON(display->drm, intel_dp->psr.enabled);
drivers/gpu/drm/i915/display/intel_psr.c
2271
drm_dbg_kms(display->drm, "Enabling Panel Replay\n");
drivers/gpu/drm/i915/display/intel_psr.c
2273
drm_dbg_kms(display->drm, "Enabling PSR%s\n",
drivers/gpu/drm/i915/display/intel_psr.c
2312
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2317
if (transcoder_has_psr2(display, cpu_transcoder)) {
drivers/gpu/drm/i915/display/intel_psr.c
2318
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2319
EDP_PSR2_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
2320
drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE);
drivers/gpu/drm/i915/display/intel_psr.c
2323
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
2324
psr_ctl_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
2325
drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE);
drivers/gpu/drm/i915/display/intel_psr.c
2331
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2336
val = intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
2337
EDP_PSR2_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2340
drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));
drivers/gpu/drm/i915/display/intel_psr.c
2342
if ((DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_psr.c
2343
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
drivers/gpu/drm/i915/display/intel_psr.c
2345
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
drivers/gpu/drm/i915/display/intel_psr.c
2349
val = intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
2350
psr_ctl_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2353
drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE));
drivers/gpu/drm/i915/display/intel_psr.c
2360
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2367
psr_status = EDP_PSR2_STATUS(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
2370
psr_status = psr_status_reg(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
2375
if (intel_de_wait_for_clear_ms(display, psr_status,
drivers/gpu/drm/i915/display/intel_psr.c
2377
drm_err(display->drm, "Timed out waiting PSR idle state\n");
drivers/gpu/drm/i915/display/intel_psr.c
2382
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2391
drm_dbg_kms(display->drm, "Disabling Panel Replay\n");
drivers/gpu/drm/i915/display/intel_psr.c
2393
drm_dbg_kms(display->drm, "Disabling PSR%s\n",
drivers/gpu/drm/i915/display/intel_psr.c
2403
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_psr.c
2404
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
drivers/gpu/drm/i915/display/intel_psr.c
2410
IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))
drivers/gpu/drm/i915/display/intel_psr.c
2411
intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
2412
MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2414
else if (display->platform.alderlake_p)
drivers/gpu/drm/i915/display/intel_psr.c
2415
intel_de_rmw(display, CLKGATE_DIS_MISC,
drivers/gpu/drm/i915/display/intel_psr.c
2435
if ((DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_psr.c
2436
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
drivers/gpu/drm/i915/display/intel_psr.c
2438
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);
drivers/gpu/drm/i915/display/intel_psr.c
2460
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2465
if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) &&
drivers/gpu/drm/i915/display/intel_psr.c
2519
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2531
drm_warn(display->drm, "Unbalanced PSR pause/resume!\n");
drivers/gpu/drm/i915/display/intel_psr.c
2556
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
2573
if ((DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_psr.c
2574
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
drivers/gpu/drm/i915/display/intel_psr.c
2596
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_psr.c
2601
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_psr.c
2602
CURSURFLIVE(display, crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_psr.c
2619
static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
2621
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 :
drivers/gpu/drm/i915/display/intel_psr.c
2625
static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
2627
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
drivers/gpu/drm/i915/display/intel_psr.c
2632
static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
2634
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
drivers/gpu/drm/i915/display/intel_psr.c
2639
static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
2641
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
drivers/gpu/drm/i915/display/intel_psr.c
2648
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2663
intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);
drivers/gpu/drm/i915/display/intel_psr.c
2669
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
2677
for_each_intel_encoder_mask_with_psr(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_psr.c
2684
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
drivers/gpu/drm/i915/display/intel_psr.c
2689
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_psr.c
269
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2690
PSR2_MAN_TRK_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
2696
intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
drivers/gpu/drm/i915/display/intel_psr.c
2709
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
2710
u32 val = man_trk_ctl_enable_bit_get(display);
drivers/gpu/drm/i915/display/intel_psr.c
2713
val |= man_trk_ctl_partial_frame_bit_get(display);
drivers/gpu/drm/i915/display/intel_psr.c
2716
val |= man_trk_ctl_continuos_full_frame(display);
drivers/gpu/drm/i915/display/intel_psr.c
272
display->params.enable_panel_replay;
drivers/gpu/drm/i915/display/intel_psr.c
2723
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_psr.c
277
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2776
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
2783
(display->platform.alderlake_p || DISPLAY_VER(display) >= 14))
drivers/gpu/drm/i915/display/intel_psr.c
279
return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR :
drivers/gpu/drm/i915/display/intel_psr.c
285
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
287
return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT :
drivers/gpu/drm/i915/display/intel_psr.c
2881
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
2897
for_each_intel_encoder_mask_with_psr(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_psr.c
2913
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
2917
((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
drivers/gpu/drm/i915/display/intel_psr.c
2918
display->platform.alderlake_p || display->platform.tigerlake)) &&
drivers/gpu/drm/i915/display/intel_psr.c
2922
if (intel_display_wa(display, INTEL_DISPLAY_WA_16029024088) &&
drivers/gpu/drm/i915/display/intel_psr.c
2928
if (DISPLAY_VER(display) == 30)
drivers/gpu/drm/i915/display/intel_psr.c
293
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
2935
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_psr.c
295
return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY :
drivers/gpu/drm/i915/display/intel_psr.c
301
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
303
return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK :
drivers/gpu/drm/i915/display/intel_psr.c
3037
drm_info_once(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
307
static intel_reg_t psr_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
310
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
311
return EDP_PSR_CTL(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3150
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
3153
u32 val = man_trk_ctl_enable_bit_get(display);
drivers/gpu/drm/i915/display/intel_psr.c
3156
val |= man_trk_ctl_partial_frame_bit_get(display);
drivers/gpu/drm/i915/display/intel_psr.c
3157
val |= man_trk_ctl_continuos_full_frame(display);
drivers/gpu/drm/i915/display/intel_psr.c
316
static intel_reg_t psr_debug_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3160
intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val);
drivers/gpu/drm/i915/display/intel_psr.c
3165
intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0);
drivers/gpu/drm/i915/display/intel_psr.c
3171
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_psr.c
3178
if (!HAS_PSR(display))
drivers/gpu/drm/i915/display/intel_psr.c
319
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
320
return EDP_PSR_DEBUG(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3208
(DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled))
drivers/gpu/drm/i915/display/intel_psr.c
3222
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
3227
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3236
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_psr.c
325
static intel_reg_t psr_perf_cnt_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3254
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3266
if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) {
drivers/gpu/drm/i915/display/intel_psr.c
328
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
329
return EDP_PSR_PERF_CNT(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3303
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
3312
intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
3318
return intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_psr.c
3319
EDP_PSR2_STATUS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
3328
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
3332
intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
3338
return intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_psr.c
3339
psr_status_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
334
static intel_reg_t psr_status_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3353
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
3359
for_each_intel_encoder_mask_with_psr(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_psr.c
337
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
3377
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
338
return EDP_PSR_STATUS(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3396
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3407
reg = EDP_PSR2_STATUS(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3410
reg = psr_status_reg(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3416
err = intel_de_wait_for_clear_ms(display, reg, mask, 50);
drivers/gpu/drm/i915/display/intel_psr.c
3418
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3426
static int intel_psr_fastset_force(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
343
static intel_reg_t psr_imr_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3434
state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_psr.c
3444
drm_connector_list_iter_begin(display->drm, &conn_iter);
drivers/gpu/drm/i915/display/intel_psr.c
346
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_psr.c
347
return TRANS_PSR_IMR(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3491
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3502
drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val);
drivers/gpu/drm/i915/display/intel_psr.c
352
static intel_reg_t psr_iir_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3527
ret = intel_psr_fastset_force(display);
drivers/gpu/drm/i915/display/intel_psr.c
355
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_psr.c
356
return TRANS_PSR_IIR(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3584
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3590
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_psr.c
3591
intel_de_write(display, LNL_SFF_CTL(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
3594
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_psr.c
3595
PSR2_MAN_TRK_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
3596
man_trk_ctl_enable_bit_get(display) |
drivers/gpu/drm/i915/display/intel_psr.c
3597
man_trk_ctl_partial_frame_bit_get(display) |
drivers/gpu/drm/i915/display/intel_psr.c
3598
man_trk_ctl_single_full_frame_bit_get(display) |
drivers/gpu/drm/i915/display/intel_psr.c
3599
man_trk_ctl_continuos_full_frame(display));
drivers/gpu/drm/i915/display/intel_psr.c
3604
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3606
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
drivers/gpu/drm/i915/display/intel_psr.c
361
static intel_reg_t psr_aux_ctl_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3631
void intel_psr_invalidate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3639
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
364
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
365
return EDP_PSR_AUX_CTL(display, cpu_transcoder);
drivers/gpu/drm/i915/display/intel_psr.c
3669
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3684
mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
drivers/gpu/drm/i915/display/intel_psr.c
3690
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3692
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_psr.c
370
static intel_reg_t psr_aux_data_reg(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3727
queue_work(display->wq.unordered, &intel_dp->psr.work);
drivers/gpu/drm/i915/display/intel_psr.c
373
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
374
return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);
drivers/gpu/drm/i915/display/intel_psr.c
3743
void intel_psr_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
3748
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
3797
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3801
if (!(HAS_PSR(display) || HAS_DP20(display)))
drivers/gpu/drm/i915/display/intel_psr.c
381
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3813
if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) {
drivers/gpu/drm/i915/display/intel_psr.c
3814
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3819
if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||
drivers/gpu/drm/i915/display/intel_psr.c
3820
DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_psr.c
3823
if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))
drivers/gpu/drm/i915/display/intel_psr.c
3827
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/intel_psr.c
3877
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3884
drm_err(display->drm, "Error reading DP_PSR_ESI\n");
drivers/gpu/drm/i915/display/intel_psr.c
3891
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3908
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
3926
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
393
intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
3939
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3942
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3945
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3948
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
3952
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
397
static void psr_event_print(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
400
drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val);
drivers/gpu/drm/i915/display/intel_psr.c
4018
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
402
drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n");
drivers/gpu/drm/i915/display/intel_psr.c
4024
for_each_intel_encoder_mask_with_psr(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_psr.c
404
drm_dbg_kms(display->drm, "\tPSR2 disabled\n");
drivers/gpu/drm/i915/display/intel_psr.c
4041
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
4047
for_each_intel_encoder_mask_with_psr(display->drm, encoder,
drivers/gpu/drm/i915/display/intel_psr.c
4059
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
406
drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n");
drivers/gpu/drm/i915/display/intel_psr.c
4071
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
drivers/gpu/drm/i915/display/intel_psr.c
4078
struct intel_display *display = container_of(work, typeof(*display),
drivers/gpu/drm/i915/display/intel_psr.c
408
drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n");
drivers/gpu/drm/i915/display/intel_psr.c
4082
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
410
drm_dbg_kms(display->drm, "\tGraphics reset\n");
drivers/gpu/drm/i915/display/intel_psr.c
4102
void intel_psr_notify_dc5_dc6(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
4104
if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647))
drivers/gpu/drm/i915/display/intel_psr.c
4107
schedule_work(&display->psr_dc5_dc6_wa_work);
drivers/gpu/drm/i915/display/intel_psr.c
4117
void intel_psr_dc5_dc6_wa_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
4119
if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647))
drivers/gpu/drm/i915/display/intel_psr.c
412
drm_dbg_kms(display->drm, "\tPCH interrupt\n");
drivers/gpu/drm/i915/display/intel_psr.c
4122
INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work);
drivers/gpu/drm/i915/display/intel_psr.c
4137
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_psr.c
414
drm_dbg_kms(display->drm, "\tMemory up\n");
drivers/gpu/drm/i915/display/intel_psr.c
4140
if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647))
drivers/gpu/drm/i915/display/intel_psr.c
4143
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
416
drm_dbg_kms(display->drm, "\tFront buffer modification\n");
drivers/gpu/drm/i915/display/intel_psr.c
418
drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n");
drivers/gpu/drm/i915/display/intel_psr.c
4185
void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.c
4190
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
4197
intel_display_power_get(display,
drivers/gpu/drm/i915/display/intel_psr.c
420
drm_dbg_kms(display->drm, "\tPIPE registers updated\n");
drivers/gpu/drm/i915/display/intel_psr.c
4200
intel_display_power_put(display, POWER_DOMAIN_DC_OFF,
drivers/gpu/drm/i915/display/intel_psr.c
4215
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
422
drm_dbg_kms(display->drm, "\tRegister updated\n");
drivers/gpu/drm/i915/display/intel_psr.c
4220
if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) &&
drivers/gpu/drm/i915/display/intel_psr.c
4235
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4236
EDP_PSR2_STATUS(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
424
drm_dbg_kms(display->drm, "\tHDCP enabled\n");
drivers/gpu/drm/i915/display/intel_psr.c
4251
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4252
psr_status_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
426
drm_dbg_kms(display->drm, "\tKVMR session enabled\n");
drivers/gpu/drm/i915/display/intel_psr.c
428
drm_dbg_kms(display->drm, "\tVBI enabled\n");
drivers/gpu/drm/i915/display/intel_psr.c
430
drm_dbg_kms(display->drm, "\tLPSP mode exited\n");
drivers/gpu/drm/i915/display/intel_psr.c
4317
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
432
drm_dbg_kms(display->drm, "\tPSR disabled\n");
drivers/gpu/drm/i915/display/intel_psr.c
4329
wakeref = intel_display_rpm_get(display);
drivers/gpu/drm/i915/display/intel_psr.c
4342
val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
4345
psr2_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4346
EDP_PSR2_CTL(display,
drivers/gpu/drm/i915/display/intel_psr.c
4351
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4352
EDP_PSR2_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
4355
val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
437
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
4370
val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_psr.c
4388
if (DISPLAY_VER(display) < 13) {
drivers/gpu/drm/i915/display/intel_psr.c
4394
val = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_psr.c
4395
PSR2_SU_STATUS(display, cpu_transcoder, frame));
drivers/gpu/drm/i915/display/intel_psr.c
4417
intel_display_rpm_put(display, wakeref);
drivers/gpu/drm/i915/display/intel_psr.c
4424
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_psr.c
4428
if (!HAS_PSR(display))
drivers/gpu/drm/i915/display/intel_psr.c
443
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
4432
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
4447
struct intel_display *display = data;
drivers/gpu/drm/i915/display/intel_psr.c
4451
if (!HAS_PSR(display))
drivers/gpu/drm/i915/display/intel_psr.c
4454
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
4457
drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val);
drivers/gpu/drm/i915/display/intel_psr.c
4460
with_intel_display_rpm(display)
drivers/gpu/drm/i915/display/intel_psr.c
4470
struct intel_display *display = data;
drivers/gpu/drm/i915/display/intel_psr.c
4473
if (!HAS_PSR(display))
drivers/gpu/drm/i915/display/intel_psr.c
4476
for_each_intel_encoder_with_psr(display->drm, encoder) {
drivers/gpu/drm/i915/display/intel_psr.c
4491
void intel_psr_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_psr.c
4493
struct dentry *debugfs_root = display->drm->debugfs_root;
drivers/gpu/drm/i915/display/intel_psr.c
4496
display, &i915_edp_psr_debug_fops);
drivers/gpu/drm/i915/display/intel_psr.c
4499
display, &i915_edp_psr_status_fops);
drivers/gpu/drm/i915/display/intel_psr.c
450
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
454
if (DISPLAY_VER(display) >= 9) {
drivers/gpu/drm/i915/display/intel_psr.c
457
val = intel_de_rmw(display,
drivers/gpu/drm/i915/display/intel_psr.c
458
PSR_EVENT(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
4580
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_psr.c
4590
if (HAS_PSR(display) || HAS_DP20(display))
drivers/gpu/drm/i915/display/intel_psr.c
461
psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
drivers/gpu/drm/i915/display/intel_psr.c
4614
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
4621
wake_lines = DISPLAY_VER(display) < 20 ?
drivers/gpu/drm/i915/display/intel_psr.c
4635
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
4658
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
466
drm_warn(display->drm, "[transcoder %s] PSR aux error\n",
drivers/gpu/drm/i915/display/intel_psr.c
4667
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
4677
wake_lines = DISPLAY_VER(display) < 20 ?
drivers/gpu/drm/i915/display/intel_psr.c
4694
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_psr.c
4696
return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
drivers/gpu/drm/i915/display/intel_psr.c
479
intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
482
queue_work(display->wq.unordered, &intel_dp->psr.work);
drivers/gpu/drm/i915/display/intel_psr.c
488
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
495
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
503
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
521
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
532
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
608
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
617
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
634
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
641
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
659
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
668
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
679
drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
drivers/gpu/drm/i915/display/intel_psr.c
683
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
689
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_psr.c
699
if (intel_has_quirk(display, QUIRK_DISABLE_PSR2))
drivers/gpu/drm/i915/display/intel_psr.c
702
if (DISPLAY_VER(display) >= 9 &&
drivers/gpu/drm/i915/display/intel_psr.c
720
drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
drivers/gpu/drm/i915/display/intel_psr.c
743
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
758
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_psr.c
759
psr_aux_data_reg(display, cpu_transcoder, i >> 2),
drivers/gpu/drm/i915/display/intel_psr.c
774
intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
781
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
783
if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||
drivers/gpu/drm/i915/display/intel_psr.c
825
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
834
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
879
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
883
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/intel_psr.c
886
if (display->params.psr_safest_params) {
drivers/gpu/drm/i915/display/intel_psr.c
914
if (DISPLAY_VER(display) < 9 &&
drivers/gpu/drm/i915/display/intel_psr.c
920
if (intel_dp_source_supports_tps3(display) &&
drivers/gpu/drm/i915/display/intel_psr.c
931
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
941
if (drm_WARN_ON(display->drm, idle_frames > 0xf))
drivers/gpu/drm/i915/display/intel_psr.c
949
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
950
u32 current_dc_state = intel_display_power_get_current_dc_state(display);
drivers/gpu/drm/i915/display/intel_psr.c
951
struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);
drivers/gpu/drm/i915/display/intel_psr.c
962
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_psr.c
969
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/intel_psr.c
972
if (display->platform.haswell)
drivers/gpu/drm/i915/display/intel_psr.c
980
if (DISPLAY_VER(display) >= 8)
drivers/gpu/drm/i915/display/intel_psr.c
983
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_psr.c
986
intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_psr.c
990
if ((DISPLAY_VER(display) == 20 ||
drivers/gpu/drm/i915/display/intel_psr.c
991
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
drivers/gpu/drm/i915/display/intel_psr.c
993
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
drivers/gpu/drm/i915/display/intel_psr.h
40
void intel_psr_invalidate(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.h
43
void intel_psr_flush(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.h
68
void intel_psr_notify_dc5_dc6(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_psr.h
69
void intel_psr_dc5_dc6_wa_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_psr.h
70
void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_psr.h
81
void intel_psr_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_quirks.c
100
drm_info(display->drm, "PSR2 support not currently available for this setup, applying disable PSR2 quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
107
void (*hook)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_quirks.c
129
void (*hook)(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_quirks.c
14
static void intel_set_quirk(struct intel_display *display, enum intel_quirk_id quirk)
drivers/gpu/drm/i915/display/intel_quirks.c
16
display->quirks.mask |= BIT(quirk);
drivers/gpu/drm/i915/display/intel_quirks.c
27
static void quirk_ssc_force_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
29
intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE);
drivers/gpu/drm/i915/display/intel_quirks.c
291
void intel_init_quirks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
293
struct pci_dev *d = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_quirks.c
30
drm_info(display->drm, "applying lvds SSC disable quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
305
q->hook(display);
drivers/gpu/drm/i915/display/intel_quirks.c
309
intel_dmi_quirks[i].hook(display);
drivers/gpu/drm/i915/display/intel_quirks.c
316
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_quirks.c
317
struct pci_dev *d = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_quirks.c
337
bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk)
drivers/gpu/drm/i915/display/intel_quirks.c
339
return display->quirks.mask & BIT(quirk);
drivers/gpu/drm/i915/display/intel_quirks.c
37
static void quirk_invert_brightness(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
39
intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS);
drivers/gpu/drm/i915/display/intel_quirks.c
40
drm_info(display->drm, "applying inverted panel brightness quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
44
static void quirk_backlight_present(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
46
intel_set_quirk(display, QUIRK_BACKLIGHT_PRESENT);
drivers/gpu/drm/i915/display/intel_quirks.c
47
drm_info(display->drm, "applying backlight present quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
53
static void quirk_increase_t12_delay(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
55
intel_set_quirk(display, QUIRK_INCREASE_T12_DELAY);
drivers/gpu/drm/i915/display/intel_quirks.c
56
drm_info(display->drm, "Applying T12 delay quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
63
static void quirk_increase_ddi_disabled_time(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
65
intel_set_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME);
drivers/gpu/drm/i915/display/intel_quirks.c
66
drm_info(display->drm, "Applying Increase DDI Disabled quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
69
static void quirk_no_pps_backlight_power_hook(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
71
intel_set_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK);
drivers/gpu/drm/i915/display/intel_quirks.c
72
drm_info(display->drm, "Applying no pps backlight power quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
77
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_quirks.c
80
drm_info(display->drm, "Applying Fast Wake sync pulse count quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
83
static void quirk_edp_limit_rate_hbr2(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
85
intel_set_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2);
drivers/gpu/drm/i915/display/intel_quirks.c
86
drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
91
struct intel_display *display = to_intel_display(intel_dp);
drivers/gpu/drm/i915/display/intel_quirks.c
94
drm_info(display->drm, "Applying disable Panel Replay quirk\n");
drivers/gpu/drm/i915/display/intel_quirks.c
97
static void quirk_disable_psr2(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_quirks.c
99
intel_set_quirk(display, QUIRK_DISABLE_PSR2);
drivers/gpu/drm/i915/display/intel_quirks.h
28
void intel_init_quirks(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_quirks.h
31
bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk);
drivers/gpu/drm/i915/display/intel_rom.c
21
struct intel_display *display;
drivers/gpu/drm/i915/display/intel_rom.c
34
intel_de_write(rom->display, PRIMARY_SPI_ADDRESS,
drivers/gpu/drm/i915/display/intel_rom.c
37
return intel_de_read(rom->display, PRIMARY_SPI_TRIGGER);
drivers/gpu/drm/i915/display/intel_rom.c
54
rom->display = to_intel_display(drm);
drivers/gpu/drm/i915/display/intel_rom.c
56
static_region = intel_de_read(rom->display, SPI_STATIC_REGIONS);
drivers/gpu/drm/i915/display/intel_rom.c
58
intel_de_write(rom->display, PRIMARY_SPI_REGIONID, static_region);
drivers/gpu/drm/i915/display/intel_rom.c
60
rom->offset = intel_de_read(rom->display, OROM_OFFSET) & OROM_OFFSET_MASK;
drivers/gpu/drm/i915/display/intel_sbi.c
16
static int intel_sbi_rw(struct intel_display *display, u16 reg,
drivers/gpu/drm/i915/display/intel_sbi.c
22
lockdep_assert_held(&display->sbi.lock);
drivers/gpu/drm/i915/display/intel_sbi.c
24
if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
drivers/gpu/drm/i915/display/intel_sbi.c
26
drm_err(display->drm, "timeout waiting for SBI to become ready\n");
drivers/gpu/drm/i915/display/intel_sbi.c
30
intel_de_write_fw(display, SBI_ADDR, SBI_ADDR_VALUE(reg));
drivers/gpu/drm/i915/display/intel_sbi.c
31
intel_de_write_fw(display, SBI_DATA, is_read ? 0 : *val);
drivers/gpu/drm/i915/display/intel_sbi.c
39
intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);
drivers/gpu/drm/i915/display/intel_sbi.c
41
if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
drivers/gpu/drm/i915/display/intel_sbi.c
43
drm_err(display->drm, "timeout waiting for SBI to complete read\n");
drivers/gpu/drm/i915/display/intel_sbi.c
48
drm_err(display->drm, "error during SBI read of reg %x\n", reg);
drivers/gpu/drm/i915/display/intel_sbi.c
53
*val = intel_de_read_fw(display, SBI_DATA);
drivers/gpu/drm/i915/display/intel_sbi.c
58
void intel_sbi_lock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_sbi.c
60
mutex_lock(&display->sbi.lock);
drivers/gpu/drm/i915/display/intel_sbi.c
63
void intel_sbi_unlock(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_sbi.c
65
mutex_unlock(&display->sbi.lock);
drivers/gpu/drm/i915/display/intel_sbi.c
68
u32 intel_sbi_read(struct intel_display *display, u16 reg,
drivers/gpu/drm/i915/display/intel_sbi.c
73
intel_sbi_rw(display, reg, destination, &result, true);
drivers/gpu/drm/i915/display/intel_sbi.c
78
void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,
drivers/gpu/drm/i915/display/intel_sbi.c
81
intel_sbi_rw(display, reg, destination, &value, false);
drivers/gpu/drm/i915/display/intel_sbi.c
84
void intel_sbi_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_sbi.c
86
mutex_init(&display->sbi.lock);
drivers/gpu/drm/i915/display/intel_sbi.c
89
void intel_sbi_fini(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_sbi.c
91
mutex_destroy(&display->sbi.lock);
drivers/gpu/drm/i915/display/intel_sbi.h
18
void intel_sbi_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_sbi.h
19
void intel_sbi_fini(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_sbi.h
20
void intel_sbi_lock(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_sbi.h
21
void intel_sbi_unlock(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_sbi.h
22
u32 intel_sbi_read(struct intel_display *display, u16 reg,
drivers/gpu/drm/i915/display/intel_sbi.h
24
void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,
drivers/gpu/drm/i915/display/intel_sdvo.c
1011
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1024
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1051
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1081
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1102
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1128
if (drm_WARN_ON(display->drm, ret))
drivers/gpu/drm/i915/display/intel_sdvo.c
1137
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1146
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1151
if (drm_WARN_ON(display->drm, len < 0))
drivers/gpu/drm/i915/display/intel_sdvo.c
1162
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1174
drm_dbg_kms(display->drm, "failed to read AVI infoframe\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
1185
drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
1190
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1198
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1214
drm_dbg_kms(display->drm, "failed to read ELD\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
1284
struct intel_display *display = to_intel_display(pipe_config);
drivers/gpu/drm/i915/display/intel_sdvo.c
1305
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1361
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_sdvo.c
1368
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_sdvo.c
1374
drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
1454
drm_dbg_kms(display->drm, "bad AVI infoframe\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
1528
struct intel_display *display = to_intel_display(intel_encoder);
drivers/gpu/drm/i915/display/intel_sdvo.c
1573
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1603
drm_info(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1609
drm_WARN(display->drm, 1,
drivers/gpu/drm/i915/display/intel_sdvo.c
1620
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_sdvo.c
1624
if (DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_sdvo.c
1627
sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1635
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
1640
if (DISPLAY_VER(display) >= 4) {
drivers/gpu/drm/i915/display/intel_sdvo.c
1642
} else if (display->platform.i945g || display->platform.i945gm ||
drivers/gpu/drm/i915/display/intel_sdvo.c
1643
display->platform.g33 || display->platform.pineview) {
drivers/gpu/drm/i915/display/intel_sdvo.c
1651
DISPLAY_VER(display) < 5)
drivers/gpu/drm/i915/display/intel_sdvo.c
1668
bool intel_sdvo_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sdvo.c
1673
val = intel_de_read(display, sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1676
if (HAS_PCH_CPT(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
1678
else if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_sdvo.c
1689
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_sdvo.c
1696
ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe);
drivers/gpu/drm/i915/display/intel_sdvo.c
1704
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_sdvo.c
1715
sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1723
drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
1746
if (display->platform.i915g || display->platform.i915gm) {
drivers/gpu/drm/i915/display/intel_sdvo.c
1775
drm_WARN(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1840
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_sdvo.c
1850
temp = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1860
if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {
drivers/gpu/drm/i915/display/intel_sdvo.c
1865
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/intel_sdvo.c
1866
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
drivers/gpu/drm/i915/display/intel_sdvo.c
1875
intel_wait_for_vblank_if_active(display, PIPE_A);
drivers/gpu/drm/i915/display/intel_sdvo.c
1876
intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/intel_sdvo.c
1877
intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
drivers/gpu/drm/i915/display/intel_sdvo.c
1901
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_sdvo.c
1911
temp = intel_de_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
1926
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
1941
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
1946
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_sdvo.c
1950
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_sdvo.c
1986
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
1994
drm_dbg_kms(display->drm, "SDVO capabilities:\n"
drivers/gpu/drm/i915/display/intel_sdvo.c
2036
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2039
if (!HAS_HOTPLUG(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
2046
if (display->platform.i945g || display->platform.i945gm)
drivers/gpu/drm/i915/display/intel_sdvo.c
2090
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
2093
ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);
drivers/gpu/drm/i915/display/intel_sdvo.c
2144
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
2150
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
2153
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
2156
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
216
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2168
drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
220
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_sdvo.c
2204
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
221
intel_de_write(display, intel_sdvo->sdvo_reg, val);
drivers/gpu/drm/i915/display/intel_sdvo.c
2211
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
222
intel_de_posting_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
227
if (HAS_PCH_IBX(display)) {
drivers/gpu/drm/i915/display/intel_sdvo.c
228
intel_de_write(display, intel_sdvo->sdvo_reg, val);
drivers/gpu/drm/i915/display/intel_sdvo.c
229
intel_de_posting_read(display, intel_sdvo->sdvo_reg);
drivers/gpu/drm/i915/display/intel_sdvo.c
2305
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
2315
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
2318
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
235
cval = intel_de_read(display, GEN3_SDVOC);
drivers/gpu/drm/i915/display/intel_sdvo.c
2357
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
2359
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
237
bval = intel_de_read(display, GEN3_SDVOB);
drivers/gpu/drm/i915/display/intel_sdvo.c
245
intel_de_write(display, GEN3_SDVOB, bval);
drivers/gpu/drm/i915/display/intel_sdvo.c
246
intel_de_posting_read(display, GEN3_SDVOB);
drivers/gpu/drm/i915/display/intel_sdvo.c
248
intel_de_write(display, GEN3_SDVOC, cval);
drivers/gpu/drm/i915/display/intel_sdvo.c
249
intel_de_posting_read(display, GEN3_SDVOC);
drivers/gpu/drm/i915/display/intel_sdvo.c
255
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2623
struct intel_display *display = to_intel_display(&sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2628
mapping = &display->vbt.sdvo_mappings[0];
drivers/gpu/drm/i915/display/intel_sdvo.c
2630
mapping = &display->vbt.sdvo_mappings[1];
drivers/gpu/drm/i915/display/intel_sdvo.c
2646
struct intel_display *display = to_intel_display(&sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2651
mapping = &display->vbt.sdvo_mappings[0];
drivers/gpu/drm/i915/display/intel_sdvo.c
2653
mapping = &display->vbt.sdvo_mappings[1];
drivers/gpu/drm/i915/display/intel_sdvo.c
2656
intel_gmbus_is_valid_pin(display, mapping->i2c_pin))
drivers/gpu/drm/i915/display/intel_sdvo.c
2661
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
2665
sdvo->i2c = intel_gmbus_get_adapter(display, pin);
drivers/gpu/drm/i915/display/intel_sdvo.c
2691
struct intel_display *display = to_intel_display(&sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2695
my_mapping = &display->vbt.sdvo_mappings[0];
drivers/gpu/drm/i915/display/intel_sdvo.c
2696
other_mapping = &display->vbt.sdvo_mappings[1];
drivers/gpu/drm/i915/display/intel_sdvo.c
2698
my_mapping = &display->vbt.sdvo_mappings[1];
drivers/gpu/drm/i915/display/intel_sdvo.c
2699
other_mapping = &display->vbt.sdvo_mappings[0];
drivers/gpu/drm/i915/display/intel_sdvo.c
2735
struct intel_display *display = to_intel_display(&encoder->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
275
drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret);
drivers/gpu/drm/i915/display/intel_sdvo.c
2760
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
2803
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2810
drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type);
drivers/gpu/drm/i915/display/intel_sdvo.c
2856
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2862
drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type);
drivers/gpu/drm/i915/display/intel_sdvo.c
2896
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2902
drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type);
drivers/gpu/drm/i915/display/intel_sdvo.c
2928
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
2934
drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type);
drivers/gpu/drm/i915/display/intel_sdvo.c
2955
intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL);
drivers/gpu/drm/i915/display/intel_sdvo.c
2964
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_sdvo.c
2969
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_sdvo.c
3018
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3037
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
3060
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3064
&display->drm->mode_config.connector_list, head) {
drivers/gpu/drm/i915/display/intel_sdvo.c
3076
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3101
drm_property_create(display->drm, DRM_MODE_PROP_ENUM,
drivers/gpu/drm/i915/display/intel_sdvo.c
3123
drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \
drivers/gpu/drm/i915/display/intel_sdvo.c
3128
drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \
drivers/gpu/drm/i915/display/intel_sdvo.c
3140
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3163
drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]);
drivers/gpu/drm/i915/display/intel_sdvo.c
3171
drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]);
drivers/gpu/drm/i915/display/intel_sdvo.c
3177
drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
3196
drm_property_create_range(display->drm, 0,
drivers/gpu/drm/i915/display/intel_sdvo.c
3205
drm_property_create_range(display->drm, 0,
drivers/gpu/drm/i915/display/intel_sdvo.c
3212
drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
3235
drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1);
drivers/gpu/drm/i915/display/intel_sdvo.c
3241
drm_dbg_kms(display->drm, "dot crawl: current %d\n", response);
drivers/gpu/drm/i915/display/intel_sdvo.c
3252
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3266
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3278
drm_dbg_kms(display->drm, "No enhancement is supported\n");
drivers/gpu/drm/i915/display/intel_sdvo.c
3353
struct intel_display *display = to_intel_display(&sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
3354
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_sdvo.c
3370
static bool is_sdvo_port_valid(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_sdvo.c
3372
if (HAS_PCH_SPLIT(display))
drivers/gpu/drm/i915/display/intel_sdvo.c
3378
static bool assert_sdvo_port_valid(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_sdvo.c
3380
return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port),
drivers/gpu/drm/i915/display/intel_sdvo.c
3384
bool intel_sdvo_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sdvo.c
3391
if (!assert_port_valid(display, port))
drivers/gpu/drm/i915/display/intel_sdvo.c
3394
if (!assert_sdvo_port_valid(display, port))
drivers/gpu/drm/i915/display/intel_sdvo.c
3407
drm_encoder_init(display->drm, &intel_encoder->base,
drivers/gpu/drm/i915/display/intel_sdvo.c
3421
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
3429
if (HAS_PCH_SPLIT(display)) {
drivers/gpu/drm/i915/display/intel_sdvo.c
3459
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sdvo.c
3496
drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, "
drivers/gpu/drm/i915/display/intel_sdvo.c
417
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
438
drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);
drivers/gpu/drm/i915/display/intel_sdvo.c
441
drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),
drivers/gpu/drm/i915/display/intel_sdvo.c
467
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
517
drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret);
drivers/gpu/drm/i915/display/intel_sdvo.c
523
drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3);
drivers/gpu/drm/i915/display/intel_sdvo.c
542
struct intel_display *display = to_intel_display(&intel_sdvo->base);
drivers/gpu/drm/i915/display/intel_sdvo.c
607
drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);
drivers/gpu/drm/i915/display/intel_sdvo.c
610
drm_dbg_kms(display->drm, "%s: R: %s\n",
drivers/gpu/drm/i915/display/intel_sdvo.c
615
drm_dbg_kms(display->drm, "%s: R: ... failed %s\n",
drivers/gpu/drm/i915/display/intel_sdvo.h
18
bool intel_sdvo_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sdvo.h
20
bool intel_sdvo_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sdvo.h
23
static inline bool intel_sdvo_port_enabled(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sdvo.h
28
static inline bool intel_sdvo_init(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_snps_phy.c
1822
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1832
intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1833
intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1834
intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1835
intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1836
intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1837
intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1838
intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1849
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1858
intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy),
drivers/gpu/drm/i915/display/intel_snps_phy.c
1866
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
drivers/gpu/drm/i915/display/intel_snps_phy.c
1867
drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1880
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1894
intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1900
intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1906
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
drivers/gpu/drm/i915/display/intel_snps_phy.c
1907
drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1952
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1955
pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1956
pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1957
pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1958
pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1959
pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1960
pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1961
pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));
drivers/gpu/drm/i915/display/intel_snps_phy.c
1969
pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &
drivers/gpu/drm/i915/display/intel_snps_phy.c
1984
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_snps_phy.c
1991
if (!display->platform.dg2)
drivers/gpu/drm/i915/display/intel_snps_phy.c
2006
INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \
drivers/gpu/drm/i915/display/intel_snps_phy.c
32
void intel_snps_phy_wait_for_calibration(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_snps_phy.c
37
if (!intel_phy_is_snps(display, phy))
drivers/gpu/drm/i915/display/intel_snps_phy.c
45
if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),
drivers/gpu/drm/i915/display/intel_snps_phy.c
47
display->snps.phy_failed_calibration |= BIT(phy);
drivers/gpu/drm/i915/display/intel_snps_phy.c
54
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_snps_phy.c
63
intel_de_rmw(display, SNPS_PHY_TX_REQ(phy),
drivers/gpu/drm/i915/display/intel_snps_phy.c
70
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_snps_phy.c
76
if (drm_WARN_ON_ONCE(display->drm, !trans))
drivers/gpu/drm/i915/display/intel_snps_phy.c
87
intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val);
drivers/gpu/drm/i915/display/intel_snps_phy.h
19
void intel_snps_phy_wait_for_calibration(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_sprite.c
1011
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
1019
if (display->platform.sandybridge)
drivers/gpu/drm/i915/display/intel_sprite.c
104
intel_de_write_fw(display, SPCSCYGOFF(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
106
intel_de_write_fw(display, SPCSCCBOFF(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
108
intel_de_write_fw(display, SPCSCCROFF(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1080
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
1096
intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),
drivers/gpu/drm/i915/display/intel_sprite.c
111
intel_de_write_fw(display, SPCSCC01(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1110
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
1125
intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),
drivers/gpu/drm/i915/display/intel_sprite.c
1128
intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
1129
intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
113
intel_de_write_fw(display, SPCSCC23(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1130
intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
1140
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
115
intel_de_write_fw(display, SPCSCC45(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1155
intel_de_write_fw(display, DVSSTRIDE(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
1157
intel_de_write_fw(display, DVSPOS(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
1159
intel_de_write_fw(display, DVSSIZE(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
1161
intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);
drivers/gpu/drm/i915/display/intel_sprite.c
117
intel_de_write_fw(display, SPCSCC67(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1170
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
1180
intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);
drivers/gpu/drm/i915/display/intel_sprite.c
1181
intel_de_write_fw(display, DVSKEYMSK(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
1183
intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);
drivers/gpu/drm/i915/display/intel_sprite.c
1186
intel_de_write_fw(display, DVSLINOFF(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
1188
intel_de_write_fw(display, DVSTILEOFF(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
119
intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
drivers/gpu/drm/i915/display/intel_sprite.c
1196
intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);
drivers/gpu/drm/i915/display/intel_sprite.c
1197
intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);
drivers/gpu/drm/i915/display/intel_sprite.c
1199
if (display->platform.g4x)
drivers/gpu/drm/i915/display/intel_sprite.c
121
intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1210
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
1213
intel_de_write_fw(display, DVSCNTR(pipe), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
1215
intel_de_write_fw(display, DVSSCALE(pipe), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
1216
intel_de_write_fw(display, DVSSURF(pipe), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
1223
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
1225
error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
1226
error->surf = intel_de_read(display, DVSSURF(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
1227
error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
123
intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1234
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
1240
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_sprite.c
1244
ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;
drivers/gpu/drm/i915/display/intel_sprite.c
1248
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_sprite.c
125
intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1274
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
128
intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
130
intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1300
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sprite.c
1313
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sprite.c
132
intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
1320
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sprite.c
1327
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sprite.c
1340
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
1346
if (DISPLAY_VER(display) < 7) {
drivers/gpu/drm/i915/display/intel_sprite.c
1349
} else if (display->platform.ivybridge) {
drivers/gpu/drm/i915/display/intel_sprite.c
1375
if (DISPLAY_VER(display) >= 7)
drivers/gpu/drm/i915/display/intel_sprite.c
1385
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
1389
if (display->platform.cherryview &&
drivers/gpu/drm/i915/display/intel_sprite.c
1392
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_sprite.c
142
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
1594
intel_sprite_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sprite.c
1609
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/intel_sprite.c
1622
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/intel_sprite.c
1625
if (display->platform.cherryview && pipe == PIPE_B) {
drivers/gpu/drm/i915/display/intel_sprite.c
1634
} else if (DISPLAY_VER(display) >= 7) {
drivers/gpu/drm/i915/display/intel_sprite.c
1643
if (display->platform.broadwell || display->platform.haswell) {
drivers/gpu/drm/i915/display/intel_sprite.c
1653
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/intel_sprite.c
1672
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/intel_sprite.c
1675
if (display->platform.sandybridge) {
drivers/gpu/drm/i915/display/intel_sprite.c
1688
if (display->platform.cherryview && pipe == PIPE_B) {
drivers/gpu/drm/i915/display/intel_sprite.c
1701
modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X);
drivers/gpu/drm/i915/display/intel_sprite.c
1703
ret = drm_universal_plane_init(display->drm, &plane->base,
drivers/gpu/drm/i915/display/intel_sprite.c
1707
"sprite %c", sprite_name(display, pipe, sprite));
drivers/gpu/drm/i915/display/intel_sprite.c
172
intel_de_write_fw(display, SPCLRC0(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
174
intel_de_write_fw(display, SPCLRC1(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
344
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
361
intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),
drivers/gpu/drm/i915/display/intel_sprite.c
371
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
379
intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
381
intel_de_write_fw(display, SPPOS(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
383
intel_de_write_fw(display, SPSIZE(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
393
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
403
if (display->platform.cherryview && pipe == PIPE_B)
drivers/gpu/drm/i915/display/intel_sprite.c
407
intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
409
intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
411
intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
415
intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
417
intel_de_write_fw(display, SPLINOFF(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
419
intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),
drivers/gpu/drm/i915/display/intel_sprite.c
427
intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);
drivers/gpu/drm/i915/display/intel_sprite.c
428
intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);
drivers/gpu/drm/i915/display/intel_sprite.c
439
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
443
intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
444
intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
451
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
453
error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/intel_sprite.c
454
error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/intel_sprite.c
455
error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/intel_sprite.c
462
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
469
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_sprite.c
473
ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
drivers/gpu/drm/i915/display/intel_sprite.c
477
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_sprite.c
52
static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)
drivers/gpu/drm/i915/display/intel_sprite.c
54
return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';
drivers/gpu/drm/i915/display/intel_sprite.c
655
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
659
(display->platform.ivybridge || display->platform.haswell);
drivers/gpu/drm/i915/display/intel_sprite.c
664
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
672
if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_sprite.c
70
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
761
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite.c
774
intel_de_write_fw(display, SPRGAMC(pipe, i),
drivers/gpu/drm/i915/display/intel_sprite.c
777
intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
778
intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
779
intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
782
intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
783
intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
784
intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);
drivers/gpu/drm/i915/display/intel_sprite.c
794
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
809
intel_de_write_fw(display, SPRSTRIDE(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
811
intel_de_write_fw(display, SPRPOS(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
813
intel_de_write_fw(display, SPRSIZE(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
815
if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_sprite.c
816
intel_de_write_fw(display, SPRSCALE(pipe), sprscale);
drivers/gpu/drm/i915/display/intel_sprite.c
825
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
835
intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);
drivers/gpu/drm/i915/display/intel_sprite.c
836
intel_de_write_fw(display, SPRKEYMSK(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
838
intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);
drivers/gpu/drm/i915/display/intel_sprite.c
843
if (display->platform.haswell || display->platform.broadwell) {
drivers/gpu/drm/i915/display/intel_sprite.c
844
intel_de_write_fw(display, SPROFFSET(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
847
intel_de_write_fw(display, SPRLINOFF(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
849
intel_de_write_fw(display, SPRTILEOFF(pipe),
drivers/gpu/drm/i915/display/intel_sprite.c
858
intel_de_write_fw(display, SPRCTL(pipe), sprctl);
drivers/gpu/drm/i915/display/intel_sprite.c
859
intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);
drivers/gpu/drm/i915/display/intel_sprite.c
869
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
872
intel_de_write_fw(display, SPRCTL(pipe), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
874
if (display->platform.ivybridge)
drivers/gpu/drm/i915/display/intel_sprite.c
875
intel_de_write_fw(display, SPRSCALE(pipe), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
876
intel_de_write_fw(display, SPRSURF(pipe), 0);
drivers/gpu/drm/i915/display/intel_sprite.c
883
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
885
error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
886
error->surf = intel_de_read(display, SPRSURF(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
887
error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));
drivers/gpu/drm/i915/display/intel_sprite.c
894
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
900
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_sprite.c
904
ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
drivers/gpu/drm/i915/display/intel_sprite.c
908
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_sprite.c
988
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/intel_sprite.c
990
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/intel_sprite.h
17
struct intel_plane *intel_sprite_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sprite.h
29
static inline struct intel_plane *intel_sprite_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
101
if (!ret && has_dst_key_in_primary_plane(display)) {
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
103
intel_crtc_for_pipe(display,
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
11
static bool has_dst_key_in_primary_plane(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
13
return DISPLAY_VER(display) >= 9;
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
19
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
37
if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_PRIMARY &&
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
45
struct intel_display *display = to_intel_display(dev);
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
63
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_sprite_uapi.c
76
if (DISPLAY_VER(display) >= 9 &&
drivers/gpu/drm/i915/display/intel_tc.c
1007
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1010
u32 pica_isr_bits = display->hotplug.hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
1011
u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
1016
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) {
drivers/gpu/drm/i915/display/intel_tc.c
1017
pica_isr = intel_de_read(display, PICAINTERRUPT_ISR);
drivers/gpu/drm/i915/display/intel_tc.c
1018
pch_isr = intel_de_read(display, SDEISR);
drivers/gpu/drm/i915/display/intel_tc.c
1035
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1037
intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_tc.c
1041
return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;
drivers/gpu/drm/i915/display/intel_tc.c
1047
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1055
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1069
static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)
drivers/gpu/drm/i915/display/intel_tc.c
1072
if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,
drivers/gpu/drm/i915/display/intel_tc.c
1074
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1079
intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable ? 1 : 0);
drivers/gpu/drm/i915/display/intel_tc.c
1080
intel_de_write(display, TCSS_DISP_MAILBOX_IN_CMD,
drivers/gpu/drm/i915/display/intel_tc.c
1085
if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,
drivers/gpu/drm/i915/display/intel_tc.c
1087
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1095
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1097
intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_tc.c
1102
if (DISPLAY_VER(display) == 30)
drivers/gpu/drm/i915/display/intel_tc.c
1103
xelpdp_tc_power_request_wa(display, enable);
drivers/gpu/drm/i915/display/intel_tc.c
1105
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_tc.c
1110
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_tc.c
1115
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1128
if (drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY))
drivers/gpu/drm/i915/display/intel_tc.c
1142
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1144
intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_tc.c
1149
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_tc.c
1154
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/intel_tc.c
1159
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1161
intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
drivers/gpu/drm/i915/display/intel_tc.c
1165
return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;
drivers/gpu/drm/i915/display/intel_tc.c
1170
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1189
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1267
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1273
drm_WARN_ON_ONCE(display->drm, hweight32(mask) > 1);
drivers/gpu/drm/i915/display/intel_tc.c
1297
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1299
if (DISPLAY_VER(display) < 20) {
drivers/gpu/drm/i915/display/intel_tc.c
1300
drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);
drivers/gpu/drm/i915/display/intel_tc.c
1311
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1321
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1334
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1342
drm_err(display->drm, "Port %s: timeout waiting for PHY ready\n",
drivers/gpu/drm/i915/display/intel_tc.c
1412
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1432
drm_WARN_ON(display->drm, live_mode == TC_PORT_TBT_ALT);
drivers/gpu/drm/i915/display/intel_tc.c
1436
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1476
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1490
drm_WARN_ON(display->drm, !connected);
drivers/gpu/drm/i915/display/intel_tc.c
1511
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1515
intel_display_power_flush_work(display);
drivers/gpu/drm/i915/display/intel_tc.c
1520
if (intel_display_power_is_enabled(display, aux_domain))
drivers/gpu/drm/i915/display/intel_tc.c
1521
drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n",
drivers/gpu/drm/i915/display/intel_tc.c
1529
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1563
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1568
return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &
drivers/gpu/drm/i915/display/intel_tc.c
1581
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1587
drm_WARN_ON(display->drm, tc->mode != TC_PORT_DISCONNECTED);
drivers/gpu/drm/i915/display/intel_tc.c
1588
drm_WARN_ON(display->drm, tc->lock_wakeref);
drivers/gpu/drm/i915/display/intel_tc.c
1589
drm_WARN_ON(display->drm, tc->link_refcount);
drivers/gpu/drm/i915/display/intel_tc.c
1612
drm_WARN_ON(display->drm, !tc->legacy_port);
drivers/gpu/drm/i915/display/intel_tc.c
1613
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1631
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1645
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1667
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1672
drm_WARN_ON(display->drm, tc->link_refcount != 1);
drivers/gpu/drm/i915/display/intel_tc.c
1682
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1690
drm_dbg_kms(display->drm, "Port %s: sanitize mode (%s) pin assignment: %c max lanes: %d\n",
drivers/gpu/drm/i915/display/intel_tc.c
1724
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tc.c
1729
drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));
drivers/gpu/drm/i915/display/intel_tc.c
1764
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
177
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1771
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, ctx);
drivers/gpu/drm/i915/display/intel_tc.c
1782
for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) {
drivers/gpu/drm/i915/display/intel_tc.c
1800
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1806
_state = drm_atomic_commit_alloc(display->drm);
drivers/gpu/drm/i915/display/intel_tc.c
181
intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
drivers/gpu/drm/i915/display/intel_tc.c
1825
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1831
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_tc.c
1833
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
1837
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/intel_tc.c
1839
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/intel_tc.c
1867
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
187
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1877
drm_WARN_ON(display->drm, tc->mode == TC_PORT_DISCONNECTED);
drivers/gpu/drm/i915/display/intel_tc.c
1878
drm_WARN_ON(display->drm, tc->mode != TC_PORT_TBT_ALT && !tc_phy_is_owned(tc));
drivers/gpu/drm/i915/display/intel_tc.c
191
return intel_display_power_get(display, *domain);
drivers/gpu/drm/i915/display/intel_tc.c
1971
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
1976
if (drm_WARN_ON(display->drm, tc_port == TC_PORT_NONE))
drivers/gpu/drm/i915/display/intel_tc.c
1986
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_tc.c
1988
else if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_tc.c
1990
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_tc.c
211
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
213
intel_display_power_put(display, domain, wakeref);
drivers/gpu/drm/i915/display/intel_tc.c
219
struct intel_display __maybe_unused *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
223
drm_WARN_ON(display->drm, tc->lock_power_domain != domain);
drivers/gpu/drm/i915/display/intel_tc.c
231
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
233
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
234
!intel_display_power_is_enabled(display, POWER_DOMAIN_DISPLAY_CORE));
drivers/gpu/drm/i915/display/intel_tc.c
240
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
243
enabled = intel_display_power_is_enabled(display,
drivers/gpu/drm/i915/display/intel_tc.c
245
drm_WARN_ON(display->drm, !enabled);
drivers/gpu/drm/i915/display/intel_tc.c
262
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
264
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
265
!intel_display_power_is_enabled(display, tc_port_power_domain(tc)));
drivers/gpu/drm/i915/display/intel_tc.c
270
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
273
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE)
drivers/gpu/drm/i915/display/intel_tc.c
274
lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
276
drm_WARN_ON(display->drm, lane_mask == 0xffffffff);
drivers/gpu/drm/i915/display/intel_tc.c
294
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
304
if (DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/intel_tc.c
312
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE)
drivers/gpu/drm/i915/display/intel_tc.c
313
val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/intel_tc.c
315
drm_WARN_ON(display->drm, val == 0xffffffff);
drivers/gpu/drm/i915/display/intel_tc.c
324
drm_WARN_ON(display->drm, DISPLAY_VER(display) > 11);
drivers/gpu/drm/i915/display/intel_tc.c
383
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
388
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_tc.c
424
struct intel_display *display = to_intel_display(dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
429
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_tc.c
432
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
437
val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
458
intel_de_write(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia), val);
drivers/gpu/drm/i915/display/intel_tc.c
464
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
467
drm_WARN_ON(display->drm, tc->mode != TC_PORT_DISCONNECTED);
drivers/gpu/drm/i915/display/intel_tc.c
482
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
513
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
517
return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
drivers/gpu/drm/i915/display/intel_tc.c
524
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
526
u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
531
with_intel_display_power(display, tc_phy_cold_off_domain(tc)) {
drivers/gpu/drm/i915/display/intel_tc.c
532
fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
533
pch_isr = intel_de_read(display, SDEISR);
drivers/gpu/drm/i915/display/intel_tc.c
537
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
564
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
569
val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
571
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
583
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
588
val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
590
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
601
intel_de_write(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia), val);
drivers/gpu/drm/i915/display/intel_tc.c
608
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
613
val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
drivers/gpu/drm/i915/display/intel_tc.c
615
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
655
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
661
drm_WARN_ON(display->drm, max_lanes != 4);
drivers/gpu/drm/i915/display/intel_tc.c
665
drm_WARN_ON(display->drm, tc->mode != TC_PORT_DP_ALT);
drivers/gpu/drm/i915/display/intel_tc.c
672
drm_dbg_kms(display->drm, "Port %s: PHY sudden disconnect\n",
drivers/gpu/drm/i915/display/intel_tc.c
678
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
691
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
703
!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {
drivers/gpu/drm/i915/display/intel_tc.c
704
drm_dbg_kms(display->drm, "Port %s: can't take PHY ownership (ready %s)\n",
drivers/gpu/drm/i915/display/intel_tc.c
772
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
775
with_intel_display_power(display, tc_phy_cold_off_domain(tc))
drivers/gpu/drm/i915/display/intel_tc.c
776
val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));
drivers/gpu/drm/i915/display/intel_tc.c
778
drm_WARN_ON(display->drm, val == 0xffffffff);
drivers/gpu/drm/i915/display/intel_tc.c
801
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
805
return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
drivers/gpu/drm/i915/display/intel_tc.c
812
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
815
u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
816
u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
821
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) {
drivers/gpu/drm/i915/display/intel_tc.c
822
cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR);
drivers/gpu/drm/i915/display/intel_tc.c
823
pch_isr = intel_de_read(display, SDEISR);
drivers/gpu/drm/i915/display/intel_tc.c
846
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
852
val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));
drivers/gpu/drm/i915/display/intel_tc.c
854
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tc.c
866
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
871
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,
drivers/gpu/drm/i915/display/intel_tc.c
879
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
885
val = intel_de_read(display, DDI_BUF_CTL(port));
drivers/gpu/drm/i915/display/intel_tc.c
891
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
896
port_wakeref = intel_display_power_get(display, port_power_domain);
drivers/gpu/drm/i915/display/intel_tc.c
905
intel_display_power_put(display, port_power_domain, port_wakeref);
drivers/gpu/drm/i915/display/intel_tc.c
910
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
923
port_wakeref = intel_display_power_get(display, port_power_domain);
drivers/gpu/drm/i915/display/intel_tc.c
926
!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {
drivers/gpu/drm/i915/display/intel_tc.c
927
drm_dbg_kms(display->drm, "Port %s: can't take PHY ownership\n",
drivers/gpu/drm/i915/display/intel_tc.c
933
!drm_WARN_ON(display->drm, tc->mode == TC_PORT_LEGACY)) {
drivers/gpu/drm/i915/display/intel_tc.c
934
drm_dbg_kms(display->drm, "Port %s: PHY not ready\n",
drivers/gpu/drm/i915/display/intel_tc.c
946
intel_display_power_put(display, port_power_domain, port_wakeref);
drivers/gpu/drm/i915/display/intel_tc.c
955
intel_display_power_put(display, port_power_domain, port_wakeref);
drivers/gpu/drm/i915/display/intel_tc.c
962
struct intel_display *display = to_intel_display(tc->dig_port);
drivers/gpu/drm/i915/display/intel_tc.c
967
port_wakeref = intel_display_power_get(display, port_power_domain);
drivers/gpu/drm/i915/display/intel_tc.c
982
intel_display_power_put(display, port_power_domain, port_wakeref);
drivers/gpu/drm/i915/display/intel_tdf.h
20
static inline void intel_td_flush(struct intel_display *display) {}
drivers/gpu/drm/i915/display/intel_tdf.h
22
void intel_td_flush(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_tv.c
1094
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tv.c
1106
tv_ctl = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1107
hctl1 = intel_de_read(display, TV_H_CTL_1);
drivers/gpu/drm/i915/display/intel_tv.c
1108
hctl3 = intel_de_read(display, TV_H_CTL_3);
drivers/gpu/drm/i915/display/intel_tv.c
1109
vctl1 = intel_de_read(display, TV_V_CTL_1);
drivers/gpu/drm/i915/display/intel_tv.c
1110
vctl2 = intel_de_read(display, TV_V_CTL_2);
drivers/gpu/drm/i915/display/intel_tv.c
1145
tmp = intel_de_read(display, TV_WIN_POS);
drivers/gpu/drm/i915/display/intel_tv.c
1149
tmp = intel_de_read(display, TV_WIN_SIZE);
drivers/gpu/drm/i915/display/intel_tv.c
1155
drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
drivers/gpu/drm/i915/display/intel_tv.c
1168
if (display->platform.i965gm)
drivers/gpu/drm/i915/display/intel_tv.c
1173
static bool intel_tv_source_too_wide(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_tv.c
1176
return DISPLAY_VER(display) == 3 && hdisplay > 1024;
drivers/gpu/drm/i915/display/intel_tv.c
1194
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tv.c
1216
drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n");
drivers/gpu/drm/i915/display/intel_tv.c
1230
if (intel_tv_source_too_wide(display, hdisplay) ||
drivers/gpu/drm/i915/display/intel_tv.c
1237
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tv.c
1271
drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
drivers/gpu/drm/i915/display/intel_tv.c
1349
if (display->platform.i965gm)
drivers/gpu/drm/i915/display/intel_tv.c
1357
set_tv_mode_timings(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_tv.c
1403
intel_de_write(display, TV_H_CTL_1, hctl1);
drivers/gpu/drm/i915/display/intel_tv.c
1404
intel_de_write(display, TV_H_CTL_2, hctl2);
drivers/gpu/drm/i915/display/intel_tv.c
1405
intel_de_write(display, TV_H_CTL_3, hctl3);
drivers/gpu/drm/i915/display/intel_tv.c
1406
intel_de_write(display, TV_V_CTL_1, vctl1);
drivers/gpu/drm/i915/display/intel_tv.c
1407
intel_de_write(display, TV_V_CTL_2, vctl2);
drivers/gpu/drm/i915/display/intel_tv.c
1408
intel_de_write(display, TV_V_CTL_3, vctl3);
drivers/gpu/drm/i915/display/intel_tv.c
1409
intel_de_write(display, TV_V_CTL_4, vctl4);
drivers/gpu/drm/i915/display/intel_tv.c
1410
intel_de_write(display, TV_V_CTL_5, vctl5);
drivers/gpu/drm/i915/display/intel_tv.c
1411
intel_de_write(display, TV_V_CTL_6, vctl6);
drivers/gpu/drm/i915/display/intel_tv.c
1412
intel_de_write(display, TV_V_CTL_7, vctl7);
drivers/gpu/drm/i915/display/intel_tv.c
1415
static void set_color_conversion(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_tv.c
1418
intel_de_write(display, TV_CSC_Y,
drivers/gpu/drm/i915/display/intel_tv.c
1420
intel_de_write(display, TV_CSC_Y2,
drivers/gpu/drm/i915/display/intel_tv.c
1422
intel_de_write(display, TV_CSC_U,
drivers/gpu/drm/i915/display/intel_tv.c
1424
intel_de_write(display, TV_CSC_U2,
drivers/gpu/drm/i915/display/intel_tv.c
1426
intel_de_write(display, TV_CSC_V,
drivers/gpu/drm/i915/display/intel_tv.c
1428
intel_de_write(display, TV_CSC_V2,
drivers/gpu/drm/i915/display/intel_tv.c
1437
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tv.c
1452
tv_ctl = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1524
if (display->platform.i915gm)
drivers/gpu/drm/i915/display/intel_tv.c
1527
set_tv_mode_timings(display, tv_mode, burst_ena);
drivers/gpu/drm/i915/display/intel_tv.c
1529
intel_de_write(display, TV_SC_CTL_1, scctl1);
drivers/gpu/drm/i915/display/intel_tv.c
1530
intel_de_write(display, TV_SC_CTL_2, scctl2);
drivers/gpu/drm/i915/display/intel_tv.c
1531
intel_de_write(display, TV_SC_CTL_3, scctl3);
drivers/gpu/drm/i915/display/intel_tv.c
1533
set_color_conversion(display, color_conversion);
drivers/gpu/drm/i915/display/intel_tv.c
1535
if (DISPLAY_VER(display) >= 4)
drivers/gpu/drm/i915/display/intel_tv.c
1536
intel_de_write(display, TV_CLR_KNOBS, 0x00404000);
drivers/gpu/drm/i915/display/intel_tv.c
1538
intel_de_write(display, TV_CLR_KNOBS, 0x00606000);
drivers/gpu/drm/i915/display/intel_tv.c
1541
intel_de_write(display, TV_CLR_LEVEL,
drivers/gpu/drm/i915/display/intel_tv.c
1544
assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
drivers/gpu/drm/i915/display/intel_tv.c
1550
intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl);
drivers/gpu/drm/i915/display/intel_tv.c
1561
intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos);
drivers/gpu/drm/i915/display/intel_tv.c
1562
intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize);
drivers/gpu/drm/i915/display/intel_tv.c
1566
intel_de_write(display, TV_H_LUMA(i),
drivers/gpu/drm/i915/display/intel_tv.c
1569
intel_de_write(display, TV_H_CHROMA(i),
drivers/gpu/drm/i915/display/intel_tv.c
1572
intel_de_write(display, TV_V_LUMA(i),
drivers/gpu/drm/i915/display/intel_tv.c
1575
intel_de_write(display, TV_V_CHROMA(i),
drivers/gpu/drm/i915/display/intel_tv.c
1577
intel_de_write(display, TV_DAC,
drivers/gpu/drm/i915/display/intel_tv.c
1578
intel_de_read(display, TV_DAC) & TV_DAC_SAVE);
drivers/gpu/drm/i915/display/intel_tv.c
1579
intel_de_write(display, TV_CTL, tv_ctl);
drivers/gpu/drm/i915/display/intel_tv.c
1586
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_tv.c
1594
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_tv.c
1595
i915_disable_pipestat(display, 0,
drivers/gpu/drm/i915/display/intel_tv.c
1598
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_tv.c
1601
save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1602
save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1624
if (display->platform.gm45)
drivers/gpu/drm/i915/display/intel_tv.c
1628
intel_de_write(display, TV_CTL, tv_ctl);
drivers/gpu/drm/i915/display/intel_tv.c
1629
intel_de_write(display, TV_DAC, tv_dac);
drivers/gpu/drm/i915/display/intel_tv.c
1630
intel_de_posting_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1635
tv_dac = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1636
drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
drivers/gpu/drm/i915/display/intel_tv.c
1644
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tv.c
1648
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tv.c
1652
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tv.c
1656
drm_dbg_kms(display->drm, "Unrecognised TV connection\n");
drivers/gpu/drm/i915/display/intel_tv.c
1660
intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
drivers/gpu/drm/i915/display/intel_tv.c
1661
intel_de_write(display, TV_CTL, save_tv_ctl);
drivers/gpu/drm/i915/display/intel_tv.c
1662
intel_de_posting_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
1669
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_tv.c
1670
i915_enable_pipestat(display, 0,
drivers/gpu/drm/i915/display/intel_tv.c
1673
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/intel_tv.c
1712
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_tv.c
1717
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
drivers/gpu/drm/i915/display/intel_tv.c
1720
if (!intel_display_device_enabled(display))
drivers/gpu/drm/i915/display/intel_tv.c
1723
if (!intel_display_driver_check_access(display))
drivers/gpu/drm/i915/display/intel_tv.c
1792
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_tv.c
1806
if (DISPLAY_VER(display) == 3 && input->w > 1024 &&
drivers/gpu/drm/i915/display/intel_tv.c
1823
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_tv.c
1889
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_tv.c
1905
if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1)
drivers/gpu/drm/i915/display/intel_tv.c
1910
drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names);
drivers/gpu/drm/i915/display/intel_tv.c
1913
display->drm->mode_config.legacy_tv_mode_property,
drivers/gpu/drm/i915/display/intel_tv.c
1916
display->drm->mode_config.tv_left_margin_property,
drivers/gpu/drm/i915/display/intel_tv.c
1919
display->drm->mode_config.tv_top_margin_property,
drivers/gpu/drm/i915/display/intel_tv.c
1922
display->drm->mode_config.tv_right_margin_property,
drivers/gpu/drm/i915/display/intel_tv.c
1925
display->drm->mode_config.tv_bottom_margin_property,
drivers/gpu/drm/i915/display/intel_tv.c
1930
intel_tv_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_tv.c
1938
if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
drivers/gpu/drm/i915/display/intel_tv.c
1941
if (!intel_bios_is_tv_present(display)) {
drivers/gpu/drm/i915/display/intel_tv.c
1942
drm_dbg_kms(display->drm, "Integrated TV is not present.\n");
drivers/gpu/drm/i915/display/intel_tv.c
1950
save_tv_dac = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1952
intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
drivers/gpu/drm/i915/display/intel_tv.c
1953
tv_dac_on = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1955
intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
drivers/gpu/drm/i915/display/intel_tv.c
1956
tv_dac_off = intel_de_read(display, TV_DAC);
drivers/gpu/drm/i915/display/intel_tv.c
1958
intel_de_write(display, TV_DAC, save_tv_dac);
drivers/gpu/drm/i915/display/intel_tv.c
1996
drm_connector_init(display->drm, connector, &intel_tv_connector_funcs,
drivers/gpu/drm/i915/display/intel_tv.c
1999
drm_encoder_init(display->drm, &intel_encoder->base,
drivers/gpu/drm/i915/display/intel_tv.c
918
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tv.c
919
u32 tmp = intel_de_read(display, TV_CTL);
drivers/gpu/drm/i915/display/intel_tv.c
932
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tv.c
937
intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE);
drivers/gpu/drm/i915/display/intel_tv.c
946
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/intel_tv.c
948
intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);
drivers/gpu/drm/i915/display/intel_tv.c
962
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/intel_tv.c
964
int max_dotclk = display->cdclk.max_dotclk_freq;
drivers/gpu/drm/i915/display/intel_tv.c
967
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/intel_tv.h
12
void intel_tv_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_tv.h
14
static inline void intel_tv_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vblank.c
112
frame = intel_de_read64_2x32_volatile(display, PIPEFRAMEPIXEL(display, pipe),
drivers/gpu/drm/i915/display/intel_vblank.c
113
PIPEFRAME(display, pipe));
drivers/gpu/drm/i915/display/intel_vblank.c
128
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_vblank.c
135
return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
drivers/gpu/drm/i915/display/intel_vblank.c
140
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vblank.c
159
scan_prev_time = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_vblank.c
166
scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
drivers/gpu/drm/i915/display/intel_vblank.c
168
scan_post_time = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_vblank.c
201
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vblank.c
229
if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)
drivers/gpu/drm/i915/display/intel_vblank.c
231
else if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_vblank.c
232
display->platform.broadwell || display->platform.haswell)
drivers/gpu/drm/i915/display/intel_vblank.c
234
else if (DISPLAY_VER(display) >= 3)
drivers/gpu/drm/i915/display/intel_vblank.c
246
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vblank.c
260
position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
drivers/gpu/drm/i915/display/intel_vblank.c
274
if (HAS_DDI(display) && !position) {
drivers/gpu/drm/i915/display/intel_vblank.c
279
temp = intel_de_read_fw(display,
drivers/gpu/drm/i915/display/intel_vblank.c
280
PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
drivers/gpu/drm/i915/display/intel_vblank.c
306
static void intel_vblank_section_enter(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vblank.c
309
struct intel_uncore *uncore = to_intel_uncore(display->drm);
drivers/gpu/drm/i915/display/intel_vblank.c
313
static void intel_vblank_section_exit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vblank.c
316
struct intel_uncore *uncore = to_intel_uncore(display->drm);
drivers/gpu/drm/i915/display/intel_vblank.c
320
static void intel_vblank_section_enter(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vblank.c
324
static void intel_vblank_section_exit(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vblank.c
335
struct intel_display *display = to_intel_display(_crtc->dev);
drivers/gpu/drm/i915/display/intel_vblank.c
341
bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
drivers/gpu/drm/i915/display/intel_vblank.c
342
display->platform.g4x || DISPLAY_VER(display) == 2 ||
drivers/gpu/drm/i915/display/intel_vblank.c
345
if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
drivers/gpu/drm/i915/display/intel_vblank.c
346
drm_dbg(display->drm,
drivers/gpu/drm/i915/display/intel_vblank.c
364
intel_vblank_section_enter(display);
drivers/gpu/drm/i915/display/intel_vblank.c
396
position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
drivers/gpu/drm/i915/display/intel_vblank.c
432
intel_vblank_section_exit(display);
drivers/gpu/drm/i915/display/intel_vblank.c
467
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vblank.c
472
intel_vblank_section_enter(display);
drivers/gpu/drm/i915/display/intel_vblank.c
476
intel_vblank_section_exit(display);
drivers/gpu/drm/i915/display/intel_vblank.c
482
static bool pipe_scanline_is_moving(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_vblank.c
485
intel_reg_t reg = PIPEDSL(display, pipe);
drivers/gpu/drm/i915/display/intel_vblank.c
488
line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
drivers/gpu/drm/i915/display/intel_vblank.c
490
line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
drivers/gpu/drm/i915/display/intel_vblank.c
497
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vblank.c
503
ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),
drivers/gpu/drm/i915/display/intel_vblank.c
507
drm_err(display->drm,
drivers/gpu/drm/i915/display/intel_vblank.c
542
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vblank.c
553
drm_WARN_ON(display->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
drivers/gpu/drm/i915/display/intel_vblank.c
569
spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
drivers/gpu/drm/i915/display/intel_vblank.c
570
intel_vblank_section_enter(display);
drivers/gpu/drm/i915/display/intel_vblank.c
579
intel_vblank_section_exit(display);
drivers/gpu/drm/i915/display/intel_vblank.c
580
spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
drivers/gpu/drm/i915/display/intel_vblank.c
686
struct intel_display *display = to_intel_display(new_crtc_state);
drivers/gpu/drm/i915/display/intel_vblank.c
694
evade->need_vlv_dsi_wa = (display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_vblank.c
695
display->platform.cherryview) &&
drivers/gpu/drm/i915/display/intel_vblank.c
739
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vblank.c
76
struct intel_display *display = to_intel_display(crtc->dev);
drivers/gpu/drm/i915/display/intel_vblank.c
761
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_vdsc.c
103
drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
drivers/gpu/drm/i915/display/intel_vdsc.c
1058
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_vdsc.c
1074
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
1086
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/intel_vdsc.c
1090
dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vdsc.c
1091
dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vdsc.c
1107
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/intel_vdsc.c
1130
int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_vdsc.c
1137
if (drm_WARN_ON(display->drm, !htotal))
drivers/gpu/drm/i915/display/intel_vdsc.c
1148
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
1158
pixel_rate = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
1187
int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
drivers/gpu/drm/i915/display/intel_vdsc.c
1189
intel_dsc_get_pixel_rate_with_dsc_bubbles(display, pixel_clock,
drivers/gpu/drm/i915/display/intel_vdsc.c
26
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
29
if (!HAS_DSC(display))
drivers/gpu/drm/i915/display/intel_vdsc.c
32
if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
drivers/gpu/drm/i915/display/intel_vdsc.c
326
struct intel_display *display = to_intel_display(pipe_config);
drivers/gpu/drm/i915/display/intel_vdsc.c
340
drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");
drivers/gpu/drm/i915/display/intel_vdsc.c
351
if (DISPLAY_VER(display) >= 14 &&
drivers/gpu/drm/i915/display/intel_vdsc.c
372
drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",
drivers/gpu/drm/i915/display/intel_vdsc.c
395
if (DISPLAY_VER(display) >= 13 && !is_dsi_dsc_1_1(pipe_config)) {
drivers/gpu/drm/i915/display/intel_vdsc.c
43
bool intel_dsc_get_slice_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_vdsc.c
436
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
438
drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&
drivers/gpu/drm/i915/display/intel_vdsc.c
447
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vdsc.c
461
if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
drivers/gpu/drm/i915/display/intel_vdsc.c
508
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
515
drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
drivers/gpu/drm/i915/display/intel_vdsc.c
520
intel_de_write(display, dsc_reg[i], pps_val);
drivers/gpu/drm/i915/display/intel_vdsc.c
525
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
56
if (!HAS_DSC_3ENGINES(display) || pipes_per_line != 4)
drivers/gpu/drm/i915/display/intel_vdsc.c
620
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/intel_vdsc.c
638
intel_de_write(display, DSCA_RC_BUF_THRESH_0,
drivers/gpu/drm/i915/display/intel_vdsc.c
640
intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
642
intel_de_write(display, DSCA_RC_BUF_THRESH_1,
drivers/gpu/drm/i915/display/intel_vdsc.c
644
intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
647
intel_de_write(display, DSCC_RC_BUF_THRESH_0,
drivers/gpu/drm/i915/display/intel_vdsc.c
649
intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
651
intel_de_write(display, DSCC_RC_BUF_THRESH_1,
drivers/gpu/drm/i915/display/intel_vdsc.c
653
intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
657
intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
659
intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
661
intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
663
intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
666
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
669
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
672
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
675
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
692
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
drivers/gpu/drm/i915/display/intel_vdsc.c
694
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
696
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
drivers/gpu/drm/i915/display/intel_vdsc.c
698
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
700
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
drivers/gpu/drm/i915/display/intel_vdsc.c
702
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
704
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
drivers/gpu/drm/i915/display/intel_vdsc.c
706
intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,
drivers/gpu/drm/i915/display/intel_vdsc.c
709
intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,
drivers/gpu/drm/i915/display/intel_vdsc.c
711
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
714
intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,
drivers/gpu/drm/i915/display/intel_vdsc.c
716
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
719
intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,
drivers/gpu/drm/i915/display/intel_vdsc.c
721
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
724
intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,
drivers/gpu/drm/i915/display/intel_vdsc.c
726
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
731
intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
733
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
736
intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
738
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
741
intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
743
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
746
intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
drivers/gpu/drm/i915/display/intel_vdsc.c
748
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
752
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
755
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
758
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
761
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
764
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
767
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
770
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
773
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vdsc.c
826
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
834
drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);
drivers/gpu/drm/i915/display/intel_vdsc.c
835
drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);
drivers/gpu/drm/i915/display/intel_vdsc.c
840
intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
drivers/gpu/drm/i915/display/intel_vdsc.c
843
intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
drivers/gpu/drm/i915/display/intel_vdsc.c
860
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
870
intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vdsc.c
877
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
911
intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
drivers/gpu/drm/i915/display/intel_vdsc.c
912
intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
drivers/gpu/drm/i915/display/intel_vdsc.c
917
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
92
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/intel_vdsc.c
923
intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vdsc.c
924
intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vdsc.c
931
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
939
drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
drivers/gpu/drm/i915/display/intel_vdsc.c
94
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/intel_vdsc.c
945
val = intel_de_read(display, dsc_reg[0]);
drivers/gpu/drm/i915/display/intel_vdsc.c
948
if (intel_de_read(display, dsc_reg[i]) != val) {
drivers/gpu/drm/i915/display/intel_vdsc.c
959
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.c
964
drm_WARN_ON(display->drm, !all_equal);
drivers/gpu/drm/i915/display/intel_vdsc.c
971
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vdsc.h
23
bool intel_dsc_get_slice_config(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_vdsc.h
47
int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_vga.c
115
static int intel_vga_get(struct intel_display *display, bool mmio,
drivers/gpu/drm/i915/display/intel_vga.c
118
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_vga.c
137
if (display->platform.dgfx) {
drivers/gpu/drm/i915/display/intel_vga.c
148
static void intel_vga_put(struct intel_display *display, bool io_decode, bool mmio)
drivers/gpu/drm/i915/display/intel_vga.c
150
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_vga.c
158
if (display->platform.dgfx)
drivers/gpu/drm/i915/display/intel_vga.c
162
u8 intel_vga_read(struct intel_display *display, u16 reg, bool mmio)
drivers/gpu/drm/i915/display/intel_vga.c
165
return intel_de_read8(display, _MMIO(reg));
drivers/gpu/drm/i915/display/intel_vga.c
170
static void intel_vga_write(struct intel_display *display, u16 reg, u8 val, bool mmio)
drivers/gpu/drm/i915/display/intel_vga.c
173
intel_de_write8(display, _MMIO(reg), val);
drivers/gpu/drm/i915/display/intel_vga.c
179
void intel_vga_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
181
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_vga.c
182
intel_reg_t vga_reg = intel_vga_cntrl_reg(display);
drivers/gpu/drm/i915/display/intel_vga.c
183
bool mmio = has_vga_mmio_access(display);
drivers/gpu/drm/i915/display/intel_vga.c
189
if (!intel_vga_decode_is_enabled(display)) {
drivers/gpu/drm/i915/display/intel_vga.c
190
drm_dbg_kms(display->drm, "VGA decode is disabled\n");
drivers/gpu/drm/i915/display/intel_vga.c
200
tmp = intel_de_read(display, vga_reg);
drivers/gpu/drm/i915/display/intel_vga.c
205
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_vga.c
207
else if (has_vga_pipe_sel(display))
drivers/gpu/drm/i915/display/intel_vga.c
21
static unsigned int intel_gmch_ctrl_reg(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
212
drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n",
drivers/gpu/drm/i915/display/intel_vga.c
215
drm_dbg_kms(display->drm, "VGA plane is disabled\n");
drivers/gpu/drm/i915/display/intel_vga.c
225
if (display->platform.dgfx)
drivers/gpu/drm/i915/display/intel_vga.c
23
return DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : I830_GMCH_CTRL;
drivers/gpu/drm/i915/display/intel_vga.c
236
err = intel_vga_get(display, mmio, &io_decode);
drivers/gpu/drm/i915/display/intel_vga.c
240
drm_WARN_ON(display->drm, !mmio && !intel_pci_has_vga_io_decode(pdev));
drivers/gpu/drm/i915/display/intel_vga.c
242
intel_vga_write(display, VGA_SEQ_I, 0x01, mmio);
drivers/gpu/drm/i915/display/intel_vga.c
243
sr1 = intel_vga_read(display, VGA_SEQ_D, mmio);
drivers/gpu/drm/i915/display/intel_vga.c
245
intel_vga_write(display, VGA_SEQ_D, sr1, mmio);
drivers/gpu/drm/i915/display/intel_vga.c
247
msr = intel_vga_read(display, VGA_MIS_R, mmio);
drivers/gpu/drm/i915/display/intel_vga.c
26
static bool intel_vga_decode_is_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
267
intel_vga_write(display, VGA_MIS_W, msr, mmio);
drivers/gpu/drm/i915/display/intel_vga.c
269
intel_vga_put(display, io_decode, mmio);
drivers/gpu/drm/i915/display/intel_vga.c
276
if (!display->platform.dgfx)
drivers/gpu/drm/i915/display/intel_vga.c
28
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_vga.c
282
intel_de_write(display, vga_reg, VGA_DISP_DISABLE);
drivers/gpu/drm/i915/display/intel_vga.c
283
intel_de_posting_read(display, vga_reg);
drivers/gpu/drm/i915/display/intel_vga.c
288
struct intel_display *display = to_intel_display(pdev);
drivers/gpu/drm/i915/display/intel_vga.c
291
drm_dbg_kms(display->drm, "%s VGA decode due to VGA arbitration\n",
drivers/gpu/drm/i915/display/intel_vga.c
305
if (display->platform.dgfx) {
drivers/gpu/drm/i915/display/intel_vga.c
32
intel_gmch_ctrl_reg(display), &gmch_ctrl))
drivers/gpu/drm/i915/display/intel_vga.c
320
void intel_vga_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
323
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_vga.c
335
drm_WARN_ON(display->drm, ret && ret != -ENODEV);
drivers/gpu/drm/i915/display/intel_vga.c
338
void intel_vga_unregister(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
340
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
drivers/gpu/drm/i915/display/intel_vga.c
38
static intel_reg_t intel_vga_cntrl_reg(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
40
if (display->platform.valleyview || display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_vga.c
42
else if (DISPLAY_VER(display) >= 5)
drivers/gpu/drm/i915/display/intel_vga.c
48
static bool has_vga_pipe_sel(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
50
if (display->platform.i845g ||
drivers/gpu/drm/i915/display/intel_vga.c
51
display->platform.i865g)
drivers/gpu/drm/i915/display/intel_vga.c
54
if (display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_vga.c
55
display->platform.cherryview)
drivers/gpu/drm/i915/display/intel_vga.c
58
return DISPLAY_VER(display) < 7;
drivers/gpu/drm/i915/display/intel_vga.c
61
static bool has_vga_mmio_access(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vga.c
64
return DISPLAY_VER(display) < 5 && !display->platform.g4x;
drivers/gpu/drm/i915/display/intel_vga.h
13
u8 intel_vga_read(struct intel_display *display, u16 reg, bool mmio);
drivers/gpu/drm/i915/display/intel_vga.h
14
void intel_vga_reset_io_mem(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_vga.h
15
void intel_vga_disable(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_vga.h
16
void intel_vga_register(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_vga.h
17
void intel_vga_unregister(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_vrr.c
1004
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
1010
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1013
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
1028
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1035
reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1038
reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1042
intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1044
intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1046
intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1048
intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1050
intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
drivers/gpu/drm/i915/display/intel_vrr.c
1055
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1060
trans_vrr_ctl = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1061
TRANS_VRR_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1063
if (HAS_CMRR(display))
drivers/gpu/drm/i915/display/intel_vrr.c
1068
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1070
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1073
if (DISPLAY_VER(display) >= 13) {
drivers/gpu/drm/i915/display/intel_vrr.c
1088
crtc_state->vrr.flipline = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1089
TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
drivers/gpu/drm/i915/display/intel_vrr.c
1090
crtc_state->vrr.vmax = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1091
TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
drivers/gpu/drm/i915/display/intel_vrr.c
1092
crtc_state->vrr.vmin = intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1093
TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
drivers/gpu/drm/i915/display/intel_vrr.c
1095
if (DISPLAY_VER(display) < 13) {
drivers/gpu/drm/i915/display/intel_vrr.c
1101
crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
drivers/gpu/drm/i915/display/intel_vrr.c
111
static int intel_vrr_extra_vblank_delay(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vrr.c
1110
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
1114
if (HAS_AS_SDP(display)) {
drivers/gpu/drm/i915/display/intel_vrr.c
1116
intel_de_read(display,
drivers/gpu/drm/i915/display/intel_vrr.c
1117
TRANS_VRR_VSYNC(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1127
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
1150
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
1158
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1160
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_vrr.c
1186
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
119
return DISPLAY_VER(display) < 13 ? 1 : 0;
drivers/gpu/drm/i915/display/intel_vrr.c
1190
tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1200
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1204
tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
1214
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1218
tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
122
static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vrr.c
1225
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
1229
tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
132
return DISPLAY_VER(display) < 13 ? 1 : 0;
drivers/gpu/drm/i915/display/intel_vrr.c
190
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
195
if (!HAS_CMRR(display) || true)
drivers/gpu/drm/i915/display/intel_vrr.c
276
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
282
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_vrr.c
313
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
316
intel_vrr_vmin_flipline_offset(display);
drivers/gpu/drm/i915/display/intel_vrr.c
327
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
333
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
335
intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
337
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
36
struct intel_display *display = to_intel_display(connector);
drivers/gpu/drm/i915/display/intel_vrr.c
370
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
379
return (HAS_VRR_DC_BALANCE(display) &&
drivers/gpu/drm/i915/display/intel_vrr.c
40
if (!HAS_VRR(display))
drivers/gpu/drm/i915/display/intel_vrr.c
422
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
430
if (!HAS_VRR(display))
drivers/gpu/drm/i915/display/intel_vrr.c
453
if (HAS_LRR(display))
drivers/gpu/drm/i915/display/intel_vrr.c
467
if (HAS_AS_SDP(display)) {
drivers/gpu/drm/i915/display/intel_vrr.c
482
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
485
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_vrr.c
495
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
501
intel_vrr_extra_vblank_delay(display);
drivers/gpu/drm/i915/display/intel_vrr.c
514
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
526
prefill_latency_us = max(display->sagv.block_time_us,
drivers/gpu/drm/i915/display/intel_vrr.c
527
skl_watermark_max_latency(display, 1));
drivers/gpu/drm/i915/display/intel_vrr.c
558
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
573
if (intel_vrr_always_use_vrr_tg(display)) {
drivers/gpu/drm/i915/display/intel_vrr.c
584
if (DISPLAY_VER(display) < 13)
drivers/gpu/drm/i915/display/intel_vrr.c
592
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
594
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/intel_vrr.c
597
else if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/intel_vrr.c
608
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
611
if (!HAS_VRR(display))
drivers/gpu/drm/i915/display/intel_vrr.c
623
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/intel_vrr.c
624
!(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));
drivers/gpu/drm/i915/display/intel_vrr.c
631
if (IS_DISPLAY_VER(display, 12, 13))
drivers/gpu/drm/i915/display/intel_vrr.c
632
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
636
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vrr.c
637
TRANS_VRR_CTL(display, cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
642
intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
644
intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
646
intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
648
intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
654
if (!intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
655
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
658
if (HAS_AS_SDP(display))
drivers/gpu/drm/i915/display/intel_vrr.c
659
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vrr.c
660
TRANS_VRR_VSYNC(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
671
if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/intel_vrr.c
672
intel_de_write(display,
drivers/gpu/drm/i915/display/intel_vrr.c
673
EMP_AS_SDP_TL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
681
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
687
intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
695
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
701
intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
702
intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
708
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
711
if (intel_vrr_always_use_vrr_tg(display) ||
drivers/gpu/drm/i915/display/intel_vrr.c
718
if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display))
drivers/gpu/drm/i915/display/intel_vrr.c
727
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
736
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/intel_vrr.c
737
TRANS_PUSH(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
746
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
768
intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
772
drm_err(display->drm, "[CRTC:%d:%s] VRR push send still pending\n",
drivers/gpu/drm/i915/display/intel_vrr.c
779
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
785
return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
drivers/gpu/drm/i915/display/intel_vrr.c
788
bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_vrr.c
790
if (!HAS_VRR(display))
drivers/gpu/drm/i915/display/intel_vrr.c
793
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/intel_vrr.c
801
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
804
intel_vrr_vmin_flipline_offset(display);
drivers/gpu/drm/i915/display/intel_vrr.c
819
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
822
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
824
intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
826
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
833
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
837
u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
842
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
844
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
846
intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
848
intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
850
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
852
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
854
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
856
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
858
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
860
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
862
intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
864
intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
866
intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
868
intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
870
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
drivers/gpu/drm/i915/display/intel_vrr.c
872
intel_dmc_configure_dc_balance_event(display, pipe, true);
drivers/gpu/drm/i915/display/intel_vrr.c
873
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
878
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
drivers/gpu/drm/i915/display/intel_vrr.c
884
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
888
u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
drivers/gpu/drm/i915/display/intel_vrr.c
894
intel_dmc_configure_dc_balance_event(display, pipe, false);
drivers/gpu/drm/i915/display/intel_vrr.c
895
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
896
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
897
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
898
intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
899
intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
900
intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
901
intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
902
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
903
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
904
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
905
intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
906
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
907
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
908
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
909
intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
910
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
drivers/gpu/drm/i915/display/intel_vrr.c
913
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
drivers/gpu/drm/i915/display/intel_vrr.c
919
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
923
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
936
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
drivers/gpu/drm/i915/display/intel_vrr.c
941
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
944
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
947
if (intel_de_wait_for_clear_ms(display,
drivers/gpu/drm/i915/display/intel_vrr.c
948
TRANS_VRR_STATUS(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
950
drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
drivers/gpu/drm/i915/display/intel_vrr.c
952
intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder),
drivers/gpu/drm/i915/display/intel_vrr.c
958
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
966
if (!intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
972
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
977
if (!intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
986
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.c
993
if (intel_vrr_always_use_vrr_tg(display))
drivers/gpu/drm/i915/display/intel_vrr.c
999
struct intel_display *display = to_intel_display(old_crtc_state);
drivers/gpu/drm/i915/display/intel_vrr.h
48
bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_vrr_regs.h
105
#define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
112
#define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
121
#define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
141
#define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
151
#define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
158
#define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
165
#define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
171
#define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
179
#define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
184
#define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
187
#define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
190
#define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
193
#define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
82
#define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
98
#define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A)
drivers/gpu/drm/i915/display/intel_wm.c
101
if (display->wm.funcs->compute_global_watermarks)
drivers/gpu/drm/i915/display/intel_wm.c
102
return display->wm.funcs->compute_global_watermarks(state);
drivers/gpu/drm/i915/display/intel_wm.c
107
void intel_wm_get_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_wm.c
109
if (display->wm.funcs->get_hw_state)
drivers/gpu/drm/i915/display/intel_wm.c
110
return display->wm.funcs->get_hw_state(display);
drivers/gpu/drm/i915/display/intel_wm.c
113
void intel_wm_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_wm.c
115
if (display->wm.funcs->sanitize)
drivers/gpu/drm/i915/display/intel_wm.c
116
return display->wm.funcs->sanitize(display);
drivers/gpu/drm/i915/display/intel_wm.c
142
void intel_print_wm_latency(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_wm.c
147
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/intel_wm.c
151
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_wm.c
161
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
166
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/intel_wm.c
172
void intel_wm_init(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_wm.c
174
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
175
skl_wm_init(display);
drivers/gpu/drm/i915/display/intel_wm.c
177
i9xx_wm_init(display);
drivers/gpu/drm/i915/display/intel_wm.c
182
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
185
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_wm.c
187
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/intel_wm.c
194
if (DISPLAY_VER(display) >= 9 ||
drivers/gpu/drm/i915/display/intel_wm.c
195
display->platform.valleyview ||
drivers/gpu/drm/i915/display/intel_wm.c
196
display->platform.cherryview ||
drivers/gpu/drm/i915/display/intel_wm.c
197
display->platform.g4x)
drivers/gpu/drm/i915/display/intel_wm.c
206
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_wm.c
211
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
214
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
215
latencies = display->wm.skl_latency;
drivers/gpu/drm/i915/display/intel_wm.c
217
latencies = display->wm.pri_latency;
drivers/gpu/drm/i915/display/intel_wm.c
226
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
229
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
230
latencies = display->wm.skl_latency;
drivers/gpu/drm/i915/display/intel_wm.c
232
latencies = display->wm.spr_latency;
drivers/gpu/drm/i915/display/intel_wm.c
241
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
244
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
245
latencies = display->wm.skl_latency;
drivers/gpu/drm/i915/display/intel_wm.c
247
latencies = display->wm.cur_latency;
drivers/gpu/drm/i915/display/intel_wm.c
256
struct intel_display *display = inode->i_private;
drivers/gpu/drm/i915/display/intel_wm.c
258
if (DISPLAY_VER(display) < 5 && !display->platform.g4x)
drivers/gpu/drm/i915/display/intel_wm.c
261
return single_open(file, pri_wm_latency_show, display);
drivers/gpu/drm/i915/display/intel_wm.c
266
struct intel_display *display = inode->i_private;
drivers/gpu/drm/i915/display/intel_wm.c
268
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_wm.c
271
return single_open(file, spr_wm_latency_show, display);
drivers/gpu/drm/i915/display/intel_wm.c
276
struct intel_display *display = inode->i_private;
drivers/gpu/drm/i915/display/intel_wm.c
278
if (HAS_GMCH(display))
drivers/gpu/drm/i915/display/intel_wm.c
281
return single_open(file, cur_wm_latency_show, display);
drivers/gpu/drm/i915/display/intel_wm.c
288
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
305
if (ret != display->wm.num_levels)
drivers/gpu/drm/i915/display/intel_wm.c
308
drm_modeset_lock_all(display->drm);
drivers/gpu/drm/i915/display/intel_wm.c
310
for (level = 0; level < display->wm.num_levels; level++)
drivers/gpu/drm/i915/display/intel_wm.c
313
drm_modeset_unlock_all(display->drm);
drivers/gpu/drm/i915/display/intel_wm.c
322
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
325
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
326
latencies = display->wm.skl_latency;
drivers/gpu/drm/i915/display/intel_wm.c
328
latencies = display->wm.pri_latency;
drivers/gpu/drm/i915/display/intel_wm.c
337
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
340
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
341
latencies = display->wm.skl_latency;
drivers/gpu/drm/i915/display/intel_wm.c
343
latencies = display->wm.spr_latency;
drivers/gpu/drm/i915/display/intel_wm.c
352
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/intel_wm.c
355
if (DISPLAY_VER(display) >= 9)
drivers/gpu/drm/i915/display/intel_wm.c
356
latencies = display->wm.skl_latency;
drivers/gpu/drm/i915/display/intel_wm.c
358
latencies = display->wm.cur_latency;
drivers/gpu/drm/i915/display/intel_wm.c
390
void intel_wm_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_wm.c
392
struct dentry *debugfs_root = display->drm->debugfs_root;
drivers/gpu/drm/i915/display/intel_wm.c
395
display, &i915_pri_wm_latency_fops);
drivers/gpu/drm/i915/display/intel_wm.c
398
display, &i915_spr_wm_latency_fops);
drivers/gpu/drm/i915/display/intel_wm.c
401
display, &i915_cur_wm_latency_fops);
drivers/gpu/drm/i915/display/intel_wm.c
403
skl_watermark_debugfs_register(display);
drivers/gpu/drm/i915/display/intel_wm.c
49
void intel_update_watermarks(struct intel_display *display)
drivers/gpu/drm/i915/display/intel_wm.c
51
if (display->wm.funcs->update_wm)
drivers/gpu/drm/i915/display/intel_wm.c
52
display->wm.funcs->update_wm(display);
drivers/gpu/drm/i915/display/intel_wm.c
58
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_wm.c
60
if (!display->wm.funcs->compute_watermarks)
drivers/gpu/drm/i915/display/intel_wm.c
63
return display->wm.funcs->compute_watermarks(state, crtc);
drivers/gpu/drm/i915/display/intel_wm.c
69
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_wm.c
71
if (display->wm.funcs->initial_watermarks) {
drivers/gpu/drm/i915/display/intel_wm.c
72
display->wm.funcs->initial_watermarks(state, crtc);
drivers/gpu/drm/i915/display/intel_wm.c
82
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_wm.c
84
if (display->wm.funcs->atomic_update_watermarks)
drivers/gpu/drm/i915/display/intel_wm.c
85
display->wm.funcs->atomic_update_watermarks(state, crtc);
drivers/gpu/drm/i915/display/intel_wm.c
91
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_wm.c
93
if (display->wm.funcs->optimize_watermarks)
drivers/gpu/drm/i915/display/intel_wm.c
94
display->wm.funcs->optimize_watermarks(state, crtc);
drivers/gpu/drm/i915/display/intel_wm.c
99
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/intel_wm.h
17
void intel_update_watermarks(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_wm.h
27
void intel_wm_get_hw_state(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_wm.h
28
void intel_wm_sanitize(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_wm.h
31
void intel_print_wm_latency(struct intel_display *display,
drivers/gpu/drm/i915/display/intel_wm.h
33
void intel_wm_init(struct intel_display *display);
drivers/gpu/drm/i915/display/intel_wm.h
34
void intel_wm_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_scaler.c
100
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/skl_scaler.c
1004
intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
drivers/gpu/drm/i915/display/skl_scaler.c
1009
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.c
1017
intel_de_write_fw(display,
drivers/gpu/drm/i915/display/skl_scaler.c
1020
intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
drivers/gpu/drm/i915/display/skl_scaler.c
103
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/skl_scaler.c
106
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/skl_scaler.c
1068
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.c
1076
return min(max_scale, DIV_ROUND_UP_ULL((u64)display->cdclk.max_dotclk_freq << 16,
drivers/gpu/drm/i915/display/skl_scaler.c
124
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_scaler.c
126
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/skl_scaler.c
129
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/skl_scaler.c
139
skl_scaler_mode_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_scaler.c
147
skl_scaler_max_src_size(display, &max_w, &max_h);
drivers/gpu/drm/i915/display/skl_scaler.c
162
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.c
187
if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&
drivers/gpu/drm/i915/display/skl_scaler.c
189
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
210
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
222
skl_scaler_max_src_size(display, &max_src_w, &max_src_h);
drivers/gpu/drm/i915/display/skl_scaler.c
232
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
250
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
260
drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: "
drivers/gpu/drm/i915/display/skl_scaler.c
307
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_scaler.c
314
if (!icl_is_hdr_plane(display, plane->id) &&
drivers/gpu/drm/i915/display/skl_scaler.c
330
static bool scaler_has_casf(struct intel_display *display, int scaler_id)
drivers/gpu/drm/i915/display/skl_scaler.c
332
return HAS_CASF(display) && scaler_id == 1;
drivers/gpu/drm/i915/display/skl_scaler.c
340
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_scaler.c
347
if (casf_scaler && !scaler_has_casf(display, i))
drivers/gpu/drm/i915/display/skl_scaler.c
364
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_scaler.c
374
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/skl_scaler.c
387
} else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) {
drivers/gpu/drm/i915/display/skl_scaler.c
402
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_scaler.c
411
if (drm_WARN(display->drm, *scaler_id < 0,
drivers/gpu/drm/i915/display/skl_scaler.c
421
if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/skl_scaler.c
423
} else if (icl_is_hdr_plane(display, plane->id)) {
drivers/gpu/drm/i915/display/skl_scaler.c
439
} else if (DISPLAY_VER(display) >= 10) {
drivers/gpu/drm/i915/display/skl_scaler.c
475
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
512
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
525
drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n",
drivers/gpu/drm/i915/display/skl_scaler.c
552
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_scaler.c
560
if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))
drivers/gpu/drm/i915/display/skl_scaler.c
570
if (!plane_state && DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_scaler.c
603
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_scaler.c
627
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
648
to_intel_plane(drm_plane_from_index(display->drm, i));
drivers/gpu/drm/i915/display/skl_scaler.c
706
static void glk_program_nearest_filter_coefs(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_scaler.c
712
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_scaler.c
726
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_scaler.c
730
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_scaler.c
746
static void skl_scaler_setup_filter(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_scaler.c
754
glk_program_nearest_filter_coefs(display, dsb, pipe, id, set);
drivers/gpu/drm/i915/display/skl_scaler.c
773
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.c
792
if (drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/skl_scaler.c
796
if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503117))
drivers/gpu/drm/i915/display/skl_scaler.c
820
skl_scaler_setup_filter(display, NULL, pipe, id, 0,
drivers/gpu/drm/i915/display/skl_scaler.c
823
if (scaler_has_casf(display, id))
drivers/gpu/drm/i915/display/skl_scaler.c
824
intel_de_write_fw(display, SHARPNESS_CTL(crtc->pipe),
drivers/gpu/drm/i915/display/skl_scaler.c
827
intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);
drivers/gpu/drm/i915/display/skl_scaler.c
829
intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id),
drivers/gpu/drm/i915/display/skl_scaler.c
831
intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id),
drivers/gpu/drm/i915/display/skl_scaler.c
833
intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),
drivers/gpu/drm/i915/display/skl_scaler.c
835
intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),
drivers/gpu/drm/i915/display/skl_scaler.c
841
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.c
847
ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, scaler_id));
drivers/gpu/drm/i915/display/skl_scaler.c
861
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_scaler.c
885
!icl_is_hdr_plane(display, plane->id)) {
drivers/gpu/drm/i915/display/skl_scaler.c
907
skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0,
drivers/gpu/drm/i915/display/skl_scaler.c
910
intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id),
drivers/gpu/drm/i915/display/skl_scaler.c
912
intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id),
drivers/gpu/drm/i915/display/skl_scaler.c
914
intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id),
drivers/gpu/drm/i915/display/skl_scaler.c
916
intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id),
drivers/gpu/drm/i915/display/skl_scaler.c
918
intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id),
drivers/gpu/drm/i915/display/skl_scaler.c
925
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_scaler.c
929
if (scaler_has_casf(display, id))
drivers/gpu/drm/i915/display/skl_scaler.c
930
intel_de_write_dsb(display, dsb, SHARPNESS_CTL(crtc->pipe), 0);
drivers/gpu/drm/i915/display/skl_scaler.c
932
intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0);
drivers/gpu/drm/i915/display/skl_scaler.c
933
intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0);
drivers/gpu/drm/i915/display/skl_scaler.c
934
intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
drivers/gpu/drm/i915/display/skl_scaler.c
966
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.c
97
static void skl_scaler_max_src_size(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_scaler.c
977
if (scaler_has_casf(display, scaler_id))
drivers/gpu/drm/i915/display/skl_scaler.c
982
pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, scaler_id));
drivers/gpu/drm/i915/display/skl_scaler.c
983
size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, scaler_id));
drivers/gpu/drm/i915/display/skl_scaler.c
999
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_scaler.h
40
skl_scaler_mode_valid(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1170
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1173
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1187
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1195
if (DISPLAY_VER(display) < 10) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
1210
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1220
if (intel_display_wa(display, INTEL_DISPLAY_WA_22012358565))
drivers/gpu/drm/i915/display/skl_universal_plane.c
1228
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1231
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1245
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1253
if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
1295
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1300
drm_WARN_ON(display->drm, offset & 0x1fffff);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1303
drm_WARN_ON(display->drm, offset & 0xfff);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1332
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1343
if (DISPLAY_VER(display) < 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1381
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1385
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1386
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1388
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1389
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1391
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1392
intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1394
intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1395
intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1396
intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1398
intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1399
intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1400
intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1409
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1424
intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1426
intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1428
intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1440
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1455
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1459
intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1461
intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1463
intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1466
intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1469
intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1472
intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1476
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1477
intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1495
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1497
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1507
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1524
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1539
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1544
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1553
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1578
intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1580
intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1582
intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1585
intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1587
intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1589
intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1592
intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1596
intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1598
intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1603
if (HAS_AUX_DIST(display))
drivers/gpu/drm/i915/display/skl_universal_plane.c
1604
intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1607
if (icl_is_hdr_plane(display, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
1608
intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1611
intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1614
if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
1634
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1641
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1653
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1681
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1690
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1692
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1700
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1702
error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
1703
error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
1704
error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
1714
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1723
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1729
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1731
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
1750
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1760
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1768
DISPLAY_VER(display) < 35) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
1769
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1780
DISPLAY_VER(display) >= 20) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
1781
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1789
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1801
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
1814
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1827
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1834
if ((display->platform.alderlake_s || display->platform.tigerlake) &&
drivers/gpu/drm/i915/display/skl_universal_plane.c
1837
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1849
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1864
if (DISPLAY_VER(display) == 10 &&
drivers/gpu/drm/i915/display/skl_universal_plane.c
1866
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1880
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
1891
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1900
static int skl_plane_max_scale(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
1909
if (DISPLAY_VER(display) >= 10 ||
drivers/gpu/drm/i915/display/skl_universal_plane.c
2006
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2016
if (drm_WARN_ON(display->drm, alignment && !is_power_of_2(alignment)))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2040
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2057
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2075
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2103
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2110
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2111
drm_WARN_ON(display->drm, x > 65535 || y > 65535);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2113
drm_WARN_ON(display->drm, x > 8191 || y > 8191);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2131
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2162
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2197
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2204
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2205
drm_WARN_ON(display->drm, x > 65535 || y > 65535);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2207
drm_WARN_ON(display->drm, x > 8191 || y > 8191);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2293
struct intel_display *display;
drivers/gpu/drm/i915/display/skl_universal_plane.c
2298
display = to_intel_display(fb->dev);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2307
return DISPLAY_VER(display) >= 11;
drivers/gpu/drm/i915/display/skl_universal_plane.c
2315
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2319
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2368
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2382
max_scale = skl_plane_max_scale(display, fb);
drivers/gpu/drm/i915/display/skl_universal_plane.c
240
static u8 icl_nv12_y_plane_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_universal_plane.c
242
if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2423
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2427
icl_is_hdr_plane(display, plane->id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2441
struct intel_display *display = to_intel_display(uv_plane_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2445
drm_WARN_ON(display->drm, icl_is_nv12_y_plane(display, uv_plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
2446
drm_WARN_ON(display->drm, !icl_is_nv12_y_plane(display, y_plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
2450
if (icl_is_hdr_plane(display, uv_plane->id)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2470
static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2475
if (skl_plane_has_fbc(display, fbc_id, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2476
return display->fbc.instances[fbc_id];
drivers/gpu/drm/i915/display/skl_universal_plane.c
248
bool icl_is_nv12_y_plane(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2481
static bool skl_plane_has_planar(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2485
if (display->platform.skylake || display->platform.broxton)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2494
static const u32 *skl_get_plane_formats(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2498
if (skl_plane_has_planar(display, pipe, plane_id)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2507
static bool glk_plane_has_planar(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
251
return DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/skl_universal_plane.c
2513
static const u32 *glk_get_plane_formats(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2517
if (glk_plane_has_planar(display, pipe, plane_id)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
252
icl_nv12_y_plane_mask(display) & BIT(plane_id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2526
static const u32 *icl_get_plane_formats(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2530
if (icl_is_hdr_plane(display, plane_id)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2533
} else if (icl_is_nv12_y_plane(display, plane_id)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
260
bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id)
drivers/gpu/drm/i915/display/skl_universal_plane.c
262
return DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/skl_universal_plane.c
2735
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2738
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2739
bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
2740
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2746
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2749
spin_lock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2750
bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
2751
spin_unlock_irq(&display->irq.lock);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2754
static bool skl_plane_has_rc_ccs(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2763
static u8 skl_plane_caps(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2770
if (skl_plane_has_rc_ccs(display, pipe, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2776
static bool glk_plane_has_rc_ccs(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2782
static u8 glk_plane_caps(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2789
if (glk_plane_has_rc_ccs(display, pipe))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2795
static u8 icl_plane_caps(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2804
static bool tgl_plane_has_mc_ccs(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2808
if (intel_display_wa(display, INTEL_DISPLAY_WA_14010477008))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2814
static u8 tgl_plane_caps(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2821
if (HAS_4TILE(display))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2826
if (tgl_plane_has_mc_ccs(display, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2829
if (DISPLAY_VER(display) >= 14 && display->platform.dgfx)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2838
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2842
plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
2852
intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
2855
intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2857
intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
2862
skl_universal_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2884
intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2886
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2891
} else if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2892
if (DISPLAY_VER(display) >= 14 || display->platform.alderlake_p)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2896
if (icl_is_hdr_plane(display, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2902
} else if (DISPLAY_VER(display) >= 10) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2915
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2920
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2925
if (intel_scanout_needs_vtd_wa(display))
drivers/gpu/drm/i915/display/skl_universal_plane.c
2926
plane->vtd_guard = DISPLAY_VER(display) >= 10 ? 168 : 136;
drivers/gpu/drm/i915/display/skl_universal_plane.c
2928
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2941
if (HAS_ASYNC_FLIPS(display) && plane_id == PLANE_1) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
2942
plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(display, 9, 10);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2947
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2949
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2955
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2956
formats = icl_get_plane_formats(display, pipe,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2958
else if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2959
formats = glk_get_plane_formats(display, pipe,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2962
formats = skl_get_plane_formats(display, pipe,
drivers/gpu/drm/i915/display/skl_universal_plane.c
2965
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2967
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2977
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2978
caps = tgl_plane_caps(display, pipe, plane_id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2979
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2980
caps = icl_plane_caps(display, pipe, plane_id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2981
else if (DISPLAY_VER(display) == 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
2982
caps = glk_plane_caps(display, pipe, plane_id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2984
caps = skl_plane_caps(display, pipe, plane_id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2986
modifiers = intel_fb_plane_get_modifiers(display, caps);
drivers/gpu/drm/i915/display/skl_universal_plane.c
2988
ret = drm_universal_plane_init(display->drm, &plane->base,
drivers/gpu/drm/i915/display/skl_universal_plane.c
3000
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3007
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3016
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3026
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3037
if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3040
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3059
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_universal_plane.c
3074
drm_WARN_ON(display->drm, pipe != crtc->pipe);
drivers/gpu/drm/i915/display/skl_universal_plane.c
3077
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
3085
drm_dbg_kms(display->drm, "failed to alloc fb\n");
drivers/gpu/drm/i915/display/skl_universal_plane.c
3091
fb->dev = display->drm;
drivers/gpu/drm/i915/display/skl_universal_plane.c
3093
val = intel_de_read(display, PLANE_CTL(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3095
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3100
if (DISPLAY_VER(display) >= 10) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
3103
color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3122
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3124
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3129
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3137
if (HAS_4TILE(display)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
3161
fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier);
drivers/gpu/drm/i915/display/skl_universal_plane.c
3182
if (DISPLAY_VER(display) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
drivers/gpu/drm/i915/display/skl_universal_plane.c
3189
base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
drivers/gpu/drm/i915/display/skl_universal_plane.c
3192
offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3193
drm_WARN_ON(display->drm, offset != 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
3195
val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3199
val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_universal_plane.c
3208
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_universal_plane.c
3225
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_universal_plane.c
3242
intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);
drivers/gpu/drm/i915/display/skl_universal_plane.c
448
static bool skl_plane_has_fbc(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.c
451
if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)
drivers/gpu/drm/i915/display/skl_universal_plane.c
454
if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/skl_universal_plane.c
455
return icl_is_hdr_plane(display, plane_id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
585
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
598
if (display->platform.alderlake_p &&
drivers/gpu/drm/i915/display/skl_universal_plane.c
680
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
724
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
drivers/gpu/drm/i915/display/skl_universal_plane.c
726
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
drivers/gpu/drm/i915/display/skl_universal_plane.c
728
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
drivers/gpu/drm/i915/display/skl_universal_plane.c
730
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
drivers/gpu/drm/i915/display/skl_universal_plane.c
732
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
drivers/gpu/drm/i915/display/skl_universal_plane.c
734
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
drivers/gpu/drm/i915/display/skl_universal_plane.c
737
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
drivers/gpu/drm/i915/display/skl_universal_plane.c
739
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
drivers/gpu/drm/i915/display/skl_universal_plane.c
741
intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
drivers/gpu/drm/i915/display/skl_universal_plane.c
743
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_universal_plane.c
745
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_universal_plane.c
747
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_universal_plane.c
825
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
838
for (level = 0; level < display->wm.num_levels; level++)
drivers/gpu/drm/i915/display/skl_universal_plane.c
839
intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),
drivers/gpu/drm/i915/display/skl_universal_plane.c
842
intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
845
if (HAS_HW_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/skl_universal_plane.c
848
intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
850
intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
854
intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
857
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/skl_universal_plane.c
858
intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
861
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/skl_universal_plane.c
862
intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),
drivers/gpu/drm/i915/display/skl_universal_plane.c
871
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
877
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
878
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
885
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
891
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
896
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
898
return HAS_PIXEL_NORMALIZER(display) && icl_is_hdr_plane(display, plane->id);
drivers/gpu/drm/i915/display/skl_universal_plane.c
915
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
919
if (icl_is_hdr_plane(display, plane_id))
drivers/gpu/drm/i915/display/skl_universal_plane.c
920
intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
927
intel_de_write_dsb(display, dsb,
drivers/gpu/drm/i915/display/skl_universal_plane.c
930
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
931
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
drivers/gpu/drm/i915/display/skl_universal_plane.c
938
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_universal_plane.c
945
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/skl_universal_plane.c
949
ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
drivers/gpu/drm/i915/display/skl_universal_plane.c
953
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/skl_universal_plane.h
22
skl_universal_plane_create(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.h
38
bool icl_is_nv12_y_plane(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_universal_plane.h
41
bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id);
drivers/gpu/drm/i915/display/skl_watermark.c
100
intel_has_sagv(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
102
return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/skl_watermark.c
106
intel_sagv_block_time(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
108
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/skl_watermark.c
111
val = intel_de_read(display, MTL_LATENCY_SAGV);
drivers/gpu/drm/i915/display/skl_watermark.c
114
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/skl_watermark.c
118
ret = intel_parent_pcode_read(display, GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
drivers/gpu/drm/i915/display/skl_watermark.c
121
drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n");
drivers/gpu/drm/i915/display/skl_watermark.c
1244
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
1247
if (display->platform.dg2)
drivers/gpu/drm/i915/display/skl_watermark.c
1249
else if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/skl_watermark.c
1251
else if (DISPLAY_VER(display) == 12)
drivers/gpu/drm/i915/display/skl_watermark.c
1253
else if (DISPLAY_VER(display) == 11)
drivers/gpu/drm/i915/display/skl_watermark.c
126
} else if (DISPLAY_VER(display) == 11) {
drivers/gpu/drm/i915/display/skl_watermark.c
1266
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
1269
return IS_DISPLAY_VER(display, 13, 20) &&
drivers/gpu/drm/i915/display/skl_watermark.c
128
} else if (HAS_SAGV(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
1293
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
1304
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/skl_watermark.c
135
static void intel_sagv_init(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
1365
static bool skl_need_wm_copy_wa(struct intel_display *display, int level,
drivers/gpu/drm/i915/display/skl_watermark.c
137
if (!HAS_SAGV(display))
drivers/gpu/drm/i915/display/skl_watermark.c
138
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/skl_watermark.c
144
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/skl_watermark.c
1441
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
145
skl_sagv_disable(display);
drivers/gpu/drm/i915/display/skl_watermark.c
147
drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN);
drivers/gpu/drm/i915/display/skl_watermark.c
1477
for (level = display->wm.num_levels - 1; level >= 0; level--) {
drivers/gpu/drm/i915/display/skl_watermark.c
1488
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
149
display->sagv.block_time_us = intel_sagv_block_time(display);
drivers/gpu/drm/i915/display/skl_watermark.c
1507
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
1509
drm_dbg_kms(display->drm, "minimum required %d/%d\n",
drivers/gpu/drm/i915/display/skl_watermark.c
151
drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n",
drivers/gpu/drm/i915/display/skl_watermark.c
152
str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us);
drivers/gpu/drm/i915/display/skl_watermark.c
1537
if (DISPLAY_VER(display) < 11 &&
drivers/gpu/drm/i915/display/skl_watermark.c
1546
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/skl_watermark.c
155
if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX,
drivers/gpu/drm/i915/display/skl_watermark.c
1551
drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0);
drivers/gpu/drm/i915/display/skl_watermark.c
1559
for (level++; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
1568
if (DISPLAY_VER(display) < 11 &&
drivers/gpu/drm/i915/display/skl_watermark.c
157
display->sagv.block_time_us))
drivers/gpu/drm/i915/display/skl_watermark.c
1574
if (skl_need_wm_copy_wa(display, level, wm)) {
drivers/gpu/drm/i915/display/skl_watermark.c
158
display->sagv.block_time_us = 0;
drivers/gpu/drm/i915/display/skl_watermark.c
1596
if (DISPLAY_VER(display) < 11 &&
drivers/gpu/drm/i915/display/skl_watermark.c
160
if (!intel_has_sagv(display))
drivers/gpu/drm/i915/display/skl_watermark.c
1606
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/skl_watermark.c
161
display->sagv.block_time_us = 0;
drivers/gpu/drm/i915/display/skl_watermark.c
1622
skl_wm_method1(struct intel_display *display, u32 pixel_rate,
drivers/gpu/drm/i915/display/skl_watermark.c
1634
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_watermark.c
1671
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
1677
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
1694
if (DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/skl_watermark.c
1719
if (skl_needs_memory_bw_wa(display))
drivers/gpu/drm/i915/display/skl_watermark.c
1728
if (DISPLAY_VER(display) >= 30)
drivers/gpu/drm/i915/display/skl_watermark.c
1730
else if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_watermark.c
1739
if (!wp->x_tiled || DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_watermark.c
175
static void skl_sagv_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
1776
static bool skl_wm_has_lines(struct intel_display *display, int level)
drivers/gpu/drm/i915/display/skl_watermark.c
1778
if (DISPLAY_VER(display) >= 10)
drivers/gpu/drm/i915/display/skl_watermark.c
1785
static int skl_wm_max_lines(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
1787
if (DISPLAY_VER(display) >= 13)
drivers/gpu/drm/i915/display/skl_watermark.c
179
if (!intel_has_sagv(display))
drivers/gpu/drm/i915/display/skl_watermark.c
1795
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
1797
return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR;
drivers/gpu/drm/i915/display/skl_watermark.c
1808
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
182
if (display->sagv.status == I915_SAGV_ENABLED)
drivers/gpu/drm/i915/display/skl_watermark.c
1820
method1 = skl_wm_method1(display, wp->plane_pixel_rate,
drivers/gpu/drm/i915/display/skl_watermark.c
1829
} else if (DISPLAY_VER(display) >= 35) {
drivers/gpu/drm/i915/display/skl_watermark.c
1837
if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/skl_watermark.c
1847
if (DISPLAY_VER(display) < 30)
drivers/gpu/drm/i915/display/skl_watermark.c
185
drm_dbg_kms(display->drm, "Enabling SAGV\n");
drivers/gpu/drm/i915/display/skl_watermark.c
186
ret = intel_parent_pcode_write(display, GEN9_PCODE_SAGV_CONTROL,
drivers/gpu/drm/i915/display/skl_watermark.c
1866
if (skl_wm_has_lines(display, level))
drivers/gpu/drm/i915/display/skl_watermark.c
1872
if (DISPLAY_VER(display) == 9) {
drivers/gpu/drm/i915/display/skl_watermark.c
1900
if (DISPLAY_VER(display) >= 11) {
drivers/gpu/drm/i915/display/skl_watermark.c
1917
if (!skl_wm_has_lines(display, level))
drivers/gpu/drm/i915/display/skl_watermark.c
1920
if (lines > skl_wm_max_lines(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
1939
if (!HAS_SAGV_WM(display) && display->sagv.block_time_us)
drivers/gpu/drm/i915/display/skl_watermark.c
1940
result->can_sagv = latency >= display->sagv.block_time_us;
drivers/gpu/drm/i915/display/skl_watermark.c
1949
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
195
if (display->platform.skylake && ret == -ENXIO) {
drivers/gpu/drm/i915/display/skl_watermark.c
1953
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
1955
unsigned int latency = skl_wm_latency(display, level, wm_params);
drivers/gpu/drm/i915/display/skl_watermark.c
196
drm_dbg(display->drm, "No SAGV found on system, ignoring\n");
drivers/gpu/drm/i915/display/skl_watermark.c
1969
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
197
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/skl_watermark.c
1974
if (display->sagv.block_time_us)
drivers/gpu/drm/i915/display/skl_watermark.c
1975
latency = display->sagv.block_time_us +
drivers/gpu/drm/i915/display/skl_watermark.c
1976
skl_wm_latency(display, 0, wm_params);
drivers/gpu/drm/i915/display/skl_watermark.c
1983
static void skl_compute_transition_wm(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
1992
if (!skl_watermark_ipc_enabled(display))
drivers/gpu/drm/i915/display/skl_watermark.c
1999
if (DISPLAY_VER(display) == 9)
drivers/gpu/drm/i915/display/skl_watermark.c
200
drm_err(display->drm, "Failed to enable SAGV\n");
drivers/gpu/drm/i915/display/skl_watermark.c
2002
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
2008
if (DISPLAY_VER(display) == 10)
drivers/gpu/drm/i915/display/skl_watermark.c
204
display->sagv.status = I915_SAGV_ENABLED;
drivers/gpu/drm/i915/display/skl_watermark.c
2050
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
2062
skl_compute_transition_wm(display, &wm->trans_wm,
drivers/gpu/drm/i915/display/skl_watermark.c
2065
if (HAS_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
2068
skl_compute_transition_wm(display, &wm->sagv.trans_wm,
drivers/gpu/drm/i915/display/skl_watermark.c
207
static void skl_sagv_disable(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
2079
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
2097
for (level = 0; level < display->wm.num_levels; level++)
drivers/gpu/drm/i915/display/skl_watermark.c
211
if (!intel_has_sagv(display))
drivers/gpu/drm/i915/display/skl_watermark.c
2135
struct intel_display *display = to_intel_display(plane_state);
drivers/gpu/drm/i915/display/skl_watermark.c
214
if (display->sagv.status == I915_SAGV_DISABLED)
drivers/gpu/drm/i915/display/skl_watermark.c
2150
drm_WARN_ON(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
2152
drm_WARN_ON(display->drm, !fb->format->is_yuv ||
drivers/gpu/drm/i915/display/skl_watermark.c
217
drm_dbg_kms(display->drm, "Disabling SAGV\n");
drivers/gpu/drm/i915/display/skl_watermark.c
2176
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
2188
drm_WARN_ON(display->drm, !HAS_VRR(display));
drivers/gpu/drm/i915/display/skl_watermark.c
219
ret = intel_parent_pcode_request(display, GEN9_PCODE_SAGV_CONTROL,
drivers/gpu/drm/i915/display/skl_watermark.c
2192
if (HAS_4TILE(display))
drivers/gpu/drm/i915/display/skl_watermark.c
2197
info = drm_get_format_info(display->drm, format, modifier);
drivers/gpu/drm/i915/display/skl_watermark.c
2212
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/skl_watermark.c
2214
latency = skl_wm_latency(display, level, &wp);
drivers/gpu/drm/i915/display/skl_watermark.c
2220
wm.lines = skl_wm_max_lines(display);
drivers/gpu/drm/i915/display/skl_watermark.c
2254
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
2258
for (level = display->wm.num_levels - 1; level >= 0; level--) {
drivers/gpu/drm/i915/display/skl_watermark.c
226
if (display->platform.skylake && ret == -ENXIO) {
drivers/gpu/drm/i915/display/skl_watermark.c
2262
latency = skl_wm_latency(display, level, NULL);
drivers/gpu/drm/i915/display/skl_watermark.c
227
drm_dbg(display->drm, "No SAGV found on system, ignoring\n");
drivers/gpu/drm/i915/display/skl_watermark.c
2274
drm_dbg_kms(display->drm, "[CRTC:%d:%s] Not enough time in vblank for prefill\n",
drivers/gpu/drm/i915/display/skl_watermark.c
228
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
drivers/gpu/drm/i915/display/skl_watermark.c
2282
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
2300
crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;
drivers/gpu/drm/i915/display/skl_watermark.c
2309
for (level++; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
231
drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret);
drivers/gpu/drm/i915/display/skl_watermark.c
2324
if (HAS_SAGV_WM(display) &&
drivers/gpu/drm/i915/display/skl_watermark.c
2325
display->sagv.block_time_us &&
drivers/gpu/drm/i915/display/skl_watermark.c
2327
display->sagv.block_time_us)) {
drivers/gpu/drm/i915/display/skl_watermark.c
2345
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
235
display->sagv.status = I915_SAGV_DISABLED;
drivers/gpu/drm/i915/display/skl_watermark.c
2361
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
2384
static bool skl_plane_wm_equals(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
2390
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
240
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2437
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2444
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/skl_watermark.c
2455
drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n",
drivers/gpu/drm/i915/display/skl_watermark.c
247
if (!intel_bw_can_enable_sagv(display, new_bw_state))
drivers/gpu/drm/i915/display/skl_watermark.c
2474
struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);
drivers/gpu/drm/i915/display/skl_watermark.c
248
skl_sagv_disable(display);
drivers/gpu/drm/i915/display/skl_watermark.c
2484
for_each_pipe(display, pipe)
drivers/gpu/drm/i915/display/skl_watermark.c
2493
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2521
if (HAS_MBUS_JOINING(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
253
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2532
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
2555
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
2559
DISPLAY_INFO(display)->dbuf.slice_mask,
drivers/gpu/drm/i915/display/skl_watermark.c
2577
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
260
if (intel_bw_can_enable_sagv(display, new_bw_state))
drivers/gpu/drm/i915/display/skl_watermark.c
2607
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
2609
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
261
skl_sagv_enable(display);
drivers/gpu/drm/i915/display/skl_watermark.c
2641
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
2643
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
2649
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
2655
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
266
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2661
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
2667
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
2670
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
2685
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2700
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/skl_watermark.c
2710
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
2720
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/skl_watermark.c
2727
if (skl_plane_wm_equals(display, old_wm, new_wm))
drivers/gpu/drm/i915/display/skl_watermark.c
2739
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
2742
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
2748
if (HAS_HW_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
275
if (!intel_has_sagv(display))
drivers/gpu/drm/i915/display/skl_watermark.c
278
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
2786
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2793
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/skl_watermark.c
2812
drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n",
drivers/gpu/drm/i915/display/skl_watermark.c
2831
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2841
display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;
drivers/gpu/drm/i915/display/skl_watermark.c
2842
display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);
drivers/gpu/drm/i915/display/skl_watermark.c
2846
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
2847
if (display->pkgc.disable[crtc->pipe])
drivers/gpu/drm/i915/display/skl_watermark.c
2850
max_linetime = max(display->pkgc.linetime[crtc->pipe], max_linetime);
drivers/gpu/drm/i915/display/skl_watermark.c
2859
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
286
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2862
if (DISPLAY_VER(display) < 20)
drivers/gpu/drm/i915/display/skl_watermark.c
2865
mutex_lock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/skl_watermark.c
2867
latency = skl_watermark_max_latency(display, 1);
drivers/gpu/drm/i915/display/skl_watermark.c
2870
if (display->params.enable_flipq)
drivers/gpu/drm/i915/display/skl_watermark.c
2871
added_wake_time = intel_flipq_exec_time_us(display);
drivers/gpu/drm/i915/display/skl_watermark.c
2877
if (latency && IS_DISPLAY_VER(display, 20, 30)) {
drivers/gpu/drm/i915/display/skl_watermark.c
2897
intel_de_write(display, LNL_PKG_C_LATENCY,
drivers/gpu/drm/i915/display/skl_watermark.c
2901
mutex_unlock(&display->wm.wm_mutex);
drivers/gpu/drm/i915/display/skl_watermark.c
2907
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
2948
HAS_SAGV_WM(display) &&
drivers/gpu/drm/i915/display/skl_watermark.c
2949
!HAS_HW_SAGV_WM(display) &&
drivers/gpu/drm/i915/display/skl_watermark.c
295
if (!intel_has_sagv(display))
drivers/gpu/drm/i915/display/skl_watermark.c
2962
static void skl_wm_level_from_reg_val(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
2969
level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ?
drivers/gpu/drm/i915/display/skl_watermark.c
2976
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
298
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
2985
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
2987
val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));
drivers/gpu/drm/i915/display/skl_watermark.c
2989
val = intel_de_read(display, CUR_WM(pipe, level));
drivers/gpu/drm/i915/display/skl_watermark.c
2991
skl_wm_level_from_reg_val(display, val, &wm->wm[level]);
drivers/gpu/drm/i915/display/skl_watermark.c
2995
val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
2997
val = intel_de_read(display, CUR_WM_TRANS(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
2999
skl_wm_level_from_reg_val(display, val, &wm->trans_wm);
drivers/gpu/drm/i915/display/skl_watermark.c
3001
if (HAS_HW_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
3003
val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
3005
val = intel_de_read(display, CUR_WM_SAGV(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
3007
skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);
drivers/gpu/drm/i915/display/skl_watermark.c
3010
val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
3012
val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
3014
skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);
drivers/gpu/drm/i915/display/skl_watermark.c
3015
} else if (HAS_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
3022
static void skl_wm_get_hw_state(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3025
to_intel_dbuf_state(display->dbuf.obj.state);
drivers/gpu/drm/i915/display/skl_watermark.c
3028
if (HAS_MBUS_JOINING(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3029
dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
drivers/gpu/drm/i915/display/skl_watermark.c
3031
dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw);
drivers/gpu/drm/i915/display/skl_watermark.c
3034
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
306
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
3065
skl_ddb_get_hw_plane_state(display, crtc->pipe,
drivers/gpu/drm/i915/display/skl_watermark.c
3081
mbus_offset = mbus_ddb_offset(display, slices);
drivers/gpu/drm/i915/display/skl_watermark.c
3087
skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);
drivers/gpu/drm/i915/display/skl_watermark.c
3089
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
3097
dbuf_state->enabled_slices = display->dbuf.enabled_slices;
drivers/gpu/drm/i915/display/skl_watermark.c
3100
bool skl_watermark_ipc_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3102
return display->wm.ipc_enabled;
drivers/gpu/drm/i915/display/skl_watermark.c
3105
void skl_watermark_ipc_update(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3107
if (!HAS_IPC(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3110
intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE,
drivers/gpu/drm/i915/display/skl_watermark.c
3111
skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0);
drivers/gpu/drm/i915/display/skl_watermark.c
3114
static bool skl_watermark_ipc_can_enable(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3117
if (display->platform.skylake)
drivers/gpu/drm/i915/display/skl_watermark.c
3121
if (display->platform.kabylake ||
drivers/gpu/drm/i915/display/skl_watermark.c
3122
display->platform.coffeelake ||
drivers/gpu/drm/i915/display/skl_watermark.c
3123
display->platform.cometlake) {
drivers/gpu/drm/i915/display/skl_watermark.c
3124
const struct dram_info *dram_info = intel_dram_info(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3132
void skl_watermark_ipc_init(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3134
if (!HAS_IPC(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3137
display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3139
skl_watermark_ipc_update(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3142
static void multiply_wm_latency(struct intel_display *display, int mult)
drivers/gpu/drm/i915/display/skl_watermark.c
3144
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3145
int level, num_levels = display->wm.num_levels;
drivers/gpu/drm/i915/display/skl_watermark.c
3151
static void increase_wm_latency(struct intel_display *display, int inc)
drivers/gpu/drm/i915/display/skl_watermark.c
3153
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3154
int level, num_levels = display->wm.num_levels;
drivers/gpu/drm/i915/display/skl_watermark.c
3166
static bool need_16gb_dimm_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3168
const struct dram_info *dram_info = intel_dram_info(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3170
return (display->platform.skylake || display->platform.kabylake ||
drivers/gpu/drm/i915/display/skl_watermark.c
3171
display->platform.coffeelake || display->platform.cometlake ||
drivers/gpu/drm/i915/display/skl_watermark.c
3172
DISPLAY_VER(display) == 11) && dram_info->has_16gb_dimms;
drivers/gpu/drm/i915/display/skl_watermark.c
3175
static int wm_read_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3177
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/skl_watermark.c
3179
else if (DISPLAY_VER(display) >= 12)
drivers/gpu/drm/i915/display/skl_watermark.c
3185
static void sanitize_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3187
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3188
int level, num_levels = display->wm.num_levels;
drivers/gpu/drm/i915/display/skl_watermark.c
3194
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/skl_watermark.c
321
for (level = display->wm.num_levels - 1;
drivers/gpu/drm/i915/display/skl_watermark.c
3211
static void make_wm_latency_monotonic(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3213
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3214
int level, num_levels = display->wm.num_levels;
drivers/gpu/drm/i915/display/skl_watermark.c
3225
adjust_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3227
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3229
if (display->platform.dg2)
drivers/gpu/drm/i915/display/skl_watermark.c
3230
multiply_wm_latency(display, 2);
drivers/gpu/drm/i915/display/skl_watermark.c
3232
sanitize_wm_latency(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3234
make_wm_latency_monotonic(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3244
increase_wm_latency(display, wm_read_latency(display));
drivers/gpu/drm/i915/display/skl_watermark.c
3252
if (need_16gb_dimm_wa(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3253
increase_wm_latency(display, 1);
drivers/gpu/drm/i915/display/skl_watermark.c
3256
static void mtl_read_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3258
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3261
val = intel_de_read(display, MTL_LATENCY_LP0_LP1);
drivers/gpu/drm/i915/display/skl_watermark.c
3265
val = intel_de_read(display, MTL_LATENCY_LP2_LP3);
drivers/gpu/drm/i915/display/skl_watermark.c
3269
val = intel_de_read(display, MTL_LATENCY_LP4_LP5);
drivers/gpu/drm/i915/display/skl_watermark.c
3274
static void skl_read_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3276
u16 *wm = display->wm.skl_latency;
drivers/gpu/drm/i915/display/skl_watermark.c
3282
ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
drivers/gpu/drm/i915/display/skl_watermark.c
3284
drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
drivers/gpu/drm/i915/display/skl_watermark.c
3295
ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
drivers/gpu/drm/i915/display/skl_watermark.c
3297
drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
drivers/gpu/drm/i915/display/skl_watermark.c
3307
static void skl_setup_wm_latency(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3309
if (HAS_HW_SAGV_WM(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3310
display->wm.num_levels = 6;
drivers/gpu/drm/i915/display/skl_watermark.c
3312
display->wm.num_levels = 8;
drivers/gpu/drm/i915/display/skl_watermark.c
3314
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/skl_watermark.c
3315
mtl_read_wm_latency(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3317
skl_read_wm_latency(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3319
intel_print_wm_latency(display, "original", display->wm.skl_latency);
drivers/gpu/drm/i915/display/skl_watermark.c
3321
adjust_wm_latency(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3323
intel_print_wm_latency(display, "adjusted", display->wm.skl_latency);
drivers/gpu/drm/i915/display/skl_watermark.c
3351
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3354
dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj);
drivers/gpu/drm/i915/display/skl_watermark.c
3361
int intel_dbuf_init(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3369
intel_atomic_global_obj_init(display, &display->dbuf.obj,
drivers/gpu/drm/i915/display/skl_watermark.c
3397
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
3400
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/skl_watermark.c
3403
if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/skl_watermark.c
3409
if (DISPLAY_VER(display) >= 14)
drivers/gpu/drm/i915/display/skl_watermark.c
3412
else if (intel_display_wa(display, INTEL_DISPLAY_WA_22010947358))
drivers/gpu/drm/i915/display/skl_watermark.c
3419
if (DISPLAY_VER(display) >= 14) {
drivers/gpu/drm/i915/display/skl_watermark.c
3421
} else if (display->platform.alderlake_p) {
drivers/gpu/drm/i915/display/skl_watermark.c
3424
} else if (DISPLAY_VER(display) >= 12) {
drivers/gpu/drm/i915/display/skl_watermark.c
3432
if (DISPLAY_VERx100(display) == 1400) {
drivers/gpu/drm/i915/display/skl_watermark.c
3442
static void pipe_mbus_dbox_ctl_update(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
3447
for_each_intel_crtc_in_pipe_mask(display, crtc, dbuf_state->active_pipes)
drivers/gpu/drm/i915/display/skl_watermark.c
3448
intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe),
drivers/gpu/drm/i915/display/skl_watermark.c
3454
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3457
if (DISPLAY_VER(display) < 11)
drivers/gpu/drm/i915/display/skl_watermark.c
3467
pipe_mbus_dbox_ctl_update(display, new_dbuf_state);
drivers/gpu/drm/i915/display/skl_watermark.c
3484
void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
3489
if (!HAS_MBUS_JOINING(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3492
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/skl_watermark.c
3493
intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
drivers/gpu/drm/i915/display/skl_watermark.c
3495
else if (DISPLAY_VER(display) >= 20)
drivers/gpu/drm/i915/display/skl_watermark.c
3496
intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
drivers/gpu/drm/i915/display/skl_watermark.c
3502
drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n",
drivers/gpu/drm/i915/display/skl_watermark.c
3505
for_each_dbuf_slice(display, slice)
drivers/gpu/drm/i915/display/skl_watermark.c
3506
if (DISPLAY_VER(display) >= 35)
drivers/gpu/drm/i915/display/skl_watermark.c
3507
intel_de_rmw(display, DBUF_CTL_S(slice),
drivers/gpu/drm/i915/display/skl_watermark.c
3511
intel_de_rmw(display, DBUF_CTL_S(slice),
drivers/gpu/drm/i915/display/skl_watermark.c
3518
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3533
intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio,
drivers/gpu/drm/i915/display/skl_watermark.c
3540
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3545
drm_WARN_ON(display->drm, !dbuf_state->joined_mbus);
drivers/gpu/drm/i915/display/skl_watermark.c
3546
drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes));
drivers/gpu/drm/i915/display/skl_watermark.c
3548
crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/skl_watermark.c
3557
static void mbus_ctl_join_update(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
3573
intel_de_rmw(display, MBUS_CTL,
drivers/gpu/drm/i915/display/skl_watermark.c
3581
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3587
drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",
drivers/gpu/drm/i915/display/skl_watermark.c
3592
mbus_ctl_join_update(display, new_dbuf_state, pipe);
drivers/gpu/drm/i915/display/skl_watermark.c
3618
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3637
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
drivers/gpu/drm/i915/display/skl_watermark.c
3653
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
366
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
3671
gen9_dbuf_slices_update(display, new_slices);
drivers/gpu/drm/i915/display/skl_watermark.c
3676
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
368
if (!display->sagv.block_time_us)
drivers/gpu/drm/i915/display/skl_watermark.c
3694
gen9_dbuf_slices_update(display, new_slices);
drivers/gpu/drm/i915/display/skl_watermark.c
3709
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
371
if (!display->params.enable_sagv)
drivers/gpu/drm/i915/display/skl_watermark.c
3719
if (DISPLAY_VER(display) < 30) {
drivers/gpu/drm/i915/display/skl_watermark.c
3729
static void skl_mbus_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3732
to_intel_dbuf_state(display->dbuf.obj.state);
drivers/gpu/drm/i915/display/skl_watermark.c
3734
if (!HAS_MBUS_JOINING(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3741
drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n",
drivers/gpu/drm/i915/display/skl_watermark.c
3745
intel_dbuf_mdclk_cdclk_ratio_update(display,
drivers/gpu/drm/i915/display/skl_watermark.c
3748
pipe_mbus_dbox_ctl_update(display, dbuf_state);
drivers/gpu/drm/i915/display/skl_watermark.c
3749
mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE);
drivers/gpu/drm/i915/display/skl_watermark.c
3752
static bool skl_dbuf_is_misconfigured(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3755
to_intel_dbuf_state(display->dbuf.obj.state);
drivers/gpu/drm/i915/display/skl_watermark.c
3759
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
3766
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
3784
static void skl_dbuf_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3799
if (!skl_dbuf_is_misconfigured(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3802
drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");
drivers/gpu/drm/i915/display/skl_watermark.c
3804
for_each_intel_crtc(display, crtc) {
drivers/gpu/drm/i915/display/skl_watermark.c
3814
drm_WARN_ON(display->drm, crtc_state->active_planes != 0);
drivers/gpu/drm/i915/display/skl_watermark.c
3820
static void skl_wm_sanitize(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3822
skl_mbus_sanitize(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3823
skl_dbuf_sanitize(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3828
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
3832
to_intel_dbuf_state(display->dbuf.obj.state);
drivers/gpu/drm/i915/display/skl_watermark.c
3835
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/skl_watermark.c
3851
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
3855
if (DISPLAY_VER(display) < 9)
drivers/gpu/drm/i915/display/skl_watermark.c
3875
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
388
if (HAS_SAGV_WM(display))
drivers/gpu/drm/i915/display/skl_watermark.c
3880
drm_err(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
3892
struct intel_display *display = to_intel_display(plane);
drivers/gpu/drm/i915/display/skl_watermark.c
3897
drm_err(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
3907
struct intel_display *display = to_intel_display(state);
drivers/gpu/drm/i915/display/skl_watermark.c
3922
if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active)
drivers/gpu/drm/i915/display/skl_watermark.c
3933
hw_enabled_slices = intel_enabled_dbuf_slices_mask(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3935
if (DISPLAY_VER(display) >= 11 &&
drivers/gpu/drm/i915/display/skl_watermark.c
3936
hw_enabled_slices != display->dbuf.enabled_slices)
drivers/gpu/drm/i915/display/skl_watermark.c
3937
drm_err(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
3939
display->dbuf.enabled_slices,
drivers/gpu/drm/i915/display/skl_watermark.c
3942
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
drivers/gpu/drm/i915/display/skl_watermark.c
3948
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
3962
if (HAS_HW_SAGV_WM(display)) {
drivers/gpu/drm/i915/display/skl_watermark.c
3990
void skl_wm_init(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
3992
intel_sagv_init(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3994
skl_setup_wm_latency(display);
drivers/gpu/drm/i915/display/skl_watermark.c
3996
display->wm.funcs = &skl_wm_funcs;
drivers/gpu/drm/i915/display/skl_watermark.c
4001
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/skl_watermark.c
4004
str_yes_no(skl_watermark_ipc_enabled(display)));
drivers/gpu/drm/i915/display/skl_watermark.c
4010
struct intel_display *display = inode->i_private;
drivers/gpu/drm/i915/display/skl_watermark.c
4012
return single_open(file, skl_watermark_ipc_status_show, display);
drivers/gpu/drm/i915/display/skl_watermark.c
4020
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/skl_watermark.c
4028
with_intel_display_rpm(display) {
drivers/gpu/drm/i915/display/skl_watermark.c
4029
if (!skl_watermark_ipc_enabled(display) && enable)
drivers/gpu/drm/i915/display/skl_watermark.c
403
static int intel_dbuf_slice_size(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
4030
drm_info(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
4032
display->wm.ipc_enabled = enable;
drivers/gpu/drm/i915/display/skl_watermark.c
4033
skl_watermark_ipc_update(display);
drivers/gpu/drm/i915/display/skl_watermark.c
405
return DISPLAY_INFO(display)->dbuf.size /
drivers/gpu/drm/i915/display/skl_watermark.c
4050
struct intel_display *display = m->private;
drivers/gpu/drm/i915/display/skl_watermark.c
4058
seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display)));
drivers/gpu/drm/i915/display/skl_watermark.c
406
hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);
drivers/gpu/drm/i915/display/skl_watermark.c
4060
str_enabled_disabled(display->params.enable_sagv));
drivers/gpu/drm/i915/display/skl_watermark.c
4061
seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]);
drivers/gpu/drm/i915/display/skl_watermark.c
4062
seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us);
drivers/gpu/drm/i915/display/skl_watermark.c
4069
void skl_watermark_debugfs_register(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
4071
struct dentry *debugfs_root = display->drm->debugfs_root;
drivers/gpu/drm/i915/display/skl_watermark.c
4073
if (HAS_IPC(display))
drivers/gpu/drm/i915/display/skl_watermark.c
4075
display, &skl_watermark_ipc_status_fops);
drivers/gpu/drm/i915/display/skl_watermark.c
4077
if (HAS_SAGV(display))
drivers/gpu/drm/i915/display/skl_watermark.c
4079
display, &intel_sagv_status_fops);
drivers/gpu/drm/i915/display/skl_watermark.c
4082
unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)
drivers/gpu/drm/i915/display/skl_watermark.c
4086
for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) {
drivers/gpu/drm/i915/display/skl_watermark.c
4087
unsigned int latency = skl_wm_latency(display, level, NULL);
drivers/gpu/drm/i915/display/skl_watermark.c
410
skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask,
drivers/gpu/drm/i915/display/skl_watermark.c
413
int slice_size = intel_dbuf_slice_size(display);
drivers/gpu/drm/i915/display/skl_watermark.c
425
WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size);
drivers/gpu/drm/i915/display/skl_watermark.c
428
static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)
drivers/gpu/drm/i915/display/skl_watermark.c
437
skl_ddb_entry_for_slices(display, slice_mask, &ddb);
drivers/gpu/drm/i915/display/skl_watermark.c
442
u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
445
int slice_size = intel_dbuf_slice_size(display);
drivers/gpu/drm/i915/display/skl_watermark.c
491
struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);
drivers/gpu/drm/i915/display/skl_watermark.c
498
for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/display/skl_watermark.c
524
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
546
skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices);
drivers/gpu/drm/i915/display/skl_watermark.c
547
mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask);
drivers/gpu/drm/i915/display/skl_watermark.c
581
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/skl_watermark.c
60
static void skl_sagv_disable(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.c
606
static unsigned int skl_wm_latency(struct intel_display *display, int level,
drivers/gpu/drm/i915/display/skl_watermark.c
609
unsigned int latency = display->wm.skl_latency[level];
drivers/gpu/drm/i915/display/skl_watermark.c
618
if ((display->platform.kabylake || display->platform.coffeelake ||
drivers/gpu/drm/i915/display/skl_watermark.c
619
display->platform.cometlake) && skl_watermark_ipc_enabled(display))
drivers/gpu/drm/i915/display/skl_watermark.c
622
if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled)
drivers/gpu/drm/i915/display/skl_watermark.c
632
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/skl_watermark.c
634
const struct drm_mode_config *mode_config = &display->drm->mode_config;
drivers/gpu/drm/i915/display/skl_watermark.c
646
info = drm_get_format_info(display->drm, format, modifier);
drivers/gpu/drm/i915/display/skl_watermark.c
651
drm_WARN_ON(display->drm, ret);
drivers/gpu/drm/i915/display/skl_watermark.c
653
for (level = 0; level < display->wm.num_levels; level++) {
drivers/gpu/drm/i915/display/skl_watermark.c
654
unsigned int latency = skl_wm_latency(display, level, &wp);
drivers/gpu/drm/i915/display/skl_watermark.c
676
skl_ddb_get_hw_plane_state(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.c
687
val = intel_de_read(display, CUR_BUF_CFG(pipe));
drivers/gpu/drm/i915/display/skl_watermark.c
692
val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
695
if (DISPLAY_VER(display) >= 30) {
drivers/gpu/drm/i915/display/skl_watermark.c
696
val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
702
if (DISPLAY_VER(display) >= 11)
drivers/gpu/drm/i915/display/skl_watermark.c
705
val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));
drivers/gpu/drm/i915/display/skl_watermark.c
714
struct intel_display *display = to_intel_display(crtc);
drivers/gpu/drm/i915/display/skl_watermark.c
721
wakeref = intel_display_power_get_if_enabled(display, power_domain);
drivers/gpu/drm/i915/display/skl_watermark.c
726
skl_ddb_get_hw_plane_state(display, pipe,
drivers/gpu/drm/i915/display/skl_watermark.c
733
intel_display_power_put(display, power_domain, wakeref);
drivers/gpu/drm/i915/display/skl_watermark.c
77
u8 intel_enabled_dbuf_slices_mask(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
82
for_each_dbuf_slice(display, slice) {
drivers/gpu/drm/i915/display/skl_watermark.c
83
if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
drivers/gpu/drm/i915/display/skl_watermark.c
94
static bool skl_needs_memory_bw_wa(struct intel_display *display)
drivers/gpu/drm/i915/display/skl_watermark.c
96
return DISPLAY_VER(display) == 9;
drivers/gpu/drm/i915/display/skl_watermark.h
23
u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
28
bool intel_has_sagv(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
30
u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.h
44
void skl_watermark_ipc_init(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
45
void skl_watermark_ipc_update(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
46
bool skl_watermark_ipc_enabled(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
47
void skl_watermark_debugfs_register(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
49
unsigned int skl_watermark_max_latency(struct intel_display *display,
drivers/gpu/drm/i915/display/skl_watermark.h
51
void skl_wm_init(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
68
int intel_dbuf_init(struct intel_display *display);
drivers/gpu/drm/i915/display/skl_watermark.h
74
void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_clock.c
21
struct intel_display *display = to_intel_display(drm);
drivers/gpu/drm/i915/display/vlv_clock.c
24
if (!display->vlv_clock.hpll_freq) {
drivers/gpu/drm/i915/display/vlv_clock.c
25
vlv_cck_get(display);
drivers/gpu/drm/i915/display/vlv_clock.c
27
hpll_freq = vlv_cck_read(display, CCK_FUSE_REG) &
drivers/gpu/drm/i915/display/vlv_clock.c
29
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_clock.c
31
display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000;
drivers/gpu/drm/i915/display/vlv_clock.c
33
drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq);
drivers/gpu/drm/i915/display/vlv_clock.c
36
return display->vlv_clock.hpll_freq;
drivers/gpu/drm/i915/display/vlv_clock.c
42
struct intel_display *display = to_intel_display(drm);
drivers/gpu/drm/i915/display/vlv_clock.c
46
vlv_cck_get(display);
drivers/gpu/drm/i915/display/vlv_clock.c
47
val = vlv_cck_read(display, reg);
drivers/gpu/drm/i915/display/vlv_clock.c
48
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_clock.c
68
struct intel_display *display = to_intel_display(drm);
drivers/gpu/drm/i915/display/vlv_clock.c
70
if (!display->vlv_clock.czclk_freq) {
drivers/gpu/drm/i915/display/vlv_clock.c
71
display->vlv_clock.czclk_freq = vlv_clock_get_cck(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
drivers/gpu/drm/i915/display/vlv_clock.c
73
drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);
drivers/gpu/drm/i915/display/vlv_clock.c
76
return display->vlv_clock.czclk_freq;
drivers/gpu/drm/i915/display/vlv_dsi.c
1004
intel_display_power_put(display, encoder->power_domain, wakeref);
drivers/gpu/drm/i915/display/vlv_dsi.c
101
static void write_data(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1012
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
1034
if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
drivers/gpu/drm/i915/display/vlv_dsi.c
1038
fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;
drivers/gpu/drm/i915/display/vlv_dsi.c
1050
intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1053
intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1056
intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1060
hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1066
hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1067
hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1084
vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1085
vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1086
vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1094
drm_WARN_ON(display->drm, adjusted_mode->crtc_vdisplay +
drivers/gpu/drm/i915/display/vlv_dsi.c
113
intel_de_write(display, reg, val);
drivers/gpu/drm/i915/display/vlv_dsi.c
117
static void read_data(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1177
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
1181
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
1185
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1217
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
124
u32 val = intel_de_read(display, reg);
drivers/gpu/drm/i915/display/vlv_dsi.c
1252
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1259
intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1261
intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1263
intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1267
intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1269
intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);
drivers/gpu/drm/i915/display/vlv_dsi.c
1273
intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1275
intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);
drivers/gpu/drm/i915/display/vlv_dsi.c
1278
intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);
drivers/gpu/drm/i915/display/vlv_dsi.c
1279
intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1281
intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);
drivers/gpu/drm/i915/display/vlv_dsi.c
1305
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
1314
drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));
drivers/gpu/drm/i915/display/vlv_dsi.c
1325
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1330
tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
drivers/gpu/drm/i915/display/vlv_dsi.c
1332
intel_de_write(display, MIPI_CTRL(display, PORT_A),
drivers/gpu/drm/i915/display/vlv_dsi.c
1336
tmp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
1338
intel_de_write(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1340
} else if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1343
intel_de_rmw(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1348
intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);
drivers/gpu/drm/i915/display/vlv_dsi.c
1349
intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);
drivers/gpu/drm/i915/display/vlv_dsi.c
1351
intel_de_write(display, MIPI_DPHY_PARAM(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1354
intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
136
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/vlv_dsi.c
1375
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1382
intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);
drivers/gpu/drm/i915/display/vlv_dsi.c
1403
intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1406
intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1409
intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1411
intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1413
intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1419
intel_de_write(display, MIPI_INIT_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1422
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/vlv_dsi.c
1430
intel_de_write(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
1431
MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),
drivers/gpu/drm/i915/display/vlv_dsi.c
1436
intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);
drivers/gpu/drm/i915/display/vlv_dsi.c
1439
intel_de_write(display, MIPI_INIT_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1447
intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1456
intel_de_write(display, MIPI_LP_BYTECLK(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1459
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1460
intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1463
intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1472
intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1475
intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1503
intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);
drivers/gpu/drm/i915/display/vlv_dsi.c
151
data_reg = MIPI_LP_GEN_DATA(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
1510
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
1514
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/vlv_dsi.c
1519
intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);
drivers/gpu/drm/i915/display/vlv_dsi.c
1521
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/vlv_dsi.c
1525
intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
drivers/gpu/drm/i915/display/vlv_dsi.c
1527
intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
1529
intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);
drivers/gpu/drm/i915/display/vlv_dsi.c
153
ctrl_reg = MIPI_LP_GEN_CTRL(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
1540
struct intel_display *display = to_intel_display(connector->dev);
drivers/gpu/drm/i915/display/vlv_dsi.c
1542
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/vlv_dsi.c
1545
status = intel_cpu_transcoder_mode_valid(display, mode);
drivers/gpu/drm/i915/display/vlv_dsi.c
156
data_reg = MIPI_HS_GEN_DATA(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
158
ctrl_reg = MIPI_HS_GEN_CTRL(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
1593
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/vlv_dsi.c
164
if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1642
mul = display->platform.geminilake ? 8 : 2;
drivers/gpu/drm/i915/display/vlv_dsi.c
1650
drm_dbg_kms(display->drm, "prepare count too high %u\n",
drivers/gpu/drm/i915/display/vlv_dsi.c
166
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
1671
drm_dbg_kms(display->drm, "exit zero count too high %u\n",
drivers/gpu/drm/i915/display/vlv_dsi.c
1682
drm_dbg_kms(display->drm, "clock zero count too high %u\n",
drivers/gpu/drm/i915/display/vlv_dsi.c
169
write_data(display, data_reg, packet.payload,
drivers/gpu/drm/i915/display/vlv_dsi.c
1692
drm_dbg_kms(display->drm, "trail count too high %u\n",
drivers/gpu/drm/i915/display/vlv_dsi.c
174
intel_de_write(display, MIPI_INTR_STAT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1758
struct intel_display *display = to_intel_display(crtc_state);
drivers/gpu/drm/i915/display/vlv_dsi.c
1767
if (display->platform.valleyview)
drivers/gpu/drm/i915/display/vlv_dsi.c
1775
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/vlv_dsi.c
178
if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
180
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
184
intel_de_write(display, ctrl_reg,
drivers/gpu/drm/i915/display/vlv_dsi.c
190
if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
1900
void vlv_dsi_init(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi.c
1910
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
1913
if (!intel_bios_is_dsi_present(display, &port))
drivers/gpu/drm/i915/display/vlv_dsi.c
1916
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/vlv_dsi.c
1917
display->dsi.mmio_base = BXT_MIPI_BASE;
drivers/gpu/drm/i915/display/vlv_dsi.c
1919
display->dsi.mmio_base = VLV_MIPI_BASE;
drivers/gpu/drm/i915/display/vlv_dsi.c
192
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
1934
drm_encoder_init(display->drm, &encoder->base, &intel_dsi_funcs,
drivers/gpu/drm/i915/display/vlv_dsi.c
1939
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/vlv_dsi.c
195
read_data(display, data_reg, msg->rx_buf, msg->rx_len);
drivers/gpu/drm/i915/display/vlv_dsi.c
1959
if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/vlv_dsi.c
1968
intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);
drivers/gpu/drm/i915/display/vlv_dsi.c
1975
if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
drivers/gpu/drm/i915/display/vlv_dsi.c
1978
if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
drivers/gpu/drm/i915/display/vlv_dsi.c
1994
drm_dbg_kms(display->drm, "no device found\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
2001
drm_dbg_kms(display->drm, "Calculated pclk %d GOP %d\n",
drivers/gpu/drm/i915/display/vlv_dsi.c
2005
drm_dbg_kms(display->drm, "Using GOP pclk\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
2017
drm_connector_init(display->drm, &connector->base, &intel_dsi_connector_funcs,
drivers/gpu/drm/i915/display/vlv_dsi.c
2026
mutex_lock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/vlv_dsi.c
2028
mutex_unlock(&display->drm->mode_config.mutex);
drivers/gpu/drm/i915/display/vlv_dsi.c
2031
drm_dbg_kms(display->drm, "no fixed mode\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
228
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/vlv_dsi.c
238
intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);
drivers/gpu/drm/i915/display/vlv_dsi.c
241
if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))
drivers/gpu/drm/i915/display/vlv_dsi.c
242
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
245
intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
drivers/gpu/drm/i915/display/vlv_dsi.c
248
if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port), mask, 100))
drivers/gpu/drm/i915/display/vlv_dsi.c
249
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
255
static void band_gap_reset(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi.c
257
vlv_flisdsi_get(display);
drivers/gpu/drm/i915/display/vlv_dsi.c
259
vlv_flisdsi_write(display, 0x08, 0x0001);
drivers/gpu/drm/i915/display/vlv_dsi.c
260
vlv_flisdsi_write(display, 0x0F, 0x0005);
drivers/gpu/drm/i915/display/vlv_dsi.c
261
vlv_flisdsi_write(display, 0x0F, 0x0025);
drivers/gpu/drm/i915/display/vlv_dsi.c
263
vlv_flisdsi_write(display, 0x0F, 0x0000);
drivers/gpu/drm/i915/display/vlv_dsi.c
264
vlv_flisdsi_write(display, 0x08, 0x0000);
drivers/gpu/drm/i915/display/vlv_dsi.c
266
vlv_flisdsi_put(display);
drivers/gpu/drm/i915/display/vlv_dsi.c
273
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
279
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
302
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
329
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
339
intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);
drivers/gpu/drm/i915/display/vlv_dsi.c
342
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
346
u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
348
intel_de_rmw(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
354
if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
356
drm_err(display->drm, "MIPIO port is powergated\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
362
!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);
drivers/gpu/drm/i915/display/vlv_dsi.c
370
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
376
if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
378
drm_err(display->drm, "PHY is not ON\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
382
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
drivers/gpu/drm/i915/display/vlv_dsi.c
386
if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {
drivers/gpu/drm/i915/display/vlv_dsi.c
387
intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
392
intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
396
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
398
drm_err(display->drm, "ULPS not active\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
401
intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
405
intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
409
intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
415
if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
417
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
423
if (intel_de_wait_for_set_ms(display, BXT_MIPI_PORT_CTRL(port),
drivers/gpu/drm/i915/display/vlv_dsi.c
425
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
432
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
437
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
441
intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
drivers/gpu/drm/i915/display/vlv_dsi.c
447
val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
449
intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
drivers/gpu/drm/i915/display/vlv_dsi.c
452
intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
drivers/gpu/drm/i915/display/vlv_dsi.c
458
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
462
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
464
vlv_flisdsi_get(display);
drivers/gpu/drm/i915/display/vlv_dsi.c
467
vlv_flisdsi_write(display, 0x04, 0x0004);
drivers/gpu/drm/i915/display/vlv_dsi.c
468
vlv_flisdsi_put(display);
drivers/gpu/drm/i915/display/vlv_dsi.c
471
band_gap_reset(display);
drivers/gpu/drm/i915/display/vlv_dsi.c
475
intel_de_write(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
483
intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
drivers/gpu/drm/i915/display/vlv_dsi.c
486
intel_de_write(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
490
intel_de_write(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
498
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
500
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/vlv_dsi.c
502
else if (display->platform.geminilake || display->platform.broxton)
drivers/gpu/drm/i915/display/vlv_dsi.c
510
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
516
intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
521
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
523
drm_err(display->drm, "PHY is not turning OFF\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
528
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
530
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi.c
537
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
542
intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
546
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
548
drm_err(display->drm, "PHY is not turning OFF\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
553
intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
562
static intel_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/vlv_dsi.c
564
return display->platform.geminilake || display->platform.broxton ?
drivers/gpu/drm/i915/display/vlv_dsi.c
570
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
574
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
577
intel_reg_t port_ctrl = display->platform.broxton ?
drivers/gpu/drm/i915/display/vlv_dsi.c
580
intel_de_write(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
584
intel_de_write(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
588
intel_de_write(display, MIPI_DEVICE_READY(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
596
if ((display->platform.broxton || port == PORT_A) &&
drivers/gpu/drm/i915/display/vlv_dsi.c
597
intel_de_wait_for_clear_ms(display, port_ctrl,
drivers/gpu/drm/i915/display/vlv_dsi.c
599
drm_err(display->drm, "DSI LP not going Low\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
602
intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
605
intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);
drivers/gpu/drm/i915/display/vlv_dsi.c
613
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
621
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
623
intel_de_rmw(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
627
intel_de_rmw(display, VLV_CHICKEN_3,
drivers/gpu/drm/i915/display/vlv_dsi.c
634
intel_reg_t port_ctrl = port_ctrl_reg(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
637
temp = intel_de_read(display, port_ctrl);
drivers/gpu/drm/i915/display/vlv_dsi.c
645
if (display->platform.broxton)
drivers/gpu/drm/i915/display/vlv_dsi.c
657
intel_de_write(display, port_ctrl, temp | DPI_ENABLE);
drivers/gpu/drm/i915/display/vlv_dsi.c
658
intel_de_posting_read(display, port_ctrl);
drivers/gpu/drm/i915/display/vlv_dsi.c
664
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
669
intel_reg_t port_ctrl = port_ctrl_reg(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
672
intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
673
intel_de_posting_read(display, port_ctrl);
drivers/gpu/drm/i915/display/vlv_dsi.c
727
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
734
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
738
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
drivers/gpu/drm/i915/display/vlv_dsi.c
744
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
752
if (display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
754
intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
drivers/gpu/drm/i915/display/vlv_dsi.c
757
intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
drivers/gpu/drm/i915/display/vlv_dsi.c
758
intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
761
if (display->platform.valleyview || display->platform.cherryview) {
drivers/gpu/drm/i915/display/vlv_dsi.c
763
intel_de_rmw(display, VLV_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/vlv_dsi.c
767
if (!display->platform.geminilake)
drivers/gpu/drm/i915/display/vlv_dsi.c
775
if (display->platform.geminilake) {
drivers/gpu/drm/i915/display/vlv_dsi.c
787
if (display->platform.geminilake && !glk_cold_boot)
drivers/gpu/drm/i915/display/vlv_dsi.c
799
intel_de_write(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
800
MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);
drivers/gpu/drm/i915/display/vlv_dsi.c
835
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
839
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
859
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
861
if (display->platform.geminilake)
drivers/gpu/drm/i915/display/vlv_dsi.c
872
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
876
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
878
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
90
struct intel_display *display = to_intel_display(&intel_dsi->base);
drivers/gpu/drm/i915/display/vlv_dsi.c
905
if (display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
907
intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
drivers/gpu/drm/i915/display/vlv_dsi.c
908
intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,
drivers/gpu/drm/i915/display/vlv_dsi.c
912
intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
drivers/gpu/drm/i915/display/vlv_dsi.c
915
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
920
intel_de_rmw(display, VLV_DSPCLK_GATE_D,
drivers/gpu/drm/i915/display/vlv_dsi.c
936
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi.c
942
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
944
wakeref = intel_display_power_get_if_enabled(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
954
if ((display->platform.geminilake || display->platform.broxton) &&
drivers/gpu/drm/i915/display/vlv_dsi.c
955
!bxt_dsi_pll_is_enabled(display))
drivers/gpu/drm/i915/display/vlv_dsi.c
96
if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port),
drivers/gpu/drm/i915/display/vlv_dsi.c
960
intel_reg_t port_ctrl = port_ctrl_reg(display, port);
drivers/gpu/drm/i915/display/vlv_dsi.c
961
bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
drivers/gpu/drm/i915/display/vlv_dsi.c
968
if ((display->platform.valleyview || display->platform.cherryview) &&
drivers/gpu/drm/i915/display/vlv_dsi.c
970
enabled = intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
971
TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
drivers/gpu/drm/i915/display/vlv_dsi.c
975
u32 tmp = intel_de_read(display,
drivers/gpu/drm/i915/display/vlv_dsi.c
976
MIPI_DSI_FUNC_PRG(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
98
drm_err(display->drm, "DPI FIFOs are not empty\n");
drivers/gpu/drm/i915/display/vlv_dsi.c
983
if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))
drivers/gpu/drm/i915/display/vlv_dsi.c
986
if (display->platform.geminilake || display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi.c
987
u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/vlv_dsi.c
991
if (drm_WARN_ON(display->drm, tmp > PIPE_C))
drivers/gpu/drm/i915/display/vlv_dsi.h
17
void vlv_dsi_init(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_dsi.h
26
static inline void vlv_dsi_init(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
121
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
127
int refclk = display->platform.cherryview ? 100000 : 25000;
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
150
drm_err(display->drm, "wrong P1 divisor\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
160
drm_err(display->drm, "wrong m_seed programmed\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
178
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
185
ret = dsi_calc_mnp(display, config, dsi_clk);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
187
drm_dbg_kms(display->drm, "dsi_calc_mnp failed\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
199
drm_dbg_kms(display->drm, "dsi pll div %08x, ctrl %08x\n",
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
216
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
220
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
222
vlv_cck_get(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
224
vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, 0);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
225
vlv_cck_write(display, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
226
vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
234
vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
236
ret = poll_timeout_us(val = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL),
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
240
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
241
drm_err(display->drm, "DSI PLL lock failed\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
244
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
246
drm_dbg_kms(display->drm, "DSI PLL locked\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
251
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
254
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
256
vlv_cck_get(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
258
tmp = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
261
vlv_cck_write(display, CCK_REG_DSI_PLL_CONTROL, tmp);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
263
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
266
static bool has_dsic_clock(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
268
return display->platform.broxton;
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
271
bool bxt_dsi_pll_is_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
278
val = intel_de_read(display, BXT_DSI_PLL_ENABLE);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
292
val = intel_de_read(display, BXT_DSI_PLL_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
293
if (!has_dsic_clock(display)) {
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
295
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
301
drm_dbg_kms(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
312
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
314
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
316
intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
322
if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
324
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
331
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
334
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
336
vlv_cck_get(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
337
pll_ctl = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
338
pll_div = vlv_cck_read(display, CCK_REG_DSI_PLL_DIVIDER);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
339
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
363
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
366
config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
367
if (!has_dsic_clock(display))
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
372
drm_dbg_kms(display->drm, "Calculated pclk=%u\n", pclk);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
378
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
382
temp = intel_de_read(display, MIPI_CTRL(display, port));
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
384
intel_de_write(display, MIPI_CTRL(display, port),
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
388
static void glk_dsi_program_esc_clock(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
427
intel_de_write(display, MIPIO_TXESC_CLK_DIV1,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
429
intel_de_write(display, MIPIO_TXESC_CLK_DIV2,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
434
static void bxt_dsi_program_clocks(struct intel_display *display, enum port port,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
447
tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
483
intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
489
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
505
if (display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
514
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
518
drm_dbg_kms(display->drm, "DSI PLL calculation is Done!!\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
526
if (has_dsic_clock(display))
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
532
if (display->platform.broxton && dsi_ratio <= 50)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
549
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
553
drm_dbg_kms(display->drm, "\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
556
intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
557
intel_de_posting_read(display, BXT_DSI_PLL_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
560
if (display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
562
bxt_dsi_program_clocks(display, port, config);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
564
glk_dsi_program_esc_clock(display, config);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
568
intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
571
if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
573
drm_err(display->drm,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
578
drm_dbg_kms(display->drm, "DSI PLL locked\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
583
struct intel_display *display = to_intel_display(encoder);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
587
if (display->platform.broxton) {
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
588
tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
593
intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
595
intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
597
intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
599
intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
602
static void assert_dsi_pll(struct intel_display *display, bool state)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
606
vlv_cck_get(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
607
cur_state = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
608
vlv_cck_put(display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
610
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
615
void assert_dsi_pll_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
617
assert_dsi_pll(display, true);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
62
static int dsi_calc_mnp(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
620
void assert_dsi_pll_disabled(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
622
assert_dsi_pll(display, false);
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
73
drm_err(display->drm, "DSI CLK Out of Range\n");
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
77
if (display->platform.cherryview) {
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
35
bool bxt_dsi_pll_is_enabled(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
36
void assert_dsi_pll_enabled(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
37
void assert_dsi_pll_disabled(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
39
static inline bool bxt_dsi_pll_is_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
43
static inline void assert_dsi_pll_enabled(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_pll.h
47
static inline void assert_dsi_pll_disabled(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
107
#define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
110
#define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
14
#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
146
#define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
169
#define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
174
#define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
179
#define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
184
#define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
189
#define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
197
#define MIPI_DBI_FIFO_THROTTLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
205
#define MIPI_HSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
209
#define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
213
#define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
217
#define MIPI_HACTIVE_AREA_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
221
#define MIPI_VSYNC_PADDING_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
225
#define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
229
#define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
233
#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
237
#define MIPI_DPI_CONTROL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
248
#define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
254
#define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
260
#define MIPI_MAX_RETURN_PKT_SIZE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
266
#define MIPI_VIDEO_MODE_FORMAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
276
#define MIPI_EOT_DISABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
290
#define MIPI_LP_BYTECLK(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
296
#define MIPI_TLPX_TIME_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
300
#define MIPI_CLK_LANE_TIMING(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
305
#define MIPI_LP_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
310
#define MIPI_HS_GEN_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
314
#define MIPI_LP_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
317
#define MIPI_HS_GEN_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
330
#define MIPI_GEN_FIFO_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
348
#define MIPI_HS_LP_DBI_ENABLE(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
355
#define MIPI_DPHY_PARAM(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
367
#define MIPI_DBI_BW_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
371
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
379
#define MIPI_STOP_STATE_STALL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
385
#define MIPI_INTR_STAT_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
388
#define MIPI_INTR_EN_REG_1(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
392
#define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
407
#define MIPI_CTRL(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
440
#define MIPI_DATA_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
447
#define MIPI_DATA_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
453
#define MIPI_COMMAND_ADDRESS(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
462
#define MIPI_COMMAND_LENGTH(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
468
#define MIPI_READ_DATA_RETURN(display, port, n) _MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
472
#define MIPI_READ_DATA_VALID(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
97
#define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
drivers/gpu/drm/i915/display/vlv_sideband.c
101
drm_WARN(display->drm, val == 0xffffffff,
drivers/gpu/drm/i915/display/vlv_sideband.c
108
void vlv_dpio_write(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_sideband.c
111
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);
drivers/gpu/drm/i915/display/vlv_sideband.c
113
intel_parent_vlv_iosf_write(display, unit, reg, val);
drivers/gpu/drm/i915/display/vlv_sideband.c
116
void vlv_dpio_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
118
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
drivers/gpu/drm/i915/display/vlv_sideband.c
12
void vlv_bunit_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
121
void vlv_flisdsi_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
123
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_FLISDSI));
drivers/gpu/drm/i915/display/vlv_sideband.c
126
u32 vlv_flisdsi_read(struct intel_display *display, u32 reg)
drivers/gpu/drm/i915/display/vlv_sideband.c
128
return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_FLISDSI, reg);
drivers/gpu/drm/i915/display/vlv_sideband.c
131
void vlv_flisdsi_write(struct intel_display *display, u32 reg, u32 val)
drivers/gpu/drm/i915/display/vlv_sideband.c
133
intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_FLISDSI, reg, val);
drivers/gpu/drm/i915/display/vlv_sideband.c
136
void vlv_flisdsi_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
138
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_FLISDSI));
drivers/gpu/drm/i915/display/vlv_sideband.c
14
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_BUNIT));
drivers/gpu/drm/i915/display/vlv_sideband.c
141
void vlv_nc_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
143
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_NC));
drivers/gpu/drm/i915/display/vlv_sideband.c
146
u32 vlv_nc_read(struct intel_display *display, u8 addr)
drivers/gpu/drm/i915/display/vlv_sideband.c
148
return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_NC, addr);
drivers/gpu/drm/i915/display/vlv_sideband.c
151
void vlv_nc_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
153
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_NC));
drivers/gpu/drm/i915/display/vlv_sideband.c
156
void vlv_punit_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
158
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_PUNIT));
drivers/gpu/drm/i915/display/vlv_sideband.c
161
u32 vlv_punit_read(struct intel_display *display, u32 addr)
drivers/gpu/drm/i915/display/vlv_sideband.c
163
return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_PUNIT, addr);
drivers/gpu/drm/i915/display/vlv_sideband.c
166
int vlv_punit_write(struct intel_display *display, u32 addr, u32 val)
drivers/gpu/drm/i915/display/vlv_sideband.c
168
return intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_PUNIT, addr, val);
drivers/gpu/drm/i915/display/vlv_sideband.c
17
u32 vlv_bunit_read(struct intel_display *display, u32 reg)
drivers/gpu/drm/i915/display/vlv_sideband.c
171
void vlv_punit_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
173
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_PUNIT));
drivers/gpu/drm/i915/display/vlv_sideband.c
19
return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_BUNIT, reg);
drivers/gpu/drm/i915/display/vlv_sideband.c
22
void vlv_bunit_write(struct intel_display *display, u32 reg, u32 val)
drivers/gpu/drm/i915/display/vlv_sideband.c
24
intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_BUNIT, reg, val);
drivers/gpu/drm/i915/display/vlv_sideband.c
27
void vlv_bunit_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
29
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_BUNIT));
drivers/gpu/drm/i915/display/vlv_sideband.c
32
void vlv_cck_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
34
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_CCK));
drivers/gpu/drm/i915/display/vlv_sideband.c
37
u32 vlv_cck_read(struct intel_display *display, u32 reg)
drivers/gpu/drm/i915/display/vlv_sideband.c
39
return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_CCK, reg);
drivers/gpu/drm/i915/display/vlv_sideband.c
42
void vlv_cck_write(struct intel_display *display, u32 reg, u32 val)
drivers/gpu/drm/i915/display/vlv_sideband.c
44
intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_CCK, reg, val);
drivers/gpu/drm/i915/display/vlv_sideband.c
47
void vlv_cck_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
49
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_CCK));
drivers/gpu/drm/i915/display/vlv_sideband.c
52
void vlv_ccu_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
54
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_CCU));
drivers/gpu/drm/i915/display/vlv_sideband.c
57
u32 vlv_ccu_read(struct intel_display *display, u32 reg)
drivers/gpu/drm/i915/display/vlv_sideband.c
59
return intel_parent_vlv_iosf_read(display, VLV_IOSF_SB_CCU, reg);
drivers/gpu/drm/i915/display/vlv_sideband.c
62
void vlv_ccu_write(struct intel_display *display, u32 reg, u32 val)
drivers/gpu/drm/i915/display/vlv_sideband.c
64
intel_parent_vlv_iosf_write(display, VLV_IOSF_SB_CCU, reg, val);
drivers/gpu/drm/i915/display/vlv_sideband.c
67
void vlv_ccu_put(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
69
intel_parent_vlv_iosf_put(display, BIT(VLV_IOSF_SB_CCU));
drivers/gpu/drm/i915/display/vlv_sideband.c
72
void vlv_dpio_get(struct intel_display *display)
drivers/gpu/drm/i915/display/vlv_sideband.c
74
intel_parent_vlv_iosf_get(display, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
drivers/gpu/drm/i915/display/vlv_sideband.c
77
static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display,
drivers/gpu/drm/i915/display/vlv_sideband.c
84
if (display->platform.cherryview)
drivers/gpu/drm/i915/display/vlv_sideband.c
90
u32 vlv_dpio_read(struct intel_display *display, enum dpio_phy phy, int reg)
drivers/gpu/drm/i915/display/vlv_sideband.c
92
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);
drivers/gpu/drm/i915/display/vlv_sideband.c
95
val = intel_parent_vlv_iosf_read(display, unit, reg);
drivers/gpu/drm/i915/display/vlv_sideband.h
14
void vlv_bunit_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
15
u32 vlv_bunit_read(struct intel_display *display, u32 reg);
drivers/gpu/drm/i915/display/vlv_sideband.h
16
void vlv_bunit_write(struct intel_display *display, u32 reg, u32 val);
drivers/gpu/drm/i915/display/vlv_sideband.h
17
void vlv_bunit_put(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
19
void vlv_cck_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
20
u32 vlv_cck_read(struct intel_display *display, u32 reg);
drivers/gpu/drm/i915/display/vlv_sideband.h
21
void vlv_cck_write(struct intel_display *display, u32 reg, u32 val);
drivers/gpu/drm/i915/display/vlv_sideband.h
22
void vlv_cck_put(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
24
void vlv_ccu_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
25
u32 vlv_ccu_read(struct intel_display *display, u32 reg);
drivers/gpu/drm/i915/display/vlv_sideband.h
26
void vlv_ccu_write(struct intel_display *display, u32 reg, u32 val);
drivers/gpu/drm/i915/display/vlv_sideband.h
27
void vlv_ccu_put(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
29
void vlv_dpio_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
30
u32 vlv_dpio_read(struct intel_display *display, enum dpio_phy phy, int reg);
drivers/gpu/drm/i915/display/vlv_sideband.h
31
void vlv_dpio_write(struct intel_display *display, enum dpio_phy phy, int reg, u32 val);
drivers/gpu/drm/i915/display/vlv_sideband.h
32
void vlv_dpio_put(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
34
void vlv_flisdsi_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
35
u32 vlv_flisdsi_read(struct intel_display *display, u32 reg);
drivers/gpu/drm/i915/display/vlv_sideband.h
36
void vlv_flisdsi_write(struct intel_display *display, u32 reg, u32 val);
drivers/gpu/drm/i915/display/vlv_sideband.h
37
void vlv_flisdsi_put(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
39
void vlv_nc_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
40
u32 vlv_nc_read(struct intel_display *display, u8 addr);
drivers/gpu/drm/i915/display/vlv_sideband.h
41
void vlv_nc_put(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
43
void vlv_punit_get(struct intel_display *display);
drivers/gpu/drm/i915/display/vlv_sideband.h
44
u32 vlv_punit_read(struct intel_display *display, u32 addr);
drivers/gpu/drm/i915/display/vlv_sideband.h
45
int vlv_punit_write(struct intel_display *display, u32 addr, u32 val);
drivers/gpu/drm/i915/display/vlv_sideband.h
46
void vlv_punit_put(struct intel_display *display);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
115
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
127
return intel_display_device_present(display);
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
334
struct intel_display *display = ggtt->vm.i915->display;
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
360
if (intel_has_pending_fb_unpin(display))
drivers/gpu/drm/i915/gt/intel_gt_pm.c
109
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gt/intel_gt_pm.c
127
intel_display_power_put_async(display, POWER_DOMAIN_GT_IRQ, wakeref);
drivers/gpu/drm/i915/gt/intel_gt_pm.c
75
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gt/intel_gt_pm.c
90
gt->awake = intel_display_power_get(display, POWER_DOMAIN_GT_IRQ);
drivers/gpu/drm/i915/gt/intel_reset.c
1209
struct intel_display *display = gt->i915->display;
drivers/gpu/drm/i915/gt/intel_reset.c
1255
intel_overlay_reset(display);
drivers/gpu/drm/i915/gt/intel_reset.c
1422
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gt/intel_reset.c
1427
intel_display_reset_supported(display) &&
drivers/gpu/drm/i915/gt/intel_reset.c
1432
intel_display_reset_test(display) ||
drivers/gpu/drm/i915/gt/intel_reset.c
1443
intel_display_reset_prepare(display);
drivers/gpu/drm/i915/gt/intel_reset.c
1449
intel_display_reset_finish(display, !need_display_reset);
drivers/gpu/drm/i915/gt/intel_reset.c
1514
if (!intel_display_reset_test(gt->i915->display) &&
drivers/gpu/drm/i915/gt/intel_reset.c
971
struct intel_display *display = gt->i915->display;
drivers/gpu/drm/i915/gt/intel_reset.c
990
!intel_display_reset_test(display))
drivers/gpu/drm/i915/gt/intel_rps.c
562
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gt/intel_rps.c
620
ilk_display_rps_enable(display);
drivers/gpu/drm/i915/gt/intel_rps.c
632
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gt/intel_rps.c
638
ilk_display_rps_disable(display);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1296
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1325
info->ctrl_reg = DSPCNTR(display, info->pipe);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1326
info->stride_reg = DSPSTRIDE(display, info->pipe);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1327
info->surf_reg = DSPSURF(display, info->pipe);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1343
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1392
info->ctrl_reg = DSPCNTR(display, info->pipe);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1393
info->stride_reg = DSPSTRIDE(display, info->pipe);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1394
info->surf_reg = DSPSURF(display, info->pipe);
drivers/gpu/drm/i915/gvt/cmd_parser.c
1431
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1449
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;
drivers/gpu/drm/i915/gvt/display.c
189
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/display.c
202
gvt_for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/gvt/display.c
203
vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=
drivers/gpu/drm/i915/gvt/display.c
205
vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
drivers/gpu/drm/i915/gvt/display.c
207
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
drivers/gpu/drm/i915/gvt/display.c
208
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
drivers/gpu/drm/i915/gvt/display.c
212
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=
drivers/gpu/drm/i915/gvt/display.c
216
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
drivers/gpu/drm/i915/gvt/display.c
264
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
drivers/gpu/drm/i915/gvt/display.c
265
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
drivers/gpu/drm/i915/gvt/display.c
273
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
drivers/gpu/drm/i915/gvt/display.c
274
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
drivers/gpu/drm/i915/gvt/display.c
275
vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
drivers/gpu/drm/i915/gvt/display.c
276
vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
drivers/gpu/drm/i915/gvt/display.c
277
vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
drivers/gpu/drm/i915/gvt/display.c
300
TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |=
drivers/gpu/drm/i915/gvt/display.c
330
TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
drivers/gpu/drm/i915/gvt/display.c
361
TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
drivers/gpu/drm/i915/gvt/display.c
410
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
drivers/gpu/drm/i915/gvt/display.c
411
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
drivers/gpu/drm/i915/gvt/display.c
412
vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
drivers/gpu/drm/i915/gvt/display.c
413
vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
drivers/gpu/drm/i915/gvt/display.c
414
vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
drivers/gpu/drm/i915/gvt/display.c
425
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
drivers/gpu/drm/i915/gvt/display.c
428
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
drivers/gpu/drm/i915/gvt/display.c
451
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
drivers/gpu/drm/i915/gvt/display.c
454
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
drivers/gpu/drm/i915/gvt/display.c
477
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
drivers/gpu/drm/i915/gvt/display.c
480
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
drivers/gpu/drm/i915/gvt/display.c
518
gvt_for_each_pipe(display, pipe) {
drivers/gpu/drm/i915/gvt/display.c
519
vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
drivers/gpu/drm/i915/gvt/display.c
521
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
drivers/gpu/drm/i915/gvt/display.c
522
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
drivers/gpu/drm/i915/gvt/display.c
525
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
drivers/gpu/drm/i915/gvt/display.c
584
vgpu->display.port_num = port_num;
drivers/gpu/drm/i915/gvt/display.c
610
intel_vgpu_port(vgpu, vgpu->display.port_num);
drivers/gpu/drm/i915/gvt/display.c
640
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/display.c
662
vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;
drivers/gpu/drm/i915/gvt/display.c
670
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/gvt/display.c
674
gvt_for_each_pipe(display, pipe)
drivers/gpu/drm/i915/gvt/display.c
75
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/display.c
77
if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
drivers/gpu/drm/i915/gvt/display.c
88
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/display.c
94
if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
drivers/gpu/drm/i915/gvt/display.h
48
(&(vgpu->display.ports[port]))
drivers/gpu/drm/i915/gvt/display_helpers.h
11
#define DISPLAY_MMIO_BASE(display) \
drivers/gpu/drm/i915/gvt/display_helpers.h
12
intel_display_device_mmio_base((display))
drivers/gpu/drm/i915/gvt/display_helpers.h
24
#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, idx) \
drivers/gpu/drm/i915/gvt/display_helpers.h
25
intel_display_device_pipe_offset((display), (enum pipe)(idx))
drivers/gpu/drm/i915/gvt/display_helpers.h
27
#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \
drivers/gpu/drm/i915/gvt/display_helpers.h
28
intel_display_device_trans_offset((display), (trans))
drivers/gpu/drm/i915/gvt/display_helpers.h
30
#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \
drivers/gpu/drm/i915/gvt/display_helpers.h
31
intel_display_device_cursor_offset((display), (pipe))
drivers/gpu/drm/i915/gvt/display_helpers.h
33
#define gvt_for_each_pipe(display, __p) \
drivers/gpu/drm/i915/gvt/display_helpers.h
35
for_each_if(intel_display_device_pipe_valid((display), (__p)))
drivers/gpu/drm/i915/gvt/edid.c
137
if (!vgpu->display.i2c_edid.edid_available)
drivers/gpu/drm/i915/gvt/edid.c
139
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
167
vgpu->display.i2c_edid.state = I2C_GMBUS;
drivers/gpu/drm/i915/gvt/edid.c
168
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
175
vgpu->display.i2c_edid.port = port;
drivers/gpu/drm/i915/gvt/edid.c
176
vgpu->display.i2c_edid.edid_available = true;
drivers/gpu/drm/i915/gvt/edid.c
186
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
drivers/gpu/drm/i915/gvt/edid.c
298
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
drivers/gpu/drm/i915/gvt/edid.c
487
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
drivers/gpu/drm/i915/gvt/edid.c
572
struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
drivers/gpu/drm/i915/gvt/edid.c
59
struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
drivers/gpu/drm/i915/gvt/fb_decoder.c
159
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/fb_decoder.c
161
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;
drivers/gpu/drm/i915/gvt/fb_decoder.c
216
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/fb_decoder.c
224
val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));
drivers/gpu/drm/i915/gvt/fb_decoder.c
258
plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;
drivers/gpu/drm/i915/gvt/fb_decoder.c
274
plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>
drivers/gpu/drm/i915/gvt/fb_decoder.c
277
plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &
drivers/gpu/drm/i915/gvt/fb_decoder.c
281
val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));
drivers/gpu/drm/i915/gvt/fb_decoder.c
347
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/fb_decoder.c
356
val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));
drivers/gpu/drm/i915/gvt/fb_decoder.c
382
plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;
drivers/gpu/drm/i915/gvt/fb_decoder.c
393
val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));
drivers/gpu/drm/i915/gvt/gvt.h
206
struct intel_vgpu_display display;
drivers/gpu/drm/i915/gvt/handlers.c
1026
#define DSPSURF_TO_PIPE(display, offset) \
drivers/gpu/drm/i915/gvt/handlers.c
1027
calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
drivers/gpu/drm/i915/gvt/handlers.c
1033
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/handlers.c
1034
u32 pipe = DSPSURF_TO_PIPE(display, offset);
drivers/gpu/drm/i915/gvt/handlers.c
1038
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
drivers/gpu/drm/i915/gvt/handlers.c
1040
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
drivers/gpu/drm/i915/gvt/handlers.c
1042
if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)
drivers/gpu/drm/i915/gvt/handlers.c
1075
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/handlers.c
1082
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
drivers/gpu/drm/i915/gvt/handlers.c
1083
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
drivers/gpu/drm/i915/gvt/handlers.c
1189
struct intel_vgpu_display *display = &vgpu->display;
drivers/gpu/drm/i915/gvt/handlers.c
1222
port = &display->ports[port_index];
drivers/gpu/drm/i915/gvt/handlers.c
1382
struct intel_vgpu_display *display = &vgpu->display;
drivers/gpu/drm/i915/gvt/handlers.c
1383
int num = display->sbi.number;
drivers/gpu/drm/i915/gvt/handlers.c
1387
if (display->sbi.registers[i].offset == sbi_offset)
drivers/gpu/drm/i915/gvt/handlers.c
1393
return display->sbi.registers[i].value;
drivers/gpu/drm/i915/gvt/handlers.c
1399
struct intel_vgpu_display *display = &vgpu->display;
drivers/gpu/drm/i915/gvt/handlers.c
1400
int num = display->sbi.number;
drivers/gpu/drm/i915/gvt/handlers.c
1404
if (display->sbi.registers[i].offset == offset)
drivers/gpu/drm/i915/gvt/handlers.c
1413
display->sbi.number++;
drivers/gpu/drm/i915/gvt/handlers.c
1416
display->sbi.registers[i].offset = offset;
drivers/gpu/drm/i915/gvt/handlers.c
1417
display->sbi.registers[i].value = value;
drivers/gpu/drm/i915/gvt/handlers.c
2210
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/handlers.c
2299
MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,
drivers/gpu/drm/i915/gvt/handlers.c
2301
MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,
drivers/gpu/drm/i915/gvt/handlers.c
2303
MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,
drivers/gpu/drm/i915/gvt/handlers.c
2305
MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,
drivers/gpu/drm/i915/gvt/handlers.c
2307
MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
drivers/gpu/drm/i915/gvt/handlers.c
2310
MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
drivers/gpu/drm/i915/gvt/handlers.c
2313
MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
drivers/gpu/drm/i915/gvt/handlers.c
669
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/gvt/handlers.c
674
port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &
drivers/gpu/drm/i915/gvt/handlers.c
690
link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));
drivers/gpu/drm/i915/gvt/handlers.c
691
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));
drivers/gpu/drm/i915/gvt/handlers.c
694
htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
drivers/gpu/drm/i915/gvt/handlers.c
695
vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
drivers/gpu/drm/i915/gvt/handlers.c
700
u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);
drivers/gpu/drm/i915/i915_driver.c
1042
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_driver.c
1046
intel_display_power_disable(display);
drivers/gpu/drm/i915/i915_driver.c
1049
if (intel_display_device_present(display)) {
drivers/gpu/drm/i915/i915_driver.c
1051
intel_display_driver_disable_user_access(display);
drivers/gpu/drm/i915/i915_driver.c
1056
intel_dp_mst_suspend(display);
drivers/gpu/drm/i915/i915_driver.c
1059
intel_hpd_cancel_work(display);
drivers/gpu/drm/i915/i915_driver.c
1061
if (intel_display_device_present(display))
drivers/gpu/drm/i915/i915_driver.c
1062
intel_display_driver_suspend_access(display);
drivers/gpu/drm/i915/i915_driver.c
1064
intel_encoder_suspend_all(display);
drivers/gpu/drm/i915/i915_driver.c
1065
intel_encoder_shutdown_all(display);
drivers/gpu/drm/i915/i915_driver.c
1067
intel_dmc_suspend(display);
drivers/gpu/drm/i915/i915_driver.c
1082
intel_display_power_driver_remove(display);
drivers/gpu/drm/i915/i915_driver.c
1122
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
1129
intel_display_power_disable(display);
drivers/gpu/drm/i915/i915_driver.c
1131
if (intel_display_device_present(display)) {
drivers/gpu/drm/i915/i915_driver.c
1133
intel_display_driver_disable_user_access(display);
drivers/gpu/drm/i915/i915_driver.c
1136
intel_display_driver_suspend(display);
drivers/gpu/drm/i915/i915_driver.c
1139
intel_hpd_cancel_work(display);
drivers/gpu/drm/i915/i915_driver.c
1141
if (intel_display_device_present(display))
drivers/gpu/drm/i915/i915_driver.c
1142
intel_display_driver_suspend_access(display);
drivers/gpu/drm/i915/i915_driver.c
1144
intel_encoder_suspend_all(display);
drivers/gpu/drm/i915/i915_driver.c
1147
intel_dpt_suspend(display);
drivers/gpu/drm/i915/i915_driver.c
1150
i9xx_display_sr_save(display);
drivers/gpu/drm/i915/i915_driver.c
1153
intel_opregion_suspend(display, opregion_target_state);
drivers/gpu/drm/i915/i915_driver.c
1157
intel_dmc_suspend(display);
drivers/gpu/drm/i915/i915_driver.c
1169
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
1184
intel_display_power_suspend_late(display, s2idle);
drivers/gpu/drm/i915/i915_driver.c
1189
intel_display_power_resume_early(display);
drivers/gpu/drm/i915/i915_driver.c
1256
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
1279
intel_dpt_resume(display);
drivers/gpu/drm/i915/i915_driver.c
1281
intel_dmc_resume(display);
drivers/gpu/drm/i915/i915_driver.c
1283
i9xx_display_sr_restore(display);
drivers/gpu/drm/i915/i915_driver.c
1285
intel_gmbus_reset(display);
drivers/gpu/drm/i915/i915_driver.c
1287
intel_pps_unlock_regs_wa(display);
drivers/gpu/drm/i915/i915_driver.c
1289
intel_init_pch_refclk(display);
drivers/gpu/drm/i915/i915_driver.c
1303
if (intel_display_device_present(display))
drivers/gpu/drm/i915/i915_driver.c
1308
intel_display_driver_init_hw(display);
drivers/gpu/drm/i915/i915_driver.c
1312
if (intel_display_device_present(display))
drivers/gpu/drm/i915/i915_driver.c
1313
intel_display_driver_resume_access(display);
drivers/gpu/drm/i915/i915_driver.c
1315
intel_hpd_init(display);
drivers/gpu/drm/i915/i915_driver.c
1317
intel_display_driver_resume(display);
drivers/gpu/drm/i915/i915_driver.c
1319
if (intel_display_device_present(display)) {
drivers/gpu/drm/i915/i915_driver.c
1320
intel_display_driver_enable_user_access(display);
drivers/gpu/drm/i915/i915_driver.c
1323
intel_hpd_poll_disable(display);
drivers/gpu/drm/i915/i915_driver.c
1325
intel_opregion_resume(display);
drivers/gpu/drm/i915/i915_driver.c
1329
intel_display_power_enable(display);
drivers/gpu/drm/i915/i915_driver.c
1341
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
1365
intel_display_power_resume_early(display);
drivers/gpu/drm/i915/i915_driver.c
1564
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
1594
intel_display_power_runtime_suspend(display);
drivers/gpu/drm/i915/i915_driver.c
1639
intel_opregion_notify_adapter(display, PCI_D3hot);
drivers/gpu/drm/i915/i915_driver.c
1648
intel_opregion_notify_adapter(display, PCI_D1);
drivers/gpu/drm/i915/i915_driver.c
1654
intel_hpd_poll_enable(display);
drivers/gpu/drm/i915/i915_driver.c
1663
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
1678
intel_opregion_notify_adapter(display, PCI_D0);
drivers/gpu/drm/i915/i915_driver.c
1688
intel_display_power_runtime_resume(display);
drivers/gpu/drm/i915/i915_driver.c
1712
intel_hpd_init(display);
drivers/gpu/drm/i915/i915_driver.c
1713
intel_hpd_poll_disable(display);
drivers/gpu/drm/i915/i915_driver.c
1716
skl_watermark_ipc_update(display);
drivers/gpu/drm/i915/i915_driver.c
236
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
247
intel_sbi_init(display);
drivers/gpu/drm/i915/i915_driver.c
273
intel_display_driver_early_probe(display);
drivers/gpu/drm/i915/i915_driver.c
297
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
300
intel_display_power_cleanup(display);
drivers/gpu/drm/i915/i915_driver.c
309
intel_sbi_fini(display);
drivers/gpu/drm/i915/i915_driver.c
313
intel_display_device_remove(display);
drivers/gpu/drm/i915/i915_driver.c
314
dev_priv->display = NULL;
drivers/gpu/drm/i915/i915_driver.c
328
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
351
intel_display_device_info_runtime_init(display);
drivers/gpu/drm/i915/i915_driver.c
473
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
567
intel_opregion_setup(display);
drivers/gpu/drm/i915/i915_driver.c
577
ret = intel_dram_detect(display);
drivers/gpu/drm/i915/i915_driver.c
581
intel_bw_init_hw(display);
drivers/gpu/drm/i915/i915_driver.c
586
intel_opregion_cleanup(display);
drivers/gpu/drm/i915/i915_driver.c
607
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
612
intel_opregion_cleanup(display);
drivers/gpu/drm/i915/i915_driver.c
627
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
661
intel_display_driver_register(display);
drivers/gpu/drm/i915/i915_driver.c
663
intel_display_power_enable(display);
drivers/gpu/drm/i915/i915_driver.c
678
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_driver.c
685
intel_display_power_disable(display);
drivers/gpu/drm/i915/i915_driver.c
687
intel_display_driver_unregister(display);
drivers/gpu/drm/i915/i915_driver.c
798
INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct drm_i915_private, drm, display);
drivers/gpu/drm/i915/i915_driver.c
806
struct intel_display *display;
drivers/gpu/drm/i915/i915_driver.c
821
display = intel_display_device_probe(pdev, &parent);
drivers/gpu/drm/i915/i915_driver.c
822
if (IS_ERR(display))
drivers/gpu/drm/i915/i915_driver.c
823
return ERR_CAST(display);
drivers/gpu/drm/i915/i915_driver.c
825
i915->display = display;
drivers/gpu/drm/i915/i915_driver.c
844
struct intel_display *display;
drivers/gpu/drm/i915/i915_driver.c
859
display = i915->display;
drivers/gpu/drm/i915/i915_driver.c
885
ret = intel_display_driver_probe_noirq(display);
drivers/gpu/drm/i915/i915_driver.c
893
ret = intel_display_driver_probe_nogem(display);
drivers/gpu/drm/i915/i915_driver.c
905
ret = intel_display_driver_probe(display);
drivers/gpu/drm/i915/i915_driver.c
928
intel_display_driver_remove(display);
drivers/gpu/drm/i915/i915_driver.c
930
intel_display_driver_remove_noirq(display);
drivers/gpu/drm/i915/i915_driver.c
935
intel_display_driver_remove_nogem(display);
drivers/gpu/drm/i915/i915_driver.c
957
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_driver.c
971
intel_display_driver_remove(display);
drivers/gpu/drm/i915/i915_driver.c
974
intel_hpd_cancel_work(display);
drivers/gpu/drm/i915/i915_driver.c
976
intel_display_driver_remove_noirq(display);
drivers/gpu/drm/i915/i915_driver.c
981
intel_display_driver_remove_nogem(display);
drivers/gpu/drm/i915/i915_drv.h
173
struct intel_display *display;
drivers/gpu/drm/i915/i915_getparam.c
21
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_getparam.c
44
value = intel_overlay_available(display);
drivers/gpu/drm/i915/i915_gpu_error.c
2166
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_gpu_error.c
2208
error->display_snapshot = intel_display_snapshot_capture(display);
drivers/gpu/drm/i915/i915_irq.c
226
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
270
intel_display_irq_ack(display, &state);
drivers/gpu/drm/i915/i915_irq.c
287
intel_display_irq_handler(display, &state);
drivers/gpu/drm/i915/i915_irq.c
300
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
340
intel_display_irq_ack(display, &state);
drivers/gpu/drm/i915/i915_irq.c
352
intel_display_irq_handler(display, &state);
drivers/gpu/drm/i915/i915_irq.c
373
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_irq.c
385
ilk_display_irq_master_disable(display, &de_ier, &sde_ier);
drivers/gpu/drm/i915/i915_irq.c
399
if (intel_display_irq_handler(display, NULL))
drivers/gpu/drm/i915/i915_irq.c
412
ilk_display_irq_master_enable(display, de_ier, sde_ier);
drivers/gpu/drm/i915/i915_irq.c
443
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
465
intel_display_irq_handler(display, &state);
drivers/gpu/drm/i915/i915_irq.c
497
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_irq.c
517
intel_display_irq_handler(display, NULL);
drivers/gpu/drm/i915/i915_irq.c
519
gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
drivers/gpu/drm/i915/i915_irq.c
523
gen11_gu_misc_irq_handler(display, gu_misc_iir);
drivers/gpu/drm/i915/i915_irq.c
555
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_irq.c
584
intel_display_irq_handler(display, NULL);
drivers/gpu/drm/i915/i915_irq.c
586
gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
drivers/gpu/drm/i915/i915_irq.c
590
gen11_gu_misc_irq_handler(display, gu_misc_iir);
drivers/gpu/drm/i915/i915_irq.c
599
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
602
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
608
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
615
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
620
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
626
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
632
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
639
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
647
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
657
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
667
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
677
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
682
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
686
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
691
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
695
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
703
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
706
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
713
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
719
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
729
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
740
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
748
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
752
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
823
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
826
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
835
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
841
enable_mask = i9xx_display_irq_enable_mask(display) |
drivers/gpu/drm/i915/i915_irq.c
850
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
856
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
875
intel_display_irq_ack(display, &state);
drivers/gpu/drm/i915/i915_irq.c
888
intel_display_irq_handler(display, &state);
drivers/gpu/drm/i915/i915_irq.c
900
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
903
intel_display_irq_reset(display);
drivers/gpu/drm/i915/i915_irq.c
931
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
937
enable_mask = i9xx_display_irq_enable_mask(display) |
drivers/gpu/drm/i915/i915_irq.c
949
intel_display_irq_postinstall(display);
drivers/gpu/drm/i915/i915_irq.c
955
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/i915_irq.c
974
intel_display_irq_ack(display, &state);
drivers/gpu/drm/i915/i915_irq.c
992
intel_display_irq_handler(display, &state);
drivers/gpu/drm/i915/i915_overlay.c
201
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/i915_overlay.c
208
intel_frontbuffer_flip(display, overlay->frontbuffer_bits);
drivers/gpu/drm/i915/i915_switcheroo.c
20
struct intel_display *display = i915 ? i915->display : NULL;
drivers/gpu/drm/i915/i915_switcheroo.c
27
if (!intel_display_device_present(display)) {
drivers/gpu/drm/i915/i915_switcheroo.c
50
struct intel_display *display = i915 ? i915->display : NULL;
drivers/gpu/drm/i915/i915_switcheroo.c
57
return i915 && intel_display_device_present(display) &&
drivers/gpu/drm/i915/intel_clock_gating.c
128
intel_pch_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
168
intel_pch_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
173
intel_display_cfl_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
191
intel_display_kbl_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
203
intel_display_skl_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
208
intel_display_bdw_clock_gating_disable_fbcq(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
213
intel_display_bdw_clock_gating_vblank_in_srd(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
229
intel_display_bdw_clock_gating_kvm_notif(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
231
intel_pch_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
243
intel_display_hsw_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
252
intel_pch_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
257
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/intel_clock_gating.c
259
intel_display_ivb_init_clock_gating(display);
drivers/gpu/drm/i915/intel_clock_gating.c
288
intel_display_disable_trickle_feed(display);
drivers/gpu/drm/i915/intel_clock_gating.c
293
intel_pch_init_clock_gating(display);
drivers/gpu/drm/i915/intel_clock_gating.c
365
intel_display_g4x_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
374
intel_display_i965gm_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
60
intel_display_bxt_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
65
intel_display_glk_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
76
intel_display_ilk_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
77
intel_pch_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_clock_gating.c
93
intel_display_gen6_init_clock_gating(i915->display);
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1123
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1255
MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1256
MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1257
MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
145
MMIO_D(PIPEDSL(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
146
MMIO_D(PIPEDSL(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
147
MMIO_D(PIPEDSL(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
148
MMIO_D(PIPEDSL(display, _PIPE_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
149
MMIO_D(TRANSCONF(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
150
MMIO_D(TRANSCONF(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
151
MMIO_D(TRANSCONF(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
152
MMIO_D(TRANSCONF(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
153
MMIO_D(PIPESTAT(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
154
MMIO_D(PIPESTAT(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
155
MMIO_D(PIPESTAT(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
156
MMIO_D(PIPESTAT(display, _PIPE_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
157
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
158
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
159
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
160
MMIO_D(PIPE_FLIPCOUNT_G4X(display, _PIPE_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
161
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
162
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
163
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
164
MMIO_D(PIPE_FRMCOUNT_G4X(display, _PIPE_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
165
MMIO_D(CURCNTR(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
166
MMIO_D(CURCNTR(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
167
MMIO_D(CURCNTR(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
168
MMIO_D(CURPOS(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
169
MMIO_D(CURPOS(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
170
MMIO_D(CURPOS(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
171
MMIO_D(CURBASE(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
172
MMIO_D(CURBASE(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
173
MMIO_D(CURBASE(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
174
MMIO_D(CUR_FBC_CTL(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
175
MMIO_D(CUR_FBC_CTL(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
176
MMIO_D(CUR_FBC_CTL(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
184
MMIO_D(DSPCNTR(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
185
MMIO_D(DSPADDR(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
186
MMIO_D(DSPSTRIDE(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
187
MMIO_D(DSPPOS(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
188
MMIO_D(DSPSIZE(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
189
MMIO_D(DSPSURF(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
190
MMIO_D(DSPOFFSET(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
191
MMIO_D(DSPSURFLIVE(display, PIPE_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
193
MMIO_D(DSPCNTR(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
194
MMIO_D(DSPADDR(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
195
MMIO_D(DSPSTRIDE(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
196
MMIO_D(DSPPOS(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
197
MMIO_D(DSPSIZE(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
198
MMIO_D(DSPSURF(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
199
MMIO_D(DSPOFFSET(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
200
MMIO_D(DSPSURFLIVE(display, PIPE_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
202
MMIO_D(DSPCNTR(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
203
MMIO_D(DSPADDR(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
204
MMIO_D(DSPSTRIDE(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
205
MMIO_D(DSPPOS(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
206
MMIO_D(DSPSIZE(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
207
MMIO_D(DSPSURF(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
208
MMIO_D(DSPOFFSET(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
209
MMIO_D(DSPSURFLIVE(display, PIPE_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
250
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
251
MMIO_D(TRANS_HBLANK(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
252
MMIO_D(TRANS_HSYNC(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
253
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
254
MMIO_D(TRANS_VBLANK(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
255
MMIO_D(TRANS_VSYNC(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
256
MMIO_D(BCLRPAT(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
257
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
258
MMIO_D(PIPESRC(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
259
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
260
MMIO_D(TRANS_HBLANK(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
261
MMIO_D(TRANS_HSYNC(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
262
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
263
MMIO_D(TRANS_VBLANK(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
264
MMIO_D(TRANS_VSYNC(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
265
MMIO_D(BCLRPAT(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
266
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
267
MMIO_D(PIPESRC(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
268
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
269
MMIO_D(TRANS_HBLANK(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
270
MMIO_D(TRANS_HSYNC(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
271
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
272
MMIO_D(TRANS_VBLANK(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
273
MMIO_D(TRANS_VSYNC(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
274
MMIO_D(BCLRPAT(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
275
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
276
MMIO_D(PIPESRC(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
277
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
278
MMIO_D(TRANS_HBLANK(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
279
MMIO_D(TRANS_HSYNC(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
280
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
281
MMIO_D(TRANS_VBLANK(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
282
MMIO_D(TRANS_VSYNC(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
283
MMIO_D(BCLRPAT(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
284
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
285
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
286
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
287
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
288
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
289
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
290
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
291
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
292
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
293
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
294
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
295
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
296
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
297
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
298
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
299
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
300
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
301
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
302
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
303
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
304
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
305
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
306
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
307
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
308
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
309
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
310
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
311
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
312
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
313
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
314
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
315
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
316
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_EDP));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
525
MMIO_D(TRANS_MULT(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
526
MMIO_D(TRANS_MULT(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
527
MMIO_D(TRANS_MULT(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
528
MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_A));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
529
MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_B));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
530
MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_C));
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
73
struct intel_display *display = dev_priv->display;
drivers/gpu/drm/i915/intel_uncore.c
2534
struct intel_display *display = i915->display;
drivers/gpu/drm/i915/intel_uncore.c
2569
if (HAS_FPGA_DBG_UNCLAIMED(display))
drivers/gpu/drm/i915/selftests/mock_gem_device.c
147
struct intel_display *display;
drivers/gpu/drm/i915/selftests/mock_gem_device.c
188
display = intel_display_device_probe(pdev, i915_driver_parent_interface());
drivers/gpu/drm/i915/selftests/mock_gem_device.c
189
if (IS_ERR(display))
drivers/gpu/drm/i915/selftests/mock_gem_device.c
192
i915->display = display;
drivers/gpu/drm/i915/selftests/mock_gem_device.c
279
intel_display_device_remove(i915->display);
drivers/gpu/drm/i915/selftests/mock_gem_device.c
280
i915->display = NULL;
drivers/gpu/drm/meson/meson_dw_hdmi.c
359
const struct drm_display_info *display,
drivers/gpu/drm/meson/meson_dw_hdmi.c
363
bool is_hdmi2_sink = display->hdmi.scdc.supported;
drivers/gpu/drm/meson/meson_dw_hdmi.c
372
if (drm_mode_is_420_only(display, mode) ||
drivers/gpu/drm/meson/meson_dw_hdmi.c
373
(!is_hdmi2_sink && drm_mode_is_420_also(display, mode)) ||
drivers/gpu/drm/meson/meson_dw_hdmi.c
401
dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
drivers/gpu/drm/msm/dp/dp_display.c
1075
static int msm_dp_display_get_io(struct msm_dp_display_private *display)
drivers/gpu/drm/msm/dp/dp_display.c
1077
struct platform_device *pdev = display->msm_dp_display.pdev;
drivers/gpu/drm/msm/dp/dp_display.c
1079
display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len);
drivers/gpu/drm/msm/dp/dp_display.c
1080
if (IS_ERR(display->ahb_base))
drivers/gpu/drm/msm/dp/dp_display.c
1081
return PTR_ERR(display->ahb_base);
drivers/gpu/drm/msm/dp/dp_display.c
1083
display->aux_base = msm_dp_ioremap(pdev, 1, &display->aux_len);
drivers/gpu/drm/msm/dp/dp_display.c
1084
if (IS_ERR(display->aux_base)) {
drivers/gpu/drm/msm/dp/dp_display.c
1085
if (display->aux_base != ERR_PTR(-EINVAL)) {
drivers/gpu/drm/msm/dp/dp_display.c
1086
DRM_ERROR("unable to remap aux region: %pe\n", display->aux_base);
drivers/gpu/drm/msm/dp/dp_display.c
1087
return PTR_ERR(display->aux_base);
drivers/gpu/drm/msm/dp/dp_display.c
1097
if (display->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) {
drivers/gpu/drm/msm/dp/dp_display.c
1102
display->ahb_len = DP_DEFAULT_AHB_SIZE;
drivers/gpu/drm/msm/dp/dp_display.c
1103
display->aux_base = display->ahb_base + DP_DEFAULT_AUX_OFFSET;
drivers/gpu/drm/msm/dp/dp_display.c
1104
display->aux_len = DP_DEFAULT_AUX_SIZE;
drivers/gpu/drm/msm/dp/dp_display.c
1105
display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET;
drivers/gpu/drm/msm/dp/dp_display.c
1106
display->link_len = DP_DEFAULT_LINK_SIZE;
drivers/gpu/drm/msm/dp/dp_display.c
1107
display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET;
drivers/gpu/drm/msm/dp/dp_display.c
1108
display->p0_len = DP_DEFAULT_P0_SIZE;
drivers/gpu/drm/msm/dp/dp_display.c
1113
display->link_base = msm_dp_ioremap(pdev, 2, &display->link_len);
drivers/gpu/drm/msm/dp/dp_display.c
1114
if (IS_ERR(display->link_base)) {
drivers/gpu/drm/msm/dp/dp_display.c
1115
DRM_ERROR("unable to remap link region: %pe\n", display->link_base);
drivers/gpu/drm/msm/dp/dp_display.c
1116
return PTR_ERR(display->link_base);
drivers/gpu/drm/msm/dp/dp_display.c
1119
display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len);
drivers/gpu/drm/msm/dp/dp_display.c
1120
if (IS_ERR(display->p0_base)) {
drivers/gpu/drm/msm/dp/dp_display.c
1121
DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base);
drivers/gpu/drm/msm/dp/dp_display.c
1122
return PTR_ERR(display->p0_base);
drivers/gpu/drm/nouveau/dispnv50/disp.c
237
struct nvif_object *disp = &drm->display->disp.object;
drivers/gpu/drm/nouveau/nouveau_bios.c
1029
parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
drivers/gpu/drm/nouveau/nouveau_display.c
649
disp = drm->display = kzalloc_obj(*disp);
drivers/gpu/drm/nouveau/nouveau_display.c
759
drm->display = NULL;
drivers/gpu/drm/nouveau/nouveau_display.h
45
return nouveau_drm(dev)->display;
drivers/gpu/drm/nouveau/nouveau_drv.h
287
struct nouveau_display *display;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
282
nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
302
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
319
if (!mps && display)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
326
u32 ustatus_new, int display, const char *name)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
348
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
365
nv50_gr_mp_trap(gr, i, display);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
368
if (ustatus && display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
377
if (display)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
384
if (display)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
390
if (!tps && display)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
395
nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
404
if (!status && display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
414
if (!ustatus && display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
431
if (display && (addr & 0x80000000)) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
439
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
457
if (display && (addr & 0x80000000)) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
464
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
472
if (ustatus && display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
487
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
510
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
530
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
553
if (display) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
579
if (display)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
587
nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
595
nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
604
nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
611
if (display)
drivers/gpu/drm/radeon/atombios_encoders.c
2538
if (rdev->asic->display.hdmi_enable)
drivers/gpu/drm/radeon/radeon.h
1899
} display;
drivers/gpu/drm/radeon/radeon.h
2720
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
drivers/gpu/drm/radeon/radeon.h
2721
#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
drivers/gpu/drm/radeon/radeon.h
2722
#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
drivers/gpu/drm/radeon/radeon.h
2723
#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
drivers/gpu/drm/radeon/radeon.h
2724
#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
drivers/gpu/drm/radeon/radeon.h
2745
#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
drivers/gpu/drm/radeon/radeon.h
2758
#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
drivers/gpu/drm/radeon/radeon_asic.c
1043
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1136
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1242
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1362
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1456
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1550
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1698
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1818
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
1956
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
2126
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
220
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
2239
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
2364
rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
drivers/gpu/drm/radeon/radeon_asic.c
288
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
384
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
452
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
520
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
588
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
656
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
724
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
792
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
860
.display = {
drivers/gpu/drm/radeon/radeon_asic.c
957
.display = {
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
334
const struct drm_display_info *display,
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
339
dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
drivers/gpu/drm/rockchip/rk3066_hdmi.c
320
struct drm_display_info *display;
drivers/gpu/drm/rockchip/rk3066_hdmi.c
335
display = &connector->display_info;
drivers/gpu/drm/rockchip/rk3066_hdmi.c
370
if (display->is_hdmi) {
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
169
if (display->is_hdmi)
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
99
struct drm_display_info *display = &connector->display_info;
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
143
const struct drm_display_info *display,
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
229
const struct drm_display_info *display,
drivers/gpu/drm/vboxvideo/modesetting.c
29
void hgsmi_process_display_info(struct gen_pool *ctx, u32 display,
drivers/gpu/drm/vboxvideo/modesetting.c
41
p->view_index = display;
drivers/gpu/drm/vboxvideo/vboxvideo.h
408
u32 display;
drivers/gpu/drm/vboxvideo/vboxvideo_guest.h
50
void hgsmi_process_display_info(struct gen_pool *ctx, u32 display,
drivers/gpu/drm/vc4/vc4_hdmi.c
120
struct drm_display_info *display = &vc4_hdmi->connector.display_info;
drivers/gpu/drm/vc4/vc4_hdmi.c
124
if (!display->is_hdmi)
drivers/gpu/drm/vc4/vc4_hdmi.c
127
if (!display->hdmi.scdc.supported ||
drivers/gpu/drm/vc4/vc4_hdmi.c
128
!display->hdmi.scdc.scrambling.supported)
drivers/gpu/drm/vc4/vc4_hdmi.c
1626
struct drm_display_info *display = &vc4_hdmi->connector.display_info;
drivers/gpu/drm/vc4/vc4_hdmi.c
1654
if (display->is_hdmi) {
drivers/gpu/drm/vc4/vc4_hdmi.c
1681
if (display->is_hdmi) {
drivers/gpu/drm/vc4/vc4_hdmi.c
1961
struct drm_display_info *display = &vc4_hdmi->connector.display_info;
drivers/gpu/drm/vc4/vc4_hdmi.c
1969
if (!display->is_hdmi)
drivers/gpu/drm/xe/display/xe_display.c
105
intel_display_driver_early_probe(display);
drivers/gpu/drm/xe/display/xe_display.c
107
intel_display_device_info_runtime_init(display);
drivers/gpu/drm/xe/display/xe_display.c
110
if (!intel_display_device_present(display)) {
drivers/gpu/drm/xe/display/xe_display.c
117
intel_opregion_setup(display);
drivers/gpu/drm/xe/display/xe_display.c
123
err = intel_dram_detect(display);
drivers/gpu/drm/xe/display/xe_display.c
127
intel_bw_init_hw(display);
drivers/gpu/drm/xe/display/xe_display.c
129
err = intel_display_driver_probe_noirq(display);
drivers/gpu/drm/xe/display/xe_display.c
133
err = intel_display_driver_probe_nogem(display);
drivers/gpu/drm/xe/display/xe_display.c
139
intel_display_driver_remove_noirq(display);
drivers/gpu/drm/xe/display/xe_display.c
140
intel_display_power_cleanup(display);
drivers/gpu/drm/xe/display/xe_display.c
142
intel_opregion_cleanup(display);
drivers/gpu/drm/xe/display/xe_display.c
149
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
151
intel_hpd_poll_fini(display);
drivers/gpu/drm/xe/display/xe_display.c
152
intel_hdcp_component_fini(display);
drivers/gpu/drm/xe/display/xe_display.c
153
intel_audio_deinit(display);
drivers/gpu/drm/xe/display/xe_display.c
154
intel_display_driver_remove(display);
drivers/gpu/drm/xe/display/xe_display.c
159
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
165
err = intel_display_driver_probe(display);
drivers/gpu/drm/xe/display/xe_display.c
174
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
179
intel_display_driver_register(display);
drivers/gpu/drm/xe/display/xe_display.c
180
intel_display_power_enable(display);
drivers/gpu/drm/xe/display/xe_display.c
185
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
190
intel_display_power_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
191
intel_display_driver_unregister(display);
drivers/gpu/drm/xe/display/xe_display.c
198
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
204
intel_display_irq_handler(display, NULL);
drivers/gpu/drm/xe/display/xe_display.c
209
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
215
intel_opregion_asle_intr(display);
drivers/gpu/drm/xe/display/xe_display.c
220
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
225
intel_display_irq_reset(display);
drivers/gpu/drm/xe/display/xe_display.c
230
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
235
intel_display_irq_postinstall(display);
drivers/gpu/drm/xe/display/xe_display.c
249
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
258
intel_display_power_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
260
intel_display_flush_cleanup_work(display);
drivers/gpu/drm/xe/display/xe_display.c
262
intel_opregion_suspend(display, PCI_D3cold);
drivers/gpu/drm/xe/display/xe_display.c
264
intel_dmc_suspend(display);
drivers/gpu/drm/xe/display/xe_display.c
266
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
267
intel_hpd_poll_enable(display);
drivers/gpu/drm/xe/display/xe_display.c
272
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
277
intel_dmc_resume(display);
drivers/gpu/drm/xe/display/xe_display.c
279
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
282
intel_display_driver_init_hw(display);
drivers/gpu/drm/xe/display/xe_display.c
284
intel_hpd_init(display);
drivers/gpu/drm/xe/display/xe_display.c
286
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
287
intel_hpd_poll_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
289
intel_opregion_resume(display);
drivers/gpu/drm/xe/display/xe_display.c
291
intel_display_power_enable(display);
drivers/gpu/drm/xe/display/xe_display.c
296
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
306
intel_display_power_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
309
if (intel_display_device_present(display)) {
drivers/gpu/drm/xe/display/xe_display.c
311
intel_display_driver_disable_user_access(display);
drivers/gpu/drm/xe/display/xe_display.c
312
intel_display_driver_suspend(display);
drivers/gpu/drm/xe/display/xe_display.c
315
intel_display_flush_cleanup_work(display);
drivers/gpu/drm/xe/display/xe_display.c
317
intel_encoder_block_all_hpds(display);
drivers/gpu/drm/xe/display/xe_display.c
319
intel_hpd_cancel_work(display);
drivers/gpu/drm/xe/display/xe_display.c
321
if (intel_display_device_present(display)) {
drivers/gpu/drm/xe/display/xe_display.c
322
intel_display_driver_suspend_access(display);
drivers/gpu/drm/xe/display/xe_display.c
323
intel_encoder_suspend_all(display);
drivers/gpu/drm/xe/display/xe_display.c
326
intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);
drivers/gpu/drm/xe/display/xe_display.c
328
intel_dmc_suspend(display);
drivers/gpu/drm/xe/display/xe_display.c
333
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
338
intel_display_power_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
341
if (intel_display_device_present(display)) {
drivers/gpu/drm/xe/display/xe_display.c
343
intel_display_driver_disable_user_access(display);
drivers/gpu/drm/xe/display/xe_display.c
344
intel_display_driver_suspend(display);
drivers/gpu/drm/xe/display/xe_display.c
347
intel_display_flush_cleanup_work(display);
drivers/gpu/drm/xe/display/xe_display.c
348
intel_dp_mst_suspend(display);
drivers/gpu/drm/xe/display/xe_display.c
349
intel_encoder_block_all_hpds(display);
drivers/gpu/drm/xe/display/xe_display.c
350
intel_hpd_cancel_work(display);
drivers/gpu/drm/xe/display/xe_display.c
352
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
353
intel_display_driver_suspend_access(display);
drivers/gpu/drm/xe/display/xe_display.c
355
intel_encoder_suspend_all(display);
drivers/gpu/drm/xe/display/xe_display.c
356
intel_encoder_shutdown_all(display);
drivers/gpu/drm/xe/display/xe_display.c
358
intel_opregion_suspend(display, PCI_D3cold);
drivers/gpu/drm/xe/display/xe_display.c
360
intel_dmc_suspend(display);
drivers/gpu/drm/xe/display/xe_display.c
365
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
375
intel_hpd_poll_enable(display);
drivers/gpu/drm/xe/display/xe_display.c
380
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
386
intel_display_power_suspend_late(display, s2idle);
drivers/gpu/drm/xe/display/xe_display.c
391
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
404
intel_dmc_wl_flush_release_work(display);
drivers/gpu/drm/xe/display/xe_display.c
409
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
419
intel_display_power_driver_remove(display);
drivers/gpu/drm/xe/display/xe_display.c
424
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
429
intel_display_power_resume_early(display);
drivers/gpu/drm/xe/display/xe_display.c
434
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
439
intel_dmc_resume(display);
drivers/gpu/drm/xe/display/xe_display.c
441
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
444
intel_display_driver_init_hw(display);
drivers/gpu/drm/xe/display/xe_display.c
446
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
447
intel_display_driver_resume_access(display);
drivers/gpu/drm/xe/display/xe_display.c
449
intel_hpd_init(display);
drivers/gpu/drm/xe/display/xe_display.c
451
intel_encoder_unblock_all_hpds(display);
drivers/gpu/drm/xe/display/xe_display.c
453
if (intel_display_device_present(display)) {
drivers/gpu/drm/xe/display/xe_display.c
454
intel_display_driver_resume(display);
drivers/gpu/drm/xe/display/xe_display.c
456
intel_display_driver_enable_user_access(display);
drivers/gpu/drm/xe/display/xe_display.c
459
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
460
intel_hpd_poll_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
462
intel_opregion_resume(display);
drivers/gpu/drm/xe/display/xe_display.c
466
intel_display_power_enable(display);
drivers/gpu/drm/xe/display/xe_display.c
471
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
481
intel_hpd_init(display);
drivers/gpu/drm/xe/display/xe_display.c
482
intel_hpd_poll_disable(display);
drivers/gpu/drm/xe/display/xe_display.c
483
skl_watermark_ipc_update(display);
drivers/gpu/drm/xe/display/xe_display.c
491
intel_display_device_remove(xe->display);
drivers/gpu/drm/xe/display/xe_display.c
492
xe->display = NULL;
drivers/gpu/drm/xe/display/xe_display.c
53
INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct xe_device, drm, display);
drivers/gpu/drm/xe/display/xe_display.c
548
struct intel_display *display;
drivers/gpu/drm/xe/display/xe_display.c
554
display = intel_display_device_probe(pdev, &parent);
drivers/gpu/drm/xe/display/xe_display.c
555
if (IS_ERR(display))
drivers/gpu/drm/xe/display/xe_display.c
556
return PTR_ERR(display);
drivers/gpu/drm/xe/display/xe_display.c
558
xe->display = display;
drivers/gpu/drm/xe/display/xe_display.c
564
if (intel_display_device_present(display))
drivers/gpu/drm/xe/display/xe_display.c
82
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display.c
87
intel_hpd_cancel_work(display);
drivers/gpu/drm/xe/display/xe_display.c
88
intel_display_driver_remove_nogem(display);
drivers/gpu/drm/xe/display/xe_display.c
89
intel_display_driver_remove_noirq(display);
drivers/gpu/drm/xe/display/xe_display.c
90
intel_opregion_cleanup(display);
drivers/gpu/drm/xe/display/xe_display.c
91
intel_display_power_cleanup(display);
drivers/gpu/drm/xe/display/xe_display.c
96
struct intel_display *display = xe->display;
drivers/gpu/drm/xe/display/xe_display_wa.c
13
bool intel_display_needs_wa_16023588340(struct intel_display *display)
drivers/gpu/drm/xe/display/xe_display_wa.c
15
struct xe_device *xe = to_xe_device(display->drm);
drivers/gpu/drm/xe/display/xe_tdf.c
10
void intel_td_flush(struct intel_display *display)
drivers/gpu/drm/xe/display/xe_tdf.c
12
struct xe_device *xe = to_xe_device(display->drm);
drivers/gpu/drm/xe/xe_device_types.h
96
struct intel_display *display;
drivers/media/pci/ivtv/ivtv-yuv.c
953
int draw, display;
drivers/media/pci/ivtv/ivtv-yuv.c
960
display = atomic_read(&yi->next_dma_frame);
drivers/media/pci/ivtv/ivtv-yuv.c
962
if (display > draw)
drivers/media/pci/ivtv/ivtv-yuv.c
963
display -= IVTV_YUV_BUFFERS;
drivers/media/pci/ivtv/ivtv-yuv.c
965
if (draw - display >= yi->max_frames_buffered)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1305
vpu_buf->display = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
436
dst_vpu_buf->display = true;
drivers/media/platform/chips-media/wave5/wave5-vpu.h
31
bool display;
drivers/media/platform/ti/davinci/vpif.c
48
struct platform_device *display;
drivers/media/platform/ti/davinci/vpif.c
524
data->display = pdev_display;
drivers/media/platform/ti/davinci/vpif.c
548
if (data->display)
drivers/media/platform/ti/davinci/vpif.c
549
platform_device_unregister(data->display);
drivers/media/platform/ti/omap/omap_vout.c
1312
struct omap_dss_device *display = ovl->get_device(ovl);
drivers/media/platform/ti/omap/omap_vout.c
1332
vout->fbuf.fmt.width = display->panel.timings.x_res;
drivers/media/platform/ti/omap/omap_vout.c
1333
vout->fbuf.fmt.height = display->panel.timings.y_res;
drivers/media/platform/ti/omap/omap_vout.c
1688
struct omap_dss_device *display = vid_dev->displays[i];
drivers/media/platform/ti/omap/omap_vout.c
1690
if (display->driver->update)
drivers/media/platform/ti/omap/omap_vout.c
1691
display->driver->update(display, 0, 0,
drivers/media/platform/ti/omap/omap_vout.c
1692
display->panel.timings.x_res,
drivers/media/platform/ti/omap/omap_vout.c
1693
display->panel.timings.y_res);
drivers/net/wireless/intel/iwlegacy/3945.h
183
bool display);
drivers/net/wireless/intel/iwlegacy/4965-mac.c
1207
il4965_dump_fh(struct il_priv *il, char **buf, bool display)
drivers/net/wireless/intel/iwlegacy/4965-mac.c
1226
if (display) {
drivers/net/wireless/intel/iwlegacy/4965.h
43
int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
drivers/net/wireless/intel/iwlegacy/common.h
1560
int (*dump_fh) (struct il_priv *il, char **buf, bool display);
drivers/pinctrl/pinconf-generic.c
154
seq_printf(s, "%s: 0x%x", conf_items[i].display,
drivers/pinctrl/pinconf-generic.c
167
pctldev->desc->custom_conf_items[i].display,
drivers/pinctrl/pinconf-generic.c
94
seq_puts(s, item->display);
drivers/platform/x86/asus-laptop.c
1129
static DEVICE_ATTR_WO(display);
drivers/platform/x86/hp/hp-wmi.c
1127
static DEVICE_ATTR_RO(display);
drivers/staging/fbtft/fb_agm1264k-fl.c
420
static struct fbtft_display display = {
drivers/staging/fbtft/fb_agm1264k-fl.c
436
FBTFT_REGISTER_DRIVER(DRVNAME, "displaytronic,fb_agm1264k-fl", &display);
drivers/staging/fbtft/fb_bd663474.c
150
static struct fbtft_display display = {
drivers/staging/fbtft/fb_bd663474.c
162
FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display);
drivers/staging/fbtft/fb_hx8340bn.c
193
static struct fbtft_display display = {
drivers/staging/fbtft/fb_hx8340bn.c
208
FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8340bn", &display);
drivers/staging/fbtft/fb_hx8347d.c
159
static struct fbtft_display display = {
drivers/staging/fbtft/fb_hx8347d.c
174
FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8347d", &display);
drivers/staging/fbtft/fb_hx8353d.c
112
static struct fbtft_display display = {
drivers/staging/fbtft/fb_hx8353d.c
126
FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8353d", &display);
drivers/staging/fbtft/fb_hx8357d.c
166
static struct fbtft_display display = {
drivers/staging/fbtft/fb_hx8357d.c
178
FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8357d", &display);
drivers/staging/fbtft/fb_ili9163.c
230
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9163.c
251
FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9163", &display);
drivers/staging/fbtft/fb_ili9320.c
241
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9320.c
256
FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
drivers/staging/fbtft/fb_ili9325.c
235
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9325.c
252
FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display);
drivers/staging/fbtft/fb_ili9340.c
108
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9340.c
118
FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9340", &display);
drivers/staging/fbtft/fb_ili9341.c
121
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9341.c
136
FBTFT_REGISTER_SPI_DRIVER(DRVNAME, "ilitek", "ili9341", &display);
drivers/staging/fbtft/fb_ili9481.c
72
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9481.c
82
FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9481", &display);
drivers/staging/fbtft/fb_ili9486.c
72
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ili9486.c
82
FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9486", &display);
drivers/staging/fbtft/fb_pcd8544.c
143
static struct fbtft_display display = {
drivers/staging/fbtft/fb_pcd8544.c
160
FBTFT_REGISTER_DRIVER(DRVNAME, "philips,pcd8544", &display);
drivers/staging/fbtft/fb_ra8875.c
278
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ra8875.c
289
FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);
drivers/staging/fbtft/fb_s6d02a1.c
135
static struct fbtft_display display = {
drivers/staging/fbtft/fb_s6d02a1.c
145
FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d02a1", &display);
drivers/staging/fbtft/fb_s6d1121.c
156
static struct fbtft_display display = {
drivers/staging/fbtft/fb_s6d1121.c
173
FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d1121", &display);
drivers/staging/fbtft/fb_seps525.c
192
static struct fbtft_display display = {
drivers/staging/fbtft/fb_seps525.c
203
FBTFT_REGISTER_DRIVER(DRVNAME, "syncoam,seps525", &display);
drivers/staging/fbtft/fb_sh1106.c
154
static struct fbtft_display display = {
drivers/staging/fbtft/fb_sh1106.c
173
FBTFT_REGISTER_SPI_DRIVER(DRVNAME, "sinowealth", "sh1106", &display);
drivers/staging/fbtft/fb_ssd1289.c
152
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ssd1289.c
167
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1289", &display);
drivers/staging/fbtft/fb_ssd1305.c
181
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ssd1305.c
198
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1305", &display);
drivers/staging/fbtft/fb_ssd1306.c
200
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ssd1306.c
216
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1306", &display);
drivers/staging/fbtft/fb_ssd1325.c
159
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ssd1325.c
176
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1325", &display);
drivers/staging/fbtft/fb_ssd1331.c
177
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ssd1331.c
193
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1331", &display);
drivers/staging/fbtft/fb_ssd1351.c
174
static struct fbtft_display display = {
drivers/staging/fbtft/fb_ssd1351.c
230
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1351", &display);
drivers/staging/fbtft/fb_ssd1351.c
32
par->pdata->display.backlight == FBTFT_ONBOARD_BACKLIGHT) {
drivers/staging/fbtft/fb_st7735r.c
151
static struct fbtft_display display = {
drivers/staging/fbtft/fb_st7735r.c
165
FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7735r", &display);
drivers/staging/fbtft/fb_st7789v.c
244
switch (par->pdata->display.buswidth) {
drivers/staging/fbtft/fb_st7789v.c
256
par->pdata->display.buswidth);
drivers/staging/fbtft/fb_st7789v.c
369
static struct fbtft_display display = {
drivers/staging/fbtft/fb_st7789v.c
385
FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7789v", &display);
drivers/staging/fbtft/fb_tinylcd.c
74
static struct fbtft_display display = {
drivers/staging/fbtft/fb_tinylcd.c
84
FBTFT_REGISTER_DRIVER(DRVNAME, "neosec,tinylcd", &display);
drivers/staging/fbtft/fb_tls8204.c
136
static struct fbtft_display display = {
drivers/staging/fbtft/fb_tls8204.c
153
FBTFT_REGISTER_DRIVER(DRVNAME, "teralane,tls8204", &display);
drivers/staging/fbtft/fb_uc1611.c
227
switch (par->pdata->display.buswidth) {
drivers/staging/fbtft/fb_uc1611.c
299
par->pdata->display.buswidth);
drivers/staging/fbtft/fb_uc1611.c
309
static struct fbtft_display display = {
drivers/staging/fbtft/fb_uc1611.c
325
FBTFT_REGISTER_DRIVER(DRVNAME, "ultrachip,uc1611", &display);
drivers/staging/fbtft/fb_uc1701.c
151
static struct fbtft_display display = {
drivers/staging/fbtft/fb_uc1701.c
163
FBTFT_REGISTER_DRIVER(DRVNAME, "UltraChip,uc1701", &display);
drivers/staging/fbtft/fb_upd161704.c
164
static struct fbtft_display display = {
drivers/staging/fbtft/fb_upd161704.c
175
FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);
drivers/staging/fbtft/fbtft-core.c
1050
if (pdata->display.buswidth != 9 && par->startbyte == 0 &&
drivers/staging/fbtft/fbtft-core.c
1064
for (i = 0; i < pdata->display.buswidth; i++) {
drivers/staging/fbtft/fbtft-core.c
1101
pdata->display.width = fbtft_property_value(dev, "width");
drivers/staging/fbtft/fbtft-core.c
1102
pdata->display.height = fbtft_property_value(dev, "height");
drivers/staging/fbtft/fbtft-core.c
1103
pdata->display.regwidth = fbtft_property_value(dev, "regwidth");
drivers/staging/fbtft/fbtft-core.c
1104
pdata->display.buswidth = fbtft_property_value(dev, "buswidth");
drivers/staging/fbtft/fbtft-core.c
1105
pdata->display.backlight = fbtft_property_value(dev, "backlight");
drivers/staging/fbtft/fbtft-core.c
1106
pdata->display.bpp = fbtft_property_value(dev, "bpp");
drivers/staging/fbtft/fbtft-core.c
1107
pdata->display.debug = fbtft_property_value(dev, "debug");
drivers/staging/fbtft/fbtft-core.c
1116
pdata->display.backlight = 1;
drivers/staging/fbtft/fbtft-core.c
1118
pdata->display.fbtftops.init_display =
drivers/staging/fbtft/fbtft-core.c
1121
pdata->display.fbtftops.request_gpios = fbtft_request_gpios;
drivers/staging/fbtft/fbtft-core.c
1138
int fbtft_probe_common(struct fbtft_display *display,
drivers/staging/fbtft/fbtft-core.c
1160
info = fbtft_framebuffer_alloc(display, dev, pdata);
drivers/staging/fbtft/fbtft-core.c
1168
if (display->buswidth == 0) {
drivers/staging/fbtft/fbtft-core.c
1174
if (display->regwidth == 8 && display->buswidth == 8)
drivers/staging/fbtft/fbtft-core.c
1176
else if (display->regwidth == 8 && display->buswidth == 9 && par->spi)
drivers/staging/fbtft/fbtft-core.c
1178
else if (display->regwidth == 16 && display->buswidth == 8)
drivers/staging/fbtft/fbtft-core.c
1180
else if (display->regwidth == 16 && display->buswidth == 16)
drivers/staging/fbtft/fbtft-core.c
1185
display->regwidth, display->buswidth);
drivers/staging/fbtft/fbtft-core.c
1188
if (display->buswidth == 8)
drivers/staging/fbtft/fbtft-core.c
1190
else if (display->buswidth == 9)
drivers/staging/fbtft/fbtft-core.c
1192
else if (display->buswidth == 16)
drivers/staging/fbtft/fbtft-core.c
1197
if (display->buswidth == 8)
drivers/staging/fbtft/fbtft-core.c
1199
else if (display->buswidth == 16)
drivers/staging/fbtft/fbtft-core.c
1204
if (par->spi && display->buswidth == 9) {
drivers/staging/fbtft/fbtft-core.c
1227
fbtft_merge_fbtftops(&par->fbtftops, &display->fbtftops);
drivers/staging/fbtft/fbtft-core.c
1234
fbtft_merge_fbtftops(&par->fbtftops, &pdata->display.fbtftops);
drivers/staging/fbtft/fbtft-core.c
491
struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,
drivers/staging/fbtft/fbtft-core.c
503
int txbuflen = display->txbuflen;
drivers/staging/fbtft/fbtft-core.c
504
unsigned int bpp = display->bpp;
drivers/staging/fbtft/fbtft-core.c
505
unsigned int fps = display->fps;
drivers/staging/fbtft/fbtft-core.c
507
const s16 *init_sequence = display->init_sequence;
drivers/staging/fbtft/fbtft-core.c
508
char *gamma = display->gamma;
drivers/staging/fbtft/fbtft-core.c
512
if (display->gamma_num * display->gamma_len >
drivers/staging/fbtft/fbtft-core.c
535
if (pdata->display.init_sequence)
drivers/staging/fbtft/fbtft-core.c
536
init_sequence = pdata->display.init_sequence;
drivers/staging/fbtft/fbtft-core.c
539
if (pdata->display.debug)
drivers/staging/fbtft/fbtft-core.c
540
display->debug = pdata->display.debug;
drivers/staging/fbtft/fbtft-core.c
541
if (pdata->display.backlight)
drivers/staging/fbtft/fbtft-core.c
542
display->backlight = pdata->display.backlight;
drivers/staging/fbtft/fbtft-core.c
543
if (pdata->display.width)
drivers/staging/fbtft/fbtft-core.c
544
display->width = pdata->display.width;
drivers/staging/fbtft/fbtft-core.c
545
if (pdata->display.height)
drivers/staging/fbtft/fbtft-core.c
546
display->height = pdata->display.height;
drivers/staging/fbtft/fbtft-core.c
547
if (pdata->display.buswidth)
drivers/staging/fbtft/fbtft-core.c
548
display->buswidth = pdata->display.buswidth;
drivers/staging/fbtft/fbtft-core.c
549
if (pdata->display.regwidth)
drivers/staging/fbtft/fbtft-core.c
550
display->regwidth = pdata->display.regwidth;
drivers/staging/fbtft/fbtft-core.c
552
display->debug |= debug;
drivers/staging/fbtft/fbtft-core.c
553
fbtft_expand_debug_value(&display->debug);
drivers/staging/fbtft/fbtft-core.c
558
width = display->height;
drivers/staging/fbtft/fbtft-core.c
559
height = display->width;
drivers/staging/fbtft/fbtft-core.c
562
width = display->width;
drivers/staging/fbtft/fbtft-core.c
563
height = display->height;
drivers/staging/fbtft/fbtft-core.c
574
if (display->gamma_num && display->gamma_len) {
drivers/staging/fbtft/fbtft-core.c
576
display->gamma_num *
drivers/staging/fbtft/fbtft-core.c
577
display->gamma_len,
drivers/staging/fbtft/fbtft-core.c
588
vmem_size = display->width * display->height * bpp / 8;
drivers/staging/fbtft/fbtft-core.c
636
par->debug = display->debug;
drivers/staging/fbtft/fbtft-core.c
643
par->gamma.num_curves = display->gamma_num;
drivers/staging/fbtft/fbtft-core.c
644
par->gamma.num_values = display->gamma_len;
drivers/staging/fbtft/fbtft-core.c
682
if (display->backlight)
drivers/staging/fbtft/fbtft-core.c
686
fbtft_merge_fbtftops(&par->fbtftops, &display->fbtftops);
drivers/staging/fbtft/fbtft.h
136
struct fbtft_display display;
drivers/staging/fbtft/fbtft.h
246
struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,
drivers/staging/fbtft/fbtft.h
255
int fbtft_probe_common(struct fbtft_display *display, struct spi_device *sdev,
drivers/staging/fbtft/fbtft.h
427
(((struct fbtft_platform_data *)(dev)->platform_data)->display.debug & DEBUG_DRIVER_INIT_FUNCTIONS))) \
drivers/video/fbdev/cirrusfb.c
1905
unsigned long *display, unsigned long *registers)
drivers/video/fbdev/cirrusfb.c
1908
assert(display != NULL);
drivers/video/fbdev/cirrusfb.c
1911
*display = 0;
drivers/video/fbdev/cirrusfb.c
1917
*display = pci_resource_start(pdev, 1);
drivers/video/fbdev/cirrusfb.c
1920
*display = pci_resource_start(pdev, 0);
drivers/video/fbdev/cirrusfb.c
1924
assert(*display != 0);
drivers/video/fbdev/neofb.c
1767
unsigned char type, display;
drivers/video/fbdev/neofb.c
1779
display = vga_rgfx(NULL, 0x20);
drivers/video/fbdev/neofb.c
1781
par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
drivers/video/fbdev/neofb.c
1782
par->external_display = display & 1;
drivers/video/fbdev/omap2/omapfb/dss/manager-sysfs.c
427
static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
205
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
215
if (display && display->driver->sync)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
216
display->driver->sync(display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
280
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
283
if (!display)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
289
display->driver->get_resolution(display, &dw, &dh);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
294
return display->driver->update(display, x, y, w, h);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
300
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
306
if (!display)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
314
d = get_display_data(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
323
if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
325
omapfb_start_auto_update(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
327
omapfb_stop_auto_update(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
343
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
348
if (!display)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
353
d = get_display_data(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
477
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
481
if (!display || !display->driver->memory_read)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
496
r = display->driver->memory_read(display, buf, mr->buffer_size,
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
575
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
602
if (!display || !display->driver->sync) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
608
r = display->driver->sync(display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
613
if (!display || !display->driver->update) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
631
if (!display || !display->driver->update) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
686
if (!display) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
692
if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
694
if (display->caps & OMAP_DSS_DISPLAY_CAP_TEAR_ELIM)
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
767
if (!display) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
772
mgr = omapdss_find_mgr_from_display(display);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
783
if (!display) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
799
if (!display || !display->driver->run_test) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
804
r = display->driver->run_test(display, p.test_num);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
814
if (!display || !display->driver->run_test) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
819
r = display->driver->run_test(display, p.test_num);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
862
if (!display || !display->driver->enable_te) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
867
r = display->driver->enable_te(display,
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
878
if (display == NULL) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
883
display->driver->get_resolution(display, &xres, &yres);
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
888
if (display->driver->get_dimensions) {
drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c
890
display->driver->get_dimensions(display, &w, &h);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1226
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1230
if (!display)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1235
d = get_display_data(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1239
if (display->state == OMAP_DSS_DISPLAY_ACTIVE)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1242
r = display->driver->enable(display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1244
if ((display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) &&
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1247
omapfb_start_auto_update(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1257
if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1261
omapfb_stop_auto_update(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1263
display->driver->disable(display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1429
struct omap_dss_device *display;
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1432
display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1434
if (!display)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1437
switch (omapfb_get_recommended_bpp(fbdev, display)) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1452
display->driver->get_resolution(display, &w, &h);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1695
struct omap_dss_device *display)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1713
d = get_display_data(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1723
struct omap_dss_device *display)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1727
d = get_display_data(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1738
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1755
if (display) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1759
display->driver->get_resolution(display, &w, &h);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
1774
switch (omapfb_get_recommended_bpp(fbdev, display)) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2005
struct omap_dss_device *display,
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2059
if (display->driver->get_timings) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2060
display->driver->get_timings(display, timings);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2106
struct omap_dss_device *display, char *mode_str)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2113
r = omapfb_mode_to_timings(mode_str, display, &timings, &bpp);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2117
d = get_display_data(fbdev, display);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2120
if (display->driver->check_timings) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2121
r = display->driver->check_timings(display, &timings);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2126
if (display->driver->get_timings) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2127
display->driver->get_timings(display, &temp_timings);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2135
if (display->driver->set_timings)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2136
display->driver->set_timings(display, &timings);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2168
struct omap_dss_device *display;
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2181
display = NULL;
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2185
display = fbdev->displays[i].dssdev;
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2190
if (!display) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2195
r = omapfb_set_def_mode(fbdev, display, mode_str);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2206
struct omap_dss_device *display,
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2209
if (display->driver->get_timings) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2210
display->driver->get_timings(display, t);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2235
static int omapfb_find_best_mode(struct omap_dss_device *display,
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2242
if (!display->driver->read_edid)
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2250
r = display->driver->read_edid(display, edid, len);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2281
fb_videomode_to_omap_timings(m, display, &t);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2283
r = display->driver->check_timings(display, &t);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
2295
fb_videomode_to_omap_timings(&specs->modedb[best_idx], display,
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
657
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
698
if (display && display->driver->get_dimensions) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
700
display->driver->get_dimensions(display, &w, &h);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
710
if (display && display->driver->get_timings) {
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
712
display->driver->get_timings(display, &timings);
drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c
428
struct omap_dss_device *display = fb2display(fbi);
drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c
442
if (display && display->driver->sync)
drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c
443
display->driver->sync(display);
drivers/video/fbdev/omap2/omapfb/omapfb.h
127
struct omap_dss_device *display);
drivers/video/fbdev/omap2/omapfb/omapfb.h
129
struct omap_dss_device *display);
drivers/video/fbdev/pxafb.c
2158
struct device_node *display, *np;
drivers/video/fbdev/pxafb.c
2174
display = of_graph_get_remote_port_parent(np);
drivers/video/fbdev/pxafb.c
2176
if (!display) {
drivers/video/fbdev/pxafb.c
2181
ret = of_get_pxafb_display(dev, display, info, bus_width);
drivers/video/fbdev/pxafb.c
2182
of_node_put(display);
drivers/video/fbdev/s1d13xxxfb.c
206
if ((s1dfb->display & 0x01)) /* LCD */
drivers/video/fbdev/s1d13xxxfb.c
237
if ((s1dfb->display & 0x01)) /* LCD */
drivers/video/fbdev/s1d13xxxfb.c
337
if ((par->display & 0x01) != 0)
drivers/video/fbdev/s1d13xxxfb.c
339
if ((par->display & 0x02) != 0)
drivers/video/fbdev/s1d13xxxfb.c
382
if ((par->display & 0x01)) {
drivers/video/fbdev/s1d13xxxfb.c
646
u8 panel, display;
drivers/video/fbdev/s1d13xxxfb.c
657
par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
drivers/video/fbdev/s1d13xxxfb.c
658
crt_enabled = (par->display & 0x02) != 0;
drivers/video/fbdev/s1d13xxxfb.c
659
lcd_enabled = (par->display & 0x01) != 0;
drivers/video/fbdev/s1d13xxxfb.c
665
display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
drivers/video/fbdev/s1d13xxxfb.c
667
display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
drivers/video/fbdev/s1d13xxxfb.c
669
bpp = display & 0x07;
drivers/video/fbdev/s1d13xxxfb.c
990
if ((s1dfb->display & 0x01) != 0)
drivers/video/fbdev/s1d13xxxfb.c
992
if ((s1dfb->display & 0x02) != 0)
drivers/video/fbdev/sh_mobile_lcdcfb.c
1760
if (fb_mode_is_equal(&ch->display.mode, &mode))
drivers/video/fbdev/sh_mobile_lcdcfb.c
1765
fb_videomode_to_var(&var, &ch->display.mode);
drivers/video/fbdev/sh_mobile_lcdcfb.c
1766
var.width = ch->display.width;
drivers/video/fbdev/sh_mobile_lcdcfb.c
1767
var.height = ch->display.height;
drivers/video/fbdev/sh_mobile_lcdcfb.c
2094
var->width = ch->display.width;
drivers/video/fbdev/sh_mobile_lcdcfb.c
2095
var->height = ch->display.height;
drivers/video/fbdev/sh_mobile_lcdcfb.c
2463
ch->display.width = cfg->panel_cfg.width;
drivers/video/fbdev/sh_mobile_lcdcfb.c
2464
ch->display.height = cfg->panel_cfg.height;
drivers/video/fbdev/sh_mobile_lcdcfb.c
2465
ch->display.mode = *mode;
drivers/video/fbdev/sh_mobile_lcdcfb.c
723
const struct fb_videomode *mode = &ch->display.mode;
drivers/video/fbdev/sh_mobile_lcdcfb.h
101
} display;
include/drm/bridge/dw_hdmi.h
117
const struct drm_display_info *display,
include/drm/bridge/dw_hdmi.h
203
const struct drm_display_info *display);
include/drm/drm_modes.h
464
bool drm_mode_is_420_only(const struct drm_display_info *display,
include/drm/drm_modes.h
466
bool drm_mode_is_420_also(const struct drm_display_info *display,
include/drm/drm_modes.h
468
bool drm_mode_is_420(const struct drm_display_info *display,
include/drm/intel/display_member.h
23
struct intel_display *display;
include/drm/intel/display_member.h
38
offsetof(struct __intel_generic_device, display) - offsetof(struct __intel_generic_device, drm) == \
include/linux/pinctrl/pinconf-generic.h
196
.param = a, .display = b, .format = c, .has_arg = d, \
include/linux/pinctrl/pinconf-generic.h
204
const char * const display;
include/video/omapfb_dss.h
696
int (*enable)(struct omap_dss_device *display);
include/video/omapfb_dss.h
697
void (*disable)(struct omap_dss_device *display);
include/video/omapfb_dss.h
698
int (*run_test)(struct omap_dss_device *display, int test);
include/video/s1d13xxxfb.h
152
unsigned char display;
tools/perf/builtin-c2c.c
116
int display;
tools/perf/builtin-c2c.c
1276
switch (c2c.display) {
tools/perf/builtin-c2c.c
2167
switch (c2c.display) {
tools/perf/builtin-c2c.c
2202
switch (c2c.display) {
tools/perf/builtin-c2c.c
2283
bool display = he__display(he, &c2c.shared_clines_stats);
tools/perf/builtin-c2c.c
2288
if (display && c2c_hists) {
tools/perf/builtin-c2c.c
2317
if (c2c.display == DISPLAY_SNP_PEER)
tools/perf/builtin-c2c.c
2532
if (c2c.display != DISPLAY_SNP_PEER)
tools/perf/builtin-c2c.c
2584
display_str[c2c.display]);
tools/perf/builtin-c2c.c
2784
display_str[c2c.display]);
tools/perf/builtin-c2c.c
2896
dim_percent_costly_snoop.header = percent_costly_snoop_header[c2c.display];
tools/perf/builtin-c2c.c
2982
const char *display = str;
tools/perf/builtin-c2c.c
2984
if (!strcmp(display, "tot"))
tools/perf/builtin-c2c.c
2985
c2c.display = DISPLAY_TOT_HITM;
tools/perf/builtin-c2c.c
2986
else if (!strcmp(display, "rmt"))
tools/perf/builtin-c2c.c
2987
c2c.display = DISPLAY_RMT_HITM;
tools/perf/builtin-c2c.c
2988
else if (!strcmp(display, "lcl"))
tools/perf/builtin-c2c.c
2989
c2c.display = DISPLAY_LCL_HITM;
tools/perf/builtin-c2c.c
2990
else if (!strcmp(display, "peer"))
tools/perf/builtin-c2c.c
2991
c2c.display = DISPLAY_SNP_PEER;
tools/perf/builtin-c2c.c
3040
c2c.display == DISPLAY_SNP_PEER ? "percent_rmt_peer,"
tools/perf/builtin-c2c.c
3051
c2c.display == DISPLAY_SNP_PEER ? "mean_rmt_peer,"
tools/perf/builtin-c2c.c
3083
if (c2c.display == DISPLAY_TOT_HITM)
tools/perf/builtin-c2c.c
3085
else if (c2c.display == DISPLAY_RMT_HITM)
tools/perf/builtin-c2c.c
3087
else if (c2c.display == DISPLAY_LCL_HITM)
tools/perf/builtin-c2c.c
3089
else if (c2c.display == DISPLAY_SNP_PEER)
tools/perf/builtin-c2c.c
3115
const char *display = NULL;
tools/perf/builtin-c2c.c
3139
OPT_STRING('d', "display", &display, "Switch HITM output type", "tot,lcl,rmt,peer"),
tools/perf/builtin-c2c.c
3231
if (!display) {
tools/perf/builtin-c2c.c
3233
display = "peer";
tools/perf/builtin-c2c.c
3235
display = "tot";
tools/perf/builtin-c2c.c
3238
err = setup_display(display);
tools/perf/builtin-c2c.c
3319
if (c2c.display != DISPLAY_SNP_PEER)
tools/perf/builtin-c2c.c
3350
if (c2c.display == DISPLAY_TOT_HITM)
tools/perf/builtin-c2c.c
3352
else if (c2c.display == DISPLAY_RMT_HITM)
tools/perf/builtin-c2c.c
3354
else if (c2c.display == DISPLAY_LCL_HITM)
tools/perf/builtin-c2c.c
3356
else if (c2c.display == DISPLAY_SNP_PEER)
tools/perf/builtin-c2c.c
865
switch (c2c.display) {
tools/perf/builtin-help.c
142
const char *display = getenv("DISPLAY");
tools/perf/builtin-help.c
144
if (display && *display) {
tools/perf/builtin-timechart.c
102
int display;
tools/perf/builtin-timechart.c
119
int display;
tools/perf/builtin-timechart.c
1197
if (!c->display) {
tools/perf/builtin-timechart.c
1310
if (!c->display) {
tools/perf/builtin-timechart.c
1394
p->display = 0;
tools/perf/builtin-timechart.c
1405
c->display = 0;
tools/perf/builtin-timechart.c
1411
c->display = 1;
tools/perf/builtin-timechart.c
1412
p->display = 1;
tools/perf/builtin-timechart.c
1434
p->display = 0;
tools/perf/builtin-timechart.c
1442
p->display = 1;
tools/perf/builtin-timechart.c
1447
c->display = 0;
tools/perf/builtin-timechart.c
1453
c->display = 1;
tools/perf/builtin-timechart.c
1482
c->display = 0;
tools/perf/builtin-timechart.c
1485
c->display = 1;
