/*
 * Copyright © 2006-2019 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DISPLAY_H_
#define _INTEL_DISPLAY_H_

#include <drm/drm_util.h>

#include "intel_display_reg_defs.h"
#include "intel_display_limits.h"

struct drm_atomic_commit;
struct drm_device;
struct drm_display_mode;
struct drm_encoder;
struct drm_format_info;
struct drm_modeset_acquire_ctx;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_display;
struct intel_encoder;
struct intel_link_m_n;
struct intel_plane;
struct intel_plane_state;
struct intel_power_domain_mask;

#define pipe_name(p) ((p) + 'A')

static inline const char *transcoder_name(enum transcoder transcoder)
{
        switch (transcoder) {
        case TRANSCODER_A:
                return "A";
        case TRANSCODER_B:
                return "B";
        case TRANSCODER_C:
                return "C";
        case TRANSCODER_D:
                return "D";
        case TRANSCODER_EDP:
                return "EDP";
        case TRANSCODER_DSI_A:
                return "DSI A";
        case TRANSCODER_DSI_C:
                return "DSI C";
        default:
                return "<invalid>";
        }
}

static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
        return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

#define plane_name(p) ((p) + 'A')

#define for_each_plane_id_on_crtc(__crtc, __p) \
        for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
                for_each_if((__crtc)->plane_ids_mask & BIT(__p))

#define for_each_dbuf_slice(__dev_priv, __slice) \
        for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
                for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))

#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
        for_each_dbuf_slice((__dev_priv), (__slice)) \
                for_each_if((__mask) & BIT(__slice))

#define port_name(p) ((p) + 'A')

/*
 * Ports identifier referenced from other drivers.
 * Expected to remain stable over time
 */
static inline const char *port_identifier(enum port port)
{
        switch (port) {
        case PORT_A:
                return "Port A";
        case PORT_B:
                return "Port B";
        case PORT_C:
                return "Port C";
        case PORT_D:
                return "Port D";
        case PORT_E:
                return "Port E";
        case PORT_F:
                return "Port F";
        case PORT_G:
                return "Port G";
        case PORT_H:
                return "Port H";
        case PORT_I:
                return "Port I";
        default:
                return "<invalid>";
        }
}

enum tc_port {
        TC_PORT_NONE = -1,

        TC_PORT_1 = 0,
        TC_PORT_2,
        TC_PORT_3,
        TC_PORT_4,
        TC_PORT_5,
        TC_PORT_6,

        I915_MAX_TC_PORTS
};

enum phy {
        PHY_NONE = -1,

        PHY_A = 0,
        PHY_B,
        PHY_C,
        PHY_D,
        PHY_E,
        PHY_F,
        PHY_G,
        PHY_H,
        PHY_I,

        I915_MAX_PHYS
};

#define phy_name(a) ((a) + 'A')

enum phy_fia {
        FIA1,
        FIA2,
        FIA3,
};

#define for_each_hpd_pin(__pin) \
        for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

#define for_each_pipe(__dev_priv, __p) \
        for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
                for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))

#define for_each_pipe_masked(__dev_priv, __p, __mask) \
        for_each_pipe(__dev_priv, __p) \
                for_each_if((__mask) & BIT(__p))

#define for_each_cpu_transcoder(__dev_priv, __t) \
        for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
                for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))

#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
        for_each_cpu_transcoder(__dev_priv, __t) \
                for_each_if ((__mask) & BIT(__t))

#define for_each_sprite(__dev_priv, __p, __s)                           \
        for ((__s) = 0;                                                 \
             (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
             (__s)++)

#define for_each_port(__port) \
        for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)

#define for_each_port_masked(__port, __ports_mask)                      \
        for_each_port(__port)                                           \
                for_each_if((__ports_mask) & BIT(__port))

#define for_each_phy_masked(__phy, __phys_mask) \
        for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
                for_each_if((__phys_mask) & BIT(__phy))

#define for_each_intel_plane(dev, intel_plane) \
        list_for_each_entry(intel_plane,                        \
                            &(dev)->mode_config.plane_list,     \
                            base.head)

#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
        list_for_each_entry(intel_plane,                                \
                            &(dev)->mode_config.plane_list,             \
                            base.head)                                  \
                for_each_if((plane_mask) &                              \
                            drm_plane_mask(&intel_plane->base))

#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
        list_for_each_entry(intel_plane,                                \
                            &(dev)->mode_config.plane_list,             \
                            base.head)                                  \
                for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)

#define for_each_intel_crtc(display, crtc) \
        list_for_each_entry((crtc), \
                            &(display)->pipe_list, \
                            pipe_head)

#define for_each_intel_crtc_reverse(display, crtc) \
        list_for_each_entry_reverse((crtc), \
                                    &(display)->pipe_list, \
                                    pipe_head)

#define for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) \
        for_each_intel_crtc((display), (crtc)) \
                for_each_if((pipe_mask) & BIT((crtc)->pipe))

#define for_each_intel_crtc_in_pipe_mask_reverse(display, crtc, pipe_mask) \
        for_each_intel_crtc_reverse((display), (crtc)) \
                for_each_if((pipe_mask) & BIT((crtc)->pipe))

#define for_each_intel_encoder(dev, intel_encoder)              \
        list_for_each_entry(intel_encoder,                      \
                            &(dev)->mode_config.encoder_list,   \
                            base.head)

#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
        list_for_each_entry(intel_encoder,                              \
                            &(dev)->mode_config.encoder_list,           \
                            base.head)                                  \
                for_each_if((encoder_mask) &                            \
                            drm_encoder_mask(&intel_encoder->base))

#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
        list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
                for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
                            intel_encoder_can_psr(intel_encoder))

#define for_each_intel_dp(dev, intel_encoder)                   \
        for_each_intel_encoder(dev, intel_encoder)              \
                for_each_if(intel_encoder_is_dp(intel_encoder))

#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
        for_each_intel_encoder((dev), (intel_encoder)) \
                for_each_if(intel_encoder_can_psr(intel_encoder))

#define for_each_intel_connector_iter(intel_connector, iter) \
        while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
        list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
                for_each_if((intel_encoder)->base.crtc == (__crtc))

#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
        for ((__i) = 0; \
             (__i) < (__state)->base.dev->mode_config.num_total_plane && \
                     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
                      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
             (__i)++) \
                for_each_if(plane)

#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
        for ((__i) = 0; \
             (__i) < (__state)->base.dev->mode_config.num_total_plane && \
                     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
                      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
             (__i)++) \
                for_each_if(plane)

#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
        for ((__i) = 0; \
             (__i) < (__state)->base.dev->mode_config.num_total_plane && \
                     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
                      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
                      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
             (__i)++) \
                for_each_if(plane)

#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state) \
        for_each_intel_crtc(to_intel_display(__state), (crtc)) \
                for_each_if((old_crtc_state) = intel_atomic_get_old_crtc_state((__state), (crtc)))

#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state) \
        for_each_intel_crtc(to_intel_display(__state), (crtc)) \
                for_each_if((new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc)))

#define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state) \
        for_each_intel_crtc_reverse(to_intel_display(__state), (crtc)) \
                for_each_if((new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc)))

#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state) \
        for_each_intel_crtc(to_intel_display(__state), (crtc)) \
                for_each_if(((old_crtc_state) = intel_atomic_get_old_crtc_state((__state), (crtc)), \
                             (new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc))))

#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state) \
        for_each_intel_crtc_reverse(to_intel_display(__state), (crtc)) \
                for_each_if(((old_crtc_state) = intel_atomic_get_old_crtc_state((__state), (crtc)), \
                             (new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc))))

#define intel_atomic_crtc_state_for_each_plane_state( \
                  plane, plane_state, \
                  crtc_state) \
        for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
                                ((crtc_state)->uapi.plane_mask)) \
                for_each_if ((plane_state = \
                              to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))

#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
        for ((__i) = 0; \
             (__i) < (__state)->base.num_connector; \
             (__i)++) \
                for_each_if ((__state)->base.connectors[__i].ptr && \
                             ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
                             (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

#define __for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \
        for (int (i) = 0; \
             (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
             (i)++) \
                for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))

#define __for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \
        for (int (i) = (I915_MAX_PIPES * 2 - 1); \
             (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
             (i)--) \
                for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))

#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state) \
        __for_each_crtc_in_masks(display, crtc, \
                                 _intel_modeset_primary_pipes(crtc_state), \
                                 _intel_modeset_secondary_pipes(crtc_state), \
                                 __UNIQUE_ID(i))

#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state) \
        __for_each_crtc_in_masks_reverse(display, crtc,                 \
                                         _intel_modeset_primary_pipes(crtc_state), \
                                         _intel_modeset_secondary_pipes(crtc_state), \
                                         __UNIQUE_ID(i))

int intel_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state);
u8 intel_calc_enabled_pipes(struct intel_atomic_state *state,
                            u8 enabled_pipes);
u8 intel_calc_active_pipes(struct intel_atomic_state *state,
                           u8 active_pipes);
void intel_link_compute_m_n(u16 bpp, int nlanes,
                            int pixel_clock, int link_clock,
                            int bw_overhead,
                            struct intel_link_m_n *m_n);
u32 intel_plane_fb_max_stride(struct intel_display *display,
                              const struct drm_format_info *info,
                              u64 modifier);
u32 intel_dumb_fb_max_stride(struct drm_device *drm,
                             u32 pixel_format, u64 modifier);
enum drm_mode_status
intel_mode_valid_max_plane_size(struct intel_display *display,
                                const struct drm_display_mode *mode,
                                int num_joined_pipes);
enum drm_mode_status
intel_cpu_transcoder_mode_valid(struct intel_display *display,
                                const struct drm_display_mode *mode);
enum phy intel_port_to_phy(struct intel_display *display, enum port port);
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
bool is_trans_port_sync_master(const struct intel_crtc_state *state);
u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);
u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);
struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
                               const struct intel_crtc_state *pipe_config,
                               bool fastset);

void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
bool intel_has_pending_fb_unpin(struct intel_display *display);
void intel_display_flush_cleanup_work(struct intel_display *display);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
void intel_encoder_get_config(struct intel_encoder *encoder,
                              struct intel_crtc_state *crtc_state);
bool intel_phy_is_combo(struct intel_display *display, enum phy phy);
bool intel_phy_is_tc(struct intel_display *display, enum phy phy);
bool intel_phy_is_snps(struct intel_display *display, enum phy phy);
enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);
enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port);

enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
bool intel_encoder_is_combo(struct intel_encoder *encoder);
bool intel_encoder_is_snps(struct intel_encoder *encoder);
bool intel_encoder_is_tc(struct intel_encoder *encoder);
enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);

int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);

bool intel_fuzzy_clock_check(int clock1, int clock2);

void intel_zero_m_n(struct intel_link_m_n *m_n);
void intel_set_m_n(struct intel_display *display,
                   const struct intel_link_m_n *m_n,
                   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
                   intel_reg_t link_m_reg, intel_reg_t link_n_reg);
void intel_get_m_n(struct intel_display *display,
                   struct intel_link_m_n *m_n,
                   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
                   intel_reg_t link_m_reg, intel_reg_t link_n_reg);
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
                                    enum transcoder transcoder);
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
                                    enum transcoder cpu_transcoder,
                                    const struct intel_link_m_n *m_n);
void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
                                    enum transcoder cpu_transcoder,
                                    const struct intel_link_m_n *m_n);
void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
                                    enum transcoder cpu_transcoder,
                                    struct intel_link_m_n *m_n);
void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
                                    enum transcoder cpu_transcoder,
                                    struct intel_link_m_n *m_n);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
int intel_max_uncompressed_dotclock(struct intel_display *display);
enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port);
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
                                  struct intel_crtc_state *crtc_state);
int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);

struct intel_encoder *
intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
                           const struct intel_crtc_state *crtc_state);
void intel_plane_disable_noatomic(struct intel_crtc *crtc,
                                  struct intel_plane *plane);
void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
                             struct intel_plane_state *plane_state,
                             bool visible);
void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);

bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
                              struct intel_crtc *crtc);

int intel_display_min_pipe_bpp(void);
int intel_display_max_pipe_bpp(struct intel_display *display);

/* modesetting */
int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
                                      const char *reason, u8 pipe_mask);
int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
                                 const char *reason);
int intel_modeset_commit_pipes(struct intel_display *display,
                               u8 pipe_mask,
                               struct drm_modeset_acquire_ctx *ctx);
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
                                          struct intel_power_domain_mask *old_domains);
void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
                                          struct intel_power_domain_mask *domains);

/* interface for intel_display_driver.c */
void intel_init_display_hooks(struct intel_display *display);
void intel_setup_outputs(struct intel_display *display);
int intel_initial_commit(struct intel_display *display);
void intel_panel_sanitize_ssc(struct intel_display *display);
enum drm_mode_status intel_mode_valid(struct drm_device *dev,
                                      const struct drm_display_mode *mode);
int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_commit *_state,
                        bool nonblock);

/* modesetting asserts */
void assert_transcoder(struct intel_display *display,
                       enum transcoder cpu_transcoder, bool state);
#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)

bool assert_port_valid(struct intel_display *display, enum port port);

/*
 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
 * state sanity checks to check for unexpected conditions which may not
 * necessarily be a user visible problem. This will either drm_WARN() or
 * drm_err() depending on the verbose_state_checks module param, to enable
 * distros and users to tailor their preferred amount of i915 abrt spam.
 */
#define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({    \
        int __ret_warn_on = !!(condition);                              \
        if (unlikely(__ret_warn_on))                                    \
                if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
                        drm_err((__display)->drm, format);              \
        unlikely(__ret_warn_on);                                        \
})

bool intel_scanout_needs_vtd_wa(struct intel_display *display);
int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);

#endif