crypto/libressl/crypto/aes/aes_core.c

1200

static const u32 rcon[] = {

crypto/libressl/crypto/aes/aes_core.c

121

static const u32 Te1[256] = {

crypto/libressl/crypto/aes/aes_core.c

1213

u32 *rk;

crypto/libressl/crypto/aes/aes_core.c

1215

u32 temp;

crypto/libressl/crypto/aes/aes_core.c

1315

u32 *rk;

crypto/libressl/crypto/aes/aes_core.c

1317

u32 temp;

crypto/libressl/crypto/aes/aes_core.c

1345

u32 tp1, tp2, tp4, tp8, tp9, tpb, tpd, tpe, m;

crypto/libressl/crypto/aes/aes_core.c

187

static const u32 Te2[256] = {

crypto/libressl/crypto/aes/aes_core.c

253

static const u32 Te3[256] = {

crypto/libressl/crypto/aes/aes_core.c

320

static const u32 Td0[256] = {

crypto/libressl/crypto/aes/aes_core.c

386

static const u32 Td1[256] = {

crypto/libressl/crypto/aes/aes_core.c

452

static const u32 Td2[256] = {

crypto/libressl/crypto/aes/aes_core.c

518

static const u32 Td3[256] = {

crypto/libressl/crypto/aes/aes_core.c

55

static const u32 Te0[256] = {

crypto/libressl/crypto/aes/aes_core.c

618

static const u32 rcon[] = {

crypto/libressl/crypto/aes/aes_core.c

630

u32 *rk;

crypto/libressl/crypto/aes/aes_core.c

632

u32 temp;

crypto/libressl/crypto/aes/aes_core.c

731

u32 *rk;

crypto/libressl/crypto/aes/aes_core.c

733

u32 temp;

crypto/libressl/crypto/aes/aes_core.c

791

const u32 *rk;

crypto/libressl/crypto/aes/aes_core.c

792

u32 s0, s1, s2, s3, t0, t1, t2, t3;

crypto/libressl/crypto/aes/aes_core.c

981

const u32 *rk;

crypto/libressl/crypto/aes/aes_core.c

982

u32 s0, s1, s2, s3, t0, t1, t2, t3;

crypto/libressl/crypto/aes/aes_locl.h

67

#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))

crypto/libressl/crypto/camellia/camellia.c

102

# define LeftRotate(x,s) ({u32 ret; asm ("rlwinm %0,%1,%2,0,31":"=r"(ret):"r"(x),"I"(s)); ret; })

crypto/libressl/crypto/camellia/camellia.c

114

# define GETU32(p) (((u32)(p)[0] << 24) ^ ((u32)(p)[1] << 16) ^ ((u32)(p)[2] << 8) ^ ((u32)(p)[3]))

crypto/libressl/crypto/camellia/camellia.c

123

static const u32 Camellia_SBOX[][256] = {

crypto/libressl/crypto/camellia/camellia.c

299

static const u32 SIGMA[] = {

crypto/libressl/crypto/camellia/camellia.c

314

u32 _t0, _t1, _t2, _t3; \

crypto/libressl/crypto/camellia/camellia.c

339

u32 _t0 = _s0 >> (32 - _n); \

crypto/libressl/crypto/camellia/camellia.c

349

u32 s0, s1, s2, s3;

crypto/libressl/crypto/camellia/camellia.c

468

u32 s0, s1, s2, s3;

crypto/libressl/crypto/camellia/camellia.c

469

const u32 *k = keyTable, *kend = keyTable + grandRounds * 16;

crypto/libressl/crypto/camellia/camellia.c

520

u32 s0, s1, s2, s3;

crypto/libressl/crypto/camellia/camellia.c

521

const u32 *k = keyTable+grandRounds * 16, *kend = keyTable+4;

crypto/libressl/crypto/camellia/camellia.c

96

# define RightRotate(x,s) ({u32 ret; asm ("rorl %1,%0":"=r"(ret):"I"(s),"0"(x):"cc"); ret; })

crypto/libressl/crypto/camellia/camellia.c

97

# define LeftRotate(x,s) ({u32 ret; asm ("roll %1,%0":"=r"(ret):"I"(s),"0"(x):"cc"); ret; })

crypto/libressl/crypto/camellia/camellia.c

98

# define GETU32(p) ({u32 r=*(const u32 *)(p); asm("bswapl %0":"=r"(r):"0"(r)); r; })

crypto/libressl/crypto/camellia/camellia.c

99

# define PUTU32(p,v) ({u32 r=(v); asm("bswapl %0":"=r"(r):"0"(r)); *(u32 *)(p)=r; })

crypto/libressl/crypto/chacha/chacha-merged.c

123

chacha_encrypt_bytes(chacha_ctx *x, const u8 *m, u8 *c, u32 bytes)

crypto/libressl/crypto/chacha/chacha-merged.c

125

u32 x0, x1, x2, x3, x4, x5, x6, x7;

crypto/libressl/crypto/chacha/chacha-merged.c

126

u32 x8, x9, x10, x11, x12, x13, x14, x15;

crypto/libressl/crypto/chacha/chacha-merged.c

127

u32 j0, j1, j2, j3, j4, j5, j6, j7;

crypto/libressl/crypto/chacha/chacha-merged.c

128

u32 j8, j9, j10, j11, j12, j13, j14, j15;

crypto/libressl/crypto/chacha/chacha-merged.c

131

u32 i;

crypto/libressl/crypto/chacha/chacha-merged.c

24

u32 input[16];

crypto/libressl/crypto/chacha/chacha-merged.c

29

static inline void chacha_keysetup(struct chacha_ctx *x, const u8 *k, u32 kbits)

crypto/libressl/crypto/chacha/chacha-merged.c

36

u8 *c, u32 bytes)

crypto/libressl/crypto/chacha/chacha-merged.c

46

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

crypto/libressl/crypto/chacha/chacha-merged.c

52

(((u32)((p)[0])) | \

crypto/libressl/crypto/chacha/chacha-merged.c

53

((u32)((p)[1]) << 8) | \

crypto/libressl/crypto/chacha/chacha-merged.c

54

((u32)((p)[2]) << 16) | \

crypto/libressl/crypto/chacha/chacha-merged.c

55

((u32)((p)[3]) << 24))

crypto/libressl/crypto/chacha/chacha-merged.c

89

chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)

crypto/libressl/crypto/modes/ctr128.c

178

u32 n=12;

crypto/libressl/crypto/modes/ctr128.c

223

ctr32 += (u32)blocks;

crypto/libressl/crypto/modes/ctr128.c

68

u32 n=16;

crypto/libressl/crypto/modes/gcm128.c

240

u32 v;

crypto/libressl/crypto/modes/gcm128.c

241

v = (u32)(Z.hi>>32); PUTU32(p,v);

crypto/libressl/crypto/modes/gcm128.c

242

v = (u32)(Z.hi); PUTU32(p+4,v);

crypto/libressl/crypto/modes/gcm128.c

243

v = (u32)(Z.lo>>32); PUTU32(p+8,v);

crypto/libressl/crypto/modes/gcm128.c

244

v = (u32)(Z.lo); PUTU32(p+12,v);

crypto/libressl/crypto/modes/gcm128.c

382

u32 v;

crypto/libressl/crypto/modes/gcm128.c

383

v = (u32)(Z.hi>>32); PUTU32(p,v);

crypto/libressl/crypto/modes/gcm128.c

384

v = (u32)(Z.hi); PUTU32(p+4,v);

crypto/libressl/crypto/modes/gcm128.c

385

v = (u32)(Z.lo>>32); PUTU32(p+8,v);

crypto/libressl/crypto/modes/gcm128.c

386

v = (u32)(Z.lo); PUTU32(p+12,v);

crypto/libressl/crypto/modes/gcm128.c

550

u32 v;

crypto/libressl/crypto/modes/gcm128.c

551

v = (u32)(Z.hi>>32); PUTU32(p,v);

crypto/libressl/crypto/modes/gcm128.c

552

v = (u32)(Z.hi); PUTU32(p+4,v);

crypto/libressl/crypto/modes/gcm128.c

553

v = (u32)(Z.lo>>32); PUTU32(p+8,v);

crypto/libressl/crypto/modes/gcm128.c

554

v = (u32)(Z.lo); PUTU32(p+12,v);

crypto/libressl/crypto/modes/gcm128.c

621

u32 v;

crypto/libressl/crypto/modes/gcm128.c

622

v = (u32)(Z.hi>>32); PUTU32(p,v);

crypto/libressl/crypto/modes/gcm128.c

623

v = (u32)(Z.hi); PUTU32(p+4,v);

crypto/libressl/crypto/modes/gcm128.c

624

v = (u32)(Z.lo>>32); PUTU32(p+8,v);

crypto/libressl/crypto/modes/gcm128.c

625

v = (u32)(Z.lo); PUTU32(p+12,v);

crypto/libressl/crypto/modes/gcm128.c

66

#define GETU32(p) BSWAP4(*(const u32 *)(p))

crypto/libressl/crypto/modes/gcm128.c

68

#define PUTU32(p,v) *(u32 *)(p) = BSWAP4(v)

crypto/libressl/crypto/modes/gcm128.c

79

u32 T = 0xe1000000U & (0-(u32)(V.lo&1)); \

crypto/libressl/crypto/modes/modes_lcl.h

36

# define BSWAP4(x) ({ u32 ret=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

40

# define BSWAP8(x) ({ u32 lo=(u64)(x)>>32,hi=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

44

# define BSWAP4(x) ({ u32 ret=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

49

# define BSWAP8(x) ({ u32 lo=(u64)(x)>>32,hi=(x); \

crypto/libressl/crypto/modes/modes_lcl.h

53

# define BSWAP4(x) ({ u32 ret; \

crypto/libressl/crypto/modes/modes_lcl.h

55

: "=r"(ret) : "r"((u32)(x))); \

crypto/libressl/crypto/modes/modes_lcl.h

63

#define GETU32(p) BSWAP4(*(const u32 *)(p))

crypto/libressl/crypto/modes/modes_lcl.h

64

#define PUTU32(p,v) *(u32 *)(p) = BSWAP4(v)

crypto/libressl/crypto/modes/modes_lcl.h

66

#define GETU32(p) ((u32)(p)[0]<<24|(u32)(p)[1]<<16|(u32)(p)[2]<<8|(u32)(p)[3])

crypto/libressl/crypto/modes/modes_lcl.h

85

union { u64 u[2]; u32 d[4]; u8 c[16]; size_t t[16/sizeof(size_t)]; }

crypto/libressl/crypto/modes/xts128.c

67

union { u64 u[2]; u32 d[4]; u8 c[16]; } tweak, scratch;

crypto/openssh/chacha.c

21

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

crypto/openssh/chacha.c

27

(((u32)((p)[0]) ) | \

crypto/openssh/chacha.c

28

((u32)((p)[1]) << 8) | \

crypto/openssh/chacha.c

29

((u32)((p)[2]) << 16) | \

crypto/openssh/chacha.c

30

((u32)((p)[3]) << 24))

crypto/openssh/chacha.c

55

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

crypto/openssh/chacha.c

89

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

crypto/openssh/chacha.c

91

u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15;

crypto/openssh/chacha.c

92

u32 j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15;

crypto/openssh/cipher-aesctr.c

33

aesctr_inc(u8 *ctr, u32 len)

crypto/openssh/cipher-aesctr.c

57

aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits)

crypto/openssh/cipher-aesctr.c

69

aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes)

crypto/openssh/cipher-aesctr.c

71

u32 n = 0;

crypto/openssh/cipher-aesctr.h

27

u32 ek[4*(AES_MAXROUNDS + 1)]; /* encrypt key schedule */

crypto/openssh/cipher-aesctr.h

31

void aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits);

crypto/openssh/cipher-aesctr.h

33

void aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes);

crypto/openssh/rijndael.c

117

static const u32 Te1[256] = {

crypto/openssh/rijndael.c

183

static const u32 Te2[256] = {

crypto/openssh/rijndael.c

249

static const u32 Te3[256] = {

crypto/openssh/rijndael.c

316

static const u32 Td0[256] = {

crypto/openssh/rijndael.c

382

static const u32 Td1[256] = {

crypto/openssh/rijndael.c

448

static const u32 Td2[256] = {

crypto/openssh/rijndael.c

51

static const u32 Te0[256] = {

crypto/openssh/rijndael.c

514

static const u32 Td3[256] = {

crypto/openssh/rijndael.c

615

static const u32 rcon[] = {

crypto/openssh/rijndael.c

621

#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))

crypto/openssh/rijndael.c

630

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

crypto/openssh/rijndael.c

633

u32 temp;

crypto/openssh/rijndael.c

718

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

crypto/openssh/rijndael.c

721

u32 temp;

crypto/openssh/rijndael.c

762

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

crypto/openssh/rijndael.c

765

u32 s0, s1, s2, s3, t0, t1, t2, t3;

crypto/openssh/rijndael.c

947

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

crypto/openssh/rijndael.c

950

u32 s0, s1, s2, s3, t0, t1, t2, t3;

crypto/openssh/rijndael.h

47

u32 ek[4*(AES_MAXROUNDS + 1)]; /* encrypt key schedule */

crypto/openssh/rijndael.h

48

u32 dk[4*(AES_MAXROUNDS + 1)]; /* decrypt key schedule */

crypto/openssh/umac.c

173

rijndaelEncrypt((u32 *)(int_key), AES_ROUNDS, (u8 *)(in), (u8 *)(out))

crypto/openssh/umac.c

175

rijndaelKeySetupEnc((u32 *)(int_key), (const unsigned char *)(key), \

lib/i18n_module/UTF7/citrus_utf7.c

245

uint32_t u32;

lib/i18n_module/UTF7/citrus_utf7.c

265

u32 = (uint32_t)hi;

lib/i18n_module/UTF7/citrus_utf7.c

282

u32 = (hi << 10 | lo) + SRG_BASE;

lib/i18n_module/UTF7/citrus_utf7.c

286

*pwc = (wchar_t)u32;

lib/i18n_module/UTF7/citrus_utf7.c

287

if (u32 == (uint32_t)0) {

lib/i18n_module/UTF7/citrus_utf7.c

350

uint32_t u32;

lib/i18n_module/UTF7/citrus_utf7.c

355

u32 = (uint32_t)wchar;

lib/i18n_module/UTF7/citrus_utf7.c

356

if (u32 <= UTF16_MAX) {

lib/i18n_module/UTF7/citrus_utf7.c

357

u16[0] = (uint16_t)u32;

lib/i18n_module/UTF7/citrus_utf7.c

359

} else if (u32 <= UTF32_MAX) {

lib/i18n_module/UTF7/citrus_utf7.c

360

u32 -= SRG_BASE;

lib/i18n_module/UTF7/citrus_utf7.c

361

u16[0] = (u32 >> 10) + HISRG_MIN;

lib/i18n_module/UTF7/citrus_utf7.c

362

u16[1] = ((uint16_t)(u32 & UINT32_C(0x3ff))) + LOSRG_MIN;

sys/crypto/chacha20/chacha.c

111

chacha_encrypt_bytes(chacha_ctx *x, const u8 *m, u8 *c, u32 bytes)

sys/crypto/chacha20/chacha.c

113

u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15;

sys/crypto/chacha20/chacha.c

114

u32 j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15;

sys/crypto/chacha20/chacha.c

117

u32 i;

sys/crypto/chacha20/chacha.c

22

#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))

sys/crypto/chacha20/chacha.c

266

u32 x[16] = {

sys/crypto/chacha20/chacha.c

28

(((u32)((p)[0]) ) | \

sys/crypto/chacha20/chacha.c

284

u32 i;

sys/crypto/chacha20/chacha.c

29

((u32)((p)[1]) << 8) | \

sys/crypto/chacha20/chacha.c

30

((u32)((p)[2]) << 16) | \

sys/crypto/chacha20/chacha.c

31

((u32)((p)[3]) << 24))

sys/crypto/chacha20/chacha.c

56

chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)

sys/crypto/rijndael/rijndael-alg-fst.c

1043

void rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16], u8 pt[16]) {

sys/crypto/rijndael/rijndael-alg-fst.c

1044

u32 s0, s1, s2, s3, t0, t1, t2, t3;

sys/crypto/rijndael/rijndael-alg-fst.c

122

static const u32 Te1[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

188

static const u32 Te2[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

254

static const u32 Te3[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

321

static const u32 Te4[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

387

static const u32 Td0[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

453

static const u32 Td1[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

519

static const u32 Td2[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

56

static const u32 Te0[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

586

static const u32 Td3[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

652

static const u32 Td4[256] = {

sys/crypto/rijndael/rijndael-alg-fst.c

718

static const u32 rcon[] = {

sys/crypto/rijndael/rijndael-alg-fst.c

726

#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3]))

sys/crypto/rijndael/rijndael-alg-fst.c

734

int rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits) {

sys/crypto/rijndael/rijndael-alg-fst.c

736

u32 temp;

sys/crypto/rijndael/rijndael-alg-fst.c

822

int rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits) {

sys/crypto/rijndael/rijndael-alg-fst.c

824

u32 temp;

sys/crypto/rijndael/rijndael-alg-fst.c

862

void rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16], u8 ct[16]) {

sys/crypto/rijndael/rijndael-alg-fst.c

863

u32 s0, s1, s2, s3, t0, t1, t2, t3;

sys/dev/disk/sym/sym_defs.h

150

u32 boot_crc;

sys/dev/disk/sym/sym_defs.h

374

/*1c*/ u32 nc_temp; /* ### Temporary stack */

sys/dev/disk/sym/sym_defs.h

387

/*24*/ u32 nc_dbc; /* ### Byte count and command */

sys/dev/disk/sym/sym_defs.h

388

/*28*/ u32 nc_dnad; /* ### Next command register */

sys/dev/disk/sym/sym_defs.h

389

/*2c*/ u32 nc_dsp; /* --> Script Pointer */

sys/dev/disk/sym/sym_defs.h

390

/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */

sys/dev/disk/sym/sym_defs.h

418

/*3c*/ u32 nc_adder;

sys/dev/disk/sym/sym_defs.h

495

/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */

sys/dev/disk/sym/sym_defs.h

496

/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */

sys/dev/disk/sym/sym_defs.h

497

/*a8*/ u32 nc_sfs; /* Script Fetch Selector */

sys/dev/disk/sym/sym_defs.h

498

/*ac*/ u32 nc_drs; /* DSA Relative Selector */

sys/dev/disk/sym/sym_defs.h

499

/*b0*/ u32 nc_sbms; /* Static Block Move Selector */

sys/dev/disk/sym/sym_defs.h

500

/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */

sys/dev/disk/sym/sym_defs.h

501

/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */

sys/dev/disk/sym/sym_defs.h

513

/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */

sys/dev/disk/sym/sym_defs.h

514

/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */

sys/dev/disk/sym/sym_defs.h

524

/*d0*/ u32 nc_esa; /* Entry Storage Address */

sys/dev/disk/sym/sym_defs.h

529

/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */

sys/dev/disk/sym/sym_defs.h

530

/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */

sys/dev/disk/sym/sym_defs.h

536

/*e4*/ u32 nc_crcdata; /* CRC data register */

sys/dev/disk/sym/sym_defs.h

537

/*e8*/ u32 nc_e8_;

sys/dev/disk/sym/sym_defs.h

538

/*ec*/ u32 nc_ec_;

sys/dev/disk/sym/sym_defs.h

552

typedef u32 symcmd;

sys/dev/disk/sym/sym_defs.h

602

u32 size;

sys/dev/disk/sym/sym_defs.h

603

u32 addr;

sys/dev/disk/sym/sym_defs.h

634

#define SCR_ID(id) (((u32)(id)) << 16)

sys/dev/disk/sym/sym_fw.h

118

SYM_GEN_FW_A(u32)

sys/dev/disk/sym/sym_fw.h

121

SYM_GEN_FW_B(u32)

sys/dev/disk/sym/sym_fw.h

122

SYM_GEN_B(u32, start64)

sys/dev/disk/sym/sym_fw.h

123

SYM_GEN_B(u32, pm_handle)

sys/dev/disk/sym/sym_fw.h

139

const u32 *a_base;/* Pointer to script A template */

sys/dev/disk/sym/sym_fw.h

143

const u32 *b_base;/* Pointer to script B template */

sys/dev/disk/sym/sym_fw.h

158

(const u32 *) &fw##a_scr, sizeof(fw##a_scr), &fw##a_ofs,\

sys/dev/disk/sym/sym_fw.h

159

(const u32 *) &fw##b_scr, sizeof(fw##b_scr), &fw##b_ofs,\

sys/dev/disk/sym/sym_fw1.h

100

u32 msg_in [ 2];

sys/dev/disk/sym/sym_fw1.h

101

u32 msg_in2 [ 10];

sys/dev/disk/sym/sym_fw1.h

103

u32 status [ 14];

sys/dev/disk/sym/sym_fw1.h

105

u32 status [ 10];

sys/dev/disk/sym/sym_fw1.h

107

u32 complete [ 9];

sys/dev/disk/sym/sym_fw1.h

108

u32 complete2 [ 8];

sys/dev/disk/sym/sym_fw1.h

109

u32 _sms_a40 [ 12];

sys/dev/disk/sym/sym_fw1.h

110

u32 complete_error [ 5];

sys/dev/disk/sym/sym_fw1.h

111

u32 done [ 5];

sys/dev/disk/sym/sym_fw1.h

112

u32 _sms_a50 [ 5];

sys/dev/disk/sym/sym_fw1.h

113

u32 _sms_a60 [ 2];

sys/dev/disk/sym/sym_fw1.h

114

u32 done_end [ 4];

sys/dev/disk/sym/sym_fw1.h

115

u32 save_dp [ 9];

sys/dev/disk/sym/sym_fw1.h

116

u32 restore_dp [ 5];

sys/dev/disk/sym/sym_fw1.h

117

u32 disconnect [ 20];

sys/dev/disk/sym/sym_fw1.h

118

u32 disconnect2 [ 5];

sys/dev/disk/sym/sym_fw1.h

119

u32 _sms_a65 [ 3];

sys/dev/disk/sym/sym_fw1.h

121

u32 idle [ 4];

sys/dev/disk/sym/sym_fw1.h

123

u32 idle [ 2];

sys/dev/disk/sym/sym_fw1.h

126

u32 ungetjob [ 7];

sys/dev/disk/sym/sym_fw1.h

128

u32 ungetjob [ 5];

sys/dev/disk/sym/sym_fw1.h

130

u32 reselect [ 4];

sys/dev/disk/sym/sym_fw1.h

131

u32 reselected [ 19];

sys/dev/disk/sym/sym_fw1.h

132

u32 _sms_a70 [ 6];

sys/dev/disk/sym/sym_fw1.h

133

u32 _sms_a80 [ 4];

sys/dev/disk/sym/sym_fw1.h

134

u32 reselected1 [ 25];

sys/dev/disk/sym/sym_fw1.h

135

u32 _sms_a90 [ 4];

sys/dev/disk/sym/sym_fw1.h

136

u32 resel_lun0 [ 7];

sys/dev/disk/sym/sym_fw1.h

137

u32 _sms_a100 [ 4];

sys/dev/disk/sym/sym_fw1.h

138

u32 resel_tag [ 8];

sys/dev/disk/sym/sym_fw1.h

140

u32 _sms_a110 [ 23];

sys/dev/disk/sym/sym_fw1.h

142

u32 _sms_a110 [ 17];

sys/dev/disk/sym/sym_fw1.h

144

u32 _sms_a110 [ 13];

sys/dev/disk/sym/sym_fw1.h

146

u32 _sms_a120 [ 2];

sys/dev/disk/sym/sym_fw1.h

147

u32 resel_go [ 4];

sys/dev/disk/sym/sym_fw1.h

148

u32 _sms_a130 [ 7];

sys/dev/disk/sym/sym_fw1.h

149

u32 resel_dsa [ 2];

sys/dev/disk/sym/sym_fw1.h

150

u32 resel_dsa1 [ 4];

sys/dev/disk/sym/sym_fw1.h

151

u32 _sms_a140 [ 10];

sys/dev/disk/sym/sym_fw1.h

152

u32 resel_no_tag [ 4];

sys/dev/disk/sym/sym_fw1.h

153

u32 _sms_a145 [ 7];

sys/dev/disk/sym/sym_fw1.h

154

u32 data_in [SYM_CONF_MAX_SG * 2];

sys/dev/disk/sym/sym_fw1.h

155

u32 data_in2 [ 4];

sys/dev/disk/sym/sym_fw1.h

156

u32 data_out [SYM_CONF_MAX_SG * 2];

sys/dev/disk/sym/sym_fw1.h

157

u32 data_out2 [ 4];

sys/dev/disk/sym/sym_fw1.h

158

u32 pm0_data [ 12];

sys/dev/disk/sym/sym_fw1.h

159

u32 pm0_data_out [ 6];

sys/dev/disk/sym/sym_fw1.h

160

u32 pm0_data_end [ 7];

sys/dev/disk/sym/sym_fw1.h

161

u32 pm_data_end [ 4];

sys/dev/disk/sym/sym_fw1.h

162

u32 _sms_a150 [ 4];

sys/dev/disk/sym/sym_fw1.h

163

u32 pm1_data [ 12];

sys/dev/disk/sym/sym_fw1.h

164

u32 pm1_data_out [ 6];

sys/dev/disk/sym/sym_fw1.h

165

u32 pm1_data_end [ 9];

sys/dev/disk/sym/sym_fw1.h

173

u32 no_data [ 2];

sys/dev/disk/sym/sym_fw1.h

174

u32 sel_for_abort [ 18];

sys/dev/disk/sym/sym_fw1.h

175

u32 sel_for_abort_1 [ 2];

sys/dev/disk/sym/sym_fw1.h

176

u32 msg_in_etc [ 12];

sys/dev/disk/sym/sym_fw1.h

177

u32 msg_received [ 5];

sys/dev/disk/sym/sym_fw1.h

178

u32 msg_weird_seen [ 5];

sys/dev/disk/sym/sym_fw1.h

179

u32 msg_extended [ 17];

sys/dev/disk/sym/sym_fw1.h

180

u32 _sms_b10 [ 4];

sys/dev/disk/sym/sym_fw1.h

181

u32 msg_bad [ 6];

sys/dev/disk/sym/sym_fw1.h

182

u32 msg_weird [ 4];

sys/dev/disk/sym/sym_fw1.h

183

u32 msg_weird1 [ 8];

sys/dev/disk/sym/sym_fw1.h

184

u32 wdtr_resp [ 6];

sys/dev/disk/sym/sym_fw1.h

185

u32 send_wdtr [ 4];

sys/dev/disk/sym/sym_fw1.h

186

u32 sdtr_resp [ 6];

sys/dev/disk/sym/sym_fw1.h

187

u32 send_sdtr [ 4];

sys/dev/disk/sym/sym_fw1.h

188

u32 ppr_resp [ 6];

sys/dev/disk/sym/sym_fw1.h

189

u32 send_ppr [ 4];

sys/dev/disk/sym/sym_fw1.h

190

u32 nego_bad_phase [ 4];

sys/dev/disk/sym/sym_fw1.h

191

u32 msg_out [ 4];

sys/dev/disk/sym/sym_fw1.h

192

u32 msg_out_done [ 4];

sys/dev/disk/sym/sym_fw1.h

193

u32 data_ovrun [ 3];

sys/dev/disk/sym/sym_fw1.h

194

u32 data_ovrun1 [ 22];

sys/dev/disk/sym/sym_fw1.h

195

u32 data_ovrun2 [ 8];

sys/dev/disk/sym/sym_fw1.h

196

u32 abort_resel [ 16];

sys/dev/disk/sym/sym_fw1.h

197

u32 resend_ident [ 4];

sys/dev/disk/sym/sym_fw1.h

198

u32 ident_break [ 4];

sys/dev/disk/sym/sym_fw1.h

199

u32 ident_break_atn [ 4];

sys/dev/disk/sym/sym_fw1.h

200

u32 sdata_in [ 6];

sys/dev/disk/sym/sym_fw1.h

201

u32 resel_bad_lun [ 4];

sys/dev/disk/sym/sym_fw1.h

202

u32 bad_i_t_l [ 4];

sys/dev/disk/sym/sym_fw1.h

203

u32 bad_i_t_l_q [ 4];

sys/dev/disk/sym/sym_fw1.h

204

u32 bad_status [ 7];

sys/dev/disk/sym/sym_fw1.h

205

u32 wsr_ma_helper [ 4];

sys/dev/disk/sym/sym_fw1.h

208

u32 zero [ 1];

sys/dev/disk/sym/sym_fw1.h

209

u32 scratch [ 1];

sys/dev/disk/sym/sym_fw1.h

210

u32 scratch1 [ 1];

sys/dev/disk/sym/sym_fw1.h

211

u32 prev_done [ 1];

sys/dev/disk/sym/sym_fw1.h

212

u32 done_pos [ 1];

sys/dev/disk/sym/sym_fw1.h

213

u32 nextjob [ 1];

sys/dev/disk/sym/sym_fw1.h

214

u32 startpos [ 1];

sys/dev/disk/sym/sym_fw1.h

215

u32 targtbl [ 1];

sys/dev/disk/sym/sym_fw1.h

218

u32 snooptest [ 9];

sys/dev/disk/sym/sym_fw1.h

219

u32 snoopend [ 2];

sys/dev/disk/sym/sym_fw1.h

76

u32 start [ 11];

sys/dev/disk/sym/sym_fw1.h

77

u32 getjob_begin [ 4];

sys/dev/disk/sym/sym_fw1.h

78

u32 _sms_a10 [ 5];

sys/dev/disk/sym/sym_fw1.h

79

u32 getjob_end [ 4];

sys/dev/disk/sym/sym_fw1.h

80

u32 _sms_a20 [ 4];

sys/dev/disk/sym/sym_fw1.h

81

u32 select [ 8];

sys/dev/disk/sym/sym_fw1.h

82

u32 _sms_a30 [ 8];

sys/dev/disk/sym/sym_fw1.h

83

u32 wf_sel_done [ 2];

sys/dev/disk/sym/sym_fw1.h

84

u32 send_ident [ 2];

sys/dev/disk/sym/sym_fw1.h

86

u32 select2 [ 8];

sys/dev/disk/sym/sym_fw1.h

88

u32 select2 [ 2];

sys/dev/disk/sym/sym_fw1.h

90

u32 command [ 2];

sys/dev/disk/sym/sym_fw1.h

91

u32 dispatch [ 28];

sys/dev/disk/sym/sym_fw1.h

92

u32 sel_no_cmd [ 10];

sys/dev/disk/sym/sym_fw1.h

93

u32 init [ 6];

sys/dev/disk/sym/sym_fw1.h

94

u32 clrack [ 4];

sys/dev/disk/sym/sym_fw1.h

95

u32 disp_status [ 4];

sys/dev/disk/sym/sym_fw1.h

96

u32 datai_done [ 26];

sys/dev/disk/sym/sym_fw1.h

97

u32 datao_done [ 12];

sys/dev/disk/sym/sym_fw1.h

98

u32 datai_phase [ 2];

sys/dev/disk/sym/sym_fw1.h

99

u32 datao_phase [ 2];

sys/dev/disk/sym/sym_fw2.h

101

u32 status [ 14];

sys/dev/disk/sym/sym_fw2.h

103

u32 status [ 10];

sys/dev/disk/sym/sym_fw2.h

105

u32 complete [ 8];

sys/dev/disk/sym/sym_fw2.h

106

u32 complete2 [ 12];

sys/dev/disk/sym/sym_fw2.h

107

u32 complete_error [ 4];

sys/dev/disk/sym/sym_fw2.h

108

u32 done [ 14];

sys/dev/disk/sym/sym_fw2.h

109

u32 done_end [ 2];

sys/dev/disk/sym/sym_fw2.h

110

u32 save_dp [ 8];

sys/dev/disk/sym/sym_fw2.h

111

u32 restore_dp [ 4];

sys/dev/disk/sym/sym_fw2.h

112

u32 disconnect [ 20];

sys/dev/disk/sym/sym_fw2.h

114

u32 idle [ 4];

sys/dev/disk/sym/sym_fw2.h

116

u32 idle [ 2];

sys/dev/disk/sym/sym_fw2.h

119

u32 ungetjob [ 6];

sys/dev/disk/sym/sym_fw2.h

121

u32 ungetjob [ 4];

sys/dev/disk/sym/sym_fw2.h

123

u32 reselect [ 4];

sys/dev/disk/sym/sym_fw2.h

124

u32 reselected [ 22];

sys/dev/disk/sym/sym_fw2.h

125

u32 resel_scntl4 [ 20];

sys/dev/disk/sym/sym_fw2.h

126

u32 resel_lun0 [ 6];

sys/dev/disk/sym/sym_fw2.h

128

u32 resel_tag [ 26];

sys/dev/disk/sym/sym_fw2.h

130

u32 resel_tag [ 20];

sys/dev/disk/sym/sym_fw2.h

132

u32 resel_tag [ 16];

sys/dev/disk/sym/sym_fw2.h

134

u32 resel_dsa [ 2];

sys/dev/disk/sym/sym_fw2.h

135

u32 resel_dsa1 [ 6];

sys/dev/disk/sym/sym_fw2.h

136

u32 resel_no_tag [ 6];

sys/dev/disk/sym/sym_fw2.h

137

u32 data_in [SYM_CONF_MAX_SG * 2];

sys/dev/disk/sym/sym_fw2.h

138

u32 data_in2 [ 4];

sys/dev/disk/sym/sym_fw2.h

139

u32 data_out [SYM_CONF_MAX_SG * 2];

sys/dev/disk/sym/sym_fw2.h

140

u32 data_out2 [ 4];

sys/dev/disk/sym/sym_fw2.h

141

u32 pm0_data [ 12];

sys/dev/disk/sym/sym_fw2.h

142

u32 pm0_data_out [ 6];

sys/dev/disk/sym/sym_fw2.h

143

u32 pm0_data_end [ 6];

sys/dev/disk/sym/sym_fw2.h

144

u32 pm1_data [ 12];

sys/dev/disk/sym/sym_fw2.h

145

u32 pm1_data_out [ 6];

sys/dev/disk/sym/sym_fw2.h

146

u32 pm1_data_end [ 6];

sys/dev/disk/sym/sym_fw2.h

154

u32 start64 [ 2];

sys/dev/disk/sym/sym_fw2.h

155

u32 no_data [ 2];

sys/dev/disk/sym/sym_fw2.h

156

u32 sel_for_abort [ 18];

sys/dev/disk/sym/sym_fw2.h

157

u32 sel_for_abort_1 [ 2];

sys/dev/disk/sym/sym_fw2.h

158

u32 msg_in_etc [ 12];

sys/dev/disk/sym/sym_fw2.h

159

u32 msg_received [ 4];

sys/dev/disk/sym/sym_fw2.h

160

u32 msg_weird_seen [ 4];

sys/dev/disk/sym/sym_fw2.h

161

u32 msg_extended [ 20];

sys/dev/disk/sym/sym_fw2.h

162

u32 msg_bad [ 6];

sys/dev/disk/sym/sym_fw2.h

163

u32 msg_weird [ 4];

sys/dev/disk/sym/sym_fw2.h

164

u32 msg_weird1 [ 8];

sys/dev/disk/sym/sym_fw2.h

166

u32 wdtr_resp [ 6];

sys/dev/disk/sym/sym_fw2.h

167

u32 send_wdtr [ 4];

sys/dev/disk/sym/sym_fw2.h

168

u32 sdtr_resp [ 6];

sys/dev/disk/sym/sym_fw2.h

169

u32 send_sdtr [ 4];

sys/dev/disk/sym/sym_fw2.h

170

u32 ppr_resp [ 6];

sys/dev/disk/sym/sym_fw2.h

171

u32 send_ppr [ 4];

sys/dev/disk/sym/sym_fw2.h

172

u32 nego_bad_phase [ 4];

sys/dev/disk/sym/sym_fw2.h

173

u32 msg_out [ 4];

sys/dev/disk/sym/sym_fw2.h

174

u32 msg_out_done [ 4];

sys/dev/disk/sym/sym_fw2.h

175

u32 data_ovrun [ 2];

sys/dev/disk/sym/sym_fw2.h

176

u32 data_ovrun1 [ 22];

sys/dev/disk/sym/sym_fw2.h

177

u32 data_ovrun2 [ 8];

sys/dev/disk/sym/sym_fw2.h

178

u32 abort_resel [ 16];

sys/dev/disk/sym/sym_fw2.h

179

u32 resend_ident [ 4];

sys/dev/disk/sym/sym_fw2.h

180

u32 ident_break [ 4];

sys/dev/disk/sym/sym_fw2.h

181

u32 ident_break_atn [ 4];

sys/dev/disk/sym/sym_fw2.h

182

u32 sdata_in [ 6];

sys/dev/disk/sym/sym_fw2.h

183

u32 resel_bad_lun [ 4];

sys/dev/disk/sym/sym_fw2.h

184

u32 bad_i_t_l [ 4];

sys/dev/disk/sym/sym_fw2.h

185

u32 bad_i_t_l_q [ 4];

sys/dev/disk/sym/sym_fw2.h

186

u32 bad_status [ 6];

sys/dev/disk/sym/sym_fw2.h

187

u32 pm_handle [ 20];

sys/dev/disk/sym/sym_fw2.h

188

u32 pm_handle1 [ 4];

sys/dev/disk/sym/sym_fw2.h

189

u32 pm_save [ 4];

sys/dev/disk/sym/sym_fw2.h

190

u32 pm0_save [ 14];

sys/dev/disk/sym/sym_fw2.h

191

u32 pm1_save [ 14];

sys/dev/disk/sym/sym_fw2.h

194

u32 pm_wsr_handle [ 42];

sys/dev/disk/sym/sym_fw2.h

195

u32 wsr_ma_helper [ 4];

sys/dev/disk/sym/sym_fw2.h

198

u32 zero [ 1];

sys/dev/disk/sym/sym_fw2.h

199

u32 scratch [ 1];

sys/dev/disk/sym/sym_fw2.h

200

u32 pm0_data_addr [ 1];

sys/dev/disk/sym/sym_fw2.h

201

u32 pm1_data_addr [ 1];

sys/dev/disk/sym/sym_fw2.h

202

u32 saved_dsa [ 1];

sys/dev/disk/sym/sym_fw2.h

203

u32 saved_drs [ 1];

sys/dev/disk/sym/sym_fw2.h

204

u32 done_pos [ 1];

sys/dev/disk/sym/sym_fw2.h

205

u32 startpos [ 1];

sys/dev/disk/sym/sym_fw2.h

206

u32 targtbl [ 1];

sys/dev/disk/sym/sym_fw2.h

209

u32 snooptest [ 6];

sys/dev/disk/sym/sym_fw2.h

210

u32 snoopend [ 2];

sys/dev/disk/sym/sym_fw2.h

76

u32 start [ 14];

sys/dev/disk/sym/sym_fw2.h

77

u32 getjob_begin [ 4];

sys/dev/disk/sym/sym_fw2.h

78

u32 getjob_end [ 4];

sys/dev/disk/sym/sym_fw2.h

79

u32 select [ 8];

sys/dev/disk/sym/sym_fw2.h

80

u32 wf_sel_done [ 2];

sys/dev/disk/sym/sym_fw2.h

81

u32 sel_done [ 2];

sys/dev/disk/sym/sym_fw2.h

82

u32 send_ident [ 2];

sys/dev/disk/sym/sym_fw2.h

84

u32 select2 [ 8];

sys/dev/disk/sym/sym_fw2.h

86

u32 select2 [ 2];

sys/dev/disk/sym/sym_fw2.h

88

u32 command [ 2];

sys/dev/disk/sym/sym_fw2.h

89

u32 dispatch [ 28];

sys/dev/disk/sym/sym_fw2.h

90

u32 sel_no_cmd [ 10];

sys/dev/disk/sym/sym_fw2.h

91

u32 init [ 6];

sys/dev/disk/sym/sym_fw2.h

92

u32 clrack [ 4];

sys/dev/disk/sym/sym_fw2.h

93

u32 disp_status [ 4];

sys/dev/disk/sym/sym_fw2.h

94

u32 datai_done [ 26];

sys/dev/disk/sym/sym_fw2.h

95

u32 datao_done [ 12];

sys/dev/disk/sym/sym_fw2.h

96

u32 datai_phase [ 2];

sys/dev/disk/sym/sym_fw2.h

97

u32 datao_phase [ 4];

sys/dev/disk/sym/sym_fw2.h

98

u32 msg_in [ 2];

sys/dev/disk/sym/sym_fw2.h

99

u32 msg_in2 [ 10];

sys/dev/disk/sym/sym_hipd.c

1092

u32 luntbl_sa; /* bus address of this table */

sys/dev/disk/sym/sym_hipd.c

1093

u32 lun0_sa; /* bus address of LCB #0 */

sys/dev/disk/sym/sym_hipd.c

1119

u32 *luntbl; /* LCBs bus address table */

sys/dev/disk/sym/sym_hipd.c

1134

u32 lun_map[(SYM_CONF_MAX_LUN+31)/32];

sys/dev/disk/sym/sym_hipd.c

1140

u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32];

sys/dev/disk/sym/sym_hipd.c

1182

/*0*/ u32 resel_sa;

sys/dev/disk/sym/sym_hipd.c

1188

u32 itl_task_sa;

sys/dev/disk/sym/sym_hipd.c

1193

u32 itlq_tbl_sa;

sys/dev/disk/sym/sym_hipd.c

1211

u32 *itlq_tbl; /* Kernel virtual address */

sys/dev/disk/sym/sym_hipd.c

1244

u32 start; /* Jumped by SCRIPTS after selection */

sys/dev/disk/sym/sym_hipd.c

1245

u32 restart; /* Jumped by SCRIPTS on relection */

sys/dev/disk/sym/sym_hipd.c

1257

u32 ret; /* SCRIPT return address */

sys/dev/disk/sym/sym_hipd.c

1338

u32 savep; /* Jump address to saved data pointer */

sys/dev/disk/sym/sym_hipd.c

1339

u32 lastp; /* SCRIPTS address at end of data */

sys/dev/disk/sym/sym_hipd.c

1340

u32 goalp; /* Not accessed for now from SCRIPTS */

sys/dev/disk/sym/sym_hipd.c

1410

u32 extra_bytes; /* Extraneous bytes transferred */

sys/dev/disk/sym/sym_hipd.c

1444

u32 ccb_ba; /* BUS address of this CCB */

sys/dev/disk/sym/sym_hipd.c

1452

u32 startp; /* Initial data pointer */

sys/dev/disk/sym/sym_hipd.c

1488

u32 *badluntbl; /* Table physical address */

sys/dev/disk/sym/sym_hipd.c

1489

u32 badlun_sa; /* SCRIPT handler BUS address */

sys/dev/disk/sym/sym_hipd.c

1494

u32 hcb_ba;

sys/dev/disk/sym/sym_hipd.c

1501

u32 scr_ram_seg;

sys/dev/disk/sym/sym_hipd.c

1538

u32 *targtbl;

sys/dev/disk/sym/sym_hipd.c

1539

u32 targtbl_ba;

sys/dev/disk/sym/sym_hipd.c

1624

u32 clock_khz; /* SCSI clock frequency in KHz */

sys/dev/disk/sym/sym_hipd.c

1625

u32 pciclk_khz; /* Estimated PCI clock in KHz */

sys/dev/disk/sym/sym_hipd.c

1632

u32 *squeue; /* Start queue virtual address */

sys/dev/disk/sym/sym_hipd.c

1633

u32 squeue_ba; /* Start queue BUS address */

sys/dev/disk/sym/sym_hipd.c

1643

u32 *dqueue; /* Completion (done) queue */

sys/dev/disk/sym/sym_hipd.c

1644

u32 dqueue_ba; /* Done queue BUS address */

sys/dev/disk/sym/sym_hipd.c

1653

u32 lastmsg; /* Last SCSI message sent */

sys/dev/disk/sym/sym_hipd.c

1662

u32 cache; /* Used for cache test at init. */

sys/dev/disk/sym/sym_hipd.c

1902

sym_fw_fill_data (u32 *in, u32 *out)

sys/dev/disk/sym/sym_hipd.c

1921

u32 *pa;

sys/dev/disk/sym/sym_hipd.c

1930

pa = (u32 *) &np->fwa_bas;

sys/dev/disk/sym/sym_hipd.c

1931

for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++)

sys/dev/disk/sym/sym_hipd.c

1938

pa = (u32 *) &np->fwb_bas;

sys/dev/disk/sym/sym_hipd.c

1939

for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++)

sys/dev/disk/sym/sym_hipd.c

2014

static void sym_fw_bind_script (hcb_p np, u32 *start, int len)

sys/dev/disk/sym/sym_hipd.c

2016

u32 opcode, new, old, tmp1, tmp2;

sys/dev/disk/sym/sym_hipd.c

2017

u32 *end, *cur;

sys/dev/disk/sym/sym_hipd.c

2229

static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs);

sys/dev/disk/sym/sym_hipd.c

2243

static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);

sys/dev/disk/sym/sym_hipd.c

2396

static const u32 div_10M[] =

sys/dev/disk/sym/sym_hipd.c

241

#define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f)))

sys/dev/disk/sym/sym_hipd.c

242

#define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f)))

sys/dev/disk/sym/sym_hipd.c

243

#define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f)))

sys/dev/disk/sym/sym_hipd.c

2503

u32 period;

sys/dev/disk/sym/sym_hipd.c

3016

u32 term;

sys/dev/disk/sym/sym_hipd.c

3077

u32 dsa;

sys/dev/disk/sym/sym_hipd.c

3132

u32 phys;

sys/dev/disk/sym/sym_hipd.c

3355

u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */

sys/dev/disk/sym/sym_hipd.c

3357

u32 fak; /* Sync factor in sxfer */

sys/dev/disk/sym/sym_hipd.c

3358

u32 per; /* Period in tenths of ns */

sys/dev/disk/sym/sym_hipd.c

3359

u32 kpc; /* (per * clk) */

sys/dev/disk/sym/sym_hipd.c

3708

u32 dsp;

sys/dev/disk/sym/sym_hipd.c

3747

scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));

sys/dev/disk/sym/sym_hipd.c

4022

u32 dsp = INL (nc_dsp);

sys/dev/disk/sym/sym_hipd.c

4023

u32 dsa = INL (nc_dsa);

sys/dev/disk/sym/sym_hipd.c

4073

u32 dsp = INL (nc_dsp);

sys/dev/disk/sym/sym_hipd.c

4147

u32 dsp = INL (nc_dsp);

sys/dev/disk/sym/sym_hipd.c

4148

u32 dbc = INL (nc_dbc);

sys/dev/disk/sym/sym_hipd.c

4149

u32 dsa = INL (nc_dsa);

sys/dev/disk/sym/sym_hipd.c

4227

u32 dbc;

sys/dev/disk/sym/sym_hipd.c

4228

u32 rest;

sys/dev/disk/sym/sym_hipd.c

4229

u32 dsp;

sys/dev/disk/sym/sym_hipd.c

4230

u32 dsa;

sys/dev/disk/sym/sym_hipd.c

4231

u32 nxtdsp;

sys/dev/disk/sym/sym_hipd.c

4232

u32 *vdsp;

sys/dev/disk/sym/sym_hipd.c

4233

u32 oadr, olen;

sys/dev/disk/sym/sym_hipd.c

4234

u32 *tblp;

sys/dev/disk/sym/sym_hipd.c

4235

u32 newcmd;

sys/dev/disk/sym/sym_hipd.c

4267

u32 dfifo;

sys/dev/disk/sym/sym_hipd.c

4325

vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8));

sys/dev/disk/sym/sym_hipd.c

4330

vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8));

sys/dev/disk/sym/sym_hipd.c

4360

tblp = (u32 *) ((char*) &cp->phys + oadr);

sys/dev/disk/sym/sym_hipd.c

4450

u32 tmp;

sys/dev/disk/sym/sym_hipd.c

4681

u32 startp;

sys/dev/disk/sym/sym_hipd.c

5282

static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs)

sys/dev/disk/sym/sym_hipd.c

5284

u32 dp_scr;

sys/dev/disk/sym/sym_hipd.c

5403

u32 dp_scr = INL (nc_temp);

sys/dev/disk/sym/sym_hipd.c

5404

u32 dp_ret;

sys/dev/disk/sym/sym_hipd.c

5405

u32 tmp;

sys/dev/disk/sym/sym_hipd.c

6025

u32 dsa = INL (nc_dsa);

sys/dev/disk/sym/sym_hipd.c

6583

static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa)

sys/dev/disk/sym/sym_hipd.c

6753

volatile u32 data;

sys/dev/disk/sym/sym_hipd.c

6777

u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat;

sys/dev/disk/sym/sym_hipd.c

7675

u32 cmd_ba;

sys/dev/disk/sym/sym_hipd.c

7700

cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff;

sys/dev/disk/sym/sym_hipd.c

7724

u32 lastp, goalp;

sys/dev/disk/sym/sym_hipd.c

8212

sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg)

sys/dev/disk/sym/sym_hipd.c

8707

np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE");

sys/dev/disk/sym/sym_hipd.c

8715

np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE");

sys/dev/disk/sym/sym_hipd.c

8723

np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL");

sys/dev/disk/sym/sym_hipd.c

8781

sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz);

sys/dev/disk/sym/sym_hipd.c

8782

sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz);

sys/dev/disk/sym/sym_hipd.c

8914

sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE");

sys/dev/disk/sym/sym_hipd.c

8916

sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE");

sys/dev/drm/amd/amdgpu/amdgpu.h

1073

u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);

sys/dev/drm/amd/amdgpu/amdgpu.h

1074

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);

sys/dev/drm/amd/amdgpu/amdgpu.h

1076

u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);

sys/dev/drm/amd/amdgpu/amdgpu.h

1077

void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);

sys/dev/drm/amd/amdgpu/amdgpu.h

1078

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);

sys/dev/drm/amd/amdgpu/amdgpu.h

1079

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);

sys/dev/drm/amd/amdgpu/amdgpu.h

1200

const u32 *registers,

sys/dev/drm/amd/amdgpu/amdgpu.h

1201

const u32 array_size);

sys/dev/drm/amd/amdgpu/amdgpu.h

1242

u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/amd/amdgpu/amdgpu.h

1258

u32 clock;

sys/dev/drm/amd/amdgpu/amdgpu.h

250

u32 *flags);

sys/dev/drm/amd/amdgpu/amdgpu.h

268

const u32 major;

sys/dev/drm/amd/amdgpu/amdgpu.h

269

const u32 minor;

sys/dev/drm/amd/amdgpu/amdgpu.h

270

const u32 rev;

sys/dev/drm/amd/amdgpu/amdgpu.h

281

u32 major, u32 minor);

sys/dev/drm/amd/amdgpu/amdgpu.h

395

u32 __iomem *ptr;

sys/dev/drm/amd/amdgpu/amdgpu.h

396

u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */

sys/dev/drm/amd/amdgpu/amdgpu.h

493

u32 target_vblank;

sys/dev/drm/amd/amdgpu/amdgpu.h

585

static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

sys/dev/drm/amd/amdgpu/amdgpu.h

607

u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */

sys/dev/drm/amd/amdgpu/amdgpu.h

611

int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);

sys/dev/drm/amd/amdgpu/amdgpu.h

612

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);

sys/dev/drm/amd/amdgpu/amdgpu.h

639

u8 *bios, u32 length_bytes);

sys/dev/drm/amd/amdgpu/amdgpu.h

640

int (*read_register)(struct amdgpu_device *adev, u32 se_num,

sys/dev/drm/amd/amdgpu/amdgpu.h

641

u32 sh_num, u32 reg_offset, u32 *value);

sys/dev/drm/amd/amdgpu/amdgpu.h

645

u32 (*get_xclk)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

647

int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

sys/dev/drm/amd/amdgpu/amdgpu.h

648

int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);

sys/dev/drm/amd/amdgpu/amdgpu.h

653

u32 (*get_config_memsize)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

728

u32 ref_and_mask_cp0;

sys/dev/drm/amd/amdgpu/amdgpu.h

729

u32 ref_and_mask_cp1;

sys/dev/drm/amd/amdgpu/amdgpu.h

730

u32 ref_and_mask_cp2;

sys/dev/drm/amd/amdgpu/amdgpu.h

731

u32 ref_and_mask_cp3;

sys/dev/drm/amd/amdgpu/amdgpu.h

732

u32 ref_and_mask_cp4;

sys/dev/drm/amd/amdgpu/amdgpu.h

733

u32 ref_and_mask_cp5;

sys/dev/drm/amd/amdgpu/amdgpu.h

734

u32 ref_and_mask_cp6;

sys/dev/drm/amd/amdgpu/amdgpu.h

735

u32 ref_and_mask_cp7;

sys/dev/drm/amd/amdgpu/amdgpu.h

736

u32 ref_and_mask_cp8;

sys/dev/drm/amd/amdgpu/amdgpu.h

737

u32 ref_and_mask_cp9;

sys/dev/drm/amd/amdgpu/amdgpu.h

738

u32 ref_and_mask_sdma0;

sys/dev/drm/amd/amdgpu/amdgpu.h

739

u32 ref_and_mask_sdma1;

sys/dev/drm/amd/amdgpu/amdgpu.h

744

u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

745

u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

746

u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

747

u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

748

u32 (*get_rev_id)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

751

u32 (*get_memsize)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

765

u32 *flags);

sys/dev/drm/amd/amdgpu/amdgpu.h

775

u32 (*get_fb_channel_number)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

776

u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu.h

780

u32 *flags);

sys/dev/drm/amd/amdgpu/amdgpu.h

943

u32 log2_max_MBps;

sys/dev/drm/amd/amdgpu/amdgpu.h

971

u32 cg_flags;

sys/dev/drm/amd/amdgpu/amdgpu.h

972

u32 pg_flags;

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

188

u32 val = 0;

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

189

u32 count = 0;

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

382

if (val & (u32) 0x1)

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

406

u32 val = 0;

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

407

u32 count = 0;

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

444

if (val & (u32) 0x1)

sys/dev/drm/amd/amdgpu/amdgpu_acpi.c

138

static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask)

sys/dev/drm/amd/amdgpu/amdgpu_acpi.c

161

static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mask)

sys/dev/drm/amd/amdgpu/amdgpu_acpi.c

500

static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mask)

sys/dev/drm/amd/amdgpu/amdgpu_acpi.c

626

u32 retry = 3;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

114

if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

117

*start_offset = adev->doorbell.num_doorbells * sizeof(u32);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

514

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.h

128

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1014

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1103

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1154

u32 eng_clock, u32 mem_clock)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1158

u32 tmp;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1376

u32 entry_id;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1377

u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1418

u32 size = le16_to_cpu(v3->sHeader.usStructureSize);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1419

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1589

u32 i = 0, j;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1631

while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1633

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1637

(u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1642

(u32)le32_to_cpu(*((u32 *)reg_data + j));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1654

if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1729

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1741

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1761

u32 src_tmp[5], dst_tmp[5];

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

203

u32 reg;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

898

int id, u32 clock)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

103

u32 mclk_max;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

104

u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

124

u32 smio_low;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

129

u32 count;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

130

u32 mask_low;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

131

u32 phase_delay;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

155

int id, u32 clock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

159

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

164

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

169

u32 eng_clock, u32 mem_clock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

28

u32 post_div;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

32

u32 reserved : 6;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

33

u32 whole_fb_div : 12;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

34

u32 frac_fb_div : 14;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

36

u32 frac_fb_div : 14;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

37

u32 whole_fb_div : 12;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

38

u32 reserved : 6;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

41

u32 fb_div;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

43

u32 ref_div;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

46

u32 vco_mode;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

47

u32 real_clock;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

49

u32 post_divider;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

50

u32 flags;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

57

u32 reserved : 8;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

58

u32 clkfrac : 12;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

59

u32 clkf : 12;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

61

u32 clkf : 12;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

62

u32 clkfrac : 12;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

63

u32 reserved : 8;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

66

u32 fb_div;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

68

u32 post_div;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

69

u32 bwcntl;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

70

u32 dll_speed;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

71

u32 vco_mode;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

72

u32 yclk_sel;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

73

u32 qdr;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

74

u32 half_rate;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

96

u32 mclk[MAX_AC_TIMING_ENTRIES];

sys/dev/drm/amd/amdgpu/amdgpu_ctx.c

215

int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,

sys/dev/drm/amd/amdgpu/amdgpu_ctx.c

216

u32 ring, struct drm_sched_entity **entity)

sys/dev/drm/amd/amdgpu/amdgpu_ctx.c

275

u32 i;

sys/dev/drm/amd/amdgpu/amdgpu_ctx.h

70

int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,

sys/dev/drm/amd/amdgpu/amdgpu_ctx.h

71

u32 ring, struct drm_sched_entity **entity);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1100

u32 *flags)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

1199

u32 major, u32 minor)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

237

u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

2376

u32 max_MBps;

sys/dev/drm/amd/amdgpu/amdgpu_device.c

256

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

283

u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

303

void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

321

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

341

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

464

const u32 *registers,

sys/dev/drm/amd/amdgpu/amdgpu_device.c

465

const u32 array_size)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

467

u32 tmp, reg, and_mask, or_mask;

sys/dev/drm/amd/amdgpu/amdgpu_device.c

531

adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),

sys/dev/drm/amd/amdgpu/amdgpu_device.c

538

sizeof(u32));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

627

int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

648

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

670

u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;

sys/dev/drm/amd/amdgpu/amdgpu_display.c

671

u32 src_v = 1, dst_v = 1;

sys/dev/drm/amd/amdgpu/amdgpu_display.c

672

u32 src_h = 1, dst_h = 1;

sys/dev/drm/amd/amdgpu/amdgpu_display.c

779

u32 vbl = 0, position = 0;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

140

u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

145

u32 vblank_in_pixels;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

146

u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

167

u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

172

u32 vrefresh = 0;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

187

void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

188

u32 *p, u32 *u)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

190

u32 b_c = 0;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

191

u32 i_c;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

192

u32 tmp;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

206

int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

208

u32 k, a, ah, al;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

209

u32 t1;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

227

bool amdgpu_is_uvd_state(u32 class, u32 class2)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

285

u32 size = atom_table->ucNumEntries *

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

33

void amdgpu_dpm_print_class_info(u32 class, u32 class2)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

501

u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

554

u32 size = limits->numEntries *

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

609

u32 size = limits->numEntries *

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

641

u32 size = limits->numEntries *

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

699

u32 size = limits->numEntries *

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

928

u32 sys_mask,

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

94

void amdgpu_dpm_print_cap_info(u32 caps)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

975

u8 amdgpu_encode_pci_lane_width(u32 lanes)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

986

amdgpu_get_vce_clock_state(void *handle, u32 idx)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

105

u32 count;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

106

u32 *values;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

110

u32 clk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

115

u32 count;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

122

u32 leakage;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

132

u32 count;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

138

u32 sclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

139

u32 mclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

143

u32 count;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

148

u32 vclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

149

u32 dclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

159

u32 ecclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

160

u32 evclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

172

u32 platform_tdp;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

173

u32 small_ac_platform_tdp;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

174

u32 platform_tdc;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

175

u32 small_ac_platform_tdc;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

176

u32 apu_tdp;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

177

u32 dgpu_tdp;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

178

u32 dgpu_ulv_power;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

179

u32 tj_max;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

208

u32 mclk_sclk_ratio;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

209

u32 sclk_mclk_delta;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

226

u32 cycle_delay;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

380

u32 num_of_vce_states;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

387

u32 platform_caps;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

388

u32 voltage_response_time;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

389

u32 backbias_response_time;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

391

u32 new_active_crtcs;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

393

u32 current_active_crtcs;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

397

u32 tdp_limit;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

398

u32 near_tdp_limit;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

399

u32 near_tdp_limit_adjusted;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

400

u32 sq_ramping_threshold;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

401

u32 cac_leakage;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

403

u32 tdp_adjustment;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

418

u32 current_sclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

419

u32 current_mclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

420

u32 default_sclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

421

u32 default_mclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

474

void amdgpu_dpm_print_class_info(u32 class, u32 class2);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

475

void amdgpu_dpm_print_cap_info(u32 caps);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

478

u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

479

u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

481

bool amdgpu_is_uvd_state(u32 class, u32 class2);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

482

void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

483

u32 *p, u32 *u);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

484

int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

496

u32 sys_mask,

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

503

u8 amdgpu_encode_pci_lane_width(u32 lanes);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

506

amdgpu_get_vce_clock_state(void *handle, u32 idx);

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

56

u32 caps; /* vbios flags */

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

57

u32 class; /* vbios flags */

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

58

u32 class2; /* vbios flags */

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

60

u32 vclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

61

u32 dclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

63

u32 evclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

64

u32 ecclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

92

u32 sclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

93

u32 mclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

98

u32 sclk;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

99

u32 mclk;

sys/dev/drm/amd/amdgpu/amdgpu_encoders.c

190

u32 pixel_clock)

sys/dev/drm/amd/amdgpu/amdgpu_fb.c

137

u32 tiling_flags = 0, domain;

sys/dev/drm/amd/amdgpu/amdgpu_fb.c

141

u32 cpp;

sys/dev/drm/amd/amdgpu/amdgpu_fence.c

112

static u32 amdgpu_fence_read(struct amdgpu_ring *ring)

sys/dev/drm/amd/amdgpu/amdgpu_fence.c

115

u32 seq = 0;

sys/dev/drm/amd/amdgpu/amdgpu_fence.c

96

static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)

sys/dev/drm/amd/amdgpu/amdgpu_gem.c

261

(u32)(0xffffffff & args->in.domains),

sys/dev/drm/amd/amdgpu/amdgpu_gem.c

46

int alignment, u32 initial_domain,

sys/dev/drm/amd/amdgpu/amdgpu_gem.c

756

u32 domain;

sys/dev/drm/amd/amdgpu/amdgpu_gem.h

62

int alignment, u32 initial_domain,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

286

u32 *hpd;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

100

u32 num_pipe_per_mec;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

101

u32 num_queue_per_pipe;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

204

void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

205

u32 sh_num, u32 instance);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

214

void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

215

u32 queue);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

326

static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

328

return (u32)((1ULL << bit_width) - 1);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

50

const u32 *reg_list;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

51

u32 reg_list_size;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

57

u32 clear_state_size;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

62

u32 cp_table_size;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

69

u32 save_and_restore_offset;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

70

u32 clear_state_descriptor_offset;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

71

u32 avail_scratch_ram_locations;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

72

u32 reg_restore_list_size;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

73

u32 reg_list_format_start;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

74

u32 reg_list_format_separate_start;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

75

u32 starting_offsets_start;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

76

u32 reg_list_format_size_bytes;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

77

u32 reg_list_size_bytes;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

78

u32 reg_list_format_direct_reg_list_length;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

79

u32 save_restore_list_cntl_size_bytes;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

80

u32 save_restore_list_gpm_size_bytes;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

81

u32 save_restore_list_srm_size_bytes;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

83

u32 *register_list_format;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

84

u32 *register_restore;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

99

u32 num_mec;

sys/dev/drm/amd/amdgpu/amdgpu_ih.c

135

u32 wptr;

sys/dev/drm/amd/amdgpu/amdgpu_ih.c

43

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/amdgpu_ih.h

44

u32 doorbell_index;

sys/dev/drm/amd/amdgpu/amdgpu_ih.h

53

u32 (*get_wptr)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu_irq.c

162

u32 ring_index = ih->rptr >> 2;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1105

u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1109

u32 count;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

254

u32 offset;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

256

u32 id;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

269

u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

279

u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

284

u32 *vbl, u32 *position);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

410

u32 pll_id;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

418

u32 adjusted_clock;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

420

u32 pll_reference_div;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

421

u32 pll_post_div;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

422

u32 pll_flags;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

426

u32 line_time;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

427

u32 wm_low;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

428

u32 wm_high;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

429

u32 lb_vblank_lead_lines;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

493

u32 reg;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

494

u32 mask;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

495

u32 shift;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

505

u32 router_id;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

596

u32 pixel_clock);

sys/dev/drm/amd/amdgpu/amdgpu_object.c

131

void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

137

u32 c = 0;

sys/dev/drm/amd/amdgpu/amdgpu_object.c

239

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/drm/amd/amdgpu/amdgpu_object.c

333

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/drm/amd/amdgpu/amdgpu_object.c

383

unsigned long size, u32 domain)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

851

int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,

sys/dev/drm/amd/amdgpu/amdgpu_object.c

946

int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)

sys/dev/drm/amd/amdgpu/amdgpu_object.h

121

static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)

sys/dev/drm/amd/amdgpu/amdgpu_object.h

226

void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

233

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/drm/amd/amdgpu/amdgpu_object.h

237

u32 domain, struct amdgpu_bo **bo_ptr,

sys/dev/drm/amd/amdgpu/amdgpu_object.h

246

int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

247

int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,

sys/dev/drm/amd/amdgpu/amdgpu_object.h

297

unsigned size, u32 align, u32 domain);

sys/dev/drm/amd/amdgpu/amdgpu_object.h

40

u32 domain;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

41

u32 preferred_domain;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

79

u32 preferred_domains;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

80

u32 allowed_domains;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

90

u32 metadata_size;

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

115

u32 freq,

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

116

u32 *dot_clock_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

117

u32 *fb_div_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

118

u32 *frac_fb_div_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

119

u32 *ref_div_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

120

u32 *post_div_p)

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

260

u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

265

u32 pll_in_use = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

322

u32 adjusted_clock, test_adjusted_clock;

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

28

u32 freq,

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

29

u32 *dot_clock_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

30

u32 *fb_div_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

31

u32 *frac_fb_div_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

32

u32 *ref_div_p,

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

33

u32 *post_div_p);

sys/dev/drm/amd/amdgpu/amdgpu_pll.h

34

u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc);

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1082

u32 pwm_mode = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1138

u32 value;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1139

u32 pwm_mode;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1173

u32 speed = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1197

u32 speed = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1218

u32 min_rpm = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1219

u32 size = sizeof(min_rpm);

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1238

u32 max_rpm = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1239

u32 size = sizeof(max_rpm);

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1259

u32 rpm = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1281

u32 value;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1282

u32 pwm_mode;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1311

u32 pwm_mode = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1329

u32 pwm_mode;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1361

u32 vddgfx;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1396

u32 vddnb;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1435

u32 query = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1436

int r, size = sizeof(u32);

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1506

u32 value;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

1762

u32 ui_class;

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

2253

static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

2268

u32 flags = 0;

sys/dev/drm/amd/amdgpu/amdgpu_pm.h

29

u32 flag;

sys/dev/drm/amd/amdgpu/amdgpu_prime.c

363

u32 domain = amdgpu_display_supported_domains(adev);

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

115

u32 nop;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

193

u32 idx;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

194

u32 me;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

195

u32 pipe;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

196

u32 queue;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

201

u32 doorbell_index;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

210

volatile u32 *cond_exe_cpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_sa.c

52

unsigned size, u32 align, u32 domain)

sys/dev/drm/amd/amdgpu/amdgpu_vf_error.c

54

u32 data1, data2, data3;

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

59

void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

76

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

77

(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

sys/dev/drm/amd/amdgpu/atom.c

218

val = get_unaligned_le32((u32 *)&ctx->ps[idx]);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

305

static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

314

u32 adjusted_clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

316

u32 dp_clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

317

u32 clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

472

u32 dispclk)

sys/dev/drm/amd/amdgpu/atombios_crtc.c

526

u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

527

u32 freq, u8 clk_type, u8 clk_src)

sys/dev/drm/amd/amdgpu/atombios_crtc.c

532

u32 ret_freq = 0;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

564

static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)

sys/dev/drm/amd/amdgpu/atombios_crtc.c

577

u32 crtc_id,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

579

u32 encoder_mode,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

580

u32 encoder_id,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

581

u32 clock,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

582

u32 ref_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

583

u32 fb_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

584

u32 frac_fb_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

585

u32 post_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

824

u32 pll_clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

825

u32 clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

826

u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

867

u32 step_size;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

868

u32 amount = (((fb_div * 10) + frac_fb_div) *

sys/dev/drm/amd/amdgpu/atombios_crtc.c

869

(u32)amdgpu_crtc->ss.percentage) /

sys/dev/drm/amd/amdgpu/atombios_crtc.c

870

(100 * (u32)amdgpu_crtc->ss.percentage_divider);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

875

step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /

sys/dev/drm/amd/amdgpu/atombios_crtc.c

878

step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /

sys/dev/drm/amd/amdgpu/atombios_crtc.h

39

u32 dispclk);

sys/dev/drm/amd/amdgpu/atombios_crtc.h

40

u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

41

u32 freq, u8 clk_type, u8 clk_src);

sys/dev/drm/amd/amdgpu/atombios_crtc.h

43

u32 crtc_id,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

45

u32 encoder_mode,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

46

u32 encoder_id,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

47

u32 clock,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

48

u32 ref_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

49

u32 fb_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

50

u32 frac_fb_div,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

51

u32 post_div,

sys/dev/drm/amd/amdgpu/atombios_encoders.c

1308

u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

1867

u32 bios_0_scratch;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

42

u32 bios_2_scratch;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

56

u32 bios_2_scratch;

sys/dev/drm/amd/amdgpu/atombios_i2c.c

162

u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)

sys/dev/drm/amd/amdgpu/atombios_i2c.h

29

u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1011

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1044

u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1070

static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1073

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1098

u32 duty100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1099

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1101

u32 reference_clock, tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1217

u32 *speed)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1219

u32 duty, duty100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1236

*speed = (u32)tmp64;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1245

u32 speed)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1247

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1248

u32 duty, duty100;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1270

duty = (u32)tmp64;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1279

static void ci_dpm_set_fan_control_mode(void *handle, u32 mode)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1302

static u32 ci_dpm_get_fan_control_mode(void *handle)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1315

u32 *speed)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1317

u32 tach_period;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1318

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1337

u32 speed)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1339

u32 tach_period, tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1340

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1369

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1393

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1435

u16 reg_offset, u32 *value)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1445

u16 reg_offset, u32 value)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1474

u32 low_sclk_interrupt_t = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1483

sizeof(u32), pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1532

static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1537

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1684

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1745

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1774

u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1790

u32 power_limit;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1793

power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1795

power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1811

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1818

PPSMC_Msg msg, u32 *parameter)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1830

static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1844

static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1858

static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1872

static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1887

u32 target_tdp)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1903

static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1905

u32 sclk_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1916

static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1918

u32 mclk_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1951

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2039

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

204

u32 arb_freq_src, u32 arb_freq_dest)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2050

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

206

u32 mc_arb_dram_timing;

sys/dev/drm/amd/amdgpu/ci_dpm.c

207

u32 mc_arb_dram_timing2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

208

u32 burst_time;

sys/dev/drm/amd/amdgpu/ci_dpm.c

209

u32 mc_cg_config;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2119

u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2120

u32 pre_vbi_time_in_us;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2121

u32 frame_time_in_us;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2122

u32 ref_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2123

u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2124

u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2154

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2182

u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2194

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2212

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2256

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2446

static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2450

u32 i = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2480

for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2484

if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2497

for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2501

if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2520

u32 sclk,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2521

u32 *phase_shedding)

sys/dev/drm/amd/amdgpu/ci_dpm.c

253

static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2537

u32 mclk,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2538

u32 *phase_shedding)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2555

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2572

u32 clock, u32 *voltage)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2574

u32 i = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2591

static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2593

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2594

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2595

u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2622

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2633

const u32 engine_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2634

const u32 memory_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2635

u32 *dram_timimg2)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2638

u32 tmp, tmp2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2659

u32 sclk,

sys/dev/drm/amd/amdgpu/ci_dpm.c

266

static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2660

u32 mclk,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2663

u32 dram_timing;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2664

u32 dram_timing2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2665

u32 burst_time;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2686

u32 i, j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2727

u32 level = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2746

static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2748

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2749

u32 mask_value = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2767

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2787

u32 count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2830

u32 count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2863

u32 count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

289

u32 max_voltage_steps,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2895

u32 count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2925

u32 memory_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2931

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2932

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2933

u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2934

u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2935

u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2936

u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2937

u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2938

u32 mpll_ss1 = pi->clock_registers.mpll_ss1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2939

u32 mpll_ss2 = pi->clock_registers.mpll_ss2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2968

u32 freq_nom;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2969

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2970

u32 reference_clock = adev->clock.mpll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2981

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2982

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3017

u32 memory_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

308

static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);

sys/dev/drm/amd/amdgpu/ci_dpm.c

310

u32 target_tdp);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3137

u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3138

u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3139

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3140

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

315

PPSMC_Msg msg, u32 parameter);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3304

u32 engine_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3309

u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3310

u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3311

u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3312

u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3313

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3314

u32 reference_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3315

u32 fbdiv;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3333

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3337

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3338

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3360

u32 engine_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3423

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

3425

u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *

sys/dev/drm/amd/amdgpu/ci_dpm.c

3428

u32 i, ret;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3470

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

3472

u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *

sys/dev/drm/amd/amdgpu/ci_dpm.c

3475

u32 i, ret;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3517

u32 count)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3519

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3527

u32 index, u32 pcie_gen, u32 pcie_lanes)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3591

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3685

u32 value, u32 *boot_level)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3687

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3776

(u32 *)&pi->smc_state_table.GraphicsBootLevel);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3780

(u32 *)&pi->smc_state_table.MemoryBootLevel);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3850

u32 low_limit, u32 high_limit)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3852

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3864

u32 speed_low, u32 lanes_low,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3865

u32 speed_high, u32 lanes_high)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3869

u32 i, j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3899

u32 high_limit_count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3934

u32 requested_voltage = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3935

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4008

u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4010

u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4011

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

404

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4046

u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4047

u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4224

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4253

u32 min_evclk = 30000; /* ??? */

sys/dev/drm/amd/amdgpu/ci_dpm.c

4271

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4300

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

431

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4341

static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4342

u32 level_mask)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4344

u32 level = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4358

u32 tmp, levels, i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4494

u32 temp_reg;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4646

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4687

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

480

(u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4836

u32 i, j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4855

u32 num_entries, u32 valid_flag)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4857

u32 i, j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4868

const u32 memory_clock,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4872

u32 i = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4891

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4940

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4964

u32 speed_cntl = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4975

u32 link_width = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5110

u32 leakage_index;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5124

u32 leakage_index;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5137

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5148

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5159

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5170

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5181

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5201

u32 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5725

u32 sclk, mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5990

u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

605

u32 pm_fuse_table_offset;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6090

u32 sclk = ci_get_average_sclk_freq(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6091

u32 mclk = ci_get_average_mclk_freq(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6092

u32 activity_percent = 50;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6183

static u32 ci_dpm_get_sclk(void *handle, bool low)

sys/dev/drm/amd/amdgpu/ci_dpm.c

6195

static u32 ci_dpm_get_mclk(void *handle, bool low)

sys/dev/drm/amd/amdgpu/ci_dpm.c

6210

u32 temp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6453

u32 cg_thermal_int;

sys/dev/drm/amd/amdgpu/ci_dpm.c

652

u32 data;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6729

u32 activity_percent = 50;

sys/dev/drm/amd/amdgpu/ci_dpm.c

695

u32 data;

sys/dev/drm/amd/amdgpu/ci_dpm.c

696

u32 cache = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

796

u32 default_pwr_limit =

sys/dev/drm/amd/amdgpu/ci_dpm.c

797

(u32)(cac_tdp_table->maximum_power_delivery_limit * 256);

sys/dev/drm/amd/amdgpu/ci_dpm.c

881

ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);

sys/dev/drm/amd/amdgpu/ci_dpm.c

909

u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

910

u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;

sys/dev/drm/amd/amdgpu/ci_dpm.c

932

u32 sclk, mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.h

107

u32 uvd_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

108

u32 vce_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

109

u32 acp_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

110

u32 samu_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

111

u32 sclk_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

112

u32 mclk_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

113

u32 pcie_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

121

u32 sclk_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.h

122

u32 mclk_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.h

128

u32 cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

129

u32 cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.h

130

u32 cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/ci_dpm.h

131

u32 cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/ci_dpm.h

132

u32 cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/ci_dpm.h

133

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/ci_dpm.h

134

u32 dll_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

135

u32 mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

136

u32 mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

137

u32 mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

138

u32 mpll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

139

u32 mpll_func_cntl_1;

sys/dev/drm/amd/amdgpu/ci_dpm.h

140

u32 mpll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.h

141

u32 mpll_ss1;

sys/dev/drm/amd/amdgpu/ci_dpm.h

142

u32 mpll_ss2;

sys/dev/drm/amd/amdgpu/ci_dpm.h

169

u32 offset;

sys/dev/drm/amd/amdgpu/ci_dpm.h

170

u32 mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

171

u32 shift;

sys/dev/drm/amd/amdgpu/ci_dpm.h

172

u32 value;

sys/dev/drm/amd/amdgpu/ci_dpm.h

183

u32 display_cac;

sys/dev/drm/amd/amdgpu/ci_dpm.h

184

u32 bapm_temp_gradient;

sys/dev/drm/amd/amdgpu/ci_dpm.h

197

u32 voltage_control;

sys/dev/drm/amd/amdgpu/ci_dpm.h

198

u32 mvdd_control;

sys/dev/drm/amd/amdgpu/ci_dpm.h

199

u32 vddci_control;

sys/dev/drm/amd/amdgpu/ci_dpm.h

200

u32 active_auto_throttle_sources;

sys/dev/drm/amd/amdgpu/ci_dpm.h

212

u32 mclk_strobe_mode_threshold;

sys/dev/drm/amd/amdgpu/ci_dpm.h

213

u32 mclk_stutter_mode_threshold;

sys/dev/drm/amd/amdgpu/ci_dpm.h

214

u32 mclk_edc_enable_threshold;

sys/dev/drm/amd/amdgpu/ci_dpm.h

215

u32 mclk_edc_wr_enable_threshold;

sys/dev/drm/amd/amdgpu/ci_dpm.h

218

u32 sram_end;

sys/dev/drm/amd/amdgpu/ci_dpm.h

219

u32 dpm_table_start;

sys/dev/drm/amd/amdgpu/ci_dpm.h

220

u32 soft_regs_start;

sys/dev/drm/amd/amdgpu/ci_dpm.h

221

u32 mc_reg_table_start;

sys/dev/drm/amd/amdgpu/ci_dpm.h

222

u32 fan_table_start;

sys/dev/drm/amd/amdgpu/ci_dpm.h

223

u32 arb_table_start;

sys/dev/drm/amd/amdgpu/ci_dpm.h

234

u32 power_containment_features;

sys/dev/drm/amd/amdgpu/ci_dpm.h

236

u32 dte_tj_offset;

sys/dev/drm/amd/amdgpu/ci_dpm.h

240

u32 need_update_smu7_dpm_table;

sys/dev/drm/amd/amdgpu/ci_dpm.h

241

u32 sclk_dpm_key_disabled;

sys/dev/drm/amd/amdgpu/ci_dpm.h

242

u32 mclk_dpm_key_disabled;

sys/dev/drm/amd/amdgpu/ci_dpm.h

243

u32 pcie_dpm_key_disabled;

sys/dev/drm/amd/amdgpu/ci_dpm.h

244

u32 thermal_sclk_dpm_enabled;

sys/dev/drm/amd/amdgpu/ci_dpm.h

249

u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];

sys/dev/drm/amd/amdgpu/ci_dpm.h

250

u32 mclk_activity_target;

sys/dev/drm/amd/amdgpu/ci_dpm.h

251

u32 low_sclk_interrupt_t;

sys/dev/drm/amd/amdgpu/ci_dpm.h

252

u32 last_mclk_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

253

u32 sys_pcie_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.h

296

u32 t_min;

sys/dev/drm/amd/amdgpu/ci_dpm.h

297

u32 fan_ctrl_default_mode;

sys/dev/drm/amd/amdgpu/ci_dpm.h

333

u32 smc_start_address,

sys/dev/drm/amd/amdgpu/ci_dpm.h

334

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/amd/amdgpu/ci_dpm.h

343

int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit);

sys/dev/drm/amd/amdgpu/ci_dpm.h

345

u32 smc_address, u32 *value, u32 limit);

sys/dev/drm/amd/amdgpu/ci_dpm.h

347

u32 smc_address, u32 value, u32 limit);

sys/dev/drm/amd/amdgpu/ci_dpm.h

40

u32 mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.h

41

u32 sclk;

sys/dev/drm/amd/amdgpu/ci_dpm.h

49

u32 sclk_t;

sys/dev/drm/amd/amdgpu/ci_dpm.h

55

u32 value;

sys/dev/drm/amd/amdgpu/ci_dpm.h

56

u32 param1;

sys/dev/drm/amd/amdgpu/ci_dpm.h

64

u32 count;

sys/dev/drm/amd/amdgpu/ci_dpm.h

78

u32 mclk_max;

sys/dev/drm/amd/amdgpu/ci_dpm.h

79

u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/ci_dpm.h

93

u32 cg_ulv_parameter;

sys/dev/drm/amd/amdgpu/ci_dpm.h

94

u32 volt_change_delay;

sys/dev/drm/amd/amdgpu/ci_smc.c

119

u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);

sys/dev/drm/amd/amdgpu/ci_smc.c

127

u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);

sys/dev/drm/amd/amdgpu/ci_smc.c

142

u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/ci_smc.c

151

u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/ci_smc.c

160

u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/ci_smc.c

161

u32 pc_c = RREG32_SMC(ixSMC_PC_C);

sys/dev/drm/amd/amdgpu/ci_smc.c

171

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_smc.c

192

u32 tmp;

sys/dev/drm/amd/amdgpu/ci_smc.c

208

int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit)

sys/dev/drm/amd/amdgpu/ci_smc.c

212

u32 ucode_start_address;

sys/dev/drm/amd/amdgpu/ci_smc.c

213

u32 ucode_size;

sys/dev/drm/amd/amdgpu/ci_smc.c

215

u32 data;

sys/dev/drm/amd/amdgpu/ci_smc.c

252

u32 smc_address, u32 *value, u32 limit)

sys/dev/drm/amd/amdgpu/ci_smc.c

267

u32 smc_address, u32 value, u32 limit)

sys/dev/drm/amd/amdgpu/ci_smc.c

37

u32 smc_address, u32 limit)

sys/dev/drm/amd/amdgpu/ci_smc.c

51

u32 smc_start_address,

sys/dev/drm/amd/amdgpu/ci_smc.c

52

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/amd/amdgpu/ci_smc.c

55

u32 data, original_data;

sys/dev/drm/amd/amdgpu/ci_smc.c

56

u32 addr;

sys/dev/drm/amd/amdgpu/ci_smc.c

57

u32 extra_shift;

sys/dev/drm/amd/amdgpu/cik.c

100

static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

1027

bool indexed, u32 se_num,

sys/dev/drm/amd/amdgpu/cik.c

1028

u32 sh_num, u32 reg_offset)

sys/dev/drm/amd/amdgpu/cik.c

103

u32 r;

sys/dev/drm/amd/amdgpu/cik.c

112

static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

1122

static int cik_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/drm/amd/amdgpu/cik.c

1123

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/drm/amd/amdgpu/cik.c

1142

u32 gmcon_reng_execute;

sys/dev/drm/amd/amdgpu/cik.c

1143

u32 gmcon_misc;

sys/dev/drm/amd/amdgpu/cik.c

1144

u32 gmcon_misc3;

sys/dev/drm/amd/amdgpu/cik.c

122

static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

1237

u32 i;

sys/dev/drm/amd/amdgpu/cik.c

125

u32 r;

sys/dev/drm/amd/amdgpu/cik.c

1293

static u32 cik_get_config_memsize(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/cik.c

1298

static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/drm/amd/amdgpu/cik.c

1299

u32 cntl_reg, u32 status_reg)

sys/dev/drm/amd/amdgpu/cik.c

1328

static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/drm/amd/amdgpu/cik.c

134

static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

1340

static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/drm/amd/amdgpu/cik.c

1344

u32 tmp;

sys/dev/drm/amd/amdgpu/cik.c

1381

u32 speed_cntl, current_data_rate;

sys/dev/drm/amd/amdgpu/cik.c

1430

u32 max_lw, current_lw, tmp;

sys/dev/drm/amd/amdgpu/cik.c

144

static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

147

u32 r;

sys/dev/drm/amd/amdgpu/cik.c

1542

u32 data, orig;

sys/dev/drm/amd/amdgpu/cik.c

156

static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

1631

u32 lnkcap;

sys/dev/drm/amd/amdgpu/cik.c

166

static const u32 bonaire_golden_spm_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

171

static const u32 bonaire_golden_common_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

179

static const u32 bonaire_golden_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

224

static const u32 bonaire_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/cik.c

310

static const u32 spectre_golden_spm_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

315

static const u32 spectre_golden_common_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

323

static const u32 spectre_golden_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

352

static const u32 spectre_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/cik.c

443

static const u32 kalindi_golden_spm_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

448

static const u32 kalindi_golden_common_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

456

static const u32 kalindi_golden_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

490

static const u32 kalindi_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/cik.c

549

static const u32 hawaii_golden_spm_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

554

static const u32 hawaii_golden_common_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

563

static const u32 hawaii_golden_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

603

static const u32 hawaii_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/cik.c

714

static const u32 godavari_golden_registers[] =

sys/dev/drm/amd/amdgpu/cik.c

75

static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

78

u32 r;

sys/dev/drm/amd/amdgpu/cik.c

840

static u32 cik_get_xclk(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/cik.c

842

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/cik.c

868

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/amd/amdgpu/cik.c

870

u32 srbm_gfx_cntl =

sys/dev/drm/amd/amdgpu/cik.c

88

static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

892

u32 bus_cntl;

sys/dev/drm/amd/amdgpu/cik.c

893

u32 d1vga_control = 0;

sys/dev/drm/amd/amdgpu/cik.c

894

u32 d2vga_control = 0;

sys/dev/drm/amd/amdgpu/cik.c

895

u32 vga_render_control = 0;

sys/dev/drm/amd/amdgpu/cik.c

896

u32 rom_cntl;

sys/dev/drm/amd/amdgpu/cik.c

936

u8 *bios, u32 length_bytes)

sys/dev/drm/amd/amdgpu/cik.c

938

u32 *dw_ptr;

sys/dev/drm/amd/amdgpu/cik.c

940

u32 i, length_dw;

sys/dev/drm/amd/amdgpu/cik.c

950

dw_ptr = (u32 *)bios;

sys/dev/drm/amd/amdgpu/cik.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/drm/amd/amdgpu/cik_ih.c

107

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/drm/amd/amdgpu/cik_ih.c

186

static u32 cik_ih_get_wptr(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/cik_ih.c

188

u32 wptr, tmp;

sys/dev/drm/amd/amdgpu/cik_ih.c

240

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/cik_ih.c

271

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/cik_ih.c

379

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/cik_ih.c

390

u32 tmp;

sys/dev/drm/amd/amdgpu/cik_ih.c

407

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/cik_ih.c

408

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/cik_ih.c

60

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/drm/amd/amdgpu/cik_ih.c

61

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cik_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cik_ih.c

80

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1059

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1071

u32 tmp;

sys/dev/drm/amd/amdgpu/cik_sdma.c

1087

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/cik_sdma.c

1089

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1131

u32 sdma_cntl;

sys/dev/drm/amd/amdgpu/cik_sdma.c

163

u32 rptr;

sys/dev/drm/amd/amdgpu/cik_sdma.c

224

u32 extra_bits = vmid & 0xf;

sys/dev/drm/amd/amdgpu/cik_sdma.c

245

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

sys/dev/drm/amd/amdgpu/cik_sdma.c

247

u32 ref_and_mask;

sys/dev/drm/amd/amdgpu/cik_sdma.c

306

u32 rb_cntl;

sys/dev/drm/amd/amdgpu/cik_sdma.c

345

u32 f32_cntl, phase_quantum = 0;

sys/dev/drm/amd/amdgpu/cik_sdma.c

402

u32 me_cntl;

sys/dev/drm/amd/amdgpu/cik_sdma.c

431

u32 rb_cntl, ib_cntl;

sys/dev/drm/amd/amdgpu/cik_sdma.c

432

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/cik_sdma.c

433

u32 wb_offset;

sys/dev/drm/amd/amdgpu/cik_sdma.c

45

static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

sys/dev/drm/amd/amdgpu/cik_sdma.c

543

u32 fw_size;

sys/dev/drm/amd/amdgpu/cik_sdma.c

617

u32 tmp;

sys/dev/drm/amd/amdgpu/cik_sdma.c

676

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/cik_sdma.c

68

u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/cik_sdma.c

826

u32 pad_count;

sys/dev/drm/amd/amdgpu/cik_sdma.c

876

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |

sys/dev/drm/amd/amdgpu/cik_sdma.c

900

u32 orig, data;

sys/dev/drm/amd/amdgpu/cik_sdma.c

921

u32 orig, data;

sys/dev/drm/amd/amdgpu/clearstate_si.h

239

static const u32 si_SECT_CONTEXT_def_2[] =

sys/dev/drm/amd/amdgpu/clearstate_si.h

24

static const u32 si_SECT_CONTEXT_def_1[] =

sys/dev/drm/amd/amdgpu/clearstate_si.h

514

static const u32 si_SECT_CONTEXT_def_3[] =

sys/dev/drm/amd/amdgpu/clearstate_si.h

523

static const u32 si_SECT_CONTEXT_def_4[] =

sys/dev/drm/amd/amdgpu/clearstate_si.h

683

static const u32 si_SECT_CONTEXT_def_5[] =

sys/dev/drm/amd/amdgpu/clearstate_si.h

687

static const u32 si_SECT_CONTEXT_def_6[] =

sys/dev/drm/amd/amdgpu/clearstate_si.h

691

static const u32 si_SECT_CONTEXT_def_7[] =

sys/dev/drm/amd/amdgpu/cz_ih.c

107

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/drm/amd/amdgpu/cz_ih.c

188

static u32 cz_ih_get_wptr(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/cz_ih.c

190

u32 wptr, tmp;

sys/dev/drm/amd/amdgpu/cz_ih.c

219

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/cz_ih.c

250

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/cz_ih.c

358

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/cz_ih.c

369

u32 tmp;

sys/dev/drm/amd/amdgpu/cz_ih.c

384

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/cz_ih.c

386

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/cz_ih.c

60

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/drm/amd/amdgpu/cz_ih.c

61

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cz_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cz_ih.c

80

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1015

u32 lb_size, u32 num_heads)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1019

u32 active_time;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1020

u32 line_time = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1021

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1022

u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1025

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1026

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1027

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1028

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1029

line_time = min(line_time, (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1059

latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1098

latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1148

u32 num_heads = 0, lb_size;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1168

u32 offset, tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

119

static const u32 golden_settings_tonga_a11[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1202

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1220

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1262

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

127

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

133

static const u32 golden_settings_fiji_a10[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1355

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1400

static const u32 pin_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

141

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1465

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1513

static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1520

u32 dto_phase = 24 * 1000;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1521

u32 dto_modulo = clock;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1522

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1554

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

171

static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

172

u32 block_offset, u32 reg)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

175

u32 r;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1786

static const u32 vga_control_regs[6] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1801

u32 vga_control;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1834

u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1835

u32 pipe_config;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1836

u32 tmp, viewport_w, viewport_h;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

186

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

196

static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2006

(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2008

(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2075

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2092

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2224

static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2229

u32 pll_in_use;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2279

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2290

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

236

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

254

u32 *vbl, u32 *position)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2920

u32 srbm_soft_reset = 0, tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2949

u32 lb_interrupt_mask;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2978

u32 lb_interrupt_mask;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

300

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3008

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3086

u32 reg;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3160

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3175

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3190

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

326

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

378

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

395

static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

402

u32 crtc_hung = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

403

u32 crtc_status[6];

sys/dev/drm/amd/amdgpu/dce_v10_0.c

404

u32 i, j, tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

433

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

471

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

499

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

50

static const u32 crtc_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

581

static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

585

u32 tmp, buffer_alloc, i, mem_cfg;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

586

u32 pipe_offset = amdgpu_crtc->crtc_id;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

61

static const u32 hpd_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v10_0.c

655

static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

657

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

683

u32 dram_channels; /* number of dram channels */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

684

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

685

u32 sclk; /* engine clock in kHz */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

686

u32 disp_clk; /* display clock in kHz */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

687

u32 src_width; /* viewport width */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

688

u32 active_time; /* active display time in ns */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

689

u32 blank_time; /* blank time in ns */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

692

u32 num_heads; /* number of active crtcs */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

693

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

694

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

695

u32 vtaps; /* vertical scaler taps */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

707

static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

736

static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

765

static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

794

static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

825

static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

828

u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

829

u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

830

u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

844

static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

877

static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

880

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

881

u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

882

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

883

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

884

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

885

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/drm/amd/amdgpu/dce_v10_0.c

887

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

888

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

889

u32 tmp, dmif_size = 12288;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

978

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

979

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

980

u32 latency_tolerant_lines;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

981

u32 latency_hiding;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1004

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1005

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1006

u32 latency_tolerant_lines;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1007

u32 latency_hiding;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1041

u32 lb_size, u32 num_heads)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1045

u32 active_time;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1046

u32 line_time = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1047

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1048

u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1051

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1052

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1053

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1054

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1055

line_time = min(line_time, (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1085

latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1124

latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1174

u32 num_heads = 0, lb_size;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1194

u32 offset, tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

121

static const u32 cz_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1228

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1246

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

127

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1288

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

133

static const u32 stoney_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1381

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

139

static const u32 polaris11_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1426

static const u32 pin_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

148

static const u32 polaris10_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1507

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1555

static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1562

u32 dto_phase = 24 * 1000;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1563

u32 dto_modulo = clock;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1564

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1596

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1828

static const u32 vga_control_regs[6] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1843

u32 vga_control;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1876

u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1877

u32 pipe_config;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1878

u32 tmp, viewport_w, viewport_h;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

189

static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

190

u32 block_offset, u32 reg)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

193

u32 r;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

204

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2048

(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2050

(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2117

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2134

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

214

static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2257

static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2262

u32 pll_in_use;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2358

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2369

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

254

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

272

u32 *vbl, u32 *position)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3046

u32 srbm_soft_reset = 0, tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3075

u32 lb_interrupt_mask;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3104

u32 lb_interrupt_mask;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3134

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

318

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3212

u32 reg;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3286

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3301

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3316

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

344

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

395

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

411

static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

418

u32 crtc_hung = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

419

u32 crtc_status[6];

sys/dev/drm/amd/amdgpu/dce_v11_0.c

420

u32 i, j, tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

449

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

497

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

50

static const u32 crtc_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

525

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

607

static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

61

static const u32 hpd_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v11_0.c

611

u32 tmp, buffer_alloc, i, mem_cfg;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

612

u32 pipe_offset = amdgpu_crtc->crtc_id;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

681

static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

683

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

709

u32 dram_channels; /* number of dram channels */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

710

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

711

u32 sclk; /* engine clock in kHz */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

712

u32 disp_clk; /* display clock in kHz */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

713

u32 src_width; /* viewport width */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

714

u32 active_time; /* active display time in ns */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

715

u32 blank_time; /* blank time in ns */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

718

u32 num_heads; /* number of active crtcs */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

719

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

720

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

721

u32 vtaps; /* vertical scaler taps */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

733

static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

762

static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

791

static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

820

static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

851

static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

854

u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

855

u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

856

u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

870

static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

903

static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

906

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

907

u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

908

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

909

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

910

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

911

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/drm/amd/amdgpu/dce_v11_0.c

913

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

914

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

915

u32 tmp, dmif_size = 12288;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1033

latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1085

u32 num_heads = 0, lb_size;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1105

u32 offset, tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1139

u32 offset;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1158

u32 tmp = 0, offset;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

119

static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

120

u32 block_offset, u32 reg)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1215

u32 offset, tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

123

u32 r;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1262

u32 offset;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1308

u32 value = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

134

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1354

static const u32 pin_offsets[7] =

sys/dev/drm/amd/amdgpu/dce_v8_0.c

144

static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1464

static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1471

u32 dto_phase = 24 * 1000;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1472

u32 dto_modulo = clock;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1715

static const u32 vga_control_regs[6] =

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1730

u32 vga_control;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1763

u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1764

u32 pipe_config;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1765

u32 viewport_w, viewport_h;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1918

(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1920

(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

199

u32 *vbl, u32 *position)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2114

static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2119

u32 pll_in_use;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

245

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

271

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2808

u32 srbm_soft_reset = 0, tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2837

u32 reg_block, lb_interrupt_mask;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2888

u32 reg_block, lb_interrupt_mask;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2940

u32 dc_hpd_int_cntl;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3055

u32 reg;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

313

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

329

static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

336

u32 crtc_hung = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

337

u32 crtc_status[6];

sys/dev/drm/amd/amdgpu/dce_v8_0.c

338

u32 i, j, tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

366

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

411

u32 tmp;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

439

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

51

static const u32 crtc_offsets[6] =

sys/dev/drm/amd/amdgpu/dce_v8_0.c

518

static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

522

u32 tmp, buffer_alloc, i;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

523

u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

590

static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

592

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

61

static const u32 hpd_offsets[] =

sys/dev/drm/amd/amdgpu/dce_v8_0.c

618

u32 dram_channels; /* number of dram channels */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

619

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

620

u32 sclk; /* engine clock in kHz */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

621

u32 disp_clk; /* display clock in kHz */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

622

u32 src_width; /* viewport width */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

623

u32 active_time; /* active display time in ns */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

624

u32 blank_time; /* blank time in ns */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

627

u32 num_heads; /* number of active crtcs */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

628

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

629

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

630

u32 vtaps; /* vertical scaler taps */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

642

static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

671

static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

700

static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

729

static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

760

static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

763

u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

764

u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

765

u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

779

static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

812

static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

815

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

816

u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

817

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

818

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

819

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

820

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/drm/amd/amdgpu/dce_v8_0.c

822

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

823

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

824

u32 tmp, dmif_size = 12288;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

913

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

914

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

915

u32 latency_tolerant_lines;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

916

u32 latency_hiding;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

950

u32 lb_size, u32 num_heads)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

954

u32 active_time;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

955

u32 line_time = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

956

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

957

u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

960

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

961

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

962

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

963

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

964

line_time = min(line_time, (u32)65535);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

994

latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);

sys/dev/drm/amd/amdgpu/dce_virtual.c

52

static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/drm/amd/amdgpu/dce_virtual.c

64

u32 *vbl, u32 *position)

sys/dev/drm/amd/amdgpu/dce_virtual.c

84

static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/df_v1_7.c

30

static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};

sys/dev/drm/amd/amdgpu/df_v1_7.c

39

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v1_7.c

50

static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/df_v1_7.c

52

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v1_7.c

61

static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/df_v1_7.c

73

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v1_7.c

95

u32 *flags)

sys/dev/drm/amd/amdgpu/df_v1_7.c

97

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v3_6.c

100

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v3_6.c

30

static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,

sys/dev/drm/amd/amdgpu/df_v3_6.c

40

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v3_6.c

51

static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/df_v3_6.c

53

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v3_6.c

62

static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/df_v3_6.c

76

u32 tmp;

sys/dev/drm/amd/amdgpu/df_v3_6.c

98

u32 *flags)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1024

const u32 num_tile_mode_states =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1026

const u32 num_secondary_tile_mode_states =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1028

u32 reg_offset, split_equal_to_row_size;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

111

static const u32 spectre_rlc_save_restore_register_list[] =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1588

u32 se_num, u32 sh_num, u32 instance)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1590

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1620

static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1622

u32 data, mask;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1637

gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1670

u32 raster_config, u32 raster_config_1,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1789

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1790

u32 raster_config = 0, raster_config_1 = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1791

u32 active_rbs = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1792

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1898

u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1899

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2110

u32 ref_and_mask;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2239

u32 header, control = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2268

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2567

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2568

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2771

u32 *hpd;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2805

u32 cp_mqd_base_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2806

u32 cp_mqd_base_addr_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2807

u32 cp_hqd_active;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2808

u32 cp_hqd_vmid;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2809

u32 cp_hqd_persistent_state;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2810

u32 cp_hqd_pipe_priority;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2811

u32 cp_hqd_queue_priority;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2812

u32 cp_hqd_quantum;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2813

u32 cp_hqd_pq_base;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2814

u32 cp_hqd_pq_base_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2815

u32 cp_hqd_pq_rptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2816

u32 cp_hqd_pq_rptr_report_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2817

u32 cp_hqd_pq_rptr_report_addr_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2818

u32 cp_hqd_pq_wptr_poll_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2819

u32 cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2820

u32 cp_hqd_pq_doorbell_control;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2821

u32 cp_hqd_pq_wptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2822

u32 cp_hqd_pq_control;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2823

u32 cp_hqd_ib_base_addr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2824

u32 cp_hqd_ib_base_addr_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2825

u32 cp_hqd_ib_rptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2826

u32 cp_hqd_ib_control;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2827

u32 cp_hqd_iq_timer;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2828

u32 cp_hqd_iq_rptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2829

u32 cp_hqd_dequeue_request;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2830

u32 cp_hqd_dma_offload;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2831

u32 cp_hqd_sema_cmd;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2832

u32 cp_hqd_msg_type;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2833

u32 cp_hqd_atomic0_preop_lo;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2834

u32 cp_hqd_atomic0_preop_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2835

u32 cp_hqd_atomic1_preop_lo;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2836

u32 cp_hqd_atomic1_preop_hi;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2837

u32 cp_hqd_hq_scheduler0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2838

u32 cp_hqd_hq_scheduler1;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2839

u32 cp_mqd_control;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2846

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3084

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3142

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3281

const u32 *src_ptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3282

volatile u32 *dst_ptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3283

u32 dws, i;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3292

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3296

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3377

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3389

u32 i, j, k;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3390

u32 mask;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3417

static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3419

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3426

static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3428

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3433

u32 i;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3452

u32 tmp, i, mask;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3474

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3514

u32 tmp = RREG32(mmGRBM_SOFT_RESET);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3538

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3593

u32 data, orig, tmp, tmp2;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3636

u32 data, orig, tmp = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3737

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3751

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3764

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3777

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3791

volatile u32 *dst_ptr;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3793

u32 bo_offset = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3794

u32 table_offset, table_size;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3859

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3887

u32 bitmap)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3889

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3900

static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3902

u32 data, mask;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3917

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3930

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3944

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3960

u32 data, orig;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3961

u32 i;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4014

static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4016

u32 count = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4047

volatile u32 *buffer)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4049

u32 count = 0, i;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4278

u32 me, u32 pipe, u32 q)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4329

u32 gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4330

u32 mc_shared_chmap, mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4331

u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4332

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4682

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4698

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4699

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4778

u32 cp_int_cntl;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4800

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4852

u32 cp_int_cntl;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4877

u32 cp_int_cntl;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5177

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5180

u32 ao_cu_num;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

558

static const u32 kalindi_rlc_save_restore_register_list[] =

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

883

static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

884

static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1255

volatile u32 *buffer)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1257

u32 count = 0, i;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1304

volatile u32 *dst_ptr;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1306

u32 bo_offset = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1307

u32 table_offset, table_size;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1374

volatile u32 *dst_ptr;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1375

u32 dws;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1435

u32 *hpd;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1463

static const u32 vgpr_init_compute_shader[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1500

static const u32 sgpr_init_compute_shader[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1525

static const u32 vgpr_init_regs[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1546

static const u32 sgpr1_init_regs[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1567

static const u32 sgpr2_init_regs[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1588

static const u32 sec_ded_counter_registers[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1623

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1782

u32 gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1783

u32 mc_shared_chmap, mc_arb_ramcfg;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1784

u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1785

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

193

static const u32 golden_settings_tonga_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

213

static const u32 tonga_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2202

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2203

const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2204

u32 reg_offset;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

225

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

304

static const u32 golden_settings_vegam_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

325

static const u32 vegam_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

335

static const u32 golden_settings_polaris11_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3522

u32 se_num, u32 sh_num, u32 instance)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3524

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3545

u32 me, u32 pipe, u32 q)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3550

static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3552

u32 data, mask;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

356

static const u32 polaris11_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3566

gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3608

u32 raster_config, u32 raster_config_1,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

366

static const u32 golden_settings_polaris10_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3718

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3719

u32 raster_config = 0, raster_config_1 = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3720

u32 active_rbs = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3721

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3832

u32 tmp, sh_static_mem_cfg;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

387

static const u32 polaris10_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3914

u32 i, j, k;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3915

u32 mask;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3953

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

399

static const u32 fiji_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

413

static const u32 golden_settings_fiji_a10[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4189

u32 tmp = RREG32(mmCP_ME_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4206

static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4208

u32 count = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

428

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4300

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4335

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4336

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4484

static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

467

static const u32 golden_settings_iceland_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

487

static const u32 iceland_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

499

static const u32 iceland_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5004

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5005

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5066

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5108

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5109

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5170

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5508

static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5600

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5634

u32 data = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

567

static const u32 cz_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

583

static const u32 cz_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

595

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6093

u32 ref_and_mask, reg_mem_engine;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6139

u32 header, control = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6169

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6532

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

674

static const u32 stoney_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6771

u32 enc, se_id, sh_id, cu_id;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

688

static const u32 stoney_golden_common_all[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

700

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7081

u32 bitmap)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7083

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7094

static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7096

u32 data, mask;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7109

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7112

u32 ao_cu_num;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

724

static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1071

volatile u32 *dst_ptr;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1073

u32 bo_offset = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1074

u32 table_offset, table_size;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1145

volatile u32 *dst_ptr;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1146

u32 dws;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1252

u32 *hpd;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1255

u32 *fw;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1373

u32 me, u32 pipe, u32 q)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1389

u32 gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1592

u32 data, base;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1867

static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1869

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1889

static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1891

u32 data, mask;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1908

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1909

u32 active_rbs = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1910

u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1963

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2024

u32 i, j, k;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2025

u32 mask;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2063

u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2131

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2133

u32 *register_list_format =

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2440

u32 rlc_ucode_ver;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2535

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

263

static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2670

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2671

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

275

static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2758

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

299

static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

346

(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3481

u32 grbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3482

u32 tmp;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3970

static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4050

u32 ref_and_mask, reg_mem_engine;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4080

u32 header, control = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4111

u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4543

u32 mec_int_cntl, mec_int_cntl_reg;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4949

u32 bitmap)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4951

u32 data;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4962

static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4964

u32 data, mask;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4981

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

852

static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

854

u32 count = 0;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

881

volatile u32 *buffer)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

883

u32 count = 0, i;

sys/dev/drm/amd/amdgpu/gfx_v9_0.h

29

void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

101

(u32)(adev->dummy_page_addr >> 12));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

103

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

287

u32 tmp;

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

288

u32 i;

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

317

u32 tmp;

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

54

(u32)(adev->gmc.gart_start >> 12));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

56

(u32)(adev->gmc.gart_start >> 44));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

59

(u32)(adev->gmc.gart_end >> 12));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

61

(u32)(adev->gmc.gart_end >> 44));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

95

(u32)(value >> 12));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

97

(u32)(value >> 44));

sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c

33

u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c

34

u32 max_region =

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

108

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1168

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1180

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1201

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1202

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1249

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1250

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1289

u32 addr, status, mc_client, vmid;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1319

u32 protections = REG_GET_FIELD(status,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

183

u32 running;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

259

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

325

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

517

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

58

static const u32 golden_settings_iceland_a11[] =

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

607

u32 tmp, field;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

652

(u32)(adev->dummy_page_addr >> 12));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

66

static const u32 iceland_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

682

(u32)(adev->dummy_page_addr >> 12));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

735

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

763

static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

764

u32 addr, u32 mc_client, unsigned pasid)

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

766

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

767

u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

771

u32 mc_id;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

784

static const u32 mc_cg_registers[] = {

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

796

static const u32 mc_cg_ls_en[] = {

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

808

static const u32 mc_cg_en[] = {

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

824

u32 orig, data;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

841

u32 orig, data;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

857

u32 orig, data;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

880

u32 orig, data;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

89

u32 blackout;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

896

u32 orig, data;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

963

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

969

u32 viewport = RREG32(mmVIEWPORT_SIZE);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

989

u32 tmp = RREG32(mmMC_SEQ_MISC0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

100

static const u32 golden_settings_polaris10_a11[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1007

static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1008

u32 addr, u32 mc_client, unsigned pasid)

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1010

u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1011

u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1015

u32 mc_id;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1081

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1087

u32 viewport = RREG32(mmVIEWPORT_SIZE);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

109

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1109

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

114

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

120

static const u32 golden_settings_stoney_common[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1302

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1314

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1335

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1337

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1376

u32 srbm_soft_reset;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1383

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1420

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1421

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1461

u32 addr, status, mc_client, vmid;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1503

u32 protections = REG_GET_FIELD(status,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1711

static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

177

u32 blackout;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

196

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

300

u32 running;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

369

u32 data;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

450

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

527

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

63

static const u32 golden_settings_tonga_a11[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

74

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

742

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

770

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

79

static const u32 golden_settings_fiji_a10[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

834

u32 tmp, field;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

87

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

895

(u32)(adev->dummy_page_addr >> 12));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

92

static const u32 golden_settings_polaris11_a11[] =

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

925

(u32)(adev->dummy_page_addr >> 12));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

979

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1091

u32 tmp;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1243

static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

208

u32 tmp, reg, bits, i, j;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

298

u32 req = 0;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

384

u32 tmp = gmc_v9_0_get_invalidate_req(vmid);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

61

static const u32 golden_settings_vega10_hdp[] =

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

882

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

896

u32 viewport;

sys/dev/drm/amd/amdgpu/iceland_ih.c

107

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/drm/amd/amdgpu/iceland_ih.c

188

static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/iceland_ih.c

190

u32 wptr, tmp;

sys/dev/drm/amd/amdgpu/iceland_ih.c

219

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/iceland_ih.c

250

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/iceland_ih.c

358

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/iceland_ih.c

369

u32 tmp;

sys/dev/drm/amd/amdgpu/iceland_ih.c

384

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/iceland_ih.c

386

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/iceland_ih.c

60

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/drm/amd/amdgpu/iceland_ih.c

61

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/iceland_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/iceland_ih.c

80

u32 ih_cntl = RREG32(mmIH_CNTL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

100

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1043

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1109

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1163

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

126

u32 v = RREG32(mmDOUT_SCRATCH3);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1405

u16 reg_offset, u32 value)

sys/dev/drm/amd/amdgpu/kv_dpm.c

141

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1414

u16 reg_offset, u32 *value)

sys/dev/drm/amd/amdgpu/kv_dpm.c

142

u32 n = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

143

u32 prev_sclk = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1500

u32 mask;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1530

static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

163

u32 i, j;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1777

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2111

u32 enable_mask, i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2131

u32 enable_mask, i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2149

u32 sclk, u32 min_sclk_in_sr)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2152

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2153

u32 temp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2154

u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2211

u32 min_sclk = 10000; /* ??? */

sys/dev/drm/amd/amdgpu/kv_dpm.c

2212

u32 sclk, mclk = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2217

u32 stable_p_state_sclk = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2322

u32 index, bool enable)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2332

u32 sclk_in_sr = 10000; /* ??? */

sys/dev/drm/amd/amdgpu/kv_dpm.c

2333

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2350

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2354

u32 mclk = max_limits->mclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2404

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2418

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2423

u32 vid_2bit;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2467

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2475

static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2477

u32 new_mask = (1 << level);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2487

u32 i, new_mask = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2502

u32 nbdpmconfig1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2526

u32 tmp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2687

u32 sclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2779

u32 sclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2870

u32 current_index =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2874

u32 sclk, tmp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2929

static u32 kv_dpm_get_sclk(void *handle, bool low)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2941

static u32 kv_dpm_get_mclk(void *handle, bool low)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2952

u32 temp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3144

u32 cg_thermal_int;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3287

u32 pl_index =

sys/dev/drm/amd/amdgpu/kv_dpm.c

390

u32 i, count, data;

sys/dev/drm/amd/amdgpu/kv_dpm.c

415

u32 data;

sys/dev/drm/amd/amdgpu/kv_dpm.c

416

u32 cache = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

463

u32 data;

sys/dev/drm/amd/amdgpu/kv_dpm.c

57

static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);

sys/dev/drm/amd/amdgpu/kv_dpm.c

586

u32 tmp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

663

u32 index, u32 sclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

687

u32 vid_2bit)

sys/dev/drm/amd/amdgpu/kv_dpm.c

690

u32 vid_8bit = kv_convert_vid2_to_vid7(adev,

sys/dev/drm/amd/amdgpu/kv_dpm.c

698

static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)

sys/dev/drm/amd/amdgpu/kv_dpm.c

709

static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)

sys/dev/drm/amd/amdgpu/kv_dpm.c

719

u32 index, bool enable)

sys/dev/drm/amd/amdgpu/kv_dpm.c

72

static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/kv_dpm.c

728

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/kv_dpm.c

74

u32 vid_2bit)

sys/dev/drm/amd/amdgpu/kv_dpm.c

743

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

754

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

78

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

784

u32 low_sclk_interrupt_t = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

794

sizeof(u32), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

802

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

872

static u32 kv_get_clock_difference(u32 a, u32 b)

sys/dev/drm/amd/amdgpu/kv_dpm.c

877

static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

880

u32 value;

sys/dev/drm/amd/amdgpu/kv_dpm.c

909

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

94

static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/kv_dpm.c

96

u32 vid_7bit)

sys/dev/drm/amd/amdgpu/kv_dpm.c

977

u32 i;

sys/dev/drm/amd/amdgpu/kv_dpm.h

109

u32 num_levels;

sys/dev/drm/amd/amdgpu/kv_dpm.h

118

u32 bootup_uma_clk;

sys/dev/drm/amd/amdgpu/kv_dpm.h

119

u32 bootup_sclk;

sys/dev/drm/amd/amdgpu/kv_dpm.h

120

u32 dentist_vco_freq;

sys/dev/drm/amd/amdgpu/kv_dpm.h

121

u32 nb_dpm_enable;

sys/dev/drm/amd/amdgpu/kv_dpm.h

122

u32 nbp_memory_clock[KV_NUM_NBPSTATES];

sys/dev/drm/amd/amdgpu/kv_dpm.h

123

u32 nbp_n_clock[KV_NUM_NBPSTATES];

sys/dev/drm/amd/amdgpu/kv_dpm.h

129

u32 uma_channel_number;

sys/dev/drm/amd/amdgpu/kv_dpm.h

133

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/amd/amdgpu/kv_dpm.h

134

u32 voltage_drop_t;

sys/dev/drm/amd/amdgpu/kv_dpm.h

141

u32 lowest_valid;

sys/dev/drm/amd/amdgpu/kv_dpm.h

142

u32 highest_valid;

sys/dev/drm/amd/amdgpu/kv_dpm.h

147

u32 sram_end;

sys/dev/drm/amd/amdgpu/kv_dpm.h

148

u32 dpm_table_start;

sys/dev/drm/amd/amdgpu/kv_dpm.h

149

u32 soft_regs_start;

sys/dev/drm/amd/amdgpu/kv_dpm.h

178

u32 low_sclk_interrupt_t;

sys/dev/drm/amd/amdgpu/kv_dpm.h

217

int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id);

sys/dev/drm/amd/amdgpu/kv_dpm.h

218

int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);

sys/dev/drm/amd/amdgpu/kv_dpm.h

220

PPSMC_Msg msg, u32 parameter);

sys/dev/drm/amd/amdgpu/kv_dpm.h

221

int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/drm/amd/amdgpu/kv_dpm.h

222

u32 *value, u32 limit);

sys/dev/drm/amd/amdgpu/kv_dpm.h

226

u32 smc_start_address,

sys/dev/drm/amd/amdgpu/kv_dpm.h

227

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/amd/amdgpu/kv_dpm.h

43

u32 num_entries;

sys/dev/drm/amd/amdgpu/kv_dpm.h

48

u32 sclk_frequency;

sys/dev/drm/amd/amdgpu/kv_dpm.h

54

u32 num_max_dpm_entries;

sys/dev/drm/amd/amdgpu/kv_dpm.h

71

u32 offset;

sys/dev/drm/amd/amdgpu/kv_dpm.h

72

u32 mask;

sys/dev/drm/amd/amdgpu/kv_dpm.h

73

u32 shift;

sys/dev/drm/amd/amdgpu/kv_dpm.h

74

u32 value;

sys/dev/drm/amd/amdgpu/kv_dpm.h

79

u32 block_id;

sys/dev/drm/amd/amdgpu/kv_dpm.h

80

u32 signal_id;

sys/dev/drm/amd/amdgpu/kv_dpm.h

81

u32 t;

sys/dev/drm/amd/amdgpu/kv_dpm.h

85

u32 cntl;

sys/dev/drm/amd/amdgpu/kv_dpm.h

86

u32 block_mask;

sys/dev/drm/amd/amdgpu/kv_dpm.h

87

u32 block_shift;

sys/dev/drm/amd/amdgpu/kv_dpm.h

88

u32 signal_mask;

sys/dev/drm/amd/amdgpu/kv_dpm.h

89

u32 signal_shift;

sys/dev/drm/amd/amdgpu/kv_dpm.h

90

u32 t_mask;

sys/dev/drm/amd/amdgpu/kv_dpm.h

91

u32 t_shift;

sys/dev/drm/amd/amdgpu/kv_dpm.h

92

u32 enable_mask;

sys/dev/drm/amd/amdgpu/kv_dpm.h

93

u32 enable_shift;

sys/dev/drm/amd/amdgpu/kv_dpm.h

97

u32 sclk;

sys/dev/drm/amd/amdgpu/kv_smc.c

123

u32 smc_start_address,

sys/dev/drm/amd/amdgpu/kv_smc.c

124

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/amd/amdgpu/kv_smc.c

127

u32 data, original_data, addr, extra_shift, t_byte, count, mask;

sys/dev/drm/amd/amdgpu/kv_smc.c

33

int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id)

sys/dev/drm/amd/amdgpu/kv_smc.c

35

u32 i;

sys/dev/drm/amd/amdgpu/kv_smc.c

36

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/kv_smc.c

57

int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask)

sys/dev/drm/amd/amdgpu/kv_smc.c

70

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/amd/amdgpu/kv_smc.c

79

u32 smc_address, u32 limit)

sys/dev/drm/amd/amdgpu/kv_smc.c

93

int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/drm/amd/amdgpu/kv_smc.c

94

u32 *value, u32 limit)

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

113

(u32)(value >> 12));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

115

(u32)(value >> 44));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

119

(u32)(adev->dummy_page_addr >> 12));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

121

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

319

u32 tmp;

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

320

u32 i;

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

350

u32 tmp;

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

548

void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

71

(u32)(adev->gmc.gart_start >> 12));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

73

(u32)(adev->gmc.gart_start >> 44));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

76

(u32)(adev->gmc.gart_end >> 12));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

78

(u32)(adev->gmc.gart_end >> 44));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.h

34

void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

117

enum idh_request req, u32 data1, u32 data2, u32 data3) {

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

118

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

226

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

278

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

63

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

125

static const u32 xgpu_fiji_golden_common_all[] = {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

138

static const u32 xgpu_tonga_mgcg_cgcg_init[] = {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

228

static const u32 xgpu_tonga_golden_settings_a11[] = {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

268

static const u32 xgpu_tonga_golden_common_all[] = {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

320

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

322

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

344

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

355

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

368

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

369

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

391

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

392

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

47

static const u32 xgpu_fiji_mgcg_cgcg_init[] = {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

503

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

533

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

97

static const u32 xgpu_fiji_golden_settings_a10[] = {

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

100

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

120

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

133

u32 interrupt_cntl;

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

196

u32 *flags)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

211

static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

216

static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

221

static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

226

static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

36

static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

38

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

68

static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

76

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

79

u32 doorbell_range = RREG32(reg);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

103

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

191

u32 *flags)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

208

u32 interrupt_cntl;

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

222

static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

227

static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

232

static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

237

static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

37

static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

39

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

66

static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

74

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

77

u32 doorbell_range = RREG32(reg);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

114

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

153

u32 *flags)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

170

u32 interrupt_cntl;

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

184

static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

189

static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

194

static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

199

static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

35

static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

37

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

64

static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

72

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

75

u32 doorbell_range = RREG32(reg);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

95

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1023

u32 sdma_cntl;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

207

u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

274

u32 ref_and_mask = 0;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

337

u32 rb_cntl, ib_cntl;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

378

u32 f32_cntl;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

407

u32 rb_cntl, ib_cntl;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

408

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

409

u32 wb_offset;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

549

u32 tmp;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

57

static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

610

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

63

static const u32 golden_settings_iceland_a11[] =

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

71

static const u32 iceland_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

764

u32 pad_count;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

951

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

963

u32 tmp;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

979

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

981

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1035

u32 pad_count;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

109

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

115

static const u32 golden_settings_polaris11_a11[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1237

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1249

u32 tmp;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1266

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1267

u32 tmp = RREG32(mmSRBM_STATUS2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1287

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

129

static const u32 golden_settings_polaris10_a11[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1306

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1325

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1326

u32 tmp;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1358

u32 sdma_cntl;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

143

static const u32 cz_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1542

static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

159

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

165

static const u32 stoney_golden_settings_a11[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

173

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

363

u32 wptr;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

387

u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

392

u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

448

u32 ref_and_mask = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

511

u32 rb_cntl, ib_cntl;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

552

u32 f32_cntl, phase_quantum = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

613

u32 f32_cntl;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

642

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

643

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

644

u32 wb_offset;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

645

u32 doorbell;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

71

static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

77

static const u32 golden_settings_tonga_a11[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

821

u32 tmp;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

882

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

91

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

97

static const u32 golden_settings_fiji_a10[] =

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1055

u32 tmp = 0;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1211

u32 pad_count;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1414

u32 i;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1417

u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1429

u32 sdma0, sdma1;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1455

u32 sdma_cntl;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1457

u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1664

static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

197

static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

198

u32 instance, u32 offset)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

371

u32 lowbit, highbit;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

500

u32 ref_and_mask = 0;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

564

u32 rb_cntl, ib_cntl;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

606

u32 f32_cntl, phase_quantum = 0;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

660

u32 f32_cntl;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

686

u32 rb_cntl, ib_cntl, wptr_poll_cntl;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

687

u32 rb_bufsz;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

688

u32 wb_offset;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

689

u32 doorbell;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

690

u32 doorbell_offset;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

691

u32 temp;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

908

u32 fw_size;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

993

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

116

static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =

sys/dev/drm/amd/amdgpu/si_dpm.c

1843

u16 reg_offset, u32 value);

sys/dev/drm/amd/amdgpu/si_dpm.c

1848

u32 engine_clock,

sys/dev/drm/amd/amdgpu/si_dpm.c

1862

u16 v, s32 t, u32 ileakage, u32 *leakage)

sys/dev/drm/amd/amdgpu/si_dpm.c

1892

u32 i_leakage,

sys/dev/drm/amd/amdgpu/si_dpm.c

1893

u32 *leakage)

sys/dev/drm/amd/amdgpu/si_dpm.c

1899

const u32 fixed_kt, u16 v,

sys/dev/drm/amd/amdgpu/si_dpm.c

1900

u32 ileakage, u32 *leakage)

sys/dev/drm/amd/amdgpu/si_dpm.c

1918

const u32 fixed_kt,

sys/dev/drm/amd/amdgpu/si_dpm.c

1920

u32 i_leakage,

sys/dev/drm/amd/amdgpu/si_dpm.c

1921

u32 *leakage)

sys/dev/drm/amd/amdgpu/si_dpm.c

1930

u32 p_limit1 = adev->pm.dpm.tdp_limit;

sys/dev/drm/amd/amdgpu/si_dpm.c

1931

u32 p_limit2 = adev->pm.dpm.near_tdp_limit;

sys/dev/drm/amd/amdgpu/si_dpm.c

1932

u32 k = dte_data->k;

sys/dev/drm/amd/amdgpu/si_dpm.c

1933

u32 t_max = dte_data->max_t;

sys/dev/drm/amd/amdgpu/si_dpm.c

1934

u32 t_split[5] = { 10, 15, 20, 25, 30 };

sys/dev/drm/amd/amdgpu/si_dpm.c

1935

u32 t_0 = dte_data->t0;

sys/dev/drm/amd/amdgpu/si_dpm.c

1936

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

1943

(t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /

sys/dev/drm/amd/amdgpu/si_dpm.c

1944

(p_limit2 * (u32)100);

sys/dev/drm/amd/amdgpu/si_dpm.c

2182

static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/si_dpm.c

2187

static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/si_dpm.c

2189

u32 xclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

2190

u32 wintime;

sys/dev/drm/amd/amdgpu/si_dpm.c

2191

u32 cac_window;

sys/dev/drm/amd/amdgpu/si_dpm.c

2192

u32 cac_window_size;

sys/dev/drm/amd/amdgpu/si_dpm.c

2207

static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)

sys/dev/drm/amd/amdgpu/si_dpm.c

2214

u32 tdp_adjustment,

sys/dev/drm/amd/amdgpu/si_dpm.c

2215

u32 *tdp_limit,

sys/dev/drm/amd/amdgpu/si_dpm.c

2216

u32 *near_tdp_limit)

sys/dev/drm/amd/amdgpu/si_dpm.c

2218

u32 adjustment_delta, max_tdp_limit;

sys/dev/drm/amd/amdgpu/si_dpm.c

2220

if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)

sys/dev/drm/amd/amdgpu/si_dpm.c

2255

u32 scaling_factor = si_get_smc_power_scaling_factor(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

2256

u32 tdp_limit;

sys/dev/drm/amd/amdgpu/si_dpm.c

2257

u32 near_tdp_limit;

sys/dev/drm/amd/amdgpu/si_dpm.c

2284

sizeof(u32) * 3,

sys/dev/drm/amd/amdgpu/si_dpm.c

2318

u32 scaling_factor = si_get_smc_power_scaling_factor(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

2333

sizeof(u32) * 2,

sys/dev/drm/amd/amdgpu/si_dpm.c

2391

u32 prev_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

2392

u32 max_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

2393

u32 min_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

2437

min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;

sys/dev/drm/amd/amdgpu/si_dpm.c

2482

u32 sq_power_throttle, sq_power_throttle2;

sys/dev/drm/amd/amdgpu/si_dpm.c

2569

u32 table_size;

sys/dev/drm/amd/amdgpu/si_dpm.c

2571

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

2615

for (i = 0; i < (u32)tdep_count; i++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

2636

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

2637

u32 v0_loadline;

sys/dev/drm/amd/amdgpu/si_dpm.c

2680

u32 leakage;

sys/dev/drm/amd/amdgpu/si_dpm.c

2683

u32 smc_leakage;

sys/dev/drm/amd/amdgpu/si_dpm.c

2684

u32 scaling_factor;

sys/dev/drm/amd/amdgpu/si_dpm.c

2719

u32 leakage;

sys/dev/drm/amd/amdgpu/si_dpm.c

2721

u32 smc_leakage;

sys/dev/drm/amd/amdgpu/si_dpm.c

2722

u32 scaling_factor;

sys/dev/drm/amd/amdgpu/si_dpm.c

2756

u32 load_line_slope, reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

2758

u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;

sys/dev/drm/amd/amdgpu/si_dpm.c

2798

load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;

sys/dev/drm/amd/amdgpu/si_dpm.c

2803

cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);

sys/dev/drm/amd/amdgpu/si_dpm.c

2804

cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);

sys/dev/drm/amd/amdgpu/si_dpm.c

2811

cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);

sys/dev/drm/amd/amdgpu/si_dpm.c

2812

cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);

sys/dev/drm/amd/amdgpu/si_dpm.c

2839

u32 data = 0, offset;

sys/dev/drm/amd/amdgpu/si_dpm.c

2950

u32 fb_div, p_div;

sys/dev/drm/amd/amdgpu/si_dpm.c

2951

u32 clk_s, clk_v;

sys/dev/drm/amd/amdgpu/si_dpm.c

2952

u32 sclk = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

2954

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

3034

u32 evclk, u32 ecclk, u16 *voltage)

sys/dev/drm/amd/amdgpu/si_dpm.c

3036

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

3068

u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

3070

u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

3080

u32 arb_freq_src, u32 arb_freq_dest)

sys/dev/drm/amd/amdgpu/si_dpm.c

3082

u32 mc_arb_dram_timing;

sys/dev/drm/amd/amdgpu/si_dpm.c

3083

u32 mc_arb_dram_timing2;

sys/dev/drm/amd/amdgpu/si_dpm.c

3084

u32 burst_time;

sys/dev/drm/amd/amdgpu/si_dpm.c

3085

u32 mc_cg_config;

sys/dev/drm/amd/amdgpu/si_dpm.c

3217

static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,

sys/dev/drm/amd/amdgpu/si_dpm.c

3218

u32 max_clock, u32 requested_clock)

sys/dev/drm/amd/amdgpu/si_dpm.c

3234

static u32 btc_get_valid_mclk(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

3235

u32 max_mclk, u32 requested_mclk)

sys/dev/drm/amd/amdgpu/si_dpm.c

3241

static u32 btc_get_valid_sclk(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

3242

u32 max_sclk, u32 requested_sclk)

sys/dev/drm/amd/amdgpu/si_dpm.c

3249

u32 *max_clock)

sys/dev/drm/amd/amdgpu/si_dpm.c

3251

u32 i, clock = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

3266

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/drm/amd/amdgpu/si_dpm.c

3268

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

3337

static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/drm/amd/amdgpu/si_dpm.c

3338

u32 *p, u32 *u)

sys/dev/drm/amd/amdgpu/si_dpm.c

3340

u32 b_c = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

3341

u32 i_c;

sys/dev/drm/amd/amdgpu/si_dpm.c

3342

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

3356

static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)

sys/dev/drm/amd/amdgpu/si_dpm.c

3358

u32 k, a, ah, al;

sys/dev/drm/amd/amdgpu/si_dpm.c

3359

u32 t1;

sys/dev/drm/amd/amdgpu/si_dpm.c

3377

static bool r600_is_uvd_state(u32 class, u32 class2)

sys/dev/drm/amd/amdgpu/si_dpm.c

3432

u32 mclk, sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

3434

u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

3435

u32 max_sclk = 0, max_mclk = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

3642

u16 reg_offset, u32 *value)

sys/dev/drm/amd/amdgpu/si_dpm.c

3653

u16 reg_offset, u32 value)

sys/dev/drm/amd/amdgpu/si_dpm.c

3665

u32 tmp, width, row, column, bank, density;

sys/dev/drm/amd/amdgpu/si_dpm.c

3710

u32 index, u16 *leakage_voltage)

sys/dev/drm/amd/amdgpu/si_dpm.c

3736

static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)

sys/dev/drm/amd/amdgpu/si_dpm.c

3811

u32 thermal_level)

sys/dev/drm/amd/amdgpu/si_dpm.c

3843

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/amd/amdgpu/si_dpm.c

3864

u32 levels = ps->performance_level_count;

sys/dev/drm/amd/amdgpu/si_dpm.c

3939

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

4101

u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;

sys/dev/drm/amd/amdgpu/si_dpm.c

4102

u32 vddc_dly, acpi_dly, vbi_dly;

sys/dev/drm/amd/amdgpu/si_dpm.c

4103

u32 reference_clock;

sys/dev/drm/amd/amdgpu/si_dpm.c

4107

voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;

sys/dev/drm/amd/amdgpu/si_dpm.c

4108

backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;

sys/dev/drm/amd/amdgpu/si_dpm.c

4131

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

4148

u32 tmp, pipe;

sys/dev/drm/amd/amdgpu/si_dpm.c

4207

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4265

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/amd/amdgpu/si_dpm.c

4289

static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/amd/amdgpu/si_dpm.c

4302

static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/drm/amd/amdgpu/si_dpm.c

4324

static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)

sys/dev/drm/amd/amdgpu/si_dpm.c

4358

u32 data, num_bits, num_levels;

sys/dev/drm/amd/amdgpu/si_dpm.c

4382

u32 max_voltage_steps,

sys/dev/drm/amd/amdgpu/si_dpm.c

4402

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

4562

(u32)si_pi->vddc_phase_shed_table.phase_delay);

sys/dev/drm/amd/amdgpu/si_dpm.c

4592

static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,

sys/dev/drm/amd/amdgpu/si_dpm.c

4622

for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4626

if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/amd/amdgpu/si_dpm.c

4637

for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4641

if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/amd/amdgpu/si_dpm.c

4652

if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/amd/amdgpu/si_dpm.c

4672

u16 voltage, u32 sclk, u32 mclk,

sys/dev/drm/amd/amdgpu/si_dpm.c

4692

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

4721

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

4737

static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

4738

u32 engine_clock)

sys/dev/drm/amd/amdgpu/si_dpm.c

4740

u32 dram_rows;

sys/dev/drm/amd/amdgpu/si_dpm.c

4741

u32 dram_refresh_rate;

sys/dev/drm/amd/amdgpu/si_dpm.c

4742

u32 mc_arb_rfsh_rate;

sys/dev/drm/amd/amdgpu/si_dpm.c

4743

u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

sys/dev/drm/amd/amdgpu/si_dpm.c

4760

u32 dram_timing;

sys/dev/drm/amd/amdgpu/si_dpm.c

4761

u32 dram_timing2;

sys/dev/drm/amd/amdgpu/si_dpm.c

4762

u32 burst_time;

sys/dev/drm/amd/amdgpu/si_dpm.c

4837

u32 reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

4956

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

4957

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.c

4958

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/si_dpm.c

4959

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/si_dpm.c

4960

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

4961

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

4962

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

4963

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

4964

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

4965

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/amd/amdgpu/si_dpm.c

4966

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.c

4967

u32 reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

5098

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/drm/amd/amdgpu/si_dpm.c

5163

u32 lane_width;

sys/dev/drm/amd/amdgpu/si_dpm.c

5164

u32 vr_hot_gpio;

sys/dev/drm/amd/amdgpu/si_dpm.c

5244

u32 engine_clock,

sys/dev/drm/amd/amdgpu/si_dpm.c

5250

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

5251

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.c

5252

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/si_dpm.c

5253

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/si_dpm.c

5254

u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/si_dpm.c

5255

u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/si_dpm.c

5257

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/si_dpm.c

5258

u32 reference_divider;

sys/dev/drm/amd/amdgpu/si_dpm.c

5259

u32 fbdiv;

sys/dev/drm/amd/amdgpu/si_dpm.c

5271

fbdiv = (u32) tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

5286

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/amd/amdgpu/si_dpm.c

5290

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/amd/amdgpu/si_dpm.c

5291

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/amd/amdgpu/si_dpm.c

5314

u32 engine_clock,

sys/dev/drm/amd/amdgpu/si_dpm.c

5335

u32 engine_clock,

sys/dev/drm/amd/amdgpu/si_dpm.c

5336

u32 memory_clock,

sys/dev/drm/amd/amdgpu/si_dpm.c

5343

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

5344

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

5345

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

5346

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

5347

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

5348

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/amd/amdgpu/si_dpm.c

5349

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.c

5350

u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;

sys/dev/drm/amd/amdgpu/si_dpm.c

5351

u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;

sys/dev/drm/amd/amdgpu/si_dpm.c

5377

u32 freq_nom;

sys/dev/drm/amd/amdgpu/si_dpm.c

5378

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

5379

u32 reference_clock = adev->clock.mpll.reference_freq;

sys/dev/drm/amd/amdgpu/si_dpm.c

5390

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/drm/amd/amdgpu/si_dpm.c

5391

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/drm/amd/amdgpu/si_dpm.c

5553

u32 a_t;

sys/dev/drm/amd/amdgpu/si_dpm.c

5554

u32 t_l, t_h;

sys/dev/drm/amd/amdgpu/si_dpm.c

5555

u32 high_bsp;

sys/dev/drm/amd/amdgpu/si_dpm.c

5659

u32 threshold;

sys/dev/drm/amd/amdgpu/si_dpm.c

5660

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/drm/amd/amdgpu/si_dpm.c

5736

u32 address = si_pi->state_table_start +

sys/dev/drm/amd/amdgpu/si_dpm.c

5738

u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +

sys/dev/drm/amd/amdgpu/si_dpm.c

5760

u32 address = si_pi->state_table_start +

sys/dev/drm/amd/amdgpu/si_dpm.c

5763

u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);

sys/dev/drm/amd/amdgpu/si_dpm.c

5819

u32 temp_reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

5950

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

6040

u32 i, j;

sys/dev/drm/amd/amdgpu/si_dpm.c

6058

u32 num_entries, u32 valid_flag)

sys/dev/drm/amd/amdgpu/si_dpm.c

6060

u32 i, j;

sys/dev/drm/amd/amdgpu/si_dpm.c

6075

u32 i = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

6147

u32 address = si_pi->mc_reg_table_start +

sys/dev/drm/amd/amdgpu/si_dpm.c

6187

u32 speed_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.c

6261

bool ds_status_on, u32 count_write)

sys/dev/drm/amd/amdgpu/si_dpm.c

6322

u32 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

6373

u32 lane_width;

sys/dev/drm/amd/amdgpu/si_dpm.c

6374

u32 new_lane_width =

sys/dev/drm/amd/amdgpu/si_dpm.c

6376

u32 current_lane_width =

sys/dev/drm/amd/amdgpu/si_dpm.c

6395

u32 thermal_int = RREG32(CG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/si_dpm.c

6440

static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)

sys/dev/drm/amd/amdgpu/si_dpm.c

6443

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6466

u32 duty100;

sys/dev/drm/amd/amdgpu/si_dpm.c

6467

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/drm/amd/amdgpu/si_dpm.c

6469

u32 reference_clock, tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6561

u32 *speed)

sys/dev/drm/amd/amdgpu/si_dpm.c

6563

u32 duty, duty100;

sys/dev/drm/amd/amdgpu/si_dpm.c

6578

*speed = (u32)tmp64;

sys/dev/drm/amd/amdgpu/si_dpm.c

6587

u32 speed)

sys/dev/drm/amd/amdgpu/si_dpm.c

6591

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6592

u32 duty, duty100;

sys/dev/drm/amd/amdgpu/si_dpm.c

6611

duty = (u32)tmp64;

sys/dev/drm/amd/amdgpu/si_dpm.c

6620

static void si_dpm_set_fan_control_mode(void *handle, u32 mode)

sys/dev/drm/amd/amdgpu/si_dpm.c

6638

static u32 si_dpm_get_fan_control_mode(void *handle)

sys/dev/drm/amd/amdgpu/si_dpm.c

6642

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6653

u32 *speed)

sys/dev/drm/amd/amdgpu/si_dpm.c

6655

u32 tach_period;

sys/dev/drm/amd/amdgpu/si_dpm.c

6656

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

6674

u32 speed)

sys/dev/drm/amd/amdgpu/si_dpm.c

6676

u32 tach_period, tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6677

u32 xclk = amdgpu_asic_get_xclk(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

6706

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6730

u32 tmp;

sys/dev/drm/amd/amdgpu/si_dpm.c

7287

u32 sclk, mclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

7487

u32 current_index =

sys/dev/drm/amd/amdgpu/si_dpm.c

7506

u32 cg_thermal_int;

sys/dev/drm/amd/amdgpu/si_dpm.c

7850

u32 temp;

sys/dev/drm/amd/amdgpu/si_dpm.c

7867

static u32 si_dpm_get_sclk(void *handle, bool low)

sys/dev/drm/amd/amdgpu/si_dpm.c

7879

static u32 si_dpm_get_mclk(void *handle, bool low)

sys/dev/drm/amd/amdgpu/si_dpm.c

7988

u32 pl_index =

sys/dev/drm/amd/amdgpu/si_dpm.c

97

static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =

sys/dev/drm/amd/amdgpu/si_dpm.h

1010

u32 t_min;

sys/dev/drm/amd/amdgpu/si_dpm.h

1011

u32 fan_ctrl_default_mode;

sys/dev/drm/amd/amdgpu/si_dpm.h

252

u32 at;

sys/dev/drm/amd/amdgpu/si_dpm.h

253

u32 bt;

sys/dev/drm/amd/amdgpu/si_dpm.h

254

u32 av;

sys/dev/drm/amd/amdgpu/si_dpm.h

255

u32 bv;

sys/dev/drm/amd/amdgpu/si_dpm.h

258

u32 t_ref;

sys/dev/drm/amd/amdgpu/si_dpm.h

270

u32 mclk_max;

sys/dev/drm/amd/amdgpu/si_dpm.h

271

u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/si_dpm.h

307

u32 mclk_max;

sys/dev/drm/amd/amdgpu/si_dpm.h

308

u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/si_dpm.h

335

u32 mc_arb_dram_timing;

sys/dev/drm/amd/amdgpu/si_dpm.h

336

u32 mc_arb_dram_timing2;

sys/dev/drm/amd/amdgpu/si_dpm.h

337

u32 mc_arb_rfsh_rate;

sys/dev/drm/amd/amdgpu/si_dpm.h

338

u32 mc_arb_burst_time;

sys/dev/drm/amd/amdgpu/si_dpm.h

342

u32 rlp;

sys/dev/drm/amd/amdgpu/si_dpm.h

343

u32 rmp;

sys/dev/drm/amd/amdgpu/si_dpm.h

344

u32 lhp;

sys/dev/drm/amd/amdgpu/si_dpm.h

345

u32 lmp;

sys/dev/drm/amd/amdgpu/si_dpm.h

349

u32 cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

350

u32 cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

351

u32 cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/si_dpm.h

352

u32 cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/si_dpm.h

353

u32 cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/si_dpm.h

354

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

355

u32 mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

356

u32 dll_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

357

u32 mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

358

u32 mpll_ad_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

359

u32 mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

360

u32 mpll_dq_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

361

u32 mpll_ss1;

sys/dev/drm/amd/amdgpu/si_dpm.h

362

u32 mpll_ss2;

sys/dev/drm/amd/amdgpu/si_dpm.h

492

u32 low_smio;

sys/dev/drm/amd/amdgpu/si_dpm.h

496

u32 cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

497

u32 cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

498

u32 cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/si_dpm.h

499

u32 cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/si_dpm.h

500

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

501

u32 mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

502

u32 mpll_ad_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

503

u32 mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

504

u32 mpll_dq_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

505

u32 mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

506

u32 dll_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

507

u32 mpll_ss1;

sys/dev/drm/amd/amdgpu/si_dpm.h

508

u32 mpll_ss2;

sys/dev/drm/amd/amdgpu/si_dpm.h

512

u32 cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

513

u32 cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

514

u32 cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/si_dpm.h

515

u32 cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/si_dpm.h

516

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

517

u32 mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

518

u32 dll_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

519

u32 mpll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

520

u32 mpll_func_cntl2;

sys/dev/drm/amd/amdgpu/si_dpm.h

521

u32 mpll_func_cntl3;

sys/dev/drm/amd/amdgpu/si_dpm.h

522

u32 mpll_ss;

sys/dev/drm/amd/amdgpu/si_dpm.h

523

u32 mpll_ss2;

sys/dev/drm/amd/amdgpu/si_dpm.h

553

u32 s0_vid_lower_smio_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

555

u32 vddc_mask_low;

sys/dev/drm/amd/amdgpu/si_dpm.h

556

u32 mvdd_mask_low;

sys/dev/drm/amd/amdgpu/si_dpm.h

557

u32 mvdd_split_frequency;

sys/dev/drm/amd/amdgpu/si_dpm.h

558

u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];

sys/dev/drm/amd/amdgpu/si_dpm.h

565

u32 mclk_odt_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

569

u32 boot_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.h

571

u32 ref_div;

sys/dev/drm/amd/amdgpu/si_dpm.h

572

u32 active_auto_throttle_sources;

sys/dev/drm/amd/amdgpu/si_dpm.h

573

u32 mclk_stutter_mode_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

574

u32 mclk_strobe_mode_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

575

u32 mclk_edc_enable_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

576

u32 bsp;

sys/dev/drm/amd/amdgpu/si_dpm.h

577

u32 bsu;

sys/dev/drm/amd/amdgpu/si_dpm.h

578

u32 pbsp;

sys/dev/drm/amd/amdgpu/si_dpm.h

579

u32 pbsu;

sys/dev/drm/amd/amdgpu/si_dpm.h

580

u32 dsp;

sys/dev/drm/amd/amdgpu/si_dpm.h

581

u32 psp;

sys/dev/drm/amd/amdgpu/si_dpm.h

582

u32 asi;

sys/dev/drm/amd/amdgpu/si_dpm.h

583

u32 pasi;

sys/dev/drm/amd/amdgpu/si_dpm.h

584

u32 vrc;

sys/dev/drm/amd/amdgpu/si_dpm.h

585

u32 restricted_levels;

sys/dev/drm/amd/amdgpu/si_dpm.h

586

u32 rlp;

sys/dev/drm/amd/amdgpu/si_dpm.h

587

u32 rmp;

sys/dev/drm/amd/amdgpu/si_dpm.h

588

u32 lhp;

sys/dev/drm/amd/amdgpu/si_dpm.h

589

u32 lmp;

sys/dev/drm/amd/amdgpu/si_dpm.h

599

u32 sclk;

sys/dev/drm/amd/amdgpu/si_dpm.h

600

u32 mclk;

sys/dev/drm/amd/amdgpu/si_dpm.h

603

u32 flags;

sys/dev/drm/amd/amdgpu/si_dpm.h

631

u32 i_leakage;

sys/dev/drm/amd/amdgpu/si_dpm.h

633

u32 pwr_const;

sys/dev/drm/amd/amdgpu/si_dpm.h

634

u32 dc_cac_value;

sys/dev/drm/amd/amdgpu/si_dpm.h

635

u32 bif_cac_value;

sys/dev/drm/amd/amdgpu/si_dpm.h

636

u32 lkge_pwr;

sys/dev/drm/amd/amdgpu/si_dpm.h

666

u32 mclk_edc_wr_enable_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

823

u32 mclk_rtt_mode_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

841

u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/drm/amd/amdgpu/si_dpm.h

854

u32 offset;

sys/dev/drm/amd/amdgpu/si_dpm.h

855

u32 mask;

sys/dev/drm/amd/amdgpu/si_dpm.h

856

u32 shift;

sys/dev/drm/amd/amdgpu/si_dpm.h

857

u32 value;

sys/dev/drm/amd/amdgpu/si_dpm.h

863

u32 cac_window;

sys/dev/drm/amd/amdgpu/si_dpm.h

864

u32 l2_lta_window_size_default;

sys/dev/drm/amd/amdgpu/si_dpm.h

869

u32 fixed_kt;

sys/dev/drm/amd/amdgpu/si_dpm.h

870

u32 lkge_lut_v0_percent;

sys/dev/drm/amd/amdgpu/si_dpm.h

877

u32 cac_leakage;

sys/dev/drm/amd/amdgpu/si_dpm.h

879

u32 wintime;

sys/dev/drm/amd/amdgpu/si_dpm.h

880

u32 l2_lta_window_size;

sys/dev/drm/amd/amdgpu/si_dpm.h

889

u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/drm/amd/amdgpu/si_dpm.h

890

u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/drm/amd/amdgpu/si_dpm.h

891

u32 k;

sys/dev/drm/amd/amdgpu/si_dpm.h

892

u32 t0;

sys/dev/drm/amd/amdgpu/si_dpm.h

893

u32 max_t;

sys/dev/drm/amd/amdgpu/si_dpm.h

899

u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/si_dpm.h

900

u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/si_dpm.h

901

u32 t_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.h

906

u32 cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

907

u32 cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

908

u32 cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/si_dpm.h

909

u32 cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/si_dpm.h

910

u32 cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/si_dpm.h

911

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

912

u32 dll_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

913

u32 mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

914

u32 mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

915

u32 mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

916

u32 mpll_func_cntl;

sys/dev/drm/amd/amdgpu/si_dpm.h

917

u32 mpll_func_cntl_1;

sys/dev/drm/amd/amdgpu/si_dpm.h

918

u32 mpll_func_cntl_2;

sys/dev/drm/amd/amdgpu/si_dpm.h

919

u32 mpll_ss1;

sys/dev/drm/amd/amdgpu/si_dpm.h

920

u32 mpll_ss2;

sys/dev/drm/amd/amdgpu/si_dpm.h

924

u32 mclk_max;

sys/dev/drm/amd/amdgpu/si_dpm.h

925

u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/si_dpm.h

951

u32 cg_ulv_control;

sys/dev/drm/amd/amdgpu/si_dpm.h

952

u32 cg_ulv_parameter;

sys/dev/drm/amd/amdgpu/si_dpm.h

953

u32 volt_change_delay;

sys/dev/drm/amd/amdgpu/si_dpm.h

968

u32 max_cu;

sys/dev/drm/amd/amdgpu/si_dpm.h

973

u32 sys_pcie_mask;

sys/dev/drm/amd/amdgpu/si_dpm.h

983

u32 sram_end;

sys/dev/drm/amd/amdgpu/si_dpm.h

984

u32 state_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

985

u32 soft_regs_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

986

u32 mc_reg_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

987

u32 arb_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

988

u32 cac_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

989

u32 dte_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

990

u32 spll_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

991

u32 papm_cfg_table_start;

sys/dev/drm/amd/amdgpu/si_dpm.h

992

u32 fan_table_start;

sys/dev/drm/amd/amdgpu/sislands_smc.h

407

u32 smc_start_address,

sys/dev/drm/amd/amdgpu/sislands_smc.h

408

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/amd/amdgpu/sislands_smc.h

416

int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);

sys/dev/drm/amd/amdgpu/sislands_smc.h

417

int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/drm/amd/amdgpu/sislands_smc.h

418

u32 *value, u32 limit);

sys/dev/drm/amd/amdgpu/sislands_smc.h

419

int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

sys/dev/drm/amd/amdgpu/sislands_smc.h

420

u32 value, u32 limit);

sys/dev/drm/amd/amdgpu/soc15.c

1021

static void soc15_common_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/soc15.c

108

static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

111

u32 r;

sys/dev/drm/amd/amdgpu/soc15.c

123

static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

136

static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

139

u32 r;

sys/dev/drm/amd/amdgpu/soc15.c

151

static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

164

static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

167

u32 r;

sys/dev/drm/amd/amdgpu/soc15.c

176

static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

186

static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

189

u32 r;

sys/dev/drm/amd/amdgpu/soc15.c

198

static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

208

static u32 soc15_get_config_memsize(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/soc15.c

213

static u32 soc15_get_xclk(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/soc15.c

220

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/amd/amdgpu/soc15.c

222

u32 grbm_gfx_cntl = 0;

sys/dev/drm/amd/amdgpu/soc15.c

243

u8 *bios, u32 length_bytes)

sys/dev/drm/amd/amdgpu/soc15.c

245

u32 *dw_ptr;

sys/dev/drm/amd/amdgpu/soc15.c

246

u32 i, length_dw;

sys/dev/drm/amd/amdgpu/soc15.c

256

dw_ptr = (u32 *)bios;

sys/dev/drm/amd/amdgpu/soc15.c

299

static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/drm/amd/amdgpu/soc15.c

300

u32 sh_num, u32 reg_offset)

sys/dev/drm/amd/amdgpu/soc15.c

317

bool indexed, u32 se_num,

sys/dev/drm/amd/amdgpu/soc15.c

318

u32 sh_num, u32 reg_offset)

sys/dev/drm/amd/amdgpu/soc15.c

331

static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/drm/amd/amdgpu/soc15.c

332

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/drm/amd/amdgpu/soc15.c

366

const u32 array_size)

sys/dev/drm/amd/amdgpu/soc15.c

369

u32 tmp, reg;

sys/dev/drm/amd/amdgpu/soc15.c

391

u32 i;

sys/dev/drm/amd/amdgpu/soc15.c

408

u32 memsize = adev->nbio_funcs->get_memsize(adev);

sys/dev/drm/amd/amdgpu/soc15.c

426

static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/drm/amd/amdgpu/soc15.c

439

static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/drm/amd/amdgpu/soc15.c

78

static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

81

u32 r;

sys/dev/drm/amd/amdgpu/soc15.c

93

static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.h

37

u32 hwip;

sys/dev/drm/amd/amdgpu/soc15.h

38

u32 instance;

sys/dev/drm/amd/amdgpu/soc15.h

39

u32 segment;

sys/dev/drm/amd/amdgpu/soc15.h

40

u32 reg;

sys/dev/drm/amd/amdgpu/soc15.h

41

u32 and_mask;

sys/dev/drm/amd/amdgpu/soc15.h

42

u32 or_mask;

sys/dev/drm/amd/amdgpu/soc15.h

51

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/drm/amd/amdgpu/soc15.h

56

const u32 array_size);

sys/dev/drm/amd/amdgpu/tonga_ih.c

103

u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;

sys/dev/drm/amd/amdgpu/tonga_ih.c

196

static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/tonga_ih.c

198

u32 wptr, tmp;

sys/dev/drm/amd/amdgpu/tonga_ih.c

230

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/tonga_ih.c

261

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/tonga_ih.c

381

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/tonga_ih.c

392

u32 tmp;

sys/dev/drm/amd/amdgpu/tonga_ih.c

408

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/tonga_ih.c

409

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/tonga_ih.c

447

u32 srbm_soft_reset;

sys/dev/drm/amd/amdgpu/tonga_ih.c

454

u32 tmp;

sys/dev/drm/amd/amdgpu/tonga_ih.c

60

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/tonga_ih.c

77

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

262

u32 tmp;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

264

u32 lmi_swap_cntl = 0;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

265

u32 mp_swap_cntl = 0;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

588

u32 orig, data;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

614

u32 tmp, tmp2;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

748

u32 orig, data;

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

818

static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1144

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1145

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1175

u32 srbm_soft_reset;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1182

u32 tmp;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1405

u32 orig, data;

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1476

static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

625

u32 data, data1;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1463

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1464

u32 tmp = RREG32(mmSRBM_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1496

u32 srbm_soft_reset;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1503

u32 tmp;

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1686

u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

377

u32 harvest;

sys/dev/drm/amd/amdgpu/vce_v2_0.c

149

u32 tmp;

sys/dev/drm/amd/amdgpu/vce_v2_0.c

312

u32 tmp;

sys/dev/drm/amd/amdgpu/vce_v2_0.c

347

u32 orig, tmp;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

113

u32 v;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

172

u32 data;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

367

u32 tmp;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

584

u32 mask = 0;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

613

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

654

u32 srbm_soft_reset;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

661

u32 tmp;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

81

u32 v;

sys/dev/drm/amd/amdgpu/vce_v3_0.c

812

static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/vce_v4_0.c

669

u32 mask = 0;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

698

u32 srbm_soft_reset = 0;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

739

u32 srbm_soft_reset;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

746

u32 tmp;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

794

u32 tmp, data;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

809

u32 data;

sys/dev/drm/amd/amdgpu/vce_v4_0.c

875

u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

194

static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/vega10_ih.c

196

u32 wptr, tmp;

sys/dev/drm/amd/amdgpu/vega10_ih.c

231

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/vega10_ih.c

232

u32 dw0, dw3, dw4, dw5;

sys/dev/drm/amd/amdgpu/vega10_ih.c

324

u32 ring_index = adev->irq.ih.rptr >> 2;

sys/dev/drm/amd/amdgpu/vega10_ih.c

47

u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

64

u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

91

u32 ih_rb_cntl, ih_doorbell_rtpr;

sys/dev/drm/amd/amdgpu/vega10_ih.c

92

u32 tmp;

sys/dev/drm/amd/amdgpu/vi.c

109

static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

112

u32 r;

sys/dev/drm/amd/amdgpu/vi.c

121

static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

135

static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

138

u32 r;

sys/dev/drm/amd/amdgpu/vi.c

147

static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

1531

static void vi_common_get_clockgating_state(void *handle, u32 *flags)

sys/dev/drm/amd/amdgpu/vi.c

157

static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

160

u32 r;

sys/dev/drm/amd/amdgpu/vi.c

169

static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

179

static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

182

u32 r;

sys/dev/drm/amd/amdgpu/vi.c

191

static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

201

static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

204

u32 r;

sys/dev/drm/amd/amdgpu/vi.c

213

static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

224

static const u32 tonga_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/vi.c

235

static const u32 fiji_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/vi.c

246

static const u32 iceland_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/vi.c

255

static const u32 cz_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/vi.c

264

static const u32 stoney_mgcg_cgcg_init[] =

sys/dev/drm/amd/amdgpu/vi.c

326

static u32 vi_get_xclk(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/vi.c

328

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/vi.c

329

u32 tmp;

sys/dev/drm/amd/amdgpu/vi.c

359

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/amd/amdgpu/vi.c

361

u32 srbm_gfx_cntl = 0;

sys/dev/drm/amd/amdgpu/vi.c

376

u32 bus_cntl;

sys/dev/drm/amd/amdgpu/vi.c

377

u32 d1vga_control = 0;

sys/dev/drm/amd/amdgpu/vi.c

378

u32 d2vga_control = 0;

sys/dev/drm/amd/amdgpu/vi.c

379

u32 vga_render_control = 0;

sys/dev/drm/amd/amdgpu/vi.c

380

u32 rom_cntl;

sys/dev/drm/amd/amdgpu/vi.c

420

u8 *bios, u32 length_bytes)

sys/dev/drm/amd/amdgpu/vi.c

422

u32 *dw_ptr;

sys/dev/drm/amd/amdgpu/vi.c

424

u32 i, length_dw;

sys/dev/drm/amd/amdgpu/vi.c

434

dw_ptr = (u32 *)bios;

sys/dev/drm/amd/amdgpu/vi.c

551

bool indexed, u32 se_num,

sys/dev/drm/amd/amdgpu/vi.c

552

u32 sh_num, u32 reg_offset)

sys/dev/drm/amd/amdgpu/vi.c

646

static int vi_read_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/drm/amd/amdgpu/vi.c

647

u32 sh_num, u32 reg_offset, u32 *value)

sys/dev/drm/amd/amdgpu/vi.c

667

u32 i;

sys/dev/drm/amd/amdgpu/vi.c

713

static u32 vi_get_config_memsize(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/vi.c

718

static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/drm/amd/amdgpu/vi.c

719

u32 cntl_reg, u32 status_reg)

sys/dev/drm/amd/amdgpu/vi.c

764

static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

sys/dev/drm/amd/amdgpu/vi.c

789

static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)

sys/dev/drm/amd/amdgpu/vi.c

793

u32 tmp;

sys/dev/drm/amd/amdgpu/vi.c

794

u32 reg_ctrl;

sys/dev/drm/amd/amdgpu/vi.c

795

u32 reg_status;

sys/dev/drm/amd/amdgpu/vi.c

796

u32 status_mask;

sys/dev/drm/amd/amdgpu/vi.c

797

u32 reg_mask;

sys/dev/drm/amd/amdgpu/vi.c

84

static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

87

u32 r;

sys/dev/drm/amd/amdgpu/vi.c

875

u32 tmp;

sys/dev/drm/amd/amdgpu/vi.c

97

static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

162

static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

183

u32 *vbl, u32 *position)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3635

static const u32 cursor_formats[] = {

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4018

static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

301

masterCmdData1.u32 = 0;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

304

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

706

masterCmdData1.u32 = 0;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

709

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

249

unsigned int u32;

sys/dev/drm/amd/include/amd_acpi.h

32

u32 notification_mask; /* supported notifications mask */

sys/dev/drm/amd/include/amd_acpi.h

33

u32 function_bits; /* supported functions bit vector */

sys/dev/drm/amd/include/amd_acpi.h

38

u32 valid_mask; /* valid flags mask */

sys/dev/drm/amd/include/amd_acpi.h

39

u32 flags; /* flags */

sys/dev/drm/amd/include/amd_acpi.h

45

u32 pending; /* pending sbios requests */

sys/dev/drm/amd/include/amd_acpi.h

63

u32 function_bits; /* supported functions bit vector */

sys/dev/drm/amd/include/amd_shared.h

188

void (*get_clockgating_state)(void *handle, u32 *flags);

sys/dev/drm/amd/include/kgd_pp_interface.h

218

void (*set_fan_control_mode)(void *handle, u32 mode);

sys/dev/drm/amd/include/kgd_pp_interface.h

219

u32 (*get_fan_control_mode)(void *handle);

sys/dev/drm/amd/include/kgd_pp_interface.h

220

int (*set_fan_speed_percent)(void *handle, u32 speed);

sys/dev/drm/amd/include/kgd_pp_interface.h

221

int (*get_fan_speed_percent)(void *handle, u32 *speed);

sys/dev/drm/amd/include/kgd_pp_interface.h

240

struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);

sys/dev/drm/amd/include/kgd_pp_interface.h

254

u32 (*get_sclk)(void *handle, bool low);

sys/dev/drm/amd/include/kgd_pp_interface.h

255

u32 (*get_mclk)(void *handle, bool low);

sys/dev/drm/amd/include/kgd_pp_interface.h

31

u32 evclk;

sys/dev/drm/amd/include/kgd_pp_interface.h

32

u32 ecclk;

sys/dev/drm/amd/include/kgd_pp_interface.h

34

u32 sclk;

sys/dev/drm/amd/include/kgd_pp_interface.h

35

u32 mclk;

sys/dev/drm/amd/include/linux/chash.h

321

static inline u32 chash_iter_key32(const struct chash_iter iter)

sys/dev/drm/amd/include/linux/chash.h

340

static inline u32 chash_iter_hash32(const struct chash_iter iter)

sys/dev/drm/amd/include/linux/chash.h

346

static inline u32 chash_iter_hash64(const struct chash_iter iter)

sys/dev/drm/amd/include/linux/chash.h

352

static inline u32 chash_iter_hash(const struct chash_iter iter)

sys/dev/drm/amd/include/linux/chash.h

44

u32 size_mask;

sys/dev/drm/amd/include/linux/chash.h

47

u32 *keys32;

sys/dev/drm/amd/lib/chash.c

194

u32 hash;

sys/dev/drm/amd/lib/chash.c

279

u32 hash = iter->slot;

sys/dev/drm/amd/lib/chash.c

319

u32 cur_hash = chash_iter_hash(*iter);

sys/dev/drm/amd/lib/chash.c

397

u32 hash = (table->key_size == 4) ?

sys/dev/drm/amd/lib/chash.c

432

u32 hash = (table->key_size == 4) ?

sys/dev/drm/amd/lib/chash.c

77

u32 __rem; \

sys/dev/drm/amd/lib/chash.c

94

u32 filled = 0, empty = 0, tombstones = 0;

sys/dev/drm/amd/lib/chash.c

96

u32 frac1, frac2;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3475

static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3478

u32 tmp = 0;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

86

uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

88

u32 mask = 0;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c

89

u32 shift = 0;

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

97

extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1947

u32 i;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

42

u32 display_cac;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

43

u32 bapm_temp_gradient;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1898

u32 mask = 0;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1905

u32 tmp = param_led_dpm.mask_low;

sys/dev/drm/drm_agpsupport.c

189

static void *drm_agp_allocate_memory(size_t pages, u32 type)

sys/dev/drm/drm_color_mgmt.c

413

u32 supported_encodings,

sys/dev/drm/drm_color_mgmt.c

414

u32 supported_ranges,

sys/dev/drm/drm_connector.c

1274

u32 scaling_mode_mask)

sys/dev/drm/drm_connector.c

721

const u32 *formats,

sys/dev/drm/drm_connector.c

724

u32 *fmts = NULL;

sys/dev/drm/drm_crtc.c

705

u32 out_id;

sys/dev/drm/drm_crtc_internal.h

187

int drm_mode_rmfb(struct drm_device *dev, u32 fb_id,

sys/dev/drm/drm_crtc_internal.h

231

u32 format, u64 modifier);

sys/dev/drm/drm_crtc_internal.h

253

u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid);

sys/dev/drm/drm_crtc_internal.h

79

int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,

sys/dev/drm/drm_dp_helper.c

1268

u32 quirks;

sys/dev/drm/drm_dp_helper.c

1294

static u32

sys/dev/drm/drm_dp_helper.c

1298

u32 quirks = 0;

sys/dev/drm/drm_dp_helper.c

668

static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)

sys/dev/drm/drm_dp_mst_topology.c

1407

static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes)

sys/dev/drm/drm_dp_mst_topology.c

2898

u32 numerator;

sys/dev/drm/drm_dp_mst_topology.c

2899

u32 denominator;

sys/dev/drm/drm_dp_mst_topology.c

3343

static u32 drm_dp_mst_i2c_functionality(struct i2c_adapter *adapter)

sys/dev/drm/drm_dp_mst_topology.c

668

static int build_dpcd_write(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes, u8 *bytes)

sys/dev/drm/drm_dumb_buffers.c

132

int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,

sys/dev/drm/drm_dumb_buffers.c

60

u32 cpp, stride, size;

sys/dev/drm/drm_edid.c

109

u32 quirks;

sys/dev/drm/drm_edid.c

1817

static u32 edid_get_quirks(const struct edid *edid)

sys/dev/drm/drm_edid.c

1845

u32 quirks)

sys/dev/drm/drm_edid.c

2259

u32 quirks)

sys/dev/drm/drm_edid.c

2390

static u32

sys/dev/drm/drm_edid.c

2409

u32 max_clock;

sys/dev/drm/drm_edid.c

2849

u32 quirks)

sys/dev/drm/drm_edid.c

4350

u32 max_tmds_clock = hf_vsdb[5] * 5000;

sys/dev/drm/drm_edid.c

4514

u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)

sys/dev/drm/drm_edid.c

4518

u32 quirks = edid_get_quirks(edid);

sys/dev/drm/drm_edid.c

4732

u32 quirks;

sys/dev/drm/drm_edid.c

5018

u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;

sys/dev/drm/drm_edid.c

5067

u32 s3d_flags;

sys/dev/drm/drm_edid.c

97

u32 quirks;

sys/dev/drm/drm_fb_helper.c

1040

static void drm_fb_helper_dirty(struct fb_info *info, u32 x, u32 y,

sys/dev/drm/drm_fb_helper.c

1041

u32 width, u32 height)

sys/dev/drm/drm_fb_helper.c

1051

clip->x1 = min_t(u32, clip->x1, x);

sys/dev/drm/drm_fb_helper.c

1052

clip->y1 = min_t(u32, clip->y1, y);

sys/dev/drm/drm_fb_helper.c

1053

clip->x2 = max_t(u32, clip->x2, x + width);

sys/dev/drm/drm_fb_helper.c

1054

clip->y2 = max_t(u32, clip->y2, y + height);

sys/dev/drm/drm_fb_helper.c

1073

u32 y1, y2;

sys/dev/drm/drm_fb_helper.c

1086

y2 = min_t(u32, DIV_ROUND_UP(max, info->fix.line_length),

sys/dev/drm/drm_fb_helper.c

1339

u32 *palette = (u32 *)info->pseudo_palette;

sys/dev/drm/drm_fb_helper.c

1349

u32 value;

sys/dev/drm/drm_fb_helper.c

1358

u32 mask = (1 << info->var.transp.length) - 1;

sys/dev/drm/drm_fb_helper.c

1922

sizes.fb_width = (u32)-1;

sys/dev/drm/drm_fb_helper.c

1923

sizes.fb_height = (u32)-1;

sys/dev/drm/drm_fb_helper.c

1985

sizes.surface_width = max_t(u32, desired_mode->hdisplay + x, sizes.surface_width);

sys/dev/drm/drm_fb_helper.c

1986

sizes.surface_height = max_t(u32, desired_mode->vdisplay + y, sizes.surface_height);

sys/dev/drm/drm_fb_helper.c

2000

sizes.fb_width = min_t(u32, desired_mode->hdisplay + x, sizes.fb_width);

sys/dev/drm/drm_fb_helper.c

2002

sizes.fb_height = min_t(u32, desired_mode->vdisplay + y, sizes.fb_height);

sys/dev/drm/drm_fb_helper.c

2554

u32 width, u32 height)

sys/dev/drm/drm_fb_helper.c

3145

u32 format;

sys/dev/drm/drm_fourcc.c

157

const struct drm_format_info *__drm_format_info(u32 format)

sys/dev/drm/drm_fourcc.c

251

const struct drm_format_info *drm_format_info(u32 format)

sys/dev/drm/drm_framebuffer.c

436

int drm_mode_rmfb(struct drm_device *dev, u32 fb_id,

sys/dev/drm/drm_gem.c

336

drm_gem_handle_delete(struct drm_file *filp, u32 handle)

sys/dev/drm/drm_gem.c

382

u32 handle, u64 *offset)

sys/dev/drm/drm_gem.c

443

u32 *handlep)

sys/dev/drm/drm_gem.c

446

u32 handle;

sys/dev/drm/drm_gem.c

510

u32 *handlep)

sys/dev/drm/drm_gem.c

621

drm_gem_object_lookup(struct drm_file *filp, u32 handle)

sys/dev/drm/drm_gem.c

729

u32 handle;

sys/dev/drm/drm_internal.h

116

u32 *handlep);

sys/dev/drm/drm_ioctl.c

535

int drm_ioctl_permit(u32 flags, struct drm_file *file_priv)

sys/dev/drm/drm_ioctl.c

761

u32 flags)

sys/dev/drm/drm_mipi_dsi.c

165

u32 reg;

sys/dev/drm/drm_modes.c

667

void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags)

sys/dev/drm/drm_modes.c

703

struct drm_display_mode *dmode, u32 *bus_flags,

sys/dev/drm/drm_plane.c

1021

u32 target_vblank = page_flip->sequence;

sys/dev/drm/drm_plane.c

1050

u32 current_vblank;

sys/dev/drm/drm_plane.c

1057

current_vblank = (u32)drm_crtc_vblank_count(crtc);

sys/dev/drm/drm_plane.c

564

u32 format, u64 modifier)

sys/dev/drm/drm_plane.c

74

static inline u32 *

sys/dev/drm/drm_plane.c

77

return (u32 *)(((char *)blob) + blob->formats_offset);

sys/dev/drm/drm_prime.c

951

u32 len, index;

sys/dev/drm/drm_property.c

158

u32 flags, const char *name,

sys/dev/drm/drm_property.c

206

u32 flags, const char *name,

sys/dev/drm/drm_property.c

238

u32 flags, const char *name,

sys/dev/drm/drm_property.c

273

u32 flags, const char *name,

sys/dev/drm/drm_property.c

301

u32 flags, const char *name,

sys/dev/drm/drm_property.c

328

u32 flags, const char *name,

sys/dev/drm/drm_property.c

365

u32 flags, const char *name)

sys/dev/drm/drm_property.c

53

static bool drm_property_flags_valid(u32 flags)

sys/dev/drm/drm_property.c

55

u32 legacy_type = flags & DRM_MODE_PROP_LEGACY_TYPE;

sys/dev/drm/drm_property.c

56

u32 ext_type = flags & DRM_MODE_PROP_EXTENDED_TYPE;

sys/dev/drm/drm_property.c

92

u32 flags, const char *name,

sys/dev/drm/drm_rect.c

103

u32 new_src_w = clip_scaled(drm_rect_width(src),

sys/dev/drm/drm_rect.c

111

u32 new_src_h = clip_scaled(drm_rect_height(src),

sys/dev/drm/drm_rect.c

53

static u32 clip_scaled(u32 src, u32 dst, u32 clip)

sys/dev/drm/drm_rect.c

87

u32 new_src_w = clip_scaled(drm_rect_width(src),

sys/dev/drm/drm_rect.c

95

u32 new_src_h = clip_scaled(drm_rect_height(src),

sys/dev/drm/drm_syncobj.c

233

u32 handle, u64 point,

sys/dev/drm/drm_syncobj.c

324

struct drm_syncobj *syncobj, u32 *handle)

sys/dev/drm/drm_syncobj.c

349

u32 *handle, uint32_t flags)

sys/dev/drm/drm_syncobj.c

364

u32 handle)

sys/dev/drm/drm_syncobj.c

432

u32 handle, int *p_fd)

sys/dev/drm/drm_syncobj.c

446

int fd, u32 *handle)

sys/dev/drm/drm_syncobj.c

84

u32 handle)

sys/dev/drm/drm_vblank.c

112

static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

118

static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1268

u32 cur_vblank, diff = 1;

sys/dev/drm/drm_vblank.c

147

u32 cur_vblank;

sys/dev/drm/drm_vblank.c

1502

static u64 widen_32_to_64(u32 narrow, u64 near)

sys/dev/drm/drm_vblank.c

1520

reply->tval_sec = (u32)ts.tv_sec;

sys/dev/drm/drm_vblank.c

1825

u32 flags;

sys/dev/drm/drm_vblank.c

196

u32 cur_vblank, diff;

sys/dev/drm/drm_vblank.c

93

u32 vblank_count_inc,

sys/dev/drm/drm_vblank.c

94

ktime_t t_vblank, u32 last)

sys/dev/drm/i915/dvo.h

38

u32 gpio;

sys/dev/drm/i915/gvt/gvt.h

127

u32 gfn[INTEL_GVT_OPREGION_PAGES];

sys/dev/drm/i915/gvt/gvt.h

243

u32 opregion_pa;

sys/dev/drm/i915/gvt/gvt.h

377

u32 fence, u64 value);

sys/dev/drm/i915/gvt/gvt.h

381

(*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

389

(*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

402

u32 offset, u32 val, bool low)

sys/dev/drm/i915/gvt/gvt.h

404

u32 *pval;

sys/dev/drm/i915/gvt/gvt.h

408

pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);

sys/dev/drm/i915/gvt/gvt.h

460

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);

sys/dev/drm/i915/gvt/gvt.h

489

int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);

sys/dev/drm/i915/gvt/gvt.h

491

int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);

sys/dev/drm/i915/gvt/gvt.h

67

u32 max_support_vgpus;

sys/dev/drm/i915/gvt/gvt.h

68

u32 cfg_space_size;

sys/dev/drm/i915/gvt/gvt.h

69

u32 mmio_size;

sys/dev/drm/i915/gvt/gvt.h

70

u32 mmio_bar;

sys/dev/drm/i915/gvt/gvt.h

72

u32 gtt_start_offset;

sys/dev/drm/i915/gvt/gvt.h

73

u32 gtt_entry_size;

sys/dev/drm/i915/gvt/gvt.h

74

u32 gtt_entry_size_shift;

sys/dev/drm/i915/gvt/gvt.h

76

u32 max_surface_size;

sys/dev/drm/i915/gvt/gvt.h

93

u32 base;

sys/dev/drm/i915/gvt/gvt.h

94

u32 size;

sys/dev/drm/i915/gvt/hypercall.h

45

int (*inject_msi)(unsigned long handle, u32 addr, u16 data);

sys/dev/drm/i915/gvt/mpt.h

122

u32 addr;

sys/dev/drm/i915/gvt/mpt.h

126

addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));

sys/dev/drm/i915/i915_cmd_parser.c

1013

__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)

sys/dev/drm/i915/i915_cmd_parser.c

1030

find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr)

sys/dev/drm/i915/i915_cmd_parser.c

1049

static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,

sys/dev/drm/i915/i915_cmd_parser.c

1051

u32 batch_start_offset,

sys/dev/drm/i915/i915_cmd_parser.c

1052

u32 batch_len,

sys/dev/drm/i915/i915_cmd_parser.c

108

u32 flags;

sys/dev/drm/i915/i915_cmd_parser.c

1130

const u32 *cmd, u32 length,

sys/dev/drm/i915/i915_cmd_parser.c

1153

const u32 step = desc->reg.step ? desc->reg.step : length;

sys/dev/drm/i915/i915_cmd_parser.c

1154

u32 offset;

sys/dev/drm/i915/i915_cmd_parser.c

1158

const u32 reg_addr = cmd[offset] & desc->reg.mask;

sys/dev/drm/i915/i915_cmd_parser.c

1200

u32 dword;

sys/dev/drm/i915/i915_cmd_parser.c

1206

u32 offset =

sys/dev/drm/i915/i915_cmd_parser.c

1208

u32 condition = cmd[offset] &

sys/dev/drm/i915/i915_cmd_parser.c

122

u32 value;

sys/dev/drm/i915/i915_cmd_parser.c

123

u32 mask;

sys/dev/drm/i915/i915_cmd_parser.c

1258

u32 batch_start_offset,

sys/dev/drm/i915/i915_cmd_parser.c

1259

u32 batch_len,

sys/dev/drm/i915/i915_cmd_parser.c

1262

u32 *cmd, *batch_end;

sys/dev/drm/i915/i915_cmd_parser.c

1283

u32 length;

sys/dev/drm/i915/i915_cmd_parser.c

134

u32 fixed;

sys/dev/drm/i915/i915_cmd_parser.c

135

u32 mask;

sys/dev/drm/i915/i915_cmd_parser.c

148

u32 offset;

sys/dev/drm/i915/i915_cmd_parser.c

149

u32 mask;

sys/dev/drm/i915/i915_cmd_parser.c

150

u32 step;

sys/dev/drm/i915/i915_cmd_parser.c

166

u32 offset;

sys/dev/drm/i915/i915_cmd_parser.c

167

u32 mask;

sys/dev/drm/i915/i915_cmd_parser.c

168

u32 expected;

sys/dev/drm/i915/i915_cmd_parser.c

169

u32 condition_offset;

sys/dev/drm/i915/i915_cmd_parser.c

170

u32 condition_mask;

sys/dev/drm/i915/i915_cmd_parser.c

513

u32 mask;

sys/dev/drm/i915/i915_cmd_parser.c

514

u32 value;

sys/dev/drm/i915/i915_cmd_parser.c

656

static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)

sys/dev/drm/i915/i915_cmd_parser.c

658

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/drm/i915/i915_cmd_parser.c

659

u32 subclient =

sys/dev/drm/i915/i915_cmd_parser.c

675

static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)

sys/dev/drm/i915/i915_cmd_parser.c

677

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/drm/i915/i915_cmd_parser.c

678

u32 subclient =

sys/dev/drm/i915/i915_cmd_parser.c

680

u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;

sys/dev/drm/i915/i915_cmd_parser.c

698

static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)

sys/dev/drm/i915/i915_cmd_parser.c

700

u32 client = cmd_header >> INSTR_CLIENT_SHIFT;

sys/dev/drm/i915/i915_cmd_parser.c

723

u32 previous = 0;

sys/dev/drm/i915/i915_cmd_parser.c

729

u32 curr = desc->cmd.value & desc->cmd.mask;

sys/dev/drm/i915/i915_cmd_parser.c

751

u32 previous = 0;

sys/dev/drm/i915/i915_cmd_parser.c

755

u32 curr = i915_mmio_reg_offset(reg_table[i].addr);

sys/dev/drm/i915/i915_cmd_parser.c

800

static inline u32 cmd_header_key(u32 x)

sys/dev/drm/i915/i915_cmd_parser.c

964

u32 cmd_header)

sys/dev/drm/i915/i915_cmd_parser.c

988

u32 cmd_header,

sys/dev/drm/i915/i915_cmd_parser.c

992

u32 mask;

sys/dev/drm/i915/i915_drv.c

1126

static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)

sys/dev/drm/i915/i915_drv.c

1154

skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)

sys/dev/drm/i915/i915_drv.c

1156

u32 tmp_l, tmp_s;

sys/dev/drm/i915/i915_drv.c

1157

u32 s_val = val >> SKL_DRAM_S_SHIFT;

sys/dev/drm/i915/i915_drv.c

1205

intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,

sys/dev/drm/i915/i915_drv.c

1220

u32 val_ch0, val_ch1;

sys/dev/drm/i915/i915_drv.c

1269

u32 mem_freq_khz, val;

sys/dev/drm/i915/i915_drv.c

1296

u32 dram_channels;

sys/dev/drm/i915/i915_drv.c

1297

u32 mem_freq_khz, val;

sys/dev/drm/i915/i915_drv.c

1322

u32 tmp;

sys/dev/drm/i915/i915_drv.c

2727

u32 val;

sys/dev/drm/i915/i915_drv.c

2812

u32 mask, u32 val)

sys/dev/drm/i915/i915_drv.c

2828

u32 val;

sys/dev/drm/i915/i915_drv.c

2855

u32 mask;

sys/dev/drm/i915/i915_drv.c

2856

u32 val;

sys/dev/drm/i915/i915_drv.c

2879

u32 mask;

sys/dev/drm/i915/i915_drv.c

2880

u32 val;

sys/dev/drm/i915/i915_drv.c

2908

u32 mask;

sys/dev/drm/i915/i915_drv.c

493

u32 temp_lo, temp_hi = 0;

sys/dev/drm/i915/i915_drv.c

535

u32 temp;

sys/dev/drm/i915/i915_drv.c

578

u32 deven_val;

sys/dev/drm/i915/i915_drv.c

586

u32 mchbar_val;

sys/dev/drm/i915/i915_drv.h

1032

u32 object_count;

sys/dev/drm/i915/i915_drv.h

1143

u32 size;

sys/dev/drm/i915/i915_drv.h

1327

u32 addr;

sys/dev/drm/i915/i915_drv.h

1328

u32 value;

sys/dev/drm/i915/i915_drv.h

1330

u32 mask;

sys/dev/drm/i915/i915_drv.h

1337

u32 count;

sys/dev/drm/i915/i915_drv.h

1342

u32 caps;

sys/dev/drm/i915/i915_drv.h

1353

u32 format;

sys/dev/drm/i915/i915_drv.h

1359

u32 value;

sys/dev/drm/i915/i915_drv.h

1367

u32 mux_regs_len;

sys/dev/drm/i915/i915_drv.h

1369

u32 b_counter_regs_len;

sys/dev/drm/i915/i915_drv.h

1371

u32 flex_regs_len;

sys/dev/drm/i915/i915_drv.h

1465

u32 sample_flags;

sys/dev/drm/i915/i915_drv.h

1508

u32 addr);

sys/dev/drm/i915/i915_drv.h

1514

bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);

sys/dev/drm/i915/i915_drv.h

1520

bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);

sys/dev/drm/i915/i915_drv.h

1580

u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);

sys/dev/drm/i915/i915_drv.h

1689

u32 irq_mask;

sys/dev/drm/i915/i915_drv.h

1690

u32 de_irq_mask[I915_MAX_PIPES];

sys/dev/drm/i915/i915_drv.h

1692

u32 gt_irq_mask;

sys/dev/drm/i915/i915_drv.h

1693

u32 pm_imr;

sys/dev/drm/i915/i915_drv.h

1694

u32 pm_ier;

sys/dev/drm/i915/i915_drv.h

1695

u32 pm_rps_events;

sys/dev/drm/i915/i915_drv.h

1696

u32 pm_guc_events;

sys/dev/drm/i915/i915_drv.h

1697

u32 pipestat_irq_mask[I915_MAX_PIPES];

sys/dev/drm/i915/i915_drv.h

1828

u32 edram_cap;

sys/dev/drm/i915/i915_drv.h

1886

u32 fdi_rx_config;

sys/dev/drm/i915/i915_drv.h

1889

u32 chv_phy_control;

sys/dev/drm/i915/i915_drv.h

1895

u32 chv_dpll_md[I915_MAX_PIPES];

sys/dev/drm/i915/i915_drv.h

1896

u32 bxt_phy_grc;

sys/dev/drm/i915/i915_drv.h

1898

u32 suspend_count;

sys/dev/drm/i915/i915_drv.h

1963

u32 bandwidth_kbps;

sys/dev/drm/i915/i915_drv.h

2004

u32 specific_ctx_id;

sys/dev/drm/i915/i915_drv.h

2005

u32 specific_ctx_id_mask;

sys/dev/drm/i915/i915_drv.h

2025

u32 last_ctx_id;

sys/dev/drm/i915/i915_drv.h

2066

u32 offset;

sys/dev/drm/i915/i915_drv.h

2091

u32 head;

sys/dev/drm/i915/i915_drv.h

2094

u32 gen7_latched_oastatus1;

sys/dev/drm/i915/i915_drv.h

2095

u32 ctx_oactxctrl_offset;

sys/dev/drm/i915/i915_drv.h

2096

u32 ctx_flexeu0_offset;

sys/dev/drm/i915/i915_drv.h

2103

u32 gen8_valid_ctx_bit;

sys/dev/drm/i915/i915_drv.h

2119

u32 active_requests;

sys/dev/drm/i915/i915_drv.h

2120

u32 request_serial;

sys/dev/drm/i915/i915_drv.h

2237

#define I915_GTT_OFFSET_NONE ((u32)-1)

sys/dev/drm/i915/i915_drv.h

2774

extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);

sys/dev/drm/i915/i915_drv.h

2798

u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);

sys/dev/drm/i915/i915_drv.h

2802

u32 pin_mask, u32 long_mask);

sys/dev/drm/i915/i915_drv.h

2831

u32 engine_mask,

sys/dev/drm/i915/i915_drv.h

2854

u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/i915_drv.h

2858

u32 status_mask);

sys/dev/drm/i915/i915_drv.h

2862

u32 status_mask);

sys/dev/drm/i915/i915_drv.h

300

u32 event_bits;

sys/dev/drm/i915/i915_drv.h

303

u32 long_port_mask;

sys/dev/drm/i915/i915_drv.h

304

u32 short_port_mask;

sys/dev/drm/i915/i915_drv.h

3172

int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);

sys/dev/drm/i915/i915_drv.h

3197

static inline u32 i915_reset_count(struct i915_gpu_error *error)

sys/dev/drm/i915/i915_drv.h

3202

static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,

sys/dev/drm/i915/i915_drv.h

3250

u32 alignment,

sys/dev/drm/i915/i915_drv.h

3289

__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)

sys/dev/drm/i915/i915_drv.h

3295

i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)

sys/dev/drm/i915/i915_drv.h

3389

u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,

sys/dev/drm/i915/i915_drv.h

3391

u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,

sys/dev/drm/i915/i915_drv.h

3415

u32 batch_start_offset,

sys/dev/drm/i915/i915_drv.h

3416

u32 batch_len,

sys/dev/drm/i915/i915_drv.h

3522

int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);

sys/dev/drm/i915/i915_drv.h

3523

int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,

sys/dev/drm/i915/i915_drv.h

3524

u32 val, int fast_timeout_us,

sys/dev/drm/i915/i915_drv.h

3529

int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,

sys/dev/drm/i915/i915_drv.h

3530

u32 reply_mask, u32 reply, int timeout_base_ms);

sys/dev/drm/i915/i915_drv.h

3533

u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);

sys/dev/drm/i915/i915_drv.h

3534

int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);

sys/dev/drm/i915/i915_drv.h

3535

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);

sys/dev/drm/i915/i915_drv.h

3536

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);

sys/dev/drm/i915/i915_drv.h

3537

void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3538

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3539

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3540

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3541

void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3542

u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3543

void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3544

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);

sys/dev/drm/i915/i915_drv.h

3545

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3546

u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,

sys/dev/drm/i915/i915_drv.h

3548

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

sys/dev/drm/i915/i915_drv.h

3550

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3551

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3557

enum port port, u32 margin, u32 scale,

sys/dev/drm/i915/i915_drv.h

3558

u32 enable, u32 deemphasis);

sys/dev/drm/i915/i915_drv.h

3571

u32 deemph_reg_value, u32 margin_reg_value,

sys/dev/drm/i915/i915_drv.h

3585

u32 demph_reg_value, u32 preemph_reg_value,

sys/dev/drm/i915/i915_drv.h

3586

u32 uniqtranscale_reg_value, u32 tx3_demph);

sys/dev/drm/i915/i915_drv.h

3599

u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);

sys/dev/drm/i915/i915_drv.h

3637

u32 upper, lower, old_upper, loop = 0; \

sys/dev/drm/i915/i915_drv.h

3769

u32 seqno;

sys/dev/drm/i915/i915_drv.h

3881

static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)

sys/dev/drm/i915/i915_drv.h

623

u32 debug;

sys/dev/drm/i915/i915_drv.h

670

u32 force_bit;

sys/dev/drm/i915/i915_drv.h

671

u32 reg0;

sys/dev/drm/i915/i915_drv.h

678

u32 saveDSPARB;

sys/dev/drm/i915/i915_drv.h

679

u32 saveFBC_CONTROL;

sys/dev/drm/i915/i915_drv.h

680

u32 saveCACHE_MODE_0;

sys/dev/drm/i915/i915_drv.h

681

u32 saveMI_ARB_STATE;

sys/dev/drm/i915/i915_drv.h

682

u32 saveSWF0[16];

sys/dev/drm/i915/i915_drv.h

683

u32 saveSWF1[16];

sys/dev/drm/i915/i915_drv.h

684

u32 saveSWF3[3];

sys/dev/drm/i915/i915_drv.h

686

u32 savePCH_PORT_HOTPLUG;

sys/dev/drm/i915/i915_drv.h

692

u32 wr_watermark;

sys/dev/drm/i915/i915_drv.h

693

u32 gfx_prio_ctrl;

sys/dev/drm/i915/i915_drv.h

694

u32 arb_mode;

sys/dev/drm/i915/i915_drv.h

695

u32 gfx_pend_tlb0;

sys/dev/drm/i915/i915_drv.h

696

u32 gfx_pend_tlb1;

sys/dev/drm/i915/i915_drv.h

697

u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];

sys/dev/drm/i915/i915_drv.h

698

u32 media_max_req_count;

sys/dev/drm/i915/i915_drv.h

699

u32 gfx_max_req_count;

sys/dev/drm/i915/i915_drv.h

700

u32 render_hwsp;

sys/dev/drm/i915/i915_drv.h

701

u32 ecochk;

sys/dev/drm/i915/i915_drv.h

702

u32 bsd_hwsp;

sys/dev/drm/i915/i915_drv.h

703

u32 blt_hwsp;

sys/dev/drm/i915/i915_drv.h

704

u32 tlb_rd_addr;

sys/dev/drm/i915/i915_drv.h

707

u32 g3dctl;

sys/dev/drm/i915/i915_drv.h

708

u32 gsckgctl;

sys/dev/drm/i915/i915_drv.h

709

u32 mbctl;

sys/dev/drm/i915/i915_drv.h

712

u32 ucgctl1;

sys/dev/drm/i915/i915_drv.h

713

u32 ucgctl3;

sys/dev/drm/i915/i915_drv.h

714

u32 rcgctl1;

sys/dev/drm/i915/i915_drv.h

715

u32 rcgctl2;

sys/dev/drm/i915/i915_drv.h

716

u32 rstctl;

sys/dev/drm/i915/i915_drv.h

717

u32 misccpctl;

sys/dev/drm/i915/i915_drv.h

720

u32 gfxpause;

sys/dev/drm/i915/i915_drv.h

721

u32 rpdeuhwtc;

sys/dev/drm/i915/i915_drv.h

722

u32 rpdeuc;

sys/dev/drm/i915/i915_drv.h

723

u32 ecobus;

sys/dev/drm/i915/i915_drv.h

724

u32 pwrdwnupctl;

sys/dev/drm/i915/i915_drv.h

725

u32 rp_down_timeout;

sys/dev/drm/i915/i915_drv.h

726

u32 rp_deucsw;

sys/dev/drm/i915/i915_drv.h

727

u32 rcubmabdtmr;

sys/dev/drm/i915/i915_drv.h

728

u32 rcedata;

sys/dev/drm/i915/i915_drv.h

729

u32 spare2gh;

sys/dev/drm/i915/i915_drv.h

732

u32 gt_imr;

sys/dev/drm/i915/i915_drv.h

733

u32 gt_ier;

sys/dev/drm/i915/i915_drv.h

734

u32 pm_imr;

sys/dev/drm/i915/i915_drv.h

735

u32 pm_ier;

sys/dev/drm/i915/i915_drv.h

736

u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

sys/dev/drm/i915/i915_drv.h

739

u32 tilectl;

sys/dev/drm/i915/i915_drv.h

740

u32 gt_fifoctl;

sys/dev/drm/i915/i915_drv.h

741

u32 gtlc_wake_ctrl;

sys/dev/drm/i915/i915_drv.h

742

u32 gtlc_survive;

sys/dev/drm/i915/i915_drv.h

743

u32 pmwgicz;

sys/dev/drm/i915/i915_drv.h

746

u32 gu_ctl0;

sys/dev/drm/i915/i915_drv.h

747

u32 gu_ctl1;

sys/dev/drm/i915/i915_drv.h

748

u32 pcbr;

sys/dev/drm/i915/i915_drv.h

749

u32 clock_gate_dis2;

sys/dev/drm/i915/i915_drv.h

754

u32 render_c0;

sys/dev/drm/i915/i915_drv.h

755

u32 media_c0;

sys/dev/drm/i915/i915_drv.h

765

u32 pm_iir;

sys/dev/drm/i915/i915_drv.h

768

u32 pm_intrmsk_mbz;

sys/dev/drm/i915/i915_drv.h

950

u32 *remap_info[MAX_L3_SLICES];

sys/dev/drm/i915/i915_gem.c

1251

u32 page_base = node.start;

sys/dev/drm/i915/i915_gem.c

1455

u32 page_base = node.start;

sys/dev/drm/i915/i915_gem.c

149

static u32 __i915_gem_park(struct drm_i915_private *i915)

sys/dev/drm/i915/i915_gem.c

4633

u32 alignment,

sys/dev/drm/i915/i915_gem.c

5643

static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)

sys/dev/drm/i915/i915_gem.c

5705

u32 temp = I915_READ(GEN7_MSG_CTL);

sys/dev/drm/i915/i915_gem.c

5709

u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);

sys/dev/drm/i915/i915_gem.c

74

struct drm_mm_node *node, u32 size)

sys/dev/drm/i915/i915_gem.c

743

u32 handle;

sys/dev/drm/i915/i915_gem_context.c

301

static u32 default_desc_template(const struct drm_i915_private *i915,

sys/dev/drm/i915/i915_gem_context.c

304

u32 address_mode;

sys/dev/drm/i915/i915_gem_context.c

305

u32 desc;

sys/dev/drm/i915/i915_gem_context.h

159

u32 user_handle;

sys/dev/drm/i915/i915_gem_context.h

168

u32 *lrc_reg_state;

sys/dev/drm/i915/i915_gem_context.h

176

u32 ring_size;

sys/dev/drm/i915/i915_gem_context.h

178

u32 desc_template;

sys/dev/drm/i915/i915_gem_execbuffer.c

1110

static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)

sys/dev/drm/i915/i915_gem_execbuffer.c

1141

u32 *cmd;

sys/dev/drm/i915/i915_gem_execbuffer.c

1225

static u32 *reloc_gpu(struct i915_execbuffer *eb,

sys/dev/drm/i915/i915_gem_execbuffer.c

1230

u32 *cmd;

sys/dev/drm/i915/i915_gem_execbuffer.c

1232

if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))

sys/dev/drm/i915/i915_gem_execbuffer.c

1272

u32 *batch;

sys/dev/drm/i915/i915_gem_execbuffer.c

1338

offset += sizeof(u32);

sys/dev/drm/i915/i915_gem_execbuffer.c

1910

u32 *cs;

sys/dev/drm/i915/i915_gem_execbuffer.c

271

u32 *rq_cmd;

sys/dev/drm/i915/i915_gem_execbuffer.c

276

u32 context_flags; /** Set of execobj.flags to insert from the ctx */

sys/dev/drm/i915/i915_gem_execbuffer.c

278

u32 batch_start_offset; /** Location within object of batch */

sys/dev/drm/i915/i915_gem_execbuffer.c

279

u32 batch_len; /** Length of batch within object */

sys/dev/drm/i915/i915_gem_execbuffer.c

280

u32 batch_flags; /** Flags composed for emit_bb_start() */

sys/dev/drm/i915/i915_gem_execbuffer.c

776

u32 handle = eb->exec[i].handle;

sys/dev/drm/i915/i915_gem_execbuffer.c

941

GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));

sys/dev/drm/i915/i915_gem_fence_reg.c

119

u32 val;

sys/dev/drm/i915/i915_gem_fence_reg.c

159

u32 val;

sys/dev/drm/i915/i915_gem_gtt.c

1043

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

1097

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

1113

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

1231

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

1491

u32 pml4e;

sys/dev/drm/i915/i915_gem_gtt.c

1529

u32 pdpe;

sys/dev/drm/i915/i915_gem_gtt.c

1535

u32 pde;

sys/dev/drm/i915/i915_gem_gtt.c

1542

u32 pte;

sys/dev/drm/i915/i915_gem_gtt.c

1729

u32 pte, pde;

sys/dev/drm/i915/i915_gem_gtt.c

1738

u32 expected =

sys/dev/drm/i915/i915_gem_gtt.c

1741

u32 pd_entry = readl(ppgtt->pd_addr + pde);

sys/dev/drm/i915/i915_gem_gtt.c

1794

u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?

sys/dev/drm/i915/i915_gem_gtt.c

1804

u32 ecochk, ecobits;

sys/dev/drm/i915/i915_gem_gtt.c

1828

u32 ecochk, gab_ctl, ecobits;

sys/dev/drm/i915/i915_gem_gtt.c

187

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

1889

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

189

u32 pte_flags;

sys/dev/drm/i915/i915_gem_gtt.c

1895

const u32 pte_encode = vm->pte_encode(0, cache_level, flags);

sys/dev/drm/i915/i915_gem_gtt.c

1974

u32 pde;

sys/dev/drm/i915/i915_gem_gtt.c

2007

u32 pde;

sys/dev/drm/i915/i915_gem_gtt.c

2039

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

2043

u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE;

sys/dev/drm/i915/i915_gem_gtt.c

2356

u32 fault;

sys/dev/drm/i915/i915_gem_gtt.c

2376

u32 fault = I915_READ(GEN8_RING_FAULT_REG);

sys/dev/drm/i915/i915_gem_gtt.c

2379

u32 fault_data0, fault_data1;

sys/dev/drm/i915/i915_gem_gtt.c

240

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2467

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

2481

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2510

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2530

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2609

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

2620

u32 flags;

sys/dev/drm/i915/i915_gem_gtt.c

2636

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2695

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

2706

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

2723

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2727

u32 pte_flags;

sys/dev/drm/i915/i915_gem_gtt.c

2761

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

2764

u32 pte_flags;

sys/dev/drm/i915/i915_gem_gtt.c

279

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

2942

ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,

sys/dev/drm/i915/i915_gem_gtt.c

301

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

325

u32 flags)

sys/dev/drm/i915/i915_gem_gtt.c

341

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

354

u32 unused)

sys/dev/drm/i915/i915_gem_gtt.c

618

const u32 v)

sys/dev/drm/i915/i915_gem_gtt.c

906

u32 pde;

sys/dev/drm/i915/i915_gem_gtt.h

226

u32 ggtt_offset;

sys/dev/drm/i915/i915_gem_gtt.h

260

u32 flags);

sys/dev/drm/i915/i915_gem_gtt.h

345

u32 flags); /* Create a valid PTE */

sys/dev/drm/i915/i915_gem_gtt.h

356

u32 flags);

sys/dev/drm/i915/i915_gem_gtt.h

360

u32 flags);

sys/dev/drm/i915/i915_gem_gtt.h

405

u32 pin_bias;

sys/dev/drm/i915/i915_gem_gtt.h

455

({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \

sys/dev/drm/i915/i915_gem_gtt.h

465

static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)

sys/dev/drm/i915/i915_gem_gtt.h

467

const u32 mask = NUM_PTE(pde_shift) - 1;

sys/dev/drm/i915/i915_gem_gtt.h

476

static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)

sys/dev/drm/i915/i915_gem_gtt.h

492

static inline u32 i915_pde_index(u64 addr, u32 shift)

sys/dev/drm/i915/i915_gem_gtt.h

497

static inline u32 gen6_pte_index(u32 addr)

sys/dev/drm/i915/i915_gem_gtt.h

502

static inline u32 gen6_pte_count(u32 addr, u32 length)

sys/dev/drm/i915/i915_gem_gtt.h

507

static inline u32 gen6_pde_index(u32 addr)

sys/dev/drm/i915/i915_gem_gtt.h

549

static inline u32 gen8_pte_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

554

static inline u32 gen8_pde_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

559

static inline u32 gen8_pdpe_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

564

static inline u32 gen8_pml4e_index(u64 address)

sys/dev/drm/i915/i915_gem_gtt.h

69

typedef u32 gen6_pte_t;

sys/dev/drm/i915/i915_gem_object.h

308

i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle)

sys/dev/drm/i915/i915_gem_object.h

317

i915_gem_object_lookup(struct drm_file *file, u32 handle)

sys/dev/drm/i915/i915_gem_object.h

333

drm_gem_object_lookup(struct drm_file *file, u32 handle);

sys/dev/drm/i915/i915_gem_object.h

51

u32 handle;

sys/dev/drm/i915/i915_gem_render_state.c

120

so->batch_size = rodata->batch_items * sizeof(u32);

sys/dev/drm/i915/i915_gem_render_state.c

125

so->aux_offset = i * sizeof(u32);

sys/dev/drm/i915/i915_gem_render_state.c

144

u32 eu_pool_config = 0x00777000;

sys/dev/drm/i915/i915_gem_render_state.c

155

so->aux_size = i * sizeof(u32) - so->aux_offset;

sys/dev/drm/i915/i915_gem_render_state.c

164

drm_clflush_virt_range(d, i * sizeof(u32));

sys/dev/drm/i915/i915_gem_render_state.c

36

u32 batch_offset;

sys/dev/drm/i915/i915_gem_render_state.c

37

u32 batch_size;

sys/dev/drm/i915/i915_gem_render_state.c

38

u32 aux_offset;

sys/dev/drm/i915/i915_gem_render_state.c

39

u32 aux_size;

sys/dev/drm/i915/i915_gem_render_state.c

73

if ((i) >= PAGE_SIZE / sizeof(u32)) \

sys/dev/drm/i915/i915_gem_render_state.c

84

u32 *d;

sys/dev/drm/i915/i915_gem_render_state.c

94

u32 s = rodata->batch[i];

sys/dev/drm/i915/i915_gem_stolen.c

205

u32 reg_val = I915_READ(IS_GM45(dev_priv) ?

sys/dev/drm/i915/i915_gem_stolen.c

235

u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);

sys/dev/drm/i915/i915_gem_stolen.c

267

u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);

sys/dev/drm/i915/i915_gem_stolen.c

295

u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);

sys/dev/drm/i915/i915_gem_stolen.c

321

u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);

sys/dev/drm/i915/i915_gem_stolen.c

353

u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED);

sys/dev/drm/i915/i915_gem_tiling.c

111

u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,

sys/dev/drm/i915/i915_gem_tiling.c

181

u32 size, alignment;

sys/dev/drm/i915/i915_gem_tiling.c

71

u32 i915_gem_fence_size(struct drm_i915_private *i915,

sys/dev/drm/i915/i915_gem_tiling.c

72

u32 size, unsigned int tiling, unsigned int stride)

sys/dev/drm/i915/i915_gem_tiling.c

74

u32 ggtt_size;

sys/dev/drm/i915/i915_gem_userptr.c

784

u32 handle;

sys/dev/drm/i915/i915_gpu_error.c

1057

static u32 capture_error_bo(struct drm_i915_error_buffer *err,

sys/dev/drm/i915/i915_gpu_error.c

1723

u32 engine_mask,

sys/dev/drm/i915/i915_gpu_error.c

1726

u32 ecode;

sys/dev/drm/i915/i915_gpu_error.c

1859

u32 engine_mask,

sys/dev/drm/i915/i915_gpu_error.c

483

(u32)(ee->acthd>>32), (u32)ee->acthd);

sys/dev/drm/i915/i915_gpu_error.c

499

(u32)(ee->bbaddr>>32), (u32)ee->bbaddr);

sys/dev/drm/i915/i915_gpu_error.c

973

dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), M_DRM,

sys/dev/drm/i915/i915_gpu_error.h

100

u32 last_seqno;

sys/dev/drm/i915/i915_gpu_error.h

103

u32 start;

sys/dev/drm/i915/i915_gpu_error.h

104

u32 tail;

sys/dev/drm/i915/i915_gpu_error.h

105

u32 head;

sys/dev/drm/i915/i915_gpu_error.h

106

u32 ctl;

sys/dev/drm/i915/i915_gpu_error.h

107

u32 mode;

sys/dev/drm/i915/i915_gpu_error.h

108

u32 hws;

sys/dev/drm/i915/i915_gpu_error.h

109

u32 ipeir;

sys/dev/drm/i915/i915_gpu_error.h

110

u32 ipehr;

sys/dev/drm/i915/i915_gpu_error.h

111

u32 bbstate;

sys/dev/drm/i915/i915_gpu_error.h

112

u32 instpm;

sys/dev/drm/i915/i915_gpu_error.h

113

u32 instps;

sys/dev/drm/i915/i915_gpu_error.h

114

u32 seqno;

sys/dev/drm/i915/i915_gpu_error.h

117

u32 fault_reg;

sys/dev/drm/i915/i915_gpu_error.h

119

u32 rc_psmi; /* sleep state */

sys/dev/drm/i915/i915_gpu_error.h

120

u32 semaphore_mboxes[I915_NUM_ENGINES - 1];

sys/dev/drm/i915/i915_gpu_error.h

126

u32 handle;

sys/dev/drm/i915/i915_gpu_error.h

127

u32 hw_id;

sys/dev/drm/i915/i915_gpu_error.h

141

u32 *pages[0];

sys/dev/drm/i915/i915_gpu_error.h

153

u32 context;

sys/dev/drm/i915/i915_gpu_error.h

155

u32 seqno;

sys/dev/drm/i915/i915_gpu_error.h

156

u32 start;

sys/dev/drm/i915/i915_gpu_error.h

157

u32 head;

sys/dev/drm/i915/i915_gpu_error.h

158

u32 tail;

sys/dev/drm/i915/i915_gpu_error.h

166

u32 seqno;

sys/dev/drm/i915/i915_gpu_error.h

170

u32 gfx_mode;

sys/dev/drm/i915/i915_gpu_error.h

173

u32 pp_dir_base;

sys/dev/drm/i915/i915_gpu_error.h

179

u32 size;

sys/dev/drm/i915/i915_gpu_error.h

180

u32 name;

sys/dev/drm/i915/i915_gpu_error.h

181

u32 wseqno;

sys/dev/drm/i915/i915_gpu_error.h

183

u32 read_domains;

sys/dev/drm/i915/i915_gpu_error.h

184

u32 write_domain;

sys/dev/drm/i915/i915_gpu_error.h

186

u32 tiling:2;

sys/dev/drm/i915/i915_gpu_error.h

187

u32 dirty:1;

sys/dev/drm/i915/i915_gpu_error.h

188

u32 purgeable:1;

sys/dev/drm/i915/i915_gpu_error.h

189

u32 userptr:1;

sys/dev/drm/i915/i915_gpu_error.h

191

u32 cache_level:3;

sys/dev/drm/i915/i915_gpu_error.h

193

u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;

sys/dev/drm/i915/i915_gpu_error.h

275

u32 reset_engine_count[I915_NUM_ENGINES];

sys/dev/drm/i915/i915_gpu_error.h

278

u32 stalled_mask;

sys/dev/drm/i915/i915_gpu_error.h

327

u32 engine_mask,

sys/dev/drm/i915/i915_gpu_error.h

362

u32 engine_mask,

sys/dev/drm/i915/i915_gpu_error.h

45

u32 reset_count;

sys/dev/drm/i915/i915_gpu_error.h

46

u32 suspend_count;

sys/dev/drm/i915/i915_gpu_error.h

58

u32 eir;

sys/dev/drm/i915/i915_gpu_error.h

59

u32 pgtbl_er;

sys/dev/drm/i915/i915_gpu_error.h

60

u32 ier;

sys/dev/drm/i915/i915_gpu_error.h

61

u32 gtier[6], ngtier;

sys/dev/drm/i915/i915_gpu_error.h

62

u32 ccid;

sys/dev/drm/i915/i915_gpu_error.h

63

u32 derrmr;

sys/dev/drm/i915/i915_gpu_error.h

64

u32 forcewake;

sys/dev/drm/i915/i915_gpu_error.h

65

u32 error; /* gen6+ */

sys/dev/drm/i915/i915_gpu_error.h

66

u32 err_int; /* gen7 */

sys/dev/drm/i915/i915_gpu_error.h

67

u32 fault_data0; /* gen8, gen9 */

sys/dev/drm/i915/i915_gpu_error.h

68

u32 fault_data1; /* gen8, gen9 */

sys/dev/drm/i915/i915_gpu_error.h

69

u32 done_reg;

sys/dev/drm/i915/i915_gpu_error.h

70

u32 gac_eco;

sys/dev/drm/i915/i915_gpu_error.h

71

u32 gam_ecochk;

sys/dev/drm/i915/i915_gpu_error.h

72

u32 gab_ctl;

sys/dev/drm/i915/i915_gpu_error.h

73

u32 gfx_mode;

sys/dev/drm/i915/i915_gpu_error.h

75

u32 nfence;

sys/dev/drm/i915/i915_gpu_error.h

91

u32 reset_count;

sys/dev/drm/i915/i915_gpu_error.h

94

u32 rq_head, rq_post, rq_tail;

sys/dev/drm/i915/i915_gpu_error.h

97

u32 cpu_ring_head;

sys/dev/drm/i915/i915_gpu_error.h

98

u32 cpu_ring_tail;

sys/dev/drm/i915/i915_irq.c

102

static const u32 hpd_status_i915[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

1119

u32 busy_up, busy_down, max_avg, min_avg;

sys/dev/drm/i915/i915_irq.c

112

static const u32 hpd_bxt[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

1157

const u32 seqno = intel_engine_get_seqno(engine);

sys/dev/drm/i915/i915_irq.c

118

static const u32 hpd_gen11[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

1238

static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)

sys/dev/drm/i915/i915_irq.c

1243

u32 events = 0;

sys/dev/drm/i915/i915_irq.c

125

static const u32 hpd_icp[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

1252

u32 render, media;

sys/dev/drm/i915/i915_irq.c

1285

u32 pm_iir = 0;

sys/dev/drm/i915/i915_irq.c

1377

u32 error_status, row, bank, subbank;

sys/dev/drm/i915/i915_irq.c

1446

u32 iir)

sys/dev/drm/i915/i915_irq.c

1466

u32 gt_iir)

sys/dev/drm/i915/i915_irq.c

1475

u32 gt_iir)

sys/dev/drm/i915/i915_irq.c

1494

gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)

sys/dev/drm/i915/i915_irq.c

1511

u32 master_ctl, u32 gt_iir[4])

sys/dev/drm/i915/i915_irq.c

1549

u32 master_ctl, u32 gt_iir[4])

sys/dev/drm/i915/i915_irq.c

1576

static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1592

static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1606

static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1618

static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1634

static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1644

static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1660

static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1670

static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1684

static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)

sys/dev/drm/i915/i915_irq.c

1706

u32 *pin_mask, u32 *long_mask,

sys/dev/drm/i915/i915_irq.c

1707

u32 hotplug_trigger, u32 dig_hotplug_reg,

sys/dev/drm/i915/i915_irq.c

1708

const u32 hpd[HPD_NUM_PINS],

sys/dev/drm/i915/i915_irq.c

1709

bool long_pulse_detect(enum hpd_pin pin, u32 val))

sys/dev/drm/i915/i915_irq.c

171

u32 val = I915_READ(reg);

sys/dev/drm/i915/i915_irq.c

1829

static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)

sys/dev/drm/i915/i915_irq.c

1855

static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)

sys/dev/drm/i915/i915_irq.c

1875

u32 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/drm/i915/i915_irq.c

1888

u32 status_mask, enable_mask, iir_bit = 0;

sys/dev/drm/i915/i915_irq.c

1940

u16 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/drm/i915/i915_irq.c

1957

u32 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/drm/i915/i915_irq.c

1981

u32 iir, u32 pipe_stats[I915_MAX_PIPES])

sys/dev/drm/i915/i915_irq.c

2008

u32 pipe_stats[I915_MAX_PIPES])

sys/dev/drm/i915/i915_irq.c

2027

static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_irq.c

2029

u32 hotplug_status = 0, hotplug_status_mask;

sys/dev/drm/i915/i915_irq.c

2049

u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;

sys/dev/drm/i915/i915_irq.c

2066

u32 hotplug_status)

sys/dev/drm/i915/i915_irq.c

2068

u32 pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2072

u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;

sys/dev/drm/i915/i915_irq.c

2086

u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;

sys/dev/drm/i915/i915_irq.c

2111

u32 iir, gt_iir, pm_iir;

sys/dev/drm/i915/i915_irq.c

2112

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/drm/i915/i915_irq.c

2113

u32 hotplug_status = 0;

sys/dev/drm/i915/i915_irq.c

2114

u32 ier = 0;

sys/dev/drm/i915/i915_irq.c

2197

u32 master_ctl, iir;

sys/dev/drm/i915/i915_irq.c

2198

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/drm/i915/i915_irq.c

2199

u32 hotplug_status = 0;

sys/dev/drm/i915/i915_irq.c

2200

u32 gt_iir[4];

sys/dev/drm/i915/i915_irq.c

2201

u32 ier = 0;

sys/dev/drm/i915/i915_irq.c

221

static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

sys/dev/drm/i915/i915_irq.c

222

static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

sys/dev/drm/i915/i915_irq.c

2266

u32 hotplug_trigger,

sys/dev/drm/i915/i915_irq.c

2267

const u32 hpd[HPD_NUM_PINS])

sys/dev/drm/i915/i915_irq.c

2269

u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2279

u32 mask = PORTA_HOTPLUG_STATUS_MASK |

sys/dev/drm/i915/i915_irq.c

2297

static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)

sys/dev/drm/i915/i915_irq.c

2300

u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;

sys/dev/drm/i915/i915_irq.c

2347

u32 err_int = I915_READ(GEN7_ERR_INT);

sys/dev/drm/i915/i915_irq.c

2370

u32 serr_int = I915_READ(SERR_INT);

sys/dev/drm/i915/i915_irq.c

2383

static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)

sys/dev/drm/i915/i915_irq.c

2386

u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;

sys/dev/drm/i915/i915_irq.c

2419

static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)

sys/dev/drm/i915/i915_irq.c

2421

u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;

sys/dev/drm/i915/i915_irq.c

2422

u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;

sys/dev/drm/i915/i915_irq.c

2423

u32 pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2426

u32 dig_hotplug_reg;

sys/dev/drm/i915/i915_irq.c

2438

u32 dig_hotplug_reg;

sys/dev/drm/i915/i915_irq.c

2456

static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)

sys/dev/drm/i915/i915_irq.c

2458

u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &

sys/dev/drm/i915/i915_irq.c

2460

u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;

sys/dev/drm/i915/i915_irq.c

2461

u32 pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2464

u32 dig_hotplug_reg;

sys/dev/drm/i915/i915_irq.c

2475

u32 dig_hotplug_reg;

sys/dev/drm/i915/i915_irq.c

2493

u32 hotplug_trigger,

sys/dev/drm/i915/i915_irq.c

2494

const u32 hpd[HPD_NUM_PINS])

sys/dev/drm/i915/i915_irq.c

2496

u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2509

u32 de_iir)

sys/dev/drm/i915/i915_irq.c

2512

u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;

sys/dev/drm/i915/i915_irq.c

2539

u32 pch_iir = I915_READ(SDEIIR);

sys/dev/drm/i915/i915_irq.c

2555

u32 de_iir)

sys/dev/drm/i915/i915_irq.c

2558

u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;

sys/dev/drm/i915/i915_irq.c

2567

u32 psr_iir = I915_READ(EDP_PSR_IIR);

sys/dev/drm/i915/i915_irq.c

2586

u32 pch_iir = I915_READ(SDEIIR);

sys/dev/drm/i915/i915_irq.c

2607

u32 de_iir, gt_iir, de_ier, sde_ier = 0;

sys/dev/drm/i915/i915_irq.c

262

static u32

sys/dev/drm/i915/i915_irq.c

2653

u32 pm_iir = I915_READ(GEN6_PMIIR);

sys/dev/drm/i915/i915_irq.c

2672

u32 hotplug_trigger,

sys/dev/drm/i915/i915_irq.c

2673

const u32 hpd[HPD_NUM_PINS])

sys/dev/drm/i915/i915_irq.c

2675

u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2687

static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)

sys/dev/drm/i915/i915_irq.c

2689

u32 pin_mask = 0, long_mask = 0;

sys/dev/drm/i915/i915_irq.c

2690

u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;

sys/dev/drm/i915/i915_irq.c

2691

u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;

sys/dev/drm/i915/i915_irq.c

2694

u32 dig_hotplug_reg;

sys/dev/drm/i915/i915_irq.c

2705

u32 dig_hotplug_reg;

sys/dev/drm/i915/i915_irq.c

271

u32 dw;

sys/dev/drm/i915/i915_irq.c

2722

gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)

sys/dev/drm/i915/i915_irq.c

2725

u32 iir;

sys/dev/drm/i915/i915_irq.c

2742

u32 psr_iir = I915_READ(EDP_PSR_IIR);

sys/dev/drm/i915/i915_irq.c

2770

u32 tmp_mask;

sys/dev/drm/i915/i915_irq.c

2823

u32 fault_errors;

sys/dev/drm/i915/i915_irq.c

2893

u32 master_ctl;

sys/dev/drm/i915/i915_irq.c

2894

u32 gt_iir[4];

sys/dev/drm/i915/i915_irq.c

2968

static u32

sys/dev/drm/i915/i915_irq.c

2973

u32 timeout_ts;

sys/dev/drm/i915/i915_irq.c

2974

u32 ident;

sys/dev/drm/i915/i915_irq.c

3033

const u32 identity)

sys/dev/drm/i915/i915_irq.c

3070

const u32 ident = gen11_gt_engine_identity(i915,

sys/dev/drm/i915/i915_irq.c

3082

const u32 master_ctl)

sys/dev/drm/i915/i915_irq.c

3096

static u32

sys/dev/drm/i915/i915_irq.c

3097

gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)

sys/dev/drm/i915/i915_irq.c

3100

u32 iir;

sys/dev/drm/i915/i915_irq.c

3113

gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)

sys/dev/drm/i915/i915_irq.c

3123

u32 master_ctl;

sys/dev/drm/i915/i915_irq.c

3124

u32 gu_misc_iir;

sys/dev/drm/i915/i915_irq.c

3142

const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);

sys/dev/drm/i915/i915_irq.c

3164

u32 engine_mask,

sys/dev/drm/i915/i915_irq.c

3216

u32 eir;

sys/dev/drm/i915/i915_irq.c

3269

u32 engine_mask,

sys/dev/drm/i915/i915_irq.c

3528

u32 pipestat_mask;

sys/dev/drm/i915/i915_irq.c

3529

u32 enable_mask;

sys/dev/drm/i915/i915_irq.c

3730

static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/i915_irq.c

3731

const u32 hpd[HPD_NUM_PINS])

sys/dev/drm/i915/i915_irq.c

3734

u32 enabled_irqs = 0;

sys/dev/drm/i915/i915_irq.c

3745

u32 hotplug;

sys/dev/drm/i915/i915_irq.c

3770

u32 hotplug_irqs, enabled_irqs;

sys/dev/drm/i915/i915_irq.c

3787

u32 hotplug;

sys/dev/drm/i915/i915_irq.c

3804

u32 hotplug_irqs, enabled_irqs;

sys/dev/drm/i915/i915_irq.c

3816

u32 hotplug;

sys/dev/drm/i915/i915_irq.c

3835

u32 hotplug_irqs, enabled_irqs;

sys/dev/drm/i915/i915_irq.c

3836

u32 val;

sys/dev/drm/i915/i915_irq.c

3854

u32 val, hotplug;

sys/dev/drm/i915/i915_irq.c

3879

u32 hotplug_irqs, enabled_irqs;

sys/dev/drm/i915/i915_irq.c

3891

u32 hotplug;

sys/dev/drm/i915/i915_irq.c

3907

u32 hotplug_irqs, enabled_irqs;

sys/dev/drm/i915/i915_irq.c

3932

u32 enabled_irqs)

sys/dev/drm/i915/i915_irq.c

3934

u32 hotplug;

sys/dev/drm/i915/i915_irq.c

3969

u32 hotplug_irqs, enabled_irqs;

sys/dev/drm/i915/i915_irq.c

3982

u32 mask;

sys/dev/drm/i915/i915_irq.c

4007

u32 pm_irqs, gt_irqs;

sys/dev/drm/i915/i915_irq.c

4045

u32 display_mask, extra_mask;

sys/dev/drm/i915/i915_irq.c

414

void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)

sys/dev/drm/i915/i915_irq.c

4176

u32 de_port_masked = GEN8_AUX_CHANNEL_A;

sys/dev/drm/i915/i915_irq.c

4177

u32 de_port_enables;

sys/dev/drm/i915/i915_irq.c

4178

u32 de_misc_masked = GEN8_DE_EDP_PSR;

sys/dev/drm/i915/i915_irq.c

422

static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)

sys/dev/drm/i915/i915_irq.c

4226

u32 de_hpd_masked = 0;

sys/dev/drm/i915/i915_irq.c

4227

u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |

sys/dev/drm/i915/i915_irq.c

4260

const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;

sys/dev/drm/i915/i915_irq.c

427

void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)

sys/dev/drm/i915/i915_irq.c

4288

u32 mask = SDE_GMBUS_ICP;

sys/dev/drm/i915/i915_irq.c

4303

u32 gu_misc_masked = GEN11_GU_MISC_GSE;

sys/dev/drm/i915/i915_irq.c

435

static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)

sys/dev/drm/i915/i915_irq.c

4420

u32 *eir, u32 *eir_stuck)

sys/dev/drm/i915/i915_irq.c

4422

u32 emr;

sys/dev/drm/i915/i915_irq.c

4448

u32 eir, u32 eir_stuck)

sys/dev/drm/i915/i915_irq.c

446

static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)

sys/dev/drm/i915/i915_irq.c

4469

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/drm/i915/i915_irq.c

4521

u32 enable_mask;

sys/dev/drm/i915/i915_irq.c

456

static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)

sys/dev/drm/i915/i915_irq.c

4574

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/drm/i915/i915_irq.c

4575

u32 eir = 0, eir_stuck = 0;

sys/dev/drm/i915/i915_irq.c

4576

u32 hotplug_status = 0;

sys/dev/drm/i915/i915_irq.c

4577

u32 iir;

sys/dev/drm/i915/i915_irq.c

4632

u32 enable_mask;

sys/dev/drm/i915/i915_irq.c

4633

u32 error_mask;

sys/dev/drm/i915/i915_irq.c

4686

u32 hotplug_en;

sys/dev/drm/i915/i915_irq.c

4722

u32 pipe_stats[I915_MAX_PIPES] = {};

sys/dev/drm/i915/i915_irq.c

4723

u32 eir = 0, eir_stuck = 0;

sys/dev/drm/i915/i915_irq.c

4724

u32 hotplug_status = 0;

sys/dev/drm/i915/i915_irq.c

4725

u32 iir;

sys/dev/drm/i915/i915_irq.c

48

static const u32 hpd_ilk[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

52

static const u32 hpd_ivb[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

56

static const u32 hpd_bdw[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

60

static const u32 hpd_ibx[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

663

u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/i915_irq.c

666

u32 status_mask = dev_priv->pipestat_irq_mask[pipe];

sys/dev/drm/i915/i915_irq.c

667

u32 enable_mask = status_mask << 16;

sys/dev/drm/i915/i915_irq.c

68

static const u32 hpd_cpt[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

705

enum i915_pipe pipe, u32 status_mask)

sys/dev/drm/i915/i915_irq.c

708

u32 enable_mask;

sys/dev/drm/i915/i915_irq.c

728

enum i915_pipe pipe, u32 status_mask)

sys/dev/drm/i915/i915_irq.c

731

u32 enable_mask;

sys/dev/drm/i915/i915_irq.c

76

static const u32 hpd_spt[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

822

static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

826

u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;

sys/dev/drm/i915/i915_irq.c

84

static const u32 hpd_mask_i915[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_irq.c

872

static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

887

static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)

sys/dev/drm/i915/i915_irq.c

893

u32 vblank_start = mode->crtc_vblank_start;

sys/dev/drm/i915/i915_irq.c

894

u32 vtotal = mode->crtc_vtotal;

sys/dev/drm/i915/i915_irq.c

895

u32 htotal = mode->crtc_htotal;

sys/dev/drm/i915/i915_irq.c

896

u32 clock = mode->crtc_clock;

sys/dev/drm/i915/i915_irq.c

897

u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;

sys/dev/drm/i915/i915_irq.c

93

static const u32 hpd_status_g4x[HPD_NUM_PINS] = {

sys/dev/drm/i915/i915_perf.c

1076

u32 oastatus1;

sys/dev/drm/i915/i915_perf.c

1386

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

1435

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

1558

u32 n_regs)

sys/dev/drm/i915/i915_perf.c

1560

u32 i;

sys/dev/drm/i915/i915_perf.c

1636

u32 *reg_state,

sys/dev/drm/i915/i915_perf.c

1640

u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;

sys/dev/drm/i915/i915_perf.c

1641

u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;

sys/dev/drm/i915/i915_perf.c

1660

u32 state_offset = ctx_flexeu0 + i * 2;

sys/dev/drm/i915/i915_perf.c

1661

u32 mmio = i915_mmio_reg_offset(flex_regs[i]);

sys/dev/drm/i915/i915_perf.c

1668

u32 value = 0;

sys/dev/drm/i915/i915_perf.c

1671

u32 j;

sys/dev/drm/i915/i915_perf.c

1742

u32 *regs;

sys/dev/drm/i915/i915_perf.c

1847

u32 ctx_id = dev_priv->perf.oa.specific_ctx_id;

sys/dev/drm/i915/i915_perf.c

1849

u32 period_exponent = dev_priv->perf.oa.period_exponent;

sys/dev/drm/i915/i915_perf.c

1850

u32 report_format = dev_priv->perf.oa.oa_buffer.format;

sys/dev/drm/i915/i915_perf.c

1875

u32 report_format = dev_priv->perf.oa.oa_buffer.format;

sys/dev/drm/i915/i915_perf.c

2136

u32 *reg_state)

sys/dev/drm/i915/i915_perf.c

2553

u32 ctx_handle = props->ctx_handle;

sys/dev/drm/i915/i915_perf.c

2671

u32 n_props,

sys/dev/drm/i915/i915_perf.c

2675

u32 i;

sys/dev/drm/i915/i915_perf.c

277

static u32 i915_perf_stream_paranoid = true;

sys/dev/drm/i915/i915_perf.c

2824

u32 known_open_flags;

sys/dev/drm/i915/i915_perf.c

2965

static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

2985

static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

2995

static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

3006

static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

3014

static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

3021

static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

3030

static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/i915_perf.c

3036

static uint32_t mask_reg_value(u32 reg, u32 val)

sys/dev/drm/i915/i915_perf.c

3056

bool (*is_valid)(struct drm_i915_private *dev_priv, u32 addr),

sys/dev/drm/i915/i915_perf.c

3057

u32 __user *regs,

sys/dev/drm/i915/i915_perf.c

3058

u32 n_regs)

sys/dev/drm/i915/i915_perf.c

3062

u32 i;

sys/dev/drm/i915/i915_perf.c

3067

if (!access_ok(VERIFY_READ, regs, n_regs * sizeof(u32) * 2))

sys/dev/drm/i915/i915_perf.c

3080

u32 addr, value;

sys/dev/drm/i915/i915_perf.c

314

static u32 i915_oa_max_sample_rate = 100000;

sys/dev/drm/i915/i915_perf.c

356

u32 sample_flags;

sys/dev/drm/i915/i915_perf.c

417

static u32 gen8_oa_hw_tail_read(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_perf.c

422

static u32 gen7_oa_hw_tail_read(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_perf.c

424

u32 oastatus1 = I915_READ(GEN7_OASTATUS1);

sys/dev/drm/i915/i915_perf.c

458

u32 head, hw_tail, aged_tail, aging_tail;

sys/dev/drm/i915/i915_perf.c

522

u32 gtt_offset = i915_ggtt_offset(vma);

sys/dev/drm/i915/i915_perf.c

605

u32 sample_flags = stream->sample_flags;

sys/dev/drm/i915/i915_perf.c

657

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

658

u32 mask = (OA_BUFFER_SIZE - 1);

sys/dev/drm/i915/i915_perf.c

662

u32 head, tail;

sys/dev/drm/i915/i915_perf.c

663

u32 taken;

sys/dev/drm/i915/i915_perf.c

709

u32 *report32 = (void *)report;

sys/dev/drm/i915/i915_perf.c

710

u32 ctx_id;

sys/dev/drm/i915/i915_perf.c

711

u32 reason;

sys/dev/drm/i915/i915_perf.c

865

u32 oastatus;

sys/dev/drm/i915/i915_perf.c

946

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

947

u32 mask = (OA_BUFFER_SIZE - 1);

sys/dev/drm/i915/i915_perf.c

951

u32 head, tail;

sys/dev/drm/i915/i915_perf.c

952

u32 taken;

sys/dev/drm/i915/i915_perf.c

995

u32 *report32 = (void *)report;

sys/dev/drm/i915/i915_pmu.c

160

add_sample(struct i915_pmu_sample *sample, u32 val)

sys/dev/drm/i915/i915_pmu.c

182

u32 current_seqno = intel_engine_get_seqno(engine);

sys/dev/drm/i915/i915_pmu.c

183

u32 last_seqno = intel_engine_last_submit(engine);

sys/dev/drm/i915/i915_pmu.c

184

u32 val;

sys/dev/drm/i915/i915_pmu.c

217

add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)

sys/dev/drm/i915/i915_pmu.c

227

u32 val;

sys/dev/drm/i915/i915_pvinfo.h

100

u32 cursor_y_hot;

sys/dev/drm/i915/i915_pvinfo.h

103

u32 lo;

sys/dev/drm/i915/i915_pvinfo.h

104

u32 hi;

sys/dev/drm/i915/i915_pvinfo.h

107

u32 execlist_context_descriptor_lo;

sys/dev/drm/i915/i915_pvinfo.h

108

u32 execlist_context_descriptor_hi;

sys/dev/drm/i915/i915_pvinfo.h

110

u32 rsv7[0x200 - 24]; /* pad to one page */

sys/dev/drm/i915/i915_pvinfo.h

63

u32 vgt_id; /* ID of vGT instance */

sys/dev/drm/i915/i915_pvinfo.h

64

u32 vgt_caps; /* VGT capabilities */

sys/dev/drm/i915/i915_pvinfo.h

65

u32 rsv1[11]; /* pad to offset 0x40 */

sys/dev/drm/i915/i915_pvinfo.h

75

u32 base;

sys/dev/drm/i915/i915_pvinfo.h

76

u32 size;

sys/dev/drm/i915/i915_pvinfo.h

80

u32 base;

sys/dev/drm/i915/i915_pvinfo.h

81

u32 size;

sys/dev/drm/i915/i915_pvinfo.h

84

u32 fence_num;

sys/dev/drm/i915/i915_pvinfo.h

85

u32 rsv2[3];

sys/dev/drm/i915/i915_pvinfo.h

87

u32 rsv3[0x200 - 24]; /* pad to half page */

sys/dev/drm/i915/i915_pvinfo.h

91

u32 rsv4;

sys/dev/drm/i915/i915_pvinfo.h

92

u32 display_ready; /* ready for display owner switch */

sys/dev/drm/i915/i915_pvinfo.h

94

u32 rsv5[4];

sys/dev/drm/i915/i915_pvinfo.h

96

u32 g2v_notify;

sys/dev/drm/i915/i915_pvinfo.h

97

u32 rsv6[5];

sys/dev/drm/i915/i915_pvinfo.h

99

u32 cursor_x_hot;

sys/dev/drm/i915/i915_query.c

100

u32 i;

sys/dev/drm/i915/i915_query.c

18

u32 slice_length, subslice_length, eu_length, total_length;

sys/dev/drm/i915/i915_reg.h

155

#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])

sys/dev/drm/i915/i915_request.c

1022

u32 head;

sys/dev/drm/i915/i915_request.c

1051

u32 *cs;

sys/dev/drm/i915/i915_request.c

1191

u32 seqno, int state, unsigned long timeout_us)

sys/dev/drm/i915/i915_request.c

199

static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)

sys/dev/drm/i915/i915_request.c

248

int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)

sys/dev/drm/i915/i915_request.c

496

static u32 timeline_get_seqno(struct i915_timeline *tl)

sys/dev/drm/i915/i915_request.c

515

u32 seqno;

sys/dev/drm/i915/i915_request.c

872

u32 seqno;

sys/dev/drm/i915/i915_request.h

141

u32 global_seqno;

sys/dev/drm/i915/i915_request.h

144

u32 head;

sys/dev/drm/i915/i915_request.h

147

u32 infix;

sys/dev/drm/i915/i915_request.h

154

u32 postfix;

sys/dev/drm/i915/i915_request.h

157

u32 tail;

sys/dev/drm/i915/i915_request.h

160

u32 wa_tail;

sys/dev/drm/i915/i915_request.h

163

u32 reserved_space;

sys/dev/drm/i915/i915_request.h

253

static u32

sys/dev/drm/i915/i915_request.h

285

u32 seqno);

sys/dev/drm/i915/i915_request.h

287

u32 seqno);

sys/dev/drm/i915/i915_request.h

292

static inline bool i915_seqno_passed(u32 seq1, u32 seq2)

sys/dev/drm/i915/i915_request.h

308

u32 seqno;

sys/dev/drm/i915/i915_request.h

318

__i915_request_completed(const struct i915_request *rq, u32 seqno)

sys/dev/drm/i915/i915_request.h

327

u32 seqno;

sys/dev/drm/i915/i915_request.h

46

u32 seqno;

sys/dev/drm/i915/i915_syncmap.c

102

return (u32 *)(p + 1);

sys/dev/drm/i915/i915_syncmap.c

135

static inline bool seqno_later(u32 a, u32 b)

sys/dev/drm/i915/i915_syncmap.c

154

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

203

p = kmalloc(sizeof(*p) + KSYNCMAP * sizeof(u32), M_DRM, GFP_KERNEL);

sys/dev/drm/i915/i915_syncmap.c

214

static inline void __sync_set_seqno(struct i915_syncmap *p, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

230

static noinline int __sync_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

353

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/drm/i915/i915_syncmap.c

99

static inline u32 *__sync_seqno(struct i915_syncmap *p)

sys/dev/drm/i915/i915_syncmap.h

34

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/drm/i915/i915_syncmap.h

35

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/drm/i915/i915_sysfs.c

100

u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);

sys/dev/drm/i915/i915_sysfs.c

202

u32 **remap_info;

sys/dev/drm/i915/i915_sysfs.c

268

u32 freq;

sys/dev/drm/i915/i915_sysfs.c

310

u32 val;

sys/dev/drm/i915/i915_sysfs.c

358

u32 val;

sys/dev/drm/i915/i915_sysfs.c

416

u32 val;

sys/dev/drm/i915/i915_sysfs.c

43

static u32 calc_residency(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/i915_sysfs.c

473

u32 val;

sys/dev/drm/i915/i915_sysfs.c

76

u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);

sys/dev/drm/i915/i915_sysfs.c

84

u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);

sys/dev/drm/i915/i915_sysfs.c

92

u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);

sys/dev/drm/i915/i915_timeline.h

104

u64 context, u32 seqno)

sys/dev/drm/i915/i915_timeline.h

116

u64 context, u32 seqno)

sys/dev/drm/i915/i915_timeline.h

37

u32 seqno;

sys/dev/drm/i915/i915_timeline.h

74

u32 global_sync[I915_NUM_ENGINES];

sys/dev/drm/i915/i915_vma.c

176

if (unlikely(overflows_type(vma->size, u32)))

sys/dev/drm/i915/i915_vma.c

299

u32 flags)

sys/dev/drm/i915/i915_vma.c

301

u32 bind_flags;

sys/dev/drm/i915/i915_vma.c

302

u32 vma_flags;

sys/dev/drm/i915/i915_vma.h

133

u32 exec_handle;

sys/dev/drm/i915/i915_vma.h

202

static inline u32 i915_ggtt_offset(const struct i915_vma *vma)

sys/dev/drm/i915/i915_vma.h

211

static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)

sys/dev/drm/i915/i915_vma.h

274

u32 flags);

sys/dev/drm/i915/i915_vma.h

63

u32 fence_size;

sys/dev/drm/i915/i915_vma.h

64

u32 fence_alignment;

sys/dev/drm/i915/icl_dsi.c

35

u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

sys/dev/drm/i915/icl_dsi.c

36

u32 afe_clk_khz; /* 8X Clock */

sys/dev/drm/i915/icl_dsi.c

37

u32 esc_clk_div_m;

sys/dev/drm/i915/icl_dsi.c

62

u32 tmp;

sys/dev/drm/i915/icl_dsi.c

82

u32 tmp;

sys/dev/drm/i915/icl_dsi.c

83

u32 lane_mask;

sys/dev/drm/i915/intel_audio.c

130

u32 config;

sys/dev/drm/i915/intel_audio.c

187

static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)

sys/dev/drm/i915/intel_audio.c

228

i915_reg_t reg_eldv, u32 bits_eldv,

sys/dev/drm/i915/intel_audio.c

229

i915_reg_t reg_elda, u32 bits_elda,

sys/dev/drm/i915/intel_audio.c

234

u32 tmp;

sys/dev/drm/i915/intel_audio.c

248

if (I915_READ(reg_edid) != *((const u32 *)eld + i))

sys/dev/drm/i915/intel_audio.c

259

u32 eldv, tmp;

sys/dev/drm/i915/intel_audio.c

282

u32 eldv;

sys/dev/drm/i915/intel_audio.c

283

u32 tmp;

sys/dev/drm/i915/intel_audio.c

308

I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));

sys/dev/drm/i915/intel_audio.c

326

u32 tmp;

sys/dev/drm/i915/intel_audio.c

373

u32 tmp;

sys/dev/drm/i915/intel_audio.c

423

u32 tmp;

sys/dev/drm/i915/intel_audio.c

457

u32 tmp;

sys/dev/drm/i915/intel_audio.c

486

I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));

sys/dev/drm/i915/intel_audio.c

507

u32 tmp, eldv;

sys/dev/drm/i915/intel_audio.c

555

u32 tmp, eldv;

sys/dev/drm/i915/intel_audio.c

605

I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));

sys/dev/drm/i915/intel_audio.c

760

u32 tmp;

sys/dev/drm/i915/intel_bios.c

1102

u32 seq_size;

sys/dev/drm/i915/intel_bios.c

1692

if (ioread32(bios + i) != *((const u32 *) "$VBT"))

sys/dev/drm/i915/intel_bios.c

62

static u32 _get_blocksize(const u8 *block_base)

sys/dev/drm/i915/intel_bios.c

66

return *((const u32 *)(block_base + 4));

sys/dev/drm/i915/intel_bios.c

72

static u32 get_blocksize(const void *block_data)

sys/dev/drm/i915/intel_bios.c

83

u32 total, current_size;

sys/dev/drm/i915/intel_bios.c

862

u16 panel_id, u32 *seq_size)

sys/dev/drm/i915/intel_bios.c

864

u32 total = get_blocksize(sequence);

sys/dev/drm/i915/intel_bios.c

867

u32 current_size;

sys/dev/drm/i915/intel_bios.c

884

current_size = *((const u32 *)(data + index + 1));

sys/dev/drm/i915/intel_bios.c

950

u32 size_of_sequence;

sys/dev/drm/i915/intel_bios.c

969

size_of_sequence = *((const u32 *)(data + index));

sys/dev/drm/i915/intel_bios.h

100

u32 video_transfer_mode:2;

sys/dev/drm/i915/intel_bios.h

102

u32 cabc_supported:1;

sys/dev/drm/i915/intel_bios.h

105

u32 pwm_blc:1;

sys/dev/drm/i915/intel_bios.h

112

u32 videomode_color_format:4;

sys/dev/drm/i915/intel_bios.h

119

u32 rotation:2;

sys/dev/drm/i915/intel_bios.h

120

u32 bta_enabled:1;

sys/dev/drm/i915/intel_bios.h

121

u32 rsvd2:15;

sys/dev/drm/i915/intel_bios.h

141

u32 target_burst_mode_freq;

sys/dev/drm/i915/intel_bios.h

142

u32 dsi_ddr_clk;

sys/dev/drm/i915/intel_bios.h

143

u32 bridge_ref_clk;

sys/dev/drm/i915/intel_bios.h

158

u32 hs_tx_timeout;

sys/dev/drm/i915/intel_bios.h

159

u32 lp_rx_timeout;

sys/dev/drm/i915/intel_bios.h

160

u32 turn_around_timeout;

sys/dev/drm/i915/intel_bios.h

161

u32 device_reset_timer;

sys/dev/drm/i915/intel_bios.h

162

u32 master_init_timer;

sys/dev/drm/i915/intel_bios.h

163

u32 dbi_bw_timer;

sys/dev/drm/i915/intel_bios.h

164

u32 lp_byte_clk_val;

sys/dev/drm/i915/intel_bios.h

167

u32 prepare_cnt:6;

sys/dev/drm/i915/intel_bios.h

168

u32 rsvd8:2;

sys/dev/drm/i915/intel_bios.h

169

u32 clk_zero_cnt:8;

sys/dev/drm/i915/intel_bios.h

170

u32 trail_cnt:5;

sys/dev/drm/i915/intel_bios.h

171

u32 rsvd9:3;

sys/dev/drm/i915/intel_bios.h

172

u32 exit_zero_cnt:6;

sys/dev/drm/i915/intel_bios.h

173

u32 rsvd10:2;

sys/dev/drm/i915/intel_bios.h

175

u32 clk_lane_switch_cnt;

sys/dev/drm/i915/intel_bios.h

176

u32 hl_switch_cnt;

sys/dev/drm/i915/intel_bios.h

178

u32 rsvd11[6];

sys/dev/drm/i915/intel_bios.h

90

u32 enable_dithering:1;

sys/dev/drm/i915/intel_bios.h

91

u32 rsvd1:1;

sys/dev/drm/i915/intel_bios.h

92

u32 is_bridge:1;

sys/dev/drm/i915/intel_bios.h

94

u32 panel_arch_type:2;

sys/dev/drm/i915/intel_bios.h

95

u32 is_cmd_mode:1;

sys/dev/drm/i915/intel_breadcrumbs.c

397

u32 seqno;

sys/dev/drm/i915/intel_breadcrumbs.c

563

u32 seqno = intel_engine_get_seqno(engine);

sys/dev/drm/i915/intel_breadcrumbs.c

628

u32 seqno;

sys/dev/drm/i915/intel_breadcrumbs.c

647

u32 this = rq->signaling.wait.seqno;

sys/dev/drm/i915/intel_breadcrumbs.c

719

const u32 seqno)

sys/dev/drm/i915/intel_breadcrumbs.c

748

u32 seqno;

sys/dev/drm/i915/intel_cdclk.c

1258

u32 val;

sys/dev/drm/i915/intel_cdclk.c

1277

u32 divider;

sys/dev/drm/i915/intel_cdclk.c

1335

u32 val;

sys/dev/drm/i915/intel_cdclk.c

1360

u32 val, divider;

sys/dev/drm/i915/intel_cdclk.c

1445

u32 cdctl, expected;

sys/dev/drm/i915/intel_cdclk.c

1573

u32 val;

sys/dev/drm/i915/intel_cdclk.c

1595

u32 divider;

sys/dev/drm/i915/intel_cdclk.c

1632

u32 val;

sys/dev/drm/i915/intel_cdclk.c

1648

u32 val;

sys/dev/drm/i915/intel_cdclk.c

1668

u32 val, divider;

sys/dev/drm/i915/intel_cdclk.c

1752

u32 cdctl, expected;

sys/dev/drm/i915/intel_cdclk.c

1912

u32 val;

sys/dev/drm/i915/intel_cdclk.c

1972

u32 val;

sys/dev/drm/i915/intel_cdclk.c

2569

u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

sys/dev/drm/i915/intel_cdclk.c

2650

u32 rawclk;

sys/dev/drm/i915/intel_cdclk.c

2674

u32 rawclk;

sys/dev/drm/i915/intel_cdclk.c

463

u32 val;

sys/dev/drm/i915/intel_cdclk.c

522

u32 val, cmd = cdclk_state->voltage_level;

sys/dev/drm/i915/intel_cdclk.c

559

u32 divider;

sys/dev/drm/i915/intel_cdclk.c

603

u32 val, cmd = cdclk_state->voltage_level;

sys/dev/drm/i915/intel_cdclk.c

818

u32 val;

sys/dev/drm/i915/intel_cdclk.c

858

u32 cdctl;

sys/dev/drm/i915/intel_cdclk.c

935

u32 val;

sys/dev/drm/i915/intel_cdclk.c

992

u32 freq_select, cdclk_ctl;

sys/dev/drm/i915/intel_color.c

421

static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)

sys/dev/drm/i915/intel_color.c

95

u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;

sys/dev/drm/i915/intel_color.c

96

u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,

sys/dev/drm/i915/intel_crt.c

104

u32 tmp, flags = 0;

sys/dev/drm/i915/intel_crt.c

1045

u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |

sys/dev/drm/i915/intel_crt.c

157

u32 adpa;

sys/dev/drm/i915/intel_crt.c

414

u32 adpa;

sys/dev/drm/i915/intel_crt.c

420

u32 save_adpa;

sys/dev/drm/i915/intel_crt.c

462

u32 adpa;

sys/dev/drm/i915/intel_crt.c

464

u32 save_adpa;

sys/dev/drm/i915/intel_crt.c

514

u32 stat;

sys/dev/drm/i915/intel_crt.c

69

u32 val;

sys/dev/drm/i915/intel_crt.c

890

u32 adpa;

sys/dev/drm/i915/intel_crt.c

934

u32 adpa;

sys/dev/drm/i915/intel_csr.c

246

u32 *payload = dev_priv->csr.dmc_payload;

sys/dev/drm/i915/intel_ddi.c

1003

u32 iboost_bit = 0;

sys/dev/drm/i915/intel_ddi.c

1113

u32 temp, i, rx_ctl_val, ddi_pll_sel;

sys/dev/drm/i915/intel_ddi.c

1277

u32 wrpll;

sys/dev/drm/i915/intel_ddi.c

1433

u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

sys/dev/drm/i915/intel_ddi.c

1455

u32 mg_pll_div0, mg_clktop_hsclkctl;

sys/dev/drm/i915/intel_ddi.c

1456

u32 m1, m2_int, m2_frac, div1, div2, refclk;

sys/dev/drm/i915/intel_ddi.c

1663

u32 val, pll;

sys/dev/drm/i915/intel_ddi.c

1757

u32 temp;

sys/dev/drm/i915/intel_ddi.c

2008

u32 tmp;

sys/dev/drm/i915/intel_ddi.c

2149

u32 tmp;

sys/dev/drm/i915/intel_ddi.c

2296

u32 val;

sys/dev/drm/i915/intel_ddi.c

2359

u32 val;

sys/dev/drm/i915/intel_ddi.c

2421

u32 level, enum port port, int type)

sys/dev/drm/i915/intel_ddi.c

2424

u32 n_entries, val;

sys/dev/drm/i915/intel_ddi.c

2479

u32 level,

sys/dev/drm/i915/intel_ddi.c

2486

u32 val;

sys/dev/drm/i915/intel_ddi.c

2550

u32 level)

sys/dev/drm/i915/intel_ddi.c

2555

u32 n_entries, val;

sys/dev/drm/i915/intel_ddi.c

2669

u32 level,

sys/dev/drm/i915/intel_ddi.c

2705

u32 bxt_signal_levels(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_ddi.c

3007

u32 val;

sys/dev/drm/i915/intel_ddi.c

3188

u32 val;

sys/dev/drm/i915/intel_ddi.c

33

u32 trans1; /* balance leg enable, de-emph level */

sys/dev/drm/i915/intel_ddi.c

3369

u32 temp, flags = 0;

sys/dev/drm/i915/intel_ddi.c

34

u32 trans2; /* vref sel, vswing */

sys/dev/drm/i915/intel_ddi.c

497

u32 dw2_swing_select;

sys/dev/drm/i915/intel_ddi.c

498

u32 dw2_swing_scalar;

sys/dev/drm/i915/intel_ddi.c

499

u32 dw4_scaling;

sys/dev/drm/i915/intel_ddi.c

596

u32 cri_txdeemph_override_5_0;

sys/dev/drm/i915/intel_ddi.c

597

u32 cri_txdeemph_override_11_6;

sys/dev/drm/i915/intel_ddi.c

598

u32 cri_txdeemph_override_17_12;

sys/dev/drm/i915/intel_ddi.c

809

u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

sys/dev/drm/i915/intel_ddi.c

830

u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

sys/dev/drm/i915/intel_ddi.c

851

u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

sys/dev/drm/i915/intel_ddi.c

877

u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;

sys/dev/drm/i915/intel_ddi.c

966

u32 iboost_bit = 0;

sys/dev/drm/i915/intel_device_info.c

165

u32 ss_en, ss_en_mask;

sys/dev/drm/i915/intel_device_info.c

203

const u32 fuse2 = I915_READ(GEN8_FUSE2);

sys/dev/drm/i915/intel_device_info.c

206

u32 subslice_mask, eu_en;

sys/dev/drm/i915/intel_device_info.c

280

u32 fuse;

sys/dev/drm/i915/intel_device_info.c

335

u32 fuse2, eu_disable, subslice_mask;

sys/dev/drm/i915/intel_device_info.c

438

u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */

sys/dev/drm/i915/intel_device_info.c

475

u32 n_disabled;

sys/dev/drm/i915/intel_device_info.c

520

u32 fuse1;

sys/dev/drm/i915/intel_device_info.c

582

static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_device_info.c

584

u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);

sys/dev/drm/i915/intel_device_info.c

585

u32 base_freq, frac_freq;

sys/dev/drm/i915/intel_device_info.c

599

static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_device_info.c

600

u32 rpm_config_reg)

sys/dev/drm/i915/intel_device_info.c

602

u32 f19_2_mhz = 19200;

sys/dev/drm/i915/intel_device_info.c

603

u32 f24_mhz = 24000;

sys/dev/drm/i915/intel_device_info.c

604

u32 crystal_clock = (rpm_config_reg &

sys/dev/drm/i915/intel_device_info.c

619

static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_device_info.c

620

u32 rpm_config_reg)

sys/dev/drm/i915/intel_device_info.c

622

u32 f19_2_mhz = 19200;

sys/dev/drm/i915/intel_device_info.c

623

u32 f24_mhz = 24000;

sys/dev/drm/i915/intel_device_info.c

624

u32 f25_mhz = 25000;

sys/dev/drm/i915/intel_device_info.c

625

u32 f38_4_mhz = 38400;

sys/dev/drm/i915/intel_device_info.c

626

u32 crystal_clock = (rpm_config_reg &

sys/dev/drm/i915/intel_device_info.c

645

static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_device_info.c

647

u32 f12_5_mhz = 12500;

sys/dev/drm/i915/intel_device_info.c

648

u32 f19_2_mhz = 19200;

sys/dev/drm/i915/intel_device_info.c

649

u32 f24_mhz = 24000;

sys/dev/drm/i915/intel_device_info.c

668

u32 ctc_reg = I915_READ(CTC_MODE);

sys/dev/drm/i915/intel_device_info.c

669

u32 freq = 0;

sys/dev/drm/i915/intel_device_info.c

686

u32 ctc_reg = I915_READ(CTC_MODE);

sys/dev/drm/i915/intel_device_info.c

687

u32 freq = 0;

sys/dev/drm/i915/intel_device_info.c

697

u32 rpm_config_reg = I915_READ(RPM_CONFIG0);

sys/dev/drm/i915/intel_device_info.c

785

u32 fuse_strap = I915_READ(FUSE_STRAP);

sys/dev/drm/i915/intel_device_info.c

786

u32 sfuse_strap = I915_READ(SFUSE_STRAP);

sys/dev/drm/i915/intel_device_info.c

808

u32 dfsm = I915_READ(SKL_DFSM);

sys/dev/drm/i915/intel_device_info.c

876

u32 media_fuse;

sys/dev/drm/i915/intel_device_info.h

155

u32 platform_mask;

sys/dev/drm/i915/intel_device_info.h

159

u32 display_mmio_offset;

sys/dev/drm/i915/intel_device_info.h

179

u32 cs_timestamp_frequency_khz;

sys/dev/drm/i915/intel_display.c

10008

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_display.c

10014

static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_display.c

10020

u32 cntl = 0;

sys/dev/drm/i915/intel_display.c

10155

u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;

sys/dev/drm/i915/intel_display.c

10222

u32 val;

sys/dev/drm/i915/intel_display.c

10486

u32 dpll = pipe_config->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

1049

u32 line1, line2;

sys/dev/drm/i915/intel_display.c

1050

u32 line_mask;

sys/dev/drm/i915/intel_display.c

10505

u32 dpll = pipe_config->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

10506

u32 fp;

sys/dev/drm/i915/intel_display.c

10553

u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);

sys/dev/drm/i915/intel_display.c

1109

u32 val;

sys/dev/drm/i915/intel_display.c

1122

u32 val;

sys/dev/drm/i915/intel_display.c

1144

u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

sys/dev/drm/i915/intel_display.c

1147

u32 val = I915_READ(FDI_TX_CTL(pipe));

sys/dev/drm/i915/intel_display.c

1160

u32 val;

sys/dev/drm/i915/intel_display.c

1175

u32 val;

sys/dev/drm/i915/intel_display.c

1192

u32 val;

sys/dev/drm/i915/intel_display.c

1205

u32 val;

sys/dev/drm/i915/intel_display.c

1213

u32 port_sel;

sys/dev/drm/i915/intel_display.c

1240

u32 port_sel;

sys/dev/drm/i915/intel_display.c

12594

u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)

sys/dev/drm/i915/intel_display.c

12599

return (u32)drm_crtc_accurate_vblank_count(&crtc->base);

sys/dev/drm/i915/intel_display.c

1273

u32 val = I915_READ(PIPECONF(cpu_transcoder));

sys/dev/drm/i915/intel_display.c

1319

u32 val;

sys/dev/drm/i915/intel_display.c

13368

u32 pixel_format)

sys/dev/drm/i915/intel_display.c

13486

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_display.c

13509

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_display.c

13534

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_display.c

13584

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_display.c

14260

u32 val = I915_READ(PP_CONTROL(pps_idx));

sys/dev/drm/i915/intel_display.c

1432

u32 tmp;

sys/dev/drm/i915/intel_display.c

14527

u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_display.c

14551

u32 pitch_limit;

sys/dev/drm/i915/intel_display.c

14720

u32 stride_alignment;

sys/dev/drm/i915/intel_display.c

1513

u32 dpll = crtc_state->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

15263

u32 fdi_pll_clk =

sys/dev/drm/i915/intel_display.c

15489

u32 dpll, fp;

sys/dev/drm/i915/intel_display.c

1596

u32 val;

sys/dev/drm/i915/intel_display.c

1613

u32 val;

sys/dev/drm/i915/intel_display.c

16264

u32 power_well_driver;

sys/dev/drm/i915/intel_display.c

16269

u32 control;

sys/dev/drm/i915/intel_display.c

16270

u32 position;

sys/dev/drm/i915/intel_display.c

16271

u32 base;

sys/dev/drm/i915/intel_display.c

16272

u32 size;

sys/dev/drm/i915/intel_display.c

16277

u32 source;

sys/dev/drm/i915/intel_display.c

16278

u32 stat;

sys/dev/drm/i915/intel_display.c

16282

u32 control;

sys/dev/drm/i915/intel_display.c

16283

u32 stride;

sys/dev/drm/i915/intel_display.c

16284

u32 size;

sys/dev/drm/i915/intel_display.c

16285

u32 pos;

sys/dev/drm/i915/intel_display.c

16286

u32 addr;

sys/dev/drm/i915/intel_display.c

16287

u32 surface;

sys/dev/drm/i915/intel_display.c

16288

u32 tile_offset;

sys/dev/drm/i915/intel_display.c

16295

u32 conf;

sys/dev/drm/i915/intel_display.c

16297

u32 htotal;

sys/dev/drm/i915/intel_display.c

16298

u32 hblank;

sys/dev/drm/i915/intel_display.c

16299

u32 hsync;

sys/dev/drm/i915/intel_display.c

16300

u32 vtotal;

sys/dev/drm/i915/intel_display.c

16301

u32 vblank;

sys/dev/drm/i915/intel_display.c

16302

u32 vsync;

sys/dev/drm/i915/intel_display.c

1640

u32 port_mask;

sys/dev/drm/i915/intel_display.c

1730

u32 val, pipeconf_val;

sys/dev/drm/i915/intel_display.c

1793

u32 val;

sys/dev/drm/i915/intel_display.c

1827

u32 val;

sys/dev/drm/i915/intel_display.c

1883

u32 val;

sys/dev/drm/i915/intel_display.c

194

const char *name, u32 reg, int ref_freq)

sys/dev/drm/i915/intel_display.c

196

u32 val;

sys/dev/drm/i915/intel_display.c

2092

u32 alignment;

sys/dev/drm/i915/intel_display.c

213

const char *name, u32 reg)

sys/dev/drm/i915/intel_display.c

2197

u32 intel_fb_xy_to_linear(int x, int y,

sys/dev/drm/i915/intel_display.c

2230

static u32 intel_adjust_tile_offset(int *x, int *y,

sys/dev/drm/i915/intel_display.c

2235

u32 old_offset,

sys/dev/drm/i915/intel_display.c

2236

u32 new_offset)

sys/dev/drm/i915/intel_display.c

2257

static u32 intel_adjust_aligned_offset(int *x, int *y,

sys/dev/drm/i915/intel_display.c

2262

u32 old_offset, u32 new_offset)

sys/dev/drm/i915/intel_display.c

2300

static u32 intel_plane_adjust_aligned_offset(int *x, int *y,

sys/dev/drm/i915/intel_display.c

2303

u32 old_offset, u32 new_offset)

sys/dev/drm/i915/intel_display.c

2325

static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_display.c

233

static inline u32 /* units of 100MHz */

sys/dev/drm/i915/intel_display.c

2331

u32 alignment)

sys/dev/drm/i915/intel_display.c

2335

u32 offset, offset_aligned;

sys/dev/drm/i915/intel_display.c

2377

static u32 intel_plane_compute_aligned_offset(int *x, int *y,

sys/dev/drm/i915/intel_display.c

2386

u32 alignment;

sys/dev/drm/i915/intel_display.c

2455

int num_formats, u32 format)

sys/dev/drm/i915/intel_display.c

2494

u32 gtt_offset_rotated = 0;

sys/dev/drm/i915/intel_display.c

2502

u32 offset;

sys/dev/drm/i915/intel_display.c

2710

u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);

sys/dev/drm/i915/intel_display.c

2711

u32 size_aligned = round_up(plane_config->base + plane_config->size,

sys/dev/drm/i915/intel_display.c

2988

int main_x, int main_y, u32 main_offset)

sys/dev/drm/i915/intel_display.c

2995

u32 aux_offset = plane_state->color_plane[1].offset;

sys/dev/drm/i915/intel_display.c

2996

u32 alignment = intel_surf_alignment(fb, 1);

sys/dev/drm/i915/intel_display.c

3035

u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;

sys/dev/drm/i915/intel_display.c

3134

u32 offset;

sys/dev/drm/i915/intel_display.c

3162

u32 offset;

sys/dev/drm/i915/intel_display.c

3227

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_display.c

3252

static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_display.c

3260

u32 dspcntr;

sys/dev/drm/i915/intel_display.c

3322

u32 offset;

sys/dev/drm/i915/intel_display.c

3400

u32 linear_offset;

sys/dev/drm/i915/intel_display.c

3401

u32 dspcntr = plane_state->ctl;

sys/dev/drm/i915/intel_display.c

3406

u32 dspaddr_offset;

sys/dev/drm/i915/intel_display.c

3483

u32 val;

sys/dev/drm/i915/intel_display.c

3509

static u32

sys/dev/drm/i915/intel_display.c

3545

u32 skl_plane_stride(const struct intel_plane_state *plane_state,

sys/dev/drm/i915/intel_display.c

3550

u32 stride = plane_state->color_plane[color_plane].stride;

sys/dev/drm/i915/intel_display.c

3567

static u32 skl_plane_ctl_format(uint32_t pixel_format)

sys/dev/drm/i915/intel_display.c

3606

static u32 skl_plane_ctl_alpha(uint32_t pixel_format)

sys/dev/drm/i915/intel_display.c

3617

static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)

sys/dev/drm/i915/intel_display.c

3628

static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)

sys/dev/drm/i915/intel_display.c

3650

static u32 skl_plane_ctl_rotate(unsigned int rotate)

sys/dev/drm/i915/intel_display.c

3672

static u32 cnl_plane_ctl_flip(unsigned int reflect)

sys/dev/drm/i915/intel_display.c

3687

u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_display.c

3695

u32 plane_ctl;

sys/dev/drm/i915/intel_display.c

3729

u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_display.c

3735

u32 plane_color_ctl = 0;

sys/dev/drm/i915/intel_display.c

3954

u32 temp;

sys/dev/drm/i915/intel_display.c

3997

u32 temp, tries;

sys/dev/drm/i915/intel_display.c

4098

u32 temp, i, retry;

sys/dev/drm/i915/intel_display.c

4231

u32 temp, i, j;

sys/dev/drm/i915/intel_display.c

4349

u32 temp;

sys/dev/drm/i915/intel_display.c

4386

u32 temp;

sys/dev/drm/i915/intel_display.c

4417

u32 temp;

sys/dev/drm/i915/intel_display.c

4490

u32 temp;

sys/dev/drm/i915/intel_display.c

4508

u32 divsel, phaseinc, auxdiv, phasedir = 0;

sys/dev/drm/i915/intel_display.c

4509

u32 temp;

sys/dev/drm/i915/intel_display.c

4520

u32 iclk_virtual_root_freq = 172800 * 1000;

sys/dev/drm/i915/intel_display.c

4521

u32 iclk_pi_range = 64;

sys/dev/drm/i915/intel_display.c

4522

u32 desired_divisor;

sys/dev/drm/i915/intel_display.c

4583

u32 divsel, phaseinc, auxdiv;

sys/dev/drm/i915/intel_display.c

4584

u32 iclk_virtual_root_freq = 172800 * 1000;

sys/dev/drm/i915/intel_display.c

4585

u32 iclk_pi_range = 64;

sys/dev/drm/i915/intel_display.c

4586

u32 desired_divisor;

sys/dev/drm/i915/intel_display.c

4587

u32 temp;

sys/dev/drm/i915/intel_display.c

4730

u32 temp;

sys/dev/drm/i915/intel_display.c

4748

u32 sel;

sys/dev/drm/i915/intel_display.c

4781

u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;

sys/dev/drm/i915/intel_display.c

4828

u32 temp;

sys/dev/drm/i915/intel_display.c

5726

u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));

sys/dev/drm/i915/intel_display.c

5727

u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;

sys/dev/drm/i915/intel_display.c

5762

u32 pipe_chicken;

sys/dev/drm/i915/intel_display.c

5923

u32 temp;

sys/dev/drm/i915/intel_display.c

6878

u32 fp, fp2 = 0;

sys/dev/drm/i915/intel_display.c

6903

u32 reg_val;

sys/dev/drm/i915/intel_display.c

7039

u32 mdiv;

sys/dev/drm/i915/intel_display.c

7040

u32 bestn, bestm1, bestm2, bestp1, bestp2;

sys/dev/drm/i915/intel_display.c

7041

u32 coreclk, reg_val;

sys/dev/drm/i915/intel_display.c

7139

u32 loopfilter, tribuf_calcntr;

sys/dev/drm/i915/intel_display.c

7140

u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;

sys/dev/drm/i915/intel_display.c

7141

u32 dpio_val;

sys/dev/drm/i915/intel_display.c

7297

u32 dpll;

sys/dev/drm/i915/intel_display.c

7359

u32 dpll_md = (crtc_state->pixel_multiplier - 1)

sys/dev/drm/i915/intel_display.c

7371

u32 dpll;

sys/dev/drm/i915/intel_display.c

7518

u32 tmp;

sys/dev/drm/i915/intel_display.c

7829

u32 mdiv;

sys/dev/drm/i915/intel_display.c

7858

u32 val, base, offset;

sys/dev/drm/i915/intel_display.c

7940

u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;

sys/dev/drm/i915/intel_display.c

8084

u32 val, final;

sys/dev/drm/i915/intel_display.c

8119

u32 temp = I915_READ(PCH_DPLL(i));

sys/dev/drm/i915/intel_display.c

8556

u32 val = 0;

sys/dev/drm/i915/intel_display.c

8577

u32 val = 0;

sys/dev/drm/i915/intel_display.c

8617

u32 bps = target_clock * bpp * 21 / 20;

sys/dev/drm/i915/intel_display.c

8633

u32 dpll, fp, fp2;

sys/dev/drm/i915/intel_display.c

8897

u32 val, base, offset, stride_mult, tiling, alpha;

sys/dev/drm/i915/intel_display.c

9381

u32 temp;

sys/dev/drm/i915/intel_display.c

9397

u32 temp;

sys/dev/drm/i915/intel_display.c

9459

u32 temp;

sys/dev/drm/i915/intel_display.c

9513

u32 tmp;

sys/dev/drm/i915/intel_display.c

9567

u32 tmp;

sys/dev/drm/i915/intel_display.c

9691

u32 tmp = I915_READ(PIPEMISC(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9744

static u32 intel_cursor_base(const struct intel_plane_state *plane_state)

sys/dev/drm/i915/intel_display.c

9750

u32 base;

sys/dev/drm/i915/intel_display.c

9768

static u32 intel_cursor_position(const struct intel_plane_state *plane_state)

sys/dev/drm/i915/intel_display.c

9772

u32 pos = 0;

sys/dev/drm/i915/intel_display.c

9805

u32 offset;

sys/dev/drm/i915/intel_display.c

9867

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_display.c

9873

static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_display.c

9940

u32 cntl = 0, base = 0, pos = 0, size = 0;

sys/dev/drm/i915/intel_display.h

272

u32 tu;

sys/dev/drm/i915/intel_display.h

273

u32 gmch_m;

sys/dev/drm/i915/intel_display.h

274

u32 gmch_n;

sys/dev/drm/i915/intel_display.h

275

u32 link_m;

sys/dev/drm/i915/intel_display.h

276

u32 link_n;

sys/dev/drm/i915/intel_dp.c

1068

u32 pp_div;

sys/dev/drm/i915/intel_dp.c

1261

u32 aux_send_ctl_flags)

sys/dev/drm/i915/intel_dp.c

1304

static u32 last_status = -1;

sys/dev/drm/i915/intel_dp.c

1305

const u32 status = I915_READ(ch_ctl);

sys/dev/drm/i915/intel_dp.c

1324

u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,

sys/dev/drm/i915/intel_dp.c

178

u32 lane_info;

sys/dev/drm/i915/intel_dp.c

2186

u32 trans_dp;

sys/dev/drm/i915/intel_dp.c

2228

u32 mask,

sys/dev/drm/i915/intel_dp.c

2229

u32 value)

sys/dev/drm/i915/intel_dp.c

2305

static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_dp.c

2308

u32 control;

sys/dev/drm/i915/intel_dp.c

232

u32 ln0, ln1, lane_info;

sys/dev/drm/i915/intel_dp.c

2330

u32 pp;

sys/dev/drm/i915/intel_dp.c

2402

u32 pp;

sys/dev/drm/i915/intel_dp.c

2486

u32 pp;

sys/dev/drm/i915/intel_dp.c

2544

u32 pp;

sys/dev/drm/i915/intel_dp.c

2592

u32 pp;

sys/dev/drm/i915/intel_dp.c

2635

u32 pp;

sys/dev/drm/i915/intel_dp.c

2840

u32 val = I915_READ(TRANS_DP_CTL(p));

sys/dev/drm/i915/intel_dp.c

2861

u32 val;

sys/dev/drm/i915/intel_dp.c

2904

u32 tmp, flags = 0;

sys/dev/drm/i915/intel_dp.c

2918

u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

sys/dev/drm/i915/intel_dp.c

298

u32 val;

sys/dev/drm/i915/intel_dp.c

331

u32 val;

sys/dev/drm/i915/intel_dp.c

3555

u32 deemph_reg_value, margin_reg_value;

sys/dev/drm/i915/intel_dp.c

399

u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

sys/dev/drm/i915/intel_dp.c

4606

u32 bit;

sys/dev/drm/i915/intel_dp.c

4629

u32 bit;

sys/dev/drm/i915/intel_dp.c

4652

u32 bit;

sys/dev/drm/i915/intel_dp.c

4671

u32 bit;

sys/dev/drm/i915/intel_dp.c

4694

u32 bit;

sys/dev/drm/i915/intel_dp.c

4757

u32 bit;

sys/dev/drm/i915/intel_dp.c

4842

u32 val;

sys/dev/drm/i915/intel_dp.c

4888

u32 val;

sys/dev/drm/i915/intel_dp.c

4921

u32 dpsp;

sys/dev/drm/i915/intel_dp.c

5499

int i, u32 *part)

sys/dev/drm/i915/intel_dp.c

5752

u32 allowed_scalers;

sys/dev/drm/i915/intel_dp.c

5776

u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;

sys/dev/drm/i915/intel_dp.c

5937

u32 pp_on, pp_off, pp_div, port_sel = 0;

sys/dev/drm/i915/intel_dp.c

5960

u32 pp = ironlake_get_pp_control(intel_dp);

sys/dev/drm/i915/intel_dp.c

6117

u32 val;

sys/dev/drm/i915/intel_dp.c

6667

u32 temp = I915_READ(PEG_BAND_GAP_DATA);

sys/dev/drm/i915/intel_dp.c

914

u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &

sys/dev/drm/i915/intel_dp_aux_backlight.c

57

static u32 intel_dp_aux_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_dp_aux_backlight.c

81

intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_dp_link_training.c

241

static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_dp_link_training.c

284

u32 training_pattern;

sys/dev/drm/i915/intel_dpio_phy.c

1046

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

143

u32 pwron_mask;

sys/dev/drm/i915/intel_dpio_phy.c

264

enum port port, u32 margin, u32 scale,

sys/dev/drm/i915/intel_dpio_phy.c

265

u32 enable, u32 deemphasis)

sys/dev/drm/i915/intel_dpio_phy.c

267

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

334

static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)

sys/dev/drm/i915/intel_dpio_phy.c

336

u32 val = I915_READ(BXT_PORT_REF_DW6(phy));

sys/dev/drm/i915/intel_dpio_phy.c

355

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

489

i915_reg_t reg, u32 mask, u32 expected,

sys/dev/drm/i915/intel_dpio_phy.c

494

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

551

u32 grc_code = dev_priv->bxt_phy_grc;

sys/dev/drm/i915/intel_dpio_phy.c

599

u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));

sys/dev/drm/i915/intel_dpio_phy.c

627

u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));

sys/dev/drm/i915/intel_dpio_phy.c

638

u32 deemph_reg_value, u32 margin_reg_value,

sys/dev/drm/i915/intel_dpio_phy.c

646

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

789

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

869

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

955

u32 val;

sys/dev/drm/i915/intel_dpio_phy.c

985

u32 demph_reg_value, u32 preemph_reg_value,

sys/dev/drm/i915/intel_dpio_phy.c

986

u32 uniqtranscale_reg_value, u32 tx3_demph)

sys/dev/drm/i915/intel_dpll_mgr.c

2168

u32 dco_freq, u32 ref_freq,

sys/dev/drm/i915/intel_dpll_mgr.c

2171

u32 dco;

sys/dev/drm/i915/intel_dpll_mgr.c

2234

u32 afe_clock = clock * 5;

sys/dev/drm/i915/intel_dpll_mgr.c

2236

u32 dco_min = 7998000;

sys/dev/drm/i915/intel_dpll_mgr.c

2237

u32 dco_max = 10000000;

sys/dev/drm/i915/intel_dpll_mgr.c

2238

u32 dco_mid = (dco_min + dco_max) / 2;

sys/dev/drm/i915/intel_dpll_mgr.c

2245

u32 dco, best_dco = 0, dco_centrality = 0;

sys/dev/drm/i915/intel_dpll_mgr.c

2246

u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */

sys/dev/drm/i915/intel_dpll_mgr.c

2654

u32 hsdiv;

sys/dev/drm/i915/intel_dpll_mgr.c

3043

u32 val;

sys/dev/drm/i915/intel_dpll_mgr.c

373

u32 val;

sys/dev/drm/i915/intel_drv.h

1179

u32 saved_port_bits;

sys/dev/drm/i915/intel_drv.h

1386

void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);

sys/dev/drm/i915/intel_drv.h

1387

void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);

sys/dev/drm/i915/intel_drv.h

1393

static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,

sys/dev/drm/i915/intel_drv.h

1394

u32 mask)

sys/dev/drm/i915/intel_drv.h

1447

u32 bxt_signal_levels(struct intel_dp *intel_dp);

sys/dev/drm/i915/intel_drv.h

1509

const char *name, u32 reg, int ref_freq);

sys/dev/drm/i915/intel_drv.h

1511

const char *name, u32 reg);

sys/dev/drm/i915/intel_drv.h

1573

u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);

sys/dev/drm/i915/intel_drv.h

1667

u32 pixel_format);

sys/dev/drm/i915/intel_drv.h

1669

static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)

sys/dev/drm/i915/intel_drv.h

1674

u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_drv.h

1676

u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_drv.h

1678

u32 glk_color_ctl(const struct intel_plane_state *plane_state);

sys/dev/drm/i915/intel_drv.h

1679

u32 skl_plane_stride(const struct intel_plane_state *plane_state,

sys/dev/drm/i915/intel_drv.h

1685

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_drv.h

1919

u32 level, u32 max);

sys/dev/drm/i915/intel_drv.h

1974

void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);

sys/dev/drm/i915/intel_drv.h

1975

void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);

sys/dev/drm/i915/intel_drv.h

1978

u32 *out_value);

sys/dev/drm/i915/intel_drv.h

2155

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_drv.h

292

u32 level;

sys/dev/drm/i915/intel_drv.h

293

u32 min;

sys/dev/drm/i915/intel_drv.h

294

u32 max;

sys/dev/drm/i915/intel_drv.h

382

int i, u32 *part);

sys/dev/drm/i915/intel_drv.h

404

u32 acpi_device_id;

sys/dev/drm/i915/intel_drv.h

518

u32 offset;

sys/dev/drm/i915/intel_drv.h

524

u32 stride;

sys/dev/drm/i915/intel_drv.h

529

u32 ctl;

sys/dev/drm/i915/intel_drv.h

532

u32 color_ctl;

sys/dev/drm/i915/intel_drv.h

561

u32 base;

sys/dev/drm/i915/intel_drv.h

830

u32 ctrl, div;

sys/dev/drm/i915/intel_drv.h

866

u32 control;

sys/dev/drm/i915/intel_drv.h

867

u32 pgm_ratios;

sys/dev/drm/i915/intel_drv.h

868

u32 lvds_border_bits;

sys/dev/drm/i915/intel_drv.h

873

u32 pos;

sys/dev/drm/i915/intel_drv.h

874

u32 size;

sys/dev/drm/i915/intel_drv.h

974

u32 base, cntl, size;

sys/dev/drm/i915/intel_drv.h

984

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_dsi.h

100

u32 pclk;

sys/dev/drm/i915/intel_dsi.h

134

enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);

sys/dev/drm/i915/intel_dsi.h

142

u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

sys/dev/drm/i915/intel_dsi.h

152

u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

sys/dev/drm/i915/intel_dsi.h

72

u32 video_mode_format;

sys/dev/drm/i915/intel_dsi.h

85

u32 port_bits;

sys/dev/drm/i915/intel_dsi.h

86

u32 bw_timer;

sys/dev/drm/i915/intel_dsi.h

87

u32 dphy_reg;

sys/dev/drm/i915/intel_dsi.h

88

u32 video_frmt_cfg_bits;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

44

static u32 dcs_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

63

static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_dsi_vbt.c

194

u32 delay = *((const u32 *) data);

sys/dev/drm/i915/intel_dsi_vbt.c

209

u32 tmp;

sys/dev/drm/i915/intel_dsi_vbt.c

509

u32 bpp;

sys/dev/drm/i915/intel_dsi_vbt.c

510

u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;

sys/dev/drm/i915/intel_dsi_vbt.c

511

u32 ui_num, ui_den;

sys/dev/drm/i915/intel_dsi_vbt.c

512

u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;

sys/dev/drm/i915/intel_dsi_vbt.c

513

u32 ths_prepare_ns, tclk_trail_ns;

sys/dev/drm/i915/intel_dsi_vbt.c

514

u32 tclk_prepare_clkzero, ths_prepare_hszero;

sys/dev/drm/i915/intel_dsi_vbt.c

515

u32 lp_to_hs_switch, hs_to_lp_switch;

sys/dev/drm/i915/intel_dsi_vbt.c

516

u32 pclk, computed_ddr;

sys/dev/drm/i915/intel_dsi_vbt.c

517

u32 mul;

sys/dev/drm/i915/intel_dvo.c

127

u32 tmp;

sys/dev/drm/i915/intel_dvo.c

142

u32 tmp;

sys/dev/drm/i915/intel_dvo.c

156

u32 tmp, flags = 0;

sys/dev/drm/i915/intel_dvo.c

182

u32 temp = I915_READ(dvo_reg);

sys/dev/drm/i915/intel_dvo.c

196

u32 temp = I915_READ(dvo_reg);

sys/dev/drm/i915/intel_dvo.c

271

u32 dvo_val;

sys/dev/drm/i915/intel_dvo.c

441

u32 dpll[I915_MAX_PIPES];

sys/dev/drm/i915/intel_engine_cs.c

1253

const size_t rowsize = 8 * sizeof(u32);

sys/dev/drm/i915/intel_engine_cs.c

1270

rowsize, sizeof(u32),

sys/dev/drm/i915/intel_engine_cs.c

1345

const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];

sys/dev/drm/i915/intel_engine_cs.c

189

static u32

sys/dev/drm/i915/intel_engine_cs.c

192

u32 cxt_size;

sys/dev/drm/i915/intel_engine_cs.c

242

static u32 __engine_mmio_base(struct drm_i915_private *i915,

sys/dev/drm/i915/intel_engine_cs.c

426

void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)

sys/dev/drm/i915/intel_engine_cs.c

718

const u32 base = engine->mmio_base;

sys/dev/drm/i915/intel_engine_cs.c

765

u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_engine_cs.c

768

u32 mcr_s_ss_select;

sys/dev/drm/i915/intel_engine_cs.c

769

u32 slice = fls(sseu->slice_mask);

sys/dev/drm/i915/intel_engine_cs.c

770

u32 subslice = fls(sseu->subslice_mask[slice]);

sys/dev/drm/i915/intel_engine_cs.c

845

u32 mmio_base = engine->mmio_base;

sys/dev/drm/i915/intel_engine_cs.c

91

u32 gen : 8;

sys/dev/drm/i915/intel_engine_cs.c

92

u32 base : 24;

sys/dev/drm/i915/intel_fbc.c

122

u32 fbc_ctl;

sys/dev/drm/i915/intel_fbc.c

140

u32 fbc_ctl2;

sys/dev/drm/i915/intel_fbc.c

168

u32 dpfc_ctl;

sys/dev/drm/i915/intel_fbc.c

189

u32 dpfc_ctl;

sys/dev/drm/i915/intel_fbc.c

214

u32 dpfc_ctl;

sys/dev/drm/i915/intel_fbc.c

263

u32 dpfc_ctl;

sys/dev/drm/i915/intel_fbc.c

281

u32 dpfc_ctl;

sys/dev/drm/i915/intel_fbc.c

286

u32 val = I915_READ(CHICKEN_MISC_4);

sys/dev/drm/i915/intel_fbc.c

98

u32 fbc_ctl;

sys/dev/drm/i915/intel_fifo_underrun.c

116

u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

91

u32 enable_mask;

sys/dev/drm/i915/intel_guc.c

242

static u32 guc_ctl_debug_flags(struct intel_guc *guc)

sys/dev/drm/i915/intel_guc.c

244

u32 level = intel_guc_log_get_level(&guc->log);

sys/dev/drm/i915/intel_guc.c

245

u32 flags;

sys/dev/drm/i915/intel_guc.c

246

u32 ads;

sys/dev/drm/i915/intel_guc.c

263

static u32 guc_ctl_feature_flags(struct intel_guc *guc)

sys/dev/drm/i915/intel_guc.c

265

u32 flags = 0;

sys/dev/drm/i915/intel_guc.c

277

static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)

sys/dev/drm/i915/intel_guc.c

279

u32 flags = 0;

sys/dev/drm/i915/intel_guc.c

282

u32 ctxnum, base;

sys/dev/drm/i915/intel_guc.c

294

static u32 guc_ctl_log_params_flags(struct intel_guc *guc)

sys/dev/drm/i915/intel_guc.c

296

u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;

sys/dev/drm/i915/intel_guc.c

297

u32 flags;

sys/dev/drm/i915/intel_guc.c

343

u32 params[GUC_CTL_MAX_DWORDS];

sys/dev/drm/i915/intel_guc.c

381

int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/drm/i915/intel_guc.c

382

u32 *response_buf, u32 response_buf_size)

sys/dev/drm/i915/intel_guc.c

396

int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/drm/i915/intel_guc.c

397

u32 *response_buf, u32 response_buf_size)

sys/dev/drm/i915/intel_guc.c

400

u32 status;

sys/dev/drm/i915/intel_guc.c

41

static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)

sys/dev/drm/i915/intel_guc.c

465

u32 msg, val;

sys/dev/drm/i915/intel_guc.c

489

void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg)

sys/dev/drm/i915/intel_guc.c

504

u32 action[2];

sys/dev/drm/i915/intel_guc.c

528

int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)

sys/dev/drm/i915/intel_guc.c

530

u32 action[] = {

sys/dev/drm/i915/intel_guc.c

544

u32 data[] = {

sys/dev/drm/i915/intel_guc.c

561

u32 data[7];

sys/dev/drm/i915/intel_guc.c

582

u32 data[] = {

sys/dev/drm/i915/intel_guc.c

632

struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)

sys/dev/drm/i915/intel_guc.c

674

u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)

sys/dev/drm/i915/intel_guc.h

105

intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/drm/i915/intel_guc.h

106

u32 *response_buf, u32 response_buf_size)

sys/dev/drm/i915/intel_guc.h

137

static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,

sys/dev/drm/i915/intel_guc.h

140

u32 offset = i915_ggtt_offset(vma);

sys/dev/drm/i915/intel_guc.h

155

int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/drm/i915/intel_guc.h

156

u32 *response_buf, u32 response_buf_size);

sys/dev/drm/i915/intel_guc.h

157

int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/drm/i915/intel_guc.h

158

u32 *response_buf, u32 response_buf_size);

sys/dev/drm/i915/intel_guc.h

164

void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg);

sys/dev/drm/i915/intel_guc.h

166

int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);

sys/dev/drm/i915/intel_guc.h

169

struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);

sys/dev/drm/i915/intel_guc.h

170

u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);

sys/dev/drm/i915/intel_guc.h

178

static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)

sys/dev/drm/i915/intel_guc.h

185

static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)

sys/dev/drm/i915/intel_guc.h

75

u32 db_cacheline;

sys/dev/drm/i915/intel_guc.h

79

u32 base;

sys/dev/drm/i915/intel_guc.h

88

int (*send)(struct intel_guc *guc, const u32 *data, u32 len,

sys/dev/drm/i915/intel_guc.h

89

u32 *response_buf, u32 response_buf_size);

sys/dev/drm/i915/intel_guc.h

99

inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)

sys/dev/drm/i915/intel_guc_ads.c

48

u32 p, i;

sys/dev/drm/i915/intel_guc_ads.c

68

#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))

sys/dev/drm/i915/intel_guc_ads.c

89

const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;

sys/dev/drm/i915/intel_guc_ads.c

90

const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;

sys/dev/drm/i915/intel_guc_ads.c

91

u32 base;

sys/dev/drm/i915/intel_guc_ct.c

105

u32 desc_addr,

sys/dev/drm/i915/intel_guc_ct.c

106

u32 type)

sys/dev/drm/i915/intel_guc_ct.c

108

u32 action[] = {

sys/dev/drm/i915/intel_guc_ct.c

125

u32 owner,

sys/dev/drm/i915/intel_guc_ct.c

126

u32 type)

sys/dev/drm/i915/intel_guc_ct.c

128

u32 action[] = {

sys/dev/drm/i915/intel_guc_ct.c

223

u32 base;

sys/dev/drm/i915/intel_guc_ct.c

293

static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)

sys/dev/drm/i915/intel_guc_ct.c

318

const u32 *action,

sys/dev/drm/i915/intel_guc_ct.c

319

u32 len /* in dwords */,

sys/dev/drm/i915/intel_guc_ct.c

320

u32 fence,

sys/dev/drm/i915/intel_guc_ct.c

324

u32 head = desc->head / 4; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

325

u32 tail = desc->tail / 4; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

326

u32 size = desc->size / 4; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

327

u32 used; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

328

u32 header;

sys/dev/drm/i915/intel_guc_ct.c

329

u32 *cmds = ctb->cmds;

sys/dev/drm/i915/intel_guc_ct.c

35

u32 fence;

sys/dev/drm/i915/intel_guc_ct.c

36

u32 status;

sys/dev/drm/i915/intel_guc_ct.c

37

u32 response_len;

sys/dev/drm/i915/intel_guc_ct.c

38

u32 *response_buf;

sys/dev/drm/i915/intel_guc_ct.c

400

u32 fence,

sys/dev/drm/i915/intel_guc_ct.c

401

u32 *status)

sys/dev/drm/i915/intel_guc_ct.c

43

u32 msg[];

sys/dev/drm/i915/intel_guc_ct.c

447

static int wait_for_ct_request_update(struct ct_request *req, u32 *status)

sys/dev/drm/i915/intel_guc_ct.c

471

const u32 *action,

sys/dev/drm/i915/intel_guc_ct.c

472

u32 len,

sys/dev/drm/i915/intel_guc_ct.c

473

u32 *response_buf,

sys/dev/drm/i915/intel_guc_ct.c

474

u32 response_buf_size,

sys/dev/drm/i915/intel_guc_ct.c

475

u32 *status)

sys/dev/drm/i915/intel_guc_ct.c

481

u32 fence;

sys/dev/drm/i915/intel_guc_ct.c

540

static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,

sys/dev/drm/i915/intel_guc_ct.c

541

u32 *response_buf, u32 response_buf_size)

sys/dev/drm/i915/intel_guc_ct.c

545

u32 status = ~0; /* undefined */

sys/dev/drm/i915/intel_guc_ct.c

564

static inline unsigned int ct_header_get_len(u32 header)

sys/dev/drm/i915/intel_guc_ct.c

569

static inline unsigned int ct_header_get_action(u32 header)

sys/dev/drm/i915/intel_guc_ct.c

574

static inline bool ct_header_is_response(u32 header)

sys/dev/drm/i915/intel_guc_ct.c

579

static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)

sys/dev/drm/i915/intel_guc_ct.c

582

u32 head = desc->head / 4; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

583

u32 tail = desc->tail / 4; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

584

u32 size = desc->size / 4; /* in dwords */

sys/dev/drm/i915/intel_guc_ct.c

585

u32 *cmds = ctb->cmds;

sys/dev/drm/i915/intel_guc_ct.c

612

if (unlikely(len > (u32)available)) {

sys/dev/drm/i915/intel_guc_ct.c

650

static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)

sys/dev/drm/i915/intel_guc_ct.c

652

u32 header = msg[0];

sys/dev/drm/i915/intel_guc_ct.c

653

u32 len = ct_header_get_len(header);

sys/dev/drm/i915/intel_guc_ct.c

654

u32 msglen = len + 1; /* total message length including header */

sys/dev/drm/i915/intel_guc_ct.c

655

u32 fence;

sys/dev/drm/i915/intel_guc_ct.c

656

u32 status;

sys/dev/drm/i915/intel_guc_ct.c

657

u32 datalen;

sys/dev/drm/i915/intel_guc_ct.c

711

u32 action, u32 len, const u32 *payload)

sys/dev/drm/i915/intel_guc_ct.c

72

static inline const char *guc_ct_buffer_type_to_str(u32 type)

sys/dev/drm/i915/intel_guc_ct.c

736

u32 header;

sys/dev/drm/i915/intel_guc_ct.c

737

u32 *payload;

sys/dev/drm/i915/intel_guc_ct.c

790

static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)

sys/dev/drm/i915/intel_guc_ct.c

792

u32 header = msg[0];

sys/dev/drm/i915/intel_guc_ct.c

793

u32 len = ct_header_get_len(header);

sys/dev/drm/i915/intel_guc_ct.c

794

u32 msglen = len + 1; /* total message length including header */

sys/dev/drm/i915/intel_guc_ct.c

819

u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */

sys/dev/drm/i915/intel_guc_ct.c

85

u32 cmds_addr, u32 size, u32 owner)

sys/dev/drm/i915/intel_guc_ct.h

54

u32 *cmds;

sys/dev/drm/i915/intel_guc_ct.h

71

u32 owner;

sys/dev/drm/i915/intel_guc_ct.h

72

u32 next_fence;

sys/dev/drm/i915/intel_guc_fw.c

133

u32 rsa[UOS_RSA_SCRATCH_COUNT];

sys/dev/drm/i915/intel_guc_fw.c

158

u32 status;

sys/dev/drm/i915/intel_guc_fw.c

199

static inline bool guc_ready(struct intel_guc *guc, u32 *status)

sys/dev/drm/i915/intel_guc_fw.c

202

u32 val = I915_READ(GUC_STATUS);

sys/dev/drm/i915/intel_guc_fw.c

203

u32 uk_val = val & GS_UKERNEL_MASK;

sys/dev/drm/i915/intel_guc_fw.c

212

u32 status;

sys/dev/drm/i915/intel_guc_fwif.h

177

u32 module_type;

sys/dev/drm/i915/intel_guc_fwif.h

180

u32 header_size_dw;

sys/dev/drm/i915/intel_guc_fwif.h

181

u32 header_version;

sys/dev/drm/i915/intel_guc_fwif.h

182

u32 module_id;

sys/dev/drm/i915/intel_guc_fwif.h

183

u32 module_vendor;

sys/dev/drm/i915/intel_guc_fwif.h

190

u32 date;

sys/dev/drm/i915/intel_guc_fwif.h

192

u32 size_dw; /* uCode plus header_size_dw */

sys/dev/drm/i915/intel_guc_fwif.h

193

u32 key_size_dw;

sys/dev/drm/i915/intel_guc_fwif.h

194

u32 modulus_size_dw;

sys/dev/drm/i915/intel_guc_fwif.h

195

u32 exponent_size_dw;

sys/dev/drm/i915/intel_guc_fwif.h

202

u32 time;

sys/dev/drm/i915/intel_guc_fwif.h

209

u32 branch_client_version;

sys/dev/drm/i915/intel_guc_fwif.h

210

u32 sw_version;

sys/dev/drm/i915/intel_guc_fwif.h

213

u32 sw_version;

sys/dev/drm/i915/intel_guc_fwif.h

214

u32 reserved;

sys/dev/drm/i915/intel_guc_fwif.h

217

u32 prod_preprod_fw;

sys/dev/drm/i915/intel_guc_fwif.h

218

u32 reserved[12];

sys/dev/drm/i915/intel_guc_fwif.h

219

u32 header_info;

sys/dev/drm/i915/intel_guc_fwif.h

223

u32 db_status;

sys/dev/drm/i915/intel_guc_fwif.h

224

u32 cookie;

sys/dev/drm/i915/intel_guc_fwif.h

225

u32 reserved[14];

sys/dev/drm/i915/intel_guc_fwif.h

230

u32 db_status;

sys/dev/drm/i915/intel_guc_fwif.h

231

u32 cookie;

sys/dev/drm/i915/intel_guc_fwif.h

244

u32 header;

sys/dev/drm/i915/intel_guc_fwif.h

245

u32 context_desc;

sys/dev/drm/i915/intel_guc_fwif.h

246

u32 submit_element_info;

sys/dev/drm/i915/intel_guc_fwif.h

247

u32 fence_id;

sys/dev/drm/i915/intel_guc_fwif.h

251

u32 stage_id;

sys/dev/drm/i915/intel_guc_fwif.h

253

u32 head;

sys/dev/drm/i915/intel_guc_fwif.h

254

u32 tail;

sys/dev/drm/i915/intel_guc_fwif.h

255

u32 error_offset;

sys/dev/drm/i915/intel_guc_fwif.h

257

u32 wq_size_bytes;

sys/dev/drm/i915/intel_guc_fwif.h

258

u32 wq_status;

sys/dev/drm/i915/intel_guc_fwif.h

259

u32 engine_presence;

sys/dev/drm/i915/intel_guc_fwif.h

260

u32 priority;

sys/dev/drm/i915/intel_guc_fwif.h

261

u32 reserved[30];

sys/dev/drm/i915/intel_guc_fwif.h

270

u32 context_desc;

sys/dev/drm/i915/intel_guc_fwif.h

271

u32 context_id;

sys/dev/drm/i915/intel_guc_fwif.h

272

u32 ring_status;

sys/dev/drm/i915/intel_guc_fwif.h

273

u32 ring_lrca;

sys/dev/drm/i915/intel_guc_fwif.h

274

u32 ring_begin;

sys/dev/drm/i915/intel_guc_fwif.h

275

u32 ring_end;

sys/dev/drm/i915/intel_guc_fwif.h

276

u32 ring_next_free_location;

sys/dev/drm/i915/intel_guc_fwif.h

277

u32 ring_current_tail_pointer_value;

sys/dev/drm/i915/intel_guc_fwif.h

294

u32 sched_common_area;

sys/dev/drm/i915/intel_guc_fwif.h

295

u32 stage_id;

sys/dev/drm/i915/intel_guc_fwif.h

296

u32 pas_id;

sys/dev/drm/i915/intel_guc_fwif.h

299

u32 db_trigger_uk;

sys/dev/drm/i915/intel_guc_fwif.h

307

u32 priority;

sys/dev/drm/i915/intel_guc_fwif.h

309

u32 wq_sampled_tail_offset;

sys/dev/drm/i915/intel_guc_fwif.h

310

u32 wq_total_submit_enqueues;

sys/dev/drm/i915/intel_guc_fwif.h

312

u32 process_desc;

sys/dev/drm/i915/intel_guc_fwif.h

313

u32 wq_addr;

sys/dev/drm/i915/intel_guc_fwif.h

314

u32 wq_size;

sys/dev/drm/i915/intel_guc_fwif.h

316

u32 engine_presence;

sys/dev/drm/i915/intel_guc_fwif.h

383

u32 addr; /* gfx address */

sys/dev/drm/i915/intel_guc_fwif.h

385

u32 size; /* size in bytes */

sys/dev/drm/i915/intel_guc_fwif.h

386

u32 head; /* offset updated by GuC*/

sys/dev/drm/i915/intel_guc_fwif.h

387

u32 tail; /* offset updated by owner */

sys/dev/drm/i915/intel_guc_fwif.h

388

u32 is_in_error; /* error indicator */

sys/dev/drm/i915/intel_guc_fwif.h

389

u32 fence; /* fence updated by GuC */

sys/dev/drm/i915/intel_guc_fwif.h

390

u32 status; /* status updated by GuC */

sys/dev/drm/i915/intel_guc_fwif.h

391

u32 owner; /* id of the channel owner */

sys/dev/drm/i915/intel_guc_fwif.h

392

u32 owner_sub_id; /* owner-defined field for extra tracking */

sys/dev/drm/i915/intel_guc_fwif.h

393

u32 reserved[5];

sys/dev/drm/i915/intel_guc_fwif.h

443

u32 execution_quantum;

sys/dev/drm/i915/intel_guc_fwif.h

444

u32 reserved1;

sys/dev/drm/i915/intel_guc_fwif.h

448

u32 preemption_time;

sys/dev/drm/i915/intel_guc_fwif.h

452

u32 fault_time;

sys/dev/drm/i915/intel_guc_fwif.h

454

u32 policy_flags;

sys/dev/drm/i915/intel_guc_fwif.h

455

u32 reserved[2];

sys/dev/drm/i915/intel_guc_fwif.h

464

u32 dpc_promote_time;

sys/dev/drm/i915/intel_guc_fwif.h

467

u32 is_valid;

sys/dev/drm/i915/intel_guc_fwif.h

471

u32 max_num_work_items;

sys/dev/drm/i915/intel_guc_fwif.h

473

u32 reserved[19];

sys/dev/drm/i915/intel_guc_fwif.h

492

u32 offset;

sys/dev/drm/i915/intel_guc_fwif.h

493

u32 value;

sys/dev/drm/i915/intel_guc_fwif.h

494

u32 flags;

sys/dev/drm/i915/intel_guc_fwif.h

497

u32 values_valid;

sys/dev/drm/i915/intel_guc_fwif.h

498

u32 number_of_registers;

sys/dev/drm/i915/intel_guc_fwif.h

503

u32 mmio_start;

sys/dev/drm/i915/intel_guc_fwif.h

504

u32 offsets[GUC_MMIO_WHITE_LIST_MAX];

sys/dev/drm/i915/intel_guc_fwif.h

505

u32 count;

sys/dev/drm/i915/intel_guc_fwif.h

517

u32 reg_state_addr;

sys/dev/drm/i915/intel_guc_fwif.h

518

u32 reg_state_buffer;

sys/dev/drm/i915/intel_guc_fwif.h

519

u32 golden_context_lrca;

sys/dev/drm/i915/intel_guc_fwif.h

520

u32 scheduler_policies;

sys/dev/drm/i915/intel_guc_fwif.h

521

u32 reserved0[3];

sys/dev/drm/i915/intel_guc_fwif.h

522

u32 eng_state_size[GUC_MAX_ENGINES_NUM];

sys/dev/drm/i915/intel_guc_fwif.h

523

u32 reserved2[4];

sys/dev/drm/i915/intel_guc_fwif.h

555

u32 marker[2];

sys/dev/drm/i915/intel_guc_fwif.h

556

u32 read_ptr;

sys/dev/drm/i915/intel_guc_fwif.h

557

u32 write_ptr;

sys/dev/drm/i915/intel_guc_fwif.h

558

u32 size;

sys/dev/drm/i915/intel_guc_fwif.h

559

u32 sampled_write_ptr;

sys/dev/drm/i915/intel_guc_fwif.h

562

u32 flush_to_file:1;

sys/dev/drm/i915/intel_guc_fwif.h

563

u32 buffer_full_cnt:4;

sys/dev/drm/i915/intel_guc_fwif.h

564

u32 reserved:27;

sys/dev/drm/i915/intel_guc_fwif.h

566

u32 flags;

sys/dev/drm/i915/intel_guc_fwif.h

568

u32 version;

sys/dev/drm/i915/intel_guc_fwif.h

572

u32 report_return_status;

sys/dev/drm/i915/intel_guc_fwif.h

573

u32 reserved1[64];

sys/dev/drm/i915/intel_guc_fwif.h

574

u32 affected_count;

sys/dev/drm/i915/intel_guc_fwif.h

575

u32 reserved2[2];

sys/dev/drm/i915/intel_guc_fwif.h

580

u32 addr_of_last_preempted_data_low;

sys/dev/drm/i915/intel_guc_fwif.h

581

u32 addr_of_last_preempted_data_high;

sys/dev/drm/i915/intel_guc_fwif.h

582

u32 addr_of_last_preempted_data_high_tmp;

sys/dev/drm/i915/intel_guc_fwif.h

583

u32 padding;

sys/dev/drm/i915/intel_guc_fwif.h

584

u32 is_mapped_to_proxy;

sys/dev/drm/i915/intel_guc_fwif.h

585

u32 proxy_ctx_id;

sys/dev/drm/i915/intel_guc_fwif.h

586

u32 engine_reset_ctx_id;

sys/dev/drm/i915/intel_guc_fwif.h

587

u32 media_reset_count;

sys/dev/drm/i915/intel_guc_fwif.h

588

u32 reserved1[8];

sys/dev/drm/i915/intel_guc_fwif.h

589

u32 uk_last_ctx_switch_reason;

sys/dev/drm/i915/intel_guc_fwif.h

590

u32 was_reset;

sys/dev/drm/i915/intel_guc_fwif.h

591

u32 lrca_gpu_addr;

sys/dev/drm/i915/intel_guc_fwif.h

593

u32 reserved2[66];

sys/dev/drm/i915/intel_guc_fwif.h

701

(typecheck(u32, (m)) && \

sys/dev/drm/i915/intel_guc_log.c

44

u32 action[] = {

sys/dev/drm/i915/intel_guc_log.c

456

u32 guc_log_size;

sys/dev/drm/i915/intel_guc_log.c

505

int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)

sys/dev/drm/i915/intel_guc_log.c

53

u32 action[] = {

sys/dev/drm/i915/intel_guc_log.c

62

bool default_logging, u32 verbosity)

sys/dev/drm/i915/intel_guc_log.c

64

u32 action[] = {

sys/dev/drm/i915/intel_guc_log.h

66

u32 level;

sys/dev/drm/i915/intel_guc_log.h

74

u32 full_count;

sys/dev/drm/i915/intel_guc_log.h

78

u32 sampled_overflow;

sys/dev/drm/i915/intel_guc_log.h

79

u32 overflow;

sys/dev/drm/i915/intel_guc_log.h

80

u32 flush;

sys/dev/drm/i915/intel_guc_log.h

89

int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);

sys/dev/drm/i915/intel_guc_log.h

98

static inline u32 intel_guc_log_get_level(struct intel_guc_log *log)

sys/dev/drm/i915/intel_guc_submission.c

1056

u32 sr = ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1];

sys/dev/drm/i915/intel_guc_submission.c

147

static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)

sys/dev/drm/i915/intel_guc_submission.c

149

u32 action[] = {

sys/dev/drm/i915/intel_guc_submission.c

157

static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)

sys/dev/drm/i915/intel_guc_submission.c

159

u32 action[] = {

sys/dev/drm/i915/intel_guc_submission.c

35

(sizeof(u32) * GUC_PREEMPT_BREADCRUMB_DWORDS)

sys/dev/drm/i915/intel_guc_submission.c

352

u32 gfx_addr;

sys/dev/drm/i915/intel_guc_submission.c

367

u32 guc_engine_id = engine->guc_id;

sys/dev/drm/i915/intel_guc_submission.c

438

u32 target_engine, u32 context_desc,

sys/dev/drm/i915/intel_guc_submission.c

439

u32 ring_tail, u32 fence_id)

sys/dev/drm/i915/intel_guc_submission.c

443

const u32 wqi_len = wqi_size / sizeof(u32) - 1;

sys/dev/drm/i915/intel_guc_submission.c

446

u32 wq_off;

sys/dev/drm/i915/intel_guc_submission.c

500

u32 cookie;

sys/dev/drm/i915/intel_guc_submission.c

522

u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);

sys/dev/drm/i915/intel_guc_submission.c

523

u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);

sys/dev/drm/i915/intel_guc_submission.c

561

u32 data[7];

sys/dev/drm/i915/intel_guc_submission.c

564

u32 addr = intel_hws_preempt_done_address(engine);

sys/dev/drm/i915/intel_guc_submission.c

565

u32 *cs;

sys/dev/drm/i915/intel_guc_submission.c

881

u32 drbregl;

sys/dev/drm/i915/intel_guc_submission.c

963

u32 engines,

sys/dev/drm/i915/intel_guc_submission.c

964

u32 priority,

sys/dev/drm/i915/intel_guc_submission.h

63

u32 engines;

sys/dev/drm/i915/intel_guc_submission.h

64

u32 priority;

sys/dev/drm/i915/intel_guc_submission.h

65

u32 stage_id;

sys/dev/drm/i915/intel_guc_submission.h

66

u32 proc_desc_offset;

sys/dev/drm/i915/intel_hangcheck.c

130

u32 seqno;

sys/dev/drm/i915/intel_hangcheck.c

165

static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)

sys/dev/drm/i915/intel_hangcheck.c

167

u32 tmp = current_instdone | *old_instdone;

sys/dev/drm/i915/intel_hangcheck.c

233

u32 tmp;

sys/dev/drm/i915/intel_hangcheck.c

28

ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)

sys/dev/drm/i915/intel_hangcheck.c

36

semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,

sys/dev/drm/i915/intel_hangcheck.c

40

u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

sys/dev/drm/i915/intel_hangcheck.c

59

semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)

sys/dev/drm/i915/intel_hangcheck.c

63

u32 cmd, ipehr, head;

sys/dev/drm/i915/intel_hdcp.c

137

static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)

sys/dev/drm/i915/intel_hdcp.c

149

u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)

sys/dev/drm/i915/intel_hdcp.c

188

u32 vprime, sha_text, sha_leftovers, rep_ctl;

sys/dev/drm/i915/intel_hdcp.c

474

u32 reg[2];

sys/dev/drm/i915/intel_hdcp.c

478

u32 reg[2];

sys/dev/drm/i915/intel_hdcp.c

482

u32 reg;

sys/dev/drm/i915/intel_hdcp.c

87

u32 val;

sys/dev/drm/i915/intel_hdmi.c

1063

int i, u32 *part)

sys/dev/drm/i915/intel_hdmi.c

1103

u32 reg;

sys/dev/drm/i915/intel_hdmi.c

113

static u32 hsw_infoframe_enable(unsigned int type)

sys/dev/drm/i915/intel_hdmi.c

1144

u32 hdmi_val;

sys/dev/drm/i915/intel_hdmi.c

1200

u32 tmp, flags = 0;

sys/dev/drm/i915/intel_hdmi.c

1264

u32 temp;

sys/dev/drm/i915/intel_hdmi.c

1286

u32 temp;

sys/dev/drm/i915/intel_hdmi.c

1338

u32 temp;

sys/dev/drm/i915/intel_hdmi.c

1400

u32 temp;

sys/dev/drm/i915/intel_hdmi.c

156

const u32 *data = frame;

sys/dev/drm/i915/intel_hdmi.c

159

u32 val = I915_READ(VIDEO_DIP_CTL);

sys/dev/drm/i915/intel_hdmi.c

194

u32 val = I915_READ(VIDEO_DIP_CTL);

sys/dev/drm/i915/intel_hdmi.c

211

const u32 *data = frame;

sys/dev/drm/i915/intel_hdmi.c

216

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

2404

u32 temp = I915_READ(PEG_BAND_GAP_DATA);

sys/dev/drm/i915/intel_hdmi.c

253

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

271

const u32 *data = frame;

sys/dev/drm/i915/intel_hdmi.c

276

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

314

u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));

sys/dev/drm/i915/intel_hdmi.c

329

const u32 *data = frame;

sys/dev/drm/i915/intel_hdmi.c

334

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

370

u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));

sys/dev/drm/i915/intel_hdmi.c

388

const u32 *data = frame;

sys/dev/drm/i915/intel_hdmi.c

396

u32 val = I915_READ(ctl_reg);

sys/dev/drm/i915/intel_hdmi.c

422

u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));

sys/dev/drm/i915/intel_hdmi.c

54

u32 enabled_bits;

sys/dev/drm/i915/intel_hdmi.c

551

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

552

u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);

sys/dev/drm/i915/intel_hdmi.c

667

u32 val = 0;

sys/dev/drm/i915/intel_hdmi.c

702

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

703

u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);

sys/dev/drm/i915/intel_hdmi.c

754

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

798

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

799

u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);

sys/dev/drm/i915/intel_hdmi.c

83

static u32 g4x_infoframe_index(unsigned int type)

sys/dev/drm/i915/intel_hdmi.c

848

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

98

static u32 g4x_infoframe_enable(unsigned int type)

sys/dev/drm/i915/intel_hotplug.c

285

u32 long_port_mask, short_port_mask;

sys/dev/drm/i915/intel_hotplug.c

287

u32 old_bits = 0;

sys/dev/drm/i915/intel_hotplug.c

341

u32 hpd_event_bits;

sys/dev/drm/i915/intel_hotplug.c

395

u32 pin_mask, u32 long_mask)

sys/dev/drm/i915/intel_hotplug.c

400

u32 long_hpd_pulse_mask = 0;

sys/dev/drm/i915/intel_hotplug.c

401

u32 short_hpd_pulse_mask = 0;

sys/dev/drm/i915/intel_huc.c

117

u32 status;

sys/dev/drm/i915/intel_huc.c

59

u32 status;

sys/dev/drm/i915/intel_huc_fw.c

113

u32 size;

sys/dev/drm/i915/intel_i2c.c

147

u32 val;

sys/dev/drm/i915/intel_i2c.c

161

u32 val;

sys/dev/drm/i915/intel_i2c.c

174

u32 val;

sys/dev/drm/i915/intel_i2c.c

184

static u32 get_reserved(struct intel_gmbus *bus)

sys/dev/drm/i915/intel_i2c.c

187

u32 reserved = 0;

sys/dev/drm/i915/intel_i2c.c

202

u32 reserved = get_reserved(bus);

sys/dev/drm/i915/intel_i2c.c

212

u32 reserved = get_reserved(bus);

sys/dev/drm/i915/intel_i2c.c

222

u32 reserved = get_reserved(bus);

sys/dev/drm/i915/intel_i2c.c

223

u32 clock_bits;

sys/dev/drm/i915/intel_i2c.c

239

u32 reserved = get_reserved(bus);

sys/dev/drm/i915/intel_i2c.c

240

u32 data_bits;

sys/dev/drm/i915/intel_i2c.c

307

static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)

sys/dev/drm/i915/intel_i2c.c

310

u32 gmbus2;

sys/dev/drm/i915/intel_i2c.c

341

u32 irq_enable;

sys/dev/drm/i915/intel_i2c.c

372

u32 gmbus0_reg, u32 gmbus1_index)

sys/dev/drm/i915/intel_i2c.c

399

u32 val, loop = 0;

sys/dev/drm/i915/intel_i2c.c

434

u32 gmbus0_reg, u32 gmbus1_index)

sys/dev/drm/i915/intel_i2c.c

462

u32 gmbus1_index)

sys/dev/drm/i915/intel_i2c.c

465

u32 val, loop;

sys/dev/drm/i915/intel_i2c.c

499

u32 gmbus1_index)

sys/dev/drm/i915/intel_i2c.c

537

u32 gmbus0_reg)

sys/dev/drm/i915/intel_i2c.c

539

u32 gmbus1_index = 0;

sys/dev/drm/i915/intel_i2c.c

540

u32 gmbus5 = 0;

sys/dev/drm/i915/intel_i2c.c

569

u32 gmbus0_source)

sys/dev/drm/i915/intel_i2c.c

762

static u32 gmbus_func(struct i2c_adapter *adapter)

sys/dev/drm/i915/intel_lpe_audio.c

333

u32 audio_enable;

sys/dev/drm/i915/intel_lrc.c

1459

static u32 *

sys/dev/drm/i915/intel_lrc.c

1460

gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)

sys/dev/drm/i915/intel_lrc.c

1500

static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/drm/i915/intel_lrc.c

1536

u32 value;

sys/dev/drm/i915/intel_lrc.c

1539

static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)

sys/dev/drm/i915/intel_lrc.c

1553

static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/drm/i915/intel_lrc.c

1629

static u32 *

sys/dev/drm/i915/intel_lrc.c

1630

gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/drm/i915/intel_lrc.c

165

#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)

sys/dev/drm/i915/intel_lrc.c

1698

typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);

sys/dev/drm/i915/intel_lrc.c

170

static void execlists_init_reg_state(u32 *reg_state,

sys/dev/drm/i915/intel_lrc.c

1934

u32 *regs;

sys/dev/drm/i915/intel_lrc.c

2027

u32 *cs;

sys/dev/drm/i915/intel_lrc.c

2051

u64 offset, u32 len,

sys/dev/drm/i915/intel_lrc.c

2054

u32 *cs;

sys/dev/drm/i915/intel_lrc.c

2126

static int gen8_emit_flush(struct i915_request *request, u32 mode)

sys/dev/drm/i915/intel_lrc.c

2128

u32 cmd, *cs;

sys/dev/drm/i915/intel_lrc.c

2159

u32 mode)

sys/dev/drm/i915/intel_lrc.c

2162

u32 scratch_addr =

sys/dev/drm/i915/intel_lrc.c

2165

u32 *cs, flags = 0;

sys/dev/drm/i915/intel_lrc.c

2233

static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)

sys/dev/drm/i915/intel_lrc.c

2241

static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)

sys/dev/drm/i915/intel_lrc.c

2257

static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)

sys/dev/drm/i915/intel_lrc.c

2456

execlists->csb_status = (u32 __force *)

sys/dev/drm/i915/intel_lrc.c

2459

execlists->csb_write = (u32 __force *)execlists->csb_read;

sys/dev/drm/i915/intel_lrc.c

2523

static u32

sys/dev/drm/i915/intel_lrc.c

2529

u32 rpcs = 0;

sys/dev/drm/i915/intel_lrc.c

2577

u32 mask, val = slices;

sys/dev/drm/i915/intel_lrc.c

2594

u32 val = subslices;

sys/dev/drm/i915/intel_lrc.c

2605

u32 val;

sys/dev/drm/i915/intel_lrc.c

2627

static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_lrc.c

2629

u32 indirect_ctx_offset;

sys/dev/drm/i915/intel_lrc.c

2656

static void execlists_init_reg_state(u32 *regs,

sys/dev/drm/i915/intel_lrc.c

2663

u32 base = engine->mmio_base;

sys/dev/drm/i915/intel_lrc.c

2702

u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);

sys/dev/drm/i915/intel_lrc.c

2714

u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);

sys/dev/drm/i915/intel_lrc.c

2762

u32 *regs;

sys/dev/drm/i915/intel_lrc.c

2907

u32 *regs = ce->lrc_reg_state;

sys/dev/drm/i915/intel_lrc.c

414

execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)

sys/dev/drm/i915/intel_lrc.c

427

u32 *reg_state = ce->lrc_reg_state;

sys/dev/drm/i915/intel_lrc.c

459

static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)

sys/dev/drm/i915/intel_lrc.c

921

const u32 * const buf = execlists->csb_status;

sys/dev/drm/i915/intel_lrc_reg.h

43

u32 *reg_state__ = (reg_state); \

sys/dev/drm/i915/intel_lrc_reg.h

44

const u32 pos__ = (pos); \

sys/dev/drm/i915/intel_lrc_reg.h

50

u32 *reg_state__ = (reg_state); \

sys/dev/drm/i915/intel_lrc_reg.h

57

u32 *reg_state__ = (reg_state); \

sys/dev/drm/i915/intel_lvds.c

126

u32 tmp, flags = 0;

sys/dev/drm/i915/intel_lvds.c

159

u32 val;

sys/dev/drm/i915/intel_lvds.c

213

u32 val;

sys/dev/drm/i915/intel_lvds.c

242

u32 temp;

sys/dev/drm/i915/intel_lvds.c

69

u32 a3_power;

sys/dev/drm/i915/intel_lvds.c

72

u32 init_lvds_val;

sys/dev/drm/i915/intel_lvds.c

871

u32 lvds;

sys/dev/drm/i915/intel_lvds.c

873

u32 allowed_scalers;

sys/dev/drm/i915/intel_lvds.c

90

u32 val;

sys/dev/drm/i915/intel_mocs.c

279

u32 *cs;

sys/dev/drm/i915/intel_mocs.c

29

u32 control_value;

sys/dev/drm/i915/intel_mocs.c

314

static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,

sys/dev/drm/i915/intel_mocs.c

337

u32 *cs;

sys/dev/drm/i915/intel_mocs.c

34

u32 size;

sys/dev/drm/i915/intel_opregion.c

100

u32 parm; /* command parameters */

sys/dev/drm/i915/intel_opregion.c

101

u32 dslp; /* driver sleep time-out */

sys/dev/drm/i915/intel_opregion.c

107

u32 ardy; /* driver readiness */

sys/dev/drm/i915/intel_opregion.c

108

u32 aslc; /* ASLE interrupt command */

sys/dev/drm/i915/intel_opregion.c

109

u32 tche; /* technology enabled indicator */

sys/dev/drm/i915/intel_opregion.c

1092

u32 panel_details;

sys/dev/drm/i915/intel_opregion.c

110

u32 alsi; /* current ALS illuminance reading */

sys/dev/drm/i915/intel_opregion.c

111

u32 bclp; /* backlight brightness to set */

sys/dev/drm/i915/intel_opregion.c

112

u32 pfit; /* panel fitting state */

sys/dev/drm/i915/intel_opregion.c

113

u32 cblv; /* current brightness level */

sys/dev/drm/i915/intel_opregion.c

115

u32 cpfm; /* current panel fitting mode */

sys/dev/drm/i915/intel_opregion.c

116

u32 epfm; /* enabled panel fitting modes */

sys/dev/drm/i915/intel_opregion.c

118

u32 pfmb; /* PWM freq and min brightness */

sys/dev/drm/i915/intel_opregion.c

119

u32 cddv; /* color correction default values */

sys/dev/drm/i915/intel_opregion.c

120

u32 pcft; /* power conservation features */

sys/dev/drm/i915/intel_opregion.c

121

u32 srot; /* supported rotation angles */

sys/dev/drm/i915/intel_opregion.c

122

u32 iuer; /* IUER events */

sys/dev/drm/i915/intel_opregion.c

124

u32 fdsp;

sys/dev/drm/i915/intel_opregion.c

125

u32 stat;

sys/dev/drm/i915/intel_opregion.c

127

u32 rvds; /* Size of raw vbt data */

sys/dev/drm/i915/intel_opregion.c

133

u32 phed; /* Panel Header */

sys/dev/drm/i915/intel_opregion.c

268

u32 function, u32 parm, u32 *parm_out)

sys/dev/drm/i915/intel_opregion.c

272

u32 main_function, sub_function, scic;

sys/dev/drm/i915/intel_opregion.c

274

u32 dslp;

sys/dev/drm/i915/intel_opregion.c

365

u32 parm = 0;

sys/dev/drm/i915/intel_opregion.c

366

u32 type = 0;

sys/dev/drm/i915/intel_opregion.c

367

u32 port;

sys/dev/drm/i915/intel_opregion.c

415

u32 parm;

sys/dev/drm/i915/intel_opregion.c

441

static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp)

sys/dev/drm/i915/intel_opregion.c

483

static u32 asle_set_als_illum(struct drm_i915_private *dev_priv, u32 alsi)

sys/dev/drm/i915/intel_opregion.c

491

static u32 asle_set_pwm_freq(struct drm_i915_private *dev_priv, u32 pfmb)

sys/dev/drm/i915/intel_opregion.c

497

static u32 asle_set_pfit(struct drm_i915_private *dev_priv, u32 pfit)

sys/dev/drm/i915/intel_opregion.c

505

static u32 asle_set_supported_rotation_angles(struct drm_i915_private *dev_priv, u32 srot)

sys/dev/drm/i915/intel_opregion.c

511

static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer)

sys/dev/drm/i915/intel_opregion.c

529

static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer)

sys/dev/drm/i915/intel_opregion.c

539

static u32 asle_set_docking(struct drm_i915_private *dev_priv, u32 iuer)

sys/dev/drm/i915/intel_opregion.c

549

static u32 asle_isct_state(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_opregion.c

562

u32 aslc_stat = 0;

sys/dev/drm/i915/intel_opregion.c

563

u32 aslc_req;

sys/dev/drm/i915/intel_opregion.c

61

u32 size;

sys/dev/drm/i915/intel_opregion.c

62

u32 opregion_ver;

sys/dev/drm/i915/intel_opregion.c

652

static void set_did(struct intel_opregion *opregion, int i, u32 val)

sys/dev/drm/i915/intel_opregion.c

66

u32 mboxes;

sys/dev/drm/i915/intel_opregion.c

666

static u32 acpi_display_type(struct intel_connector *connector)

sys/dev/drm/i915/intel_opregion.c

668

u32 display_type;

sys/dev/drm/i915/intel_opregion.c

67

u32 driver_model;

sys/dev/drm/i915/intel_opregion.c

68

u32 pcon;

sys/dev/drm/i915/intel_opregion.c

727

u32 device_id, type;

sys/dev/drm/i915/intel_opregion.c

75

u32 drdy; /* driver readiness */

sys/dev/drm/i915/intel_opregion.c

76

u32 csts; /* notification status */

sys/dev/drm/i915/intel_opregion.c

77

u32 cevt; /* current event */

sys/dev/drm/i915/intel_opregion.c

79

u32 didl[8]; /* supported display devices ID list */

sys/dev/drm/i915/intel_opregion.c

80

u32 cpdl[8]; /* currently presented display list */

sys/dev/drm/i915/intel_opregion.c

81

u32 cadl[8]; /* currently active display list */

sys/dev/drm/i915/intel_opregion.c

82

u32 nadl[8]; /* next active devices list */

sys/dev/drm/i915/intel_opregion.c

83

u32 aslp; /* ASL sleep time-out */

sys/dev/drm/i915/intel_opregion.c

84

u32 tidx; /* toggle table index */

sys/dev/drm/i915/intel_opregion.c

85

u32 chpd; /* current hotplug enable indicator */

sys/dev/drm/i915/intel_opregion.c

853

u32 tmp;

sys/dev/drm/i915/intel_opregion.c

86

u32 clid; /* current lid state*/

sys/dev/drm/i915/intel_opregion.c

87

u32 cdck; /* current docking state */

sys/dev/drm/i915/intel_opregion.c

88

u32 sxsw; /* Sx state resume */

sys/dev/drm/i915/intel_opregion.c

884

u32 low = tmp & 0x7ff;

sys/dev/drm/i915/intel_opregion.c

885

u32 high = tmp & ~0xfff; /* bit 11 is reserved */

sys/dev/drm/i915/intel_opregion.c

89

u32 evts; /* ASL supported events */

sys/dev/drm/i915/intel_opregion.c

890

u32 req = opregion->swsci_sbcb_sub_functions;

sys/dev/drm/i915/intel_opregion.c

90

u32 cnot; /* current OS notification */

sys/dev/drm/i915/intel_opregion.c

91

u32 nrdy; /* driver status */

sys/dev/drm/i915/intel_opregion.c

92

u32 did2[7]; /* extended supported display devices ID list */

sys/dev/drm/i915/intel_opregion.c

93

u32 cpd2[7]; /* extended attached display devices list */

sys/dev/drm/i915/intel_opregion.c

965

u32 asls, mboxes;

sys/dev/drm/i915/intel_opregion.c

970

u32 vbt_size;

sys/dev/drm/i915/intel_opregion.c

99

u32 scic; /* SWSCI command|status|data */

sys/dev/drm/i915/intel_opregion.h

43

u32 swsci_gbda_sub_functions;

sys/dev/drm/i915/intel_opregion.h

44

u32 swsci_sbcb_sub_functions;

sys/dev/drm/i915/intel_opregion.h

49

u32 vbt_size;

sys/dev/drm/i915/intel_opregion.h

50

u32 *lid_state;

sys/dev/drm/i915/intel_overlay.c

1135

params->dst_y = (((u32)params->dst_y << 12) /

sys/dev/drm/i915/intel_overlay.c

1138

params->dst_height = (((u32)params->dst_height << 12) /

sys/dev/drm/i915/intel_overlay.c

118

u32 OBUF_0Y;

sys/dev/drm/i915/intel_overlay.c

1183

static bool check_gamma_bounds(u32 gamma1, u32 gamma2)

sys/dev/drm/i915/intel_overlay.c

119

u32 OBUF_1Y;

sys/dev/drm/i915/intel_overlay.c

1198

static bool check_gamma5_errata(u32 gamma5)

sys/dev/drm/i915/intel_overlay.c

120

u32 OBUF_0U;

sys/dev/drm/i915/intel_overlay.c

121

u32 OBUF_0V;

sys/dev/drm/i915/intel_overlay.c

122

u32 OBUF_1U;

sys/dev/drm/i915/intel_overlay.c

123

u32 OBUF_1V;

sys/dev/drm/i915/intel_overlay.c

124

u32 OSTRIDE;

sys/dev/drm/i915/intel_overlay.c

125

u32 YRGB_VPH;

sys/dev/drm/i915/intel_overlay.c

126

u32 UV_VPH;

sys/dev/drm/i915/intel_overlay.c

127

u32 HORZ_PH;

sys/dev/drm/i915/intel_overlay.c

128

u32 INIT_PHS;

sys/dev/drm/i915/intel_overlay.c

129

u32 DWINPOS;

sys/dev/drm/i915/intel_overlay.c

130

u32 DWINSZ;

sys/dev/drm/i915/intel_overlay.c

131

u32 SWIDTH;

sys/dev/drm/i915/intel_overlay.c

132

u32 SWIDTHSW;

sys/dev/drm/i915/intel_overlay.c

133

u32 SHEIGHT;

sys/dev/drm/i915/intel_overlay.c

134

u32 YRGBSCALE;

sys/dev/drm/i915/intel_overlay.c

135

u32 UVSCALE;

sys/dev/drm/i915/intel_overlay.c

136

u32 OCLRC0;

sys/dev/drm/i915/intel_overlay.c

137

u32 OCLRC1;

sys/dev/drm/i915/intel_overlay.c

138

u32 DCLRKV;

sys/dev/drm/i915/intel_overlay.c

139

u32 DCLRKM;

sys/dev/drm/i915/intel_overlay.c

140

u32 SCLRKVH;

sys/dev/drm/i915/intel_overlay.c

141

u32 SCLRKVL;

sys/dev/drm/i915/intel_overlay.c

1417

u32 dovsta;

sys/dev/drm/i915/intel_overlay.c

1418

u32 isr;

sys/dev/drm/i915/intel_overlay.c

142

u32 SCLRKEN;

sys/dev/drm/i915/intel_overlay.c

143

u32 OCONFIG;

sys/dev/drm/i915/intel_overlay.c

144

u32 OCMD;

sys/dev/drm/i915/intel_overlay.c

145

u32 RESERVED1; /* 0x6C */

sys/dev/drm/i915/intel_overlay.c

146

u32 OSTART_0Y;

sys/dev/drm/i915/intel_overlay.c

147

u32 OSTART_1Y;

sys/dev/drm/i915/intel_overlay.c

148

u32 OSTART_0U;

sys/dev/drm/i915/intel_overlay.c

149

u32 OSTART_0V;

sys/dev/drm/i915/intel_overlay.c

150

u32 OSTART_1U;

sys/dev/drm/i915/intel_overlay.c

151

u32 OSTART_1V;

sys/dev/drm/i915/intel_overlay.c

152

u32 OTILEOFF_0Y;

sys/dev/drm/i915/intel_overlay.c

153

u32 OTILEOFF_1Y;

sys/dev/drm/i915/intel_overlay.c

154

u32 OTILEOFF_0U;

sys/dev/drm/i915/intel_overlay.c

155

u32 OTILEOFF_0V;

sys/dev/drm/i915/intel_overlay.c

156

u32 OTILEOFF_1U;

sys/dev/drm/i915/intel_overlay.c

157

u32 OTILEOFF_1V;

sys/dev/drm/i915/intel_overlay.c

158

u32 FASTHSCALE; /* 0xA0 */

sys/dev/drm/i915/intel_overlay.c

159

u32 UVSCALEV; /* 0xA4 */

sys/dev/drm/i915/intel_overlay.c

160

u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */

sys/dev/drm/i915/intel_overlay.c

178

u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */

sys/dev/drm/i915/intel_overlay.c

179

u32 color_key:24;

sys/dev/drm/i915/intel_overlay.c

180

u32 color_key_enabled:1;

sys/dev/drm/i915/intel_overlay.c

181

u32 brightness, contrast, saturation;

sys/dev/drm/i915/intel_overlay.c

182

u32 old_xscale, old_yscale;

sys/dev/drm/i915/intel_overlay.c

186

u32 flip_addr;

sys/dev/drm/i915/intel_overlay.c

250

u32 *cs;

sys/dev/drm/i915/intel_overlay.c

306

u32 flip_addr = overlay->flip_addr;

sys/dev/drm/i915/intel_overlay.c

307

u32 tmp, *cs;

sys/dev/drm/i915/intel_overlay.c

385

u32 *cs, flip_addr = overlay->flip_addr;

sys/dev/drm/i915/intel_overlay.c

438

u32 *cs;

sys/dev/drm/i915/intel_overlay.c

492

static int packed_depth_bytes(u32 format)

sys/dev/drm/i915/intel_overlay.c

504

static int packed_width_bytes(u32 format, short width)

sys/dev/drm/i915/intel_overlay.c

514

static int uv_hsubsampling(u32 format)

sys/dev/drm/i915/intel_overlay.c

528

static int uv_vsubsampling(u32 format)

sys/dev/drm/i915/intel_overlay.c

542

static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)

sys/dev/drm/i915/intel_overlay.c

544

u32 sw;

sys/dev/drm/i915/intel_overlay.c

609

u32 xscale, yscale, xscale_UV, yscale_UV;

sys/dev/drm/i915/intel_overlay.c

669

u32 key = overlay->color_key;

sys/dev/drm/i915/intel_overlay.c

670

u32 format = 0;

sys/dev/drm/i915/intel_overlay.c

671

u32 flags = 0;

sys/dev/drm/i915/intel_overlay.c

701

static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)

sys/dev/drm/i915/intel_overlay.c

703

u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;

sys/dev/drm/i915/intel_overlay.c

752

u32 swidth, swidthsw, sheight, ostride;

sys/dev/drm/i915/intel_overlay.c

780

u32 oconfig;

sys/dev/drm/i915/intel_overlay.c

812

u32 tmp_U, tmp_V;

sys/dev/drm/i915/intel_overlay.c

896

u32 pfit_control = I915_READ(PFIT_CONTROL);

sys/dev/drm/i915/intel_overlay.c

897

u32 ratio;

sys/dev/drm/i915/intel_overlay.c

933

u32 tmp;

sys/dev/drm/i915/intel_overlay.c

953

u32 stride_mask;

sys/dev/drm/i915/intel_overlay.c

955

u32 tmp;

sys/dev/drm/i915/intel_panel.c

1008

u32 pwm_ctl, val;

sys/dev/drm/i915/intel_panel.c

1055

u32 pwm_ctl;

sys/dev/drm/i915/intel_panel.c

1127

static u32 intel_panel_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

1131

u32 val = 0;

sys/dev/drm/i915/intel_panel.c

1149

u32 user_level, u32 user_max)

sys/dev/drm/i915/intel_panel.c

1154

u32 hw_level;

sys/dev/drm/i915/intel_panel.c

1210

u32 hw_level;

sys/dev/drm/i915/intel_panel.c

128

u32 scaled_width = adjusted_mode->crtc_hdisplay

sys/dev/drm/i915/intel_panel.c

130

u32 scaled_height = pipe_config->pipe_src_w

sys/dev/drm/i915/intel_panel.c

1303

static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1313

static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1323

static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1326

u32 mul;

sys/dev/drm/i915/intel_panel.c

1341

static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1345

u32 mul, clock;

sys/dev/drm/i915/intel_panel.c

1364

static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1379

static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1397

static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1415

static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)

sys/dev/drm/i915/intel_panel.c

1434

static u32 get_backlight_max_vbt(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

1439

u32 pwm;

sys/dev/drm/i915/intel_panel.c

1467

static u32 get_backlight_min_vbt(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

1496

u32 pch_ctl1, pch_ctl2, val;

sys/dev/drm/i915/intel_panel.c

1533

u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;

sys/dev/drm/i915/intel_panel.c

1565

u32 ctl, val;

sys/dev/drm/i915/intel_panel.c

1604

u32 ctl, ctl2, val;

sys/dev/drm/i915/intel_panel.c

1638

u32 ctl, ctl2, val;

sys/dev/drm/i915/intel_panel.c

1672

u32 pwm_ctl, val;

sys/dev/drm/i915/intel_panel.c

1712

u32 pwm_ctl, val;

sys/dev/drm/i915/intel_panel.c

175

u32 border, sync_pos, blank_width, sync_width;

sys/dev/drm/i915/intel_panel.c

1820

u32 user_level, max_brightness;

sys/dev/drm/i915/intel_panel.c

197

u32 border, sync_pos, blank_width, sync_width;

sys/dev/drm/i915/intel_panel.c

214

static inline u32 panel_fitter_scaling(u32 source, u32 target)

sys/dev/drm/i915/intel_panel.c

223

u32 ratio = source * FACTOR / target;

sys/dev/drm/i915/intel_panel.c

228

u32 *pfit_control)

sys/dev/drm/i915/intel_panel.c

231

u32 scaled_width = adjusted_mode->crtc_hdisplay *

sys/dev/drm/i915/intel_panel.c

233

u32 scaled_height = pipe_config->pipe_src_w *

sys/dev/drm/i915/intel_panel.c

248

u32 *pfit_control, u32 *pfit_pgm_ratios,

sys/dev/drm/i915/intel_panel.c

249

u32 *border)

sys/dev/drm/i915/intel_panel.c

252

u32 scaled_width = adjusted_mode->crtc_hdisplay *

sys/dev/drm/i915/intel_panel.c

254

u32 scaled_height = pipe_config->pipe_src_w *

sys/dev/drm/i915/intel_panel.c

256

u32 bits;

sys/dev/drm/i915/intel_panel.c

309

u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;

sys/dev/drm/i915/intel_panel.c

389

static u32 scale(u32 source_val,

sys/dev/drm/i915/intel_panel.c

390

u32 source_min, u32 source_max,

sys/dev/drm/i915/intel_panel.c

391

u32 target_min, u32 target_max)

sys/dev/drm/i915/intel_panel.c

411

static inline u32 scale_user_to_hw(struct intel_connector *connector,

sys/dev/drm/i915/intel_panel.c

412

u32 user_level, u32 user_max)

sys/dev/drm/i915/intel_panel.c

422

static inline u32 clamp_user_to_hw(struct intel_connector *connector,

sys/dev/drm/i915/intel_panel.c

423

u32 user_level, u32 user_max)

sys/dev/drm/i915/intel_panel.c

426

u32 hw_level;

sys/dev/drm/i915/intel_panel.c

435

static inline u32 scale_hw_to_user(struct intel_connector *connector,

sys/dev/drm/i915/intel_panel.c

436

u32 hw_level, u32 user_max)

sys/dev/drm/i915/intel_panel.c

444

static u32 intel_panel_compute_brightness(struct intel_connector *connector,

sys/dev/drm/i915/intel_panel.c

445

u32 val)

sys/dev/drm/i915/intel_panel.c

463

static u32 lpt_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

470

static u32 pch_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

477

static u32 i9xx_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

481

u32 val;

sys/dev/drm/i915/intel_panel.c

497

static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_panel.c

505

static u32 vlv_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

513

static u32 bxt_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

521

static u32 pwm_get_backlight(struct intel_connector *connector)

sys/dev/drm/i915/intel_panel.c

530

static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

535

u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/drm/i915/intel_panel.c

539

static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

543

u32 tmp;

sys/dev/drm/i915/intel_panel.c

549

static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

554

u32 tmp, mask;

sys/dev/drm/i915/intel_panel.c

577

static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

582

u32 tmp;

sys/dev/drm/i915/intel_panel.c

588

static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

597

static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

606

intel_panel_actually_set_backlight(const struct drm_connector_state *conn_state, u32 level)

sys/dev/drm/i915/intel_panel.c

621

u32 user_level, u32 user_max)

sys/dev/drm/i915/intel_panel.c

626

u32 hw_level;

sys/dev/drm/i915/intel_panel.c

660

u32 tmp;

sys/dev/drm/i915/intel_panel.c

686

u32 tmp;

sys/dev/drm/i915/intel_panel.c

705

u32 tmp;

sys/dev/drm/i915/intel_panel.c

718

u32 tmp;

sys/dev/drm/i915/intel_panel.c

731

u32 tmp, val;

sys/dev/drm/i915/intel_panel.c

751

u32 tmp;

sys/dev/drm/i915/intel_panel.c

807

u32 pch_ctl1, pch_ctl2, schicken;

sys/dev/drm/i915/intel_panel.c

858

u32 cpu_ctl2, pch_ctl1, pch_ctl2;

sys/dev/drm/i915/intel_panel.c

903

u32 ctl, freq;

sys/dev/drm/i915/intel_panel.c

943

u32 ctl, ctl2, freq;

sys/dev/drm/i915/intel_panel.c

978

u32 ctl, ctl2;

sys/dev/drm/i915/intel_pm.c

132

u32 val = I915_READ(CHICKEN_MISC_2);

sys/dev/drm/i915/intel_pm.c

143

u32 tmp;

sys/dev/drm/i915/intel_pm.c

2786

u32 linetime, ips_linetime;

sys/dev/drm/i915/intel_pm.c

310

u32 val;

sys/dev/drm/i915/intel_pm.c

332

u32 val;

sys/dev/drm/i915/intel_pm.c

352

u32 val;

sys/dev/drm/i915/intel_pm.c

3866

u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;

sys/dev/drm/i915/intel_pm.c

3869

u32 i;

sys/dev/drm/i915/intel_pm.c

3940

struct skl_ddb_entry *entry, u32 reg)

sys/dev/drm/i915/intel_pm.c

3961

u32 val, val2 = 0;

sys/dev/drm/i915/intel_pm.c

4188

u32 format;

sys/dev/drm/i915/intel_pm.c

5640

u32 tmp = hw->wm_pipe[pipe];

sys/dev/drm/i915/intel_pm.c

5921

u32 val;

sys/dev/drm/i915/intel_pm.c

6154

u32 val;

sys/dev/drm/i915/intel_pm.c

6219

u32 rgvmodectl;

sys/dev/drm/i915/intel_pm.c

6316

static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6319

u32 limits;

sys/dev/drm/i915/intel_pm.c

6343

u32 threshold_up = 0, threshold_down = 0; /* in % */

sys/dev/drm/i915/intel_pm.c

6344

u32 ei_up = 0, ei_down = 0;

sys/dev/drm/i915/intel_pm.c

6475

static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6478

u32 mask = 0;

sys/dev/drm/i915/intel_pm.c

6563

u32 val = rps->idle_freq;

sys/dev/drm/i915/intel_pm.c

6750

u32 rc_ctl;

sys/dev/drm/i915/intel_pm.c

6840

u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);

sys/dev/drm/i915/intel_pm.c

6845

u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

sys/dev/drm/i915/intel_pm.c

6856

u32 ddcc_status = 0;

sys/dev/drm/i915/intel_pm.c

6922

u32 rc6_mode;

sys/dev/drm/i915/intel_pm.c

7087

u32 rc6vids, rc6_mask;

sys/dev/drm/i915/intel_pm.c

7088

u32 gtfifodbg;

sys/dev/drm/i915/intel_pm.c

7265

u32 val, rp0;

sys/dev/drm/i915/intel_pm.c

7293

u32 val, rpe;

sys/dev/drm/i915/intel_pm.c

7303

u32 val, rp1;

sys/dev/drm/i915/intel_pm.c

7311

static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_pm.c

7313

u32 val, rpn;

sys/dev/drm/i915/intel_pm.c

7324

u32 val, rp1;

sys/dev/drm/i915/intel_pm.c

7335

u32 val, rp0;

sys/dev/drm/i915/intel_pm.c

7341

rp0 = min_t(u32, rp0, 0xea);

sys/dev/drm/i915/intel_pm.c

7348

u32 val, rpe;

sys/dev/drm/i915/intel_pm.c

7360

u32 val;

sys/dev/drm/i915/intel_pm.c

7370

return max_t(u32, val, 0xc0);

sys/dev/drm/i915/intel_pm.c

7395

u32 pcbr;

sys/dev/drm/i915/intel_pm.c

7415

u32 pcbr;

sys/dev/drm/i915/intel_pm.c

7481

u32 val;

sys/dev/drm/i915/intel_pm.c

7527

u32 val;

sys/dev/drm/i915/intel_pm.c

7582

u32 gtfifodbg, rc6_mode, pcbr;

sys/dev/drm/i915/intel_pm.c

7633

u32 val;

sys/dev/drm/i915/intel_pm.c

7677

u32 gtfifodbg;

sys/dev/drm/i915/intel_pm.c

7718

u32 val;

sys/dev/drm/i915/intel_pm.c

7757

static unsigned long intel_pxfreq(u32 vidfreq)

sys/dev/drm/i915/intel_pm.c

7789

u32 count1, count2, count3, m = 0, c = 0;

sys/dev/drm/i915/intel_pm.c

7859

u32 tsfs;

sys/dev/drm/i915/intel_pm.c

7882

static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)

sys/dev/drm/i915/intel_pm.c

7896

u32 count;

sys/dev/drm/i915/intel_pm.c

7941

u32 pxvid, ext_v;

sys/dev/drm/i915/intel_pm.c

8164

u32 lcfuse;

sys/dev/drm/i915/intel_pm.c

8185

u32 pxvidfreq = I915_READ(PXVFREQ(i));

sys/dev/drm/i915/intel_pm.c

8204

u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |

sys/dev/drm/i915/intel_pm.c

8273

u32 params = 0;

sys/dev/drm/i915/intel_pm.c

845

u32 reg;

sys/dev/drm/i915/intel_pm.c

8760

u32 misccpctl;

sys/dev/drm/i915/intel_pm.c

8761

u32 val;

sys/dev/drm/i915/intel_pm.c

8801

u32 val;

sys/dev/drm/i915/intel_pm.c

9247

u32 dstate = I915_READ(D_STATE);

sys/dev/drm/i915/intel_pm.c

9487

int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)

sys/dev/drm/i915/intel_pm.c

9534

u32 mbox, u32 val,

sys/dev/drm/i915/intel_pm.c

9581

static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,

sys/dev/drm/i915/intel_pm.c

9582

u32 request, u32 reply_mask, u32 reply,

sys/dev/drm/i915/intel_pm.c

9583

u32 *status)

sys/dev/drm/i915/intel_pm.c

9585

u32 val = request;

sys/dev/drm/i915/intel_pm.c

9611

int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,

sys/dev/drm/i915/intel_pm.c

9612

u32 reply_mask, u32 reply, int timeout_base_ms)

sys/dev/drm/i915/intel_pm.c

9614

u32 status;

sys/dev/drm/i915/intel_pm.c

9734

u32 lower, upper, tmp;

sys/dev/drm/i915/intel_pm.c

9784

u32 mul, div;

sys/dev/drm/i915/intel_pm.c

9797

i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);

sys/dev/drm/i915/intel_pm.c

9851

u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)

sys/dev/drm/i915/intel_pm.c

9853

u32 cagf;

sys/dev/drm/i915/intel_psr.c

109

static void psr_event_print(u32 val, bool psr2_enabled)

sys/dev/drm/i915/intel_psr.c

146

void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)

sys/dev/drm/i915/intel_psr.c

148

u32 transcoders = BIT(TRANSCODER_EDP);

sys/dev/drm/i915/intel_psr.c

175

u32 val = I915_READ(PSR_EVENT(cpu_transcoder));

sys/dev/drm/i915/intel_psr.c

304

u32 aux_clock_divider, aux_ctl;

sys/dev/drm/i915/intel_psr.c

313

u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |

sys/dev/drm/i915/intel_psr.c

358

u32 max_sleep_time = 0x1f;

sys/dev/drm/i915/intel_psr.c

359

u32 val = EDP_PSR_ENABLE;

sys/dev/drm/i915/intel_psr.c

413

u32 val;

sys/dev/drm/i915/intel_psr.c

569

u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));

sys/dev/drm/i915/intel_psr.c

59

static bool psr_global_enabled(u32 debug)

sys/dev/drm/i915/intel_psr.c

666

u32 psr_status_mask;

sys/dev/drm/i915/intel_psr.c

760

u32 *out_value)

sys/dev/drm/i915/intel_psr.c

788

u32 mask;

sys/dev/drm/i915/intel_psr.c

815

u32 mode)

sys/dev/drm/i915/intel_psr.c

82

void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)

sys/dev/drm/i915/intel_psr.c

84

u32 debug_mask, mask;

sys/dev/drm/i915/intel_psr.c

842

u32 mode = val & I915_PSR_DEBUG_MODE_MASK;

sys/dev/drm/i915/intel_psr.c

930

u32 val;

sys/dev/drm/i915/intel_renderstate.h

30

const u32 *reloc;

sys/dev/drm/i915/intel_renderstate.h

31

const u32 *batch;

sys/dev/drm/i915/intel_renderstate.h

32

const u32 batch_items;

sys/dev/drm/i915/intel_renderstate_gen6.c

28

static const u32 gen6_null_state_relocs[] = {

sys/dev/drm/i915/intel_renderstate_gen6.c

37

static const u32 gen6_null_state_batch[] = {

sys/dev/drm/i915/intel_renderstate_gen7.c

28

static const u32 gen7_null_state_relocs[] = {

sys/dev/drm/i915/intel_renderstate_gen7.c

36

static const u32 gen7_null_state_batch[] = {

sys/dev/drm/i915/intel_renderstate_gen8.c

28

static const u32 gen8_null_state_relocs[] = {

sys/dev/drm/i915/intel_renderstate_gen8.c

36

static const u32 gen8_null_state_batch[] = {

sys/dev/drm/i915/intel_renderstate_gen9.c

28

static const u32 gen9_null_state_relocs[] = {

sys/dev/drm/i915/intel_renderstate_gen9.c

36

static const u32 gen9_null_state_batch[] = {

sys/dev/drm/i915/intel_ringbuffer.c

100

gen4_render_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

102

u32 cmd, *cs;

sys/dev/drm/i915/intel_ringbuffer.c

1045

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

1048

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

1113

void intel_ring_reset(struct intel_ring *ring, u32 tail)

sys/dev/drm/i915/intel_ringbuffer.c

1519

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

1541

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

1557

static inline int mi_set_context(struct i915_request *rq, u32 flags)

sys/dev/drm/i915/intel_ringbuffer.c

1569

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

1672

u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];

sys/dev/drm/i915/intel_ringbuffer.c

1704

u32 hw_flags = 0;

sys/dev/drm/i915/intel_ringbuffer.c

1879

u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)

sys/dev/drm/i915/intel_ringbuffer.c

1883

const unsigned int bytes = num_dwords * sizeof(u32);

sys/dev/drm/i915/intel_ringbuffer.c

1886

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

1963

num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);

sys/dev/drm/i915/intel_ringbuffer.c

2018

static int mi_flush_dw(struct i915_request *rq, u32 flags)

sys/dev/drm/i915/intel_ringbuffer.c

2020

u32 cmd, *cs;

sys/dev/drm/i915/intel_ringbuffer.c

2054

static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)

sys/dev/drm/i915/intel_ringbuffer.c

2059

static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

2066

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

2069

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

2086

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

2089

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

2106

static int gen6_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

2131

u32 wait_mbox;

sys/dev/drm/i915/intel_ringbuffer.c

2155

u32 wait_mbox;

sys/dev/drm/i915/intel_ringbuffer.c

222

u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

223

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

253

gen6_render_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

255

u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

256

u32 *cs, flags = 0;

sys/dev/drm/i915/intel_ringbuffer.c

306

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

322

gen7_render_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

324

u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

325

u32 *cs, flags = 0;

sys/dev/drm/i915/intel_ringbuffer.c

387

u32 addr;

sys/dev/drm/i915/intel_ringbuffer.c

432

u32 mask = ~0u;

sys/dev/drm/i915/intel_ringbuffer.c

602

u32 head;

sys/dev/drm/i915/intel_ringbuffer.c

607

(rq->ring->size - head) / sizeof(u32));

sys/dev/drm/i915/intel_ringbuffer.c

610

memset32(vaddr + head, MI_NOOP, (rq->postfix - head) / sizeof(u32));

sys/dev/drm/i915/intel_ringbuffer.c

70

gen2_render_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

711

static u32 *gen6_signal(struct i915_request *rq, u32 *cs)

sys/dev/drm/i915/intel_ringbuffer.c

73

u32 cmd, *cs;

sys/dev/drm/i915/intel_ringbuffer.c

767

static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/drm/i915/intel_ringbuffer.c

780

static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/drm/i915/intel_ringbuffer.c

788

u32 dw1 = MI_SEMAPHORE_MBOX |

sys/dev/drm/i915/intel_ringbuffer.c

791

u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];

sys/dev/drm/i915/intel_ringbuffer.c

792

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

907

bsd_ring_flush(struct i915_request *rq, u32 mode)

sys/dev/drm/i915/intel_ringbuffer.c

909

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

961

u64 offset, u32 length,

sys/dev/drm/i915/intel_ringbuffer.c

964

u32 *cs;

sys/dev/drm/i915/intel_ringbuffer.c

984

u64 offset, u32 len,

sys/dev/drm/i915/intel_ringbuffer.c

987

u32 *cs, cs_offset = i915_scratch_offset(rq->i915);

sys/dev/drm/i915/intel_ringbuffer.h

1007

intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)

sys/dev/drm/i915/intel_ringbuffer.h

1049

static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)

sys/dev/drm/i915/intel_ringbuffer.h

1051

memset(batch, 0, 6 * sizeof(u32));

sys/dev/drm/i915/intel_ringbuffer.h

1060

static inline u32 *

sys/dev/drm/i915/intel_ringbuffer.h

1061

gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset)

sys/dev/drm/i915/intel_ringbuffer.h

1082

static inline u32 *

sys/dev/drm/i915/intel_ringbuffer.h

1083

gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)

sys/dev/drm/i915/intel_ringbuffer.h

112

u32 instdone;

sys/dev/drm/i915/intel_ringbuffer.h

114

u32 slice_common;

sys/dev/drm/i915/intel_ringbuffer.h

115

u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];

sys/dev/drm/i915/intel_ringbuffer.h

116

u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];

sys/dev/drm/i915/intel_ringbuffer.h

121

u32 seqno;

sys/dev/drm/i915/intel_ringbuffer.h

139

u32 head;

sys/dev/drm/i915/intel_ringbuffer.h

140

u32 tail;

sys/dev/drm/i915/intel_ringbuffer.h

141

u32 emit;

sys/dev/drm/i915/intel_ringbuffer.h

143

u32 space;

sys/dev/drm/i915/intel_ringbuffer.h

144

u32 size;

sys/dev/drm/i915/intel_ringbuffer.h

145

u32 effective_size;

sys/dev/drm/i915/intel_ringbuffer.h

164

u32 offset;

sys/dev/drm/i915/intel_ringbuffer.h

165

u32 size;

sys/dev/drm/i915/intel_ringbuffer.h

230

u32 __iomem *submit_reg;

sys/dev/drm/i915/intel_ringbuffer.h

236

u32 __iomem *ctrl_reg;

sys/dev/drm/i915/intel_ringbuffer.h

265

GEM_DEBUG_DECL(u32 context_id);

sys/dev/drm/i915/intel_ringbuffer.h

309

u32 __iomem *csb_read;

sys/dev/drm/i915/intel_ringbuffer.h

316

u32 *csb_write;

sys/dev/drm/i915/intel_ringbuffer.h

323

u32 *csb_status;

sys/dev/drm/i915/intel_ringbuffer.h

328

u32 preempt_complete_status;

sys/dev/drm/i915/intel_ringbuffer.h

337

u32 csb_write_reset;

sys/dev/drm/i915/intel_ringbuffer.h

34

u32 *page_addr;

sys/dev/drm/i915/intel_ringbuffer.h

35

u32 ggtt_offset;

sys/dev/drm/i915/intel_ringbuffer.h

362

u32 context_size;

sys/dev/drm/i915/intel_ringbuffer.h

363

u32 mmio_base;

sys/dev/drm/i915/intel_ringbuffer.h

418

u32 enable;

sys/dev/drm/i915/intel_ringbuffer.h

445

u32 irq_keep_mask; /* always keep these interrupts */

sys/dev/drm/i915/intel_ringbuffer.h

446

u32 irq_enable_mask; /* bitmask to enable ring interrupt */

sys/dev/drm/i915/intel_ringbuffer.h

470

int (*emit_flush)(struct i915_request *request, u32 mode);

sys/dev/drm/i915/intel_ringbuffer.h

475

u64 offset, u32 length,

sys/dev/drm/i915/intel_ringbuffer.h

479

void (*emit_breadcrumb)(struct i915_request *rq, u32 *cs);

sys/dev/drm/i915/intel_ringbuffer.h

559

u32 wait[GEN6_NUM_SEMAPHORES];

sys/dev/drm/i915/intel_ringbuffer.h

567

u32 *(*signal)(struct i915_request *rq, u32 *cs);

sys/dev/drm/i915/intel_ringbuffer.h

615

u32 (*get_cmd_length_mask)(u32 cmd_header);

sys/dev/drm/i915/intel_ringbuffer.h

744

static inline u32

sys/dev/drm/i915/intel_ringbuffer.h

752

intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)

sys/dev/drm/i915/intel_ringbuffer.h

802

void intel_ring_reset(struct intel_ring *ring, u32 tail);

sys/dev/drm/i915/intel_ringbuffer.h

815

u32 __must_check *intel_ring_begin(struct i915_request *rq, unsigned int n);

sys/dev/drm/i915/intel_ringbuffer.h

817

static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)

sys/dev/drm/i915/intel_ringbuffer.h

830

static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)

sys/dev/drm/i915/intel_ringbuffer.h

848

static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)

sys/dev/drm/i915/intel_ringbuffer.h

851

u32 offset = addr - rq->ring->vaddr;

sys/dev/drm/i915/intel_ringbuffer.h

895

void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);

sys/dev/drm/i915/intel_ringbuffer.h

912

static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_ringbuffer.h

925

static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_ringbuffer.h

931

u32 seqno)

sys/dev/drm/i915/intel_ringbuffer.h

937

u32 seqno)

sys/dev/drm/i915/intel_ringbuffer.h

944

u32 seqno)

sys/dev/drm/i915/intel_ringbuffer.h

962

static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_ringbuffer.h

967

static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)

sys/dev/drm/i915/intel_ringbuffer.h

981

static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)

sys/dev/drm/i915/intel_ringbuffer.h

993

intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)

sys/dev/drm/i915/intel_runtime_pm.c

1111

u32 phy_control = dev_priv->chv_phy_control;

sys/dev/drm/i915/intel_runtime_pm.c

1112

u32 phy_status = 0;

sys/dev/drm/i915/intel_runtime_pm.c

1113

u32 phy_status_mask = 0xffffffff;

sys/dev/drm/i915/intel_runtime_pm.c

1312

u32 reg, val, expected, actual;

sys/dev/drm/i915/intel_runtime_pm.c

1436

u32 state, ctrl;

sys/dev/drm/i915/intel_runtime_pm.c

1465

u32 state;

sys/dev/drm/i915/intel_runtime_pm.c

1466

u32 ctrl;

sys/dev/drm/i915/intel_runtime_pm.c

309

static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_runtime_pm.c

313

u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);

sys/dev/drm/i915/intel_runtime_pm.c

314

u32 ret;

sys/dev/drm/i915/intel_runtime_pm.c

3142

u32 val, status;

sys/dev/drm/i915/intel_runtime_pm.c

331

u32 reqs;

sys/dev/drm/i915/intel_runtime_pm.c

3375

u32 dw1, dw9, dw10;

sys/dev/drm/i915/intel_runtime_pm.c

3399

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

3436

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

3485

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

3521

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

3575

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

369

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

411

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

430

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

448

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

469

u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |

sys/dev/drm/i915/intel_runtime_pm.c

513

u32 state)

sys/dev/drm/i915/intel_runtime_pm.c

517

u32 v;

sys/dev/drm/i915/intel_runtime_pm.c

549

static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_runtime_pm.c

551

u32 mask;

sys/dev/drm/i915/intel_runtime_pm.c

564

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

729

u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);

sys/dev/drm/i915/intel_runtime_pm.c

730

u32 bios_req = I915_READ(regs->bios);

sys/dev/drm/i915/intel_runtime_pm.c

734

u32 drv_req = I915_READ(regs->driver);

sys/dev/drm/i915/intel_runtime_pm.c

789

u32 tmp = I915_READ(DBUF_CTL);

sys/dev/drm/i915/intel_runtime_pm.c

877

u32 mask;

sys/dev/drm/i915/intel_runtime_pm.c

878

u32 state;

sys/dev/drm/i915/intel_runtime_pm.c

879

u32 ctrl;

sys/dev/drm/i915/intel_runtime_pm.c

926

u32 mask;

sys/dev/drm/i915/intel_runtime_pm.c

927

u32 state;

sys/dev/drm/i915/intel_runtime_pm.c

928

u32 ctrl;

sys/dev/drm/i915/intel_runtime_pm.c

959

u32 val;

sys/dev/drm/i915/intel_runtime_pm.c

998

u32 val = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_sdvo.c

1277

u32 sdvox;

sys/dev/drm/i915/intel_sdvo.c

1407

u32 val;

sys/dev/drm/i915/intel_sdvo.c

1446

u32 flags = 0, sdvox;

sys/dev/drm/i915/intel_sdvo.c

1536

u32 temp;

sys/dev/drm/i915/intel_sdvo.c

155

u32 max_hscan, max_vscan;

sys/dev/drm/i915/intel_sdvo.c

1595

u32 temp;

sys/dev/drm/i915/intel_sdvo.c

208

static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)

sys/dev/drm/i915/intel_sdvo.c

212

u32 bval = val, cval = val;

sys/dev/drm/i915/intel_sdvo.c

2986

static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)

sys/dev/drm/i915/intel_sideband.c

108

u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

110

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

118

void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

124

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)

sys/dev/drm/i915/intel_sideband.c

126

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

138

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)

sys/dev/drm/i915/intel_sideband.c

140

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

147

u8 port, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

153

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

155

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

161

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

167

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

169

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

175

void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

181

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg)

sys/dev/drm/i915/intel_sideband.c

183

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

198

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

205

u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,

sys/dev/drm/i915/intel_sideband.c

208

u32 value = 0;

sys/dev/drm/i915/intel_sideband.c

244

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

sys/dev/drm/i915/intel_sideband.c

247

u32 tmp;

sys/dev/drm/i915/intel_sideband.c

283

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

285

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

291

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

42

static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,

sys/dev/drm/i915/intel_sideband.c

43

u32 port, u32 opcode, u32 addr, u32 *val)

sys/dev/drm/i915/intel_sideband.c

45

u32 cmd, be = 0xf, bar = 0;

sys/dev/drm/i915/intel_sideband.c

80

u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)

sys/dev/drm/i915/intel_sideband.c

82

u32 val = 0;

sys/dev/drm/i915/intel_sideband.c

94

int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)

sys/dev/drm/i915/intel_sprite.c

1564

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_sprite.c

1590

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_sprite.c

1617

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_sprite.c

1649

u32 format, uint64_t modifier)

sys/dev/drm/i915/intel_sprite.c

189

u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);

sys/dev/drm/i915/intel_sprite.c

238

u32 stride, max_stride;

sys/dev/drm/i915/intel_sprite.c

259

u32 src_x, src_y, src_w, src_h;

sys/dev/drm/i915/intel_sprite.c

290

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_sprite.c

366

u32 plane_ctl = plane_state->ctl;

sys/dev/drm/i915/intel_sprite.c

368

u32 surf_addr = plane_state->color_plane[0].offset;

sys/dev/drm/i915/intel_sprite.c

369

u32 stride = skl_plane_stride(plane_state, 0);

sys/dev/drm/i915/intel_sprite.c

370

u32 aux_stride = skl_plane_stride(plane_state, 1);

sys/dev/drm/i915/intel_sprite.c

558

static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_sprite.c

564

u32 sprctl;

sys/dev/drm/i915/intel_sprite.c

634

u32 sprctl = plane_state->ctl;

sys/dev/drm/i915/intel_sprite.c

635

u32 sprsurf_offset = plane_state->color_plane[0].offset;

sys/dev/drm/i915/intel_sprite.c

636

u32 linear_offset;

sys/dev/drm/i915/intel_sprite.c

724

static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_sprite.c

732

u32 sprctl;

sys/dev/drm/i915/intel_sprite.c

794

u32 sprctl = plane_state->ctl, sprscale = 0;

sys/dev/drm/i915/intel_sprite.c

795

u32 sprsurf_offset = plane_state->color_plane[0].offset;

sys/dev/drm/i915/intel_sprite.c

796

u32 linear_offset;

sys/dev/drm/i915/intel_sprite.c

86

u32 psr_status;

sys/dev/drm/i915/intel_sprite.c

893

u32 pixel_format, u64 modifier,

sys/dev/drm/i915/intel_sprite.c

899

static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,

sys/dev/drm/i915/intel_sprite.c

907

u32 dvscntr;

sys/dev/drm/i915/intel_sprite.c

966

u32 dvscntr = plane_state->ctl, dvsscale = 0;

sys/dev/drm/i915/intel_sprite.c

967

u32 dvssurf_offset = plane_state->color_plane[0].offset;

sys/dev/drm/i915/intel_sprite.c

968

u32 linear_offset;

sys/dev/drm/i915/intel_tv.c

1138

u32 tv_ctl, save_tv_ctl;

sys/dev/drm/i915/intel_tv.c

1139

u32 tv_dac, save_tv_dac;

sys/dev/drm/i915/intel_tv.c

1440

u32 tv_dac_on, tv_dac_off, save_tv_dac;

sys/dev/drm/i915/intel_tv.c

308

u32 clock;

sys/dev/drm/i915/intel_tv.c

310

u32 oversample;

sys/dev/drm/i915/intel_tv.c

335

u32 sc_reset;

sys/dev/drm/i915/intel_tv.c

342

const u32 *filter_table;

sys/dev/drm/i915/intel_tv.c

63

static const u32 filter_table[] = {

sys/dev/drm/i915/intel_tv.c

802

u32 tmp = I915_READ(TV_CTL);

sys/dev/drm/i915/intel_tv.c

908

u32 hctl1, hctl2, hctl3;

sys/dev/drm/i915/intel_tv.c

909

u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;

sys/dev/drm/i915/intel_tv.c

990

u32 tv_ctl;

sys/dev/drm/i915/intel_tv.c

991

u32 scctl1, scctl2, scctl3;

sys/dev/drm/i915/intel_uc.c

37

u32 guc_status;

sys/dev/drm/i915/intel_uc_fw.c

106

uc_fw->rsa_size = css->key_size_dw * sizeof(u32);

sys/dev/drm/i915/intel_uc_fw.c

203

u32 ggtt_pin_bias;

sys/dev/drm/i915/intel_uc_fw.c

85

sizeof(u32);

sys/dev/drm/i915/intel_uc_fw.c

96

uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);

sys/dev/drm/i915/intel_uc_fw.h

132

static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)

sys/dev/drm/i915/intel_uc_fw.h

69

u32 header_size;

sys/dev/drm/i915/intel_uc_fw.h

70

u32 header_offset;

sys/dev/drm/i915/intel_uc_fw.h

71

u32 rsa_size;

sys/dev/drm/i915/intel_uc_fw.h

72

u32 rsa_offset;

sys/dev/drm/i915/intel_uc_fw.h

73

u32 ucode_size;

sys/dev/drm/i915/intel_uc_fw.h

74

u32 ucode_offset;

sys/dev/drm/i915/intel_uncore.c

104

const u32 ack)

sys/dev/drm/i915/intel_uncore.c

1151

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_uncore.c

1263

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_uncore.c

128

const u32 ack_bit = FORCEWAKE_KERNEL;

sys/dev/drm/i915/intel_uncore.c

129

const u32 value = type == ACK_SET ? ack_bit : 0;

sys/dev/drm/i915/intel_uncore.c

1466

u32 ecobus;

sys/dev/drm/i915/intel_uncore.c

1680

u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);

sys/dev/drm/i915/intel_uncore.c

1720

const u32 base = engine->mmio_base;

sys/dev/drm/i915/intel_uncore.c

1871

u32 hw_domain_mask)

sys/dev/drm/i915/intel_uncore.c

1912

const u32 hw_engine_mask[I915_NUM_ENGINES] = {

sys/dev/drm/i915/intel_uncore.c

1919

u32 hw_mask;

sys/dev/drm/i915/intel_uncore.c

1951

const u32 hw_engine_mask[I915_NUM_ENGINES] = {

sys/dev/drm/i915/intel_uncore.c

1961

u32 hw_mask;

sys/dev/drm/i915/intel_uncore.c

2006

u32 mask,

sys/dev/drm/i915/intel_uncore.c

2007

u32 value,

sys/dev/drm/i915/intel_uncore.c

2010

u32 *out_value)

sys/dev/drm/i915/intel_uncore.c

2012

u32 reg_value = 0;

sys/dev/drm/i915/intel_uncore.c

2054

u32 mask,

sys/dev/drm/i915/intel_uncore.c

2055

u32 value,

sys/dev/drm/i915/intel_uncore.c

2058

u32 *out_value)

sys/dev/drm/i915/intel_uncore.c

2062

u32 reg_value;

sys/dev/drm/i915/intel_uncore.c

2265

u32 guc_domain = INTEL_GEN(dev_priv) >= 11 ? GEN11_GRDOM_GUC :

sys/dev/drm/i915/intel_uncore.c

2314

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_uncore.c

2337

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_uncore.c

286

static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_uncore.c

288

u32 val;

sys/dev/drm/i915/intel_uncore.c

315

static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_uncore.c

317

u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);

sys/dev/drm/i915/intel_uncore.c

324

u32 n;

sys/dev/drm/i915/intel_uncore.c

436

const u32 cap = dev_priv->edram_cap;

sys/dev/drm/i915/intel_uncore.c

480

u32 dbg;

sys/dev/drm/i915/intel_uncore.c

494

u32 cer;

sys/dev/drm/i915/intel_uncore.c

508

u32 fifodbg;

sys/dev/drm/i915/intel_uncore.c

819

static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)

sys/dev/drm/i915/intel_uncore.c

849

find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)

sys/dev/drm/i915/intel_uncore.c

86

const u32 ack,

sys/dev/drm/i915/intel_uncore.c

87

const u32 value)

sys/dev/drm/i915/intel_uncore.c

936

static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)

sys/dev/drm/i915/intel_uncore.c

938

u32 offset = i915_mmio_reg_offset(*reg);

sys/dev/drm/i915/intel_uncore.c

949

static bool is_gen##x##_shadowed(u32 offset) \

sys/dev/drm/i915/intel_uncore.c

96

const u32 ack)

sys/dev/drm/i915/intel_uncore.h

109

u32 fw_set;

sys/dev/drm/i915/intel_uncore.h

110

u32 fw_clear;

sys/dev/drm/i915/intel_uncore.h

111

u32 fw_reset;

sys/dev/drm/i915/intel_uncore.h

181

u32 mask,

sys/dev/drm/i915/intel_uncore.h

182

u32 value,

sys/dev/drm/i915/intel_uncore.h

185

u32 *out_value);

sys/dev/drm/i915/intel_uncore.h

189

u32 mask,

sys/dev/drm/i915/intel_uncore.h

190

u32 value,

sys/dev/drm/i915/intel_uncore.h

198

u32 mask,

sys/dev/drm/i915/intel_uncore.h

199

u32 value,

sys/dev/drm/i915/intel_uncore.h

202

u32 *out_value);

sys/dev/drm/i915/intel_uncore.h

206

u32 mask,

sys/dev/drm/i915/intel_uncore.h

207

u32 value,

sys/dev/drm/i915/intel_uncore.h

74

u32 (*mmio_readl)(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_uncore.h

84

i915_reg_t r, u32 val, bool trace);

sys/dev/drm/i915/intel_uncore.h

88

u32 start;

sys/dev/drm/i915/intel_uncore.h

89

u32 end;

sys/dev/drm/i915/intel_vbt_defs.h

478

u32 lvds_panel_channel_bits;

sys/dev/drm/i915/intel_vbt_defs.h

486

u32 dps_panel_type_bits;

sys/dev/drm/i915/intel_vbt_defs.h

488

u32 blt_control_type_bits;

sys/dev/drm/i915/intel_vbt_defs.h

510

u32 lvds_reg;

sys/dev/drm/i915/intel_vbt_defs.h

511

u32 lvds_reg_val;

sys/dev/drm/i915/intel_vbt_defs.h

512

u32 pp_on_reg;

sys/dev/drm/i915/intel_vbt_defs.h

513

u32 pp_on_reg_val;

sys/dev/drm/i915/intel_vbt_defs.h

514

u32 pp_off_reg;

sys/dev/drm/i915/intel_vbt_defs.h

515

u32 pp_off_reg_val;

sys/dev/drm/i915/intel_vbt_defs.h

516

u32 pp_cycle_reg;

sys/dev/drm/i915/intel_vbt_defs.h

517

u32 pp_cycle_reg_val;

sys/dev/drm/i915/intel_vbt_defs.h

518

u32 pfit_reg;

sys/dev/drm/i915/intel_vbt_defs.h

519

u32 pfit_reg_val;

sys/dev/drm/i915/intel_vbt_defs.h

557

u32 serial;

sys/dev/drm/i915/intel_vbt_defs.h

60

u32 bdb_offset;

sys/dev/drm/i915/intel_vbt_defs.h

61

u32 aim_offset[4];

sys/dev/drm/i915/intel_vbt_defs.h

739

u32 color_depth;

sys/dev/drm/i915/intel_vbt_defs.h

741

u32 sdrrs_msa_timing_delay;

sys/dev/drm/i915/intel_wopcm.c

100

(guc_wopcm_size - offset) < sizeof(u32)) {

sys/dev/drm/i915/intel_wopcm.c

103

(u32)(offset + sizeof(u32)) / 1024);

sys/dev/drm/i915/intel_wopcm.c

110

static inline int gen9_check_huc_fw_fits(u32 guc_wopcm_size, u32 huc_fw_size)

sys/dev/drm/i915/intel_wopcm.c

128

u32 guc_wopcm_base, u32 guc_wopcm_size,

sys/dev/drm/i915/intel_wopcm.c

129

u32 huc_fw_size)

sys/dev/drm/i915/intel_wopcm.c

158

u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);

sys/dev/drm/i915/intel_wopcm.c

159

u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);

sys/dev/drm/i915/intel_wopcm.c

160

u32 ctx_rsvd = context_reserved_size(i915);

sys/dev/drm/i915/intel_wopcm.c

161

u32 guc_wopcm_base;

sys/dev/drm/i915/intel_wopcm.c

162

u32 guc_wopcm_size;

sys/dev/drm/i915/intel_wopcm.c

163

u32 guc_wopcm_rsvd;

sys/dev/drm/i915/intel_wopcm.c

220

i915_reg_t reg, u32 val, u32 mask,

sys/dev/drm/i915/intel_wopcm.c

221

u32 locked_bit)

sys/dev/drm/i915/intel_wopcm.c

223

u32 reg_val;

sys/dev/drm/i915/intel_wopcm.c

247

u32 huc_agent;

sys/dev/drm/i915/intel_wopcm.c

248

u32 mask;

sys/dev/drm/i915/intel_wopcm.c

79

static inline u32 context_reserved_size(struct drm_i915_private *i915)

sys/dev/drm/i915/intel_wopcm.c

89

static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)

sys/dev/drm/i915/intel_wopcm.c

91

u32 offset;

sys/dev/drm/i915/intel_wopcm.h

20

u32 size;

sys/dev/drm/i915/intel_wopcm.h

22

u32 base;

sys/dev/drm/i915/intel_wopcm.h

23

u32 size;

sys/dev/drm/i915/intel_workarounds.c

1103

const u32 base = engine->mmio_base;

sys/dev/drm/i915/intel_workarounds.c

567

u32 *cs;

sys/dev/drm/i915/intel_workarounds.c

624

wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

636

wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,

sys/dev/drm/i915/intel_workarounds.c

637

u32 val)

sys/dev/drm/i915/intel_workarounds.c

649

wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

655

wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

66

i915_reg_t reg, const u32 mask, const u32 val)

sys/dev/drm/i915/intel_workarounds.c

766

u32 mcr_slice_subslice_mask;

sys/dev/drm/i915/intel_workarounds.c

787

u32 slice = fls(sseu->slice_mask);

sys/dev/drm/i915/intel_workarounds.c

788

u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);

sys/dev/drm/i915/intel_workarounds.c

966

u32 val = I915_READ_FW(wa->reg);

sys/dev/drm/i915/intel_workarounds.c

988

u32 nopid;

sys/dev/drm/i915/intel_workarounds.h

14

u32 mask;

sys/dev/drm/i915/intel_workarounds.h

15

u32 val;

sys/dev/drm/i915/vlv_dsi.c

1057

u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));

sys/dev/drm/i915/vlv_dsi.c

106

u8 *data, u32 len)

sys/dev/drm/i915/vlv_dsi.c

1068

u32 tmp = I915_READ(MIPI_CTRL(port));

sys/dev/drm/i915/vlv_dsi.c

108

u32 i, j;

sys/dev/drm/i915/vlv_dsi.c

111

u32 val = I915_READ(reg);

sys/dev/drm/i915/vlv_dsi.c

113

for (j = 0; j < min_t(u32, len - i, 4); j++)

sys/dev/drm/i915/vlv_dsi.c

1255

u32 pclk;

sys/dev/drm/i915/vlv_dsi.c

129

u32 data_mask, ctrl_mask;

sys/dev/drm/i915/vlv_dsi.c

1301

static u16 txclkesc(u32 divider, unsigned int us)

sys/dev/drm/i915/vlv_dsi.c

1383

static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)

sys/dev/drm/i915/vlv_dsi.c

1411

u32 val, tmp;

sys/dev/drm/i915/vlv_dsi.c

1599

u32 val;

sys/dev/drm/i915/vlv_dsi.c

1692

u32 val;

sys/dev/drm/i915/vlv_dsi.c

1713

u32 allowed_scalers;

sys/dev/drm/i915/vlv_dsi.c

247

static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,

sys/dev/drm/i915/vlv_dsi.c

253

u32 mask;

sys/dev/drm/i915/vlv_dsi.c

365

u32 tmp;

sys/dev/drm/i915/vlv_dsi.c

414

u32 val;

sys/dev/drm/i915/vlv_dsi.c

488

u32 val;

sys/dev/drm/i915/vlv_dsi.c

515

u32 val;

sys/dev/drm/i915/vlv_dsi.c

54

enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)

sys/dev/drm/i915/vlv_dsi.c

566

u32 val;

sys/dev/drm/i915/vlv_dsi.c

598

u32 tmp;

sys/dev/drm/i915/vlv_dsi.c

638

u32 val;

sys/dev/drm/i915/vlv_dsi.c

681

u32 temp;

sys/dev/drm/i915/vlv_dsi.c

702

u32 temp;

sys/dev/drm/i915/vlv_dsi.c

735

u32 temp;

sys/dev/drm/i915/vlv_dsi.c

77

u32 mask;

sys/dev/drm/i915/vlv_dsi.c

806

u32 val;

sys/dev/drm/i915/vlv_dsi.c

837

u32 val;

sys/dev/drm/i915/vlv_dsi.c

90

const u8 *data, u32 len)

sys/dev/drm/i915/vlv_dsi.c

92

u32 i, j;

sys/dev/drm/i915/vlv_dsi.c

95

u32 val = 0;

sys/dev/drm/i915/vlv_dsi.c

954

u32 val;

sys/dev/drm/i915/vlv_dsi.c

97

for (j = 0; j < min_t(u32, len - i, 4); j++)

sys/dev/drm/i915/vlv_dsi.c

993

u32 val;

sys/dev/drm/i915/vlv_dsi_pll.c

105

(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;

sys/dev/drm/i915/vlv_dsi_pll.c

120

u32 dsi_clk;

sys/dev/drm/i915/vlv_dsi_pll.c

181

u32 tmp;

sys/dev/drm/i915/vlv_dsi_pll.c

198

u32 val;

sys/dev/drm/i915/vlv_dsi_pll.c

199

u32 mask;

sys/dev/drm/i915/vlv_dsi_pll.c

235

u32 val;

sys/dev/drm/i915/vlv_dsi_pll.c

264

u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

sys/dev/drm/i915/vlv_dsi_pll.c

269

u32 dsi_clock, pclk;

sys/dev/drm/i915/vlv_dsi_pll.c

270

u32 pll_ctl, pll_div;

sys/dev/drm/i915/vlv_dsi_pll.c

271

u32 m = 0, p = 0, n;

sys/dev/drm/i915/vlv_dsi_pll.c

330

u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

sys/dev/drm/i915/vlv_dsi_pll.c

333

u32 pclk;

sys/dev/drm/i915/vlv_dsi_pll.c

334

u32 dsi_clk;

sys/dev/drm/i915/vlv_dsi_pll.c

335

u32 dsi_ratio;

sys/dev/drm/i915/vlv_dsi_pll.c

362

u32 temp;

sys/dev/drm/i915/vlv_dsi_pll.c

377

u32 dsi_rate = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

378

u32 pll_ratio = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

379

u32 ddr_clk = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

380

u32 div1_value = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

381

u32 div2_value = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

382

u32 txesc1_div = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

383

u32 txesc2_div = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

41

static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,

sys/dev/drm/i915/vlv_dsi_pll.c

425

u32 tmp;

sys/dev/drm/i915/vlv_dsi_pll.c

426

u32 dsi_rate = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

427

u32 pll_ratio = 0;

sys/dev/drm/i915/vlv_dsi_pll.c

428

u32 rx_div;

sys/dev/drm/i915/vlv_dsi_pll.c

429

u32 tx_div;

sys/dev/drm/i915/vlv_dsi_pll.c

430

u32 rx_div_upper;

sys/dev/drm/i915/vlv_dsi_pll.c

431

u32 rx_div_lower;

sys/dev/drm/i915/vlv_dsi_pll.c

432

u32 mipi_8by3_divider;

sys/dev/drm/i915/vlv_dsi_pll.c

44

u32 dsi_clk_khz;

sys/dev/drm/i915/vlv_dsi_pll.c

45

u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);

sys/dev/drm/i915/vlv_dsi_pll.c

480

u32 dsi_clk;

sys/dev/drm/i915/vlv_dsi_pll.c

528

u32 val;

sys/dev/drm/i915/vlv_dsi_pll.c

564

u32 tmp;

sys/dev/drm/include/asm/io.h

53

static inline u32

sys/dev/drm/include/asm/io.h

56

return *(const volatile u32*)addr;

sys/dev/drm/include/asm/io.h

75

writel(u32 value, volatile void __iomem *addr)

sys/dev/drm/include/drm/drm_bridge.h

254

u32 sampling_edge;

sys/dev/drm/include/drm/drm_bridge.h

261

u32 setup_time_ps;

sys/dev/drm/include/drm/drm_bridge.h

268

u32 hold_time_ps;

sys/dev/drm/include/drm/drm_bridge.h

320

u32 connector_type);

sys/dev/drm/include/drm/drm_bridge.h

324

u32 connector_type);

sys/dev/drm/include/drm/drm_client.h

113

u32 handle;

sys/dev/drm/include/drm/drm_client.h

118

u32 pitch;

sys/dev/drm/include/drm/drm_client.h

138

drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format);

sys/dev/drm/include/drm/drm_color_mgmt.h

68

u32 supported_encodings,

sys/dev/drm/include/drm/drm_color_mgmt.h

69

u32 supported_ranges,

sys/dev/drm/include/drm/drm_connector.h

1148

static inline u32 drm_connector_mask(const struct drm_connector *connector)

sys/dev/drm/include/drm/drm_connector.h

1252

u32 scaling_mode_mask);

sys/dev/drm/include/drm/drm_connector.h

318

u32 color_formats;

sys/dev/drm/include/drm/drm_connector.h

325

const u32 *bus_formats;

sys/dev/drm/include/drm/drm_connector.h

350

u32 bus_flags;

sys/dev/drm/include/drm/drm_connector.h

391

const u32 *formats,

sys/dev/drm/include/drm/drm_crtc.h

199

u32 plane_mask;

sys/dev/drm/include/drm/drm_crtc.h

205

u32 connector_mask;

sys/dev/drm/include/drm/drm_crtc.h

211

u32 encoder_mask;

sys/dev/drm/include/drm/drm_crtc.h

283

u32 target_vblank;

sys/dev/drm/include/drm/drm_crtc.h

291

u32 pageflip_flags;

sys/dev/drm/include/drm/drm_crtc.h

823

u32 (*get_vblank_counter)(struct drm_crtc *crtc);

sys/dev/drm/include/drm/drm_debugfs.h

53

u32 driver_features;

sys/dev/drm/include/drm/drm_device.h

193

u32 max_vblank_count; /**< size of vblank counter register */

sys/dev/drm/include/drm/drm_device.h

60

u32 driver_features;

sys/dev/drm/include/drm/drm_dp_helper.h

1249

u32 quirks;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

254

u32 dpcd_address;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

260

u32 dpcd_address;

sys/dev/drm/include/drm/drm_drv.h

208

u32 (*get_vblank_counter) (struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_drv.h

583

u32 driver_features;

sys/dev/drm/include/drm/drm_drv.h

675

static inline bool drm_core_check_feature(struct drm_device *dev, u32 feature)

sys/dev/drm/include/drm/drm_edid.h

287

u32 serial; /* FIXME: byte order */

sys/dev/drm/include/drm/drm_encoder.h

207

static inline u32 drm_encoder_mask(const struct drm_encoder *encoder)

sys/dev/drm/include/drm/drm_fb_helper.h

194

u32 pseudo_palette[17];

sys/dev/drm/include/drm/drm_fb_helper.h

76

u32 fb_width;

sys/dev/drm/include/drm/drm_fb_helper.h

77

u32 fb_height;

sys/dev/drm/include/drm/drm_fb_helper.h

78

u32 surface_width;

sys/dev/drm/include/drm/drm_fb_helper.h

79

u32 surface_height;

sys/dev/drm/include/drm/drm_fb_helper.h

80

u32 surface_bpp;

sys/dev/drm/include/drm/drm_fb_helper.h

81

u32 surface_depth;

sys/dev/drm/include/drm/drm_fixed.h

163

u32 i = DRM_FIXED_POINT;

sys/dev/drm/include/drm/drm_fixed.h

31

u32 full;

sys/dev/drm/include/drm/drm_fixed.h

35

#define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */

sys/dev/drm/include/drm/drm_fixed.h

36

#define dfixed_const_half(A) (u32)(((A) << 12) + 2048)

sys/dev/drm/include/drm/drm_fixed.h

37

#define dfixed_const_666(A) (u32)(((A) << 12) + 2731)

sys/dev/drm/include/drm/drm_fixed.h

38

#define dfixed_const_8(A) (u32)(((A) << 12) + 3277)

sys/dev/drm/include/drm/drm_fixed.h

45

static inline u32 dfixed_floor(fixed20_12 A)

sys/dev/drm/include/drm/drm_fixed.h

47

u32 non_frac = dfixed_trunc(A);

sys/dev/drm/include/drm/drm_fixed.h

52

static inline u32 dfixed_ceil(fixed20_12 A)

sys/dev/drm/include/drm/drm_fixed.h

54

u32 non_frac = dfixed_trunc(A);

sys/dev/drm/include/drm/drm_fixed.h

62

static inline u32 dfixed_div(fixed20_12 A, fixed20_12 B)

sys/dev/drm/include/drm/drm_fourcc.h

67

u32 format;

sys/dev/drm/include/drm/drm_fourcc.h

85

const struct drm_format_info *__drm_format_info(u32 format);

sys/dev/drm/include/drm/drm_fourcc.h

86

const struct drm_format_info *drm_format_info(u32 format);

sys/dev/drm/include/drm/drm_gem.h

300

u32 *handlep);

sys/dev/drm/include/drm/drm_gem.h

301

int drm_gem_handle_delete(struct drm_file *filp, u32 handle);

sys/dev/drm/include/drm/drm_gem.h

312

struct drm_gem_object *drm_gem_object_lookup(struct drm_file *filp, u32 handle);

sys/dev/drm/include/drm/drm_gem.h

314

u32 handle, u64 *offset);

sys/dev/drm/include/drm/drm_ioctl.h

168

int drm_ioctl_permit(u32 flags, struct drm_file *file_priv);

sys/dev/drm/include/drm/drm_mipi_dsi.h

158

u32 channel;

sys/dev/drm/include/drm/drm_modes.h

495

void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags);

sys/dev/drm/include/drm/drm_modes.h

497

struct drm_display_mode *dmode, u32 *bus_flags,

sys/dev/drm/include/drm/drm_plane.h

736

static inline u32 drm_plane_mask(const struct drm_plane *plane)

sys/dev/drm/include/drm/drm_property.h

243

u32 flags, const char *name,

sys/dev/drm/include/drm/drm_property.h

246

u32 flags, const char *name,

sys/dev/drm/include/drm/drm_property.h

250

u32 flags, const char *name,

sys/dev/drm/include/drm/drm_property.h

255

u32 flags, const char *name,

sys/dev/drm/include/drm/drm_property.h

258

u32 flags, const char *name,

sys/dev/drm/include/drm/drm_property.h

261

u32 flags, const char *name,

sys/dev/drm/include/drm/drm_property.h

264

u32 flags, const char *name);

sys/dev/drm/include/drm/drm_syncobj.h

133

u32 handle);

sys/dev/drm/include/drm/drm_syncobj.h

137

u32 handle, u64 point,

sys/dev/drm/include/drm/drm_syncobj.h

145

struct drm_syncobj *syncobj, u32 *handle);

sys/dev/drm/include/drm/drm_vblank.h

130

u32 last;

sys/dev/drm/include/linux/hash.h

41

static inline u32 hash_32(u32 val, unsigned int bits)

sys/dev/drm/include/linux/hash.h

43

u32 ret;

sys/dev/drm/include/linux/i2c.h

73

u32 (*functionality) (struct i2c_adapter *);

sys/dev/drm/include/linux/kernel.h

132

#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))

sys/dev/drm/include/linux/kernel.h

133

#define lower_32_bits(n) ((u32)(n))

sys/dev/drm/include/linux/kernel.h

50

#define U32_MAX ((u32)~0U)

sys/dev/drm/include/linux/log2.h

133

fls((u32)(n)) - 1 : flsll((u64)(n)) - 1 \

sys/dev/drm/include/linux/math64.h

83

mul_u32_u32(u32 a, u32 b)

sys/dev/drm/include/linux/math64.h

89

mul_u64_u32_div(u64 x, u32 y, u32 div)

sys/dev/drm/include/linux/pci.h

136

pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)

sys/dev/drm/include/linux/pci.h

138

*val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);

sys/dev/drm/include/linux/pci.h

157

pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)

sys/dev/drm/include/linux/pci.h

554

int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);

sys/dev/drm/include/linux/reservation.h

61

u32 shared_count, shared_max;

sys/dev/drm/include/linux/xarray.h

115

xa_alloc(struct xarray *xa, u32 *id, void *entry, int limit, gfp_t gfp)

sys/dev/drm/include/linux/xarray.h

34

int __xa_alloc(struct xarray *, u32 *, void *, int, gfp_t);

sys/dev/drm/include/linux/xarray.h

35

int __xa_alloc_cyclic(struct xarray *, u32 *, void *, int, u32 *, gfp_t);

sys/dev/drm/linux_pci.c

30

pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)

sys/dev/drm/linux_reservation.c

107

u32 i;

sys/dev/drm/linux_reservation.c

237

u32 i = 0;

sys/dev/drm/linux_reservation.c

72

u32 max;

sys/dev/drm/radeon/atom.c

229

val = get_unaligned_le32((u32 *)&ctx->ps[idx]);

sys/dev/drm/radeon/atombios_crtc.c

1067

u32 pll_clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

1068

u32 clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

1069

u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;

sys/dev/drm/radeon/atombios_crtc.c

1120

u32 step_size;

sys/dev/drm/radeon/atombios_crtc.c

1121

u32 amount = (((fb_div * 10) + frac_fb_div) *

sys/dev/drm/radeon/atombios_crtc.c

1122

(u32)radeon_crtc->ss.percentage) /

sys/dev/drm/radeon/atombios_crtc.c

1123

(100 * (u32)radeon_crtc->ss.percentage_divider);

sys/dev/drm/radeon/atombios_crtc.c

1128

step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/drm/radeon/atombios_crtc.c

1131

step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/drm/radeon/atombios_crtc.c

1154

u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);

sys/dev/drm/radeon/atombios_crtc.c

1155

u32 tmp, viewport_w, viewport_h;

sys/dev/drm/radeon/atombios_crtc.c

1344

u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;

sys/dev/drm/radeon/atombios_crtc.c

1388

(u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);

sys/dev/drm/radeon/atombios_crtc.c

1390

(u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);

sys/dev/drm/radeon/atombios_crtc.c

1465

u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;

sys/dev/drm/radeon/atombios_crtc.c

1466

u32 viewport_w, viewport_h;

sys/dev/drm/radeon/atombios_crtc.c

1593

(u32) fb_location);

sys/dev/drm/radeon/atombios_crtc.c

1595

radeon_crtc->crtc_offset, (u32) fb_location);

sys/dev/drm/radeon/atombios_crtc.c

1682

u32 disp_merge_cntl;

sys/dev/drm/radeon/atombios_crtc.c

1707

static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)

sys/dev/drm/radeon/atombios_crtc.c

1712

u32 pll_in_use = 0;

sys/dev/drm/radeon/atombios_crtc.c

1775

u32 adjusted_clock, test_adjusted_clock;

sys/dev/drm/radeon/atombios_crtc.c

1854

u32 pll_in_use;

sys/dev/drm/radeon/atombios_crtc.c

213

static const u32 vga_control_regs[6] =

sys/dev/drm/radeon/atombios_crtc.c

230

u32 vga_control = 0;

sys/dev/drm/radeon/atombios_crtc.c

395

u32 ss_cntl;

sys/dev/drm/radeon/atombios_crtc.c

555

static u32 atombios_adjust_pll(struct drm_crtc *crtc,

sys/dev/drm/radeon/atombios_crtc.c

564

u32 adjusted_clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

566

u32 dp_clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

567

u32 clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

772

u32 dispclk)

sys/dev/drm/radeon/atombios_crtc.c

821

u32 crtc_id,

sys/dev/drm/radeon/atombios_crtc.c

823

u32 encoder_mode,

sys/dev/drm/radeon/atombios_crtc.c

824

u32 encoder_id,

sys/dev/drm/radeon/atombios_crtc.c

825

u32 clock,

sys/dev/drm/radeon/atombios_crtc.c

826

u32 ref_div,

sys/dev/drm/radeon/atombios_crtc.c

827

u32 fb_div,

sys/dev/drm/radeon/atombios_crtc.c

828

u32 frac_fb_div,

sys/dev/drm/radeon/atombios_crtc.c

829

u32 post_div,

sys/dev/drm/radeon/atombios_dp.c

60

u32 src_tmp[5], dst_tmp[5];

sys/dev/drm/radeon/atombios_encoders.c

1506

u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;

sys/dev/drm/radeon/atombios_encoders.c

1687

u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);

sys/dev/drm/radeon/atombios_encoders.c

2489

u32 bios_0_scratch;

sys/dev/drm/radeon/atombios_encoders.c

40

u32 bios_2_scratch;

sys/dev/drm/radeon/atombios_encoders.c

57

u32 bios_2_scratch;

sys/dev/drm/radeon/atombios_i2c.c

157

u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);;

sys/dev/drm/radeon/atombios_i2c.c

158

u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap)

sys/dev/drm/radeon/btc_dpm.c

1013

#define BARTS_SYSLS_DISABLE_LENGTH sizeof(barts_sysls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1015

static const u32 barts_sysls_enable[] =

sys/dev/drm/radeon/btc_dpm.c

1033

#define BARTS_SYSLS_ENABLE_LENGTH sizeof(barts_sysls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1036

static const u32 caicos_sysls_default[] =

sys/dev/drm/radeon/btc_dpm.c

1053

#define CAICOS_SYSLS_DEFAULT_LENGTH sizeof(caicos_sysls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1055

static const u32 caicos_sysls_disable[] =

sys/dev/drm/radeon/btc_dpm.c

107

#define BARTS_CGCG_CGLS_DEFAULT_LENGTH sizeof(barts_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1072

#define CAICOS_SYSLS_DISABLE_LENGTH sizeof(caicos_sysls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1074

static const u32 caicos_sysls_enable[] =

sys/dev/drm/radeon/btc_dpm.c

109

static const u32 barts_cgcg_cgls_disable[] =

sys/dev/drm/radeon/btc_dpm.c

1091

#define CAICOS_SYSLS_ENABLE_LENGTH sizeof(caicos_sysls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1094

static const u32 turks_sysls_default[] =

sys/dev/drm/radeon/btc_dpm.c

1112

#define TURKS_SYSLS_DEFAULT_LENGTH sizeof(turks_sysls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1114

static const u32 turks_sysls_disable[] =

sys/dev/drm/radeon/btc_dpm.c

1132

#define TURKS_SYSLS_DISABLE_LENGTH sizeof(turks_sysls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1134

static const u32 turks_sysls_enable[] =

sys/dev/drm/radeon/btc_dpm.c

1152

#define TURKS_SYSLS_ENABLE_LENGTH sizeof(turks_sysls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

1156

u32 btc_valid_sclk[40] =

sys/dev/drm/radeon/btc_dpm.c

1172

u32 *max_clock)

sys/dev/drm/radeon/btc_dpm.c

1174

u32 i, clock = 0;

sys/dev/drm/radeon/btc_dpm.c

1189

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/drm/radeon/btc_dpm.c

1191

u32 i;

sys/dev/drm/radeon/btc_dpm.c

1208

static u32 btc_find_valid_clock(struct radeon_clock_array *clocks,

sys/dev/drm/radeon/btc_dpm.c

1209

u32 max_clock, u32 requested_clock)

sys/dev/drm/radeon/btc_dpm.c

1225

static u32 btc_get_valid_mclk(struct radeon_device *rdev,

sys/dev/drm/radeon/btc_dpm.c

1226

u32 max_mclk, u32 requested_mclk)

sys/dev/drm/radeon/btc_dpm.c

1232

static u32 btc_get_valid_sclk(struct radeon_device *rdev,

sys/dev/drm/radeon/btc_dpm.c

1233

u32 max_sclk, u32 requested_sclk)

sys/dev/drm/radeon/btc_dpm.c

1240

const u32 max_sclk, const u32 max_mclk,

sys/dev/drm/radeon/btc_dpm.c

1241

u32 *sclk, u32 *mclk)

sys/dev/drm/radeon/btc_dpm.c

1334

u32 tmp, bif;

sys/dev/drm/radeon/btc_dpm.c

1438

const u32 *sequence, u32 count)

sys/dev/drm/radeon/btc_dpm.c

1440

u32 i, length = count * 3;

sys/dev/drm/radeon/btc_dpm.c

1441

u32 tmp;

sys/dev/drm/radeon/btc_dpm.c

1453

u32 count;

sys/dev/drm/radeon/btc_dpm.c

1454

const u32 *p = NULL;

sys/dev/drm/radeon/btc_dpm.c

1457

p = (const u32 *)&barts_cgcg_cgls_default;

sys/dev/drm/radeon/btc_dpm.c

1460

p = (const u32 *)&turks_cgcg_cgls_default;

sys/dev/drm/radeon/btc_dpm.c

1463

p = (const u32 *)&caicos_cgcg_cgls_default;

sys/dev/drm/radeon/btc_dpm.c

1474

u32 count;

sys/dev/drm/radeon/btc_dpm.c

1475

const u32 *p = NULL;

sys/dev/drm/radeon/btc_dpm.c

1479

p = (const u32 *)&barts_cgcg_cgls_enable;

sys/dev/drm/radeon/btc_dpm.c

1482

p = (const u32 *)&turks_cgcg_cgls_enable;

sys/dev/drm/radeon/btc_dpm.c

1485

p = (const u32 *)&caicos_cgcg_cgls_enable;

sys/dev/drm/radeon/btc_dpm.c

1491

p = (const u32 *)&barts_cgcg_cgls_disable;

sys/dev/drm/radeon/btc_dpm.c

1494

p = (const u32 *)&turks_cgcg_cgls_disable;

sys/dev/drm/radeon/btc_dpm.c

1497

p = (const u32 *)&caicos_cgcg_cgls_disable;

sys/dev/drm/radeon/btc_dpm.c

1508

u32 count;

sys/dev/drm/radeon/btc_dpm.c

1509

const u32 *p = NULL;

sys/dev/drm/radeon/btc_dpm.c

1512

p = (const u32 *)&barts_mgcg_default;

sys/dev/drm/radeon/btc_dpm.c

1515

p = (const u32 *)&turks_mgcg_default;

sys/dev/drm/radeon/btc_dpm.c

1518

p = (const u32 *)&caicos_mgcg_default;

sys/dev/drm/radeon/btc_dpm.c

1529

u32 count;

sys/dev/drm/radeon/btc_dpm.c

1530

const u32 *p = NULL;

sys/dev/drm/radeon/btc_dpm.c

1534

p = (const u32 *)&barts_mgcg_enable;

sys/dev/drm/radeon/btc_dpm.c

1537

p = (const u32 *)&turks_mgcg_enable;

sys/dev/drm/radeon/btc_dpm.c

1540

p = (const u32 *)&caicos_mgcg_enable;

sys/dev/drm/radeon/btc_dpm.c

1546

p = (const u32 *)&barts_mgcg_disable[0];

sys/dev/drm/radeon/btc_dpm.c

1549

p = (const u32 *)&turks_mgcg_disable[0];

sys/dev/drm/radeon/btc_dpm.c

1552

p = (const u32 *)&caicos_mgcg_disable[0];

sys/dev/drm/radeon/btc_dpm.c

1563

u32 count;

sys/dev/drm/radeon/btc_dpm.c

1564

const u32 *p = NULL;

sys/dev/drm/radeon/btc_dpm.c

1567

p = (const u32 *)&barts_sysls_default;

sys/dev/drm/radeon/btc_dpm.c

1570

p = (const u32 *)&turks_sysls_default;

sys/dev/drm/radeon/btc_dpm.c

1573

p = (const u32 *)&caicos_sysls_default;

sys/dev/drm/radeon/btc_dpm.c

1584

u32 count;

sys/dev/drm/radeon/btc_dpm.c

1585

const u32 *p = NULL;

sys/dev/drm/radeon/btc_dpm.c

1589

p = (const u32 *)&barts_sysls_enable;

sys/dev/drm/radeon/btc_dpm.c

1592

p = (const u32 *)&turks_sysls_enable;

sys/dev/drm/radeon/btc_dpm.c

1595

p = (const u32 *)&caicos_sysls_enable;

sys/dev/drm/radeon/btc_dpm.c

1601

p = (const u32 *)&barts_sysls_disable;

sys/dev/drm/radeon/btc_dpm.c

1604

p = (const u32 *)&turks_sysls_disable;

sys/dev/drm/radeon/btc_dpm.c

1607

p = (const u32 *)&caicos_sysls_disable;

sys/dev/drm/radeon/btc_dpm.c

162

#define BARTS_CGCG_CGLS_DISABLE_LENGTH sizeof(barts_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

164

static const u32 barts_cgcg_cgls_enable[] =

sys/dev/drm/radeon/btc_dpm.c

1766

u32 val;

sys/dev/drm/radeon/btc_dpm.c

1809

u32 val;

sys/dev/drm/radeon/btc_dpm.c

1918

u32 tmp;

sys/dev/drm/radeon/btc_dpm.c

1977

u32 i;

sys/dev/drm/radeon/btc_dpm.c

2066

u32 tmp;

sys/dev/drm/radeon/btc_dpm.c

2082

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/drm/radeon/btc_dpm.c

2083

u32 switch_limit = pi->mem_gddr5 ? 450 : 100;

sys/dev/drm/radeon/btc_dpm.c

2098

u32 mclk, sclk;

sys/dev/drm/radeon/btc_dpm.c

217

#define BARTS_CGCG_CGLS_ENABLE_LENGTH sizeof(barts_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

219

static const u32 barts_mgcg_default[] =

sys/dev/drm/radeon/btc_dpm.c

2737

u32 current_index =

sys/dev/drm/radeon/btc_dpm.c

2756

u32 btc_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/btc_dpm.c

2762

u32 current_index =

sys/dev/drm/radeon/btc_dpm.c

2779

u32 btc_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/btc_dpm.c

2785

u32 current_index =

sys/dev/drm/radeon/btc_dpm.c

2802

u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/btc_dpm.c

2813

u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/btc_dpm.c

366

#define BARTS_MGCG_DEFAULT_LENGTH sizeof(barts_mgcg_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

368

static const u32 barts_mgcg_disable[] =

sys/dev/drm/radeon/btc_dpm.c

381

#define BARTS_MGCG_DISABLE_LENGTH sizeof(barts_mgcg_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

383

static const u32 barts_mgcg_enable[] =

sys/dev/drm/radeon/btc_dpm.c

396

#define BARTS_MGCG_ENABLE_LENGTH sizeof(barts_mgcg_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

399

static const u32 caicos_cgcg_cgls_default[] =

sys/dev/drm/radeon/btc_dpm.c

450

#define CAICOS_CGCG_CGLS_DEFAULT_LENGTH sizeof(caicos_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

452

static const u32 caicos_cgcg_cgls_disable[] =

sys/dev/drm/radeon/btc_dpm.c

505

#define CAICOS_CGCG_CGLS_DISABLE_LENGTH sizeof(caicos_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

507

static const u32 caicos_cgcg_cgls_enable[] =

sys/dev/drm/radeon/btc_dpm.c

55

static const u32 barts_cgcg_cgls_default[] =

sys/dev/drm/radeon/btc_dpm.c

560

#define CAICOS_CGCG_CGLS_ENABLE_LENGTH sizeof(caicos_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

562

static const u32 caicos_mgcg_default[] =

sys/dev/drm/radeon/btc_dpm.c

640

#define CAICOS_MGCG_DEFAULT_LENGTH sizeof(caicos_mgcg_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

642

static const u32 caicos_mgcg_disable[] =

sys/dev/drm/radeon/btc_dpm.c

655

#define CAICOS_MGCG_DISABLE_LENGTH sizeof(caicos_mgcg_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

657

static const u32 caicos_mgcg_enable[] =

sys/dev/drm/radeon/btc_dpm.c

670

#define CAICOS_MGCG_ENABLE_LENGTH sizeof(caicos_mgcg_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

673

static const u32 turks_cgcg_cgls_default[] =

sys/dev/drm/radeon/btc_dpm.c

724

#define TURKS_CGCG_CGLS_DEFAULT_LENGTH sizeof(turks_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

726

static const u32 turks_cgcg_cgls_disable[] =

sys/dev/drm/radeon/btc_dpm.c

779

#define TURKS_CGCG_CGLS_DISABLE_LENGTH sizeof(turks_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

781

static const u32 turks_cgcg_cgls_enable[] =

sys/dev/drm/radeon/btc_dpm.c

834

#define TURKS_CGCG_CGLS_ENABLE_LENGTH sizeof(turks_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

837

static const u32 turks_mgcg_default[] =

sys/dev/drm/radeon/btc_dpm.c

935

#define TURKS_MGCG_DEFAULT_LENGTH sizeof(turks_mgcg_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

937

static const u32 turks_mgcg_disable[] =

sys/dev/drm/radeon/btc_dpm.c

950

#define TURKS_MGCG_DISABLE_LENGTH sizeof(turks_mgcg_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

952

static const u32 turks_mgcg_enable[] =

sys/dev/drm/radeon/btc_dpm.c

965

#define TURKS_MGCG_ENABLE_LENGTH sizeof(turks_mgcg_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

974

static const u32 barts_sysls_default[] =

sys/dev/drm/radeon/btc_dpm.c

993

#define BARTS_SYSLS_DEFAULT_LENGTH sizeof(barts_sysls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/btc_dpm.c

995

static const u32 barts_sysls_disable[] =

sys/dev/drm/radeon/btc_dpm.h

36

extern u32 btc_valid_sclk[40];

sys/dev/drm/radeon/btc_dpm.h

40

const u32 *sequence, u32 count);

sys/dev/drm/radeon/btc_dpm.h

42

const u32 max_sclk, const u32 max_mclk,

sys/dev/drm/radeon/btc_dpm.h

43

u32 *sclk, u32 *mclk);

sys/dev/drm/radeon/btc_dpm.h

48

u32 clock, u16 max_voltage, u16 *voltage);

sys/dev/drm/radeon/btc_dpm.h

50

u32 *max_clock);

sys/dev/drm/radeon/cayman_blit_shaders.c

320

const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);

sys/dev/drm/radeon/cayman_blit_shaders.c

41

const u32 cayman_default_state[] =

sys/dev/drm/radeon/cayman_blit_shaders.h

28

extern const u32 cayman_default_state[];

sys/dev/drm/radeon/cayman_blit_shaders.h

30

extern const u32 cayman_default_size;

sys/dev/drm/radeon/ci_dpm.c

1110

u32 *speed)

sys/dev/drm/radeon/ci_dpm.c

1112

u32 duty, duty100;

sys/dev/drm/radeon/ci_dpm.c

1126

*speed = (u32)tmp64;

sys/dev/drm/radeon/ci_dpm.c

1135

u32 speed)

sys/dev/drm/radeon/ci_dpm.c

1137

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1138

u32 duty, duty100;

sys/dev/drm/radeon/ci_dpm.c

1158

duty = (u32)tmp64;

sys/dev/drm/radeon/ci_dpm.c

1167

void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)

sys/dev/drm/radeon/ci_dpm.c

1183

u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)

sys/dev/drm/radeon/ci_dpm.c

1186

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1197

u32 *speed)

sys/dev/drm/radeon/ci_dpm.c

1199

u32 tach_period;

sys/dev/drm/radeon/ci_dpm.c

1200

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/ci_dpm.c

1218

u32 speed)

sys/dev/drm/radeon/ci_dpm.c

1220

u32 tach_period, tmp;

sys/dev/drm/radeon/ci_dpm.c

1221

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/ci_dpm.c

1250

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1274

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1316

u16 reg_offset, u32 *value)

sys/dev/drm/radeon/ci_dpm.c

1327

u16 reg_offset, u32 value)

sys/dev/drm/radeon/ci_dpm.c

1356

u32 low_sclk_interrupt_t = 0;

sys/dev/drm/radeon/ci_dpm.c

1365

sizeof(u32), pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1414

static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/drm/radeon/ci_dpm.c

1419

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1565

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1626

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1655

u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1671

u32 power_limit;

sys/dev/drm/radeon/ci_dpm.c

1674

power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);

sys/dev/drm/radeon/ci_dpm.c

1676

power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);

sys/dev/drm/radeon/ci_dpm.c

1693

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

171

u32 arb_freq_src, u32 arb_freq_dest);

sys/dev/drm/radeon/ci_dpm.c

1713

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/radeon/ci_dpm.c

1720

PPSMC_Msg msg, u32 *parameter)

sys/dev/drm/radeon/ci_dpm.c

1732

static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)

sys/dev/drm/radeon/ci_dpm.c

1746

static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)

sys/dev/drm/radeon/ci_dpm.c

176

static int ci_set_power_limit(struct radeon_device *rdev, u32 n);

sys/dev/drm/radeon/ci_dpm.c

1760

static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)

sys/dev/drm/radeon/ci_dpm.c

1774

static int ci_set_power_limit(struct radeon_device *rdev, u32 n)

sys/dev/drm/radeon/ci_dpm.c

178

u32 target_tdp);

sys/dev/drm/radeon/ci_dpm.c

1789

u32 target_tdp)

sys/dev/drm/radeon/ci_dpm.c

1805

static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)

sys/dev/drm/radeon/ci_dpm.c

1807

u32 sclk_freq;

sys/dev/drm/radeon/ci_dpm.c

1818

static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)

sys/dev/drm/radeon/ci_dpm.c

1820

u32 mclk_freq;

sys/dev/drm/radeon/ci_dpm.c

183

PPSMC_Msg msg, u32 parameter);

sys/dev/drm/radeon/ci_dpm.c

1853

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

1941

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

1952

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

2021

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2022

u32 pre_vbi_time_in_us;

sys/dev/drm/radeon/ci_dpm.c

2023

u32 frame_time_in_us;

sys/dev/drm/radeon/ci_dpm.c

2024

u32 ref_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

2025

u32 refresh_rate = r600_dpm_get_vrefresh(rdev);

sys/dev/drm/radeon/ci_dpm.c

2026

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/drm/radeon/ci_dpm.c

2056

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2082

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2093

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2111

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2151

u32 i;

sys/dev/drm/radeon/ci_dpm.c

2341

static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/drm/radeon/ci_dpm.c

2345

u32 i = 0;

sys/dev/drm/radeon/ci_dpm.c

2375

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/radeon/ci_dpm.c

2379

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/radeon/ci_dpm.c

2392

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/radeon/ci_dpm.c

2396

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/radeon/ci_dpm.c

2415

u32 sclk,

sys/dev/drm/radeon/ci_dpm.c

2416

u32 *phase_shedding)

sys/dev/drm/radeon/ci_dpm.c

2432

u32 mclk,

sys/dev/drm/radeon/ci_dpm.c

2433

u32 *phase_shedding)

sys/dev/drm/radeon/ci_dpm.c

2450

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2467

u32 clock, u32 *voltage)

sys/dev/drm/radeon/ci_dpm.c

2469

u32 i = 0;

sys/dev/drm/radeon/ci_dpm.c

2487

u32 sclk, u32 min_sclk_in_sr)

sys/dev/drm/radeon/ci_dpm.c

2489

u32 i;

sys/dev/drm/radeon/ci_dpm.c

2490

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2491

u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?

sys/dev/drm/radeon/ci_dpm.c

2519

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2530

const u32 engine_clock,

sys/dev/drm/radeon/ci_dpm.c

2531

const u32 memory_clock,

sys/dev/drm/radeon/ci_dpm.c

2532

u32 *dram_timimg2)

sys/dev/drm/radeon/ci_dpm.c

2535

u32 tmp, tmp2;

sys/dev/drm/radeon/ci_dpm.c

2557

u32 sclk,

sys/dev/drm/radeon/ci_dpm.c

2558

u32 mclk,

sys/dev/drm/radeon/ci_dpm.c

2561

u32 dram_timing;

sys/dev/drm/radeon/ci_dpm.c

2562

u32 dram_timing2;

sys/dev/drm/radeon/ci_dpm.c

2563

u32 burst_time;

sys/dev/drm/radeon/ci_dpm.c

2584

u32 i, j;

sys/dev/drm/radeon/ci_dpm.c

2625

u32 level = 0;

sys/dev/drm/radeon/ci_dpm.c

2644

static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)

sys/dev/drm/radeon/ci_dpm.c

2646

u32 i;

sys/dev/drm/radeon/ci_dpm.c

2647

u32 mask_value = 0;

sys/dev/drm/radeon/ci_dpm.c

2665

u32 i;

sys/dev/drm/radeon/ci_dpm.c

2685

u32 count;

sys/dev/drm/radeon/ci_dpm.c

2728

u32 count;

sys/dev/drm/radeon/ci_dpm.c

273

u32 i;

sys/dev/drm/radeon/ci_dpm.c

2761

u32 count;

sys/dev/drm/radeon/ci_dpm.c

2793

u32 count;

sys/dev/drm/radeon/ci_dpm.c

2823

u32 memory_clock,

sys/dev/drm/radeon/ci_dpm.c

2829

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/ci_dpm.c

2830

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ci_dpm.c

2831

u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

2832

u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

2833

u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

2834

u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/radeon/ci_dpm.c

2835

u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.c

2836

u32 mpll_ss1 = pi->clock_registers.mpll_ss1;

sys/dev/drm/radeon/ci_dpm.c

2837

u32 mpll_ss2 = pi->clock_registers.mpll_ss2;

sys/dev/drm/radeon/ci_dpm.c

2863

u32 freq_nom;

sys/dev/drm/radeon/ci_dpm.c

2864

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

2865

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

2876

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/drm/radeon/ci_dpm.c

2877

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/drm/radeon/ci_dpm.c

2910

u32 memory_clock,

sys/dev/drm/radeon/ci_dpm.c

300

u32 i;

sys/dev/drm/radeon/ci_dpm.c

3029

u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

3030

u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.c

3031

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/ci_dpm.c

3032

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ci_dpm.c

3194

u32 engine_clock,

sys/dev/drm/radeon/ci_dpm.c

3199

u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/ci_dpm.c

3200

u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/ci_dpm.c

3201

u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/radeon/ci_dpm.c

3202

u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ci_dpm.c

3203

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

3204

u32 reference_divider;

sys/dev/drm/radeon/ci_dpm.c

3205

u32 fbdiv;

sys/dev/drm/radeon/ci_dpm.c

3223

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/ci_dpm.c

3227

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/ci_dpm.c

3228

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/radeon/ci_dpm.c

3250

u32 engine_clock,

sys/dev/drm/radeon/ci_dpm.c

3314

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/radeon/ci_dpm.c

3316

u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *

sys/dev/drm/radeon/ci_dpm.c

3319

u32 i, ret;

sys/dev/drm/radeon/ci_dpm.c

3361

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/radeon/ci_dpm.c

3363

u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *

sys/dev/drm/radeon/ci_dpm.c

3366

u32 i, ret;

sys/dev/drm/radeon/ci_dpm.c

3410

u32 count)

sys/dev/drm/radeon/ci_dpm.c

3412

u32 i;

sys/dev/drm/radeon/ci_dpm.c

3420

u32 index, u32 pcie_gen, u32 pcie_lanes)

sys/dev/drm/radeon/ci_dpm.c

3484

u32 i;

sys/dev/drm/radeon/ci_dpm.c

349

(u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,

sys/dev/drm/radeon/ci_dpm.c

3574

u32 value, u32 *boot_level)

sys/dev/drm/radeon/ci_dpm.c

3576

u32 i;

sys/dev/drm/radeon/ci_dpm.c

3665

(u32 *)&pi->smc_state_table.GraphicsBootLevel);

sys/dev/drm/radeon/ci_dpm.c

3669

(u32 *)&pi->smc_state_table.MemoryBootLevel);

sys/dev/drm/radeon/ci_dpm.c

3739

u32 low_limit, u32 high_limit)

sys/dev/drm/radeon/ci_dpm.c

3741

u32 i;

sys/dev/drm/radeon/ci_dpm.c

3753

u32 speed_low, u32 lanes_low,

sys/dev/drm/radeon/ci_dpm.c

3754

u32 speed_high, u32 lanes_high)

sys/dev/drm/radeon/ci_dpm.c

3758

u32 i, j;

sys/dev/drm/radeon/ci_dpm.c

3788

u32 high_limit_count;

sys/dev/drm/radeon/ci_dpm.c

3823

u32 requested_voltage = 0;

sys/dev/drm/radeon/ci_dpm.c

3824

u32 i;

sys/dev/drm/radeon/ci_dpm.c

3895

u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;

sys/dev/drm/radeon/ci_dpm.c

3897

u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;

sys/dev/drm/radeon/ci_dpm.c

3898

u32 i;

sys/dev/drm/radeon/ci_dpm.c

3936

u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;

sys/dev/drm/radeon/ci_dpm.c

3937

u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;

sys/dev/drm/radeon/ci_dpm.c

4114

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

4136

u32 min_evclk = 30000; /* ??? */

sys/dev/drm/radeon/ci_dpm.c

4154

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

4187

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

4228

static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,

sys/dev/drm/radeon/ci_dpm.c

4229

u32 level_mask)

sys/dev/drm/radeon/ci_dpm.c

4231

u32 level = 0;

sys/dev/drm/radeon/ci_dpm.c

4244

u32 tmp, levels, i;

sys/dev/drm/radeon/ci_dpm.c

4375

u32 temp_reg;

sys/dev/drm/radeon/ci_dpm.c

4531

u32 i;

sys/dev/drm/radeon/ci_dpm.c

4572

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

4721

u32 i, j;

sys/dev/drm/radeon/ci_dpm.c

474

u32 pm_fuse_table_offset;

sys/dev/drm/radeon/ci_dpm.c

4740

u32 num_entries, u32 valid_flag)

sys/dev/drm/radeon/ci_dpm.c

4742

u32 i, j;

sys/dev/drm/radeon/ci_dpm.c

4753

const u32 memory_clock,

sys/dev/drm/radeon/ci_dpm.c

4757

u32 i = 0;

sys/dev/drm/radeon/ci_dpm.c

4776

u32 i;

sys/dev/drm/radeon/ci_dpm.c

4825

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

4849

u32 speed_cntl = 0;

sys/dev/drm/radeon/ci_dpm.c

4859

u32 link_width = 0;

sys/dev/drm/radeon/ci_dpm.c

4996

u32 leakage_index;

sys/dev/drm/radeon/ci_dpm.c

5010

u32 leakage_index;

sys/dev/drm/radeon/ci_dpm.c

5023

u32 i;

sys/dev/drm/radeon/ci_dpm.c

5034

u32 i;

sys/dev/drm/radeon/ci_dpm.c

5045

u32 i;

sys/dev/drm/radeon/ci_dpm.c

5056

u32 i;

sys/dev/drm/radeon/ci_dpm.c

5067

u32 i;

sys/dev/drm/radeon/ci_dpm.c

5087

u32 i;

sys/dev/drm/radeon/ci_dpm.c

5128

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

521

u32 data;

sys/dev/drm/radeon/ci_dpm.c

564

u32 data;

sys/dev/drm/radeon/ci_dpm.c

565

u32 cache = 0;

sys/dev/drm/radeon/ci_dpm.c

5655

u32 sclk, mclk;

sys/dev/drm/radeon/ci_dpm.c

5891

u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

5989

u32 sclk = ci_get_average_sclk_freq(rdev);

sys/dev/drm/radeon/ci_dpm.c

5990

u32 mclk = ci_get_average_mclk_freq(rdev);

sys/dev/drm/radeon/ci_dpm.c

6016

u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/ci_dpm.c

6018

u32 sclk = ci_get_average_sclk_freq(rdev);

sys/dev/drm/radeon/ci_dpm.c

6023

u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/ci_dpm.c

6025

u32 mclk = ci_get_average_mclk_freq(rdev);

sys/dev/drm/radeon/ci_dpm.c

6030

u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/ci_dpm.c

6041

u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/ci_dpm.c

665

u32 default_pwr_limit =

sys/dev/drm/radeon/ci_dpm.c

666

(u32)(cac_tdp_table->maximum_power_delivery_limit * 256);

sys/dev/drm/radeon/ci_dpm.c

750

ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);

sys/dev/drm/radeon/ci_dpm.c

771

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/drm/radeon/ci_dpm.c

772

u32 switch_limit = pi->mem_gddr5 ? 450 : 300;

sys/dev/drm/radeon/ci_dpm.c

836

u32 sclk, mclk;

sys/dev/drm/radeon/ci_dpm.c

909

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

943

u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/radeon/ci_dpm.c

969

static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)

sys/dev/drm/radeon/ci_dpm.c

972

u32 tmp;

sys/dev/drm/radeon/ci_dpm.c

995

u32 duty100;

sys/dev/drm/radeon/ci_dpm.c

996

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/drm/radeon/ci_dpm.c

998

u32 reference_clock, tmp;

sys/dev/drm/radeon/ci_dpm.h

106

u32 uvd_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

107

u32 vce_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

108

u32 acp_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

109

u32 samu_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

110

u32 sclk_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

111

u32 mclk_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

112

u32 pcie_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

120

u32 sclk_bootup_value;

sys/dev/drm/radeon/ci_dpm.h

121

u32 mclk_bootup_value;

sys/dev/drm/radeon/ci_dpm.h

127

u32 cg_spll_func_cntl;

sys/dev/drm/radeon/ci_dpm.h

128

u32 cg_spll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.h

129

u32 cg_spll_func_cntl_3;

sys/dev/drm/radeon/ci_dpm.h

130

u32 cg_spll_func_cntl_4;

sys/dev/drm/radeon/ci_dpm.h

131

u32 cg_spll_spread_spectrum;

sys/dev/drm/radeon/ci_dpm.h

132

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ci_dpm.h

133

u32 dll_cntl;

sys/dev/drm/radeon/ci_dpm.h

134

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ci_dpm.h

135

u32 mpll_ad_func_cntl;

sys/dev/drm/radeon/ci_dpm.h

136

u32 mpll_dq_func_cntl;

sys/dev/drm/radeon/ci_dpm.h

137

u32 mpll_func_cntl;

sys/dev/drm/radeon/ci_dpm.h

138

u32 mpll_func_cntl_1;

sys/dev/drm/radeon/ci_dpm.h

139

u32 mpll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.h

140

u32 mpll_ss1;

sys/dev/drm/radeon/ci_dpm.h

141

u32 mpll_ss2;

sys/dev/drm/radeon/ci_dpm.h

168

u32 offset;

sys/dev/drm/radeon/ci_dpm.h

169

u32 mask;

sys/dev/drm/radeon/ci_dpm.h

170

u32 shift;

sys/dev/drm/radeon/ci_dpm.h

171

u32 value;

sys/dev/drm/radeon/ci_dpm.h

182

u32 display_cac;

sys/dev/drm/radeon/ci_dpm.h

183

u32 bapm_temp_gradient;

sys/dev/drm/radeon/ci_dpm.h

195

u32 voltage_control;

sys/dev/drm/radeon/ci_dpm.h

196

u32 mvdd_control;

sys/dev/drm/radeon/ci_dpm.h

197

u32 vddci_control;

sys/dev/drm/radeon/ci_dpm.h

198

u32 active_auto_throttle_sources;

sys/dev/drm/radeon/ci_dpm.h

210

u32 mclk_strobe_mode_threshold;

sys/dev/drm/radeon/ci_dpm.h

211

u32 mclk_stutter_mode_threshold;

sys/dev/drm/radeon/ci_dpm.h

212

u32 mclk_edc_enable_threshold;

sys/dev/drm/radeon/ci_dpm.h

213

u32 mclk_edc_wr_enable_threshold;

sys/dev/drm/radeon/ci_dpm.h

216

u32 sram_end;

sys/dev/drm/radeon/ci_dpm.h

217

u32 dpm_table_start;

sys/dev/drm/radeon/ci_dpm.h

218

u32 soft_regs_start;

sys/dev/drm/radeon/ci_dpm.h

219

u32 mc_reg_table_start;

sys/dev/drm/radeon/ci_dpm.h

220

u32 fan_table_start;

sys/dev/drm/radeon/ci_dpm.h

221

u32 arb_table_start;

sys/dev/drm/radeon/ci_dpm.h

232

u32 power_containment_features;

sys/dev/drm/radeon/ci_dpm.h

234

u32 dte_tj_offset;

sys/dev/drm/radeon/ci_dpm.h

238

u32 need_update_smu7_dpm_table;

sys/dev/drm/radeon/ci_dpm.h

239

u32 sclk_dpm_key_disabled;

sys/dev/drm/radeon/ci_dpm.h

240

u32 mclk_dpm_key_disabled;

sys/dev/drm/radeon/ci_dpm.h

241

u32 pcie_dpm_key_disabled;

sys/dev/drm/radeon/ci_dpm.h

242

u32 thermal_sclk_dpm_enabled;

sys/dev/drm/radeon/ci_dpm.h

247

u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];

sys/dev/drm/radeon/ci_dpm.h

248

u32 mclk_activity_target;

sys/dev/drm/radeon/ci_dpm.h

249

u32 low_sclk_interrupt_t;

sys/dev/drm/radeon/ci_dpm.h

250

u32 last_mclk_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.h

251

u32 sys_pcie_mask;

sys/dev/drm/radeon/ci_dpm.h

295

u32 t_min;

sys/dev/drm/radeon/ci_dpm.h

296

u32 fan_ctrl_default_mode;

sys/dev/drm/radeon/ci_dpm.h

325

u32 smc_start_address,

sys/dev/drm/radeon/ci_dpm.h

326

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/radeon/ci_dpm.h

334

int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);

sys/dev/drm/radeon/ci_dpm.h

336

u32 smc_address, u32 *value, u32 limit);

sys/dev/drm/radeon/ci_dpm.h

338

u32 smc_address, u32 value, u32 limit);

sys/dev/drm/radeon/ci_dpm.h

39

u32 mclk;

sys/dev/drm/radeon/ci_dpm.h

40

u32 sclk;

sys/dev/drm/radeon/ci_dpm.h

48

u32 sclk_t;

sys/dev/drm/radeon/ci_dpm.h

54

u32 value;

sys/dev/drm/radeon/ci_dpm.h

55

u32 param1;

sys/dev/drm/radeon/ci_dpm.h

63

u32 count;

sys/dev/drm/radeon/ci_dpm.h

77

u32 mclk_max;

sys/dev/drm/radeon/ci_dpm.h

78

u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/ci_dpm.h

92

u32 cg_ulv_parameter;

sys/dev/drm/radeon/ci_dpm.h

93

u32 volt_change_delay;

sys/dev/drm/radeon/ci_smc.c

116

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/ci_smc.c

124

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/ci_smc.c

139

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

148

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

158

u32 pc_c = RREG32_SMC(SMC_PC_C);

sys/dev/drm/radeon/ci_smc.c

169

u32 tmp;

sys/dev/drm/radeon/ci_smc.c

186

int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)

sys/dev/drm/radeon/ci_smc.c

189

u32 ucode_start_address;

sys/dev/drm/radeon/ci_smc.c

190

u32 ucode_size;

sys/dev/drm/radeon/ci_smc.c

192

u32 data;

sys/dev/drm/radeon/ci_smc.c

247

u32 smc_address, u32 *value, u32 limit)

sys/dev/drm/radeon/ci_smc.c

262

u32 smc_address, u32 value, u32 limit)

sys/dev/drm/radeon/ci_smc.c

34

u32 smc_address, u32 limit)

sys/dev/drm/radeon/ci_smc.c

48

u32 smc_start_address,

sys/dev/drm/radeon/ci_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/radeon/ci_smc.c

52

u32 data, original_data;

sys/dev/drm/radeon/ci_smc.c

53

u32 addr;

sys/dev/drm/radeon/ci_smc.c

54

u32 extra_shift;

sys/dev/drm/radeon/cik.c

1029

static const u32 bonaire_golden_spm_registers[] =

sys/dev/drm/radeon/cik.c

1034

static const u32 bonaire_golden_common_registers[] =

sys/dev/drm/radeon/cik.c

1042

static const u32 bonaire_golden_registers[] =

sys/dev/drm/radeon/cik.c

1087

static const u32 bonaire_mgcg_cgcg_init[] =

sys/dev/drm/radeon/cik.c

1173

static const u32 spectre_golden_spm_registers[] =

sys/dev/drm/radeon/cik.c

1178

static const u32 spectre_golden_common_registers[] =

sys/dev/drm/radeon/cik.c

1186

static const u32 spectre_golden_registers[] =

sys/dev/drm/radeon/cik.c

1215

static const u32 spectre_mgcg_cgcg_init[] =

sys/dev/drm/radeon/cik.c

123

static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);

sys/dev/drm/radeon/cik.c

1306

static const u32 kalindi_golden_spm_registers[] =

sys/dev/drm/radeon/cik.c

1311

static const u32 kalindi_golden_common_registers[] =

sys/dev/drm/radeon/cik.c

1319

static const u32 kalindi_golden_registers[] =

sys/dev/drm/radeon/cik.c

1353

static const u32 kalindi_mgcg_cgcg_init[] =

sys/dev/drm/radeon/cik.c

1412

static const u32 hawaii_golden_spm_registers[] =

sys/dev/drm/radeon/cik.c

1417

static const u32 hawaii_golden_common_registers[] =

sys/dev/drm/radeon/cik.c

1426

static const u32 hawaii_golden_registers[] =

sys/dev/drm/radeon/cik.c

145

u32 reg, u32 *val)

sys/dev/drm/radeon/cik.c

1466

static const u32 hawaii_mgcg_cgcg_init[] =

sys/dev/drm/radeon/cik.c

1577

static const u32 godavari_golden_registers[] =

sys/dev/drm/radeon/cik.c

1620

(const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1623

(const u32)ARRAY_SIZE(bonaire_golden_registers));

sys/dev/drm/radeon/cik.c

1626

(const u32)ARRAY_SIZE(bonaire_golden_common_registers));

sys/dev/drm/radeon/cik.c

1629

(const u32)ARRAY_SIZE(bonaire_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1634

(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1637

(const u32)ARRAY_SIZE(kalindi_golden_registers));

sys/dev/drm/radeon/cik.c

1640

(const u32)ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/drm/radeon/cik.c

1643

(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1648

(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1651

(const u32)ARRAY_SIZE(godavari_golden_registers));

sys/dev/drm/radeon/cik.c

1654

(const u32)ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/drm/radeon/cik.c

1657

(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1662

(const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1665

(const u32)ARRAY_SIZE(spectre_golden_registers));

sys/dev/drm/radeon/cik.c

1668

(const u32)ARRAY_SIZE(spectre_golden_common_registers));

sys/dev/drm/radeon/cik.c

1671

(const u32)ARRAY_SIZE(spectre_golden_spm_registers));

sys/dev/drm/radeon/cik.c

1676

(const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));

sys/dev/drm/radeon/cik.c

1679

(const u32)ARRAY_SIZE(hawaii_golden_registers));

sys/dev/drm/radeon/cik.c

1682

(const u32)ARRAY_SIZE(hawaii_golden_common_registers));

sys/dev/drm/radeon/cik.c

1685

(const u32)ARRAY_SIZE(hawaii_golden_spm_registers));

sys/dev/drm/radeon/cik.c

170

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/cik.c

1700

u32 cik_get_xclk(struct radeon_device *rdev)

sys/dev/drm/radeon/cik.c

1702

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/cik.c

1723

u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)

sys/dev/drm/radeon/cik.c

173

u32 r;

sys/dev/drm/radeon/cik.c

1743

void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)

sys/dev/drm/radeon/cik.c

1754

static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =

sys/dev/drm/radeon/cik.c

1796

static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =

sys/dev/drm/radeon/cik.c

182

void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/cik.c

1837

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/radeon/cik.c

1839

u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |

sys/dev/drm/radeon/cik.c

1859

u32 running, tmp;

sys/dev/drm/radeon/cik.c

1860

u32 *io_mc_regs = NULL;

sys/dev/drm/radeon/cik.c

1884

io_mc_regs = (u32 *)&bonaire_io_mc_regs;

sys/dev/drm/radeon/cik.c

1888

io_mc_regs = (u32 *)&hawaii_io_mc_regs;

sys/dev/drm/radeon/cik.c

195

u32 temp;

sys/dev/drm/radeon/cik.c

214

u32 temp;

sys/dev/drm/radeon/cik.c

232

u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/cik.c

2347

u32 *tile = rdev->config.cik.tile_mode_array;

sys/dev/drm/radeon/cik.c

2348

u32 *macrotile = rdev->config.cik.macrotile_mode_array;

sys/dev/drm/radeon/cik.c

2349

const u32 num_tile_mode_states =

sys/dev/drm/radeon/cik.c

235

u32 r;

sys/dev/drm/radeon/cik.c

2351

const u32 num_secondary_tile_mode_states =

sys/dev/drm/radeon/cik.c

2353

u32 reg_offset, split_equal_to_row_size;

sys/dev/drm/radeon/cik.c

2354

u32 num_pipe_configs;

sys/dev/drm/radeon/cik.c

2355

u32 num_rbs = rdev->config.cik.max_backends_per_se *

sys/dev/drm/radeon/cik.c

245

void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/cik.c

257

static const u32 spectre_rlc_save_restore_register_list[] =

sys/dev/drm/radeon/cik.c

3052

u32 se_num, u32 sh_num)

sys/dev/drm/radeon/cik.c

3054

u32 data = INSTANCE_BROADCAST_WRITES;

sys/dev/drm/radeon/cik.c

3075

static u32 cik_create_bitmask(u32 bit_width)

sys/dev/drm/radeon/cik.c

3077

u32 i, mask = 0;

sys/dev/drm/radeon/cik.c

3097

static u32 cik_get_rb_disabled(struct radeon_device *rdev,

sys/dev/drm/radeon/cik.c

3098

u32 max_rb_num_per_se,

sys/dev/drm/radeon/cik.c

3099

u32 sh_per_se)

sys/dev/drm/radeon/cik.c

3101

u32 data, mask;

sys/dev/drm/radeon/cik.c

3128

u32 se_num, u32 sh_per_se,

sys/dev/drm/radeon/cik.c

3129

u32 max_rb_num_per_se)

sys/dev/drm/radeon/cik.c

3132

u32 data, mask;

sys/dev/drm/radeon/cik.c

3133

u32 disabled_rbs = 0;

sys/dev/drm/radeon/cik.c

3134

u32 enabled_rbs = 0;

sys/dev/drm/radeon/cik.c

3196

u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);

sys/dev/drm/radeon/cik.c

3197

u32 mc_shared_chmap, mc_arb_ramcfg;

sys/dev/drm/radeon/cik.c

3198

u32 hdp_host_path_cntl;

sys/dev/drm/radeon/cik.c

3199

u32 tmp;

sys/dev/drm/radeon/cik.c

3524

u32 ref_and_mask;

sys/dev/drm/radeon/cik.c

3680

u32 size_in_bytes, cur_size_in_bytes, control;

sys/dev/drm/radeon/cik.c

3749

u32 header, control = INDIRECT_BUFFER_VALID;

sys/dev/drm/radeon/cik.c

3758

u32 next_rptr;

sys/dev/drm/radeon/cik.c

3927

u32 fw_size;

sys/dev/drm/radeon/cik.c

4075

u32 tmp;

sys/dev/drm/radeon/cik.c

4076

u32 rb_bufsz;

sys/dev/drm/radeon/cik.c

4139

u32 cik_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/cik.c

4142

u32 rptr;

sys/dev/drm/radeon/cik.c

4152

u32 cik_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/cik.c

4165

u32 cik_compute_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/cik.c

4168

u32 rptr;

sys/dev/drm/radeon/cik.c

4183

u32 cik_compute_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/cik.c

4186

u32 wptr;

sys/dev/drm/radeon/cik.c

4213

u32 j, tmp;

sys/dev/drm/radeon/cik.c

4285

u32 fw_size;

sys/dev/drm/radeon/cik.c

4405

u32 *hpd;

sys/dev/drm/radeon/cik.c

4460

u32 cp_mqd_base_addr;

sys/dev/drm/radeon/cik.c

4461

u32 cp_mqd_base_addr_hi;

sys/dev/drm/radeon/cik.c

4462

u32 cp_hqd_active;

sys/dev/drm/radeon/cik.c

4463

u32 cp_hqd_vmid;

sys/dev/drm/radeon/cik.c

4464

u32 cp_hqd_persistent_state;

sys/dev/drm/radeon/cik.c

4465

u32 cp_hqd_pipe_priority;

sys/dev/drm/radeon/cik.c

4466

u32 cp_hqd_queue_priority;

sys/dev/drm/radeon/cik.c

4467

u32 cp_hqd_quantum;

sys/dev/drm/radeon/cik.c

4468

u32 cp_hqd_pq_base;

sys/dev/drm/radeon/cik.c

4469

u32 cp_hqd_pq_base_hi;

sys/dev/drm/radeon/cik.c

4470

u32 cp_hqd_pq_rptr;

sys/dev/drm/radeon/cik.c

4471

u32 cp_hqd_pq_rptr_report_addr;

sys/dev/drm/radeon/cik.c

4472

u32 cp_hqd_pq_rptr_report_addr_hi;

sys/dev/drm/radeon/cik.c

4473

u32 cp_hqd_pq_wptr_poll_addr;

sys/dev/drm/radeon/cik.c

4474

u32 cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/drm/radeon/cik.c

4475

u32 cp_hqd_pq_doorbell_control;

sys/dev/drm/radeon/cik.c

4476

u32 cp_hqd_pq_wptr;

sys/dev/drm/radeon/cik.c

4477

u32 cp_hqd_pq_control;

sys/dev/drm/radeon/cik.c

4478

u32 cp_hqd_ib_base_addr;

sys/dev/drm/radeon/cik.c

4479

u32 cp_hqd_ib_base_addr_hi;

sys/dev/drm/radeon/cik.c

4480

u32 cp_hqd_ib_rptr;

sys/dev/drm/radeon/cik.c

4481

u32 cp_hqd_ib_control;

sys/dev/drm/radeon/cik.c

4482

u32 cp_hqd_iq_timer;

sys/dev/drm/radeon/cik.c

4483

u32 cp_hqd_iq_rptr;

sys/dev/drm/radeon/cik.c

4484

u32 cp_hqd_dequeue_request;

sys/dev/drm/radeon/cik.c

4485

u32 cp_hqd_dma_offload;

sys/dev/drm/radeon/cik.c

4486

u32 cp_hqd_sema_cmd;

sys/dev/drm/radeon/cik.c

4487

u32 cp_hqd_msg_type;

sys/dev/drm/radeon/cik.c

4488

u32 cp_hqd_atomic0_preop_lo;

sys/dev/drm/radeon/cik.c

4489

u32 cp_hqd_atomic0_preop_hi;

sys/dev/drm/radeon/cik.c

4490

u32 cp_hqd_atomic1_preop_lo;

sys/dev/drm/radeon/cik.c

4491

u32 cp_hqd_atomic1_preop_hi;

sys/dev/drm/radeon/cik.c

4492

u32 cp_hqd_hq_scheduler0;

sys/dev/drm/radeon/cik.c

4493

u32 cp_hqd_hq_scheduler1;

sys/dev/drm/radeon/cik.c

4494

u32 cp_mqd_control;

sys/dev/drm/radeon/cik.c

4499

u32 header;

sys/dev/drm/radeon/cik.c

4500

u32 dispatch_initiator;

sys/dev/drm/radeon/cik.c

4501

u32 dimensions[3];

sys/dev/drm/radeon/cik.c

4502

u32 start_idx[3];

sys/dev/drm/radeon/cik.c

4503

u32 num_threads[3];

sys/dev/drm/radeon/cik.c

4504

u32 pipeline_stat_enable;

sys/dev/drm/radeon/cik.c

4505

u32 perf_counter_enable;

sys/dev/drm/radeon/cik.c

4506

u32 pgm[2];

sys/dev/drm/radeon/cik.c

4507

u32 tba[2];

sys/dev/drm/radeon/cik.c

4508

u32 tma[2];

sys/dev/drm/radeon/cik.c

4509

u32 pgm_rsrc[2];

sys/dev/drm/radeon/cik.c

4510

u32 vmid;

sys/dev/drm/radeon/cik.c

4511

u32 resource_limits;

sys/dev/drm/radeon/cik.c

4512

u32 static_thread_mgmt01[2];

sys/dev/drm/radeon/cik.c

4513

u32 tmp_ring_size;

sys/dev/drm/radeon/cik.c

4514

u32 static_thread_mgmt23[2];

sys/dev/drm/radeon/cik.c

4515

u32 restart[3];

sys/dev/drm/radeon/cik.c

4516

u32 thread_trace_enable;

sys/dev/drm/radeon/cik.c

4517

u32 reserved1;

sys/dev/drm/radeon/cik.c

4518

u32 user_data[16];

sys/dev/drm/radeon/cik.c

4519

u32 vgtcs_invoke_count[2];

sys/dev/drm/radeon/cik.c

4521

u32 dequeue_cntr;

sys/dev/drm/radeon/cik.c

4522

u32 interrupt_queue[64];

sys/dev/drm/radeon/cik.c

4537

u32 tmp;

sys/dev/drm/radeon/cik.c

4543

u32 *buf;

sys/dev/drm/radeon/cik.c

4868

u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/drm/radeon/cik.c

4870

u32 reset_mask = 0;

sys/dev/drm/radeon/cik.c

4871

u32 tmp;

sys/dev/drm/radeon/cik.c

4948

static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/drm/radeon/cik.c

4951

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/radeon/cik.c

4952

u32 tmp;

sys/dev/drm/radeon/cik.c

5072

u32 gmcon_reng_execute;

sys/dev/drm/radeon/cik.c

5073

u32 gmcon_misc;

sys/dev/drm/radeon/cik.c

5074

u32 gmcon_misc3;

sys/dev/drm/radeon/cik.c

5166

u32 tmp, i;

sys/dev/drm/radeon/cik.c

5237

u32 reset_mask;

sys/dev/drm/radeon/cik.c

5277

u32 reset_mask = cik_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/cik.c

5300

u32 tmp;

sys/dev/drm/radeon/cik.c

5356

u32 tmp;

sys/dev/drm/radeon/cik.c

5480

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/cik.c

5504

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/cik.c

5522

u32 tmp = RREG32(CHUB_CONTROL);

sys/dev/drm/radeon/cik.c

5677

u32 status, u32 addr, u32 mc_client)

sys/dev/drm/radeon/cik.c

5679

u32 mc_id;

sys/dev/drm/radeon/cik.c

5680

u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

sys/dev/drm/radeon/cik.c

5681

u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

sys/dev/drm/radeon/cik.c

5787

u32 tmp = RREG32(CP_INT_CNTL_RING0);

sys/dev/drm/radeon/cik.c

5798

u32 tmp;

sys/dev/drm/radeon/cik.c

5810

u32 i, j, k;

sys/dev/drm/radeon/cik.c

5811

u32 mask;

sys/dev/drm/radeon/cik.c

5833

static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)

sys/dev/drm/radeon/cik.c

5835

u32 tmp;

sys/dev/drm/radeon/cik.c

5842

static u32 cik_halt_rlc(struct radeon_device *rdev)

sys/dev/drm/radeon/cik.c

5844

u32 data, orig;

sys/dev/drm/radeon/cik.c

5849

u32 i;

sys/dev/drm/radeon/cik.c

5868

u32 tmp, i, mask;

sys/dev/drm/radeon/cik.c

5889

u32 tmp;

sys/dev/drm/radeon/cik.c

5938

u32 i, size, tmp;

sys/dev/drm/radeon/cik.c

6019

u32 data, orig, tmp, tmp2;

sys/dev/drm/radeon/cik.c

6055

u32 data, orig, tmp = 0;

sys/dev/drm/radeon/cik.c

6133

static const u32 mc_cg_registers[] =

sys/dev/drm/radeon/cik.c

6150

u32 orig, data;

sys/dev/drm/radeon/cik.c

6167

u32 orig, data;

sys/dev/drm/radeon/cik.c

6183

u32 orig, data;

sys/dev/drm/radeon/cik.c

6204

u32 orig, data;

sys/dev/drm/radeon/cik.c

6232

u32 orig, data;

sys/dev/drm/radeon/cik.c

6258

u32 orig, data;

sys/dev/drm/radeon/cik.c

6276

u32 orig, data;

sys/dev/drm/radeon/cik.c

6292

u32 orig, data;

sys/dev/drm/radeon/cik.c

6306

u32 block, bool enable)

sys/dev/drm/radeon/cik.c

6382

u32 data, orig;

sys/dev/drm/radeon/cik.c

6396

u32 data, orig;

sys/dev/drm/radeon/cik.c

6409

u32 data, orig;

sys/dev/drm/radeon/cik.c

6422

u32 data, orig;

sys/dev/drm/radeon/cik.c

6439

volatile u32 *dst_ptr;

sys/dev/drm/radeon/cik.c

6441

u32 bo_offset = 0;

sys/dev/drm/radeon/cik.c

6442

u32 table_offset, table_size;

sys/dev/drm/radeon/cik.c

6524

u32 data, orig;

sys/dev/drm/radeon/cik.c

6551

static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)

sys/dev/drm/radeon/cik.c

6553

u32 mask = 0, tmp, tmp1;

sys/dev/drm/radeon/cik.c

6576

u32 i, j, k, active_cu_number = 0;

sys/dev/drm/radeon/cik.c

6577

u32 mask, counter, cu_bitmap;

sys/dev/drm/radeon/cik.c

6578

u32 tmp = 0;

sys/dev/drm/radeon/cik.c

6610

u32 data, orig;

sys/dev/drm/radeon/cik.c

6624

u32 data, orig;

sys/dev/drm/radeon/cik.c

6640

u32 data, orig;

sys/dev/drm/radeon/cik.c

6641

u32 i;

sys/dev/drm/radeon/cik.c

6694

u32 cik_get_csb_size(struct radeon_device *rdev)

sys/dev/drm/radeon/cik.c

6696

u32 count = 0;

sys/dev/drm/radeon/cik.c

6726

void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)

sys/dev/drm/radeon/cik.c

6728

u32 count = 0, i;

sys/dev/drm/radeon/cik.c

6841

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/cik.c

6842

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/cik.c

6860

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/cik.c

6861

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/cik.c

6883

u32 tmp;

sys/dev/drm/radeon/cik.c

6966

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/drm/radeon/cik.c

704

static const u32 kalindi_rlc_save_restore_register_list[] =

sys/dev/drm/radeon/cik.c

7044

u32 cp_int_cntl;

sys/dev/drm/radeon/cik.c

7045

u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;

sys/dev/drm/radeon/cik.c

7046

u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;

sys/dev/drm/radeon/cik.c

7047

u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;

sys/dev/drm/radeon/cik.c

7048

u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;

sys/dev/drm/radeon/cik.c

7049

u32 grbm_int_cntl = 0;

sys/dev/drm/radeon/cik.c

7050

u32 dma_cntl, dma_cntl1;

sys/dev/drm/radeon/cik.c

7314

u32 tmp;

sys/dev/drm/radeon/cik.c

7508

static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)

sys/dev/drm/radeon/cik.c

7510

u32 wptr, tmp;

sys/dev/drm/radeon/cik.c

7569

u32 wptr;

sys/dev/drm/radeon/cik.c

7570

u32 rptr;

sys/dev/drm/radeon/cik.c

7571

u32 src_id, src_data, ring_id;

sys/dev/drm/radeon/cik.c

7573

u32 ring_index;

sys/dev/drm/radeon/cik.c

7577

u32 addr, status, mc_client;

sys/dev/drm/radeon/cik.c

8310

u32 nop;

sys/dev/drm/radeon/cik.c

8343

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/drm/radeon/cik.c

8347

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/drm/radeon/cik.c

8765

u32 tmp = 0;

sys/dev/drm/radeon/cik.c

8834

static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,

sys/dev/drm/radeon/cik.c

8838

u32 tmp, buffer_alloc, i;

sys/dev/drm/radeon/cik.c

8839

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/drm/radeon/cik.c

8905

static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)

sys/dev/drm/radeon/cik.c

8907

u32 tmp = RREG32(MC_SHARED_CHMAP);

sys/dev/drm/radeon/cik.c

8933

u32 dram_channels; /* number of dram channels */

sys/dev/drm/radeon/cik.c

8934

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/drm/radeon/cik.c

8935

u32 sclk; /* engine clock in kHz */

sys/dev/drm/radeon/cik.c

8936

u32 disp_clk; /* display clock in kHz */

sys/dev/drm/radeon/cik.c

8937

u32 src_width; /* viewport width */

sys/dev/drm/radeon/cik.c

8938

u32 active_time; /* active display time in ns */

sys/dev/drm/radeon/cik.c

8939

u32 blank_time; /* blank time in ns */

sys/dev/drm/radeon/cik.c

8942

u32 num_heads; /* number of active crtcs */

sys/dev/drm/radeon/cik.c

8943

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/drm/radeon/cik.c

8944

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/drm/radeon/cik.c

8945

u32 vtaps; /* vertical scaler taps */

sys/dev/drm/radeon/cik.c

8957

static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

8986

static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

9015

static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

9044

static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

9075

static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

9078

u32 dram_bandwidth = dce8_dram_bandwidth(wm);

sys/dev/drm/radeon/cik.c

9079

u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);

sys/dev/drm/radeon/cik.c

9080

u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);

sys/dev/drm/radeon/cik.c

9094

static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

9127

static u32 dce8_latency_watermark(struct dce8_wm_params *wm)

sys/dev/drm/radeon/cik.c

9130

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/drm/radeon/cik.c

9131

u32 available_bandwidth = dce8_available_bandwidth(wm);

sys/dev/drm/radeon/cik.c

9132

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/drm/radeon/cik.c

9133

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/drm/radeon/cik.c

9134

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/drm/radeon/cik.c

9135

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/drm/radeon/cik.c

9137

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/drm/radeon/cik.c

9138

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/drm/radeon/cik.c

9139

u32 tmp, dmif_size = 12288;

sys/dev/drm/radeon/cik.c

9228

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/drm/radeon/cik.c

9229

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/drm/radeon/cik.c

9230

u32 latency_tolerant_lines;

sys/dev/drm/radeon/cik.c

9231

u32 latency_hiding;

sys/dev/drm/radeon/cik.c

9265

u32 lb_size, u32 num_heads)

sys/dev/drm/radeon/cik.c

9269

u32 active_time;

sys/dev/drm/radeon/cik.c

9270

u32 line_time = 0;

sys/dev/drm/radeon/cik.c

9271

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/drm/radeon/cik.c

9272

u32 tmp, wm_mask;

sys/dev/drm/radeon/cik.c

9275

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/radeon/cik.c

9276

(u32)mode->clock);

sys/dev/drm/radeon/cik.c

9277

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/radeon/cik.c

9278

(u32)mode->clock);

sys/dev/drm/radeon/cik.c

9279

line_time = min(line_time, (u32)65535);

sys/dev/drm/radeon/cik.c

9310

latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);

sys/dev/drm/radeon/cik.c

9350

latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);

sys/dev/drm/radeon/cik.c

9402

u32 num_heads = 0, lb_size;

sys/dev/drm/radeon/cik.c

9441

static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/drm/radeon/cik.c

9442

u32 cntl_reg, u32 status_reg)

sys/dev/drm/radeon/cik.c

9469

int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/drm/radeon/cik.c

9481

int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

sys/dev/drm/radeon/cik.c

9485

u32 tmp;

sys/dev/drm/radeon/cik.c

9521

u32 speed_cntl, current_data_rate;

sys/dev/drm/radeon/cik.c

9577

u32 max_lw, current_lw, tmp;

sys/dev/drm/radeon/cik.c

9682

u32 data, orig;

sys/dev/drm/radeon/cik.c

9763

u32 lnkcap;

sys/dev/drm/radeon/cik_blit_shaders.c

246

const u32 cik_default_size = ARRAY_SIZE(cik_default_state);

sys/dev/drm/radeon/cik_blit_shaders.c

31

const u32 cik_default_state[] =

sys/dev/drm/radeon/cik_blit_shaders.h

28

extern const u32 cik_default_state[];

sys/dev/drm/radeon/cik_blit_shaders.h

30

extern const u32 cik_default_size;

sys/dev/drm/radeon/cik_sdma.c

112

u32 reg;

sys/dev/drm/radeon/cik_sdma.c

135

u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;

sys/dev/drm/radeon/cik_sdma.c

138

u32 next_rptr = ring->wptr + 5;

sys/dev/drm/radeon/cik_sdma.c

171

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

sys/dev/drm/radeon/cik_sdma.c

173

u32 ref_and_mask;

sys/dev/drm/radeon/cik_sdma.c

232

u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;

sys/dev/drm/radeon/cik_sdma.c

250

u32 rb_cntl, reg_offset;

sys/dev/drm/radeon/cik_sdma.c

331

u32 me_cntl, reg_offset;

sys/dev/drm/radeon/cik_sdma.c

366

u32 rb_cntl, ib_cntl;

sys/dev/drm/radeon/cik_sdma.c

367

u32 rb_bufsz;

sys/dev/drm/radeon/cik_sdma.c

368

u32 reg_offset, wb_offset;

sys/dev/drm/radeon/cik_sdma.c

474

u32 fw_size;

sys/dev/drm/radeon/cik_sdma.c

586

u32 size_in_bytes, cur_size_in_bytes;

sys/dev/drm/radeon/cik_sdma.c

64

u32 rptr, reg;

sys/dev/drm/radeon/cik_sdma.c

649

u32 tmp;

sys/dev/drm/radeon/cik_sdma.c

706

u32 tmp = 0;

sys/dev/drm/radeon/cik_sdma.c

775

u32 reset_mask = cik_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/cik_sdma.c

776

u32 mask;

sys/dev/drm/radeon/cik_sdma.c

91

u32 reg;

sys/dev/drm/radeon/cik_sdma.c

948

u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |

sys/dev/drm/radeon/clearstate_cayman.h

1055

static const u32 SECT_CLEAR_def_1[] =

sys/dev/drm/radeon/clearstate_cayman.h

1066

static const u32 SECT_CTRLCONST_def_1[] =

sys/dev/drm/radeon/clearstate_cayman.h

24

static const u32 SECT_CONTEXT_def_1[] =

sys/dev/drm/radeon/clearstate_cayman.h

515

static const u32 SECT_CONTEXT_def_2[] =

sys/dev/drm/radeon/clearstate_cayman.h

524

static const u32 SECT_CONTEXT_def_3[] =

sys/dev/drm/radeon/clearstate_cayman.h

582

static const u32 SECT_CONTEXT_def_4[] =

sys/dev/drm/radeon/clearstate_cayman.h

684

static const u32 SECT_CONTEXT_def_5[] =

sys/dev/drm/radeon/clearstate_cayman.h

692

static const u32 SECT_CONTEXT_def_6[] =

sys/dev/drm/radeon/clearstate_cayman.h

751

static const u32 SECT_CONTEXT_def_7[] =

sys/dev/drm/radeon/clearstate_evergreen.h

1054

static const u32 SECT_CLEAR_def_1[] =

sys/dev/drm/radeon/clearstate_evergreen.h

1065

static const u32 SECT_CTRLCONST_def_1[] =

sys/dev/drm/radeon/clearstate_evergreen.h

24

static const u32 SECT_CONTEXT_def_1[] =

sys/dev/drm/radeon/clearstate_evergreen.h

515

static const u32 SECT_CONTEXT_def_2[] =

sys/dev/drm/radeon/clearstate_evergreen.h

524

static const u32 SECT_CONTEXT_def_3[] =

sys/dev/drm/radeon/clearstate_evergreen.h

582

static const u32 SECT_CONTEXT_def_4[] =

sys/dev/drm/radeon/clearstate_evergreen.h

683

static const u32 SECT_CONTEXT_def_5[] =

sys/dev/drm/radeon/clearstate_evergreen.h

691

static const u32 SECT_CONTEXT_def_6[] =

sys/dev/drm/radeon/clearstate_evergreen.h

750

static const u32 SECT_CONTEXT_def_7[] =

sys/dev/drm/radeon/clearstate_si.h

239

static const u32 si_SECT_CONTEXT_def_2[] =

sys/dev/drm/radeon/clearstate_si.h

24

static const u32 si_SECT_CONTEXT_def_1[] =

sys/dev/drm/radeon/clearstate_si.h

514

static const u32 si_SECT_CONTEXT_def_3[] =

sys/dev/drm/radeon/clearstate_si.h

523

static const u32 si_SECT_CONTEXT_def_4[] =

sys/dev/drm/radeon/clearstate_si.h

683

static const u32 si_SECT_CONTEXT_def_5[] =

sys/dev/drm/radeon/clearstate_si.h

687

static const u32 si_SECT_CONTEXT_def_6[] =

sys/dev/drm/radeon/clearstate_si.h

691

static const u32 si_SECT_CONTEXT_def_7[] =

sys/dev/drm/radeon/cypress_dpm.c

1038

u32 i;

sys/dev/drm/radeon/cypress_dpm.c

1050

u32 i, j;

sys/dev/drm/radeon/cypress_dpm.c

1094

u32 i, j;

sys/dev/drm/radeon/cypress_dpm.c

1095

u32 channels = 2;

sys/dev/drm/radeon/cypress_dpm.c

1124

u32 strobe_mode;

sys/dev/drm/radeon/cypress_dpm.c

1125

u32 mc_seq_cg;

sys/dev/drm/radeon/cypress_dpm.c

1172

u32 value;

sys/dev/drm/radeon/cypress_dpm.c

1173

u32 i;

sys/dev/drm/radeon/cypress_dpm.c

1185

u32 strobe_mode;

sys/dev/drm/radeon/cypress_dpm.c

1186

u32 mc_seq_cg;

sys/dev/drm/radeon/cypress_dpm.c

1245

u32 a_t;

sys/dev/drm/radeon/cypress_dpm.c

1339

u32 mpll_ad_func_cntl =

sys/dev/drm/radeon/cypress_dpm.c

1341

u32 mpll_ad_func_cntl_2 =

sys/dev/drm/radeon/cypress_dpm.c

1343

u32 mpll_dq_func_cntl =

sys/dev/drm/radeon/cypress_dpm.c

1345

u32 mpll_dq_func_cntl_2 =

sys/dev/drm/radeon/cypress_dpm.c

1347

u32 spll_func_cntl =

sys/dev/drm/radeon/cypress_dpm.c

1349

u32 spll_func_cntl_2 =

sys/dev/drm/radeon/cypress_dpm.c

1351

u32 spll_func_cntl_3 =

sys/dev/drm/radeon/cypress_dpm.c

1353

u32 mclk_pwrmgt_cntl =

sys/dev/drm/radeon/cypress_dpm.c

1355

u32 dll_cntl =

sys/dev/drm/radeon/cypress_dpm.c

1565

static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)

sys/dev/drm/radeon/cypress_dpm.c

1580

u32 tmp = RREG32(GENERAL_PWRMGT);

sys/dev/drm/radeon/cypress_dpm.c

1699

u32 tmp;

sys/dev/drm/radeon/cypress_dpm.c

1734

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/cypress_dpm.c

1748

u32 tmp, pipe;

sys/dev/drm/radeon/cypress_dpm.c

178

u32 cgts_sm_ctrl_reg;

sys/dev/drm/radeon/cypress_dpm.c

2160

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/drm/radeon/cypress_dpm.c

2162

u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

sys/dev/drm/radeon/cypress_dpm.c

276

u32 reference_clock;

sys/dev/drm/radeon/cypress_dpm.c

277

u32 mclk_switch_limit;

sys/dev/drm/radeon/cypress_dpm.c

306

u32 tmp;

sys/dev/drm/radeon/cypress_dpm.c

331

u32 tmp;

sys/dev/drm/radeon/cypress_dpm.c

423

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/drm/radeon/cypress_dpm.c

441

u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)

sys/dev/drm/radeon/cypress_dpm.c

443

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/cypress_dpm.c

444

u32 vco = clkf * ref_clk;

sys/dev/drm/radeon/cypress_dpm.c

474

u32 engine_clock, u32 memory_clock,

sys/dev/drm/radeon/cypress_dpm.c

480

u32 mpll_ad_func_cntl =

sys/dev/drm/radeon/cypress_dpm.c

482

u32 mpll_ad_func_cntl_2 =

sys/dev/drm/radeon/cypress_dpm.c

484

u32 mpll_dq_func_cntl =

sys/dev/drm/radeon/cypress_dpm.c

486

u32 mpll_dq_func_cntl_2 =

sys/dev/drm/radeon/cypress_dpm.c

488

u32 mclk_pwrmgt_cntl =

sys/dev/drm/radeon/cypress_dpm.c

490

u32 dll_cntl =

sys/dev/drm/radeon/cypress_dpm.c

492

u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;

sys/dev/drm/radeon/cypress_dpm.c

493

u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;

sys/dev/drm/radeon/cypress_dpm.c

495

u32 ibias;

sys/dev/drm/radeon/cypress_dpm.c

496

u32 dll_speed;

sys/dev/drm/radeon/cypress_dpm.c

498

u32 mc_seq_misc7;

sys/dev/drm/radeon/cypress_dpm.c

53

u32 tmp, bif;

sys/dev/drm/radeon/cypress_dpm.c

555

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/drm/radeon/cypress_dpm.c

559

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/cypress_dpm.c

560

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/drm/radeon/cypress_dpm.c

561

u32 clk_s, clk_v;

sys/dev/drm/radeon/cypress_dpm.c

615

u32 memory_clock, bool strobe_mode)

sys/dev/drm/radeon/cypress_dpm.c

656

u32 mclk,

sys/dev/drm/radeon/cypress_dpm.c

819

u32 num_entries, u32 valid_flag)

sys/dev/drm/radeon/cypress_dpm.c

821

u32 i, j;

sys/dev/drm/radeon/cypress_dpm.c

836

u32 i = 0;

sys/dev/drm/radeon/cypress_dpm.c

907

u32 cypress_calculate_burst_time(struct radeon_device *rdev,

sys/dev/drm/radeon/cypress_dpm.c

908

u32 engine_clock, u32 memory_clock)

sys/dev/drm/radeon/cypress_dpm.c

911

u32 multiplier = pi->mem_gddr5 ? 1 : 2;

sys/dev/drm/radeon/cypress_dpm.c

912

u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);

sys/dev/drm/radeon/cypress_dpm.c

913

u32 burst_time;

sys/dev/drm/radeon/cypress_dpm.c

932

u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);

sys/dev/drm/radeon/cypress_dpm.c

955

u32 i, j;

sys/dev/drm/radeon/cypress_dpm.c

973

u32 i = 0;

sys/dev/drm/radeon/cypress_dpm.h

124

u32 cypress_calculate_burst_time(struct radeon_device *rdev,

sys/dev/drm/radeon/cypress_dpm.h

125

u32 engine_clock, u32 memory_clock);

sys/dev/drm/radeon/cypress_dpm.h

155

u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);

sys/dev/drm/radeon/cypress_dpm.h

157

u32 memory_clock, bool strobe_mode);

sys/dev/drm/radeon/cypress_dpm.h

158

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);

sys/dev/drm/radeon/cypress_dpm.h

30

u32 mclk_max;

sys/dev/drm/radeon/cypress_dpm.h

31

u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/cypress_dpm.h

48

u32 mc_arb_dram_timing;

sys/dev/drm/radeon/cypress_dpm.h

49

u32 mc_arb_dram_timing2;

sys/dev/drm/radeon/cypress_dpm.h

50

u32 mc_arb_rfsh_rate;

sys/dev/drm/radeon/cypress_dpm.h

51

u32 mc_arb_burst_time;

sys/dev/drm/radeon/cypress_dpm.h

55

u32 rlp;

sys/dev/drm/radeon/cypress_dpm.h

56

u32 rmp;

sys/dev/drm/radeon/cypress_dpm.h

57

u32 lhp;

sys/dev/drm/radeon/cypress_dpm.h

58

u32 lmp;

sys/dev/drm/radeon/cypress_dpm.h

82

u32 mclk_edc_wr_enable_threshold;

sys/dev/drm/radeon/dce3_1_afmt.c

130

u32 dto_phase;

sys/dev/drm/radeon/dce3_1_afmt.c

131

u32 wallclock_ratio;

sys/dev/drm/radeon/dce3_1_afmt.c

132

u32 dto_cntl;

sys/dev/drm/radeon/dce3_1_afmt.c

212

void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/dce3_1_afmt.c

213

void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/drm/radeon/dce3_1_afmt.c

234

void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/dce3_1_afmt.c

235

void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)

sys/dev/drm/radeon/dce3_1_afmt.c

36

u32 tmp;

sys/dev/drm/radeon/dce3_1_afmt.c

56

u32 tmp;

sys/dev/drm/radeon/dce3_1_afmt.c

93

u32 value = 0;

sys/dev/drm/radeon/dce6_afmt.c

139

u32 tmp = 0;

sys/dev/drm/radeon/dce6_afmt.c

169

u32 tmp;

sys/dev/drm/radeon/dce6_afmt.c

196

u32 tmp;

sys/dev/drm/radeon/dce6_afmt.c

241

u32 value = 0;

sys/dev/drm/radeon/dce6_afmt.c

287

u32 value = 0;

sys/dev/drm/radeon/dce6_afmt.c

308

u32 value = 0;

sys/dev/drm/radeon/dce6_afmt.c

32

u32 dce6_endpoint_rreg(struct radeon_device *rdev,

sys/dev/drm/radeon/dce6_afmt.c

33

u32 block_offset, u32 reg);

sys/dev/drm/radeon/dce6_afmt.c

35

u32 block_offset, u32 reg, u32 v);

sys/dev/drm/radeon/dce6_afmt.c

44

u32 dce6_endpoint_rreg(struct radeon_device *rdev,

sys/dev/drm/radeon/dce6_afmt.c

45

u32 block_offset, u32 reg)

sys/dev/drm/radeon/dce6_afmt.c

47

u32 r;

sys/dev/drm/radeon/dce6_afmt.c

58

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/radeon/dce6_afmt.c

73

u32 offset, tmp;

sys/dev/drm/radeon/evergreen.c

1000

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/drm/radeon/evergreen.c

1003

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

1006

(const u32)ARRAY_SIZE(juniper_mgcg_init));

sys/dev/drm/radeon/evergreen.c

101

void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/evergreen.c

1011

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/drm/radeon/evergreen.c

1014

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

1017

(const u32)ARRAY_SIZE(redwood_mgcg_init));

sys/dev/drm/radeon/evergreen.c

1022

(const u32)ARRAY_SIZE(cedar_golden_registers));

sys/dev/drm/radeon/evergreen.c

1025

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

1028

(const u32)ARRAY_SIZE(cedar_mgcg_init));

sys/dev/drm/radeon/evergreen.c

1033

(const u32)ARRAY_SIZE(wrestler_golden_registers));

sys/dev/drm/radeon/evergreen.c

1038

(const u32)ARRAY_SIZE(supersumo_golden_registers));

sys/dev/drm/radeon/evergreen.c

1043

(const u32)ARRAY_SIZE(supersumo_golden_registers));

sys/dev/drm/radeon/evergreen.c

1046

(const u32)ARRAY_SIZE(sumo_golden_registers));

sys/dev/drm/radeon/evergreen.c

1051

(const u32)ARRAY_SIZE(barts_golden_registers));

sys/dev/drm/radeon/evergreen.c

1056

(const u32)ARRAY_SIZE(turks_golden_registers));

sys/dev/drm/radeon/evergreen.c

1061

(const u32)ARRAY_SIZE(caicos_golden_registers));

sys/dev/drm/radeon/evergreen.c

1079

u32 reg, u32 *val)

sys/dev/drm/radeon/evergreen.c

111

static const u32 crtc_offsets[6] =

sys/dev/drm/radeon/evergreen.c

1127

static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/drm/radeon/evergreen.c

1128

u32 cntl_reg, u32 status_reg)

sys/dev/drm/radeon/evergreen.c

1151

int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/drm/radeon/evergreen.c

1154

u32 cg_scratch = RREG32(CG_SCRATCH1);

sys/dev/drm/radeon/evergreen.c

1174

int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/drm/radeon/evergreen.c

123

static const u32 sumo_rlc_save_restore_register_list[] =

sys/dev/drm/radeon/evergreen.c

1285

u32 tmp = 0;

sys/dev/drm/radeon/evergreen.c

1343

u32 pos1, pos2;

sys/dev/drm/radeon/evergreen.c

1411

(u32)crtc_base);

sys/dev/drm/radeon/evergreen.c

1436

u32 temp, toffset;

sys/dev/drm/radeon/evergreen.c

1474

u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;

sys/dev/drm/radeon/evergreen.c

1658

u32 tmp;

sys/dev/drm/radeon/evergreen.c

1683

u32 tmp;

sys/dev/drm/radeon/evergreen.c

1748

u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |

sys/dev/drm/radeon/evergreen.c

1805

static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,

sys/dev/drm/radeon/evergreen.c

1810

u32 tmp, buffer_alloc, i;

sys/dev/drm/radeon/evergreen.c

1811

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/drm/radeon/evergreen.c

1896

u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)

sys/dev/drm/radeon/evergreen.c

1898

u32 tmp = RREG32(MC_SHARED_CHMAP);

sys/dev/drm/radeon/evergreen.c

1914

u32 dram_channels; /* number of dram channels */

sys/dev/drm/radeon/evergreen.c

1915

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/drm/radeon/evergreen.c

1916

u32 sclk; /* engine clock in kHz */

sys/dev/drm/radeon/evergreen.c

1917

u32 disp_clk; /* display clock in kHz */

sys/dev/drm/radeon/evergreen.c

1918

u32 src_width; /* viewport width */

sys/dev/drm/radeon/evergreen.c

1919

u32 active_time; /* active display time in ns */

sys/dev/drm/radeon/evergreen.c

1920

u32 blank_time; /* blank time in ns */

sys/dev/drm/radeon/evergreen.c

1923

u32 num_heads; /* number of active crtcs */

sys/dev/drm/radeon/evergreen.c

1924

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/drm/radeon/evergreen.c

1925

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/drm/radeon/evergreen.c

1926

u32 vtaps; /* vertical scaler taps */

sys/dev/drm/radeon/evergreen.c

1929

static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

1949

static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

1969

static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

1989

static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

2009

static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

2012

u32 dram_bandwidth = evergreen_dram_bandwidth(wm);

sys/dev/drm/radeon/evergreen.c

2013

u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);

sys/dev/drm/radeon/evergreen.c

2014

u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);

sys/dev/drm/radeon/evergreen.c

2019

static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

2043

static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)

sys/dev/drm/radeon/evergreen.c

2046

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/drm/radeon/evergreen.c

2047

u32 available_bandwidth = evergreen_available_bandwidth(wm);

sys/dev/drm/radeon/evergreen.c

2048

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/drm/radeon/evergreen.c

2049

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/drm/radeon/evergreen.c

2050

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/drm/radeon/evergreen.c

2051

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/drm/radeon/evergreen.c

2053

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/drm/radeon/evergreen.c

2054

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/drm/radeon/evergreen.c

210

static const u32 evergreen_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

2110

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/drm/radeon/evergreen.c

2111

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/drm/radeon/evergreen.c

2112

u32 latency_tolerant_lines;

sys/dev/drm/radeon/evergreen.c

2113

u32 latency_hiding;

sys/dev/drm/radeon/evergreen.c

2136

u32 lb_size, u32 num_heads)

sys/dev/drm/radeon/evergreen.c

2140

u32 dram_channels;

sys/dev/drm/radeon/evergreen.c

2141

u32 active_time;

sys/dev/drm/radeon/evergreen.c

2142

u32 line_time = 0;

sys/dev/drm/radeon/evergreen.c

2143

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/drm/radeon/evergreen.c

2144

u32 priority_a_mark = 0, priority_b_mark = 0;

sys/dev/drm/radeon/evergreen.c

2145

u32 priority_a_cnt = PRIORITY_OFF;

sys/dev/drm/radeon/evergreen.c

2146

u32 priority_b_cnt = PRIORITY_OFF;

sys/dev/drm/radeon/evergreen.c

2147

u32 pipe_offset = radeon_crtc->crtc_id * 16;

sys/dev/drm/radeon/evergreen.c

2148

u32 tmp, arb_control3;

sys/dev/drm/radeon/evergreen.c

2152

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/radeon/evergreen.c

2153

(u32)mode->clock);

sys/dev/drm/radeon/evergreen.c

2154

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/radeon/evergreen.c

2155

(u32)mode->clock);

sys/dev/drm/radeon/evergreen.c

2156

line_time = min(line_time, (u32)65535);

sys/dev/drm/radeon/evergreen.c

2216

latency_watermark_a = min(evergreen_latency_watermark(&wm_high), (u32)65535);

sys/dev/drm/radeon/evergreen.c

2218

latency_watermark_b = min(evergreen_latency_watermark(&wm_low), (u32)65535);

sys/dev/drm/radeon/evergreen.c

2307

u32 num_heads = 0, lb_size;

sys/dev/drm/radeon/evergreen.c

2341

u32 tmp;

sys/dev/drm/radeon/evergreen.c

2359

u32 tmp;

sys/dev/drm/radeon/evergreen.c

2381

u32 tmp;

sys/dev/drm/radeon/evergreen.c

2426

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/evergreen.c

2439

u32 tmp;

sys/dev/drm/radeon/evergreen.c

2472

u32 tmp;

sys/dev/drm/radeon/evergreen.c

256

static const u32 evergreen_golden_registers2[] =

sys/dev/drm/radeon/evergreen.c

2648

u32 crtc_enabled, tmp, frame_count, blackout;

sys/dev/drm/radeon/evergreen.c

274

static const u32 cypress_mgcg_init[] =

sys/dev/drm/radeon/evergreen.c

2746

u32 tmp, frame_count;

sys/dev/drm/radeon/evergreen.c

2756

(u32)rdev->mc.vram_start);

sys/dev/drm/radeon/evergreen.c

2758

(u32)rdev->mc.vram_start);

sys/dev/drm/radeon/evergreen.c

2763

WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

sys/dev/drm/radeon/evergreen.c

2835

u32 tmp;

sys/dev/drm/radeon/evergreen.c

2915

u32 next_rptr;

sys/dev/drm/radeon/evergreen.c

3048

u32 tmp;

sys/dev/drm/radeon/evergreen.c

3049

u32 rb_bufsz;

sys/dev/drm/radeon/evergreen.c

3117

u32 gb_addr_config;

sys/dev/drm/radeon/evergreen.c

3118

u32 mc_shared_chmap, mc_arb_ramcfg;

sys/dev/drm/radeon/evergreen.c

3119

u32 sx_debug_1;

sys/dev/drm/radeon/evergreen.c

3120

u32 smx_dc_ctl0;

sys/dev/drm/radeon/evergreen.c

3121

u32 sq_config;

sys/dev/drm/radeon/evergreen.c

3122

u32 sq_lds_resource_mgmt;

sys/dev/drm/radeon/evergreen.c

3123

u32 sq_gpr_resource_mgmt_1;

sys/dev/drm/radeon/evergreen.c

3124

u32 sq_gpr_resource_mgmt_2;

sys/dev/drm/radeon/evergreen.c

3125

u32 sq_gpr_resource_mgmt_3;

sys/dev/drm/radeon/evergreen.c

3126

u32 sq_thread_resource_mgmt;

sys/dev/drm/radeon/evergreen.c

3127

u32 sq_thread_resource_mgmt_2;

sys/dev/drm/radeon/evergreen.c

3128

u32 sq_stack_resource_mgmt_1;

sys/dev/drm/radeon/evergreen.c

3129

u32 sq_stack_resource_mgmt_2;

sys/dev/drm/radeon/evergreen.c

3130

u32 sq_stack_resource_mgmt_3;

sys/dev/drm/radeon/evergreen.c

3131

u32 vgt_cache_invalidation;

sys/dev/drm/radeon/evergreen.c

3132

u32 hdp_host_path_cntl, tmp;

sys/dev/drm/radeon/evergreen.c

3133

u32 disabled_rb_mask;

sys/dev/drm/radeon/evergreen.c

3435

u32 efuse_straps_4;

sys/dev/drm/radeon/evergreen.c

3436

u32 efuse_straps_3;

sys/dev/drm/radeon/evergreen.c

3445

u32 rb_disable_bitmap;

sys/dev/drm/radeon/evergreen.c

3466

u32 simd_disable_bitmap;

sys/dev/drm/radeon/evergreen.c

3694

u32 tmp;

sys/dev/drm/radeon/evergreen.c

3781

u32 crtc_hung = 0;

sys/dev/drm/radeon/evergreen.c

3782

u32 crtc_status[6];

sys/dev/drm/radeon/evergreen.c

3783

u32 i, j, tmp;

sys/dev/drm/radeon/evergreen.c

3808

u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/drm/radeon/evergreen.c

3810

u32 reset_mask = 0;

sys/dev/drm/radeon/evergreen.c

3811

u32 tmp;

sys/dev/drm/radeon/evergreen.c

3877

static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/drm/radeon/evergreen.c

3880

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/radeon/evergreen.c

3881

u32 tmp;

sys/dev/drm/radeon/evergreen.c

3994

u32 tmp, i;

sys/dev/drm/radeon/evergreen.c

4035

u32 reset_mask;

sys/dev/drm/radeon/evergreen.c

4075

u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/evergreen.c

4137

const u32 *src_ptr;

sys/dev/drm/radeon/evergreen.c

4138

volatile u32 *dst_ptr;

sys/dev/drm/radeon/evergreen.c

4139

u32 dws, data, i, j, k, reg_num;

sys/dev/drm/radeon/evergreen.c

4140

u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index = 0;

sys/dev/drm/radeon/evergreen.c

427

static const u32 redwood_mgcg_init[] =

sys/dev/drm/radeon/evergreen.c

4354

u32 mask = RLC_ENABLE;

sys/dev/drm/radeon/evergreen.c

4365

u32 i;

sys/dev/drm/radeon/evergreen.c

4377

u32 always_on_bitmap =

sys/dev/drm/radeon/evergreen.c

4380

u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

sys/dev/drm/radeon/evergreen.c

4432

u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)

sys/dev/drm/radeon/evergreen.c

4443

u32 tmp;

sys/dev/drm/radeon/evergreen.c

4476

u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;

sys/dev/drm/radeon/evergreen.c

4477

u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;

sys/dev/drm/radeon/evergreen.c

4478

u32 grbm_int_cntl = 0;

sys/dev/drm/radeon/evergreen.c

4479

u32 dma_cntl, dma_cntl1 = 0;

sys/dev/drm/radeon/evergreen.c

4480

u32 thermal_int = 0;

sys/dev/drm/radeon/evergreen.c

45

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/evergreen.c

4597

u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;

sys/dev/drm/radeon/evergreen.c

4598

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/drm/radeon/evergreen.c

4599

u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;

sys/dev/drm/radeon/evergreen.c

4658

static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)

sys/dev/drm/radeon/evergreen.c

4660

u32 wptr, tmp;

sys/dev/drm/radeon/evergreen.c

4685

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/drm/radeon/evergreen.c

4686

u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;

sys/dev/drm/radeon/evergreen.c

4687

u32 crtc_idx, hpd_idx, afmt_idx;

sys/dev/drm/radeon/evergreen.c

4688

u32 mask;

sys/dev/drm/radeon/evergreen.c

4689

u32 wptr;

sys/dev/drm/radeon/evergreen.c

4690

u32 rptr;

sys/dev/drm/radeon/evergreen.c

4691

u32 src_id, src_data;

sys/dev/drm/radeon/evergreen.c

4692

u32 ring_index;

sys/dev/drm/radeon/evergreen.c

4697

u32 status, addr;

sys/dev/drm/radeon/evergreen.c

48

u32 r;

sys/dev/drm/radeon/evergreen.c

499

static const u32 cedar_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

5019

(u32)ARRAY_SIZE(sumo_rlc_save_restore_register_list);

sys/dev/drm/radeon/evergreen.c

5319

u32 link_width_cntl, speed_cntl;

sys/dev/drm/radeon/evergreen.c

5382

u32 data, orig;

sys/dev/drm/radeon/evergreen.c

5383

u32 pcie_lc_cntl, pcie_lc_cntl_old;

sys/dev/drm/radeon/evergreen.c

542

static const u32 cedar_mgcg_init[] =

sys/dev/drm/radeon/evergreen.c

57

void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/evergreen.c

596

static const u32 juniper_mgcg_init[] =

sys/dev/drm/radeon/evergreen.c

67

u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/evergreen.c

694

static const u32 supersumo_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

70

u32 r;

sys/dev/drm/radeon/evergreen.c

769

static const u32 sumo_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

778

static const u32 wrestler_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

79

void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/evergreen.c

831

static const u32 barts_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

880

static const u32 turks_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

89

u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/evergreen.c

92

u32 r;

sys/dev/drm/radeon/evergreen.c

931

static const u32 caicos_golden_registers[] =

sys/dev/drm/radeon/evergreen.c

989

(const u32)ARRAY_SIZE(evergreen_golden_registers));

sys/dev/drm/radeon/evergreen.c

992

(const u32)ARRAY_SIZE(evergreen_golden_registers2));

sys/dev/drm/radeon/evergreen.c

995

(const u32)ARRAY_SIZE(cypress_mgcg_init));

sys/dev/drm/radeon/evergreen_blit_shaders.c

303

const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);

sys/dev/drm/radeon/evergreen_blit_shaders.c

41

const u32 evergreen_default_state[] =

sys/dev/drm/radeon/evergreen_blit_shaders.h

28

extern const u32 evergreen_default_state[];

sys/dev/drm/radeon/evergreen_blit_shaders.h

30

extern const u32 evergreen_default_size;

sys/dev/drm/radeon/evergreen_cs.c

101

static u32 evergreen_cs_get_num_banks(u32 nbanks)

sys/dev/drm/radeon/evergreen_cs.c

1092

static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/drm/radeon/evergreen_cs.c

1096

u32 tmp, *ib;

sys/dev/drm/radeon/evergreen_cs.c

1147

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1219

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1231

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1243

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1255

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1279

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1299

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1503

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1520

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1561

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1577

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1589

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1706

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1720

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1734

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

1754

static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg)

sys/dev/drm/radeon/evergreen_cs.c

1757

u32 m, i;

sys/dev/drm/radeon/evergreen_cs.c

1780

u32 idx_value;

sys/dev/drm/radeon/evergreen_cs.c

2077

ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2112

u32 command, size, info;

sys/dev/drm/radeon/evergreen_cs.c

2230

ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2347

u32 toffset, moffset;

sys/dev/drm/radeon/evergreen_cs.c

2348

u32 size, offset, mip_address, tex_dim;

sys/dev/drm/radeon/evergreen_cs.c

2376

toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2395

moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2674

u32 tmp;

sys/dev/drm/radeon/evergreen_cs.c

2799

u32 header, cmd, count, sub_cmd;

sys/dev/drm/radeon/evergreen_cs.c

2801

u32 idx;

sys/dev/drm/radeon/evergreen_cs.c

2830

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

2838

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2881

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2882

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2894

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

2898

ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2904

ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2909

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

2940

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2941

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2953

ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2955

ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff);

sys/dev/drm/radeon/evergreen_cs.c

2989

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2990

ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

2991

ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3029

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3030

ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3031

ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3045

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3047

ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3051

ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3054

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3091

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3092

ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3093

ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3105

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3109

ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3115

ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3120

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3141

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3142

ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3178

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3179

ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/evergreen_cs.c

3180

ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3202

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/evergreen_cs.c

3224

static bool evergreen_vm_reg_valid(u32 reg)

sys/dev/drm/radeon/evergreen_cs.c

3347

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/drm/radeon/evergreen_cs.c

3349

u32 idx = pkt->idx + 1;

sys/dev/drm/radeon/evergreen_cs.c

3350

u32 idx_value = ib[idx];

sys/dev/drm/radeon/evergreen_cs.c

3351

u32 start_reg, end_reg, reg, i;

sys/dev/drm/radeon/evergreen_cs.c

3352

u32 command, info;

sys/dev/drm/radeon/evergreen_cs.c

3522

u32 idx = 0;

sys/dev/drm/radeon/evergreen_cs.c

3566

u32 idx = 0;

sys/dev/drm/radeon/evergreen_cs.c

3567

u32 header, cmd, count, sub_cmd;

sys/dev/drm/radeon/evergreen_cs.c

41

u32 group_size;

sys/dev/drm/radeon/evergreen_cs.c

42

u32 nbanks;

sys/dev/drm/radeon/evergreen_cs.c

43

u32 npipes;

sys/dev/drm/radeon/evergreen_cs.c

44

u32 row_size;

sys/dev/drm/radeon/evergreen_cs.c

46

u32 nsamples; /* unused */

sys/dev/drm/radeon/evergreen_cs.c

48

u32 cb_color_bo_offset[12];

sys/dev/drm/radeon/evergreen_cs.c

51

u32 cb_color_info[12];

sys/dev/drm/radeon/evergreen_cs.c

52

u32 cb_color_view[12];

sys/dev/drm/radeon/evergreen_cs.c

53

u32 cb_color_pitch[12];

sys/dev/drm/radeon/evergreen_cs.c

54

u32 cb_color_slice[12];

sys/dev/drm/radeon/evergreen_cs.c

55

u32 cb_color_slice_idx[12];

sys/dev/drm/radeon/evergreen_cs.c

56

u32 cb_color_attrib[12];

sys/dev/drm/radeon/evergreen_cs.c

57

u32 cb_color_cmask_slice[8];/* unused */

sys/dev/drm/radeon/evergreen_cs.c

58

u32 cb_color_fmask_slice[8];/* unused */

sys/dev/drm/radeon/evergreen_cs.c

59

u32 cb_target_mask;

sys/dev/drm/radeon/evergreen_cs.c

60

u32 cb_shader_mask; /* unused */

sys/dev/drm/radeon/evergreen_cs.c

61

u32 vgt_strmout_config;

sys/dev/drm/radeon/evergreen_cs.c

62

u32 vgt_strmout_buffer_config;

sys/dev/drm/radeon/evergreen_cs.c

64

u32 vgt_strmout_bo_offset[4];

sys/dev/drm/radeon/evergreen_cs.c

65

u32 vgt_strmout_size[4];

sys/dev/drm/radeon/evergreen_cs.c

66

u32 db_depth_control;

sys/dev/drm/radeon/evergreen_cs.c

67

u32 db_depth_view;

sys/dev/drm/radeon/evergreen_cs.c

68

u32 db_depth_slice;

sys/dev/drm/radeon/evergreen_cs.c

69

u32 db_depth_size;

sys/dev/drm/radeon/evergreen_cs.c

70

u32 db_z_info;

sys/dev/drm/radeon/evergreen_cs.c

71

u32 db_z_read_offset;

sys/dev/drm/radeon/evergreen_cs.c

72

u32 db_z_write_offset;

sys/dev/drm/radeon/evergreen_cs.c

75

u32 db_s_info;

sys/dev/drm/radeon/evergreen_cs.c

759

u32 texdw[8];

sys/dev/drm/radeon/evergreen_cs.c

76

u32 db_s_read_offset;

sys/dev/drm/radeon/evergreen_cs.c

77

u32 db_s_write_offset;

sys/dev/drm/radeon/evergreen_cs.c

84

u32 htile_offset;

sys/dev/drm/radeon/evergreen_cs.c

85

u32 htile_surface;

sys/dev/drm/radeon/evergreen_cs.c

91

static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)

sys/dev/drm/radeon/evergreen_cs.c

973

u32 format = G_028C70_FORMAT(track->cb_color_info[i]);

sys/dev/drm/radeon/evergreen_dma.c

115

u32 size_in_dw, cur_size_in_dw;

sys/dev/drm/radeon/evergreen_dma.c

171

u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/evergreen_dma.c

71

u32 next_rptr = ring->wptr + 4;

sys/dev/drm/radeon/evergreen_hdmi.c

108

u32 tmp = 0;

sys/dev/drm/radeon/evergreen_hdmi.c

132

u32 tmp;

sys/dev/drm/radeon/evergreen_hdmi.c

152

u32 tmp;

sys/dev/drm/radeon/evergreen_hdmi.c

189

u32 value = 0;

sys/dev/drm/radeon/evergreen_hdmi.c

221

void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/evergreen_hdmi.c

223

void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/evergreen_hdmi.c

248

u32 dto_phase;

sys/dev/drm/radeon/evergreen_hdmi.c

249

u32 wallclock_ratio;

sys/dev/drm/radeon/evergreen_hdmi.c

250

u32 value;

sys/dev/drm/radeon/evergreen_hdmi.c

292

u32 value;

sys/dev/drm/radeon/evergreen_hdmi.c

325

void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/evergreen_hdmi.c

326

void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/drm/radeon/evergreen_hdmi.c

337

void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc);

sys/dev/drm/radeon/evergreen_hdmi.c

338

void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)

sys/dev/drm/radeon/evergreen_hdmi.c

375

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/evergreen_hdmi.c

376

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/drm/radeon/evergreen_hdmi.c

411

void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/evergreen_hdmi.c

412

void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)

sys/dev/drm/radeon/evergreen_hdmi.c

44

u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

sys/dev/drm/radeon/kv_dpm.c

1021

u32 i;

sys/dev/drm/radeon/kv_dpm.c

1075

u32 i;

sys/dev/drm/radeon/kv_dpm.c

1171

u32 thermal_int;

sys/dev/drm/radeon/kv_dpm.c

1331

u16 reg_offset, u32 value)

sys/dev/drm/radeon/kv_dpm.c

1340

u16 reg_offset, u32 *value)

sys/dev/drm/radeon/kv_dpm.c

1426

u32 mask;

sys/dev/drm/radeon/kv_dpm.c

1456

static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)

sys/dev/drm/radeon/kv_dpm.c

1707

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2039

u32 enable_mask, i;

sys/dev/drm/radeon/kv_dpm.c

2059

u32 enable_mask, i;

sys/dev/drm/radeon/kv_dpm.c

2077

u32 sclk, u32 min_sclk_in_sr)

sys/dev/drm/radeon/kv_dpm.c

2080

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2081

u32 temp;

sys/dev/drm/radeon/kv_dpm.c

2082

u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?

sys/dev/drm/radeon/kv_dpm.c

2140

u32 min_sclk = 10000; /* ??? */

sys/dev/drm/radeon/kv_dpm.c

2141

u32 sclk, mclk = 0;

sys/dev/drm/radeon/kv_dpm.c

2146

u32 stable_p_state_sclk = 0;

sys/dev/drm/radeon/kv_dpm.c

2251

u32 index, bool enable)

sys/dev/drm/radeon/kv_dpm.c

2261

u32 sclk_in_sr = 10000; /* ??? */

sys/dev/drm/radeon/kv_dpm.c

2262

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2279

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2283

u32 mclk = max_limits->mclk;

sys/dev/drm/radeon/kv_dpm.c

2333

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2347

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2352

u32 vid_2bit;

sys/dev/drm/radeon/kv_dpm.c

2396

u32 i;

sys/dev/drm/radeon/kv_dpm.c

2404

static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)

sys/dev/drm/radeon/kv_dpm.c

2406

u32 new_mask = (1 << level);

sys/dev/drm/radeon/kv_dpm.c

2416

u32 i, new_mask = 0;

sys/dev/drm/radeon/kv_dpm.c

2431

u32 nbdpmconfig1;

sys/dev/drm/radeon/kv_dpm.c

2453

u32 tmp;

sys/dev/drm/radeon/kv_dpm.c

258

u32 i, count, data;

sys/dev/drm/radeon/kv_dpm.c

2613

u32 sclk;

sys/dev/drm/radeon/kv_dpm.c

2704

u32 sclk;

sys/dev/drm/radeon/kv_dpm.c

2800

u32 current_index =

sys/dev/drm/radeon/kv_dpm.c

2803

u32 sclk, tmp;

sys/dev/drm/radeon/kv_dpm.c

2820

u32 kv_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/kv_dpm.c

2823

u32 current_index =

sys/dev/drm/radeon/kv_dpm.c

2826

u32 sclk;

sys/dev/drm/radeon/kv_dpm.c

283

u32 data;

sys/dev/drm/radeon/kv_dpm.c

2836

u32 kv_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/kv_dpm.c

284

u32 cache = 0;

sys/dev/drm/radeon/kv_dpm.c

2878

u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/kv_dpm.c

2889

u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/kv_dpm.c

331

u32 data;

sys/dev/drm/radeon/kv_dpm.c

454

u32 tmp;

sys/dev/drm/radeon/kv_dpm.c

46

static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);

sys/dev/drm/radeon/kv_dpm.c

531

u32 index, u32 sclk)

sys/dev/drm/radeon/kv_dpm.c

548

static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,

sys/dev/drm/radeon/kv_dpm.c

550

u32 vid_2bit)

sys/dev/drm/radeon/kv_dpm.c

554

u32 i;

sys/dev/drm/radeon/kv_dpm.c

570

static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,

sys/dev/drm/radeon/kv_dpm.c

572

u32 vid_7bit)

sys/dev/drm/radeon/kv_dpm.c

576

u32 i;

sys/dev/drm/radeon/kv_dpm.c

601

u32 vid_2bit)

sys/dev/drm/radeon/kv_dpm.c

604

u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,

sys/dev/drm/radeon/kv_dpm.c

612

static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)

sys/dev/drm/radeon/kv_dpm.c

623

static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)

sys/dev/drm/radeon/kv_dpm.c

633

u32 index, bool enable)

sys/dev/drm/radeon/kv_dpm.c

642

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/kv_dpm.c

657

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/kv_dpm.c

667

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/kv_dpm.c

696

u32 low_sclk_interrupt_t = 0;

sys/dev/drm/radeon/kv_dpm.c

706

sizeof(u32), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

714

u32 i;

sys/dev/drm/radeon/kv_dpm.c

784

static u32 kv_get_clock_difference(u32 a, u32 b)

sys/dev/drm/radeon/kv_dpm.c

789

static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)

sys/dev/drm/radeon/kv_dpm.c

792

u32 value;

sys/dev/drm/radeon/kv_dpm.c

821

u32 i;

sys/dev/drm/radeon/kv_dpm.c

889

u32 i;

sys/dev/drm/radeon/kv_dpm.c

955

u32 i;

sys/dev/drm/radeon/kv_dpm.h

103

u32 uma_channel_number;

sys/dev/drm/radeon/kv_dpm.h

107

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/kv_dpm.h

108

u32 voltage_drop_t;

sys/dev/drm/radeon/kv_dpm.h

115

u32 lowest_valid;

sys/dev/drm/radeon/kv_dpm.h

116

u32 highest_valid;

sys/dev/drm/radeon/kv_dpm.h

121

u32 sram_end;

sys/dev/drm/radeon/kv_dpm.h

122

u32 dpm_table_start;

sys/dev/drm/radeon/kv_dpm.h

123

u32 soft_regs_start;

sys/dev/drm/radeon/kv_dpm.h

152

u32 low_sclk_interrupt_t;

sys/dev/drm/radeon/kv_dpm.h

188

int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);

sys/dev/drm/radeon/kv_dpm.h

189

int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);

sys/dev/drm/radeon/kv_dpm.h

191

PPSMC_Msg msg, u32 parameter);

sys/dev/drm/radeon/kv_dpm.h

192

int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/drm/radeon/kv_dpm.h

193

u32 *value, u32 limit);

sys/dev/drm/radeon/kv_dpm.h

197

u32 smc_start_address,

sys/dev/drm/radeon/kv_dpm.h

198

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/radeon/kv_dpm.h

45

u32 offset;

sys/dev/drm/radeon/kv_dpm.h

46

u32 mask;

sys/dev/drm/radeon/kv_dpm.h

47

u32 shift;

sys/dev/drm/radeon/kv_dpm.h

48

u32 value;

sys/dev/drm/radeon/kv_dpm.h

53

u32 block_id;

sys/dev/drm/radeon/kv_dpm.h

54

u32 signal_id;

sys/dev/drm/radeon/kv_dpm.h

55

u32 t;

sys/dev/drm/radeon/kv_dpm.h

59

u32 cntl;

sys/dev/drm/radeon/kv_dpm.h

60

u32 block_mask;

sys/dev/drm/radeon/kv_dpm.h

61

u32 block_shift;

sys/dev/drm/radeon/kv_dpm.h

62

u32 signal_mask;

sys/dev/drm/radeon/kv_dpm.h

63

u32 signal_shift;

sys/dev/drm/radeon/kv_dpm.h

64

u32 t_mask;

sys/dev/drm/radeon/kv_dpm.h

65

u32 t_shift;

sys/dev/drm/radeon/kv_dpm.h

66

u32 enable_mask;

sys/dev/drm/radeon/kv_dpm.h

67

u32 enable_shift;

sys/dev/drm/radeon/kv_dpm.h

71

u32 sclk;

sys/dev/drm/radeon/kv_dpm.h

83

u32 num_levels;

sys/dev/drm/radeon/kv_dpm.h

92

u32 bootup_uma_clk;

sys/dev/drm/radeon/kv_dpm.h

93

u32 bootup_sclk;

sys/dev/drm/radeon/kv_dpm.h

94

u32 dentist_vco_freq;

sys/dev/drm/radeon/kv_dpm.h

95

u32 nb_dpm_enable;

sys/dev/drm/radeon/kv_dpm.h

96

u32 nbp_memory_clock[KV_NUM_NBPSTATES];

sys/dev/drm/radeon/kv_dpm.h

97

u32 nbp_n_clock[KV_NUM_NBPSTATES];

sys/dev/drm/radeon/kv_smc.c

119

u32 smc_start_address,

sys/dev/drm/radeon/kv_smc.c

120

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/radeon/kv_smc.c

123

u32 data, original_data, addr, extra_shift, t_byte, count, mask;

sys/dev/drm/radeon/kv_smc.c

30

int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id)

sys/dev/drm/radeon/kv_smc.c

32

u32 i;

sys/dev/drm/radeon/kv_smc.c

33

u32 tmp = 0;

sys/dev/drm/radeon/kv_smc.c

54

int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask)

sys/dev/drm/radeon/kv_smc.c

67

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/radeon/kv_smc.c

76

u32 smc_address, u32 limit)

sys/dev/drm/radeon/kv_smc.c

89

int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/drm/radeon/kv_smc.c

90

u32 *value, u32 limit)

sys/dev/drm/radeon/ni.c

1103

u32 rb_disable_bitmap;

sys/dev/drm/radeon/ni.c

1123

u32 simd_disable_bitmap;

sys/dev/drm/radeon/ni.c

1319

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/ni.c

1343

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/ni.c

1403

int ring, u32 cp_int_cntl)

sys/dev/drm/radeon/ni.c

1417

u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |

sys/dev/drm/radeon/ni.c

1439

u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |

sys/dev/drm/radeon/ni.c

1484

u32 cayman_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/ni.c

1487

u32 rptr;

sys/dev/drm/radeon/ni.c

1503

u32 cayman_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/ni.c

1506

u32 wptr;

sys/dev/drm/radeon/ni.c

1756

u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/drm/radeon/ni.c

1758

u32 reset_mask = 0;

sys/dev/drm/radeon/ni.c

1759

u32 tmp;

sys/dev/drm/radeon/ni.c

1834

static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/drm/radeon/ni.c

1837

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/radeon/ni.c

1838

u32 tmp;

sys/dev/drm/radeon/ni.c

1968

u32 reset_mask;

sys/dev/drm/radeon/ni.c

2003

u32 reset_mask = cayman_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/ni.c

210

static const u32 cayman_golden_registers2[] =

sys/dev/drm/radeon/ni.c

220

static const u32 cayman_golden_registers[] =

sys/dev/drm/radeon/ni.c

2202

(u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);

sys/dev/drm/radeon/ni.c

2545

u32 status, u32 addr)

sys/dev/drm/radeon/ni.c

2547

u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;

sys/dev/drm/radeon/ni.c

2548

u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

sys/dev/drm/radeon/ni.c

2549

u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

sys/dev/drm/radeon/ni.c

261

static const u32 dvst_golden_registers2[] =

sys/dev/drm/radeon/ni.c

269

static const u32 dvst_golden_registers[] =

sys/dev/drm/radeon/ni.c

2733

int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

sys/dev/drm/radeon/ni.c

327

static const u32 scrapper_golden_registers[] =

sys/dev/drm/radeon/ni.c

41

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/ni.c

43

u32 r;

sys/dev/drm/radeon/ni.c

440

(const u32)ARRAY_SIZE(cayman_golden_registers));

sys/dev/drm/radeon/ni.c

443

(const u32)ARRAY_SIZE(cayman_golden_registers2));

sys/dev/drm/radeon/ni.c

467

(const u32)ARRAY_SIZE(dvst_golden_registers));

sys/dev/drm/radeon/ni.c

470

(const u32)ARRAY_SIZE(dvst_golden_registers2));

sys/dev/drm/radeon/ni.c

474

(const u32)ARRAY_SIZE(scrapper_golden_registers));

sys/dev/drm/radeon/ni.c

477

(const u32)ARRAY_SIZE(dvst_golden_registers2));

sys/dev/drm/radeon/ni.c

487

static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/ni.c

519

static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/ni.c

52

void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/ni.c

551

static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/ni.c

583

static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/ni.c

60

static const u32 tn_rlc_save_restore_register_list[] =

sys/dev/drm/radeon/ni.c

618

u32 mem_type, running, blackout = 0;

sys/dev/drm/radeon/ni.c

619

u32 *io_mc_regs;

sys/dev/drm/radeon/ni.c

627

io_mc_regs = (u32 *)&barts_io_mc_regs;

sys/dev/drm/radeon/ni.c

632

io_mc_regs = (u32 *)&turks_io_mc_regs;

sys/dev/drm/radeon/ni.c

638

io_mc_regs = (u32 *)&caicos_io_mc_regs;

sys/dev/drm/radeon/ni.c

643

io_mc_regs = (u32 *)&cayman_io_mc_regs;

sys/dev/drm/radeon/ni.c

872

u32 reg, u32 *val)

sys/dev/drm/radeon/ni.c

892

u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;

sys/dev/drm/radeon/ni.c

903

u32 gb_addr_config = 0;

sys/dev/drm/radeon/ni.c

904

u32 mc_shared_chmap, mc_arb_ramcfg;

sys/dev/drm/radeon/ni.c

905

u32 cgts_tcc_disable;

sys/dev/drm/radeon/ni.c

906

u32 sx_debug_1;

sys/dev/drm/radeon/ni.c

907

u32 smx_dc_ctl0;

sys/dev/drm/radeon/ni.c

908

u32 cgts_sm_ctrl_reg;

sys/dev/drm/radeon/ni.c

909

u32 hdp_host_path_cntl;

sys/dev/drm/radeon/ni.c

910

u32 tmp;

sys/dev/drm/radeon/ni.c

911

u32 disabled_rb_mask;

sys/dev/drm/radeon/ni_dma.c

102

u32 reg;

sys/dev/drm/radeon/ni_dma.c

127

u32 next_rptr = ring->wptr + 4;

sys/dev/drm/radeon/ni_dma.c

157

u32 rb_cntl;

sys/dev/drm/radeon/ni_dma.c

188

u32 rb_cntl, dma_cntl, ib_cntl;

sys/dev/drm/radeon/ni_dma.c

189

u32 rb_bufsz;

sys/dev/drm/radeon/ni_dma.c

190

u32 reg_offset, wb_offset;

sys/dev/drm/radeon/ni_dma.c

287

u32 reset_mask = cayman_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/ni_dma.c

288

u32 mask;

sys/dev/drm/radeon/ni_dma.c

54

u32 rptr, reg;

sys/dev/drm/radeon/ni_dma.c

81

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

1037

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/radeon/ni_dpm.c

1082

u32 tmp;

sys/dev/drm/radeon/ni_dpm.c

1102

u32 tmp;

sys/dev/drm/radeon/ni_dpm.c

1222

u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;

sys/dev/drm/radeon/ni_dpm.c

1223

u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit;

sys/dev/drm/radeon/ni_dpm.c

1224

u32 reference_clock;

sys/dev/drm/radeon/ni_dpm.c

1228

voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;

sys/dev/drm/radeon/ni_dpm.c

1229

backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;

sys/dev/drm/radeon/ni_dpm.c

1321

u32 mclk,

sys/dev/drm/radeon/ni_dpm.c

1347

((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))

sys/dev/drm/radeon/ni_dpm.c

1363

static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)

sys/dev/drm/radeon/ni_dpm.c

1365

u32 xclk_period;

sys/dev/drm/radeon/ni_dpm.c

1366

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/ni_dpm.c

1367

u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;

sys/dev/drm/radeon/ni_dpm.c

1375

static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)

sys/dev/drm/radeon/ni_dpm.c

1380

static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,

sys/dev/drm/radeon/ni_dpm.c

1382

u32 near_tdp_limit)

sys/dev/drm/radeon/ni_dpm.c

1387

u32 power_boost_limit = 0;

sys/dev/drm/radeon/ni_dpm.c

1426

power_boost_limit = (u32)tmp;

sys/dev/drm/radeon/ni_dpm.c

1434

u32 tdp_adjustment,

sys/dev/drm/radeon/ni_dpm.c

1435

u32 *tdp_limit,

sys/dev/drm/radeon/ni_dpm.c

1436

u32 *near_tdp_limit)

sys/dev/drm/radeon/ni_dpm.c

1438

if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)

sys/dev/drm/radeon/ni_dpm.c

1460

u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);

sys/dev/drm/radeon/ni_dpm.c

1461

u32 tdp_limit;

sys/dev/drm/radeon/ni_dpm.c

1462

u32 near_tdp_limit;

sys/dev/drm/radeon/ni_dpm.c

1463

u32 power_boost_limit;

sys/dev/drm/radeon/ni_dpm.c

1496

sizeof(u32) * 4, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1505

u32 arb_freq_src, u32 arb_freq_dest)

sys/dev/drm/radeon/ni_dpm.c

1507

u32 mc_arb_dram_timing;

sys/dev/drm/radeon/ni_dpm.c

1508

u32 mc_arb_dram_timing2;

sys/dev/drm/radeon/ni_dpm.c

1509

u32 burst_time;

sys/dev/drm/radeon/ni_dpm.c

1510

u32 mc_cg_config;

sys/dev/drm/radeon/ni_dpm.c

1573

u32 tmp;

sys/dev/drm/radeon/ni_dpm.c

1582

tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;

sys/dev/drm/radeon/ni_dpm.c

1597

u32 tmp;

sys/dev/drm/radeon/ni_dpm.c

1617

u32 dram_timing;

sys/dev/drm/radeon/ni_dpm.c

1618

u32 dram_timing2;

sys/dev/drm/radeon/ni_dpm.c

1687

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

1796

u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/radeon/ni_dpm.c

1797

u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.c

1798

u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/radeon/ni_dpm.c

1799

u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.c

1800

u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/radeon/ni_dpm.c

1801

u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.c

1802

u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/ni_dpm.c

1803

u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/ni_dpm.c

1804

u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ni_dpm.c

1805

u32 dll_cntl = ni_pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/ni_dpm.c

1806

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

1997

u32 engine_clock,

sys/dev/drm/radeon/ni_dpm.c

2003

u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/radeon/ni_dpm.c

2004

u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.c

2005

u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/ni_dpm.c

2006

u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/ni_dpm.c

2007

u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/radeon/ni_dpm.c

2008

u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ni_dpm.c

2010

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ni_dpm.c

2011

u32 reference_divider;

sys/dev/drm/radeon/ni_dpm.c

2012

u32 fbdiv;

sys/dev/drm/radeon/ni_dpm.c

2025

fbdiv = (u32) tmp;

sys/dev/drm/radeon/ni_dpm.c

2040

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/ni_dpm.c

2044

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/ni_dpm.c

2045

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/radeon/ni_dpm.c

2068

u32 engine_clock,

sys/dev/drm/radeon/ni_dpm.c

2094

u32 fb_div;

sys/dev/drm/radeon/ni_dpm.c

2095

u32 p_div;

sys/dev/drm/radeon/ni_dpm.c

2096

u32 clk_s;

sys/dev/drm/radeon/ni_dpm.c

2097

u32 clk_v;

sys/dev/drm/radeon/ni_dpm.c

2098

u32 sclk = 0;

sys/dev/drm/radeon/ni_dpm.c

2100

u32 tmp;

sys/dev/drm/radeon/ni_dpm.c

2159

u32 engine_clock,

sys/dev/drm/radeon/ni_dpm.c

2160

u32 memory_clock,

sys/dev/drm/radeon/ni_dpm.c

2167

u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/radeon/ni_dpm.c

2168

u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.c

2169

u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/radeon/ni_dpm.c

2170

u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.c

2171

u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ni_dpm.c

2172

u32 dll_cntl = ni_pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/ni_dpm.c

2173

u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;

sys/dev/drm/radeon/ni_dpm.c

2174

u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;

sys/dev/drm/radeon/ni_dpm.c

2176

u32 ibias;

sys/dev/drm/radeon/ni_dpm.c

2177

u32 dll_speed;

sys/dev/drm/radeon/ni_dpm.c

2179

u32 mc_seq_misc7;

sys/dev/drm/radeon/ni_dpm.c

2236

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/drm/radeon/ni_dpm.c

2240

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/ni_dpm.c

2241

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/drm/radeon/ni_dpm.c

2242

u32 clk_s, clk_v;

sys/dev/drm/radeon/ni_dpm.c

2321

u32 tmp = RREG32(DC_STUTTER_CNTL);

sys/dev/drm/radeon/ni_dpm.c

2399

u32 a_t;

sys/dev/drm/radeon/ni_dpm.c

2400

u32 t_l, t_h;

sys/dev/drm/radeon/ni_dpm.c

2401

u32 high_bsp;

sys/dev/drm/radeon/ni_dpm.c

2460

u32 prev_sclk;

sys/dev/drm/radeon/ni_dpm.c

2461

u32 max_sclk;

sys/dev/drm/radeon/ni_dpm.c

2462

u32 min_sclk;

sys/dev/drm/radeon/ni_dpm.c

2464

u32 tdp_limit;

sys/dev/drm/radeon/ni_dpm.c

2465

u32 near_tdp_limit;

sys/dev/drm/radeon/ni_dpm.c

2466

u32 power_boost_limit;

sys/dev/drm/radeon/ni_dpm.c

250

static const u32 cayman_cgcg_cgls_default[] =

sys/dev/drm/radeon/ni_dpm.c

2517

min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;

sys/dev/drm/radeon/ni_dpm.c

2544

u32 sq_power_throttle;

sys/dev/drm/radeon/ni_dpm.c

2545

u32 sq_power_throttle2;

sys/dev/drm/radeon/ni_dpm.c

2634

u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100;

sys/dev/drm/radeon/ni_dpm.c

2716

u32 temp_reg;

sys/dev/drm/radeon/ni_dpm.c

2836

u32 i;

sys/dev/drm/radeon/ni_dpm.c

2926

u32 i, j;

sys/dev/drm/radeon/ni_dpm.c

2945

u32 num_entries, u32 valid_flag)

sys/dev/drm/radeon/ni_dpm.c

2947

u32 i, j;

sys/dev/drm/radeon/ni_dpm.c

2962

u32 i = 0;

sys/dev/drm/radeon/ni_dpm.c

301

#define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

303

static const u32 cayman_cgcg_cgls_disable[] =

sys/dev/drm/radeon/ni_dpm.c

3051

u32 leakage = 0;

sys/dev/drm/radeon/ni_dpm.c

3054

u32 smc_leakage, max_leakage = 0;

sys/dev/drm/radeon/ni_dpm.c

3055

u32 scaling_factor;

sys/dev/drm/radeon/ni_dpm.c

3099

u32 i, j, table_size;

sys/dev/drm/radeon/ni_dpm.c

3100

u32 smc_leakage, max_leakage = 0;

sys/dev/drm/radeon/ni_dpm.c

3101

u32 scaling_factor;

sys/dev/drm/radeon/ni_dpm.c

3145

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

3211

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

3442

u32 tmp;

sys/dev/drm/radeon/ni_dpm.c

3462

u32 tmp, bif;

sys/dev/drm/radeon/ni_dpm.c

356

#define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

358

static const u32 cayman_cgcg_cgls_enable[] =

sys/dev/drm/radeon/ni_dpm.c

410

#define CAYMAN_CGCG_CGLS_ENABLE_LENGTH sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

412

static const u32 cayman_mgcg_default[] =

sys/dev/drm/radeon/ni_dpm.c

4308

u32 current_index =

sys/dev/drm/radeon/ni_dpm.c

4322

u32 ni_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/ni_dpm.c

4328

u32 current_index =

sys/dev/drm/radeon/ni_dpm.c

4340

u32 ni_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/ni_dpm.c

4346

u32 current_index =

sys/dev/drm/radeon/ni_dpm.c

4358

u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/ni_dpm.c

4369

u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/ni_dpm.c

615

#define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

617

static const u32 cayman_mgcg_disable[] =

sys/dev/drm/radeon/ni_dpm.c

630

#define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

632

static const u32 cayman_mgcg_enable[] =

sys/dev/drm/radeon/ni_dpm.c

646

#define CAYMAN_MGCG_ENABLE_LENGTH sizeof(cayman_mgcg_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

650

static const u32 cayman_sysls_default[] =

sys/dev/drm/radeon/ni_dpm.c

671

#define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

673

static const u32 cayman_sysls_disable[] =

sys/dev/drm/radeon/ni_dpm.c

696

#define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

698

static const u32 cayman_sysls_enable[] =

sys/dev/drm/radeon/ni_dpm.c

719

#define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32))

sys/dev/drm/radeon/ni_dpm.c

742

u32 ileakage,

sys/dev/drm/radeon/ni_dpm.c

743

u32 *leakage)

sys/dev/drm/radeon/ni_dpm.c

765

u32 i_leakage,

sys/dev/drm/radeon/ni_dpm.c

766

u32 *leakage)

sys/dev/drm/radeon/ni_dpm.c

774

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/drm/radeon/ni_dpm.c

776

u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

sys/dev/drm/radeon/ni_dpm.c

791

u32 mclk;

sys/dev/drm/radeon/ni_dpm.c

906

u32 count;

sys/dev/drm/radeon/ni_dpm.c

907

const u32 *ps = NULL;

sys/dev/drm/radeon/ni_dpm.c

909

ps = (const u32 *)&cayman_cgcg_cgls_default;

sys/dev/drm/radeon/ni_dpm.c

918

u32 count;

sys/dev/drm/radeon/ni_dpm.c

919

const u32 *ps = NULL;

sys/dev/drm/radeon/ni_dpm.c

922

ps = (const u32 *)&cayman_cgcg_cgls_enable;

sys/dev/drm/radeon/ni_dpm.c

925

ps = (const u32 *)&cayman_cgcg_cgls_disable;

sys/dev/drm/radeon/ni_dpm.c

934

u32 count;

sys/dev/drm/radeon/ni_dpm.c

935

const u32 *ps = NULL;

sys/dev/drm/radeon/ni_dpm.c

937

ps = (const u32 *)&cayman_mgcg_default;

sys/dev/drm/radeon/ni_dpm.c

946

u32 count;

sys/dev/drm/radeon/ni_dpm.c

947

const u32 *ps = NULL;

sys/dev/drm/radeon/ni_dpm.c

950

ps = (const u32 *)&cayman_mgcg_enable;

sys/dev/drm/radeon/ni_dpm.c

953

ps = (const u32 *)&cayman_mgcg_disable;

sys/dev/drm/radeon/ni_dpm.c

962

u32 count;

sys/dev/drm/radeon/ni_dpm.c

963

const u32 *ps = NULL;

sys/dev/drm/radeon/ni_dpm.c

965

ps = (const u32 *)&cayman_sysls_default;

sys/dev/drm/radeon/ni_dpm.c

974

u32 count;

sys/dev/drm/radeon/ni_dpm.c

975

const u32 *ps = NULL;

sys/dev/drm/radeon/ni_dpm.c

978

ps = (const u32 *)&cayman_sysls_enable;

sys/dev/drm/radeon/ni_dpm.c

981

ps = (const u32 *)&cayman_sysls_disable;

sys/dev/drm/radeon/ni_dpm.c

993

u32 i;

sys/dev/drm/radeon/ni_dpm.h

105

u32 weight_tcp_sig0;

sys/dev/drm/radeon/ni_dpm.h

106

u32 weight_tcp_sig1;

sys/dev/drm/radeon/ni_dpm.h

107

u32 weight_ta_sig;

sys/dev/drm/radeon/ni_dpm.h

108

u32 weight_tcc_en0;

sys/dev/drm/radeon/ni_dpm.h

109

u32 weight_tcc_en1;

sys/dev/drm/radeon/ni_dpm.h

110

u32 weight_tcc_en2;

sys/dev/drm/radeon/ni_dpm.h

111

u32 weight_cb_en0;

sys/dev/drm/radeon/ni_dpm.h

112

u32 weight_cb_en1;

sys/dev/drm/radeon/ni_dpm.h

113

u32 weight_cb_en2;

sys/dev/drm/radeon/ni_dpm.h

114

u32 weight_cb_en3;

sys/dev/drm/radeon/ni_dpm.h

115

u32 weight_db_sig0;

sys/dev/drm/radeon/ni_dpm.h

116

u32 weight_db_sig1;

sys/dev/drm/radeon/ni_dpm.h

117

u32 weight_db_sig2;

sys/dev/drm/radeon/ni_dpm.h

118

u32 weight_db_sig3;

sys/dev/drm/radeon/ni_dpm.h

119

u32 weight_sxm_sig0;

sys/dev/drm/radeon/ni_dpm.h

120

u32 weight_sxm_sig1;

sys/dev/drm/radeon/ni_dpm.h

121

u32 weight_sxm_sig2;

sys/dev/drm/radeon/ni_dpm.h

122

u32 weight_sxs_sig0;

sys/dev/drm/radeon/ni_dpm.h

123

u32 weight_sxs_sig1;

sys/dev/drm/radeon/ni_dpm.h

124

u32 weight_xbr_0;

sys/dev/drm/radeon/ni_dpm.h

125

u32 weight_xbr_1;

sys/dev/drm/radeon/ni_dpm.h

126

u32 weight_xbr_2;

sys/dev/drm/radeon/ni_dpm.h

127

u32 weight_spi_sig0;

sys/dev/drm/radeon/ni_dpm.h

128

u32 weight_spi_sig1;

sys/dev/drm/radeon/ni_dpm.h

129

u32 weight_spi_sig2;

sys/dev/drm/radeon/ni_dpm.h

130

u32 weight_spi_sig3;

sys/dev/drm/radeon/ni_dpm.h

131

u32 weight_spi_sig4;

sys/dev/drm/radeon/ni_dpm.h

132

u32 weight_spi_sig5;

sys/dev/drm/radeon/ni_dpm.h

133

u32 weight_lds_sig0;

sys/dev/drm/radeon/ni_dpm.h

134

u32 weight_lds_sig1;

sys/dev/drm/radeon/ni_dpm.h

135

u32 weight_sc;

sys/dev/drm/radeon/ni_dpm.h

136

u32 weight_bif;

sys/dev/drm/radeon/ni_dpm.h

137

u32 weight_cp;

sys/dev/drm/radeon/ni_dpm.h

138

u32 weight_pa_sig0;

sys/dev/drm/radeon/ni_dpm.h

139

u32 weight_pa_sig1;

sys/dev/drm/radeon/ni_dpm.h

140

u32 weight_vgt_sig0;

sys/dev/drm/radeon/ni_dpm.h

141

u32 weight_vgt_sig1;

sys/dev/drm/radeon/ni_dpm.h

142

u32 weight_vgt_sig2;

sys/dev/drm/radeon/ni_dpm.h

143

u32 weight_dc_sig0;

sys/dev/drm/radeon/ni_dpm.h

144

u32 weight_dc_sig1;

sys/dev/drm/radeon/ni_dpm.h

145

u32 weight_dc_sig2;

sys/dev/drm/radeon/ni_dpm.h

146

u32 weight_dc_sig3;

sys/dev/drm/radeon/ni_dpm.h

147

u32 weight_uvd_sig0;

sys/dev/drm/radeon/ni_dpm.h

148

u32 weight_uvd_sig1;

sys/dev/drm/radeon/ni_dpm.h

149

u32 weight_spare0;

sys/dev/drm/radeon/ni_dpm.h

150

u32 weight_spare1;

sys/dev/drm/radeon/ni_dpm.h

151

u32 weight_sq_vsp;

sys/dev/drm/radeon/ni_dpm.h

152

u32 weight_sq_vsp0;

sys/dev/drm/radeon/ni_dpm.h

153

u32 weight_sq_gpr;

sys/dev/drm/radeon/ni_dpm.h

154

u32 ovr_mode_spare_0;

sys/dev/drm/radeon/ni_dpm.h

155

u32 ovr_val_spare_0;

sys/dev/drm/radeon/ni_dpm.h

156

u32 ovr_mode_spare_1;

sys/dev/drm/radeon/ni_dpm.h

157

u32 ovr_val_spare_1;

sys/dev/drm/radeon/ni_dpm.h

158

u32 vsp;

sys/dev/drm/radeon/ni_dpm.h

159

u32 vsp0;

sys/dev/drm/radeon/ni_dpm.h

160

u32 gpr;

sys/dev/drm/radeon/ni_dpm.h

163

u32 tid_cnt;

sys/dev/drm/radeon/ni_dpm.h

164

u32 tid_unit;

sys/dev/drm/radeon/ni_dpm.h

165

u32 l2_lta_window_size;

sys/dev/drm/radeon/ni_dpm.h

166

u32 lts_truncate;

sys/dev/drm/radeon/ni_dpm.h

167

u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/drm/radeon/ni_dpm.h

168

u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];

sys/dev/drm/radeon/ni_dpm.h

183

u32 mclk_rtt_mode_threshold;

sys/dev/drm/radeon/ni_dpm.h

201

u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/drm/radeon/ni_dpm.h

235

u32 arb_freq_src, u32 arb_freq_dest);

sys/dev/drm/radeon/ni_dpm.h

31

u32 cg_spll_func_cntl;

sys/dev/drm/radeon/ni_dpm.h

32

u32 cg_spll_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.h

33

u32 cg_spll_func_cntl_3;

sys/dev/drm/radeon/ni_dpm.h

34

u32 cg_spll_func_cntl_4;

sys/dev/drm/radeon/ni_dpm.h

35

u32 cg_spll_spread_spectrum;

sys/dev/drm/radeon/ni_dpm.h

36

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ni_dpm.h

37

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ni_dpm.h

38

u32 dll_cntl;

sys/dev/drm/radeon/ni_dpm.h

39

u32 mpll_ad_func_cntl;

sys/dev/drm/radeon/ni_dpm.h

40

u32 mpll_ad_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.h

41

u32 mpll_dq_func_cntl;

sys/dev/drm/radeon/ni_dpm.h

42

u32 mpll_dq_func_cntl_2;

sys/dev/drm/radeon/ni_dpm.h

43

u32 mpll_ss1;

sys/dev/drm/radeon/ni_dpm.h

44

u32 mpll_ss2;

sys/dev/drm/radeon/ni_dpm.h

48

u32 mclk_max;

sys/dev/drm/radeon/ni_dpm.h

49

u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/ni_dpm.h

77

u32 at;

sys/dev/drm/radeon/ni_dpm.h

78

u32 bt;

sys/dev/drm/radeon/ni_dpm.h

79

u32 av;

sys/dev/drm/radeon/ni_dpm.h

80

u32 bv;

sys/dev/drm/radeon/ni_dpm.h

83

u32 t_ref;

sys/dev/drm/radeon/ni_dpm.h

89

u32 i_leakage;

sys/dev/drm/radeon/ni_dpm.h

91

u32 pwr_const;

sys/dev/drm/radeon/ni_dpm.h

92

u32 dc_cac_value;

sys/dev/drm/radeon/ni_dpm.h

93

u32 bif_cac_value;

sys/dev/drm/radeon/ni_dpm.h

94

u32 lkge_pwr;

sys/dev/drm/radeon/r100.c

1058

u32 r100_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/r100.c

1061

u32 rptr;

sys/dev/drm/radeon/r100.c

1071

u32 r100_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/r100.c

1275

u32 tile_flags = 0;

sys/dev/drm/radeon/r100.c

1276

u32 tmp;

sys/dev/drm/radeon/r100.c

1278

u32 value;

sys/dev/drm/radeon/r100.c

1290

tmp += (((u32)reloc->gpu_offset) >> 10);

sys/dev/drm/radeon/r100.c

1320

u32 idx_value;

sys/dev/drm/radeon/r100.c

1341

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1353

ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1367

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1571

u32 tile_flags = 0;

sys/dev/drm/radeon/r100.c

1572

u32 idx_value;

sys/dev/drm/radeon/r100.c

159

u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;

sys/dev/drm/radeon/r100.c

1608

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1621

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1642

ib[idx] = tmp + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1644

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1662

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1680

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1698

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1786

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1907

u32 value;

sys/dev/drm/radeon/r100.c

1945

ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1959

ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

2530

u32 rbbm_status;

sys/dev/drm/radeon/r100.c

2551

u32 tmp;

sys/dev/drm/radeon/r100.c

2569

u32 status, tmp;

sys/dev/drm/radeon/r100.c

2626

u32 tmp;

sys/dev/drm/radeon/r100.c

2668

u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);

sys/dev/drm/radeon/r100.c

2669

u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

sys/dev/drm/radeon/r100.c

2670

u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);

sys/dev/drm/radeon/r100.c

2744

static u32 r100_get_accessible_vram(struct radeon_device *rdev)

sys/dev/drm/radeon/r100.c

2746

u32 aper_size;

sys/dev/drm/radeon/r100.c

3230

u32 lb_size = 8192;

sys/dev/drm/radeon/r100.c

350

u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;

sys/dev/drm/radeon/r100.c

3559

u32 grph2_cntl;

sys/dev/drm/radeon/r100.c

3706

u32 next_rptr = ring->wptr + 2 + 3;

sys/dev/drm/radeon/r100.c

3841

u32 tmp;

sys/dev/drm/radeon/r100.c

3888

u32 tmp;

sys/dev/drm/radeon/r100.c

4024

u32 tmp;

sys/dev/drm/radeon/r100.c

4147

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r100.c

4157

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r100.c

448

u32 tmp;

sys/dev/drm/radeon/r100.c

479

u32 tmp;

sys/dev/drm/radeon/r100.c

554

u32 tmp;

sys/dev/drm/radeon/r100.c

695

u32 *gtt = rdev->gart.ptr;

sys/dev/drm/radeon/r100.c

742

u32 tmp;

sys/dev/drm/radeon/r100.c

828

u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)

sys/dev/drm/radeon/r100.c

88

u32 vline1, vline2;

sys/dev/drm/radeon/r100.c

964

u32 tmp;

sys/dev/drm/radeon/r200.c

156

u32 tile_flags = 0;

sys/dev/drm/radeon/r200.c

157

u32 idx_value;

sys/dev/drm/radeon/r200.c

191

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r200.c

204

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r200.c

228

ib[idx] = tmp + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r200.c

230

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r200.c

274

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r200.c

368

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

1081

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

1126

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

1191

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

1356

u32 tmp;

sys/dev/drm/radeon/r300.c

185

u32 tmp;

sys/dev/drm/radeon/r300.c

409

u32 status, tmp;

sys/dev/drm/radeon/r300.c

469

u32 tmp;

sys/dev/drm/radeon/r300.c

553

u32 link_width_cntl;

sys/dev/drm/radeon/r300.c

631

u32 idx_value;

sys/dev/drm/radeon/r300.c

669

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

682

ib[idx] = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

711

((idx_value & ~31) + (u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

720

tmp = idx_value + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r420.c

158

u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r420.c

161

u32 r;

sys/dev/drm/radeon/r420.c

170

void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r420.c

193

u32 sclk_cntl;

sys/dev/drm/radeon/r600.c

1067

u32 tmp;

sys/dev/drm/radeon/r600.c

1073

u32 tmp;

sys/dev/drm/radeon/r600.c

110

u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r600.c

1121

u32 tmp;

sys/dev/drm/radeon/r600.c

113

u32 r;

sys/dev/drm/radeon/r600.c

1165

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/r600.c

1179

u32 tmp;

sys/dev/drm/radeon/r600.c

122

void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r600.c

1221

u32 tmp;

sys/dev/drm/radeon/r600.c

1256

u32 tmp;

sys/dev/drm/radeon/r600.c

1296

u32 tmp;

sys/dev/drm/radeon/r600.c

132

u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r600.c

135

u32 r;

sys/dev/drm/radeon/r600.c

1426

u32 tmp;

sys/dev/drm/radeon/r600.c

144

void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r600.c

1547

u32 tmp = RREG32(R600_BIOS_3_SCRATCH);

sys/dev/drm/radeon/r600.c

1579

u32 crtc_hung = 0;

sys/dev/drm/radeon/r600.c

1580

u32 crtc_status[2];

sys/dev/drm/radeon/r600.c

1581

u32 i, j, tmp;

sys/dev/drm/radeon/r600.c

1606

u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/drm/radeon/r600.c

1608

u32 reset_mask = 0;

sys/dev/drm/radeon/r600.c

1609

u32 tmp;

sys/dev/drm/radeon/r600.c

165

u32 reg, u32 *val)

sys/dev/drm/radeon/r600.c

1675

static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/drm/radeon/r600.c

1678

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/radeon/r600.c

1679

u32 tmp;

sys/dev/drm/radeon/r600.c

1814

u32 tmp, i;

sys/dev/drm/radeon/r600.c

1874

u32 reset_mask;

sys/dev/drm/radeon/r600.c

188

u32 r600_get_xclk(struct radeon_device *rdev)

sys/dev/drm/radeon/r600.c

1914

u32 reset_mask = r600_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/r600.c

1925

u32 r6xx_remap_render_backend(struct radeon_device *rdev,

sys/dev/drm/radeon/r600.c

1926

u32 tiling_pipe_num,

sys/dev/drm/radeon/r600.c

1927

u32 max_rb_num,

sys/dev/drm/radeon/r600.c

1928

u32 total_max_rb_num,

sys/dev/drm/radeon/r600.c

1929

u32 disabled_rb_mask)

sys/dev/drm/radeon/r600.c

193

int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/drm/radeon/r600.c

1931

u32 rendering_pipe_num, rb_num_width, req_rb_num;

sys/dev/drm/radeon/r600.c

1932

u32 pipe_rb_ratio, pipe_rb_remain, tmp;

sys/dev/drm/radeon/r600.c

1933

u32 data = 0, mask = 1 << (max_rb_num - 1);

sys/dev/drm/radeon/r600.c

1982

u32 tiling_config;

sys/dev/drm/radeon/r600.c

1983

u32 ramcfg;

sys/dev/drm/radeon/r600.c

1984

u32 cc_gc_shader_pipe_config;

sys/dev/drm/radeon/r600.c

1985

u32 tmp;

sys/dev/drm/radeon/r600.c

1987

u32 sq_config;

sys/dev/drm/radeon/r600.c

1988

u32 sq_gpr_resource_mgmt_1 = 0;

sys/dev/drm/radeon/r600.c

1989

u32 sq_gpr_resource_mgmt_2 = 0;

sys/dev/drm/radeon/r600.c

1990

u32 sq_thread_resource_mgmt = 0;

sys/dev/drm/radeon/r600.c

1991

u32 sq_stack_resource_mgmt_1 = 0;

sys/dev/drm/radeon/r600.c

1992

u32 sq_stack_resource_mgmt_2 = 0;

sys/dev/drm/radeon/r600.c

1993

u32 disabled_rb_mask;

sys/dev/drm/radeon/r600.c

2386

u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r600.c

2389

u32 r;

sys/dev/drm/radeon/r600.c

2399

void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r600.c

2607

u32 r600_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/r600.c

2610

u32 rptr;

sys/dev/drm/radeon/r600.c

2620

u32 r600_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/r600.c

2728

u32 tmp;

sys/dev/drm/radeon/r600.c

2729

u32 rb_bufsz;

sys/dev/drm/radeon/r600.c

2791

u32 rb_bufsz;

sys/dev/drm/radeon/r600.c

2880

u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |

sys/dev/drm/radeon/r600.c

294

u32 tmp = 0;

sys/dev/drm/radeon/r600.c

2982

u32 size_in_bytes, cur_size_in_bytes, tmp;

sys/dev/drm/radeon/r600.c

3383

u32 next_rptr;

sys/dev/drm/radeon/r600.c

342

u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>

sys/dev/drm/radeon/r600.c

3482

u32 rb_bufsz;

sys/dev/drm/radeon/r600.c

3567

u32 i;

sys/dev/drm/radeon/r600.c

3606

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/r600.c

3607

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/r600.c

3618

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/r600.c

3619

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/r600.c

3634

u32 tmp;

sys/dev/drm/radeon/r600.c

3689

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/drm/radeon/r600.c

3777

u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;

sys/dev/drm/radeon/r600.c

3778

u32 mode_int = 0;

sys/dev/drm/radeon/r600.c

3779

u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;

sys/dev/drm/radeon/r600.c

3780

u32 grbm_int_cntl = 0;

sys/dev/drm/radeon/r600.c

3781

u32 hdmi0, hdmi1;

sys/dev/drm/radeon/r600.c

3782

u32 dma_cntl;

sys/dev/drm/radeon/r600.c

3783

u32 thermal_int = 0;

sys/dev/drm/radeon/r600.c

3928

u32 tmp;

sys/dev/drm/radeon/r600.c

4051

static u32 r600_get_ih_wptr(struct radeon_device *rdev)

sys/dev/drm/radeon/r600.c

4053

u32 wptr, tmp;

sys/dev/drm/radeon/r600.c

4108

u32 wptr;

sys/dev/drm/radeon/r600.c

4109

u32 rptr;

sys/dev/drm/radeon/r600.c

4110

u32 src_id, src_data;

sys/dev/drm/radeon/r600.c

4111

u32 ring_index;

sys/dev/drm/radeon/r600.c

4404

u32 tmp;

sys/dev/drm/radeon/r600.c

4414

u32 link_width_cntl, mask;

sys/dev/drm/radeon/r600.c

4467

u32 link_width_cntl;

sys/dev/drm/radeon/r600.c

4504

u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;

sys/dev/drm/radeon/r600.c

852

u32 tmp;

sys/dev/drm/radeon/r600.c

94

static const u32 crtc_offsets[2] =

sys/dev/drm/radeon/r600.c

959

u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);

sys/dev/drm/radeon/r600_blit_shaders.c

367

const u32 r7xx_default_state[] =

sys/dev/drm/radeon/r600_blit_shaders.c

41

const u32 r6xx_default_state[] =

sys/dev/drm/radeon/r600_blit_shaders.c

684

const u32 r6xx_vs[] =

sys/dev/drm/radeon/r600_blit_shaders.c

704

const u32 r6xx_ps[] =

sys/dev/drm/radeon/r600_blit_shaders.c

716

const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);

sys/dev/drm/radeon/r600_blit_shaders.c

717

const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);

sys/dev/drm/radeon/r600_blit_shaders.c

718

const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);

sys/dev/drm/radeon/r600_blit_shaders.c

719

const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);

sys/dev/drm/radeon/r600_blit_shaders.h

29

extern const u32 r6xx_ps[];

sys/dev/drm/radeon/r600_blit_shaders.h

30

extern const u32 r6xx_vs[];

sys/dev/drm/radeon/r600_blit_shaders.h

31

extern const u32 r7xx_default_state[];

sys/dev/drm/radeon/r600_blit_shaders.h

32

extern const u32 r6xx_default_state[];

sys/dev/drm/radeon/r600_blit_shaders.h

35

extern const u32 r6xx_ps_size, r6xx_vs_size;

sys/dev/drm/radeon/r600_blit_shaders.h

36

extern const u32 r6xx_default_size, r7xx_default_size;

sys/dev/drm/radeon/r600_cs.c

1023

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1085

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1106

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1215

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1246

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1282

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1296

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1309

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1378

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1387

ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1469

static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,

sys/dev/drm/radeon/r600_cs.c

1474

u32 tiling_flags)

sys/dev/drm/radeon/r600_cs.c

1477

u32 dim, nfaces, llevel, blevel, w0, h0, d0;

sys/dev/drm/radeon/r600_cs.c

1478

u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;

sys/dev/drm/radeon/r600_cs.c

1479

u32 height_align, pitch, pitch_align, depth_align;

sys/dev/drm/radeon/r600_cs.c

1480

u32 barray, larray;

sys/dev/drm/radeon/r600_cs.c

1483

u32 format;

sys/dev/drm/radeon/r600_cs.c

1610

static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/drm/radeon/r600_cs.c

1612

u32 m, i;

sys/dev/drm/radeon/r600_cs.c

1631

volatile u32 *ib;

sys/dev/drm/radeon/r600_cs.c

1636

u32 idx_value;

sys/dev/drm/radeon/r600_cs.c

1779

u32 command, size;

sys/dev/drm/radeon/r600_cs.c

178

bool r600_fmt_is_valid_color(u32 format)

sys/dev/drm/radeon/r600_cs.c

1862

ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

189

bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)

sys/dev/drm/radeon/r600_cs.c

1955

u32 size, offset, base_offset, mip_offset;

sys/dev/drm/radeon/r600_cs.c

1965

base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

1979

mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

203

int r600_fmt_get_blocksize(u32 format)

sys/dev/drm/radeon/r600_cs.c

211

int r600_fmt_get_nblocksx(u32 format, u32 w)

sys/dev/drm/radeon/r600_cs.c

2119

ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);

sys/dev/drm/radeon/r600_cs.c

225

int r600_fmt_get_nblocksy(u32 format, u32 h)

sys/dev/drm/radeon/r600_cs.c

2382

u32 header, cmd, count, tiled;

sys/dev/drm/radeon/r600_cs.c

2383

volatile u32 *ib = p->ib.ptr;

sys/dev/drm/radeon/r600_cs.c

2384

u32 idx, idx_value;

sys/dev/drm/radeon/r600_cs.c

241

u32 group_size;

sys/dev/drm/radeon/r600_cs.c

2411

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/r600_cs.c

2417

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

242

u32 nbanks;

sys/dev/drm/radeon/r600_cs.c

243

u32 npipes;

sys/dev/drm/radeon/r600_cs.c

244

u32 nsamples;

sys/dev/drm/radeon/r600_cs.c

2445

ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/r600_cs.c

2449

ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

245

u32 blocksize;

sys/dev/drm/radeon/r600_cs.c

2455

ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

2460

ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);

sys/dev/drm/radeon/r600_cs.c

2470

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

2471

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

2481

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

2482

ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

250

u32 *pitch_align,

sys/dev/drm/radeon/r600_cs.c

251

u32 *height_align,

sys/dev/drm/radeon/r600_cs.c

2516

ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);

sys/dev/drm/radeon/r600_cs.c

252

u32 *depth_align,

sys/dev/drm/radeon/r600_cs.c

255

u32 tile_width = 8;

sys/dev/drm/radeon/r600_cs.c

256

u32 tile_height = 8;

sys/dev/drm/radeon/r600_cs.c

257

u32 macro_tile_width = values->nbanks;

sys/dev/drm/radeon/r600_cs.c

258

u32 macro_tile_height = values->npipes;

sys/dev/drm/radeon/r600_cs.c

259

u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;

sys/dev/drm/radeon/r600_cs.c

260

u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;

sys/dev/drm/radeon/r600_cs.c

271

*pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));

sys/dev/drm/radeon/r600_cs.c

277

*pitch_align = max((u32)tile_width,

sys/dev/drm/radeon/r600_cs.c

278

(u32)(values->group_size /

sys/dev/drm/radeon/r600_cs.c

285

*pitch_align = max((u32)macro_tile_width * tile_width,

sys/dev/drm/radeon/r600_cs.c

286

(u32)((values->group_size * values->nbanks) /

sys/dev/drm/radeon/r600_cs.c

353

u32 slice_tile_max, size, tmp;

sys/dev/drm/radeon/r600_cs.c

354

u32 height, height_align, pitch, pitch_align, depth_align;

sys/dev/drm/radeon/r600_cs.c

357

volatile u32 *ib = p->ib.ptr;

sys/dev/drm/radeon/r600_cs.c

359

u32 format;

sys/dev/drm/radeon/r600_cs.c

36

extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);

sys/dev/drm/radeon/r600_cs.c

41

u32 group_size;

sys/dev/drm/radeon/r600_cs.c

42

u32 nbanks;

sys/dev/drm/radeon/r600_cs.c

43

u32 npipes;

sys/dev/drm/radeon/r600_cs.c

45

u32 sq_config;

sys/dev/drm/radeon/r600_cs.c

46

u32 log_nsamples;

sys/dev/drm/radeon/r600_cs.c

47

u32 nsamples;

sys/dev/drm/radeon/r600_cs.c

48

u32 cb_color_base_last[8];

sys/dev/drm/radeon/r600_cs.c

520

u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;

sys/dev/drm/radeon/r600_cs.c

521

u32 height_align, pitch_align, depth_align;

sys/dev/drm/radeon/r600_cs.c

522

u32 pitch = 8192;

sys/dev/drm/radeon/r600_cs.c

523

u32 height = 8192;

sys/dev/drm/radeon/r600_cs.c

527

volatile u32 *ib = p->ib.ptr;

sys/dev/drm/radeon/r600_cs.c

56

u32 cb_color_mask[8];

sys/dev/drm/radeon/r600_cs.c

57

u32 cb_color_info[8];

sys/dev/drm/radeon/r600_cs.c

58

u32 cb_color_view[8];

sys/dev/drm/radeon/r600_cs.c

59

u32 cb_color_size_idx[8]; /* unused */

sys/dev/drm/radeon/r600_cs.c

60

u32 cb_target_mask;

sys/dev/drm/radeon/r600_cs.c

61

u32 cb_shader_mask; /* unused */

sys/dev/drm/radeon/r600_cs.c

63

u32 cb_color_size[8];

sys/dev/drm/radeon/r600_cs.c

64

u32 vgt_strmout_en;

sys/dev/drm/radeon/r600_cs.c

65

u32 vgt_strmout_buffer_en;

sys/dev/drm/radeon/r600_cs.c

68

u32 vgt_strmout_bo_offset[4];

sys/dev/drm/radeon/r600_cs.c

69

u32 vgt_strmout_size[4];

sys/dev/drm/radeon/r600_cs.c

70

u32 db_depth_control;

sys/dev/drm/radeon/r600_cs.c

709

u32 tmp;

sys/dev/drm/radeon/r600_cs.c

71

u32 db_depth_info;

sys/dev/drm/radeon/r600_cs.c

72

u32 db_depth_size_idx;

sys/dev/drm/radeon/r600_cs.c

73

u32 db_depth_view;

sys/dev/drm/radeon/r600_cs.c

74

u32 db_depth_size;

sys/dev/drm/radeon/r600_cs.c

75

u32 db_offset;

sys/dev/drm/radeon/r600_cs.c

753

u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);

sys/dev/drm/radeon/r600_cs.c

84

u32 htile_surface;

sys/dev/drm/radeon/r600_cs.c

969

static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/drm/radeon/r600_cs.c

973

u32 m, i, tmp, *ib;

sys/dev/drm/radeon/r600_dma.c

121

u32 rb_cntl, dma_cntl, ib_cntl;

sys/dev/drm/radeon/r600_dma.c

122

u32 rb_bufsz;

sys/dev/drm/radeon/r600_dma.c

208

u32 reset_mask = r600_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/r600_dma.c

234

u32 tmp;

sys/dev/drm/radeon/r600_dma.c

317

u32 s = emit_wait ? 0 : 1;

sys/dev/drm/radeon/r600_dma.c

341

u32 tmp = 0;

sys/dev/drm/radeon/r600_dma.c

408

u32 next_rptr = ring->wptr + 4;

sys/dev/drm/radeon/r600_dma.c

451

u32 size_in_dw, cur_size_in_dw;

sys/dev/drm/radeon/r600_dma.c

52

u32 rptr;

sys/dev/drm/radeon/r600_dma.c

99

u32 rb_cntl = RREG32(DMA_RB_CNTL);

sys/dev/drm/radeon/r600_dpm.c

1039

u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table);

sys/dev/drm/radeon/r600_dpm.c

1092

u32 size = limits->numEntries *

sys/dev/drm/radeon/r600_dpm.c

1146

u32 size = limits->numEntries *

sys/dev/drm/radeon/r600_dpm.c

1178

u32 size = limits->numEntries *

sys/dev/drm/radeon/r600_dpm.c

1236

u32 size = limits->numEntries *

sys/dev/drm/radeon/r600_dpm.c

1318

u32 sys_mask,

sys/dev/drm/radeon/r600_dpm.c

132

void r600_dpm_print_cap_info(u32 caps)

sys/dev/drm/radeon/r600_dpm.c

1363

u8 r600_encode_pci_lane_width(u32 lanes)

sys/dev/drm/radeon/r600_dpm.c

157

u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)

sys/dev/drm/radeon/r600_dpm.c

162

u32 vblank_in_pixels;

sys/dev/drm/radeon/r600_dpm.c

163

u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */

sys/dev/drm/radeon/r600_dpm.c

184

u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)

sys/dev/drm/radeon/r600_dpm.c

189

u32 vrefresh = 0;

sys/dev/drm/radeon/r600_dpm.c

203

void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/drm/radeon/r600_dpm.c

204

u32 *p, u32 *u)

sys/dev/drm/radeon/r600_dpm.c

206

u32 b_c = 0;

sys/dev/drm/radeon/r600_dpm.c

207

u32 i_c;

sys/dev/drm/radeon/r600_dpm.c

208

u32 tmp;

sys/dev/drm/radeon/r600_dpm.c

222

int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)

sys/dev/drm/radeon/r600_dpm.c

224

u32 k, a, ah, al;

sys/dev/drm/radeon/r600_dpm.c

225

u32 t1;

sys/dev/drm/radeon/r600_dpm.c

32

const u32 r600_utc[R600_PM_NUMBER_OF_TC] =

sys/dev/drm/radeon/r600_dpm.c

339

void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)

sys/dev/drm/radeon/r600_dpm.c

345

u32 l_to_m, u32 m_to_h,

sys/dev/drm/radeon/r600_dpm.c

346

u32 h_to_m, u32 m_to_l)

sys/dev/drm/radeon/r600_dpm.c

353

u32 index, u32 u_t, u32 d_t)

sys/dev/drm/radeon/r600_dpm.c

371

void r600_set_vrc(struct radeon_device *rdev, u32 vrv)

sys/dev/drm/radeon/r600_dpm.c

376

void r600_set_tpu(struct radeon_device *rdev, u32 u)

sys/dev/drm/radeon/r600_dpm.c

381

void r600_set_tpc(struct radeon_device *rdev, u32 c)

sys/dev/drm/radeon/r600_dpm.c

386

void r600_set_sstu(struct radeon_device *rdev, u32 u)

sys/dev/drm/radeon/r600_dpm.c

391

void r600_set_sst(struct radeon_device *rdev, u32 t)

sys/dev/drm/radeon/r600_dpm.c

396

void r600_set_git(struct radeon_device *rdev, u32 t)

sys/dev/drm/radeon/r600_dpm.c

401

void r600_set_fctu(struct radeon_device *rdev, u32 u)

sys/dev/drm/radeon/r600_dpm.c

406

void r600_set_fct(struct radeon_device *rdev, u32 t)

sys/dev/drm/radeon/r600_dpm.c

411

void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)

sys/dev/drm/radeon/r600_dpm.c

416

void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)

sys/dev/drm/radeon/r600_dpm.c

421

void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)

sys/dev/drm/radeon/r600_dpm.c

426

void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)

sys/dev/drm/radeon/r600_dpm.c

431

void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)

sys/dev/drm/radeon/r600_dpm.c

436

void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)

sys/dev/drm/radeon/r600_dpm.c

441

void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)

sys/dev/drm/radeon/r600_dpm.c

447

u32 index, bool enable)

sys/dev/drm/radeon/r600_dpm.c

458

u32 index, bool enable)

sys/dev/drm/radeon/r600_dpm.c

469

u32 index, bool enable)

sys/dev/drm/radeon/r600_dpm.c

480

u32 index, u32 divider)

sys/dev/drm/radeon/r600_dpm.c

487

u32 index, u32 divider)

sys/dev/drm/radeon/r600_dpm.c

494

u32 index, u32 divider)

sys/dev/drm/radeon/r600_dpm.c

501

u32 index, u32 step_time)

sys/dev/drm/radeon/r600_dpm.c

507

void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)

sys/dev/drm/radeon/r600_dpm.c

51

const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =

sys/dev/drm/radeon/r600_dpm.c

512

void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)

sys/dev/drm/radeon/r600_dpm.c

517

void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)

sys/dev/drm/radeon/r600_dpm.c

533

u32 tmp, mask;

sys/dev/drm/radeon/r600_dpm.c

534

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

547

u32 gpio;

sys/dev/drm/radeon/r600_dpm.c

565

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

576

enum r600_power_level index, u32 voltage_index)

sys/dev/drm/radeon/r600_dpm.c

578

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

585

enum r600_power_level index, u32 mem_clock_index)

sys/dev/drm/radeon/r600_dpm.c

587

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

594

enum r600_power_level index, u32 eng_clock_index)

sys/dev/drm/radeon/r600_dpm.c

596

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

606

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

607

u32 tmp = 0;

sys/dev/drm/radeon/r600_dpm.c

617

u32 ix = 3 - (3 & index);

sys/dev/drm/radeon/r600_dpm.c

618

u32 tmp = 0;

sys/dev/drm/radeon/r600_dpm.c

627

u32 tmp;

sys/dev/drm/radeon/r600_dpm.c

636

u32 tmp;

sys/dev/drm/radeon/r600_dpm.c

70

void r600_dpm_print_class_info(u32 class, u32 class2)

sys/dev/drm/radeon/r600_dpm.c

725

bool r600_is_uvd_state(u32 class, u32 class2)

sys/dev/drm/radeon/r600_dpm.c

824

u32 size = atom_table->ucNumEntries *

sys/dev/drm/radeon/r600_dpm.h

128

extern const u32 r600_utc[R600_PM_NUMBER_OF_TC];

sys/dev/drm/radeon/r600_dpm.h

129

extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC];

sys/dev/drm/radeon/r600_dpm.h

131

void r600_dpm_print_class_info(u32 class, u32 class2);

sys/dev/drm/radeon/r600_dpm.h

132

void r600_dpm_print_cap_info(u32 caps);

sys/dev/drm/radeon/r600_dpm.h

135

u32 r600_dpm_get_vblank_time(struct radeon_device *rdev);

sys/dev/drm/radeon/r600_dpm.h

136

u32 r600_dpm_get_vrefresh(struct radeon_device *rdev);

sys/dev/drm/radeon/r600_dpm.h

137

bool r600_is_uvd_state(u32 class, u32 class2);

sys/dev/drm/radeon/r600_dpm.h

138

void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,

sys/dev/drm/radeon/r600_dpm.h

139

u32 *p, u32 *u);

sys/dev/drm/radeon/r600_dpm.h

140

int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);

sys/dev/drm/radeon/r600_dpm.h

151

void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p);

sys/dev/drm/radeon/r600_dpm.h

153

u32 l_to_m, u32 m_to_h,

sys/dev/drm/radeon/r600_dpm.h

154

u32 h_to_m, u32 m_to_l);

sys/dev/drm/radeon/r600_dpm.h

155

void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t);

sys/dev/drm/radeon/r600_dpm.h

157

void r600_set_vrc(struct radeon_device *rdev, u32 vrv);

sys/dev/drm/radeon/r600_dpm.h

158

void r600_set_tpu(struct radeon_device *rdev, u32 u);

sys/dev/drm/radeon/r600_dpm.h

159

void r600_set_tpc(struct radeon_device *rdev, u32 c);

sys/dev/drm/radeon/r600_dpm.h

160

void r600_set_sstu(struct radeon_device *rdev, u32 u);

sys/dev/drm/radeon/r600_dpm.h

161

void r600_set_sst(struct radeon_device *rdev, u32 t);

sys/dev/drm/radeon/r600_dpm.h

162

void r600_set_git(struct radeon_device *rdev, u32 t);

sys/dev/drm/radeon/r600_dpm.h

163

void r600_set_fctu(struct radeon_device *rdev, u32 u);

sys/dev/drm/radeon/r600_dpm.h

164

void r600_set_fct(struct radeon_device *rdev, u32 t);

sys/dev/drm/radeon/r600_dpm.h

165

void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p);

sys/dev/drm/radeon/r600_dpm.h

166

void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s);

sys/dev/drm/radeon/r600_dpm.h

167

void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u);

sys/dev/drm/radeon/r600_dpm.h

168

void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p);

sys/dev/drm/radeon/r600_dpm.h

169

void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s);

sys/dev/drm/radeon/r600_dpm.h

170

void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time);

sys/dev/drm/radeon/r600_dpm.h

171

void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time);

sys/dev/drm/radeon/r600_dpm.h

173

u32 index, bool enable);

sys/dev/drm/radeon/r600_dpm.h

175

u32 index, bool enable);

sys/dev/drm/radeon/r600_dpm.h

177

u32 index, bool enable);

sys/dev/drm/radeon/r600_dpm.h

179

u32 index, u32 divider);

sys/dev/drm/radeon/r600_dpm.h

181

u32 index, u32 divider);

sys/dev/drm/radeon/r600_dpm.h

183

u32 index, u32 divider);

sys/dev/drm/radeon/r600_dpm.h

185

u32 index, u32 step_time);

sys/dev/drm/radeon/r600_dpm.h

186

void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u);

sys/dev/drm/radeon/r600_dpm.h

187

void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u);

sys/dev/drm/radeon/r600_dpm.h

188

void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt);

sys/dev/drm/radeon/r600_dpm.h

198

enum r600_power_level index, u32 voltage_index);

sys/dev/drm/radeon/r600_dpm.h

200

enum r600_power_level index, u32 mem_clock_index);

sys/dev/drm/radeon/r600_dpm.h

202

enum r600_power_level index, u32 eng_clock_index);

sys/dev/drm/radeon/r600_dpm.h

227

u32 sys_mask,

sys/dev/drm/radeon/r600_dpm.h

234

u8 r600_encode_pci_lane_width(u32 lanes);

sys/dev/drm/radeon/r600_hdmi.c

145

u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

sys/dev/drm/radeon/r600_hdmi.c

219

void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/r600_hdmi.c

221

void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/r600_hdmi.c

307

u32 value;

sys/dev/drm/radeon/r600_hdmi.c

346

void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/r600_hdmi.c

347

void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/drm/radeon/r600_hdmi.c

358

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/r600_hdmi.c

359

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)

sys/dev/drm/radeon/r600_hdmi.c

401

void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/r600_hdmi.c

402

void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)

sys/dev/drm/radeon/r600_hdmi.c

485

u32 hdmi = HDMI0_ERROR_ACK;

sys/dev/drm/radeon/radeon.h

1000

u32 reg_list_size;

sys/dev/drm/radeon/radeon.h

1006

u32 clear_state_size;

sys/dev/drm/radeon/radeon.h

1011

u32 cp_table_size;

sys/dev/drm/radeon/radeon.h

1044

unsigned rptr_offs, u32 nop);

sys/dev/drm/radeon/radeon.h

1092

u32 cs_flags;

sys/dev/drm/radeon/radeon.h

1093

u32 ring;

sys/dev/drm/radeon/radeon.h

1098

static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)

sys/dev/drm/radeon/radeon.h

1271

u32 delay; /* delay in usec from voltage drop to sclk change */

sys/dev/drm/radeon/radeon.h

1288

u32 mclk;

sys/dev/drm/radeon/radeon.h

1290

u32 sclk;

sys/dev/drm/radeon/radeon.h

1294

u32 flags;

sys/dev/drm/radeon/radeon.h

1307

u32 flags;

sys/dev/drm/radeon/radeon.h

1308

u32 misc; /* vbios specific flags */

sys/dev/drm/radeon/radeon.h

1309

u32 misc2; /* vbios specific flags */

sys/dev/drm/radeon/radeon.h

1343

u32 caps; /* vbios flags */

sys/dev/drm/radeon/radeon.h

1344

u32 class; /* vbios flags */

sys/dev/drm/radeon/radeon.h

1345

u32 class2; /* vbios flags */

sys/dev/drm/radeon/radeon.h

1347

u32 vclk;

sys/dev/drm/radeon/radeon.h

1348

u32 dclk;

sys/dev/drm/radeon/radeon.h

1350

u32 evclk;

sys/dev/drm/radeon/radeon.h

1351

u32 ecclk;

sys/dev/drm/radeon/radeon.h

1377

u32 sclk;

sys/dev/drm/radeon/radeon.h

1378

u32 mclk;

sys/dev/drm/radeon/radeon.h

1383

u32 sclk;

sys/dev/drm/radeon/radeon.h

1384

u32 mclk;

sys/dev/drm/radeon/radeon.h

1390

u32 count;

sys/dev/drm/radeon/radeon.h

1391

u32 *values;

sys/dev/drm/radeon/radeon.h

1395

u32 clk;

sys/dev/drm/radeon/radeon.h

1400

u32 count;

sys/dev/drm/radeon/radeon.h

1407

u32 leakage;

sys/dev/drm/radeon/radeon.h

1417

u32 count;

sys/dev/drm/radeon/radeon.h

1423

u32 sclk;

sys/dev/drm/radeon/radeon.h

1424

u32 mclk;

sys/dev/drm/radeon/radeon.h

1428

u32 count;

sys/dev/drm/radeon/radeon.h

1433

u32 vclk;

sys/dev/drm/radeon/radeon.h

1434

u32 dclk;

sys/dev/drm/radeon/radeon.h

1444

u32 ecclk;

sys/dev/drm/radeon/radeon.h

1445

u32 evclk;

sys/dev/drm/radeon/radeon.h

1457

u32 platform_tdp;

sys/dev/drm/radeon/radeon.h

1458

u32 small_ac_platform_tdp;

sys/dev/drm/radeon/radeon.h

1459

u32 platform_tdc;

sys/dev/drm/radeon/radeon.h

1460

u32 small_ac_platform_tdc;

sys/dev/drm/radeon/radeon.h

1461

u32 apu_tdp;

sys/dev/drm/radeon/radeon.h

1462

u32 dgpu_tdp;

sys/dev/drm/radeon/radeon.h

1463

u32 dgpu_ulv_power;

sys/dev/drm/radeon/radeon.h

1464

u32 tj_max;

sys/dev/drm/radeon/radeon.h

1492

u32 mclk_sclk_ratio;

sys/dev/drm/radeon/radeon.h

1493

u32 sclk_mclk_delta;

sys/dev/drm/radeon/radeon.h

1510

u32 cycle_delay;

sys/dev/drm/radeon/radeon.h

1534

u32 evclk;

sys/dev/drm/radeon/radeon.h

1535

u32 ecclk;

sys/dev/drm/radeon/radeon.h

1537

u32 sclk;

sys/dev/drm/radeon/radeon.h

1538

u32 mclk;

sys/dev/drm/radeon/radeon.h

1560

u32 platform_caps;

sys/dev/drm/radeon/radeon.h

1561

u32 voltage_response_time;

sys/dev/drm/radeon/radeon.h

1562

u32 backbias_response_time;

sys/dev/drm/radeon/radeon.h

1564

u32 new_active_crtcs;

sys/dev/drm/radeon/radeon.h

1567

u32 current_active_crtcs;

sys/dev/drm/radeon/radeon.h

1572

u32 tdp_limit;

sys/dev/drm/radeon/radeon.h

1573

u32 near_tdp_limit;

sys/dev/drm/radeon/radeon.h

1574

u32 near_tdp_limit_adjusted;

sys/dev/drm/radeon/radeon.h

1575

u32 sq_ramping_threshold;

sys/dev/drm/radeon/radeon.h

1576

u32 cac_leakage;

sys/dev/drm/radeon/radeon.h

1578

u32 tdp_adjustment;

sys/dev/drm/radeon/radeon.h

1602

u32 active_crtcs;

sys/dev/drm/radeon/radeon.h

1626

u32 current_sclk;

sys/dev/drm/radeon/radeon.h

1627

u32 current_mclk;

sys/dev/drm/radeon/radeon.h

1630

u32 default_sclk;

sys/dev/drm/radeon/radeon.h

1631

u32 default_mclk;

sys/dev/drm/radeon/radeon.h

1762

u32 offset;

sys/dev/drm/radeon/radeon.h

1764

u32 id;

sys/dev/drm/radeon/radeon.h

1823

u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);

sys/dev/drm/radeon/radeon.h

1824

u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);

sys/dev/drm/radeon/radeon.h

1866

u32 (*get_xclk)(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon.h

1870

int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);

sys/dev/drm/radeon/radeon.h

1909

u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);

sys/dev/drm/radeon/radeon.h

1927

u32 blit_ring_index;

sys/dev/drm/radeon/radeon.h

1933

u32 dma_ring_index;

sys/dev/drm/radeon/radeon.h

1941

u32 copy_ring_index;

sys/dev/drm/radeon/radeon.h

1971

int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon.h

1972

int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/drm/radeon/radeon.h

1987

u32 (*get_sclk)(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon.h

1988

u32 (*get_mclk)(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon.h

1995

void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);

sys/dev/drm/radeon/radeon.h

1996

u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon.h

1997

int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);

sys/dev/drm/radeon/radeon.h

1998

int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);

sys/dev/drm/radeon/radeon.h

1999

u32 (*get_current_sclk)(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon.h

2000

u32 (*get_current_mclk)(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon.h

2015

u32 hdp_cntl;

sys/dev/drm/radeon/radeon.h

2021

u32 resync_scratch;

sys/dev/drm/radeon/radeon.h

2022

u32 hdp_cntl;

sys/dev/drm/radeon/radeon.h

2458

u32 cg_flags;

sys/dev/drm/radeon/radeon.h

2459

u32 pg_flags;

sys/dev/drm/radeon/radeon.h

2465

u32 px_quirk_flags;

sys/dev/drm/radeon/radeon.h

2508

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2509

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2511

u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);

sys/dev/drm/radeon/radeon.h

2512

void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);

sys/dev/drm/radeon/radeon.h

2605

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2606

void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2607

u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2608

void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2609

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2610

void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2611

u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2612

void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2613

u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2614

void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2615

u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2616

void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2617

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2618

void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2832

extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);

sys/dev/drm/radeon/radeon.h

2845

const u32 *registers,

sys/dev/drm/radeon/radeon.h

2846

const u32 array_size);

sys/dev/drm/radeon/radeon.h

2911

bool r600_fmt_is_valid_color(u32 format);

sys/dev/drm/radeon/radeon.h

2912

bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);

sys/dev/drm/radeon/radeon.h

2913

int r600_fmt_get_blocksize(u32 format);

sys/dev/drm/radeon/radeon.h

2914

int r600_fmt_get_nblocksx(u32 format, u32 w);

sys/dev/drm/radeon/radeon.h

2915

int r600_fmt_get_nblocksy(u32 format, u32 h);

sys/dev/drm/radeon/radeon.h

2921

u32 clock;

sys/dev/drm/radeon/radeon.h

2936

extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon.h

2937

u32 tiling_pipe_num,

sys/dev/drm/radeon/radeon.h

2938

u32 max_rb_num,

sys/dev/drm/radeon/radeon.h

2939

u32 total_max_rb_num,

sys/dev/drm/radeon/radeon.h

2940

u32 enabled_rb_mask);

sys/dev/drm/radeon/radeon.h

298

u32 clock,

sys/dev/drm/radeon/radeon.h

3007

u32 reg, u32 mask,

sys/dev/drm/radeon/radeon.h

302

u32 clock,

sys/dev/drm/radeon/radeon.h

308

u32 *gpio_value, u32 *gpio_mask);

sys/dev/drm/radeon/radeon.h

310

u32 eng_clock, u32 mem_clock);

sys/dev/drm/radeon/radeon.h

344

u32 mem_clock);

sys/dev/drm/radeon/radeon.h

346

u32 mem_clock);

sys/dev/drm/radeon/radeon.h

497

u32 initial_domain;

sys/dev/drm/radeon/radeon.h

502

u32 flags;

sys/dev/drm/radeon/radeon.h

505

u32 tiling_flags;

sys/dev/drm/radeon/radeon.h

506

u32 pitch;

sys/dev/drm/radeon/radeon.h

587

u32 flags, bool kernel,

sys/dev/drm/radeon/radeon.h

732

u32 __iomem *ptr;

sys/dev/drm/radeon/radeon.h

733

u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */

sys/dev/drm/radeon/radeon.h

737

int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);

sys/dev/drm/radeon/radeon.h

738

void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);

sys/dev/drm/radeon/radeon.h

749

u32 target_vblank;

sys/dev/drm/radeon/radeon.h

758

u32 disp_int;

sys/dev/drm/radeon/radeon.h

759

u32 hdmi0_status;

sys/dev/drm/radeon/radeon.h

763

u32 disp_int;

sys/dev/drm/radeon/radeon.h

764

u32 disp_int_cont;

sys/dev/drm/radeon/radeon.h

765

u32 disp_int_cont2;

sys/dev/drm/radeon/radeon.h

766

u32 d1grph_int;

sys/dev/drm/radeon/radeon.h

767

u32 d2grph_int;

sys/dev/drm/radeon/radeon.h

768

u32 hdmi0_status;

sys/dev/drm/radeon/radeon.h

769

u32 hdmi1_status;

sys/dev/drm/radeon/radeon.h

773

u32 disp_int[6];

sys/dev/drm/radeon/radeon.h

774

u32 grph_int[6];

sys/dev/drm/radeon/radeon.h

775

u32 afmt_status[6];

sys/dev/drm/radeon/radeon.h

779

u32 disp_int;

sys/dev/drm/radeon/radeon.h

780

u32 disp_int_cont;

sys/dev/drm/radeon/radeon.h

781

u32 disp_int_cont2;

sys/dev/drm/radeon/radeon.h

782

u32 disp_int_cont3;

sys/dev/drm/radeon/radeon.h

783

u32 disp_int_cont4;

sys/dev/drm/radeon/radeon.h

784

u32 disp_int_cont5;

sys/dev/drm/radeon/radeon.h

785

u32 disp_int_cont6;

sys/dev/drm/radeon/radeon.h

786

u32 d1grph_int;

sys/dev/drm/radeon/radeon.h

787

u32 d2grph_int;

sys/dev/drm/radeon/radeon.h

788

u32 d3grph_int;

sys/dev/drm/radeon/radeon.h

789

u32 d4grph_int;

sys/dev/drm/radeon/radeon.h

790

u32 d5grph_int;

sys/dev/drm/radeon/radeon.h

791

u32 d6grph_int;

sys/dev/drm/radeon/radeon.h

848

volatile u32 *next_rptr_cpu_addr;

sys/dev/drm/radeon/radeon.h

860

u32 nop;

sys/dev/drm/radeon/radeon.h

861

u32 idx;

sys/dev/drm/radeon/radeon.h

865

u32 me;

sys/dev/drm/radeon/radeon.h

866

u32 pipe;

sys/dev/drm/radeon/radeon.h

867

u32 queue;

sys/dev/drm/radeon/radeon.h

869

u32 doorbell_index;

sys/dev/drm/radeon/radeon.h

876

u32 num_pipe;

sys/dev/drm/radeon/radeon.h

877

u32 num_mec;

sys/dev/drm/radeon/radeon.h

878

u32 num_queue;

sys/dev/drm/radeon/radeon.h

999

const u32 *reg_list;

sys/dev/drm/radeon/radeon_acpi.c

150

static void radeon_atif_parse_notification(struct radeon_atif_notifications *n, u32 mask)

sys/dev/drm/radeon/radeon_acpi.c

173

static void radeon_atif_parse_functions(struct radeon_atif_functions *f, u32 mask)

sys/dev/drm/radeon/radeon_acpi.c

41

u32 notification_mask; /* supported notifications mask */

sys/dev/drm/radeon/radeon_acpi.c

42

u32 function_bits; /* supported functions bit vector */

sys/dev/drm/radeon/radeon_acpi.c

461

static void radeon_atcs_parse_functions(struct radeon_atcs_functions *f, u32 mask)

sys/dev/drm/radeon/radeon_acpi.c

47

u32 valid_mask; /* valid flags mask */

sys/dev/drm/radeon/radeon_acpi.c

48

u32 flags; /* flags */

sys/dev/drm/radeon/radeon_acpi.c

54

u32 pending; /* pending sbios requests */

sys/dev/drm/radeon/radeon_acpi.c

591

u32 retry = 3;

sys/dev/drm/radeon/radeon_acpi.c

72

u32 function_bits; /* supported functions bit vector */

sys/dev/drm/radeon/radeon_agp.c

34

u32 hostbridge_vendor;

sys/dev/drm/radeon/radeon_agp.c

35

u32 hostbridge_device;

sys/dev/drm/radeon/radeon_agp.c

36

u32 chip_vendor;

sys/dev/drm/radeon/radeon_agp.c

37

u32 chip_device;

sys/dev/drm/radeon/radeon_agp.c

38

u32 subsys_vendor;

sys/dev/drm/radeon/radeon_agp.c

39

u32 subsys_device;

sys/dev/drm/radeon/radeon_agp.c

40

u32 default_mode;

sys/dev/drm/radeon/radeon_asic.c

141

u32 reg, u32 *val)

sys/dev/drm/radeon/radeon_asic.h

146

u32 r100_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

148

u32 r100_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

199

extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon_asic.h

200

extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_asic.h

235

u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);

sys/dev/drm/radeon/radeon_asic.h

277

u32 vga_render_control;

sys/dev/drm/radeon/radeon_asic.h

278

u32 vga_hdp_control;

sys/dev/drm/radeon/radeon_asic.h

323

u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

383

u32 r600_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

385

u32 r600_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

390

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

403

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);

sys/dev/drm/radeon/radeon_asic.h

410

u32 r600_get_xclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

413

int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon_asic.h

432

u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

433

u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

440

u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

441

u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

450

u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

451

u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

458

u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

459

u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

479

u32 rv770_get_xclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

480

int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon_asic.h

491

u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

492

u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

499

u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

500

u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

506

u32 vga_render_control;

sys/dev/drm/radeon/radeon_asic.h

507

u32 vga_hdp_control;

sys/dev/drm/radeon/radeon_asic.h

526

u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);

sys/dev/drm/radeon/radeon_asic.h

536

int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon_asic.h

537

int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon_asic.h

54

u32 GENMO_WT;

sys/dev/drm/radeon/radeon_asic.h

55

u32 CRTC_EXT_CNTL;

sys/dev/drm/radeon/radeon_asic.h

552

u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

558

u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

56

u32 CRTC_GEN_CNTL;

sys/dev/drm/radeon/radeon_asic.h

57

u32 CRTC2_GEN_CNTL;

sys/dev/drm/radeon/radeon_asic.h

570

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

58

u32 CUR_OFFSET;

sys/dev/drm/radeon/radeon_asic.h

589

u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

59

u32 CUR2_OFFSET;

sys/dev/drm/radeon/radeon_asic.h

590

u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

594

u32 btc_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

595

u32 btc_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

606

u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

607

u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

614

u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

615

u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

635

u32 status, u32 addr);

sys/dev/drm/radeon/radeon_asic.h

636

u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

663

u32 cayman_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

665

u32 cayman_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

676

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

678

int ring, u32 cp_int_cntl);

sys/dev/drm/radeon/radeon_asic.h

68

u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);

sys/dev/drm/radeon/radeon_asic.h

688

u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

689

u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

697

u32 ni_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

698

u32 ni_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

709

u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

710

u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

718

u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

719

u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

720

int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/drm/radeon/radeon_asic.h

754

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);

sys/dev/drm/radeon/radeon_asic.h

755

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);

sys/dev/drm/radeon/radeon_asic.h

756

u32 si_get_csb_size(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

757

void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);

sys/dev/drm/radeon/radeon_asic.h

759

u32 max_voltage_steps,

sys/dev/drm/radeon/radeon_asic.h

761

u32 si_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

780

u32 si_get_xclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

782

int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon_asic.h

783

int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/drm/radeon/radeon_asic.h

786

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

809

u32 *speed);

sys/dev/drm/radeon/radeon_asic.h

811

u32 speed);

sys/dev/drm/radeon/radeon_asic.h

812

u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

813

void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);

sys/dev/drm/radeon/radeon_asic.h

814

u32 si_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

815

u32 si_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

823

u32 cik_get_csb_size(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

824

void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);

sys/dev/drm/radeon/radeon_asic.h

826

u32 cik_get_xclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

829

int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);

sys/dev/drm/radeon/radeon_asic.h

830

int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);

sys/dev/drm/radeon/radeon_asic.h

833

u32 block, bool enable);

sys/dev/drm/radeon/radeon_asic.h

899

u32 cik_gfx_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

901

u32 cik_gfx_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

905

u32 cik_compute_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

907

u32 cik_compute_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

911

u32 cik_sdma_get_rptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

913

u32 cik_sdma_get_wptr(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_asic.h

920

u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

927

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

939

u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

940

u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

949

u32 ci_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

950

u32 ci_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

953

u32 *speed);

sys/dev/drm/radeon/radeon_asic.h

955

u32 speed);

sys/dev/drm/radeon/radeon_asic.h

956

u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

957

void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);

sys/dev/drm/radeon/radeon_asic.h

969

u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

970

u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);

sys/dev/drm/radeon/radeon_asic.h

979

u32 kv_dpm_get_current_sclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_asic.h

980

u32 kv_dpm_get_current_mclk(struct radeon_device *rdev);

sys/dev/drm/radeon/radeon_atombios.c

1508

int id, u32 clock)

sys/dev/drm/radeon/radeon_atombios.c

2043

u32 misc, u32 misc2)

sys/dev/drm/radeon/radeon_atombios.c

2084

u32 misc, misc2 = 0;

sys/dev/drm/radeon/radeon_atombios.c

233

u32 reg;

sys/dev/drm/radeon/radeon_atombios.c

2403

u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);

sys/dev/drm/radeon/radeon_atombios.c

2404

u32 misc2 = le16_to_cpu(non_clock_info->usClassification);

sys/dev/drm/radeon/radeon_atombios.c

2477

u32 sclk, mclk;

sys/dev/drm/radeon/radeon_atombios.c

2829

u32 clock,

sys/dev/drm/radeon/radeon_atombios.c

2945

u32 clock,

sys/dev/drm/radeon/radeon_atombios.c

3049

u32 eng_clock, u32 mem_clock)

sys/dev/drm/radeon/radeon_atombios.c

3053

u32 tmp;

sys/dev/drm/radeon/radeon_atombios.c

3068

u32 mem_clock)

sys/dev/drm/radeon/radeon_atombios.c

3070

u32 args;

sys/dev/drm/radeon/radeon_atombios.c

3079

u32 mem_clock)

sys/dev/drm/radeon/radeon_atombios.c

3083

u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);

sys/dev/drm/radeon/radeon_atombios.c

3305

u32 entry_id;

sys/dev/drm/radeon/radeon_atombios.c

3306

u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;

sys/dev/drm/radeon/radeon_atombios.c

3333

u32 *gpio_value, u32 *gpio_mask)

sys/dev/drm/radeon/radeon_atombios.c

3352

*gpio_mask = le32_to_cpu(*(u32 *)&args.v2);

sys/dev/drm/radeon/radeon_atombios.c

3360

*gpio_value = le32_to_cpu(*(u32 *)&args.v2);

sys/dev/drm/radeon/radeon_atombios.c

3385

u32 size = le16_to_cpu(v1->sHeader.usStructureSize);

sys/dev/drm/radeon/radeon_atombios.c

3386

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);

sys/dev/drm/radeon/radeon_atombios.c

3402

u32 size = le16_to_cpu(v2->sHeader.usStructureSize);

sys/dev/drm/radeon/radeon_atombios.c

3403

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);

sys/dev/drm/radeon/radeon_atombios.c

3419

u32 size = le16_to_cpu(v3->sHeader.usStructureSize);

sys/dev/drm/radeon/radeon_atombios.c

3420

u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);

sys/dev/drm/radeon/radeon_atombios.c

3910

u32 mem_timing_size = gddr5 ?

sys/dev/drm/radeon/radeon_atombios.c

3981

u32 i = 0, j;

sys/dev/drm/radeon/radeon_atombios.c

4023

while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&

sys/dev/drm/radeon/radeon_atombios.c

4025

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/drm/radeon/radeon_atombios.c

4029

(u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)

sys/dev/drm/radeon/radeon_atombios.c

4034

(u32)le32_to_cpu(*((u32 *)reg_data + j));

sys/dev/drm/radeon/radeon_atombios.c

4046

if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)

sys/dev/drm/radeon/radeon_audio.c

100

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.c

101

void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/radeon_audio.c

102

void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/radeon_audio.c

103

void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/radeon_audio.c

112

static const u32 pin_offsets[7] =

sys/dev/drm/radeon/radeon_audio.c

123

static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)

sys/dev/drm/radeon/radeon_audio.c

128

static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/radeon_audio.c

129

u32 reg, u32 v)

sys/dev/drm/radeon/radeon_audio.c

350

u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)

sys/dev/drm/radeon/radeon_audio.c

358

void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/radeon_audio.c

359

u32 reg, u32 v)

sys/dev/drm/radeon/radeon_audio.c

42

u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);

sys/dev/drm/radeon/radeon_audio.c

44

u32 offset, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_audio.c

84

void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/radeon_audio.c

86

void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/radeon_audio.c

94

void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.c

95

void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.c

97

u32 offset, int bpc);

sys/dev/drm/radeon/radeon_audio.c

98

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.c

99

void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.h

37

u32 (*endpoint_rreg)(struct radeon_device *rdev, u32 offset, u32 reg);

sys/dev/drm/radeon/radeon_audio.h

39

u32 offset, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_audio.h

58

void (*set_vbi_packet)(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.h

59

void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc);

sys/dev/drm/radeon/radeon_audio.h

60

void (*set_avi_packet)(struct radeon_device *rdev, u32 offset,

sys/dev/drm/radeon/radeon_audio.h

62

void (*set_audio_packet)(struct drm_encoder *encoder, u32 offset);

sys/dev/drm/radeon/radeon_audio.h

63

void (*set_mute)(struct drm_encoder *encoder, u32 offset, bool mute);

sys/dev/drm/radeon/radeon_audio.h

73

u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev,

sys/dev/drm/radeon/radeon_audio.h

74

u32 offset, u32 reg);

sys/dev/drm/radeon/radeon_audio.h

76

u32 offset, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_bios.c

306

u32 bus_cntl;

sys/dev/drm/radeon/radeon_bios.c

307

u32 d1vga_control;

sys/dev/drm/radeon/radeon_bios.c

308

u32 d2vga_control;

sys/dev/drm/radeon/radeon_bios.c

309

u32 vga_render_control;

sys/dev/drm/radeon/radeon_bios.c

310

u32 rom_cntl;

sys/dev/drm/radeon/radeon_clocks.c

104

const u32 *val;

sys/dev/drm/radeon/radeon_clocks.c

196

u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);

sys/dev/drm/radeon/radeon_combios.c

1253

u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;

sys/dev/drm/radeon/radeon_combios.c

412

u32 clk_mask,

sys/dev/drm/radeon/radeon_combios.c

413

u32 data_mask)

sys/dev/drm/radeon/radeon_cs.c

204

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)

sys/dev/drm/radeon/radeon_cs.c

270

u32 ring = RADEON_CS_RING_GFX;

sys/dev/drm/radeon/radeon_cursor.c

73

u32 reg;

sys/dev/drm/radeon/radeon_device.c

119

u32 chip_vendor;

sys/dev/drm/radeon/radeon_device.c

120

u32 chip_device;

sys/dev/drm/radeon/radeon_device.c

121

u32 subsys_vendor;

sys/dev/drm/radeon/radeon_device.c

122

u32 subsys_device;

sys/dev/drm/radeon/radeon_device.c

123

u32 px_quirk_flags;

sys/dev/drm/radeon/radeon_device.c

195

const u32 *registers,

sys/dev/drm/radeon/radeon_device.c

196

const u32 array_size)

sys/dev/drm/radeon/radeon_device.c

198

u32 tmp, reg, and_mask, or_mask;

sys/dev/drm/radeon/radeon_device.c

336

rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);

sys/dev/drm/radeon/radeon_device.c

340

rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));

sys/dev/drm/radeon/radeon_device.c

374

int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)

sys/dev/drm/radeon/radeon_device.c

394

void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)

sys/dev/drm/radeon/radeon_device.c

724

u32 sclk = rdev->pm.current_sclk;

sys/dev/drm/radeon/radeon_device.c

725

u32 mclk = rdev->pm.current_mclk;

sys/dev/drm/radeon/radeon_display.c

1127

u32 pll_out_min, pll_out_max;

sys/dev/drm/radeon/radeon_display.c

1691

u32 src_v = 1, dst_v = 1;

sys/dev/drm/radeon/radeon_display.c

1692

u32 src_h = 1, dst_h = 1;

sys/dev/drm/radeon/radeon_display.c

1814

u32 stat_crtc = 0, vbl = 0, position = 0;

sys/dev/drm/radeon/radeon_display.c

282

u32 update_pending;

sys/dev/drm/radeon/radeon_display.c

952

u32 freq,

sys/dev/drm/radeon/radeon_display.c

953

u32 *dot_clock_p,

sys/dev/drm/radeon/radeon_display.c

954

u32 *fb_div_p,

sys/dev/drm/radeon/radeon_display.c

955

u32 *frac_fb_div_p,

sys/dev/drm/radeon/radeon_display.c

956

u32 *ref_div_p,

sys/dev/drm/radeon/radeon_display.c

957

u32 *post_div_p)

sys/dev/drm/radeon/radeon_dp_auxch.c

44

static const u32 aux_offset[] =

sys/dev/drm/radeon/radeon_dp_mst.c

69

u32 temp, val;

sys/dev/drm/radeon/radeon_drv.c

115

u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/radeon/radeon_encoders.c

360

u32 pixel_clock)

sys/dev/drm/radeon/radeon_fb.c

140

u32 tiling_flags = 0;

sys/dev/drm/radeon/radeon_fb.c

144

u32 cpp;

sys/dev/drm/radeon/radeon_fence.c

61

static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)

sys/dev/drm/radeon/radeon_fence.c

82

static u32 radeon_fence_read(struct radeon_device *rdev, int ring)

sys/dev/drm/radeon/radeon_fence.c

85

u32 seq = 0;

sys/dev/drm/radeon/radeon_gem.c

49

u32 flags, bool kernel,

sys/dev/drm/radeon/radeon_gem.c

615

u32 invalid_flags;

sys/dev/drm/radeon/radeon_i2c.c

105

u32 reg;

sys/dev/drm/radeon/radeon_i2c.c

236

static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)

sys/dev/drm/radeon/radeon_i2c.c

238

u32 sclk = rdev->pm.current_sclk;

sys/dev/drm/radeon/radeon_i2c.c

239

u32 prescale = 0;

sys/dev/drm/radeon/radeon_i2c.c

240

u32 nm;

sys/dev/drm/radeon/radeon_i2c.c

334

u32 prescale;

sys/dev/drm/radeon/radeon_i2c.c

335

u32 i2c_cntl_0, i2c_cntl_1, i2c_data;

sys/dev/drm/radeon/radeon_i2c.c

336

u32 tmp, reg;

sys/dev/drm/radeon/radeon_i2c.c

36

extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);

sys/dev/drm/radeon/radeon_i2c.c

587

u32 prescale;

sys/dev/drm/radeon/radeon_i2c.c

588

u32 tmp, reg;

sys/dev/drm/radeon/radeon_i2c.c

589

u32 saved1, saved2;

sys/dev/drm/radeon/radeon_i2c.c

893

static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)

sys/dev/drm/radeon/radeon_irq_kms.c

571

u32 reg, u32 mask,

sys/dev/drm/radeon/radeon_irq_kms.c

574

u32 tmp = RREG32(reg);

sys/dev/drm/radeon/radeon_kms.c

761

u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/radeon/radeon_kms.c

762

u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/radeon/radeon_kms.c

765

u32 count;

sys/dev/drm/radeon/radeon_legacy_crtc.c

541

crtc_offset = (u32)base;

sys/dev/drm/radeon/radeon_legacy_crtc.c

59

u32 scale, inc, crtc_more_cntl;

sys/dev/drm/radeon/radeon_legacy_crtc.c

60

u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;

sys/dev/drm/radeon/radeon_legacy_crtc.c

61

u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;

sys/dev/drm/radeon/radeon_legacy_crtc.c

62

u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;

sys/dev/drm/radeon/radeon_legacy_tv.c

524

((u32)h_inc << RADEON_H_INC_SHIFT);

sys/dev/drm/radeon/radeon_mode.h

360

u32 adjusted_clock;

sys/dev/drm/radeon/radeon_mode.h

362

u32 pll_reference_div;

sys/dev/drm/radeon/radeon_mode.h

363

u32 pll_post_div;

sys/dev/drm/radeon/radeon_mode.h

364

u32 pll_flags;

sys/dev/drm/radeon/radeon_mode.h

368

u32 line_time;

sys/dev/drm/radeon/radeon_mode.h

369

u32 wm_low;

sys/dev/drm/radeon/radeon_mode.h

370

u32 wm_high;

sys/dev/drm/radeon/radeon_mode.h

371

u32 lb_vblank_lead_lines;

sys/dev/drm/radeon/radeon_mode.h

501

u32 reg;

sys/dev/drm/radeon/radeon_mode.h

502

u32 mask;

sys/dev/drm/radeon/radeon_mode.h

503

u32 shift;

sys/dev/drm/radeon/radeon_mode.h

513

u32 router_id;

sys/dev/drm/radeon/radeon_mode.h

580

u32 post_div;

sys/dev/drm/radeon/radeon_mode.h

584

u32 reserved : 6;

sys/dev/drm/radeon/radeon_mode.h

585

u32 whole_fb_div : 12;

sys/dev/drm/radeon/radeon_mode.h

586

u32 frac_fb_div : 14;

sys/dev/drm/radeon/radeon_mode.h

588

u32 frac_fb_div : 14;

sys/dev/drm/radeon/radeon_mode.h

589

u32 whole_fb_div : 12;

sys/dev/drm/radeon/radeon_mode.h

590

u32 reserved : 6;

sys/dev/drm/radeon/radeon_mode.h

593

u32 fb_div;

sys/dev/drm/radeon/radeon_mode.h

595

u32 ref_div;

sys/dev/drm/radeon/radeon_mode.h

598

u32 vco_mode;

sys/dev/drm/radeon/radeon_mode.h

599

u32 real_clock;

sys/dev/drm/radeon/radeon_mode.h

601

u32 post_divider;

sys/dev/drm/radeon/radeon_mode.h

602

u32 flags;

sys/dev/drm/radeon/radeon_mode.h

609

u32 reserved : 8;

sys/dev/drm/radeon/radeon_mode.h

610

u32 clkfrac : 12;

sys/dev/drm/radeon/radeon_mode.h

611

u32 clkf : 12;

sys/dev/drm/radeon/radeon_mode.h

613

u32 clkf : 12;

sys/dev/drm/radeon/radeon_mode.h

614

u32 clkfrac : 12;

sys/dev/drm/radeon/radeon_mode.h

615

u32 reserved : 8;

sys/dev/drm/radeon/radeon_mode.h

618

u32 fb_div;

sys/dev/drm/radeon/radeon_mode.h

620

u32 post_div;

sys/dev/drm/radeon/radeon_mode.h

621

u32 bwcntl;

sys/dev/drm/radeon/radeon_mode.h

622

u32 dll_speed;

sys/dev/drm/radeon/radeon_mode.h

623

u32 vco_mode;

sys/dev/drm/radeon/radeon_mode.h

624

u32 yclk_sel;

sys/dev/drm/radeon/radeon_mode.h

625

u32 qdr;

sys/dev/drm/radeon/radeon_mode.h

626

u32 half_rate;

sys/dev/drm/radeon/radeon_mode.h

648

u32 mclk[MAX_AC_TIMING_ENTRIES];

sys/dev/drm/radeon/radeon_mode.h

655

u32 mclk_max;

sys/dev/drm/radeon/radeon_mode.h

656

u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/radeon_mode.h

676

u32 smio_low;

sys/dev/drm/radeon/radeon_mode.h

681

u32 count;

sys/dev/drm/radeon/radeon_mode.h

682

u32 mask_low;

sys/dev/drm/radeon/radeon_mode.h

683

u32 phase_delay;

sys/dev/drm/radeon/radeon_mode.h

738

u32 pixel_clock);

sys/dev/drm/radeon/radeon_mode.h

811

int id, u32 clock);

sys/dev/drm/radeon/radeon_mode.h

824

u32 freq,

sys/dev/drm/radeon/radeon_mode.h

825

u32 *dot_clock_p,

sys/dev/drm/radeon/radeon_mode.h

826

u32 *fb_div_p,

sys/dev/drm/radeon/radeon_mode.h

827

u32 *frac_fb_div_p,

sys/dev/drm/radeon/radeon_mode.h

828

u32 *ref_div_p,

sys/dev/drm/radeon/radeon_mode.h

829

u32 *post_div_p);

sys/dev/drm/radeon/radeon_object.c

179

u32 domain, u32 flags, struct sg_table *sg,

sys/dev/drm/radeon/radeon_object.c

324

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,

sys/dev/drm/radeon/radeon_object.c

385

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)

sys/dev/drm/radeon/radeon_object.c

549

u32 domain = lobj->preferred_domains;

sys/dev/drm/radeon/radeon_object.c

550

u32 allowed = lobj->allowed_domains;

sys/dev/drm/radeon/radeon_object.c

551

u32 current_domain =

sys/dev/drm/radeon/radeon_object.c

843

int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)

sys/dev/drm/radeon/radeon_object.c

95

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)

sys/dev/drm/radeon/radeon_object.c

97

u32 c = 0, i;

sys/dev/drm/radeon/radeon_object.h

122

extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,

sys/dev/drm/radeon/radeon_object.h

127

bool kernel, u32 domain, u32 flags,

sys/dev/drm/radeon/radeon_object.h

135

extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);

sys/dev/drm/radeon/radeon_object.h

136

extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,

sys/dev/drm/radeon/radeon_object.h

147

u32 tiling_flags, u32 pitch);

sys/dev/drm/radeon/radeon_object.h

149

u32 *tiling_flags, u32 *pitch);

sys/dev/drm/radeon/radeon_object.h

176

unsigned size, u32 align, u32 domain,

sys/dev/drm/radeon/radeon_object.h

177

u32 flags);

sys/dev/drm/radeon/radeon_object.h

40

static inline unsigned radeon_mem_type_to_domain(u32 mem_type)

sys/dev/drm/radeon/radeon_pm.c

1490

u32 chip_vendor;

sys/dev/drm/radeon/radeon_pm.c

1491

u32 chip_device;

sys/dev/drm/radeon/radeon_pm.c

1492

u32 subsys_vendor;

sys/dev/drm/radeon/radeon_pm.c

1493

u32 subsys_device;

sys/dev/drm/radeon/radeon_pm.c

173

u32 sclk, mclk;

sys/dev/drm/radeon/radeon_pm.c

1889

u32 stat_crtc = 0;

sys/dev/drm/radeon/radeon_pm.c

576

u32 pwm_mode = 0;

sys/dev/drm/radeon/radeon_pm.c

633

u32 value;

sys/dev/drm/radeon/radeon_pm.c

654

u32 speed;

sys/dev/drm/radeon/radeon_pm.c

931

u32 ui_class;

sys/dev/drm/radeon/radeon_ring.c

376

unsigned rptr_offs, u32 nop)

sys/dev/drm/radeon/radeon_ring.c

413

u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);

sys/dev/drm/radeon/radeon_sa.c

52

unsigned size, u32 align, u32 domain, u32 flags)

sys/dev/drm/radeon/rs400.c

159

tmp = (u32)rdev->gart.table_addr & 0xfffff000;

sys/dev/drm/radeon/rs400.c

231

u32 *gtt = rdev->gart.ptr;

sys/dev/drm/radeon/rs600.c

115

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/rs600.c

126

(u32)crtc_base);

sys/dev/drm/radeon/rs600.c

128

(u32)crtc_base);

sys/dev/drm/radeon/rs600.c

159

u32 tmp = 0;

sys/dev/drm/radeon/rs600.c

221

u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;

sys/dev/drm/radeon/rs600.c

222

u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;

sys/dev/drm/radeon/rs600.c

315

u32 tmp;

sys/dev/drm/radeon/rs600.c

333

u32 tmp;

sys/dev/drm/radeon/rs600.c

349

u32 tmp;

sys/dev/drm/radeon/rs600.c

372

u32 tmp;

sys/dev/drm/radeon/rs600.c

453

u32 status, tmp;

sys/dev/drm/radeon/rs600.c

49

static const u32 crtc_offsets[2] =

sys/dev/drm/radeon/rs600.c

552

u32 tmp;

sys/dev/drm/radeon/rs600.c

616

u32 tmp;

sys/dev/drm/radeon/rs600.c

65

u32 pos1, pos2;

sys/dev/drm/radeon/rs600.c

658

u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &

sys/dev/drm/radeon/rs600.c

660

u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &

sys/dev/drm/radeon/rs600.c

662

u32 hdmi0;

sys/dev/drm/radeon/rs600.c

707

static inline u32 rs600_irq_ack(struct radeon_device *rdev)

sys/dev/drm/radeon/rs600.c

711

u32 tmp;

sys/dev/drm/radeon/rs600.c

756

u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &

sys/dev/drm/radeon/rs600.c

768

u32 status, msi_rearm;

sys/dev/drm/radeon/rs600.c

839

u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)

sys/dev/drm/radeon/rs600.c

891

u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;

sys/dev/drm/radeon/rs600.c

920

u32 r;

sys/dev/drm/radeon/rs690.c

207

u32 tmp;

sys/dev/drm/radeon/rs690.c

210

u32 lb_size = 8192;

sys/dev/drm/radeon/rs690.c

258

u32 lb_request_fifo_depth;

sys/dev/drm/radeon/rs690.c

280

u32 selected_sclk;

sys/dev/drm/radeon/rs690.c

464

u32 *d1mode_priority_a_cnt,

sys/dev/drm/radeon/rs690.c

465

u32 *d2mode_priority_a_cnt)

sys/dev/drm/radeon/rs690.c

589

u32 tmp;

sys/dev/drm/radeon/rs690.c

590

u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;

sys/dev/drm/radeon/rs690.c

591

u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;

sys/dev/drm/radeon/rs780_dpm.c

1005

u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rs780_dpm.c

1007

u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;

sys/dev/drm/radeon/rs780_dpm.c

1008

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/rs780_dpm.c

1009

u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;

sys/dev/drm/radeon/rs780_dpm.c

1010

u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +

sys/dev/drm/radeon/rs780_dpm.c

1012

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/drm/radeon/rs780_dpm.c

1019

u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rs780_dpm.c

211

u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;

sys/dev/drm/radeon/rs780_dpm.c

226

u32 fv_throt_pwm_fb_div_range[3];

sys/dev/drm/radeon/rs780_dpm.c

227

u32 fv_throt_pwm_range[4];

sys/dev/drm/radeon/rs780_dpm.c

405

static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)

sys/dev/drm/radeon/rs780_dpm.c

509

static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,

sys/dev/drm/radeon/rs780_dpm.c

752

u32 sclk;

sys/dev/drm/radeon/rs780_dpm.c

963

u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/rs780_dpm.c

973

u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/rs780_dpm.c

985

u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;

sys/dev/drm/radeon/rs780_dpm.c

986

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/rs780_dpm.c

987

u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;

sys/dev/drm/radeon/rs780_dpm.c

988

u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +

sys/dev/drm/radeon/rs780_dpm.c

990

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/drm/radeon/rs780_dpm.h

39

u32 system_config;

sys/dev/drm/radeon/rs780_dpm.h

40

u32 bootup_uma_clk;

sys/dev/drm/radeon/rs780_dpm.h

55

u32 sclk_low;

sys/dev/drm/radeon/rs780_dpm.h

56

u32 sclk_high;

sys/dev/drm/radeon/rs780_dpm.h

57

u32 flags;

sys/dev/drm/radeon/rv515.c

1110

u32 *d1mode_priority_a_cnt,

sys/dev/drm/radeon/rv515.c

1111

u32 *d2mode_priority_a_cnt)

sys/dev/drm/radeon/rv515.c

1235

u32 tmp;

sys/dev/drm/radeon/rv515.c

1236

u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;

sys/dev/drm/radeon/rv515.c

1237

u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;

sys/dev/drm/radeon/rv515.c

294

u32 crtc_enabled, tmp, frame_count, blackout;

sys/dev/drm/radeon/rv515.c

376

u32 tmp, frame_count;

sys/dev/drm/radeon/rv515.c

395

(u32)rdev->mc.vram_start);

sys/dev/drm/radeon/rv515.c

397

(u32)rdev->mc.vram_start);

sys/dev/drm/radeon/rv515.c

399

WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

sys/dev/drm/radeon/rv515.c

42

static const u32 crtc_offsets[2] =

sys/dev/drm/radeon/rv515.c

937

u32 lb_request_fifo_depth;

sys/dev/drm/radeon/rv515.c

959

u32 selected_sclk;

sys/dev/drm/radeon/rv6xx_dpm.c

1002

static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,

sys/dev/drm/radeon/rv6xx_dpm.c

103

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

112

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

1183

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/rv6xx_dpm.c

124

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

1352

static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/drm/radeon/rv6xx_dpm.c

140

u32 clock, struct rv6xx_sclk_stepping *step)

sys/dev/drm/radeon/rv6xx_dpm.c

161

u32 step_index, struct rv6xx_sclk_stepping *step)

sys/dev/drm/radeon/rv6xx_dpm.c

164

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

165

u32 fb_divider;

sys/dev/drm/radeon/rv6xx_dpm.c

166

u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,

sys/dev/drm/radeon/rv6xx_dpm.c

177

u32 lo_len = (step->post_divider - 2) / 2;

sys/dev/drm/radeon/rv6xx_dpm.c

178

u32 hi_len = step->post_divider - 2 - lo_len;

sys/dev/drm/radeon/rv6xx_dpm.c

1822

u32 sclk, mclk;

sys/dev/drm/radeon/rv6xx_dpm.c

196

bool increasing_vco, u32 step_size)

sys/dev/drm/radeon/rv6xx_dpm.c

2034

u32 current_index =

sys/dev/drm/radeon/rv6xx_dpm.c

2054

u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rv6xx_dpm.c

2059

u32 current_index =

sys/dev/drm/radeon/rv6xx_dpm.c

2077

u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rv6xx_dpm.c

2082

u32 current_index =

sys/dev/drm/radeon/rv6xx_dpm.c

2110

u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/rv6xx_dpm.c

2120

u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/rv6xx_dpm.c

241

u32 low, u32 high,

sys/dev/drm/radeon/rv6xx_dpm.c

242

u32 start_index, u8 *end_index)

sys/dev/drm/radeon/rv6xx_dpm.c

247

u32 step_index = start_index;

sys/dev/drm/radeon/rv6xx_dpm.c

298

u32 clock, u32 index)

sys/dev/drm/radeon/rv6xx_dpm.c

307

u32 start_index, u32 end_index)

sys/dev/drm/radeon/rv6xx_dpm.c

309

u32 step_index;

sys/dev/drm/radeon/rv6xx_dpm.c

316

u32 index, u32 clk_s)

sys/dev/drm/radeon/rv6xx_dpm.c

323

u32 index, u32 clk_v)

sys/dev/drm/radeon/rv6xx_dpm.c

330

u32 index, bool enable)

sys/dev/drm/radeon/rv6xx_dpm.c

34

static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,

sys/dev/drm/radeon/rv6xx_dpm.c

341

u32 clk_s)

sys/dev/drm/radeon/rv6xx_dpm.c

347

u32 clk_v)

sys/dev/drm/radeon/rv6xx_dpm.c

35

u32 unscaled_count, u32 unit);

sys/dev/drm/radeon/rv6xx_dpm.c

371

u32 index, bool enable)

sys/dev/drm/radeon/rv6xx_dpm.c

381

u32 index, u32 divider)

sys/dev/drm/radeon/rv6xx_dpm.c

388

u32 index, u32 divider)

sys/dev/drm/radeon/rv6xx_dpm.c

395

u32 index, u32 divider)

sys/dev/drm/radeon/rv6xx_dpm.c

401

static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)

sys/dev/drm/radeon/rv6xx_dpm.c

411

static u32 rv6xx_clocks_per_unit(u32 unit)

sys/dev/drm/radeon/rv6xx_dpm.c

413

u32 tmp = 1 << (2 * unit);

sys/dev/drm/radeon/rv6xx_dpm.c

418

static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,

sys/dev/drm/radeon/rv6xx_dpm.c

419

u32 unscaled_count, u32 unit)

sys/dev/drm/radeon/rv6xx_dpm.c

421

u32 count_per_unit = rv6xx_clocks_per_unit(unit);

sys/dev/drm/radeon/rv6xx_dpm.c

426

static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,

sys/dev/drm/radeon/rv6xx_dpm.c

427

u32 delay_us, u32 unit)

sys/dev/drm/radeon/rv6xx_dpm.c

429

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

526

static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,

sys/dev/drm/radeon/rv6xx_dpm.c

528

u32 fb_divider_scale)

sys/dev/drm/radeon/rv6xx_dpm.c

53

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

534

static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,

sys/dev/drm/radeon/rv6xx_dpm.c

535

u32 ss_rate, u32 ss_percent,

sys/dev/drm/radeon/rv6xx_dpm.c

536

u32 fb_divider_scale)

sys/dev/drm/radeon/rv6xx_dpm.c

538

u32 fb_divider = vco_freq / ref_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

544

static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)

sys/dev/drm/radeon/rv6xx_dpm.c

550

u32 clock, enum r600_power_level level)

sys/dev/drm/radeon/rv6xx_dpm.c

552

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

556

u32 vco_freq, clk_v, clk_s;

sys/dev/drm/radeon/rv6xx_dpm.c

599

u32 entry, u32 clock)

sys/dev/drm/radeon/rv6xx_dpm.c

632

u32 requested_memory_clock,

sys/dev/drm/radeon/rv6xx_dpm.c

633

u32 ref_clk,

sys/dev/drm/radeon/rv6xx_dpm.c

635

u32 *vco_freq)

sys/dev/drm/radeon/rv6xx_dpm.c

639

u32 vco_freq_temp;

sys/dev/drm/radeon/rv6xx_dpm.c

656

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

659

u32 vco_freq = 0, clk_v, clk_s;

sys/dev/drm/radeon/rv6xx_dpm.c

703

u32 entry, u16 voltage)

sys/dev/drm/radeon/rv6xx_dpm.c

705

u32 mask, set_pins;

sys/dev/drm/radeon/rv6xx_dpm.c

77

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

782

static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/drm/radeon/rv6xx_dpm.c

783

u32 engine_clock)

sys/dev/drm/radeon/rv6xx_dpm.c

785

u32 dram_rows, dram_refresh_rate;

sys/dev/drm/radeon/rv6xx_dpm.c

786

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

798

u32 sqm_ratio;

sys/dev/drm/radeon/rv6xx_dpm.c

799

u32 arb_refresh_rate;

sys/dev/drm/radeon/rv6xx_dpm.c

800

u32 high_clock;

sys/dev/drm/radeon/rv6xx_dpm.c

841

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

91

u32 tmp;

sys/dev/drm/radeon/rv6xx_dpm.c

916

u32 rt;

sys/dev/drm/radeon/rv6xx_dpm.c

945

u32 tmp_mask, tmp_set_pins;

sys/dev/drm/radeon/rv6xx_dpm.c

984

u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |

sys/dev/drm/radeon/rv6xx_dpm.h

33

u32 vco_frequency;

sys/dev/drm/radeon/rv6xx_dpm.h

34

u32 post_divider;

sys/dev/drm/radeon/rv6xx_dpm.h

38

u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];

sys/dev/drm/radeon/rv6xx_dpm.h

39

u32 mclks[R600_PM_NUMBER_OF_MCLKS];

sys/dev/drm/radeon/rv6xx_dpm.h

67

u32 fb_div_scale;

sys/dev/drm/radeon/rv6xx_dpm.h

68

u32 spll_ref_div;

sys/dev/drm/radeon/rv6xx_dpm.h

69

u32 mpll_ref_div;

sys/dev/drm/radeon/rv6xx_dpm.h

70

u32 bsu;

sys/dev/drm/radeon/rv6xx_dpm.h

71

u32 bsp;

sys/dev/drm/radeon/rv6xx_dpm.h

73

u32 active_auto_throttle_sources;

sys/dev/drm/radeon/rv6xx_dpm.h

75

u32 restricted_levels;

sys/dev/drm/radeon/rv6xx_dpm.h

80

u32 sclk;

sys/dev/drm/radeon/rv6xx_dpm.h

81

u32 mclk;

sys/dev/drm/radeon/rv6xx_dpm.h

83

u32 flags;

sys/dev/drm/radeon/rv730_dpm.c

120

u32 engine_clock, u32 memory_clock,

sys/dev/drm/radeon/rv730_dpm.c

124

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv730_dpm.c

125

u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;

sys/dev/drm/radeon/rv730_dpm.c

126

u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

127

u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;

sys/dev/drm/radeon/rv730_dpm.c

128

u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;

sys/dev/drm/radeon/rv730_dpm.c

129

u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;

sys/dev/drm/radeon/rv730_dpm.c

130

u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;

sys/dev/drm/radeon/rv730_dpm.c

132

u32 post_divider, reference_divider;

sys/dev/drm/radeon/rv730_dpm.c

168

u32 vco_freq = memory_clock * post_divider;

sys/dev/drm/radeon/rv730_dpm.c

172

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv730_dpm.c

173

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/rv730_dpm.c

174

u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);

sys/dev/drm/radeon/rv730_dpm.c

233

u32 mpll_func_cntl = 0;

sys/dev/drm/radeon/rv730_dpm.c

234

u32 mpll_func_cntl_2 = 0 ;

sys/dev/drm/radeon/rv730_dpm.c

235

u32 mpll_func_cntl_3 = 0;

sys/dev/drm/radeon/rv730_dpm.c

236

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv730_dpm.c

237

u32 dll_cntl;

sys/dev/drm/radeon/rv730_dpm.c

238

u32 spll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

239

u32 spll_func_cntl_2;

sys/dev/drm/radeon/rv730_dpm.c

240

u32 spll_func_cntl_3;

sys/dev/drm/radeon/rv730_dpm.c

325

u32 a_t;

sys/dev/drm/radeon/rv730_dpm.c

397

u32 arb_refresh_rate = 0;

sys/dev/drm/radeon/rv730_dpm.c

398

u32 dram_timing = 0;

sys/dev/drm/radeon/rv730_dpm.c

399

u32 dram_timing2 = 0;

sys/dev/drm/radeon/rv730_dpm.c

400

u32 old_dram_timing = 0;

sys/dev/drm/radeon/rv730_dpm.c

401

u32 old_dram_timing2 = 0;

sys/dev/drm/radeon/rv730_dpm.c

41

u32 engine_clock,

sys/dev/drm/radeon/rv730_dpm.c

46

u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

47

u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv730_dpm.c

479

u32 i = use_dcodt ? 0 : 1;

sys/dev/drm/radeon/rv730_dpm.c

48

u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv730_dpm.c

480

u32 mc4_io_pad_cntl;

sys/dev/drm/radeon/rv730_dpm.c

49

u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv730_dpm.c

498

u32 mc4_io_pad_cntl;

sys/dev/drm/radeon/rv730_dpm.c

50

u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv730_dpm.c

52

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv730_dpm.c

53

u32 reference_divider, post_divider;

sys/dev/drm/radeon/rv730_dpm.c

54

u32 fbdiv;

sys/dev/drm/radeon/rv730_dpm.c

72

fbdiv = (u32) tmp;

sys/dev/drm/radeon/rv730_dpm.c

93

u32 vco_freq = engine_clock * post_divider;

sys/dev/drm/radeon/rv730_dpm.c

97

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/rv730_dpm.c

98

u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/radeon/rv740_dpm.c

121

int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,

sys/dev/drm/radeon/rv740_dpm.c

126

u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

127

u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

128

u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv740_dpm.c

129

u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv740_dpm.c

130

u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv740_dpm.c

132

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv740_dpm.c

133

u32 reference_divider;

sys/dev/drm/radeon/rv740_dpm.c

134

u32 fbdiv;

sys/dev/drm/radeon/rv740_dpm.c

146

fbdiv = (u32) tmp;

sys/dev/drm/radeon/rv740_dpm.c

161

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/rv740_dpm.c

165

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/rv740_dpm.c

166

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/radeon/rv740_dpm.c

188

u32 engine_clock, u32 memory_clock,

sys/dev/drm/radeon/rv740_dpm.c

192

u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

193

u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

194

u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

195

u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

196

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv740_dpm.c

197

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/rv740_dpm.c

198

u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;

sys/dev/drm/radeon/rv740_dpm.c

199

u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;

sys/dev/drm/radeon/rv740_dpm.c

201

u32 ibias;

sys/dev/drm/radeon/rv740_dpm.c

202

u32 dll_speed;

sys/dev/drm/radeon/rv740_dpm.c

248

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/drm/radeon/rv740_dpm.c

252

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv740_dpm.c

253

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/drm/radeon/rv740_dpm.c

254

u32 clk_s, clk_v;

sys/dev/drm/radeon/rv740_dpm.c

323

u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

324

u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

325

u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

326

u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

327

u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

328

u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

329

u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv740_dpm.c

330

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv740_dpm.c

331

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/rv740_dpm.c

34

u32 rv740_get_decoded_reference_divider(u32 encoded_ref)

sys/dev/drm/radeon/rv740_dpm.c

36

u32 ref = 0;

sys/dev/drm/radeon/rv740_dpm.c

410

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/radeon/rv740_dpm.c

72

u32 dll_speed;

sys/dev/drm/radeon/rv740_dpm.c

95

u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock)

sys/dev/drm/radeon/rv740_dpm.c

98

u32 factor;

sys/dev/drm/radeon/rv770.c

1004

u32 tmp;

sys/dev/drm/radeon/rv770.c

1133

u32 tmp, i;

sys/dev/drm/radeon/rv770.c

1166

u32 ta_aux_cntl;

sys/dev/drm/radeon/rv770.c

1167

u32 sx_debug_1;

sys/dev/drm/radeon/rv770.c

1168

u32 smx_dc_ctl0;

sys/dev/drm/radeon/rv770.c

1169

u32 db_debug3;

sys/dev/drm/radeon/rv770.c

1170

u32 num_gs_verts_per_thread;

sys/dev/drm/radeon/rv770.c

1171

u32 vgt_gs_per_es;

sys/dev/drm/radeon/rv770.c

1172

u32 gs_prim_buffer_depth = 0;

sys/dev/drm/radeon/rv770.c

1173

u32 sq_ms_fifo_sizes;

sys/dev/drm/radeon/rv770.c

1174

u32 sq_config;

sys/dev/drm/radeon/rv770.c

1175

u32 sq_thread_resource_mgmt;

sys/dev/drm/radeon/rv770.c

1176

u32 hdp_host_path_cntl;

sys/dev/drm/radeon/rv770.c

1177

u32 sq_dyn_gpr_size_simd_ab_0;

sys/dev/drm/radeon/rv770.c

1178

u32 gb_tiling_config = 0;

sys/dev/drm/radeon/rv770.c

1179

u32 cc_gc_shader_pipe_config = 0;

sys/dev/drm/radeon/rv770.c

1180

u32 mc_arb_ramcfg;

sys/dev/drm/radeon/rv770.c

1181

u32 db_debug4, tmp;

sys/dev/drm/radeon/rv770.c

1182

u32 inactive_pipes, shader_pipe_config;

sys/dev/drm/radeon/rv770.c

1183

u32 disabled_rb_mask;

sys/dev/drm/radeon/rv770.c

129

static const u32 r7xx_golden_registers[] =

sys/dev/drm/radeon/rv770.c

145

static const u32 r7xx_golden_dyn_gpr_registers[] =

sys/dev/drm/radeon/rv770.c

158

static const u32 rv770_golden_registers[] =

sys/dev/drm/radeon/rv770.c

1640

u32 tmp;

sys/dev/drm/radeon/rv770.c

168

static const u32 rv770ce_golden_registers[] =

sys/dev/drm/radeon/rv770.c

180

static const u32 rv770_mgcg_init[] =

sys/dev/drm/radeon/rv770.c

2021

u32 link_width_cntl, lanes, speed_cntl, tmp;

sys/dev/drm/radeon/rv770.c

338

static const u32 rv710_golden_registers[] =

sys/dev/drm/radeon/rv770.c

348

static const u32 rv710_mgcg_init[] =

sys/dev/drm/radeon/rv770.c

407

static const u32 rv730_golden_registers[] =

sys/dev/drm/radeon/rv770.c

418

static const u32 rv730_mgcg_init[] =

sys/dev/drm/radeon/rv770.c

44

int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/drm/radeon/rv770.c

540

static const u32 rv740_golden_registers[] =

sys/dev/drm/radeon/rv770.c

577

static const u32 rv740_mgcg_init[] =

sys/dev/drm/radeon/rv770.c

719

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/drm/radeon/rv770.c

722

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/drm/radeon/rv770.c

726

(const u32)ARRAY_SIZE(rv770ce_golden_registers));

sys/dev/drm/radeon/rv770.c

730

(const u32)ARRAY_SIZE(rv770_golden_registers));

sys/dev/drm/radeon/rv770.c

733

(const u32)ARRAY_SIZE(rv770_mgcg_init));

sys/dev/drm/radeon/rv770.c

738

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/drm/radeon/rv770.c

741

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/drm/radeon/rv770.c

744

(const u32)ARRAY_SIZE(rv730_golden_registers));

sys/dev/drm/radeon/rv770.c

747

(const u32)ARRAY_SIZE(rv730_mgcg_init));

sys/dev/drm/radeon/rv770.c

752

(const u32)ARRAY_SIZE(r7xx_golden_registers));

sys/dev/drm/radeon/rv770.c

755

(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));

sys/dev/drm/radeon/rv770.c

758

(const u32)ARRAY_SIZE(rv710_golden_registers));

sys/dev/drm/radeon/rv770.c

761

(const u32)ARRAY_SIZE(rv710_mgcg_init));

sys/dev/drm/radeon/rv770.c

766

(const u32)ARRAY_SIZE(rv740_golden_registers));

sys/dev/drm/radeon/rv770.c

769

(const u32)ARRAY_SIZE(rv740_mgcg_init));

sys/dev/drm/radeon/rv770.c

787

u32 rv770_get_xclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rv770.c

789

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv770.c

790

u32 tmp = RREG32(CG_CLKPIN_CNTL);

sys/dev/drm/radeon/rv770.c

804

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/rv770.c

822

(u32)crtc_base);

sys/dev/drm/radeon/rv770.c

824

(u32)crtc_base);

sys/dev/drm/radeon/rv770.c

851

u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>

sys/dev/drm/radeon/rv770.c

892

u32 tmp;

sys/dev/drm/radeon/rv770.c

928

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/rv770.c

942

u32 tmp;

sys/dev/drm/radeon/rv770.c

976

u32 tmp;

sys/dev/drm/radeon/rv770_dma.c

51

u32 size_in_dw, cur_size_in_dw;

sys/dev/drm/radeon/rv770_dpm.c

1033

u32 a_t;

sys/dev/drm/radeon/rv770_dpm.c

107

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.c

119

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.c

1240

u32 steps = 0;

sys/dev/drm/radeon/rv770_dpm.c

1242

u32 i;

sys/dev/drm/radeon/rv770_dpm.c

1254

u32 gpio_pins, gpio_mask;

sys/dev/drm/radeon/rv770_dpm.c

1279

static u32 rv770_get_mclk_split_point(struct atom_memory_info *memory_info)

sys/dev/drm/radeon/rv770_dpm.c

1290

u32 gpio_pins, gpio_mask;

sys/dev/drm/radeon/rv770_dpm.c

1348

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/rv770_dpm.c

153

u32 mgcg_cgtt_local0;

sys/dev/drm/radeon/rv770_dpm.c

1569

u32 sw_smio_index, vid_smio_cntl;

sys/dev/drm/radeon/rv770_dpm.c

1597

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.c

1612

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.c

1707

u32 voltage_response_time, backbias_response_time;

sys/dev/drm/radeon/rv770_dpm.c

1708

u32 acpi_delay_time, vbi_time_out;

sys/dev/drm/radeon/rv770_dpm.c

1709

u32 vddc_dly, bb_dly, acpi_dly, vbi_dly;

sys/dev/drm/radeon/rv770_dpm.c

1710

u32 reference_clock;

sys/dev/drm/radeon/rv770_dpm.c

1712

voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;

sys/dev/drm/radeon/rv770_dpm.c

1713

backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;

sys/dev/drm/radeon/rv770_dpm.c

1817

static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/drm/radeon/rv770_dpm.c

2185

u32 sclk, mclk;

sys/dev/drm/radeon/rv770_dpm.c

240

u16 reg_offset, u32 *value)

sys/dev/drm/radeon/rv770_dpm.c

2475

u32 current_index =

sys/dev/drm/radeon/rv770_dpm.c

2499

u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rv770_dpm.c

2504

u32 current_index =

sys/dev/drm/radeon/rv770_dpm.c

251

u16 reg_offset, u32 value)

sys/dev/drm/radeon/rv770_dpm.c

2521

u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/rv770_dpm.c

2526

u32 current_index =

sys/dev/drm/radeon/rv770_dpm.c

2554

u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/rv770_dpm.c

2564

u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/rv770_dpm.c

2576

u32 vblank_time = r600_dpm_get_vblank_time(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2577

u32 switch_limit = 200; /* 300 */

sys/dev/drm/radeon/rv770_dpm.c

271

u32 a_t;

sys/dev/drm/radeon/rv770_dpm.c

322

static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock,

sys/dev/drm/radeon/rv770_dpm.c

323

u32 reference_clock,

sys/dev/drm/radeon/rv770_dpm.c

326

u32 *clkf,

sys/dev/drm/radeon/rv770_dpm.c

327

u32 *clkfrac)

sys/dev/drm/radeon/rv770_dpm.c

329

u32 post_divider, reference_divider, feedback_divider8;

sys/dev/drm/radeon/rv770_dpm.c

330

u32 fyclk;

sys/dev/drm/radeon/rv770_dpm.c

347

static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv)

sys/dev/drm/radeon/rv770_dpm.c

375

u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)

sys/dev/drm/radeon/rv770_dpm.c

391

u32 engine_clock, u32 memory_clock,

sys/dev/drm/radeon/rv770_dpm.c

396

u32 mpll_ad_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

398

u32 mpll_ad_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

400

u32 mpll_dq_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

402

u32 mpll_dq_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

404

u32 mclk_pwrmgt_cntl =

sys/dev/drm/radeon/rv770_dpm.c

406

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/rv770_dpm.c

408

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv770_dpm.c

409

u32 clkf, clkfrac;

sys/dev/drm/radeon/rv770_dpm.c

410

u32 postdiv_yclk;

sys/dev/drm/radeon/rv770_dpm.c

411

u32 ibias;

sys/dev/drm/radeon/rv770_dpm.c

489

u32 engine_clock,

sys/dev/drm/radeon/rv770_dpm.c

494

u32 spll_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

496

u32 spll_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

498

u32 spll_func_cntl_3 =

sys/dev/drm/radeon/rv770_dpm.c

500

u32 cg_spll_spread_spectrum =

sys/dev/drm/radeon/rv770_dpm.c

502

u32 cg_spll_spread_spectrum_2 =

sys/dev/drm/radeon/rv770_dpm.c

505

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv770_dpm.c

506

u32 reference_divider, post_divider;

sys/dev/drm/radeon/rv770_dpm.c

507

u32 fbdiv;

sys/dev/drm/radeon/rv770_dpm.c

524

fbdiv = (u32) tmp;

sys/dev/drm/radeon/rv770_dpm.c

544

u32 vco_freq = engine_clock * post_divider;

sys/dev/drm/radeon/rv770_dpm.c

548

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/rv770_dpm.c

549

u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/radeon/rv770_dpm.c

596

int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/drm/radeon/rv770_dpm.c

726

u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/drm/radeon/rv770_dpm.c

727

u32 engine_clock)

sys/dev/drm/radeon/rv770_dpm.c

729

u32 dram_rows;

sys/dev/drm/radeon/rv770_dpm.c

730

u32 dram_refresh_rate;

sys/dev/drm/radeon/rv770_dpm.c

731

u32 mc_arb_rfsh_rate;

sys/dev/drm/radeon/rv770_dpm.c

732

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.c

748

u32 sqm_ratio;

sys/dev/drm/radeon/rv770_dpm.c

749

u32 arb_refresh_rate;

sys/dev/drm/radeon/rv770_dpm.c

750

u32 high_clock;

sys/dev/drm/radeon/rv770_dpm.c

77

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.c

823

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/rv770_dpm.c

884

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/rv770_dpm.c

924

u32 mpll_ad_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

926

u32 mpll_ad_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

928

u32 mpll_dq_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

930

u32 mpll_dq_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

932

u32 spll_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

934

u32 spll_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

936

u32 spll_func_cntl_3 =

sys/dev/drm/radeon/rv770_dpm.c

938

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv770_dpm.c

939

u32 dll_cntl;

sys/dev/drm/radeon/rv770_dpm.c

98

u32 tmp;

sys/dev/drm/radeon/rv770_dpm.h

100

u32 mvdd_split_frequency;

sys/dev/drm/radeon/rv770_dpm.h

101

u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];

sys/dev/drm/radeon/rv770_dpm.h

108

u32 mclk_odt_threshold;

sys/dev/drm/radeon/rv770_dpm.h

112

u32 boot_sclk;

sys/dev/drm/radeon/rv770_dpm.h

114

u32 ref_div;

sys/dev/drm/radeon/rv770_dpm.h

115

u32 active_auto_throttle_sources;

sys/dev/drm/radeon/rv770_dpm.h

116

u32 mclk_stutter_mode_threshold;

sys/dev/drm/radeon/rv770_dpm.h

117

u32 mclk_strobe_mode_threshold;

sys/dev/drm/radeon/rv770_dpm.h

118

u32 mclk_edc_enable_threshold;

sys/dev/drm/radeon/rv770_dpm.h

119

u32 bsp;

sys/dev/drm/radeon/rv770_dpm.h

120

u32 bsu;

sys/dev/drm/radeon/rv770_dpm.h

121

u32 pbsp;

sys/dev/drm/radeon/rv770_dpm.h

122

u32 pbsu;

sys/dev/drm/radeon/rv770_dpm.h

123

u32 dsp;

sys/dev/drm/radeon/rv770_dpm.h

124

u32 psp;

sys/dev/drm/radeon/rv770_dpm.h

125

u32 asi;

sys/dev/drm/radeon/rv770_dpm.h

126

u32 pasi;

sys/dev/drm/radeon/rv770_dpm.h

127

u32 vrc;

sys/dev/drm/radeon/rv770_dpm.h

128

u32 restricted_levels;

sys/dev/drm/radeon/rv770_dpm.h

129

u32 rlp;

sys/dev/drm/radeon/rv770_dpm.h

130

u32 rmp;

sys/dev/drm/radeon/rv770_dpm.h

131

u32 lhp;

sys/dev/drm/radeon/rv770_dpm.h

132

u32 lmp;

sys/dev/drm/radeon/rv770_dpm.h

142

u32 sclk;

sys/dev/drm/radeon/rv770_dpm.h

143

u32 mclk;

sys/dev/drm/radeon/rv770_dpm.h

146

u32 flags;

sys/dev/drm/radeon/rv770_dpm.h

180

u32 engine_clock,

sys/dev/drm/radeon/rv770_dpm.h

183

u32 engine_clock, u32 memory_clock,

sys/dev/drm/radeon/rv770_dpm.h

201

int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,

sys/dev/drm/radeon/rv770_dpm.h

204

u32 engine_clock, u32 memory_clock,

sys/dev/drm/radeon/rv770_dpm.h

211

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);

sys/dev/drm/radeon/rv770_dpm.h

212

u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);

sys/dev/drm/radeon/rv770_dpm.h

213

u32 rv740_get_decoded_reference_divider(u32 encoded_ref);

sys/dev/drm/radeon/rv770_dpm.h

216

u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);

sys/dev/drm/radeon/rv770_dpm.h

219

int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/drm/radeon/rv770_dpm.h

225

u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/drm/radeon/rv770_dpm.h

226

u32 engine_clock);

sys/dev/drm/radeon/rv770_dpm.h

282

u16 reg_offset, u32 value);

sys/dev/drm/radeon/rv770_dpm.h

29

u32 cg_spll_func_cntl;

sys/dev/drm/radeon/rv770_dpm.h

30

u32 cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.h

31

u32 cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv770_dpm.h

32

u32 cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv770_dpm.h

33

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv770_dpm.h

34

u32 mpll_ad_func_cntl;

sys/dev/drm/radeon/rv770_dpm.h

35

u32 mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.h

36

u32 mpll_dq_func_cntl;

sys/dev/drm/radeon/rv770_dpm.h

37

u32 mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.h

38

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv770_dpm.h

39

u32 dll_cntl;

sys/dev/drm/radeon/rv770_dpm.h

40

u32 mpll_ss1;

sys/dev/drm/radeon/rv770_dpm.h

41

u32 mpll_ss2;

sys/dev/drm/radeon/rv770_dpm.h

45

u32 cg_spll_func_cntl;

sys/dev/drm/radeon/rv770_dpm.h

46

u32 cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.h

47

u32 cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv770_dpm.h

48

u32 cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv770_dpm.h

49

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv770_dpm.h

50

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv770_dpm.h

51

u32 dll_cntl;

sys/dev/drm/radeon/rv770_dpm.h

52

u32 mpll_func_cntl;

sys/dev/drm/radeon/rv770_dpm.h

53

u32 mpll_func_cntl2;

sys/dev/drm/radeon/rv770_dpm.h

54

u32 mpll_func_cntl3;

sys/dev/drm/radeon/rv770_dpm.h

55

u32 mpll_ss;

sys/dev/drm/radeon/rv770_dpm.h

56

u32 mpll_ss2;

sys/dev/drm/radeon/rv770_dpm.h

68

u32 low_smio;

sys/dev/drm/radeon/rv770_dpm.h

96

u32 s0_vid_lower_smio_cntl;

sys/dev/drm/radeon/rv770_dpm.h

98

u32 vddc_mask_low;

sys/dev/drm/radeon/rv770_dpm.h

99

u32 mvdd_mask_low;

sys/dev/drm/radeon/rv770_smc.c

280

u32 addr;

sys/dev/drm/radeon/rv770_smc.c

300

u32 data, original_data, extra_shift;

sys/dev/drm/radeon/rv770_smc.c

363

u32 smc_first_vector, const u8 *src,

sys/dev/drm/radeon/rv770_smc.c

364

u32 byte_count)

sys/dev/drm/radeon/rv770_smc.c

366

u32 tmp, i;

sys/dev/drm/radeon/rv770_smc.c

414

u32 tmp;

sys/dev/drm/radeon/rv770_smc.c

426

u32 tmp;

sys/dev/drm/radeon/rv770_smc.c

604

u16 smc_address, u32 *value, u16 limit)

sys/dev/drm/radeon/rv770_smc.c

619

u16 smc_address, u32 value, u16 limit)

sys/dev/drm/radeon/rv770_smc.h

201

u16 smc_address, u32 *value, u16 limit);

sys/dev/drm/radeon/rv770_smc.h

203

u16 smc_address, u32 value, u16 limit);

sys/dev/drm/radeon/si.c

1015

static const u32 hainan_mgcg_cgcg_init[] =

sys/dev/drm/radeon/si.c

1092

static u32 verde_pg_init[] =

sys/dev/drm/radeon/si.c

121

static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);

sys/dev/drm/radeon/si.c

1225

(const u32)ARRAY_SIZE(tahiti_golden_registers));

sys/dev/drm/radeon/si.c

1228

(const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1231

(const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1234

(const u32)ARRAY_SIZE(tahiti_golden_registers2));

sys/dev/drm/radeon/si.c

1239

(const u32)ARRAY_SIZE(pitcairn_golden_registers));

sys/dev/drm/radeon/si.c

1242

(const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1245

(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1250

(const u32)ARRAY_SIZE(verde_golden_registers));

sys/dev/drm/radeon/si.c

1253

(const u32)ARRAY_SIZE(verde_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1256

(const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1259

(const u32)ARRAY_SIZE(verde_pg_init));

sys/dev/drm/radeon/si.c

1264

(const u32)ARRAY_SIZE(oland_golden_registers));

sys/dev/drm/radeon/si.c

1267

(const u32)ARRAY_SIZE(oland_golden_rlc_registers));

sys/dev/drm/radeon/si.c

1270

(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1275

(const u32)ARRAY_SIZE(hainan_golden_registers));

sys/dev/drm/radeon/si.c

1278

(const u32)ARRAY_SIZE(hainan_golden_registers2));

sys/dev/drm/radeon/si.c

1281

(const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));

sys/dev/drm/radeon/si.c

1299

u32 reg, u32 *val)

sys/dev/drm/radeon/si.c

132

static const u32 crtc_offsets[] =

sys/dev/drm/radeon/si.c

1329

u32 si_get_xclk(struct radeon_device *rdev)

sys/dev/drm/radeon/si.c

1331

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/si.c

1332

u32 tmp;

sys/dev/drm/radeon/si.c

1348

u32 temp;

sys/dev/drm/radeon/si.c

1366

static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/si.c

1405

static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/si.c

142

static const u32 si_disp_int_status[] =

sys/dev/drm/radeon/si.c

1444

static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/si.c

1483

static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/si.c

1522

static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {

sys/dev/drm/radeon/si.c

156

static const u32 verde_rlc_save_restore_register_list[] =

sys/dev/drm/radeon/si.c

1566

u32 running;

sys/dev/drm/radeon/si.c

1567

u32 *io_mc_regs = NULL;

sys/dev/drm/radeon/si.c

1590

io_mc_regs = (u32 *)&tahiti_io_mc_regs;

sys/dev/drm/radeon/si.c

1594

io_mc_regs = (u32 *)&pitcairn_io_mc_regs;

sys/dev/drm/radeon/si.c

1599

io_mc_regs = (u32 *)&verde_io_mc_regs;

sys/dev/drm/radeon/si.c

1603

io_mc_regs = (u32 *)&oland_io_mc_regs;

sys/dev/drm/radeon/si.c

1607

io_mc_regs = (u32 *)&hainan_io_mc_regs;

sys/dev/drm/radeon/si.c

1957

static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,

sys/dev/drm/radeon/si.c

1962

u32 tmp, buffer_alloc, i;

sys/dev/drm/radeon/si.c

1963

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/drm/radeon/si.c

2016

static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)

sys/dev/drm/radeon/si.c

2018

u32 tmp = RREG32(MC_SHARED_CHMAP);

sys/dev/drm/radeon/si.c

2044

u32 dram_channels; /* number of dram channels */

sys/dev/drm/radeon/si.c

2045

u32 yclk; /* bandwidth per dram data pin in kHz */

sys/dev/drm/radeon/si.c

2046

u32 sclk; /* engine clock in kHz */

sys/dev/drm/radeon/si.c

2047

u32 disp_clk; /* display clock in kHz */

sys/dev/drm/radeon/si.c

2048

u32 src_width; /* viewport width */

sys/dev/drm/radeon/si.c

2049

u32 active_time; /* active display time in ns */

sys/dev/drm/radeon/si.c

2050

u32 blank_time; /* blank time in ns */

sys/dev/drm/radeon/si.c

2053

u32 num_heads; /* number of active crtcs */

sys/dev/drm/radeon/si.c

2054

u32 bytes_per_pixel; /* bytes per pixel display + overlay */

sys/dev/drm/radeon/si.c

2055

u32 lb_size; /* line buffer allocated to pipe */

sys/dev/drm/radeon/si.c

2056

u32 vtaps; /* vertical scaler taps */

sys/dev/drm/radeon/si.c

2059

static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2079

static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2099

static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2119

static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2124

static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2130

u32 min_bandwidth;

sys/dev/drm/radeon/si.c

2156

static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2159

u32 dram_bandwidth = dce6_dram_bandwidth(wm);

sys/dev/drm/radeon/si.c

2160

u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);

sys/dev/drm/radeon/si.c

2161

u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);

sys/dev/drm/radeon/si.c

2166

static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2190

static u32 dce6_latency_watermark(struct dce6_wm_params *wm)

sys/dev/drm/radeon/si.c

2193

u32 mc_latency = 2000; /* 2000 ns. */

sys/dev/drm/radeon/si.c

2194

u32 available_bandwidth = dce6_available_bandwidth(wm);

sys/dev/drm/radeon/si.c

2195

u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;

sys/dev/drm/radeon/si.c

2196

u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;

sys/dev/drm/radeon/si.c

2197

u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */

sys/dev/drm/radeon/si.c

2198

u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +

sys/dev/drm/radeon/si.c

2200

u32 latency = mc_latency + other_heads_data_return_time + dc_latency;

sys/dev/drm/radeon/si.c

2201

u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;

sys/dev/drm/radeon/si.c

2202

u32 tmp, dmif_size = 12288;

sys/dev/drm/radeon/si.c

2260

u32 lb_partitions = wm->lb_size / wm->src_width;

sys/dev/drm/radeon/si.c

2261

u32 line_time = wm->active_time + wm->blank_time;

sys/dev/drm/radeon/si.c

2262

u32 latency_tolerant_lines;

sys/dev/drm/radeon/si.c

2263

u32 latency_hiding;

sys/dev/drm/radeon/si.c

2286

u32 lb_size, u32 num_heads)

sys/dev/drm/radeon/si.c

2290

u32 dram_channels;

sys/dev/drm/radeon/si.c

2291

u32 active_time;

sys/dev/drm/radeon/si.c

2292

u32 line_time = 0;

sys/dev/drm/radeon/si.c

2293

u32 latency_watermark_a = 0, latency_watermark_b = 0;

sys/dev/drm/radeon/si.c

2294

u32 priority_a_mark = 0, priority_b_mark = 0;

sys/dev/drm/radeon/si.c

2295

u32 priority_a_cnt = PRIORITY_OFF;

sys/dev/drm/radeon/si.c

2296

u32 priority_b_cnt = PRIORITY_OFF;

sys/dev/drm/radeon/si.c

2297

u32 tmp, arb_control3;

sys/dev/drm/radeon/si.c

2301

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/drm/radeon/si.c

2302

(u32)mode->clock);

sys/dev/drm/radeon/si.c

2303

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/drm/radeon/si.c

2304

(u32)mode->clock);

sys/dev/drm/radeon/si.c

2305

line_time = min(line_time, (u32)65535);

sys/dev/drm/radeon/si.c

2369

latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);

sys/dev/drm/radeon/si.c

2371

latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);

sys/dev/drm/radeon/si.c

2454

u32 num_heads = 0, lb_size;

sys/dev/drm/radeon/si.c

2481

u32 *tile = rdev->config.si.tile_mode_array;

sys/dev/drm/radeon/si.c

2482

const u32 num_tile_mode_states =

sys/dev/drm/radeon/si.c

2484

u32 reg_offset, split_equal_to_row_size;

sys/dev/drm/radeon/si.c

2938

u32 se_num, u32 sh_num)

sys/dev/drm/radeon/si.c

2940

u32 data = INSTANCE_BROADCAST_WRITES;

sys/dev/drm/radeon/si.c

2953

static u32 si_create_bitmask(u32 bit_width)

sys/dev/drm/radeon/si.c

2955

u32 i, mask = 0;

sys/dev/drm/radeon/si.c

2964

static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)

sys/dev/drm/radeon/si.c

2966

u32 data, mask;

sys/dev/drm/radeon/si.c

2983

u32 se_num, u32 sh_per_se,

sys/dev/drm/radeon/si.c

2984

u32 cu_per_sh)

sys/dev/drm/radeon/si.c

2987

u32 data, mask, active_cu;

sys/dev/drm/radeon/si.c

3009

static u32 si_get_rb_disabled(struct radeon_device *rdev,

sys/dev/drm/radeon/si.c

3010

u32 max_rb_num_per_se,

sys/dev/drm/radeon/si.c

3011

u32 sh_per_se)

sys/dev/drm/radeon/si.c

3013

u32 data, mask;

sys/dev/drm/radeon/si.c

3030

u32 se_num, u32 sh_per_se,

sys/dev/drm/radeon/si.c

3031

u32 max_rb_num_per_se)

sys/dev/drm/radeon/si.c

3034

u32 data, mask;

sys/dev/drm/radeon/si.c

3035

u32 disabled_rbs = 0;

sys/dev/drm/radeon/si.c

3036

u32 enabled_rbs = 0;

sys/dev/drm/radeon/si.c

3081

u32 gb_addr_config = 0;

sys/dev/drm/radeon/si.c

3082

u32 mc_shared_chmap, mc_arb_ramcfg;

sys/dev/drm/radeon/si.c

3083

u32 sx_debug_1;

sys/dev/drm/radeon/si.c

3084

u32 hdp_host_path_cntl;

sys/dev/drm/radeon/si.c

3085

u32 tmp;

sys/dev/drm/radeon/si.c

3394

u32 header;

sys/dev/drm/radeon/si.c

3403

u32 next_rptr;

sys/dev/drm/radeon/si.c

3483

u32 fw_size;

sys/dev/drm/radeon/si.c

3637

u32 tmp;

sys/dev/drm/radeon/si.c

3638

u32 rb_bufsz;

sys/dev/drm/radeon/si.c

3760

u32 si_gpu_check_soft_reset(struct radeon_device *rdev)

sys/dev/drm/radeon/si.c

3762

u32 reset_mask = 0;

sys/dev/drm/radeon/si.c

3763

u32 tmp;

sys/dev/drm/radeon/si.c

378

static const u32 tahiti_golden_rlc_registers[] =

sys/dev/drm/radeon/si.c

3841

static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

sys/dev/drm/radeon/si.c

3844

u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

sys/dev/drm/radeon/si.c

3845

u32 tmp;

sys/dev/drm/radeon/si.c

388

static const u32 tahiti_golden_registers[] =

sys/dev/drm/radeon/si.c

3975

u32 tmp, i;

sys/dev/drm/radeon/si.c

4002

u32 tmp;

sys/dev/drm/radeon/si.c

4024

u32 tmp, i;

sys/dev/drm/radeon/si.c

4075

u32 reset_mask;

sys/dev/drm/radeon/si.c

4115

u32 reset_mask = si_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/si.c

4130

u32 tmp;

sys/dev/drm/radeon/si.c

4194

u32 tmp;

sys/dev/drm/radeon/si.c

423

static const u32 tahiti_golden_registers2[] =

sys/dev/drm/radeon/si.c

428

static const u32 pitcairn_golden_rlc_registers[] =

sys/dev/drm/radeon/si.c

4306

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/si.c

4334

(u32)(rdev->dummy_page.addr >> 12));

sys/dev/drm/radeon/si.c

437

static const u32 pitcairn_golden_registers[] =

sys/dev/drm/radeon/si.c

4397

static bool si_vm_reg_valid(u32 reg)

sys/dev/drm/radeon/si.c

4444

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/drm/radeon/si.c

4465

static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)

sys/dev/drm/radeon/si.c

4467

u32 start_reg, reg, i;

sys/dev/drm/radeon/si.c

4468

u32 command = ib[idx + 4];

sys/dev/drm/radeon/si.c

4469

u32 info = ib[idx + 1];

sys/dev/drm/radeon/si.c

4470

u32 idx_value = ib[idx];

sys/dev/drm/radeon/si.c

4517

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/drm/radeon/si.c

4520

u32 idx = pkt->idx + 1;

sys/dev/drm/radeon/si.c

4521

u32 idx_value = ib[idx];

sys/dev/drm/radeon/si.c

4522

u32 start_reg, end_reg, reg, i;

sys/dev/drm/radeon/si.c

4635

u32 *ib, struct radeon_cs_packet *pkt)

sys/dev/drm/radeon/si.c

4638

u32 idx = pkt->idx + 1;

sys/dev/drm/radeon/si.c

4639

u32 idx_value = ib[idx];

sys/dev/drm/radeon/si.c

4640

u32 start_reg, reg, i;

sys/dev/drm/radeon/si.c

468

static const u32 verde_golden_rlc_registers[] =

sys/dev/drm/radeon/si.c

4725

u32 idx = 0, i;

sys/dev/drm/radeon/si.c

477

static const u32 verde_golden_registers[] =

sys/dev/drm/radeon/si.c

4808

u32 status, u32 addr)

sys/dev/drm/radeon/si.c

4810

u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;

sys/dev/drm/radeon/si.c

4811

u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

sys/dev/drm/radeon/si.c

4812

u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

sys/dev/drm/radeon/si.c

5134

u32 tmp = RREG32(CP_INT_CNTL_RING0);

sys/dev/drm/radeon/si.c

5135

u32 mask;

sys/dev/drm/radeon/si.c

5160

u32 tmp, tmp2;

sys/dev/drm/radeon/si.c

5185

u32 tmp = RREG32(UVD_CGC_CTRL);

sys/dev/drm/radeon/si.c

5191

static u32 si_halt_rlc(struct radeon_device *rdev)

sys/dev/drm/radeon/si.c

5193

u32 data, orig;

sys/dev/drm/radeon/si.c

5207

static void si_update_rlc(struct radeon_device *rdev, u32 rlc)

sys/dev/drm/radeon/si.c

5209

u32 tmp;

sys/dev/drm/radeon/si.c

5218

u32 data, orig;

sys/dev/drm/radeon/si.c

5231

u32 tmp;

sys/dev/drm/radeon/si.c

5243

u32 tmp;

sys/dev/drm/radeon/si.c

5267

u32 tmp;

sys/dev/drm/radeon/si.c

5285

static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)

sys/dev/drm/radeon/si.c

5287

u32 mask = 0, tmp, tmp1;

sys/dev/drm/radeon/si.c

5310

u32 i, j, k, active_cu_number = 0;

sys/dev/drm/radeon/si.c

5311

u32 mask, counter, cu_bitmap;

sys/dev/drm/radeon/si.c

5312

u32 tmp = 0;

sys/dev/drm/radeon/si.c

533

static const u32 oland_golden_rlc_registers[] =

sys/dev/drm/radeon/si.c

5344

u32 data, orig, tmp;

sys/dev/drm/radeon/si.c

5384

u32 data, orig, tmp = 0;

sys/dev/drm/radeon/si.c

542

static const u32 oland_golden_registers[] =

sys/dev/drm/radeon/si.c

5440

u32 orig, data, tmp;

sys/dev/drm/radeon/si.c

5469

static const u32 mc_cg_registers[] =

sys/dev/drm/radeon/si.c

5486

u32 orig, data;

sys/dev/drm/radeon/si.c

5503

u32 orig, data;

sys/dev/drm/radeon/si.c

5519

u32 orig, data, offset;

sys/dev/drm/radeon/si.c

5556

u32 orig, data;

sys/dev/drm/radeon/si.c

5574

u32 orig, data;

sys/dev/drm/radeon/si.c

5590

u32 orig, data;

sys/dev/drm/radeon/si.c

5604

u32 block, bool enable)

sys/dev/drm/radeon/si.c

5669

u32 si_get_csb_size(struct radeon_device *rdev)

sys/dev/drm/radeon/si.c

5671

u32 count = 0;

sys/dev/drm/radeon/si.c

5701

void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)

sys/dev/drm/radeon/si.c

5703

u32 count = 0, i;

sys/dev/drm/radeon/si.c

573

static const u32 hainan_golden_registers[] =

sys/dev/drm/radeon/si.c

5795

u32 tmp = RREG32(GRBM_SOFT_RESET);

sys/dev/drm/radeon/si.c

5825

u32 tmp;

sys/dev/drm/radeon/si.c

5836

u32 tmp;

sys/dev/drm/radeon/si.c

5853

u32 i;

sys/dev/drm/radeon/si.c

5879

u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;

sys/dev/drm/radeon/si.c

5908

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/si.c

5909

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/si.c

5920

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

sys/dev/drm/radeon/si.c

5921

u32 ih_cntl = RREG32(IH_CNTL);

sys/dev/drm/radeon/si.c

5937

u32 tmp;

sys/dev/drm/radeon/si.c

5968

u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

sys/dev/drm/radeon/si.c

602

static const u32 hainan_golden_registers2[] =

sys/dev/drm/radeon/si.c

6039

u32 cp_int_cntl;

sys/dev/drm/radeon/si.c

6040

u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;

sys/dev/drm/radeon/si.c

6041

u32 grbm_int_cntl = 0;

sys/dev/drm/radeon/si.c

6042

u32 dma_cntl, dma_cntl1;

sys/dev/drm/radeon/si.c

6043

u32 thermal_int = 0;

sys/dev/drm/radeon/si.c

607

static const u32 tahiti_mgcg_cgcg_init[] =

sys/dev/drm/radeon/si.c

6134

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/drm/radeon/si.c

6135

u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;

sys/dev/drm/radeon/si.c

6196

static inline u32 si_get_ih_wptr(struct radeon_device *rdev)

sys/dev/drm/radeon/si.c

6198

u32 wptr, tmp;

sys/dev/drm/radeon/si.c

6233

u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;

sys/dev/drm/radeon/si.c

6234

u32 crtc_idx, hpd_idx;

sys/dev/drm/radeon/si.c

6235

u32 mask;

sys/dev/drm/radeon/si.c

6236

u32 wptr;

sys/dev/drm/radeon/si.c

6237

u32 rptr;

sys/dev/drm/radeon/si.c

6238

u32 src_id, src_data, ring_id;

sys/dev/drm/radeon/si.c

6239

u32 ring_index;

sys/dev/drm/radeon/si.c

6243

u32 status, addr;

sys/dev/drm/radeon/si.c

6632

(u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);

sys/dev/drm/radeon/si.c

6992

int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

sys/dev/drm/radeon/si.c

7086

u32 speed_cntl, current_data_rate;

sys/dev/drm/radeon/si.c

7142

u32 max_lw, current_lw, tmp;

sys/dev/drm/radeon/si.c

7247

u32 data, orig;

sys/dev/drm/radeon/si.c

737

static const u32 pitcairn_mgcg_cgcg_init[] =

sys/dev/drm/radeon/si.c

7379

u32 lnkcap;

sys/dev/drm/radeon/si.c

7487

int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

sys/dev/drm/radeon/si.c

835

static const u32 verde_mgcg_cgcg_init[] =

sys/dev/drm/radeon/si.c

935

static const u32 oland_mgcg_cgcg_init[] =

sys/dev/drm/radeon/si_blit_shaders.c

253

const u32 si_default_size = ARRAY_SIZE(si_default_state);

sys/dev/drm/radeon/si_blit_shaders.c

31

const u32 si_default_state[] =

sys/dev/drm/radeon/si_blit_shaders.h

28

extern const u32 si_default_state[];

sys/dev/drm/radeon/si_blit_shaders.h

30

extern const u32 si_default_size;

sys/dev/drm/radeon/si_dma.c

240

u32 size_in_bytes, cur_size_in_bytes;

sys/dev/drm/radeon/si_dma.c

43

u32 reset_mask = si_gpu_check_soft_reset(rdev);

sys/dev/drm/radeon/si_dma.c

44

u32 mask;

sys/dev/drm/radeon/si_dpm.c

1753

u16 reg_offset, u32 value);

sys/dev/drm/radeon/si_dpm.c

1758

u32 engine_clock,

sys/dev/drm/radeon/si_dpm.c

1772

u16 v, s32 t, u32 ileakage, u32 *leakage)

sys/dev/drm/radeon/si_dpm.c

1802

u32 i_leakage,

sys/dev/drm/radeon/si_dpm.c

1803

u32 *leakage)

sys/dev/drm/radeon/si_dpm.c

1809

const u32 fixed_kt, u16 v,

sys/dev/drm/radeon/si_dpm.c

1810

u32 ileakage, u32 *leakage)

sys/dev/drm/radeon/si_dpm.c

1828

const u32 fixed_kt,

sys/dev/drm/radeon/si_dpm.c

1830

u32 i_leakage,

sys/dev/drm/radeon/si_dpm.c

1831

u32 *leakage)

sys/dev/drm/radeon/si_dpm.c

1840

u32 p_limit1 = rdev->pm.dpm.tdp_limit;

sys/dev/drm/radeon/si_dpm.c

1841

u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;

sys/dev/drm/radeon/si_dpm.c

1842

u32 k = dte_data->k;

sys/dev/drm/radeon/si_dpm.c

1843

u32 t_max = dte_data->max_t;

sys/dev/drm/radeon/si_dpm.c

1844

u32 t_split[5] = { 10, 15, 20, 25, 30 };

sys/dev/drm/radeon/si_dpm.c

1845

u32 t_0 = dte_data->t0;

sys/dev/drm/radeon/si_dpm.c

1846

u32 i;

sys/dev/drm/radeon/si_dpm.c

1853

(t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /

sys/dev/drm/radeon/si_dpm.c

1854

(p_limit2 * (u32)100);

sys/dev/drm/radeon/si_dpm.c

2093

static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)

sys/dev/drm/radeon/si_dpm.c

2098

static u32 si_calculate_cac_wintime(struct radeon_device *rdev)

sys/dev/drm/radeon/si_dpm.c

2100

u32 xclk;

sys/dev/drm/radeon/si_dpm.c

2101

u32 wintime;

sys/dev/drm/radeon/si_dpm.c

2102

u32 cac_window;

sys/dev/drm/radeon/si_dpm.c

2103

u32 cac_window_size;

sys/dev/drm/radeon/si_dpm.c

2118

static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)

sys/dev/drm/radeon/si_dpm.c

2125

u32 tdp_adjustment,

sys/dev/drm/radeon/si_dpm.c

2126

u32 *tdp_limit,

sys/dev/drm/radeon/si_dpm.c

2127

u32 *near_tdp_limit)

sys/dev/drm/radeon/si_dpm.c

2129

u32 adjustment_delta, max_tdp_limit;

sys/dev/drm/radeon/si_dpm.c

2131

if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)

sys/dev/drm/radeon/si_dpm.c

2166

u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);

sys/dev/drm/radeon/si_dpm.c

2167

u32 tdp_limit;

sys/dev/drm/radeon/si_dpm.c

2168

u32 near_tdp_limit;

sys/dev/drm/radeon/si_dpm.c

2195

sizeof(u32) * 3,

sys/dev/drm/radeon/si_dpm.c

2229

u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);

sys/dev/drm/radeon/si_dpm.c

2244

sizeof(u32) * 2,

sys/dev/drm/radeon/si_dpm.c

2295

u32 prev_sclk;

sys/dev/drm/radeon/si_dpm.c

2296

u32 max_sclk;

sys/dev/drm/radeon/si_dpm.c

2297

u32 min_sclk;

sys/dev/drm/radeon/si_dpm.c

2341

min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;

sys/dev/drm/radeon/si_dpm.c

2387

u32 sq_power_throttle, sq_power_throttle2;

sys/dev/drm/radeon/si_dpm.c

2474

u32 table_size;

sys/dev/drm/radeon/si_dpm.c

2476

u32 i;

sys/dev/drm/radeon/si_dpm.c

2520

for (i = 0; i < (u32)tdep_count; i++) {

sys/dev/drm/radeon/si_dpm.c

2539

u32 i;

sys/dev/drm/radeon/si_dpm.c

2540

u32 v0_loadline;

sys/dev/drm/radeon/si_dpm.c

2584

u32 leakage;

sys/dev/drm/radeon/si_dpm.c

2587

u32 smc_leakage;

sys/dev/drm/radeon/si_dpm.c

2588

u32 scaling_factor;

sys/dev/drm/radeon/si_dpm.c

2623

u32 leakage;

sys/dev/drm/radeon/si_dpm.c

2625

u32 smc_leakage;

sys/dev/drm/radeon/si_dpm.c

2626

u32 scaling_factor;

sys/dev/drm/radeon/si_dpm.c

2660

u32 load_line_slope, reg;

sys/dev/drm/radeon/si_dpm.c

2662

u32 ticks_per_us = radeon_get_xclk(rdev) / 100;

sys/dev/drm/radeon/si_dpm.c

2702

load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;

sys/dev/drm/radeon/si_dpm.c

2707

cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);

sys/dev/drm/radeon/si_dpm.c

2708

cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);

sys/dev/drm/radeon/si_dpm.c

2715

cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);

sys/dev/drm/radeon/si_dpm.c

2716

cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);

sys/dev/drm/radeon/si_dpm.c

2741

u32 data = 0, offset;

sys/dev/drm/radeon/si_dpm.c

2852

u32 fb_div, p_div;

sys/dev/drm/radeon/si_dpm.c

2853

u32 clk_s, clk_v;

sys/dev/drm/radeon/si_dpm.c

2854

u32 sclk = 0;

sys/dev/drm/radeon/si_dpm.c

2856

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

2936

u32 evclk, u32 ecclk, u16 *voltage)

sys/dev/drm/radeon/si_dpm.c

2938

u32 i;

sys/dev/drm/radeon/si_dpm.c

2974

u32 mclk, sclk;

sys/dev/drm/radeon/si_dpm.c

2976

u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

sys/dev/drm/radeon/si_dpm.c

2977

u32 max_sclk = 0, max_mclk = 0;

sys/dev/drm/radeon/si_dpm.c

3187

u16 reg_offset, u32 *value)

sys/dev/drm/radeon/si_dpm.c

3198

u16 reg_offset, u32 value)

sys/dev/drm/radeon/si_dpm.c

3210

u32 tmp, width, row, column, bank, density;

sys/dev/drm/radeon/si_dpm.c

3255

u32 index, u16 *leakage_voltage)

sys/dev/drm/radeon/si_dpm.c

3281

static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)

sys/dev/drm/radeon/si_dpm.c

3356

u32 thermal_level)

sys/dev/drm/radeon/si_dpm.c

3388

PPSMC_Msg msg, u32 parameter)

sys/dev/drm/radeon/si_dpm.c

3408

u32 levels = ps->performance_level_count;

sys/dev/drm/radeon/si_dpm.c

3483

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

3645

u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;

sys/dev/drm/radeon/si_dpm.c

3646

u32 vddc_dly, acpi_dly, vbi_dly;

sys/dev/drm/radeon/si_dpm.c

3647

u32 reference_clock;

sys/dev/drm/radeon/si_dpm.c

3651

voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;

sys/dev/drm/radeon/si_dpm.c

3652

backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;

sys/dev/drm/radeon/si_dpm.c

3675

u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */

sys/dev/drm/radeon/si_dpm.c

3686

u32 tmp, pipe;

sys/dev/drm/radeon/si_dpm.c

3745

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/si_dpm.c

3803

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/si_dpm.c

3827

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/radeon/si_dpm.c

3840

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/drm/radeon/si_dpm.c

3862

static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/drm/radeon/si_dpm.c

3899

u32 data, num_bits, num_levels;

sys/dev/drm/radeon/si_dpm.c

3923

u32 max_voltage_steps,

sys/dev/drm/radeon/si_dpm.c

3943

u32 i;

sys/dev/drm/radeon/si_dpm.c

4103

(u32)si_pi->vddc_phase_shed_table.phase_delay);

sys/dev/drm/radeon/si_dpm.c

4133

static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,

sys/dev/drm/radeon/si_dpm.c

4163

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/radeon/si_dpm.c

4167

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/radeon/si_dpm.c

4178

for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {

sys/dev/drm/radeon/si_dpm.c

4182

if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/radeon/si_dpm.c

4193

if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)

sys/dev/drm/radeon/si_dpm.c

4213

u16 voltage, u32 sclk, u32 mclk,

sys/dev/drm/radeon/si_dpm.c

4233

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

4260

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

4276

static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,

sys/dev/drm/radeon/si_dpm.c

4277

u32 engine_clock)

sys/dev/drm/radeon/si_dpm.c

4279

u32 dram_rows;

sys/dev/drm/radeon/si_dpm.c

4280

u32 dram_refresh_rate;

sys/dev/drm/radeon/si_dpm.c

4281

u32 mc_arb_rfsh_rate;

sys/dev/drm/radeon/si_dpm.c

4282

u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

sys/dev/drm/radeon/si_dpm.c

4299

u32 dram_timing;

sys/dev/drm/radeon/si_dpm.c

4300

u32 dram_timing2;

sys/dev/drm/radeon/si_dpm.c

4301

u32 burst_time;

sys/dev/drm/radeon/si_dpm.c

4376

u32 reg;

sys/dev/drm/radeon/si_dpm.c

4497

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4498

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/radeon/si_dpm.c

4499

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/si_dpm.c

4500

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/si_dpm.c

4501

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/si_dpm.c

4502

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/si_dpm.c

4503

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4504

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4505

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4506

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/radeon/si_dpm.c

4507

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/radeon/si_dpm.c

4508

u32 reg;

sys/dev/drm/radeon/si_dpm.c

4638

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/drm/radeon/si_dpm.c

4704

u32 lane_width;

sys/dev/drm/radeon/si_dpm.c

4705

u32 vr_hot_gpio;

sys/dev/drm/radeon/si_dpm.c

4785

u32 engine_clock,

sys/dev/drm/radeon/si_dpm.c

4791

u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4792

u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/radeon/si_dpm.c

4793

u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/si_dpm.c

4794

u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/si_dpm.c

4795

u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/radeon/si_dpm.c

4796

u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/si_dpm.c

4798

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/si_dpm.c

4799

u32 reference_divider;

sys/dev/drm/radeon/si_dpm.c

4800

u32 fbdiv;

sys/dev/drm/radeon/si_dpm.c

4812

fbdiv = (u32) tmp;

sys/dev/drm/radeon/si_dpm.c

4827

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/si_dpm.c

4831

u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);

sys/dev/drm/radeon/si_dpm.c

4832

u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

sys/dev/drm/radeon/si_dpm.c

4855

u32 engine_clock,

sys/dev/drm/radeon/si_dpm.c

4876

u32 engine_clock,

sys/dev/drm/radeon/si_dpm.c

4877

u32 memory_clock,

sys/dev/drm/radeon/si_dpm.c

4884

u32 dll_cntl = si_pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/si_dpm.c

4885

u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/si_dpm.c

4886

u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4887

u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4888

u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;

sys/dev/drm/radeon/si_dpm.c

4889

u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/radeon/si_dpm.c

4890

u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/radeon/si_dpm.c

4891

u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;

sys/dev/drm/radeon/si_dpm.c

4892

u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;

sys/dev/drm/radeon/si_dpm.c

4918

u32 freq_nom;

sys/dev/drm/radeon/si_dpm.c

4919

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

4920

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/si_dpm.c

4931

u32 clks = reference_clock * 5 / ss.rate;

sys/dev/drm/radeon/si_dpm.c

4932

u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);

sys/dev/drm/radeon/si_dpm.c

5094

u32 a_t;

sys/dev/drm/radeon/si_dpm.c

5095

u32 t_l, t_h;

sys/dev/drm/radeon/si_dpm.c

5096

u32 high_bsp;

sys/dev/drm/radeon/si_dpm.c

5200

u32 threshold;

sys/dev/drm/radeon/si_dpm.c

5201

u32 sclk_in_sr = 1350; /* ??? */

sys/dev/drm/radeon/si_dpm.c

5277

u32 address = si_pi->state_table_start +

sys/dev/drm/radeon/si_dpm.c

5279

u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +

sys/dev/drm/radeon/si_dpm.c

5303

u32 address = si_pi->state_table_start +

sys/dev/drm/radeon/si_dpm.c

5306

u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);

sys/dev/drm/radeon/si_dpm.c

5363

u32 temp_reg;

sys/dev/drm/radeon/si_dpm.c

5499

u32 i;

sys/dev/drm/radeon/si_dpm.c

5589

u32 i, j;

sys/dev/drm/radeon/si_dpm.c

5607

u32 num_entries, u32 valid_flag)

sys/dev/drm/radeon/si_dpm.c

5609

u32 i, j;

sys/dev/drm/radeon/si_dpm.c

5624

u32 i = 0;

sys/dev/drm/radeon/si_dpm.c

5696

u32 address = si_pi->mc_reg_table_start +

sys/dev/drm/radeon/si_dpm.c

5738

u32 speed_cntl;

sys/dev/drm/radeon/si_dpm.c

5812

bool ds_status_on, u32 count_write)

sys/dev/drm/radeon/si_dpm.c

5873

u32 i;

sys/dev/drm/radeon/si_dpm.c

5918

u32 lane_width;

sys/dev/drm/radeon/si_dpm.c

5919

u32 new_lane_width =

sys/dev/drm/radeon/si_dpm.c

5921

u32 current_lane_width =

sys/dev/drm/radeon/si_dpm.c

5961

u32 thermal_int = RREG32(CG_THERMAL_INT);

sys/dev/drm/radeon/si_dpm.c

6008

static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)

sys/dev/drm/radeon/si_dpm.c

6011

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

6034

u32 duty100;

sys/dev/drm/radeon/si_dpm.c

6035

u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/drm/radeon/si_dpm.c

6037

u32 reference_clock, tmp;

sys/dev/drm/radeon/si_dpm.c

6137

u32 *speed)

sys/dev/drm/radeon/si_dpm.c

6139

u32 duty, duty100;

sys/dev/drm/radeon/si_dpm.c

6153

*speed = (u32)tmp64;

sys/dev/drm/radeon/si_dpm.c

6162

u32 speed)

sys/dev/drm/radeon/si_dpm.c

6165

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

6166

u32 duty, duty100;

sys/dev/drm/radeon/si_dpm.c

6185

duty = (u32)tmp64;

sys/dev/drm/radeon/si_dpm.c

6194

void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)

sys/dev/drm/radeon/si_dpm.c

6210

u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)

sys/dev/drm/radeon/si_dpm.c

6213

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

6224

u32 *speed)

sys/dev/drm/radeon/si_dpm.c

6226

u32 tach_period;

sys/dev/drm/radeon/si_dpm.c

6227

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/si_dpm.c

6245

u32 speed)

sys/dev/drm/radeon/si_dpm.c

6247

u32 tach_period, tmp;

sys/dev/drm/radeon/si_dpm.c

6248

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/si_dpm.c

6277

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

6301

u32 tmp;

sys/dev/drm/radeon/si_dpm.c

6884

u32 sclk, mclk;

sys/dev/drm/radeon/si_dpm.c

7098

u32 current_index =

sys/dev/drm/radeon/si_dpm.c

7112

u32 si_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/si_dpm.c

7118

u32 current_index =

sys/dev/drm/radeon/si_dpm.c

7130

u32 si_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/si_dpm.c

7136

u32 current_index =

sys/dev/drm/radeon/si_dpm.h

100

u32 mpll_func_cntl;

sys/dev/drm/radeon/si_dpm.h

101

u32 mpll_func_cntl_1;

sys/dev/drm/radeon/si_dpm.h

102

u32 mpll_func_cntl_2;

sys/dev/drm/radeon/si_dpm.h

103

u32 mpll_ss1;

sys/dev/drm/radeon/si_dpm.h

104

u32 mpll_ss2;

sys/dev/drm/radeon/si_dpm.h

108

u32 mclk_max;

sys/dev/drm/radeon/si_dpm.h

109

u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/si_dpm.h

144

u32 cg_ulv_control;

sys/dev/drm/radeon/si_dpm.h

145

u32 cg_ulv_parameter;

sys/dev/drm/radeon/si_dpm.h

146

u32 volt_change_delay;

sys/dev/drm/radeon/si_dpm.h

161

u32 max_cu;

sys/dev/drm/radeon/si_dpm.h

166

u32 sys_pcie_mask;

sys/dev/drm/radeon/si_dpm.h

176

u32 sram_end;

sys/dev/drm/radeon/si_dpm.h

177

u32 state_table_start;

sys/dev/drm/radeon/si_dpm.h

178

u32 soft_regs_start;

sys/dev/drm/radeon/si_dpm.h

179

u32 mc_reg_table_start;

sys/dev/drm/radeon/si_dpm.h

180

u32 arb_table_start;

sys/dev/drm/radeon/si_dpm.h

181

u32 cac_table_start;

sys/dev/drm/radeon/si_dpm.h

182

u32 dte_table_start;

sys/dev/drm/radeon/si_dpm.h

183

u32 spll_table_start;

sys/dev/drm/radeon/si_dpm.h

184

u32 papm_cfg_table_start;

sys/dev/drm/radeon/si_dpm.h

185

u32 fan_table_start;

sys/dev/drm/radeon/si_dpm.h

203

u32 t_min;

sys/dev/drm/radeon/si_dpm.h

204

u32 fan_ctrl_default_mode;

sys/dev/drm/radeon/si_dpm.h

38

u32 offset;

sys/dev/drm/radeon/si_dpm.h

39

u32 mask;

sys/dev/drm/radeon/si_dpm.h

40

u32 shift;

sys/dev/drm/radeon/si_dpm.h

41

u32 value;

sys/dev/drm/radeon/si_dpm.h

47

u32 cac_window;

sys/dev/drm/radeon/si_dpm.h

48

u32 l2_lta_window_size_default;

sys/dev/drm/radeon/si_dpm.h

53

u32 fixed_kt;

sys/dev/drm/radeon/si_dpm.h

54

u32 lkge_lut_v0_percent;

sys/dev/drm/radeon/si_dpm.h

61

u32 cac_leakage;

sys/dev/drm/radeon/si_dpm.h

63

u32 wintime;

sys/dev/drm/radeon/si_dpm.h

64

u32 l2_lta_window_size;

sys/dev/drm/radeon/si_dpm.h

73

u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/drm/radeon/si_dpm.h

74

u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/drm/radeon/si_dpm.h

75

u32 k;

sys/dev/drm/radeon/si_dpm.h

76

u32 t0;

sys/dev/drm/radeon/si_dpm.h

77

u32 max_t;

sys/dev/drm/radeon/si_dpm.h

83

u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/drm/radeon/si_dpm.h

84

u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/drm/radeon/si_dpm.h

85

u32 t_threshold;

sys/dev/drm/radeon/si_dpm.h

90

u32 cg_spll_func_cntl;

sys/dev/drm/radeon/si_dpm.h

91

u32 cg_spll_func_cntl_2;

sys/dev/drm/radeon/si_dpm.h

92

u32 cg_spll_func_cntl_3;

sys/dev/drm/radeon/si_dpm.h

93

u32 cg_spll_func_cntl_4;

sys/dev/drm/radeon/si_dpm.h

94

u32 cg_spll_spread_spectrum;

sys/dev/drm/radeon/si_dpm.h

95

u32 cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/si_dpm.h

96

u32 dll_cntl;

sys/dev/drm/radeon/si_dpm.h

97

u32 mclk_pwrmgt_cntl;

sys/dev/drm/radeon/si_dpm.h

98

u32 mpll_ad_func_cntl;

sys/dev/drm/radeon/si_dpm.h

99

u32 mpll_dq_func_cntl;

sys/dev/drm/radeon/si_smc.c

115

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/si_smc.c

124

u32 tmp;

sys/dev/drm/radeon/si_smc.c

145

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

154

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

163

u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

174

u32 tmp;

sys/dev/drm/radeon/si_smc.c

195

u32 tmp;

sys/dev/drm/radeon/si_smc.c

211

int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)

sys/dev/drm/radeon/si_smc.c

214

u32 ucode_start_address;

sys/dev/drm/radeon/si_smc.c

215

u32 ucode_size;

sys/dev/drm/radeon/si_smc.c

217

u32 data;

sys/dev/drm/radeon/si_smc.c

282

int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/drm/radeon/si_smc.c

283

u32 *value, u32 limit)

sys/dev/drm/radeon/si_smc.c

297

int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/drm/radeon/si_smc.c

298

u32 value, u32 limit)

sys/dev/drm/radeon/si_smc.c

34

u32 smc_address, u32 limit)

sys/dev/drm/radeon/si_smc.c

48

u32 smc_start_address,

sys/dev/drm/radeon/si_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/radeon/si_smc.c

53

u32 data, original_data, addr, extra_shift;

sys/dev/drm/radeon/sislands_smc.h

407

u32 smc_start_address,

sys/dev/drm/radeon/sislands_smc.h

408

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/radeon/sislands_smc.h

417

int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);

sys/dev/drm/radeon/sislands_smc.h

418

int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/drm/radeon/sislands_smc.h

419

u32 *value, u32 limit);

sys/dev/drm/radeon/sislands_smc.h

420

int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,

sys/dev/drm/radeon/sislands_smc.h

421

u32 value, u32 limit);

sys/dev/drm/radeon/sumo_dpm.c

1001

u32 sumo_get_sleep_divider_from_id(u32 id)

sys/dev/drm/radeon/sumo_dpm.c

1006

u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/sumo_dpm.c

1007

u32 sclk,

sys/dev/drm/radeon/sumo_dpm.c

1008

u32 min_sclk_in_sr)

sys/dev/drm/radeon/sumo_dpm.c

1011

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

1012

u32 temp;

sys/dev/drm/radeon/sumo_dpm.c

1013

u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?

sys/dev/drm/radeon/sumo_dpm.c

1031

static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/sumo_dpm.c

1032

u32 lower_limit)

sys/dev/drm/radeon/sumo_dpm.c

1035

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

1050

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/sumo_dpm.c

1051

u32 current_vddc;

sys/dev/drm/radeon/sumo_dpm.c

1052

u32 current_sclk;

sys/dev/drm/radeon/sumo_dpm.c

1053

u32 current_index = 0;

sys/dev/drm/radeon/sumo_dpm.c

108

u32 local0;

sys/dev/drm/radeon/sumo_dpm.c

109

u32 local1;

sys/dev/drm/radeon/sumo_dpm.c

1096

u32 min_voltage = 0; /* ??? */

sys/dev/drm/radeon/sumo_dpm.c

1097

u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */

sys/dev/drm/radeon/sumo_dpm.c

1098

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/sumo_dpm.c

1099

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

125

u32 p, u;

sys/dev/drm/radeon/sumo_dpm.c

126

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.c

136

u32 p, u;

sys/dev/drm/radeon/sumo_dpm.c

137

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.c

138

u32 grs = 256 * 25 / 100;

sys/dev/drm/radeon/sumo_dpm.c

1439

u32 sclk;

sys/dev/drm/radeon/sumo_dpm.c

153

u32 rcu_pwr_gating_cntl;

sys/dev/drm/radeon/sumo_dpm.c

1530

u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,

sys/dev/drm/radeon/sumo_dpm.c

1532

u32 vid_2bit)

sys/dev/drm/radeon/sumo_dpm.c

1534

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

154

u32 p, u;

sys/dev/drm/radeon/sumo_dpm.c

1545

u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,

sys/dev/drm/radeon/sumo_dpm.c

1547

u32 vid_7bit)

sys/dev/drm/radeon/sumo_dpm.c

1549

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

155

u32 p_c, p_p, d_p;

sys/dev/drm/radeon/sumo_dpm.c

156

u32 r_t, i_t;

sys/dev/drm/radeon/sumo_dpm.c

1561

u32 vid_2bit)

sys/dev/drm/radeon/sumo_dpm.c

1564

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);

sys/dev/drm/radeon/sumo_dpm.c

157

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1576

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

1598

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

1599

u32 n = 0;

sys/dev/drm/radeon/sumo_dpm.c

1600

u32 prev_sclk = 0;

sys/dev/drm/radeon/sumo_dpm.c

1620

u32 i, j;

sys/dev/drm/radeon/sumo_dpm.c

1745

u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;

sys/dev/drm/radeon/sumo_dpm.c

1821

u32 current_index =

sys/dev/drm/radeon/sumo_dpm.c

1842

u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/sumo_dpm.c

1848

u32 current_index =

sys/dev/drm/radeon/sumo_dpm.c

1863

u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/sumo_dpm.c

1883

u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/sumo_dpm.c

1894

u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/sumo_dpm.c

318

u32 high_clk)

sys/dev/drm/radeon/sumo_dpm.c

321

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.c

349

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

350

u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;

sys/dev/drm/radeon/sumo_dpm.c

367

u32 index, u32 value)

sys/dev/drm/radeon/sumo_dpm.c

37

static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =

sys/dev/drm/radeon/sumo_dpm.c

392

u32 asi;

sys/dev/drm/radeon/sumo_dpm.c

393

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

394

u32 m_a;

sys/dev/drm/radeon/sumo_dpm.c

395

u32 a_t;

sys/dev/drm/radeon/sumo_dpm.c

396

u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/sumo_dpm.c

397

u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/sumo_dpm.c

455

void sumo_program_vc(struct radeon_device *rdev, u32 vrc)

sys/dev/drm/radeon/sumo_dpm.c

467

u32 p, u;

sys/dev/drm/radeon/sumo_dpm.c

468

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.c

477

u32 index, u32 divider)

sys/dev/drm/radeon/sumo_dpm.c

479

u32 reg_index = index / 4;

sys/dev/drm/radeon/sumo_dpm.c

480

u32 field_index = index % 4;

sys/dev/drm/radeon/sumo_dpm.c

497

u32 index, u32 divider)

sys/dev/drm/radeon/sumo_dpm.c

502

u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);

sys/dev/drm/radeon/sumo_dpm.c

511

u32 index, u32 divider)

sys/dev/drm/radeon/sumo_dpm.c

516

u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);

sys/dev/drm/radeon/sumo_dpm.c

524

static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)

sys/dev/drm/radeon/sumo_dpm.c

526

u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);

sys/dev/drm/radeon/sumo_dpm.c

533

static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)

sys/dev/drm/radeon/sumo_dpm.c

536

u32 temp = gnb_slow;

sys/dev/drm/radeon/sumo_dpm.c

537

u32 cg_sclk_dpm_ctrl_3;

sys/dev/drm/radeon/sumo_dpm.c

550

struct sumo_pl *pl, u32 index)

sys/dev/drm/radeon/sumo_dpm.c

555

u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;

sys/dev/drm/radeon/sumo_dpm.c

56

static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =

sys/dev/drm/radeon/sumo_dpm.c

583

static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)

sys/dev/drm/radeon/sumo_dpm.c

585

u32 reg_index = index / 4;

sys/dev/drm/radeon/sumo_dpm.c

586

u32 field_index = index % 4;

sys/dev/drm/radeon/sumo_dpm.c

686

u32 nbps1_old = 0;

sys/dev/drm/radeon/sumo_dpm.c

687

u32 nbps1_new = 0;

sys/dev/drm/radeon/sumo_dpm.c

704

u32 nbps1_old = 0;

sys/dev/drm/radeon/sumo_dpm.c

705

u32 nbps1_new = 0;

sys/dev/drm/radeon/sumo_dpm.c

729

static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)

sys/dev/drm/radeon/sumo_dpm.c

743

u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);

sys/dev/drm/radeon/sumo_dpm.c

761

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

762

u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;

sys/dev/drm/radeon/sumo_dpm.c

805

u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);

sys/dev/drm/radeon/sumo_dpm.c

806

u32 i;

sys/dev/drm/radeon/sumo_dpm.c

880

u32 v = RREG32(DOUT_SCRATCH3);

sys/dev/drm/radeon/sumo_dpm.c

894

u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);

sys/dev/drm/radeon/sumo_dpm.c

895

u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);

sys/dev/drm/radeon/sumo_dpm.c

896

u32 t = 1;

sys/dev/drm/radeon/sumo_dpm.c

930

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.c

931

u32 p, u;

sys/dev/drm/radeon/sumo_dpm.c

932

u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);

sys/dev/drm/radeon/sumo_dpm.c

945

u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);

sys/dev/drm/radeon/sumo_dpm.c

974

u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);

sys/dev/drm/radeon/sumo_dpm.c

975

u32 p, u;

sys/dev/drm/radeon/sumo_dpm.c

976

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_dpm.h

104

u32 asi;

sys/dev/drm/radeon/sumo_dpm.h

105

u32 pasi;

sys/dev/drm/radeon/sumo_dpm.h

106

u32 bsp;

sys/dev/drm/radeon/sumo_dpm.h

107

u32 bsu;

sys/dev/drm/radeon/sumo_dpm.h

108

u32 pbsp;

sys/dev/drm/radeon/sumo_dpm.h

109

u32 pbsu;

sys/dev/drm/radeon/sumo_dpm.h

110

u32 dsp;

sys/dev/drm/radeon/sumo_dpm.h

111

u32 psp;

sys/dev/drm/radeon/sumo_dpm.h

112

u32 thermal_auto_throttling;

sys/dev/drm/radeon/sumo_dpm.h

113

u32 uvd_m3_arbiter;

sys/dev/drm/radeon/sumo_dpm.h

114

u32 fw_version;

sys/dev/drm/radeon/sumo_dpm.h

192

void sumo_program_vc(struct radeon_device *rdev, u32 vrc);

sys/dev/drm/radeon/sumo_dpm.h

202

u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,

sys/dev/drm/radeon/sumo_dpm.h

204

u32 vid_2bit);

sys/dev/drm/radeon/sumo_dpm.h

205

u32 sumo_get_sleep_divider_from_id(u32 id);

sys/dev/drm/radeon/sumo_dpm.h

206

u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/sumo_dpm.h

207

u32 sclk,

sys/dev/drm/radeon/sumo_dpm.h

208

u32 min_sclk_in_sr);

sys/dev/drm/radeon/sumo_dpm.h

213

void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);

sys/dev/drm/radeon/sumo_dpm.h

218

u32 sumo_get_running_fw_version(struct radeon_device *rdev);

sys/dev/drm/radeon/sumo_dpm.h

32

u32 sclk;

sys/dev/drm/radeon/sumo_dpm.h

33

u32 vddc_index;

sys/dev/drm/radeon/sumo_dpm.h

34

u32 ds_divider_index;

sys/dev/drm/radeon/sumo_dpm.h

35

u32 ss_divider_index;

sys/dev/drm/radeon/sumo_dpm.h

36

u32 allow_gnb_slow;

sys/dev/drm/radeon/sumo_dpm.h

37

u32 sclk_dpm_tdp_limit;

sys/dev/drm/radeon/sumo_dpm.h

46

u32 num_levels;

sys/dev/drm/radeon/sumo_dpm.h

48

u32 flags;

sys/dev/drm/radeon/sumo_dpm.h

55

u32 num_max_voltage_levels;

sys/dev/drm/radeon/sumo_dpm.h

56

u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];

sys/dev/drm/radeon/sumo_dpm.h

65

u32 num_entries;

sys/dev/drm/radeon/sumo_dpm.h

70

u32 sclk_frequency;

sys/dev/drm/radeon/sumo_dpm.h

76

u32 num_max_dpm_entries;

sys/dev/drm/radeon/sumo_dpm.h

81

u32 bootup_sclk;

sys/dev/drm/radeon/sumo_dpm.h

82

u32 min_sclk;

sys/dev/drm/radeon/sumo_dpm.h

83

u32 bootup_uma_clk;

sys/dev/drm/radeon/sumo_dpm.h

90

u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];

sys/dev/drm/radeon/sumo_dpm.h

91

u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];

sys/dev/drm/radeon/sumo_dpm.h

92

u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];

sys/dev/drm/radeon/sumo_dpm.h

93

u32 sclk_dpm_boost_margin;

sys/dev/drm/radeon/sumo_dpm.h

94

u32 sclk_dpm_throttle_margin;

sys/dev/drm/radeon/sumo_dpm.h

95

u32 sclk_dpm_tdp_limit_pg;

sys/dev/drm/radeon/sumo_dpm.h

96

u32 gnb_tdp_limit;

sys/dev/drm/radeon/sumo_dpm.h

97

u32 sclk_dpm_tdp_limit_boost;

sys/dev/drm/radeon/sumo_dpm.h

98

u32 boost_sclk;

sys/dev/drm/radeon/sumo_dpm.h

99

u32 boost_vid_2bit;

sys/dev/drm/radeon/sumo_smc.c

112

u32 param = 0;

sys/dev/drm/radeon/sumo_smc.c

133

static u32 sumo_power_of_4(u32 unit)

sys/dev/drm/radeon/sumo_smc.c

135

u32 ret = 1;

sys/dev/drm/radeon/sumo_smc.c

136

u32 i;

sys/dev/drm/radeon/sumo_smc.c

147

u32 period, unit, timer_value;

sys/dev/drm/radeon/sumo_smc.c

148

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/sumo_smc.c

166

void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit)

sys/dev/drm/radeon/sumo_smc.c

168

u32 regoffset = 0;

sys/dev/drm/radeon/sumo_smc.c

169

u32 shift = 0;

sys/dev/drm/radeon/sumo_smc.c

170

u32 mask = 0xFFF;

sys/dev/drm/radeon/sumo_smc.c

171

u32 sclk_dpm_tdp_limit;

sys/dev/drm/radeon/sumo_smc.c

210

u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE);

sys/dev/drm/radeon/sumo_smc.c

217

u32 sumo_get_running_fw_version(struct radeon_device *rdev)

sys/dev/drm/radeon/sumo_smc.c

36

static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)

sys/dev/drm/radeon/sumo_smc.c

38

u32 gfx_int_req;

sys/dev/drm/radeon/sumo_smc.c

75

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

1013

u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);

sys/dev/drm/radeon/trinity_dpm.c

1023

u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

1032

u32 p, u;

sys/dev/drm/radeon/trinity_dpm.c

1033

u32 tp = RREG32_SMC(PM_TP);

sys/dev/drm/radeon/trinity_dpm.c

1034

u32 ni;

sys/dev/drm/radeon/trinity_dpm.c

1035

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1036

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

1193

u32 nbpsconfig;

sys/dev/drm/radeon/trinity_dpm.c

120

static const u32 trinity_mgcg_shls_enable[] =

sys/dev/drm/radeon/trinity_dpm.c

1314

u32 vid_2bit)

sys/dev/drm/radeon/trinity_dpm.c

1317

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);

sys/dev/drm/radeon/trinity_dpm.c

1318

u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;

sys/dev/drm/radeon/trinity_dpm.c

1319

u32 step = (svi_mode == 0) ? 1250 : 625;

sys/dev/drm/radeon/trinity_dpm.c

1320

u32 delta = vid_7bit * step + 50;

sys/dev/drm/radeon/trinity_dpm.c

133

static const u32 trinity_mgcg_shls_disable[] =

sys/dev/drm/radeon/trinity_dpm.c

1339

static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)

sys/dev/drm/radeon/trinity_dpm.c

1363

u32 sclk, u32 min_sclk_in_sr)

sys/dev/drm/radeon/trinity_dpm.c

1366

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

1367

u32 temp;

sys/dev/drm/radeon/trinity_dpm.c

1368

u32 min = (min_sclk_in_sr > TRINITY_MINIMUM_ENGINE_CLOCK) ?

sys/dev/drm/radeon/trinity_dpm.c

1386

static u32 trinity_get_valid_engine_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/trinity_dpm.c

1387

u32 lower_limit)

sys/dev/drm/radeon/trinity_dpm.c

1390

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

1408

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/trinity_dpm.c

1409

u32 current_vddc;

sys/dev/drm/radeon/trinity_dpm.c

1410

u32 current_sclk;

sys/dev/drm/radeon/trinity_dpm.c

1411

u32 current_index = 0;

sys/dev/drm/radeon/trinity_dpm.c

1437

struct trinity_ps *ps, u32 index)

sys/dev/drm/radeon/trinity_dpm.c

1456

static u32 trinity_get_uvd_clock_index(struct radeon_device *rdev,

sys/dev/drm/radeon/trinity_dpm.c

1460

u32 i = 0;

sys/dev/drm/radeon/trinity_dpm.c

1480

u32 high_index = 0;

sys/dev/drm/radeon/trinity_dpm.c

1481

u32 low_index = 0;

sys/dev/drm/radeon/trinity_dpm.c

150

static const u32 trinity_sysls_default[] =

sys/dev/drm/radeon/trinity_dpm.c

1510

u32 evclk, u32 ecclk, u16 *voltage)

sys/dev/drm/radeon/trinity_dpm.c

1512

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

1546

u32 min_voltage = 0; /* ??? */

sys/dev/drm/radeon/trinity_dpm.c

1547

u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */

sys/dev/drm/radeon/trinity_dpm.c

1548

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/trinity_dpm.c

1549

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

1552

u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;

sys/dev/drm/radeon/trinity_dpm.c

1641

u32 gpu_cac_avrg_cntl_window_size;

sys/dev/drm/radeon/trinity_dpm.c

1642

u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;

sys/dev/drm/radeon/trinity_dpm.c

1644

u32 dc_cac_value;

sys/dev/drm/radeon/trinity_dpm.c

1649

dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>

sys/dev/drm/radeon/trinity_dpm.c

1719

u32 sclk;

sys/dev/drm/radeon/trinity_dpm.c

173

static const u32 trinity_sysls_disable[] =

sys/dev/drm/radeon/trinity_dpm.c

1810

u32 sclk;

sys/dev/drm/radeon/trinity_dpm.c

1831

static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)

sys/dev/drm/radeon/trinity_dpm.c

1834

u32 divider;

sys/dev/drm/radeon/trinity_dpm.c

197

static const u32 trinity_sysls_enable[] =

sys/dev/drm/radeon/trinity_dpm.c

2040

u32 current_index =

sys/dev/drm/radeon/trinity_dpm.c

2055

u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev)

sys/dev/drm/radeon/trinity_dpm.c

2061

u32 current_index =

sys/dev/drm/radeon/trinity_dpm.c

2073

u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev)

sys/dev/drm/radeon/trinity_dpm.c

2094

u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/trinity_dpm.c

2105

u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low)

sys/dev/drm/radeon/trinity_dpm.c

220

static const u32 trinity_override_mgpg_sequences[] =

sys/dev/drm/radeon/trinity_dpm.c

347

const u32 *seq, u32 count);

sys/dev/drm/radeon/trinity_dpm.c

370

u32 p, u;

sys/dev/drm/radeon/trinity_dpm.c

371

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

373

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/trinity_dpm.c

374

u32 sssd = 1;

sys/dev/drm/radeon/trinity_dpm.c

376

u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;

sys/dev/drm/radeon/trinity_dpm.c

40

static const u32 trinity_mgcg_shls_default[] =

sys/dev/drm/radeon/trinity_dpm.c

410

u32 local0;

sys/dev/drm/radeon/trinity_dpm.c

411

u32 local1;

sys/dev/drm/radeon/trinity_dpm.c

438

u32 count;

sys/dev/drm/radeon/trinity_dpm.c

439

const u32 *seq = NULL;

sys/dev/drm/radeon/trinity_dpm.c

442

count = sizeof(trinity_mgcg_shls_default) / (3 * sizeof(u32));

sys/dev/drm/radeon/trinity_dpm.c

461

const u32 *seq, u32 count)

sys/dev/drm/radeon/trinity_dpm.c

463

u32 i, length = count * 3;

sys/dev/drm/radeon/trinity_dpm.c

470

const u32 *seq, u32 count)

sys/dev/drm/radeon/trinity_dpm.c

472

u32 i, length = count * 2;

sys/dev/drm/radeon/trinity_dpm.c

481

u32 count;

sys/dev/drm/radeon/trinity_dpm.c

482

const u32 *seq = NULL;

sys/dev/drm/radeon/trinity_dpm.c

485

count = sizeof(trinity_override_mgpg_sequences) / (2 * sizeof(u32));

sys/dev/drm/radeon/trinity_dpm.c

493

u32 count;

sys/dev/drm/radeon/trinity_dpm.c

494

const u32 *seq = NULL;

sys/dev/drm/radeon/trinity_dpm.c

498

count = sizeof(trinity_sysls_enable) / (3 * sizeof(u32));

sys/dev/drm/radeon/trinity_dpm.c

501

count = sizeof(trinity_sysls_disable) / (3 * sizeof(u32));

sys/dev/drm/radeon/trinity_dpm.c

524

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

589

u32 index, u32 sclk)

sys/dev/drm/radeon/trinity_dpm.c

593

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

594

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

618

u32 index, u32 divider)

sys/dev/drm/radeon/trinity_dpm.c

620

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

621

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

630

u32 index, u32 divider)

sys/dev/drm/radeon/trinity_dpm.c

632

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

633

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

641

static void trinity_set_vid(struct radeon_device *rdev, u32 index, u32 vid)

sys/dev/drm/radeon/trinity_dpm.c

644

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid);

sys/dev/drm/radeon/trinity_dpm.c

645

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

646

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

660

u32 index, u32 gnb_slow)

sys/dev/drm/radeon/trinity_dpm.c

662

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

663

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

672

u32 index, u32 force_nbp_state)

sys/dev/drm/radeon/trinity_dpm.c

674

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

675

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

684

u32 index, u32 wm)

sys/dev/drm/radeon/trinity_dpm.c

686

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

687

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

696

u32 index, u32 wm)

sys/dev/drm/radeon/trinity_dpm.c

698

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

699

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

708

u32 index, u32 at)

sys/dev/drm/radeon/trinity_dpm.c

710

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

711

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

720

struct trinity_pl *pl, u32 index)

sys/dev/drm/radeon/trinity_dpm.c

739

u32 index, bool enable)

sys/dev/drm/radeon/trinity_dpm.c

741

u32 value;

sys/dev/drm/radeon/trinity_dpm.c

742

u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;

sys/dev/drm/radeon/trinity_dpm.c

761

u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

796

u32 sclk_dpm_cntl;

sys/dev/drm/radeon/trinity_dpm.c

850

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

851

u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;

sys/dev/drm/radeon/trinity_dpm.c

865

u32 i;

sys/dev/drm/radeon/trinity_dpm.c

878

u32 uvdstates = (ps->vclk_low_divider |

sys/dev/drm/radeon/trinity_dpm.c

887

u32 interval)

sys/dev/drm/radeon/trinity_dpm.c

889

u32 p, u;

sys/dev/drm/radeon/trinity_dpm.c

890

u32 tp = RREG32_SMC(PM_TP);

sys/dev/drm/radeon/trinity_dpm.c

891

u32 val;

sys/dev/drm/radeon/trinity_dpm.c

892

u32 xclk = radeon_get_xclk(rdev);

sys/dev/drm/radeon/trinity_dpm.c

944

u32 tmp = RREG32(CG_MISC_REG);

sys/dev/drm/radeon/trinity_dpm.h

100

u32 min_sclk_did;

sys/dev/drm/radeon/trinity_dpm.h

125

int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);

sys/dev/drm/radeon/trinity_dpm.h

126

int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n);

sys/dev/drm/radeon/trinity_dpm.h

31

u32 sclk;

sys/dev/drm/radeon/trinity_dpm.h

48

u32 num_levels;

sys/dev/drm/radeon/trinity_dpm.h

51

u32 nbps_flags;

sys/dev/drm/radeon/trinity_dpm.h

52

u32 bapm_flags;

sys/dev/drm/radeon/trinity_dpm.h

59

u32 vclk_low_divider;

sys/dev/drm/radeon/trinity_dpm.h

60

u32 vclk_high_divider;

sys/dev/drm/radeon/trinity_dpm.h

61

u32 dclk_low_divider;

sys/dev/drm/radeon/trinity_dpm.h

62

u32 dclk_high_divider;

sys/dev/drm/radeon/trinity_dpm.h

69

u32 vclk;

sys/dev/drm/radeon/trinity_dpm.h

70

u32 dclk;

sys/dev/drm/radeon/trinity_dpm.h

77

u32 bootup_uma_clk;

sys/dev/drm/radeon/trinity_dpm.h

78

u32 bootup_sclk;

sys/dev/drm/radeon/trinity_dpm.h

79

u32 min_sclk;

sys/dev/drm/radeon/trinity_dpm.h

80

u32 dentist_vco_freq;

sys/dev/drm/radeon/trinity_dpm.h

81

u32 nb_dpm_enable;

sys/dev/drm/radeon/trinity_dpm.h

82

u32 nbp_mclk[TRINITY_NUM_NBPSTATES];

sys/dev/drm/radeon/trinity_dpm.h

83

u32 nbp_nclk[TRINITY_NUM_NBPSTATES];

sys/dev/drm/radeon/trinity_dpm.h

90

u32 uma_channel_number;

sys/dev/drm/radeon/trinity_dpm.h

95

u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];

sys/dev/drm/radeon/trinity_dpm.h

96

u32 dpm_interval;

sys/dev/drm/radeon/trinity_dpm.h

97

u32 thermal_auto_throttling;

sys/dev/drm/radeon/trinity_smc.c

30

static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id)

sys/dev/drm/radeon/trinity_smc.c

33

u32 v = 0;

sys/dev/drm/radeon/trinity_smc.c

74

int trinity_dpm_force_state(struct radeon_device *rdev, u32 n)

sys/dev/drm/radeon/trinity_smc.c

81

int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n)

sys/dev/drm/radeon/uvd_v1_0.c

270

u32 lmi_swap_cntl = 0;

sys/dev/drm/radeon/uvd_v1_0.c

271

u32 mp_swap_cntl = 0;

sys/dev/drm/radeon/vce_v1_0.c

105

u32 tmp;

sys/dev/drm/radeon/vce_v1_0.c

138

u32 tmp;

sys/dev/drm/radeon/vce_v2_0.c

132

u32 tmp;

sys/dev/drm/radeon/vce_v2_0.c

40

u32 tmp;

sys/dev/drm/radeon/vce_v2_0.c

75

u32 orig, tmp;

sys/dev/misc/syscons/scvgarndr.c

442

uint32_t u32 = 0;

sys/dev/misc/syscons/scvgarndr.c

449

u32 += scp->ega_palette[color] << (i * 8 * pixel_size);

sys/dev/misc/syscons/scvgarndr.c

456

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

466

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

480

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

491

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

501

uint32_t u32;

sys/dev/misc/syscons/scvgarndr.c

505

u32 = (color << 24) + (color << 16) + (color << 8) + color;

sys/dev/misc/syscons/scvgarndr.c

512

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

522

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

535

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

545

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

595

uint32_t fg, bg, u32;

sys/dev/misc/syscons/scvgarndr.c

628

u32 = 0;

sys/dev/misc/syscons/scvgarndr.c

631

u32 += (*char_data & (1 << pos--) ?

sys/dev/misc/syscons/scvgarndr.c

635

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

655

uint32_t fg, bg, u32;

sys/dev/misc/syscons/scvgarndr.c

682

u32 = ((*char_data & 1 ? fg : bg) << 24) +

sys/dev/misc/syscons/scvgarndr.c

686

writel(p + 4, u32);

sys/dev/misc/syscons/scvgarndr.c

688

u32 = ((*char_data & 16 ? fg : bg) << 24) +

sys/dev/misc/syscons/scvgarndr.c

692

writel(p, u32);

sys/dev/misc/syscons/scvgarndr.c

782

uint32_t fg, bg, u32;

sys/dev/misc/syscons/scvgarndr.c

815

u32 = 0;

sys/dev/misc/syscons/scvgarndr.c

818

u32 += (*char_data & (1 << pos--) ?

sys/dev/misc/syscons/scvgarndr.c

822

writel(draw_pos, u32);

sys/dev/misc/syscons/scvgarndr.c

835

uint32_t fg, bg, u32;

sys/dev/misc/syscons/scvgarndr.c

860

u32 = ((*char_data & 1 ? fg : bg) << 24) +

sys/dev/misc/syscons/scvgarndr.c

864

writel(draw_pos + 4, u32);

sys/dev/misc/syscons/scvgarndr.c

866

u32 = ((*char_data & 16 ? fg : bg) << 24) +

sys/dev/misc/syscons/scvgarndr.c

870

writel(draw_pos, u32);

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

334

uint32_t low1, low2, u32;

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

338

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

351

u32++;

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

353

return (((uint64_t) u32) << 32) | ((uint64_t) low2);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

330

uint32_t low1, low2, u32;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

334

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

347

u32++;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

349

return (((uint64_t) u32) << 32) | ((uint64_t) low2);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

235

uint32_t low1, low2, u32;

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

239

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

252

u32++;

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

254

return (((uint64_t) u32) << 32) | ((uint64_t) low2);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c

109

uint32_t low1, low2, u32;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c

113

u32 = OS_REG_READ(ah, AR_TSF_U32);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c

126

u32++;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_misc.c

128

return (((uint64_t) u32) << 32) | ((uint64_t) low2);

sys/dev/netif/bce/if_bce.c

1201

static u32

sys/dev/netif/bce/if_bce.c

328

static uint32_t bce_shmem_rd(struct bce_softc *, u32);

sys/dev/netif/bce/if_bcefw.h

11735

u32 bce_RXP_b09FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

11736

u32 bce_RXP_b09FwRodata[(0x33c/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

11790

u32 bce_RXP_b09FwBss[(0x1bc/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

11791

u32 bce_RXP_b09FwSbss[(0x78/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

11792

u32 bce_RXP_b09FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

11798

u32 bce_CP_b09FwStartAddr = 0x080000a0;

sys/dev/netif/bce/if_bcefw.h

11799

u32 bce_CP_b09FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

11801

u32 bce_CP_b09FwDataAddr = 0x08005920;

sys/dev/netif/bce/if_bcefw.h

11803

u32 bce_CP_b09FwRodataAddr = 0x08005744;

sys/dev/netif/bce/if_bcefw.h

11805

u32 bce_CP_b09FwBssAddr = 0x08005a58;

sys/dev/netif/bce/if_bcefw.h

11807

u32 bce_CP_b09FwSbssAddr = 0x080059b0;

sys/dev/netif/bce/if_bcefw.h

11809

u32 bce_CP_b09FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

11811

u32 bce_CP_b09FwText[(0x5744/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

1253

u32 bce_COM_b06FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

1254

u32 bce_COM_b06FwRodata[(0x14/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

1258

u32 bce_COM_b06FwBss[(0xc4/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

1259

u32 bce_COM_b06FwSbss[(0x38/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

1260

u32 bce_COM_b06FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

1266

u32 bce_RXP_b06FwStartAddr = 0x08003210;

sys/dev/netif/bce/if_bcefw.h

1267

u32 bce_RXP_b06FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

1269

u32 bce_RXP_b06FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

1271

u32 bce_RXP_b06FwRodataAddr = 0x080072d0;

sys/dev/netif/bce/if_bcefw.h

1273

u32 bce_RXP_b06FwBssAddr = 0x0800736c;

sys/dev/netif/bce/if_bcefw.h

1275

u32 bce_RXP_b06FwSbssAddr = 0x08007320;

sys/dev/netif/bce/if_bcefw.h

1277

u32 bce_RXP_b06FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

1279

u32 bce_RXP_b06FwText[(0x72d0/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

13209

u32 bce_CP_b09FwData[(0x84/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

13219

u32 bce_CP_b09FwRodata[(0x1c0/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

13249

u32 bce_CP_b09FwBss[(0x19c/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

13250

u32 bce_CP_b09FwSbss[(0xa8/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

13251

u32 bce_CP_b09FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

13254

u32 bce_xi_rv2p_proc1[] = {

sys/dev/netif/bce/if_bcefw.h

13545

u32 bce_xi_rv2p_proc2[] = {

sys/dev/netif/bce/if_bcefw.h

14014

u32 bce_xi90_rv2p_proc1[] = {

sys/dev/netif/bce/if_bcefw.h

14320

u32 bce_xi90_rv2p_proc2[] = {

sys/dev/netif/bce/if_bcefw.h

3118

u32 bce_RXP_b06FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3119

u32 bce_RXP_b06FwRodata[(0x24/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

3124

u32 bce_RXP_b06FwBss[(0x440/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3125

u32 bce_RXP_b06FwSbss[(0x4c/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3126

u32 bce_RXP_b06FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3132

u32 bce_TPAT_b06FwStartAddr = 0x08000490;

sys/dev/netif/bce/if_bcefw.h

3133

u32 bce_TPAT_b06FwTextAddr = 0x08000400;

sys/dev/netif/bce/if_bcefw.h

3135

u32 bce_TPAT_b06FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

3137

u32 bce_TPAT_b06FwRodataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

3139

u32 bce_TPAT_b06FwBssAddr = 0x08001c44;

sys/dev/netif/bce/if_bcefw.h

3141

u32 bce_TPAT_b06FwSbssAddr = 0x08001c00;

sys/dev/netif/bce/if_bcefw.h

3143

u32 bce_TPAT_b06FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

3145

u32 bce_TPAT_b06FwText[(0x17d4/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

3528

u32 bce_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3529

u32 bce_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3530

u32 bce_TPAT_b06FwBss[(0x450/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3531

u32 bce_TPAT_b06FwSbss[(0x44/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3532

u32 bce_TPAT_b06FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

3538

u32 bce_TXP_b06FwStartAddr = 0x080000a8;

sys/dev/netif/bce/if_bcefw.h

3539

u32 bce_TXP_b06FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

3541

u32 bce_TXP_b06FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

3543

u32 bce_TXP_b06FwRodataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

3545

u32 bce_TXP_b06FwBssAddr = 0x08003c88;

sys/dev/netif/bce/if_bcefw.h

3547

u32 bce_TXP_b06FwSbssAddr = 0x08003c20;

sys/dev/netif/bce/if_bcefw.h

3549

u32 bce_TXP_b06FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

3551

u32 bce_TXP_b06FwText[(0x3bfc/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

4513

u32 bce_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

4514

u32 bce_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

4515

u32 bce_TXP_b06FwBss[(0x14c/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

4516

u32 bce_TXP_b06FwSbss[(0x68/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

4517

u32 bce_TXP_b06FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

4523

u32 bce_CP_b06FwStartAddr = 0x080000a0;

sys/dev/netif/bce/if_bcefw.h

4524

u32 bce_CP_b06FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

4526

u32 bce_CP_b06FwDataAddr = 0x08005800;

sys/dev/netif/bce/if_bcefw.h

4528

u32 bce_CP_b06FwRodataAddr = 0x08005688;

sys/dev/netif/bce/if_bcefw.h

4530

u32 bce_CP_b06FwBssAddr = 0x08005978;

sys/dev/netif/bce/if_bcefw.h

4532

u32 bce_CP_b06FwSbssAddr = 0x08005884;

sys/dev/netif/bce/if_bcefw.h

4534

u32 bce_CP_b06FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

4536

u32 bce_CP_b06FwText[(0x5688/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

48

u32 bce_COM_b06FwStartAddr = 0x08000118;

sys/dev/netif/bce/if_bcefw.h

49

u32 bce_COM_b06FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

51

u32 bce_COM_b06FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

53

u32 bce_COM_b06FwRodataAddr = 0x08004a68;

sys/dev/netif/bce/if_bcefw.h

55

u32 bce_COM_b06FwBssAddr = 0x08004ad8;

sys/dev/netif/bce/if_bcefw.h

57

u32 bce_COM_b06FwSbssAddr = 0x08004aa0;

sys/dev/netif/bce/if_bcefw.h

59

u32 bce_COM_b06FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

5922

u32 bce_CP_b06FwData[(0x84/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

5932

u32 bce_CP_b06FwRodata[(0x158/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

5955

u32 bce_CP_b06FwBss[(0x5d8/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

5956

u32 bce_CP_b06FwSbss[(0xf1/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

5957

u32 bce_CP_b06FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

5960

u32 bce_rv2p_proc1[] = {

sys/dev/netif/bce/if_bcefw.h

61

u32 bce_COM_b06FwText[(0x4a68/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

6251

u32 bce_rv2p_proc2[] = {

sys/dev/netif/bce/if_bcefw.h

6672

u32 bce_TXP_b09FwStartAddr = 0x080000a8;

sys/dev/netif/bce/if_bcefw.h

6673

u32 bce_TXP_b09FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

6675

u32 bce_TXP_b09FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

6677

u32 bce_TXP_b09FwRodataAddr = 0x08003d28;

sys/dev/netif/bce/if_bcefw.h

6679

u32 bce_TXP_b09FwBssAddr = 0x08003df0;

sys/dev/netif/bce/if_bcefw.h

6681

u32 bce_TXP_b09FwSbssAddr = 0x08003d88;

sys/dev/netif/bce/if_bcefw.h

6683

u32 bce_TXP_b09FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

6685

u32 bce_TXP_b09FwText[(0x3d28/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

7665

u32 bce_TXP_b09FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

7666

u32 bce_TXP_b09FwRodata[(0x30/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

7671

u32 bce_TXP_b09FwBss[(0x24c/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

7672

u32 bce_TXP_b09FwSbss[(0x64/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

7673

u32 bce_TXP_b09FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

7679

u32 bce_TPAT_b09FwStartAddr = 0x08000490;

sys/dev/netif/bce/if_bcefw.h

7680

u32 bce_TPAT_b09FwTextAddr = 0x08000400;

sys/dev/netif/bce/if_bcefw.h

7682

u32 bce_TPAT_b09FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

7684

u32 bce_TPAT_b09FwRodataAddr = 0x080016fc;

sys/dev/netif/bce/if_bcefw.h

7686

u32 bce_TPAT_b09FwBssAddr = 0x0800175c;

sys/dev/netif/bce/if_bcefw.h

7688

u32 bce_TPAT_b09FwSbssAddr = 0x08001720;

sys/dev/netif/bce/if_bcefw.h

7690

u32 bce_TPAT_b09FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

7692

u32 bce_TPAT_b09FwText[(0x12fc/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

7998

u32 bce_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

7999

u32 bce_TPAT_b09FwRodata[(0x4/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

8001

u32 bce_TPAT_b09FwBss[(0x12b4/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

8002

u32 bce_TPAT_b09FwSbss[(0x3c/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

8003

u32 bce_TPAT_b09FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

8009

u32 bce_COM_b09FwStartAddr = 0x08000118;

sys/dev/netif/bce/if_bcefw.h

8010

u32 bce_COM_b09FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

8012

u32 bce_COM_b09FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

8014

u32 bce_COM_b09FwRodataAddr = 0x08005594;

sys/dev/netif/bce/if_bcefw.h

8016

u32 bce_COM_b09FwBssAddr = 0x08005638;

sys/dev/netif/bce/if_bcefw.h

8018

u32 bce_COM_b09FwSbssAddr = 0x08005608;

sys/dev/netif/bce/if_bcefw.h

8020

u32 bce_COM_b09FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

8022

u32 bce_COM_b09FwText[(0x5594/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

9393

u32 bce_COM_b09FwData[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

9394

u32 bce_COM_b09FwRodata[(0x38/4) + 1] = {

sys/dev/netif/bce/if_bcefw.h

9399

u32 bce_COM_b09FwBss[(0x11c/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

9400

u32 bce_COM_b09FwSbss[(0x30/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

9401

u32 bce_COM_b09FwSdata[(0x0/4) + 1] = { 0x0 };

sys/dev/netif/bce/if_bcefw.h

9407

u32 bce_RXP_b09FwStartAddr = 0x08003210;

sys/dev/netif/bce/if_bcefw.h

9408

u32 bce_RXP_b09FwTextAddr = 0x08000000;

sys/dev/netif/bce/if_bcefw.h

9410

u32 bce_RXP_b09FwDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

9412

u32 bce_RXP_b09FwRodataAddr = 0x08009090;

sys/dev/netif/bce/if_bcefw.h

9414

u32 bce_RXP_b09FwBssAddr = 0x08009478;

sys/dev/netif/bce/if_bcefw.h

9416

u32 bce_RXP_b09FwSbssAddr = 0x08009400;

sys/dev/netif/bce/if_bcefw.h

9418

u32 bce_RXP_b09FwSDataAddr = 0x00000000;

sys/dev/netif/bce/if_bcefw.h

9420

u32 bce_RXP_b09FwText[(0x9090/4) + 1] = {

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1045

u32 reg;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1191

u32 ctrl;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1281

u32 tipg;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1282

u32 i = 0;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1333

u32 tipg;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1334

u32 i = 0;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1380

static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1383

u32 kmrnctrlsta;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1417

static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1420

u32 kmrnctrlsta;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

143

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

404

u32 swfw_sync;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

405

u32 swmask = mask;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

406

u32 fwmask = mask << 16;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

451

u32 swfw_sync;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

46

u32 offset,

sys/dev/netif/ig_hal/e1000_80003es2lan.c

474

u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_80003es2lan.c

477

u32 page_select;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

49

u32 offset,

sys/dev/netif/ig_hal/e1000_80003es2lan.c

545

u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_80003es2lan.c

548

u32 page_select;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

634

u32 mask = E1000_NVM_CFG_DONE_PORT_0;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

66

static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_80003es2lan.c

68

static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_80003es2lan.c

821

u32 ctrl;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

887

u32 reg_data;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

996

u32 reg;

sys/dev/netif/ig_hal/e1000_82540.c

120

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_82540.c

272

u32 ctrl, manc;

sys/dev/netif/ig_hal/e1000_82540.c

331

u32 txdctl, ctrl_ext;

sys/dev/netif/ig_hal/e1000_82540.c

413

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82541.c

1091

u32 ret_val;

sys/dev/netif/ig_hal/e1000_82541.c

131

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_82541.c

295

u32 ledctl, ctrl, manc;

sys/dev/netif/ig_hal/e1000_82541.c

375

u32 i, txdctl;

sys/dev/netif/ig_hal/e1000_82541.c

499

u32 ledctl;

sys/dev/netif/ig_hal/e1000_82541.c

535

u32 ctrl, ledctl;

sys/dev/netif/ig_hal/e1000_82541.c

671

u32 idle_errs = 0;

sys/dev/netif/ig_hal/e1000_82542.c

196

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82542.c

248

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82542.c

375

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_82542.c

394

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_82542.c

414

static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_82542.c

416

u32 rar_low, rar_high;

sys/dev/netif/ig_hal/e1000_82542.c

424

rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |

sys/dev/netif/ig_hal/e1000_82542.c

425

((u32) addr[2] << 16) | ((u32) addr[3] << 24));

sys/dev/netif/ig_hal/e1000_82542.c

427

rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

sys/dev/netif/ig_hal/e1000_82542.c

448

u32 e1000_translate_register_82542(u32 reg)

sys/dev/netif/ig_hal/e1000_82542.c

50

static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_82543.c

1017

u32 ctrl_ext;

sys/dev/netif/ig_hal/e1000_82543.c

1058

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82543.c

1146

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82543.c

1196

u32 icr, rctl;

sys/dev/netif/ig_hal/e1000_82543.c

1332

u32 rxcw, ctrl, status;

sys/dev/netif/ig_hal/e1000_82543.c

1401

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82543.c

1453

static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)

sys/dev/netif/ig_hal/e1000_82543.c

1455

u32 temp;

sys/dev/netif/ig_hal/e1000_82543.c

1478

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_82543.c

1505

u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_82543.c

408

struct e1000_hw_stats *stats, u32 frame_len,

sys/dev/netif/ig_hal/e1000_82543.c

409

u8 *mac_addr, u32 max_frame_size)

sys/dev/netif/ig_hal/e1000_82543.c

483

static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_82543.c

485

u32 mdic;

sys/dev/netif/ig_hal/e1000_82543.c

49

static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_82543.c

51

static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_82543.c

539

static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_82543.c

541

u32 mdic;

sys/dev/netif/ig_hal/e1000_82543.c

570

mdic |= (u32)data;

sys/dev/netif/ig_hal/e1000_82543.c

586

static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)

sys/dev/netif/ig_hal/e1000_82543.c

605

static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)

sys/dev/netif/ig_hal/e1000_82543.c

626

static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,

sys/dev/netif/ig_hal/e1000_82543.c

629

u32 ctrl, mask;

sys/dev/netif/ig_hal/e1000_82543.c

64

static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_82543.c

65

u32 value);

sys/dev/netif/ig_hal/e1000_82543.c

680

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82543.c

69

static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);

sys/dev/netif/ig_hal/e1000_82543.c

71

static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);

sys/dev/netif/ig_hal/e1000_82543.c

73

static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,

sys/dev/netif/ig_hal/e1000_82543.c

859

u32 ctrl_ext;

sys/dev/netif/ig_hal/e1000_82543.c

899

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82543.c

956

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82543.h

51

u32 frame_len, u8 *mac_addr,

sys/dev/netif/ig_hal/e1000_82543.h

52

u32 max_frame_size);

sys/dev/netif/ig_hal/e1000_82571.c

1061

u32 ctrl, ctrl_ext, eecd, tctl;

sys/dev/netif/ig_hal/e1000_82571.c

1187

u32 reg_data;

sys/dev/netif/ig_hal/e1000_82571.c

1266

u32 reg;

sys/dev/netif/ig_hal/e1000_82571.c

1400

u32 offset;

sys/dev/netif/ig_hal/e1000_82571.c

1401

u32 vfta_value = 0;

sys/dev/netif/ig_hal/e1000_82571.c

1402

u32 vfta_offset = 0;

sys/dev/netif/ig_hal/e1000_82571.c

1403

u32 vfta_bit_in_reg = 0;

sys/dev/netif/ig_hal/e1000_82571.c

1469

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82571.c

1470

u32 i;

sys/dev/netif/ig_hal/e1000_82571.c

1566

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82571.c

1647

u32 rxcw;

sys/dev/netif/ig_hal/e1000_82571.c

1648

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82571.c

1649

u32 status;

sys/dev/netif/ig_hal/e1000_82571.c

1650

u32 txcw;

sys/dev/netif/ig_hal/e1000_82571.c

1651

u32 i;

sys/dev/netif/ig_hal/e1000_82571.c

206

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_82571.c

287

u32 swsm = 0;

sys/dev/netif/ig_hal/e1000_82571.c

288

u32 swsm2 = 0;

sys/dev/netif/ig_hal/e1000_82571.c

489

phy->id = (u32)(phy_id << 16);

sys/dev/netif/ig_hal/e1000_82571.c

495

phy->id |= (u32)(phy_id);

sys/dev/netif/ig_hal/e1000_82571.c

496

phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

sys/dev/netif/ig_hal/e1000_82571.c

514

u32 swsm;

sys/dev/netif/ig_hal/e1000_82571.c

575

u32 swsm;

sys/dev/netif/ig_hal/e1000_82571.c

595

u32 extcnf_ctrl;

sys/dev/netif/ig_hal/e1000_82571.c

632

u32 extcnf_ctrl;

sys/dev/netif/ig_hal/e1000_82571.c

686

u32 data = E1000_READ_REG(hw, E1000_POEMB);

sys/dev/netif/ig_hal/e1000_82571.c

712

u32 data = E1000_READ_REG(hw, E1000_POEMB);

sys/dev/netif/ig_hal/e1000_82571.c

822

u32 eecd;

sys/dev/netif/ig_hal/e1000_82571.c

909

u32 i, eewr = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1000

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_82575.c

1011

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_82575.c

1054

u32 swfw_sync;

sys/dev/netif/ig_hal/e1000_82575.c

1055

u32 swmask = mask;

sys/dev/netif/ig_hal/e1000_82575.c

1056

u32 fwmask = mask << 16;

sys/dev/netif/ig_hal/e1000_82575.c

1106

u32 swfw_sync;

sys/dev/netif/ig_hal/e1000_82575.c

113

static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);

sys/dev/netif/ig_hal/e1000_82575.c

1133

u32 mask = E1000_NVM_CFG_DONE_PORT_0;

sys/dev/netif/ig_hal/e1000_82575.c

114

static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);

sys/dev/netif/ig_hal/e1000_82575.c

115

static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);

sys/dev/netif/ig_hal/e1000_82575.c

116

static bool e1000_get_i2c_data(u32 *i2cctl);

sys/dev/netif/ig_hal/e1000_82575.c

1295

u32 reg;

sys/dev/netif/ig_hal/e1000_82575.c

1331

u32 pcs;

sys/dev/netif/ig_hal/e1000_82575.c

1332

u32 status;

sys/dev/netif/ig_hal/e1000_82575.c

134

u32 reg = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1393

u32 reg;

sys/dev/netif/ig_hal/e1000_82575.c

1428

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82575.c

1549

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82575.c

1551

u32 phpm_reg;

sys/dev/netif/ig_hal/e1000_82575.c

1635

u32 ctrl_ext, ctrl_reg, reg, anadv_reg;

sys/dev/netif/ig_hal/e1000_82575.c

167

u32 ctrl_ext;

sys/dev/netif/ig_hal/e1000_82575.c

1780

u32 ctrl_ext = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1781

u32 link_mode = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1857

u32 ctrl_ext = 0;

sys/dev/netif/ig_hal/e1000_82575.c

2037

u32 tctl_ext;

sys/dev/netif/ig_hal/e1000_82575.c

2147

u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;

sys/dev/netif/ig_hal/e1000_82575.c

2227

u32 gcr = E1000_READ_REG(hw, E1000_GCR);

sys/dev/netif/ig_hal/e1000_82575.c

2276

u32 reg_val, reg_offset;

sys/dev/netif/ig_hal/e1000_82575.c

2314

u32 dtxswc;

sys/dev/netif/ig_hal/e1000_82575.c

2351

u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);

sys/dev/netif/ig_hal/e1000_82575.c

2370

static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_82575.c

2396

static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_82575.c

2425

u32 mdicnfg;

sys/dev/netif/ig_hal/e1000_82575.c

2465

u32 ctrl;

sys/dev/netif/ig_hal/e1000_82575.c

2560

u16 e1000_rxpbs_adjust_82580(u32 data)

sys/dev/netif/ig_hal/e1000_82575.c

3020

u32 ipcnfg, eeer;

sys/dev/netif/ig_hal/e1000_82575.c

3032

u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);

sys/dev/netif/ig_hal/e1000_82575.c

3196

u32 offset;

sys/dev/netif/ig_hal/e1000_82575.c

3218

void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)

sys/dev/netif/ig_hal/e1000_82575.c

3241

u32 ctrl_ext, i2cparams;

sys/dev/netif/ig_hal/e1000_82575.c

3274

u32 max_retry = 10;

sys/dev/netif/ig_hal/e1000_82575.c

3275

u32 retry = 1;

sys/dev/netif/ig_hal/e1000_82575.c

332

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_82575.c

3365

u32 max_retry = 1;

sys/dev/netif/ig_hal/e1000_82575.c

3366

u32 retry = 0;

sys/dev/netif/ig_hal/e1000_82575.c

3432

u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);

sys/dev/netif/ig_hal/e1000_82575.c

3463

u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);

sys/dev/netif/ig_hal/e1000_82575.c

3514

u32 i2cctl;

sys/dev/netif/ig_hal/e1000_82575.c

3546

u32 i = 0;

sys/dev/netif/ig_hal/e1000_82575.c

3547

u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);

sys/dev/netif/ig_hal/e1000_82575.c

3548

u32 timeout = 10;

sys/dev/netif/ig_hal/e1000_82575.c

3591

u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);

sys/dev/netif/ig_hal/e1000_82575.c

3621

u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);

sys/dev/netif/ig_hal/e1000_82575.c

3652

static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)

sys/dev/netif/ig_hal/e1000_82575.c

3672

static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)

sys/dev/netif/ig_hal/e1000_82575.c

3694

static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)

sys/dev/netif/ig_hal/e1000_82575.c

3729

static bool e1000_get_i2c_data(u32 *i2cctl)

sys/dev/netif/ig_hal/e1000_82575.c

3752

u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);

sys/dev/netif/ig_hal/e1000_82575.c

3753

u32 i;

sys/dev/netif/ig_hal/e1000_82575.c

596

static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_82575.c

60

static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_82575.c

629

static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_82575.c

65

u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_82575.c

665

u32 ctrl_ext;

sys/dev/netif/ig_hal/e1000_82575.c

666

u32 mdic;

sys/dev/netif/ig_hal/e1000_82575.c

67

u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_82575.c

80

u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_82575.c

899

u32 data;

sys/dev/netif/ig_hal/e1000_82575.c

946

u32 data;

sys/dev/netif/ig_hal/e1000_82575.h

101

u32 ip_config;

sys/dev/netif/ig_hal/e1000_82575.h

103

u32 iplen:9;

sys/dev/netif/ig_hal/e1000_82575.h

104

u32 maclen:7;

sys/dev/netif/ig_hal/e1000_82575.h

105

u32 vlan_tag:16;

sys/dev/netif/ig_hal/e1000_82575.h

108

u32 seq_num;

sys/dev/netif/ig_hal/e1000_82575.h

112

u32 mkrloc:9;

sys/dev/netif/ig_hal/e1000_82575.h

113

u32 tucmd:11;

sys/dev/netif/ig_hal/e1000_82575.h

114

u32 dtyp:4;

sys/dev/netif/ig_hal/e1000_82575.h

115

u32 adv:8;

sys/dev/netif/ig_hal/e1000_82575.h

116

u32 rsvd:4;

sys/dev/netif/ig_hal/e1000_82575.h

117

u32 idx:4;

sys/dev/netif/ig_hal/e1000_82575.h

118

u32 l4len:8;

sys/dev/netif/ig_hal/e1000_82575.h

119

u32 mss:16;

sys/dev/netif/ig_hal/e1000_82575.h

496

void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);

sys/dev/netif/ig_hal/e1000_82575.h

497

u16 e1000_rxpbs_adjust_82580(u32 data);

sys/dev/netif/ig_hal/e1000_82575.h

64

u32 data;

sys/dev/netif/ig_hal/e1000_82575.h

66

u32 datalen:16; /* Data buffer length */

sys/dev/netif/ig_hal/e1000_82575.h

67

u32 rsvd:4;

sys/dev/netif/ig_hal/e1000_82575.h

68

u32 dtyp:4; /* Descriptor type */

sys/dev/netif/ig_hal/e1000_82575.h

69

u32 dcmd:8; /* Descriptor command */

sys/dev/netif/ig_hal/e1000_82575.h

73

u32 data;

sys/dev/netif/ig_hal/e1000_82575.h

75

u32 status:4; /* Descriptor status */

sys/dev/netif/ig_hal/e1000_82575.h

76

u32 idx:4;

sys/dev/netif/ig_hal/e1000_82575.h

77

u32 popts:6; /* Packet Options */

sys/dev/netif/ig_hal/e1000_82575.h

78

u32 paylen:18; /* Payload length */

sys/dev/netif/ig_hal/e1000_api.c

1015

s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_api.c

1032

s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_api.c

1090

s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_api.c

1105

s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_api.c

1243

s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size)

sys/dev/netif/ig_hal/e1000_api.c

1258

s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)

sys/dev/netif/ig_hal/e1000_api.c

1352

s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,

sys/dev/netif/ig_hal/e1000_api.c

586

void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)

sys/dev/netif/ig_hal/e1000_api.c

602

u32 mc_addr_count)

sys/dev/netif/ig_hal/e1000_api.c

880

int e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_api.c

911

u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

sys/dev/netif/ig_hal/e1000_api.c

983

s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr)

sys/dev/netif/ig_hal/e1000_api.h

100

s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);

sys/dev/netif/ig_hal/e1000_api.h

101

s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);

sys/dev/netif/ig_hal/e1000_api.h

106

s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_api.h

107

s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_api.h

119

u32 e1000_translate_register_82542(u32 reg);

sys/dev/netif/ig_hal/e1000_api.h

54

s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr);

sys/dev/netif/ig_hal/e1000_api.h

63

void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);

sys/dev/netif/ig_hal/e1000_api.h

72

int e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_api.h

73

u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);

sys/dev/netif/ig_hal/e1000_api.h

75

u32 mc_addr_count);

sys/dev/netif/ig_hal/e1000_api.h

87

s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_api.h

88

s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_api.h

89

s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,

sys/dev/netif/ig_hal/e1000_hw.h

1001

u32 vf_number;

sys/dev/netif/ig_hal/e1000_hw.h

1002

u32 v2p_mailbox;

sys/dev/netif/ig_hal/e1000_hw.h

1063

s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

1064

s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

1065

void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

1066

void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

407

#define __le32 u32

sys/dev/netif/ig_hal/e1000_hw.h

646

u32 last_gprc;

sys/dev/netif/ig_hal/e1000_hw.h

647

u32 last_gptc;

sys/dev/netif/ig_hal/e1000_hw.h

648

u32 last_gorc;

sys/dev/netif/ig_hal/e1000_hw.h

649

u32 last_gotc;

sys/dev/netif/ig_hal/e1000_hw.h

650

u32 last_mprc;

sys/dev/netif/ig_hal/e1000_hw.h

651

u32 last_gotlbc;

sys/dev/netif/ig_hal/e1000_hw.h

652

u32 last_gptlbc;

sys/dev/netif/ig_hal/e1000_hw.h

653

u32 last_gorlbc;

sys/dev/netif/ig_hal/e1000_hw.h

654

u32 last_gprlbc;

sys/dev/netif/ig_hal/e1000_hw.h

669

u32 idle_errors;

sys/dev/netif/ig_hal/e1000_hw.h

670

u32 receive_errors;

sys/dev/netif/ig_hal/e1000_hw.h

674

u32 signature;

sys/dev/netif/ig_hal/e1000_hw.h

678

u32 reserved1;

sys/dev/netif/ig_hal/e1000_hw.h

734

void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);

sys/dev/netif/ig_hal/e1000_hw.h

742

void (*write_vfta)(struct e1000_hw *, u32, u32);

sys/dev/netif/ig_hal/e1000_hw.h

744

int (*rar_set)(struct e1000_hw *, u8*, u32);

sys/dev/netif/ig_hal/e1000_hw.h

747

s32 (*set_obff_timer)(struct e1000_hw *, u32);

sys/dev/netif/ig_hal/e1000_hw.h

778

s32 (*read_reg)(struct e1000_hw *, u32, u16 *);

sys/dev/netif/ig_hal/e1000_hw.h

779

s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);

sys/dev/netif/ig_hal/e1000_hw.h

780

s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);

sys/dev/netif/ig_hal/e1000_hw.h

785

s32 (*write_reg)(struct e1000_hw *, u32, u16);

sys/dev/netif/ig_hal/e1000_hw.h

786

s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);

sys/dev/netif/ig_hal/e1000_hw.h

787

s32 (*write_reg_page)(struct e1000_hw *, u32, u16);

sys/dev/netif/ig_hal/e1000_hw.h

814

u32 collision_delta;

sys/dev/netif/ig_hal/e1000_hw.h

815

u32 ledctl_default;

sys/dev/netif/ig_hal/e1000_hw.h

816

u32 ledctl_mode1;

sys/dev/netif/ig_hal/e1000_hw.h

817

u32 ledctl_mode2;

sys/dev/netif/ig_hal/e1000_hw.h

818

u32 mc_filter_type;

sys/dev/netif/ig_hal/e1000_hw.h

819

u32 tx_packet_delta;

sys/dev/netif/ig_hal/e1000_hw.h

820

u32 txcw;

sys/dev/netif/ig_hal/e1000_hw.h

832

u32 mta_shadow[MAX_MTA_REG];

sys/dev/netif/ig_hal/e1000_hw.h

849

u32 max_frame_size;

sys/dev/netif/ig_hal/e1000_hw.h

863

u32 addr;

sys/dev/netif/ig_hal/e1000_hw.h

864

u32 id;

sys/dev/netif/ig_hal/e1000_hw.h

865

u32 reset_delay_us; /* in usec */

sys/dev/netif/ig_hal/e1000_hw.h

866

u32 revision;

sys/dev/netif/ig_hal/e1000_hw.h

890

u32 flash_bank_size;

sys/dev/netif/ig_hal/e1000_hw.h

891

u32 flash_base_addr;

sys/dev/netif/ig_hal/e1000_hw.h

910

u32 high_water; /* Flow control high-water mark */

sys/dev/netif/ig_hal/e1000_hw.h

911

u32 low_water; /* Flow control low-water mark */

sys/dev/netif/ig_hal/e1000_hw.h

932

u32 tbi_compatibility;

sys/dev/netif/ig_hal/e1000_hw.h

939

u32 smb_counter;

sys/dev/netif/ig_hal/e1000_hw.h

962

s32 (*read)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_hw.h

963

s32 (*write)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_hw.h

964

s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_hw.h

965

s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_hw.h

972

u32 msgs_tx;

sys/dev/netif/ig_hal/e1000_hw.h

973

u32 msgs_rx;

sys/dev/netif/ig_hal/e1000_hw.h

975

u32 acks;

sys/dev/netif/ig_hal/e1000_hw.h

976

u32 reqs;

sys/dev/netif/ig_hal/e1000_hw.h

977

u32 rsts;

sys/dev/netif/ig_hal/e1000_hw.h

983

u32 timeout;

sys/dev/netif/ig_hal/e1000_hw.h

984

u32 usec_delay;

sys/dev/netif/ig_hal/e1000_hw.h

994

u32 mtu;

sys/dev/netif/ig_hal/e1000_i210.c

142

u32 swfw_sync;

sys/dev/netif/ig_hal/e1000_i210.c

164

u32 swsm;

sys/dev/netif/ig_hal/e1000_i210.c

325

u32 i, k, eewr = 0;

sys/dev/netif/ig_hal/e1000_i210.c

326

u32 attempts = 100000;

sys/dev/netif/ig_hal/e1000_i210.c

379

u32 invm_dword;

sys/dev/netif/ig_hal/e1000_i210.c

501

u32 *record = NULL;

sys/dev/netif/ig_hal/e1000_i210.c

502

u32 *next_record = NULL;

sys/dev/netif/ig_hal/e1000_i210.c

503

u32 i = 0;

sys/dev/netif/ig_hal/e1000_i210.c

504

u32 invm_dword = 0;

sys/dev/netif/ig_hal/e1000_i210.c

505

u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /

sys/dev/netif/ig_hal/e1000_i210.c

507

u32 buffer[E1000_INVM_SIZE];

sys/dev/netif/ig_hal/e1000_i210.c

697

u32 eec = 0;

sys/dev/netif/ig_hal/e1000_i210.c

718

u32 flup;

sys/dev/netif/ig_hal/e1000_i210.c

749

u32 i, reg;

sys/dev/netif/ig_hal/e1000_i210.c

90

u32 swfw_sync;

sys/dev/netif/ig_hal/e1000_i210.c

91

u32 swmask = mask;

sys/dev/netif/ig_hal/e1000_i210.c

92

u32 fwmask = mask << 16;

sys/dev/netif/ig_hal/e1000_i210.c

928

u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;

sys/dev/netif/ig_hal/e1000_i210.c

997

u32 mask = E1000_NVM_CFG_DONE_PORT_0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1008

u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1009

u32 status = E1000_READ_REG(hw, E1000_STATUS);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1087

u32 value, scale;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1117

u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |

sys/dev/netif/ig_hal/e1000_ich8lan.c

1130

u32 rxa;

sys/dev/netif/ig_hal/e1000_ich8lan.c

122

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1223

static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)

sys/dev/netif/ig_hal/e1000_ich8lan.c

1225

u32 svcr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1259

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

126

u32 offset, u8 *data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

127

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

129

static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

130

u32 *data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

132

u32 offset, u32 *data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

134

u32 offset, u32 data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

136

u32 offset, u32 dword);

sys/dev/netif/ig_hal/e1000_ich8lan.c

138

u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

140

u32 offset, u8 byte);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1407

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

147

static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1693

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1724

u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1728

u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);

sys/dev/netif/ig_hal/e1000_ich8lan.c

182

u32 grra:8; /* 0:7 GbE region Read Access */

sys/dev/netif/ig_hal/e1000_ich8lan.c

183

u32 grwa:8; /* 8:15 GbE region Write Access */

sys/dev/netif/ig_hal/e1000_ich8lan.c

184

u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */

sys/dev/netif/ig_hal/e1000_ich8lan.c

185

u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */

sys/dev/netif/ig_hal/e1000_ich8lan.c

1879

u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1935

u32 extcnf_ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1961

u32 fwsm;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1982

u32 fwsm;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2003

static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_ich8lan.c

2005

u32 rar_low, rar_high;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2012

rar_low = ((u32) addr[0] |

sys/dev/netif/ig_hal/e1000_ich8lan.c

2013

((u32) addr[1] << 8) |

sys/dev/netif/ig_hal/e1000_ich8lan.c

2014

((u32) addr[2] << 16) | ((u32) addr[3] << 24));

sys/dev/netif/ig_hal/e1000_ich8lan.c

2016

rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

sys/dev/netif/ig_hal/e1000_ich8lan.c

203

u32 phy_id = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2033

if (index < (u32) (hw->mac.rar_entry_count)) {

sys/dev/netif/ig_hal/e1000_ich8lan.c

206

u32 mac_reg = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2072

static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_ich8lan.c

2074

u32 rar_low, rar_high;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2075

u32 wlock_mac;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2082

rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |

sys/dev/netif/ig_hal/e1000_ich8lan.c

2083

((u32) addr[2] << 16) | ((u32) addr[3] << 24));

sys/dev/netif/ig_hal/e1000_ich8lan.c

2085

rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

sys/dev/netif/ig_hal/e1000_ich8lan.c

212

phy_id = (u32)(phy_reg << 16);

sys/dev/netif/ig_hal/e1000_ich8lan.c

2151

u32 mc_addr_count)

sys/dev/netif/ig_hal/e1000_ich8lan.c

219

phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

sys/dev/netif/ig_hal/e1000_ich8lan.c

2194

u32 fwsm;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2222

u32 strap = E1000_READ_REG(hw, E1000_STRAP);

sys/dev/netif/ig_hal/e1000_ich8lan.c

2223

u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>

sys/dev/netif/ig_hal/e1000_ich8lan.c

2263

u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;

sys/dev/netif/ig_hal/e1000_ich8lan.c

228

hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

sys/dev/netif/ig_hal/e1000_ich8lan.c

2366

ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,

sys/dev/netif/ig_hal/e1000_ich8lan.c

2472

u32 ctrl_reg = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2473

u32 ctrl_ext = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2474

u32 reg = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2525

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2699

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2734

static u32 e1000_calc_rx_da_crc(u8 mac[])

sys/dev/netif/ig_hal/e1000_ich8lan.c

2736

u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */

sys/dev/netif/ig_hal/e1000_ich8lan.c

2737

u32 i, j, mask, crc;

sys/dev/netif/ig_hal/e1000_ich8lan.c

274

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2762

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2783

u32 addr_high, addr_low;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3000

u32 mac_reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3021

u32 extcnf_ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3047

u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

318

u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3214

u32 phy_ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3310

u32 phy_ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3396

static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)

sys/dev/netif/ig_hal/e1000_ich8lan.c

3398

u32 eecd;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3400

u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3401

u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3402

u32 nvm_dword = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3504

u32 act_offset;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3506

u32 bank = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3507

u32 dword = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3599

u32 act_offset;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3601

u32 bank = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3740

static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)

sys/dev/netif/ig_hal/e1000_ich8lan.c

3744

u32 i = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3784

static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

3785

u32 *data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

3807

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

3829

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

3860

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

3865

u32 flash_linear_addr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3866

u32 flash_data = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3935

static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

3936

u32 *data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

3940

u32 flash_linear_addr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3964

hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3970

(u32)hsflctl.regval << 16);

sys/dev/netif/ig_hal/e1000_ich8lan.c

4056

u32 i, act_offset, new_bank_offset, old_bank_offset, bank;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4058

u32 dword = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4218

u32 i, act_offset, new_bank_offset, old_bank_offset, bank;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4417

static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

4422

u32 flash_linear_addr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4423

u32 flash_data = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4473

flash_data = (u32)data & 0x00FF;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4475

flash_data = (u32)data;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4514

static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

4515

u32 data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

4519

u32 flash_linear_addr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4549

hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4603

static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_ich8lan.c

4623

u32 offset, u32 dword)

sys/dev/netif/ig_hal/e1000_ich8lan.c

4660

u32 offset, u8 byte)

sys/dev/netif/ig_hal/e1000_ich8lan.c

4692

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)

sys/dev/netif/ig_hal/e1000_ich8lan.c

4697

u32 flash_linear_addr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4699

u32 flash_bank_size = nvm->flash_bank_size * 2;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4748

u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4848

const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4849

const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4943

u32 ctrl, reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5078

u32 ctrl_ext, txdctl, snoop;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5136

snoop = (u32) ~(PCIE_NO_SNOOP_ALL);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5162

u32 reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5299

u32 ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5390

u32 ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5455

u32 phy_ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5543

u32 reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5638

u32 phy_ctrl;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5654

u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5769

u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)

sys/dev/netif/ig_hal/e1000_ich8lan.c

5924

u32 i, led;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5956

u32 i, led;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5994

u32 bank = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5995

u32 status;

sys/dev/netif/ig_hal/e1000_ich8lan.c

637

u32 gfpreg, sector_base_addr, sector_end_addr;

sys/dev/netif/ig_hal/e1000_ich8lan.c

639

u32 nvm_size;

sys/dev/netif/ig_hal/e1000_ich8lan.c

80

static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_ich8lan.c

81

static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_ich8lan.c

85

u32 mc_addr_count);

sys/dev/netif/ig_hal/e1000_ich8lan.h

338

u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);

sys/dev/netif/ig_hal/e1000_mac.c

1067

u32 txcw;

sys/dev/netif/ig_hal/e1000_mac.c

1136

u32 i, status;

sys/dev/netif/ig_hal/e1000_mac.c

1184

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

1235

u32 tctl;

sys/dev/netif/ig_hal/e1000_mac.c

1258

u32 fcrtl = 0, fcrth = 0;

sys/dev/netif/ig_hal/e1000_mac.c

1297

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

133

u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)

sys/dev/netif/ig_hal/e1000_mac.c

1361

u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;

sys/dev/netif/ig_hal/e1000_mac.c

146

u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)

sys/dev/netif/ig_hal/e1000_mac.c

159

u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)

sys/dev/netif/ig_hal/e1000_mac.c

1668

u32 status;

sys/dev/netif/ig_hal/e1000_mac.c

170

u32 E1000_UNUSEDARG a)

sys/dev/netif/ig_hal/e1000_mac.c

1723

u32 swsm;

sys/dev/netif/ig_hal/e1000_mac.c

1774

u32 swsm;

sys/dev/netif/ig_hal/e1000_mac.c

1847

const u32 ledctl_mask = 0x000000FF;

sys/dev/netif/ig_hal/e1000_mac.c

1848

const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;

sys/dev/netif/ig_hal/e1000_mac.c

1849

const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;

sys/dev/netif/ig_hal/e1000_mac.c

188

u32 status = E1000_READ_REG(hw, E1000_STATUS);

sys/dev/netif/ig_hal/e1000_mac.c

1913

u32 ledctl;

sys/dev/netif/ig_hal/e1000_mac.c

1959

u32 ledctl_blink = 0;

sys/dev/netif/ig_hal/e1000_mac.c

1960

u32 i;

sys/dev/netif/ig_hal/e1000_mac.c

1977

u32 mode = (hw->mac.ledctl_mode2 >> i) &

sys/dev/netif/ig_hal/e1000_mac.c

1979

u32 led_default = hw->mac.ledctl_default >> i;

sys/dev/netif/ig_hal/e1000_mac.c

2006

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

2035

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

2063

void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)

sys/dev/netif/ig_hal/e1000_mac.c

2065

u32 gcr;

sys/dev/netif/ig_hal/e1000_mac.c

2093

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

2235

s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,

sys/dev/netif/ig_hal/e1000_mac.c

2236

u32 offset, u8 data)

sys/dev/netif/ig_hal/e1000_mac.c

2238

u32 i, regvalue = 0;

sys/dev/netif/ig_hal/e1000_mac.c

2243

regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);

sys/dev/netif/ig_hal/e1000_mac.c

288

u32 reg;

sys/dev/netif/ig_hal/e1000_mac.c

307

u32 status;

sys/dev/netif/ig_hal/e1000_mac.c

341

u32 offset;

sys/dev/netif/ig_hal/e1000_mac.c

360

void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)

sys/dev/netif/ig_hal/e1000_mac.c

379

u32 i;

sys/dev/netif/ig_hal/e1000_mac.c

409

u32 i;

sys/dev/netif/ig_hal/e1000_mac.c

484

int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_mac.c

486

u32 rar_low, rar_high;

sys/dev/netif/ig_hal/e1000_mac.c

493

rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |

sys/dev/netif/ig_hal/e1000_mac.c

494

((u32) addr[2] << 16) | ((u32) addr[3] << 24));

sys/dev/netif/ig_hal/e1000_mac.c

496

rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

sys/dev/netif/ig_hal/e1000_mac.c

522

u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)

sys/dev/netif/ig_hal/e1000_mac.c

524

u32 hash_value, hash_mask;

sys/dev/netif/ig_hal/e1000_mac.c

594

u8 *mc_addr_list, u32 mc_addr_count)

sys/dev/netif/ig_hal/e1000_mac.c

596

u32 hash_value, hash_bit, hash_reg;

sys/dev/netif/ig_hal/e1000_mac.c

605

for (i = 0; (u32) i < mc_addr_count; i++) {

sys/dev/netif/ig_hal/e1000_mac.c

783

u32 rxcw;

sys/dev/netif/ig_hal/e1000_mac.c

784

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

785

u32 status;

sys/dev/netif/ig_hal/e1000_mac.c

850

u32 rxcw;

sys/dev/netif/ig_hal/e1000_mac.c

851

u32 ctrl;

sys/dev/netif/ig_hal/e1000_mac.c

852

u32 status;

sys/dev/netif/ig_hal/e1000_mac.h

44

void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);

sys/dev/netif/ig_hal/e1000_mac.h

45

void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);

sys/dev/netif/ig_hal/e1000_mac.h

46

int e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);

sys/dev/netif/ig_hal/e1000_mac.h

47

s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a);

sys/dev/netif/ig_hal/e1000_mac.h

72

u8 *mc_addr_list, u32 mc_addr_count);

sys/dev/netif/ig_hal/e1000_mac.h

73

int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_mac.h

80

s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,

sys/dev/netif/ig_hal/e1000_mac.h

81

u32 offset, u8 data);

sys/dev/netif/ig_hal/e1000_mac.h

83

u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);

sys/dev/netif/ig_hal/e1000_mac.h

92

void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);

sys/dev/netif/ig_hal/e1000_mac.h

94

void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);

sys/dev/netif/ig_hal/e1000_manage.c

115

u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);

sys/dev/netif/ig_hal/e1000_manage.c

134

u32 *buffer = (u32 *)&hw->mng_cookie;

sys/dev/netif/ig_hal/e1000_manage.c

135

u32 offset;

sys/dev/netif/ig_hal/e1000_manage.c

206

*((u32 *) hdr + i));

sys/dev/netif/ig_hal/e1000_manage.c

230

u32 data = 0;

sys/dev/netif/ig_hal/e1000_manage.c

246

for (j = prev_bytes; j < sizeof(u32); j++) {

sys/dev/netif/ig_hal/e1000_manage.c

265

for (j = 0; j < sizeof(u32); j++) {

sys/dev/netif/ig_hal/e1000_manage.c

274

for (j = 0; j < sizeof(u32); j++) {

sys/dev/netif/ig_hal/e1000_manage.c

302

u32 hicr;

sys/dev/netif/ig_hal/e1000_manage.c

344

u32 manc;

sys/dev/netif/ig_hal/e1000_manage.c

345

u32 fwsm, factps;

sys/dev/netif/ig_hal/e1000_manage.c

396

s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)

sys/dev/netif/ig_hal/e1000_manage.c

398

u32 hicr, i;

sys/dev/netif/ig_hal/e1000_manage.c

433

*((u32 *)buffer + i));

sys/dev/netif/ig_hal/e1000_manage.c

453

*((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,

sys/dev/netif/ig_hal/e1000_manage.c

46

u8 e1000_calculate_checksum(u8 *buffer, u32 length)

sys/dev/netif/ig_hal/e1000_manage.c

469

s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)

sys/dev/netif/ig_hal/e1000_manage.c

471

u32 hicr, hibba, fwsm, icr, i;

sys/dev/netif/ig_hal/e1000_manage.c

48

u32 i;

sys/dev/netif/ig_hal/e1000_manage.c

555

*((u32 *)buffer + i));

sys/dev/netif/ig_hal/e1000_manage.c

74

u32 hicr;

sys/dev/netif/ig_hal/e1000_manage.h

48

u8 e1000_calculate_checksum(u8 *buffer, u32 length);

sys/dev/netif/ig_hal/e1000_manage.h

49

s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);

sys/dev/netif/ig_hal/e1000_manage.h

50

s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);

sys/dev/netif/ig_hal/e1000_mbx.c

246

s32 e1000_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ig_hal/e1000_mbx.c

275

s32 e1000_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ig_hal/e1000_mbx.c

322

static u32 e1000_read_v2p_mailbox(struct e1000_hw *hw)

sys/dev/netif/ig_hal/e1000_mbx.c

324

u32 v2p_mailbox = E1000_READ_REG(hw, E1000_V2PMAILBOX(0));

sys/dev/netif/ig_hal/e1000_mbx.c

340

static s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask)

sys/dev/netif/ig_hal/e1000_mbx.c

342

u32 v2p_mailbox = e1000_read_v2p_mailbox(hw);

sys/dev/netif/ig_hal/e1000_mbx.c

457

static s32 e1000_write_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ig_hal/e1000_mbx.c

498

static s32 e1000_read_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ig_hal/e1000_mbx.c

54

u32 E1000_UNUSEDARG *msg,

sys/dev/netif/ig_hal/e1000_mbx.c

559

static s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask)

sys/dev/netif/ig_hal/e1000_mbx.c

561

u32 mbvficr = E1000_READ_REG(hw, E1000_MBVFICR);

sys/dev/netif/ig_hal/e1000_mbx.c

623

u32 vflre = E1000_READ_REG(hw, E1000_VFLRE);

sys/dev/netif/ig_hal/e1000_mbx.c

647

u32 p2v_mailbox;

sys/dev/netif/ig_hal/e1000_mbx.c

679

static s32 e1000_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ig_hal/e1000_mbx.c

72

s32 e1000_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ig_hal/e1000_mbx.c

722

static s32 e1000_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ig_hal/e1000_mbx.c

98

s32 e1000_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ig_hal/e1000_mbx.h

95

s32 e1000_read_mbx(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_mbx.h

96

s32 e1000_write_mbx(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_mbx.h

97

s32 e1000_read_posted_mbx(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_mbx.h

98

s32 e1000_write_posted_mbx(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_nvm.c

1023

u32 eeprom_buf_size, struct e1000_pba *pba)

sys/dev/netif/ig_hal/e1000_nvm.c

1055

if (eeprom_buf_size > (u32)(pba->word[1] +

sys/dev/netif/ig_hal/e1000_nvm.c

1082

u32 eeprom_buf_size, u16 *pba_block_size)

sys/dev/netif/ig_hal/e1000_nvm.c

1139

u32 rar_high;

sys/dev/netif/ig_hal/e1000_nvm.c

1140

u32 rar_low;

sys/dev/netif/ig_hal/e1000_nvm.c

121

static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)

sys/dev/netif/ig_hal/e1000_nvm.c

1231

u32 ctrl_ext;

sys/dev/netif/ig_hal/e1000_nvm.c

136

static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)

sys/dev/netif/ig_hal/e1000_nvm.c

157

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_nvm.c

158

u32 mask;

sys/dev/netif/ig_hal/e1000_nvm.c

203

u32 eecd;

sys/dev/netif/ig_hal/e1000_nvm.c

204

u32 i;

sys/dev/netif/ig_hal/e1000_nvm.c

240

u32 attempts = 100000;

sys/dev/netif/ig_hal/e1000_nvm.c

241

u32 i, reg = 0;

sys/dev/netif/ig_hal/e1000_nvm.c

270

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_nvm.c

305

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_nvm.c

345

u32 eecd;

sys/dev/netif/ig_hal/e1000_nvm.c

371

u32 eecd;

sys/dev/netif/ig_hal/e1000_nvm.c

391

u32 eecd = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_nvm.c

450

u32 i = 0;

sys/dev/netif/ig_hal/e1000_nvm.c

511

u32 i = 0;

sys/dev/netif/ig_hal/e1000_nvm.c

565

u32 i, eerd = 0;

sys/dev/netif/ig_hal/e1000_nvm.c

695

u32 eecd;

sys/dev/netif/ig_hal/e1000_nvm.c

775

u32 pba_num_size)

sys/dev/netif/ig_hal/e1000_nvm.c

858

if (pba_num_size < (((u32)length * 2) - 1)) {

sys/dev/netif/ig_hal/e1000_nvm.c

889

s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)

sys/dev/netif/ig_hal/e1000_nvm.c

935

*pba_num_size = ((u32)length * 2) - 1;

sys/dev/netif/ig_hal/e1000_nvm.c

954

u32 eeprom_buf_size, u16 max_pba_block_size,

sys/dev/netif/ig_hal/e1000_nvm.c

997

if (eeprom_buf_size > (u32)(pba->word[1] +

sys/dev/netif/ig_hal/e1000_nvm.h

44

u32 etrack_id;

sys/dev/netif/ig_hal/e1000_nvm.h

70

u32 pba_num_size);

sys/dev/netif/ig_hal/e1000_nvm.h

71

s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);

sys/dev/netif/ig_hal/e1000_nvm.h

73

u32 eeprom_buf_size, u16 max_pba_block_size,

sys/dev/netif/ig_hal/e1000_nvm.h

76

u32 eeprom_buf_size, struct e1000_pba *pba);

sys/dev/netif/ig_hal/e1000_nvm.h

78

u32 eeprom_buf_size, u16 *pba_block_size);

sys/dev/netif/ig_hal/e1000_osdep.h

80

#define __le32 u32

sys/dev/netif/ig_hal/e1000_phy.c

1003

s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

122

u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)

sys/dev/netif/ig_hal/e1000_phy.c

157

u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)

sys/dev/netif/ig_hal/e1000_phy.c

2022

u32 ctrl;

sys/dev/netif/ig_hal/e1000_phy.c

207

u32 manc;

sys/dev/netif/ig_hal/e1000_phy.c

2354

s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,

sys/dev/netif/ig_hal/e1000_phy.c

2355

u32 usec_interval, bool *success)

sys/dev/netif/ig_hal/e1000_phy.c

241

phy->id = (u32)(phy_id << 16);

sys/dev/netif/ig_hal/e1000_phy.c

247

phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

sys/dev/netif/ig_hal/e1000_phy.c

248

phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

sys/dev/netif/ig_hal/e1000_phy.c

2860

u32 ctrl;

sys/dev/netif/ig_hal/e1000_phy.c

290

s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

293

u32 i, mdic = 0;

sys/dev/netif/ig_hal/e1000_phy.c

2995

enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)

sys/dev/netif/ig_hal/e1000_phy.c

3064

u32 phy_addr = 0;

sys/dev/netif/ig_hal/e1000_phy.c

3065

u32 i;

sys/dev/netif/ig_hal/e1000_phy.c

3099

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)

sys/dev/netif/ig_hal/e1000_phy.c

3101

u32 phy_addr = 2;

sys/dev/netif/ig_hal/e1000_phy.c

3118

s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

3121

u32 page = offset >> IGP_PAGE_SHIFT;

sys/dev/netif/ig_hal/e1000_phy.c

3139

u32 page_shift, page_select;

sys/dev/netif/ig_hal/e1000_phy.c

3178

s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

3181

u32 page = offset >> IGP_PAGE_SHIFT;

sys/dev/netif/ig_hal/e1000_phy.c

3199

u32 page_shift, page_select;

sys/dev/netif/ig_hal/e1000_phy.c

3237

s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

3282

s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

3435

static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_phy.c

3539

static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,

sys/dev/netif/ig_hal/e1000_phy.c

3545

u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);

sys/dev/netif/ig_hal/e1000_phy.c

355

s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

358

u32 i, mdic = 0;

sys/dev/netif/ig_hal/e1000_phy.c

3605

s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

3619

s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

3633

s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

3649

static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,

sys/dev/netif/ig_hal/e1000_phy.c

3655

u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);

sys/dev/netif/ig_hal/e1000_phy.c

371

mdic = (((u32)data) |

sys/dev/netif/ig_hal/e1000_phy.c

3731

s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

3745

s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

3759

s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

3768

static u32 e1000_get_phy_addr_for_hv_page(u32 page)

sys/dev/netif/ig_hal/e1000_phy.c

3770

u32 phy_addr = 2;

sys/dev/netif/ig_hal/e1000_phy.c

3790

static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_phy.c

3794

u32 addr_reg;

sys/dev/netif/ig_hal/e1000_phy.c

3795

u32 data_reg;

sys/dev/netif/ig_hal/e1000_phy.c

38

static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_phy.c

40

static u32 e1000_get_phy_addr_for_hv_page(u32 page);

sys/dev/netif/ig_hal/e1000_phy.c

4053

s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

4085

s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

41

static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,

sys/dev/netif/ig_hal/e1000_phy.c

4116

s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)

sys/dev/netif/ig_hal/e1000_phy.c

4118

u32 mphy_ctrl = 0;

sys/dev/netif/ig_hal/e1000_phy.c

4177

s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,

sys/dev/netif/ig_hal/e1000_phy.c

4180

u32 mphy_ctrl = 0;

sys/dev/netif/ig_hal/e1000_phy.c

421

s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

424

u32 i, i2ccmd = 0;

sys/dev/netif/ig_hal/e1000_phy.c

4242

u32 mphy_ctrl = 0;

sys/dev/netif/ig_hal/e1000_phy.c

468

s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

471

u32 i, i2ccmd = 0;

sys/dev/netif/ig_hal/e1000_phy.c

531

u32 i = 0;

sys/dev/netif/ig_hal/e1000_phy.c

532

u32 i2ccmd = 0;

sys/dev/netif/ig_hal/e1000_phy.c

533

u32 data_local = 0;

sys/dev/netif/ig_hal/e1000_phy.c

586

u32 i = 0;

sys/dev/netif/ig_hal/e1000_phy.c

587

u32 i2ccmd = 0;

sys/dev/netif/ig_hal/e1000_phy.c

588

u32 data_local = 0;

sys/dev/netif/ig_hal/e1000_phy.c

654

s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

684

s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

736

static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,

sys/dev/netif/ig_hal/e1000_phy.c

776

s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

790

s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

805

static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,

sys/dev/netif/ig_hal/e1000_phy.c

844

s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

858

s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.c

874

static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,

sys/dev/netif/ig_hal/e1000_phy.c

877

u32 kmrnctrlsta;

sys/dev/netif/ig_hal/e1000_phy.c

918

s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

933

s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)

sys/dev/netif/ig_hal/e1000_phy.c

949

static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,

sys/dev/netif/ig_hal/e1000_phy.c

952

u32 kmrnctrlsta;

sys/dev/netif/ig_hal/e1000_phy.c

989

s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)

sys/dev/netif/ig_hal/e1000_phy.h

100

s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

101

s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

102

s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

103

s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

104

s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

105

s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

106

s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

108

s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

109

s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

117

s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

118

s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

119

s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data);

sys/dev/netif/ig_hal/e1000_phy.h

120

s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,

sys/dev/netif/ig_hal/e1000_phy.h

39

s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

42

s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

73

s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

74

s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

76

s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

77

s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

78

s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

81

s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

82

s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

83

s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

84

s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

85

s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

86

s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,

sys/dev/netif/ig_hal/e1000_phy.h

87

u32 usec_interval, bool *success);

sys/dev/netif/ig_hal/e1000_phy.h

89

enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);

sys/dev/netif/ig_hal/e1000_phy.h

91

s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

92

s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

95

s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_phy.h

96

s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);

sys/dev/netif/ig_hal/e1000_phy.h

99

s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);

sys/dev/netif/ig_hal/e1000_vf.c

261

u32 timeout = E1000_VF_INIT_TIMEOUT;

sys/dev/netif/ig_hal/e1000_vf.c

263

u32 ctrl, msgbuf[3];

sys/dev/netif/ig_hal/e1000_vf.c

324

u32 E1000_UNUSEDARG index)

sys/dev/netif/ig_hal/e1000_vf.c

327

u32 msgbuf[3];

sys/dev/netif/ig_hal/e1000_vf.c

357

static u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)

sys/dev/netif/ig_hal/e1000_vf.c

359

u32 hash_value, hash_mask;

sys/dev/netif/ig_hal/e1000_vf.c

381

u32 *msg, u16 size)

sys/dev/netif/ig_hal/e1000_vf.c

384

u32 retmsg[E1000_VFMAILBOX_SIZE];

sys/dev/netif/ig_hal/e1000_vf.c

401

u8 *mc_addr_list, u32 mc_addr_count)

sys/dev/netif/ig_hal/e1000_vf.c

403

u32 msgbuf[E1000_VFMAILBOX_SIZE];

sys/dev/netif/ig_hal/e1000_vf.c

405

u32 hash_value;

sys/dev/netif/ig_hal/e1000_vf.c

406

u32 i;

sys/dev/netif/ig_hal/e1000_vf.c

447

u32 msgbuf[2];

sys/dev/netif/ig_hal/e1000_vf.c

464

u32 msgbuf[2];

sys/dev/netif/ig_hal/e1000_vf.c

481

u32 msgbuf = E1000_VF_SET_PROMISC;

sys/dev/netif/ig_hal/e1000_vf.c

51

static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);

sys/dev/netif/ig_hal/e1000_vf.c

52

static int e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);

sys/dev/netif/ig_hal/e1000_vf.c

536

u32 in_msg = 0;

sys/dev/netif/ig_hal/e1000_vf.h

101

u32 rss; /* RSS Hash */

sys/dev/netif/ig_hal/e1000_vf.h

109

u32 status_error; /* ext status/error */

sys/dev/netif/ig_hal/e1000_vf.h

123

u32 cmd_type_len;

sys/dev/netif/ig_hal/e1000_vf.h

124

u32 olinfo_status;

sys/dev/netif/ig_hal/e1000_vf.h

128

u32 nxtseq_seed;

sys/dev/netif/ig_hal/e1000_vf.h

129

u32 status;

sys/dev/netif/ig_hal/e1000_vf.h

146

u32 vlan_macip_lens;

sys/dev/netif/ig_hal/e1000_vf.h

147

u32 seqnum_seed;

sys/dev/netif/ig_hal/e1000_vf.h

148

u32 type_tucmd_mlhl;

sys/dev/netif/ig_hal/e1000_vf.h

149

u32 mss_l4len_idx;

sys/dev/netif/ig_hal/e1000_vf.h

176

u32 last_gprc;

sys/dev/netif/ig_hal/e1000_vf.h

177

u32 last_gptc;

sys/dev/netif/ig_hal/e1000_vf.h

178

u32 last_gorc;

sys/dev/netif/ig_hal/e1000_vf.h

179

u32 last_gotc;

sys/dev/netif/ig_hal/e1000_vf.h

180

u32 last_mprc;

sys/dev/netif/ig_hal/e1000_vf.h

181

u32 last_gotlbc;

sys/dev/netif/ig_hal/e1000_vf.h

182

u32 last_gptlbc;

sys/dev/netif/ig_hal/e1000_vf.h

183

u32 last_gorlbc;

sys/dev/netif/ig_hal/e1000_vf.h

184

u32 last_gprlbc;

sys/dev/netif/ig_hal/e1000_vf.h

206

void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);

sys/dev/netif/ig_hal/e1000_vf.h

210

void (*write_vfta)(struct e1000_hw *, u32, u32);

sys/dev/netif/ig_hal/e1000_vf.h

211

int (*rar_set)(struct e1000_hw *, u8*, u32);

sys/dev/netif/ig_hal/e1000_vf.h

230

s32 (*read)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_vf.h

231

s32 (*write)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_vf.h

232

s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_vf.h

233

s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);

sys/dev/netif/ig_hal/e1000_vf.h

240

u32 msgs_tx;

sys/dev/netif/ig_hal/e1000_vf.h

241

u32 msgs_rx;

sys/dev/netif/ig_hal/e1000_vf.h

243

u32 acks;

sys/dev/netif/ig_hal/e1000_vf.h

244

u32 reqs;

sys/dev/netif/ig_hal/e1000_vf.h

245

u32 rsts;

sys/dev/netif/ig_hal/e1000_vf.h

251

u32 timeout;

sys/dev/netif/ig_hal/e1000_vf.h

252

u32 usec_delay;

sys/dev/netif/ig_hal/e1000_vf.h

257

u32 vf_number;

sys/dev/netif/ig_hal/e1000_vf.h

258

u32 v2p_mailbox;

sys/dev/netif/ig_hal/e1000_vf.h

292

s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_vf.h

92

u32 data;

sys/dev/netif/ix/ixgbe_82598.c

1004

s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,

sys/dev/netif/ix/ixgbe_82598.c

1007

u32 regindex;

sys/dev/netif/ix/ixgbe_82598.c

1008

u32 bitindex;

sys/dev/netif/ix/ixgbe_82598.c

1009

u32 bits;

sys/dev/netif/ix/ixgbe_82598.c

1010

u32 vftabyte;

sys/dev/netif/ix/ixgbe_82598.c

1055

u32 offset;

sys/dev/netif/ix/ixgbe_82598.c

1056

u32 vlanbyte;

sys/dev/netif/ix/ixgbe_82598.c

1079

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_82598.c

1081

u32 atlas_ctl;

sys/dev/netif/ix/ixgbe_82598.c

1103

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_82598.c

1105

u32 atlas_ctl;

sys/dev/netif/ix/ixgbe_82598.c

1134

u32 i;

sys/dev/netif/ix/ixgbe_82598.c

1230

u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/netif/ix/ixgbe_82598.c

1231

u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;

sys/dev/netif/ix/ixgbe_82598.c

1232

u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;

sys/dev/netif/ix/ixgbe_82598.c

1364

u32 regval;

sys/dev/netif/ix/ixgbe_82598.c

1365

u32 i;

sys/dev/netif/ix/ixgbe_82598.c

1395

u32 headroom, int strategy)

sys/dev/netif/ix/ixgbe_82598.c

1397

u32 rxpktsize = IXGBE_RXPBSIZE_64KB;

sys/dev/netif/ix/ixgbe_82598.c

1434

s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)

sys/dev/netif/ix/ixgbe_82598.c

256

u32 regval;

sys/dev/netif/ix/ixgbe_82598.c

257

u32 i;

sys/dev/netif/ix/ixgbe_82598.c

301

u32 autoc = 0;

sys/dev/netif/ix/ixgbe_82598.c

411

u32 fctrl_reg;

sys/dev/netif/ix/ixgbe_82598.c

412

u32 rmcs_reg;

sys/dev/netif/ix/ixgbe_82598.c

413

u32 reg;

sys/dev/netif/ix/ixgbe_82598.c

414

u32 fcrtl, fcrth;

sys/dev/netif/ix/ixgbe_82598.c

415

u32 link_speed = 0;

sys/dev/netif/ix/ixgbe_82598.c

560

u32 autoc_reg;

sys/dev/netif/ix/ixgbe_82598.c

561

u32 links_reg;

sys/dev/netif/ix/ixgbe_82598.c

562

u32 i;

sys/dev/netif/ix/ixgbe_82598.c

607

u32 timeout;

sys/dev/netif/ix/ixgbe_82598.c

64

static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

sys/dev/netif/ix/ixgbe_82598.c

646

u32 links_reg;

sys/dev/netif/ix/ixgbe_82598.c

647

u32 i;

sys/dev/netif/ix/ixgbe_82598.c

67

u32 headroom, int strategy);

sys/dev/netif/ix/ixgbe_82598.c

738

u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/netif/ix/ixgbe_82598.c

739

u32 autoc = curr_autoc;

sys/dev/netif/ix/ixgbe_82598.c

740

u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;

sys/dev/netif/ix/ixgbe_82598.c

814

u32 ctrl;

sys/dev/netif/ix/ixgbe_82598.c

815

u32 gheccr;

sys/dev/netif/ix/ixgbe_82598.c

816

u32 i;

sys/dev/netif/ix/ixgbe_82598.c

817

u32 autoc;

sys/dev/netif/ix/ixgbe_82598.c

82

u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);

sys/dev/netif/ix/ixgbe_82598.c

946

s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

sys/dev/netif/ix/ixgbe_82598.c

948

u32 rar_high;

sys/dev/netif/ix/ixgbe_82598.c

949

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_82598.c

972

static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

sys/dev/netif/ix/ixgbe_82598.c

974

u32 rar_high;

sys/dev/netif/ix/ixgbe_82598.c

975

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_82598.h

38

u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_82598.h

42

s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

sys/dev/netif/ix/ixgbe_82598.h

43

s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,

sys/dev/netif/ix/ixgbe_82598.h

45

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_82598.h

46

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_82598.h

53

s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval);

sys/dev/netif/ix/ixgbe_82599.c

1036

u32 ctrl = 0;

sys/dev/netif/ix/ixgbe_82599.c

1037

u32 i, autoc, autoc2;

sys/dev/netif/ix/ixgbe_82599.c

1038

u32 curr_lms;

sys/dev/netif/ix/ixgbe_82599.c

120

u32 esdp;

sys/dev/netif/ix/ixgbe_82599.c

1211

static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)

sys/dev/netif/ix/ixgbe_82599.c

1233

u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);

sys/dev/netif/ix/ixgbe_82599.c

1234

u32 fdircmd;

sys/dev/netif/ix/ixgbe_82599.c

1303

static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)

sys/dev/netif/ix/ixgbe_82599.c

1345

s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)

sys/dev/netif/ix/ixgbe_82599.c

1372

s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,

sys/dev/netif/ix/ixgbe_82599.c

1411

u32 fdirctrl;

sys/dev/netif/ix/ixgbe_82599.c

1447

u32 n = (_n); \

sys/dev/netif/ix/ixgbe_82599.c

1473

u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,

sys/dev/netif/ix/ixgbe_82599.c

1476

u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;

sys/dev/netif/ix/ixgbe_82599.c

1477

u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;

sys/dev/netif/ix/ixgbe_82599.c

1547

u32 fdircmd;

sys/dev/netif/ix/ixgbe_82599.c

1575

fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;

sys/dev/netif/ix/ixgbe_82599.c

1576

fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;

sys/dev/netif/ix/ixgbe_82599.c

1588

DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);

sys/dev/netif/ix/ixgbe_82599.c

1595

u32 n = (_n); \

sys/dev/netif/ix/ixgbe_82599.c

1617

u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;

sys/dev/netif/ix/ixgbe_82599.c

1618

u32 bucket_hash = 0;

sys/dev/netif/ix/ixgbe_82599.c

1619

u32 hi_dword = 0;

sys/dev/netif/ix/ixgbe_82599.c

1620

u32 i = 0;

sys/dev/netif/ix/ixgbe_82599.c

1670

static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)

sys/dev/netif/ix/ixgbe_82599.c

1672

u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);

sys/dev/netif/ix/ixgbe_82599.c

1689

(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \

sys/dev/netif/ix/ixgbe_82599.c

1690

(((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))

sys/dev/netif/ix/ixgbe_82599.c

1702

u32 fdirm = IXGBE_FDIRM_DIPv6;

sys/dev/netif/ix/ixgbe_82599.c

1703

u32 fdirtcpm;

sys/dev/netif/ix/ixgbe_82599.c

1704

u32 fdirip6m;

sys/dev/netif/ix/ixgbe_82599.c

1783

fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);

sys/dev/netif/ix/ixgbe_82599.c

1878

u32 fdirport, fdirvlan, fdirhash, fdircmd;

sys/dev/netif/ix/ixgbe_82599.c

1879

u32 addr_low, addr_high;

sys/dev/netif/ix/ixgbe_82599.c

1880

u32 cloud_type = 0;

sys/dev/netif/ix/ixgbe_82599.c

1920

addr_low = ((u32)input->formatted.inner_mac[0] |

sys/dev/netif/ix/ixgbe_82599.c

1921

((u32)input->formatted.inner_mac[1] << 8) |

sys/dev/netif/ix/ixgbe_82599.c

1922

((u32)input->formatted.inner_mac[2] << 16) |

sys/dev/netif/ix/ixgbe_82599.c

1923

((u32)input->formatted.inner_mac[3] << 24));

sys/dev/netif/ix/ixgbe_82599.c

1924

addr_high = ((u32)input->formatted.inner_mac[4] |

sys/dev/netif/ix/ixgbe_82599.c

1925

((u32)input->formatted.inner_mac[5] << 8));

sys/dev/netif/ix/ixgbe_82599.c

1951

fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;

sys/dev/netif/ix/ixgbe_82599.c

1952

fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;

sys/dev/netif/ix/ixgbe_82599.c

1968

u32 fdirhash;

sys/dev/netif/ix/ixgbe_82599.c

1969

u32 fdircmd;

sys/dev/netif/ix/ixgbe_82599.c

2075

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_82599.c

2077

u32 core_ctl;

sys/dev/netif/ix/ixgbe_82599.c

2099

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_82599.c

2101

u32 core_ctl;

sys/dev/netif/ix/ixgbe_82599.c

2190

u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/netif/ix/ixgbe_82599.c

2191

u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

sys/dev/netif/ix/ixgbe_82599.c

2192

u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;

sys/dev/netif/ix/ixgbe_82599.c

2193

u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;

sys/dev/netif/ix/ixgbe_82599.c

2194

u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;

sys/dev/netif/ix/ixgbe_82599.c

2275

s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)

sys/dev/netif/ix/ixgbe_82599.c

2484

u32 anlp1_reg = 0;

sys/dev/netif/ix/ixgbe_82599.c

2485

u32 i, autoc_reg, autoc2_reg;

sys/dev/netif/ix/ixgbe_82599.c

250

s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)

sys/dev/netif/ix/ixgbe_82599.c

2537

u32 esdp;

sys/dev/netif/ix/ixgbe_82599.c

2595

u32 esdp;

sys/dev/netif/ix/ixgbe_82599.c

279

s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)

sys/dev/netif/ix/ixgbe_82599.c

420

u32 autoc = 0;

sys/dev/netif/ix/ixgbe_82599.c

589

u32 autoc2_reg;

sys/dev/netif/ix/ixgbe_82599.c

614

u32 autoc_reg;

sys/dev/netif/ix/ixgbe_82599.c

615

u32 links_reg;

sys/dev/netif/ix/ixgbe_82599.c

616

u32 i;

sys/dev/netif/ix/ixgbe_82599.c

681

u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/netif/ix/ixgbe_82599.c

704

u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/netif/ix/ixgbe_82599.c

750

u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/netif/ix/ixgbe_82599.c

785

u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/netif/ix/ixgbe_82599.c

895

u32 pma_pmd_1g, link_mode;

sys/dev/netif/ix/ixgbe_82599.c

896

u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */

sys/dev/netif/ix/ixgbe_82599.c

897

u32 orig_autoc = 0; /* holds the cached value of AUTOC register */

sys/dev/netif/ix/ixgbe_82599.c

898

u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */

sys/dev/netif/ix/ixgbe_82599.c

899

u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

sys/dev/netif/ix/ixgbe_82599.c

900

u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;

sys/dev/netif/ix/ixgbe_82599.c

901

u32 links_reg;

sys/dev/netif/ix/ixgbe_82599.c

902

u32 i;

sys/dev/netif/ix/ixgbe_82599.h

56

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_82599.h

57

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_82599.h

62

s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);

sys/dev/netif/ix/ixgbe_82599.h

63

s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);

sys/dev/netif/ix/ixgbe_82599.h

64

s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);

sys/dev/netif/ix/ixgbe_api.c

1002

u32 addr_count, ixgbe_mc_addr_itr func)

sys/dev/netif/ix/ixgbe_api.c

1023

u32 mc_addr_count, ixgbe_mc_addr_itr func,

sys/dev/netif/ix/ixgbe_api.c

1077

s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,

sys/dev/netif/ix/ixgbe_api.c

1097

s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,

sys/dev/netif/ix/ixgbe_api.c

1098

u32 *vfta_delta, u32 vfta, bool vlvf_bypass)

sys/dev/netif/ix/ixgbe_api.c

1238

s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_api.c

1239

u32 device_type, u32 *phy_data)

sys/dev/netif/ix/ixgbe_api.c

1254

s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_api.c

1255

u32 device_type, u32 phy_data)

sys/dev/netif/ix/ixgbe_api.c

1289

void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)

sys/dev/netif/ix/ixgbe_api.c

1302

void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)

sys/dev/netif/ix/ixgbe_api.c

1358

s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status)

sys/dev/netif/ix/ixgbe_api.c

1377

bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg)

sys/dev/netif/ix/ixgbe_api.c

1396

s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action)

sys/dev/netif/ix/ixgbe_api.c

1409

s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value)

sys/dev/netif/ix/ixgbe_api.c

1423

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_api.c

1437

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_api.c

1634

s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)

sys/dev/netif/ix/ixgbe_api.c

1672

s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_api.c

1686

void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_api.c

40

static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/netif/ix/ixgbe_api.c

410

u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_api.c

421

u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_api.c

44

static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/netif/ix/ixgbe_api.c

449

s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)

sys/dev/netif/ix/ixgbe_api.c

461

s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)

sys/dev/netif/ix/ixgbe_api.c

48

static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/netif/ix/ixgbe_api.c

52

static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/netif/ix/ixgbe_api.c

528

s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_api.c

547

s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_api.c

56

static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/netif/ix/ixgbe_api.c

737

s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_api.c

750

s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_api.c

763

s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_api.c

776

s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_api.c

894

s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)

sys/dev/netif/ix/ixgbe_api.c

911

s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_api.c

912

u32 enable_addr)

sys/dev/netif/ix/ixgbe_api.c

925

s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_api.c

937

s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

sys/dev/netif/ix/ixgbe_api.c

949

s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)

sys/dev/netif/ix/ixgbe_api.c

961

s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

sys/dev/netif/ix/ixgbe_api.c

985

u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_api.h

110

s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

111

s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_api.h

112

u32 enable_addr);

sys/dev/netif/ix/ixgbe_api.h

113

s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_api.h

114

s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

115

s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

116

s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

118

u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_api.h

120

u32 addr_count, ixgbe_mc_addr_itr func);

sys/dev/netif/ix/ixgbe_api.h

122

u32 mc_addr_count, ixgbe_mc_addr_itr func,

sys/dev/netif/ix/ixgbe_api.h

124

void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

128

s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,

sys/dev/netif/ix/ixgbe_api.h

129

u32 vind, bool vlan_on, bool vlvf_bypass);

sys/dev/netif/ix/ixgbe_api.h

130

s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,

sys/dev/netif/ix/ixgbe_api.h

131

bool vlan_on, u32 *vfta_delta, u32 vfta,

sys/dev/netif/ix/ixgbe_api.h

140

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_api.h

141

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_api.h

145

s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);

sys/dev/netif/ix/ixgbe_api.h

150

s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);

sys/dev/netif/ix/ixgbe_api.h

151

s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,

sys/dev/netif/ix/ixgbe_api.h

173

u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,

sys/dev/netif/ix/ixgbe_api.h

193

s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_api.h

194

void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_api.h

199

s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status);

sys/dev/netif/ix/ixgbe_api.h

200

s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);

sys/dev/netif/ix/ixgbe_api.h

201

s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value);

sys/dev/netif/ix/ixgbe_api.h

203

bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg);

sys/dev/netif/ix/ixgbe_api.h

213

s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_api.h

214

u32 device_type, u32 *phy_data);

sys/dev/netif/ix/ixgbe_api.h

215

s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_api.h

216

u32 device_type, u32 phy_data);

sys/dev/netif/ix/ixgbe_api.h

219

void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap);

sys/dev/netif/ix/ixgbe_api.h

220

void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf);

sys/dev/netif/ix/ixgbe_api.h

227

s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,

sys/dev/netif/ix/ixgbe_api.h

228

u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);

sys/dev/netif/ix/ixgbe_api.h

61

u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_api.h

62

u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);

sys/dev/netif/ix/ixgbe_api.h

64

s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);

sys/dev/netif/ix/ixgbe_api.h

65

s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);

sys/dev/netif/ix/ixgbe_api.h

69

s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_api.h

71

s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_api.h

94

s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_api.h

95

s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_api.h

96

s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_api.h

97

s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_common.c

1079

u32 reg;

sys/dev/netif/ix/ixgbe_common.c

1112

u32 reg_val;

sys/dev/netif/ix/ixgbe_common.c

1165

u32 led_reg, led_mode;

sys/dev/netif/ix/ixgbe_common.c

1201

s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_common.c

1203

u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/netif/ix/ixgbe_common.c

1224

s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_common.c

1226

u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/netif/ix/ixgbe_common.c

1252

u32 eec;

sys/dev/netif/ix/ixgbe_common.c

1609

u32 eerd;

sys/dev/netif/ix/ixgbe_common.c

1611

u32 i;

sys/dev/netif/ix/ixgbe_common.c

1717

u32 eewr;

sys/dev/netif/ix/ixgbe_common.c

1782

s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)

sys/dev/netif/ix/ixgbe_common.c

1784

u32 i;

sys/dev/netif/ix/ixgbe_common.c

1785

u32 reg;

sys/dev/netif/ix/ixgbe_common.c

1820

u32 eec;

sys/dev/netif/ix/ixgbe_common.c

1821

u32 i;

sys/dev/netif/ix/ixgbe_common.c

1874

u32 timeout = 2000;

sys/dev/netif/ix/ixgbe_common.c

1875

u32 i;

sys/dev/netif/ix/ixgbe_common.c

1876

u32 swsm;

sys/dev/netif/ix/ixgbe_common.c

1964

u32 swsm;

sys/dev/netif/ix/ixgbe_common.c

2023

u32 eec;

sys/dev/netif/ix/ixgbe_common.c

2049

u32 eec;

sys/dev/netif/ix/ixgbe_common.c

2050

u32 mask;

sys/dev/netif/ix/ixgbe_common.c

2051

u32 i;

sys/dev/netif/ix/ixgbe_common.c

2104

u32 eec;

sys/dev/netif/ix/ixgbe_common.c

2105

u32 i;

sys/dev/netif/ix/ixgbe_common.c

2142

static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)

sys/dev/netif/ix/ixgbe_common.c

2161

static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)

sys/dev/netif/ix/ixgbe_common.c

2181

u32 eec;

sys/dev/netif/ix/ixgbe_common.c

237

u32 reg = 0, reg_bp = 0;

sys/dev/netif/ix/ixgbe_common.c

2384

s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_common.c

2385

u32 enable_addr)

sys/dev/netif/ix/ixgbe_common.c

2387

u32 rar_low, rar_high;

sys/dev/netif/ix/ixgbe_common.c

2388

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_common.c

2406

rar_low = ((u32)addr[0] |

sys/dev/netif/ix/ixgbe_common.c

2407

((u32)addr[1] << 8) |

sys/dev/netif/ix/ixgbe_common.c

2408

((u32)addr[2] << 16) |

sys/dev/netif/ix/ixgbe_common.c

2409

((u32)addr[3] << 24));

sys/dev/netif/ix/ixgbe_common.c

2417

rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));

sys/dev/netif/ix/ixgbe_common.c

2435

s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_common.c

2437

u32 rar_high;

sys/dev/netif/ix/ixgbe_common.c

2438

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_common.c

2476

u32 i;

sys/dev/netif/ix/ixgbe_common.c

2477

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_common.c

2543

void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

2545

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_common.c

2546

u32 rar;

sys/dev/netif/ix/ixgbe_common.c

2584

u32 addr_count, ixgbe_mc_addr_itr next)

sys/dev/netif/ix/ixgbe_common.c

2587

u32 i;

sys/dev/netif/ix/ixgbe_common.c

2588

u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;

sys/dev/netif/ix/ixgbe_common.c

2589

u32 uc_addr_in_use;

sys/dev/netif/ix/ixgbe_common.c

2590

u32 fctrl;

sys/dev/netif/ix/ixgbe_common.c

2591

u32 vmdq;

sys/dev/netif/ix/ixgbe_common.c

2653

u32 vector = 0;

sys/dev/netif/ix/ixgbe_common.c

2690

u32 vector;

sys/dev/netif/ix/ixgbe_common.c

2691

u32 vector_bit;

sys/dev/netif/ix/ixgbe_common.c

2692

u32 vector_reg;

sys/dev/netif/ix/ixgbe_common.c

2727

u32 mc_addr_count, ixgbe_mc_addr_itr next,

sys/dev/netif/ix/ixgbe_common.c

2730

u32 i;

sys/dev/netif/ix/ixgbe_common.c

2731

u32 vmdq;

sys/dev/netif/ix/ixgbe_common.c

2813

u32 mflcn_reg, fccfg_reg;

sys/dev/netif/ix/ixgbe_common.c

2814

u32 reg;

sys/dev/netif/ix/ixgbe_common.c

2815

u32 fcrtl, fcrth;

sys/dev/netif/ix/ixgbe_common.c

2950

s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,

sys/dev/netif/ix/ixgbe_common.c

2951

u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)

sys/dev/netif/ix/ixgbe_common.c

2999

u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;

sys/dev/netif/ix/ixgbe_common.c

3036

u32 links2, anlp1_reg, autoc_reg, links;

sys/dev/netif/ix/ixgbe_common.c

3090

return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,

sys/dev/netif/ix/ixgbe_common.c

3091

(u32)lp_technology_ability_reg,

sys/dev/netif/ix/ixgbe_common.c

3172

static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_common.c

3175

u32 pollcnt;

sys/dev/netif/ix/ixgbe_common.c

3221

u32 i, poll;

sys/dev/netif/ix/ixgbe_common.c

3285

s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_common.c

3287

u32 gssr = 0;

sys/dev/netif/ix/ixgbe_common.c

3288

u32 swmask = mask;

sys/dev/netif/ix/ixgbe_common.c

3289

u32 fwmask = mask << 5;

sys/dev/netif/ix/ixgbe_common.c

3290

u32 timeout = 200;

sys/dev/netif/ix/ixgbe_common.c

3291

u32 i;

sys/dev/netif/ix/ixgbe_common.c

3332

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_common.c

3334

u32 gssr;

sys/dev/netif/ix/ixgbe_common.c

3335

u32 swmask = mask;

sys/dev/netif/ix/ixgbe_common.c

3393

s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)

sys/dev/netif/ix/ixgbe_common.c

3409

s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)

sys/dev/netif/ix/ixgbe_common.c

3425

u32 secrxreg;

sys/dev/netif/ix/ixgbe_common.c

3444

s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)

sys/dev/netif/ix/ixgbe_common.c

3461

s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_common.c

3465

u32 autoc_reg = 0;

sys/dev/netif/ix/ixgbe_common.c

3466

u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/netif/ix/ixgbe_common.c

3511

s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_common.c

3513

u32 autoc_reg = 0;

sys/dev/netif/ix/ixgbe_common.c

3514

u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/netif/ix/ixgbe_common.c

3722

s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

3724

static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;

sys/dev/netif/ix/ixgbe_common.c

3725

u32 first_empty_rar = NO_EMPTY_RAR_FOUND;

sys/dev/netif/ix/ixgbe_common.c

3726

u32 rar;

sys/dev/netif/ix/ixgbe_common.c

3727

u32 rar_low, rar_high;

sys/dev/netif/ix/ixgbe_common.c

3728

u32 addr_low, addr_high;

sys/dev/netif/ix/ixgbe_common.c

3788

s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

3790

u32 mpsar_lo, mpsar_hi;

sys/dev/netif/ix/ixgbe_common.c

3791

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_common.c

3842

s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

3844

u32 mpsar;

sys/dev/netif/ix/ixgbe_common.c

3845

u32 rar_entries = hw->mac.num_rar_entries;

sys/dev/netif/ix/ixgbe_common.c

3878

s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

3880

u32 rar = hw->mac.san_mac_rar_index;

sys/dev/netif/ix/ixgbe_common.c

3923

s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)

sys/dev/netif/ix/ixgbe_common.c

3926

u32 bits;

sys/dev/netif/ix/ixgbe_common.c

396

u32 ctrl_ext;

sys/dev/netif/ix/ixgbe_common.c

3973

s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,

sys/dev/netif/ix/ixgbe_common.c

3976

u32 regidx, vfta_delta, vfta;

sys/dev/netif/ix/ixgbe_common.c

4040

s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,

sys/dev/netif/ix/ixgbe_common.c

4041

bool vlan_on, u32 *vfta_delta, u32 vfta,

sys/dev/netif/ix/ixgbe_common.c

4044

u32 bits;

sys/dev/netif/ix/ixgbe_common.c

4124

u32 offset;

sys/dev/netif/ix/ixgbe_common.c

4178

u32 links_reg, links_orig;

sys/dev/netif/ix/ixgbe_common.c

4179

u32 i;

sys/dev/netif/ix/ixgbe_common.c

4187

u32 sfp_cage_full;

sys/dev/netif/ix/ixgbe_common.c

4389

u32 pfvfspoof;

sys/dev/netif/ix/ixgbe_common.c

4413

u32 pfvfspoof;

sys/dev/netif/ix/ixgbe_common.c

4450

u32 regval;

sys/dev/netif/ix/ixgbe_common.c

4451

u32 i;

sys/dev/netif/ix/ixgbe_common.c

4478

u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)

sys/dev/netif/ix/ixgbe_common.c

4480

u32 i;

sys/dev/netif/ix/ixgbe_common.c

4508

s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,

sys/dev/netif/ix/ixgbe_common.c

4509

u32 timeout)

sys/dev/netif/ix/ixgbe_common.c

4511

u32 hicr, i, fwsts;

sys/dev/netif/ix/ixgbe_common.c

4533

if (length % sizeof(u32)) {

sys/dev/netif/ix/ixgbe_common.c

4586

s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,

sys/dev/netif/ix/ixgbe_common.c

4587

u32 length, u32 timeout, bool return_data)

sys/dev/netif/ix/ixgbe_common.c

4589

u32 hdr_size = sizeof(struct ixgbe_hic_hdr);

sys/dev/netif/ix/ixgbe_common.c

459

u32 i;

sys/dev/netif/ix/ixgbe_common.c

4593

u32 bi;

sys/dev/netif/ix/ixgbe_common.c

4594

u32 dword_len;

sys/dev/netif/ix/ixgbe_common.c

460

u32 regval;

sys/dev/netif/ix/ixgbe_common.c

4706

ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,

sys/dev/netif/ix/ixgbe_common.c

4732

void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,

sys/dev/netif/ix/ixgbe_common.c

4735

u32 pbsize = hw->mac.rx_pb_size;

sys/dev/netif/ix/ixgbe_common.c

4737

u32 rxpktsize, txpktsize, txpbthresh;

sys/dev/netif/ix/ixgbe_common.c

4794

u32 gcr_ext, hlreg0, i, poll;

sys/dev/netif/ix/ixgbe_common.c

4855

s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)

sys/dev/netif/ix/ixgbe_common.c

4858

u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;

sys/dev/netif/ix/ixgbe_common.c

4859

u32 esdp;

sys/dev/netif/ix/ixgbe_common.c

49

static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);

sys/dev/netif/ix/ixgbe_common.c

4969

bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)

sys/dev/netif/ix/ixgbe_common.c

4971

u32 mask;

sys/dev/netif/ix/ixgbe_common.c

50

static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);

sys/dev/netif/ix/ixgbe_common.c

5025

s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,

sys/dev/netif/ix/ixgbe_common.c

5026

u32 action)

sys/dev/netif/ix/ixgbe_common.c

5028

u32 by_ctl = 0;

sys/dev/netif/ix/ixgbe_common.c

5029

u32 cmd, verify;

sys/dev/netif/ix/ixgbe_common.c

5030

u32 count = 0;

sys/dev/netif/ix/ixgbe_common.c

5067

s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)

sys/dev/netif/ix/ixgbe_common.c

5069

u32 cmd;

sys/dev/netif/ix/ixgbe_common.c

5070

u32 status;

sys/dev/netif/ix/ixgbe_common.c

5213

u32 reg, i;

sys/dev/netif/ix/ixgbe_common.c

5224

u32 pfdtxgswc;

sys/dev/netif/ix/ixgbe_common.c

5225

u32 rxctrl;

sys/dev/netif/ix/ixgbe_common.c

5246

u32 pfdtxgswc;

sys/dev/netif/ix/ixgbe_common.c

5247

u32 rxctrl;

sys/dev/netif/ix/ixgbe_common.c

5268

u32 fwsm;

sys/dev/netif/ix/ixgbe_common.c

5286

u32 fwsm, manc, factps;

sys/dev/netif/ix/ixgbe_common.c

5320

u32 speedcnt = 0;

sys/dev/netif/ix/ixgbe_common.c

5321

u32 i = 0;

sys/dev/netif/ix/ixgbe_common.c

643

u32 pba_num_size)

sys/dev/netif/ix/ixgbe_common.c

722

if (pba_num_size < (((u32)length * 2) - 1)) {

sys/dev/netif/ix/ixgbe_common.c

73

u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_common.c

752

s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)

sys/dev/netif/ix/ixgbe_common.c

767

*pba_num = (u32)(data << 16);

sys/dev/netif/ix/ixgbe_common.c

792

u32 eeprom_buf_size, u16 max_pba_block_size,

sys/dev/netif/ix/ixgbe_common.c

835

if (eeprom_buf_size > (u32)(pba->word[1] +

sys/dev/netif/ix/ixgbe_common.c

861

u32 eeprom_buf_size, struct ixgbe_pba *pba)

sys/dev/netif/ix/ixgbe_common.c

893

if (eeprom_buf_size > (u32)(pba->word[1] +

sys/dev/netif/ix/ixgbe_common.c

920

u32 eeprom_buf_size, u16 *pba_block_size)

sys/dev/netif/ix/ixgbe_common.c

979

u32 rar_high;

sys/dev/netif/ix/ixgbe_common.c

980

u32 rar_low;

sys/dev/netif/ix/ixgbe_common.h

100

s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_common.h

101

u32 enable_addr);

sys/dev/netif/ix/ixgbe_common.h

102

s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_common.h

105

u32 mc_addr_count,

sys/dev/netif/ix/ixgbe_common.h

108

u32 addr_count, ixgbe_mc_addr_itr func);

sys/dev/netif/ix/ixgbe_common.h

111

s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);

sys/dev/netif/ix/ixgbe_common.h

121

s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_common.h

122

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_common.h

125

s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);

sys/dev/netif/ix/ixgbe_common.h

126

s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);

sys/dev/netif/ix/ixgbe_common.h

128

s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_common.h

129

s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_common.h

134

s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

sys/dev/netif/ix/ixgbe_common.h

135

s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);

sys/dev/netif/ix/ixgbe_common.h

136

s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);

sys/dev/netif/ix/ixgbe_common.h

137

s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);

sys/dev/netif/ix/ixgbe_common.h

139

s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,

sys/dev/netif/ix/ixgbe_common.h

140

u32 vind, bool vlan_on, bool vlvf_bypass);

sys/dev/netif/ix/ixgbe_common.h

141

s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,

sys/dev/netif/ix/ixgbe_common.h

142

bool vlan_on, u32 *vfta_delta, u32 vfta,

sys/dev/netif/ix/ixgbe_common.h

145

s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass);

sys/dev/netif/ix/ixgbe_common.h

158

void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,

sys/dev/netif/ix/ixgbe_common.h

163

u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);

sys/dev/netif/ix/ixgbe_common.h

164

s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,

sys/dev/netif/ix/ixgbe_common.h

165

u32 length, u32 timeout, bool return_data);

sys/dev/netif/ix/ixgbe_common.h

166

s32 ixgbe_hic_unlocked(struct ixgbe_hw *, u32 *buffer, u32 length, u32 timeout);

sys/dev/netif/ix/ixgbe_common.h

169

u32 (*data)[FW_PHY_ACT_DATA_COUNT]);

sys/dev/netif/ix/ixgbe_common.h

171

s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status);

sys/dev/netif/ix/ixgbe_common.h

172

bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg);

sys/dev/netif/ix/ixgbe_common.h

173

s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,

sys/dev/netif/ix/ixgbe_common.h

174

u32 action);

sys/dev/netif/ix/ixgbe_common.h

175

s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value);

sys/dev/netif/ix/ixgbe_common.h

41

IXGBE_WRITE_REG(hw, reg, (u32) value); \

sys/dev/netif/ix/ixgbe_common.h

42

IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \

sys/dev/netif/ix/ixgbe_common.h

60

s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);

sys/dev/netif/ix/ixgbe_common.h

62

u32 pba_num_size);

sys/dev/netif/ix/ixgbe_common.h

64

u32 eeprom_buf_size, u16 max_pba_block_size,

sys/dev/netif/ix/ixgbe_common.h

67

u32 eeprom_buf_size, struct ixgbe_pba *pba);

sys/dev/netif/ix/ixgbe_common.h

69

u32 eeprom_buf_size, u16 *pba_block_size);

sys/dev/netif/ix/ixgbe_common.h

76

s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_common.h

77

s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_common.h

98

s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);

sys/dev/netif/ix/ixgbe_dcb.c

103

u32 min_credit = 0;

sys/dev/netif/ix/ixgbe_dcb.c

104

u32 credit_refill = 0;

sys/dev/netif/ix/ixgbe_dcb.c

105

u32 credit_max = 0;

sys/dev/netif/ix/ixgbe_dcb.c

156

(u32)IXGBE_DCB_MAX_CREDIT_REFILL);

sys/dev/netif/ix/ixgbe_dcb.c

96

u32 max_frame_size, u8 direction)

sys/dev/netif/ix/ixgbe_dcb.c

99

u32 min_multiplier = 0;

sys/dev/netif/ix/ixgbe_dcb.h

131

u32 dcb_cfg_version; /* Not used...OS-specific? */

sys/dev/netif/ix/ixgbe_dcb.h

132

u32 link_speed; /* For bandwidth allocation validation purpose */

sys/dev/netif/ix/ixgbe_dcb.h

144

struct ixgbe_dcb_config *, u32, u8);

sys/dev/netif/ix/ixgbe_dcb.h

67

u32 capabilities; /* DCB capabilities */

sys/dev/netif/ix/ixgbe_dcb_82598.c

123

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

124

u32 credit_refill = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

125

u32 credit_max = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

182

u32 reg, max_credits;

sys/dev/netif/ix/ixgbe_dcb_82598.c

201

reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

229

u32 reg;

sys/dev/netif/ix/ixgbe_dcb_82598.c

243

reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

244

reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

272

u32 fcrtl, reg;

sys/dev/netif/ix/ixgbe_dcb_82598.c

324

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

125

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

126

u32 credit_refill = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

127

u32 credit_max = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

155

reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

186

u32 reg, max_credits;

sys/dev/netif/ix/ixgbe_dcb_82599.c

200

reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

236

u32 reg;

sys/dev/netif/ix/ixgbe_dcb_82599.c

263

reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

264

reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

296

u32 i, j, fcrtl, reg;

sys/dev/netif/ix/ixgbe_dcb_82599.c

384

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

510

u32 reg;

sys/dev/netif/ix/ixgbe_dcb_82599.c

511

u32 q;

sys/dev/netif/ix/ixgbe_mbx.c

224

s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ix/ixgbe_mbx.c

253

s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ix/ixgbe_mbx.c

296

static u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw)

sys/dev/netif/ix/ixgbe_mbx.c

298

u32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX);

sys/dev/netif/ix/ixgbe_mbx.c

314

static s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_mbx.c

316

u32 v2p_mailbox = ixgbe_read_v2p_mailbox(hw);

sys/dev/netif/ix/ixgbe_mbx.c

425

static s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ix/ixgbe_mbx.c

467

static s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ix/ixgbe_mbx.c

47

s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ix/ixgbe_mbx.c

527

static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)

sys/dev/netif/ix/ixgbe_mbx.c

529

u32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index));

sys/dev/netif/ix/ixgbe_mbx.c

551

u32 vf_bit = vf_number % 16;

sys/dev/netif/ix/ixgbe_mbx.c

575

u32 vf_bit = vf_number % 16;

sys/dev/netif/ix/ixgbe_mbx.c

597

u32 reg_offset = (vf_number < 32) ? 0 : 1;

sys/dev/netif/ix/ixgbe_mbx.c

598

u32 vf_shift = vf_number % 32;

sys/dev/netif/ix/ixgbe_mbx.c

599

u32 vflre = 0;

sys/dev/netif/ix/ixgbe_mbx.c

637

u32 p2v_mailbox;

sys/dev/netif/ix/ixgbe_mbx.c

665

static s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ix/ixgbe_mbx.c

708

static s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,

sys/dev/netif/ix/ixgbe_mbx.c

73

s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)

sys/dev/netif/ix/ixgbe_mbx.h

155

s32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_mbx.h

156

s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_mbx.h

157

s32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_mbx.h

158

s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_osdep.h

130

#define __le32 u32

sys/dev/netif/ix/ixgbe_osdep.h

133

#define __be32 u32

sys/dev/netif/ix/ixgbe_osdep.h

187

extern u16 ixgbe_read_pci_cfg_vf(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_osdep.h

188

extern u16 ixgbe_read_pci_cfg_pf(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_osdep.h

190

extern void ixgbe_write_pci_cfg_vf(struct ixgbe_hw *, u32, u16);

sys/dev/netif/ix/ixgbe_osdep.h

191

extern void ixgbe_write_pci_cfg_pf(struct ixgbe_hw *, u32, u16);

sys/dev/netif/ix/ixgbe_osdep.h

195

extern u32 ixgbe_read_reg_vf(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_osdep.h

196

extern u32 ixgbe_read_reg_pf(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_osdep.h

197

extern void ixgbe_write_reg_vf(struct ixgbe_hw *, u32, u32);

sys/dev/netif/ix/ixgbe_osdep.h

198

extern void ixgbe_write_reg_pf(struct ixgbe_hw *, u32, u32);

sys/dev/netif/ix/ixgbe_osdep.h

200

extern u32 ixgbe_read_reg_array_vf(struct ixgbe_hw *, u32, u32);

sys/dev/netif/ix/ixgbe_osdep.h

201

extern u32 ixgbe_read_reg_array_pf(struct ixgbe_hw *, u32, u32);

sys/dev/netif/ix/ixgbe_osdep.h

203

extern void ixgbe_write_reg_array_vf(struct ixgbe_hw *, u32, u32, u32);

sys/dev/netif/ix/ixgbe_osdep.h

204

extern void ixgbe_write_reg_array_pf(struct ixgbe_hw *, u32, u32, u32);

sys/dev/netif/ix/ixgbe_osdep_pf.c

104

ixgbe_write_reg_pf(struct ixgbe_hw *hw, u32 reg, u32 val)

sys/dev/netif/ix/ixgbe_osdep_pf.c

111

u32

sys/dev/netif/ix/ixgbe_osdep_pf.c

112

ixgbe_read_reg_array_pf(struct ixgbe_hw *hw, u32 reg, u32 offset)

sys/dev/netif/ix/ixgbe_osdep_pf.c

120

ixgbe_write_reg_array_pf(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)

sys/dev/netif/ix/ixgbe_osdep_pf.c

48

ixgbe_read_pci_cfg_pf(struct ixgbe_hw *hw, u32 reg)

sys/dev/netif/ix/ixgbe_osdep_pf.c

54

ixgbe_write_pci_cfg_pf(struct ixgbe_hw *hw, u32 reg, u16 value)

sys/dev/netif/ix/ixgbe_osdep_pf.c

59

u32

sys/dev/netif/ix/ixgbe_osdep_pf.c

60

ixgbe_read_reg_pf(struct ixgbe_hw *hw, u32 reg)

sys/dev/netif/ix/ixgbe_osdep_pf.c

63

u32 retval;

sys/dev/netif/ix/ixgbe_phy.c

116

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_phy.c

1160

u32 i;

sys/dev/netif/ix/ixgbe_phy.c

1304

u32 vendor_oui = 0;

sys/dev/netif/ix/ixgbe_phy.c

1647

u32 vendor_oui = 0;

sys/dev/netif/ix/ixgbe_phy.c

194

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_phy.c

2005

u32 max_retry = 10;

sys/dev/netif/ix/ixgbe_phy.c

2006

u32 retry = 0;

sys/dev/netif/ix/ixgbe_phy.c

2007

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_phy.c

2131

u32 max_retry = 1;

sys/dev/netif/ix/ixgbe_phy.c

2132

u32 retry = 0;

sys/dev/netif/ix/ixgbe_phy.c

2133

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_phy.c

2231

u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_phy.c

2266

u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_phy.c

2267

u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2268

u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2269

u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2327

u32 i2cctl;

sys/dev/netif/ix/ixgbe_phy.c

2358

u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2360

u32 i = 0;

sys/dev/netif/ix/ixgbe_phy.c

2361

u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_phy.c

2362

u32 timeout = 10;

sys/dev/netif/ix/ixgbe_phy.c

2411

u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_phy.c

2412

u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2448

u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_phy.c

2482

static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)

sys/dev/netif/ix/ixgbe_phy.c

2484

u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2485

u32 i = 0;

sys/dev/netif/ix/ixgbe_phy.c

2486

u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;

sys/dev/netif/ix/ixgbe_phy.c

2487

u32 i2cctl_r = 0;

sys/dev/netif/ix/ixgbe_phy.c

2518

static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)

sys/dev/netif/ix/ixgbe_phy.c

2541

static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)

sys/dev/netif/ix/ixgbe_phy.c

2543

u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2588

static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)

sys/dev/netif/ix/ixgbe_phy.c

2590

u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/netif/ix/ixgbe_phy.c

2619

u32 i2cctl;

sys/dev/netif/ix/ixgbe_phy.c

2620

u32 i;

sys/dev/netif/ix/ixgbe_phy.c

2683

u32 status;

sys/dev/netif/ix/ixgbe_phy.c

381

u32 mmngc;

sys/dev/netif/ix/ixgbe_phy.c

405

bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)

sys/dev/netif/ix/ixgbe_phy.c

431

u32 status;

sys/dev/netif/ix/ixgbe_phy.c

442

hw->phy.id = (u32)(phy_id_high << 16);

sys/dev/netif/ix/ixgbe_phy.c

446

hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);

sys/dev/netif/ix/ixgbe_phy.c

447

hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);

sys/dev/netif/ix/ixgbe_phy.c

46

static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);

sys/dev/netif/ix/ixgbe_phy.c

460

enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)

sys/dev/netif/ix/ixgbe_phy.c

47

static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);

sys/dev/netif/ix/ixgbe_phy.c

48

static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);

sys/dev/netif/ix/ixgbe_phy.c

49

static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);

sys/dev/netif/ix/ixgbe_phy.c

502

u32 i;

sys/dev/netif/ix/ixgbe_phy.c

583

s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_phy.c

586

u32 i, data, command;

sys/dev/netif/ix/ixgbe_phy.c

665

s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_phy.c

666

u32 device_type, u16 *phy_data)

sys/dev/netif/ix/ixgbe_phy.c

669

u32 gssr = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_phy.c

691

s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_phy.c

692

u32 device_type, u16 phy_data)

sys/dev/netif/ix/ixgbe_phy.c

694

u32 i, command;

sys/dev/netif/ix/ixgbe_phy.c

697

IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);

sys/dev/netif/ix/ixgbe_phy.c

765

s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_phy.c

766

u32 device_type, u16 phy_data)

sys/dev/netif/ix/ixgbe_phy.c

769

u32 gssr = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_phy.c

995

u32 time_out;

sys/dev/netif/ix/ixgbe_phy.c

996

u32 max_time_out = 10;

sys/dev/netif/ix/ixgbe_phy.h

160

bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);

sys/dev/netif/ix/ixgbe_phy.h

161

enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);

sys/dev/netif/ix/ixgbe_phy.h

165

s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_phy.h

167

s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/netif/ix/ixgbe_phy.h

169

s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_phy.h

170

u32 device_type, u16 *phy_data);

sys/dev/netif/ix/ixgbe_phy.h

171

s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_phy.h

172

u32 device_type, u16 phy_data);

sys/dev/netif/ix/ixgbe_type.h

2925

#define __le32 u32

sys/dev/netif/ix/ixgbe_type.h

2934

#define __be32 u32

sys/dev/netif/ix/ixgbe_type.h

302

u32 etk_id;

sys/dev/netif/ix/ixgbe_type.h

3185

u32 address;

sys/dev/netif/ix/ixgbe_type.h

3194

u32 address;

sys/dev/netif/ix/ixgbe_type.h

3395

typedef u32 ixgbe_autoneg_advertised;

sys/dev/netif/ix/ixgbe_type.h

3397

typedef u32 ixgbe_link_speed;

sys/dev/netif/ix/ixgbe_type.h

3767

u32 num_mc_addrs;

sys/dev/netif/ix/ixgbe_type.h

3768

u32 rar_used_count;

sys/dev/netif/ix/ixgbe_type.h

3769

u32 mta_in_use;

sys/dev/netif/ix/ixgbe_type.h

3770

u32 overflow_promisc;

sys/dev/netif/ix/ixgbe_type.h

3787

u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */

sys/dev/netif/ix/ixgbe_type.h

3788

u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */

sys/dev/netif/ix/ixgbe_type.h

3883

u32 *vmdq);

sys/dev/netif/ix/ixgbe_type.h

3914

s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);

sys/dev/netif/ix/ixgbe_type.h

3915

s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);

sys/dev/netif/ix/ixgbe_type.h

3917

s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3920

s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3921

void (*release_swfw_sync)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3923

s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);

sys/dev/netif/ix/ixgbe_type.h

3924

s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);

sys/dev/netif/ix/ixgbe_type.h

3938

void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);

sys/dev/netif/ix/ixgbe_type.h

3941

s32 (*led_on)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3942

s32 (*led_off)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3943

s32 (*blink_led_start)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3944

s32 (*blink_led_stop)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3948

s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);

sys/dev/netif/ix/ixgbe_type.h

3949

s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);

sys/dev/netif/ix/ixgbe_type.h

3950

s32 (*clear_rar)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3951

s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);

sys/dev/netif/ix/ixgbe_type.h

3952

s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);

sys/dev/netif/ix/ixgbe_type.h

3953

s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);

sys/dev/netif/ix/ixgbe_type.h

3954

s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);

sys/dev/netif/ix/ixgbe_type.h

3956

s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,

sys/dev/netif/ix/ixgbe_type.h

3958

s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,

sys/dev/netif/ix/ixgbe_type.h

3963

s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);

sys/dev/netif/ix/ixgbe_type.h

3964

s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32,

sys/dev/netif/ix/ixgbe_type.h

3978

s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status);

sys/dev/netif/ix/ixgbe_type.h

3979

bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);

sys/dev/netif/ix/ixgbe_type.h

3980

s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);

sys/dev/netif/ix/ixgbe_type.h

3981

s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value);

sys/dev/netif/ix/ixgbe_type.h

3992

s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);

sys/dev/netif/ix/ixgbe_type.h

3993

s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);

sys/dev/netif/ix/ixgbe_type.h

3996

void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);

sys/dev/netif/ix/ixgbe_type.h

3997

void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);

sys/dev/netif/ix/ixgbe_type.h

4006

s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);

sys/dev/netif/ix/ixgbe_type.h

4007

s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);

sys/dev/netif/ix/ixgbe_type.h

4008

s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);

sys/dev/netif/ix/ixgbe_type.h

4009

s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);

sys/dev/netif/ix/ixgbe_type.h

4048

u32 semaphore_delay;

sys/dev/netif/ix/ixgbe_type.h

4067

u32 mta_shadow[IXGBE_MAX_MTA];

sys/dev/netif/ix/ixgbe_type.h

4069

u32 mcft_size;

sys/dev/netif/ix/ixgbe_type.h

4070

u32 vft_size;

sys/dev/netif/ix/ixgbe_type.h

4071

u32 num_rar_entries;

sys/dev/netif/ix/ixgbe_type.h

4072

u32 rar_highwater;

sys/dev/netif/ix/ixgbe_type.h

4073

u32 rx_pb_size;

sys/dev/netif/ix/ixgbe_type.h

4074

u32 max_tx_queues;

sys/dev/netif/ix/ixgbe_type.h

4075

u32 max_rx_queues;

sys/dev/netif/ix/ixgbe_type.h

4076

u32 orig_autoc;

sys/dev/netif/ix/ixgbe_type.h

4079

u32 orig_autoc2;

sys/dev/netif/ix/ixgbe_type.h

4087

u32 max_link_up_time;

sys/dev/netif/ix/ixgbe_type.h

4094

u32 addr;

sys/dev/netif/ix/ixgbe_type.h

4095

u32 id;

sys/dev/netif/ix/ixgbe_type.h

4098

u32 revision;

sys/dev/netif/ix/ixgbe_type.h

4100

u32 phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_type.h

4111

u32 nw_mng_if_sel;

sys/dev/netif/ix/ixgbe_type.h

4118

s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_type.h

4119

s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_type.h

4120

s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_type.h

4121

s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);

sys/dev/netif/ix/ixgbe_type.h

4128

u32 msgs_tx;

sys/dev/netif/ix/ixgbe_type.h

4129

u32 msgs_rx;

sys/dev/netif/ix/ixgbe_type.h

4131

u32 acks;

sys/dev/netif/ix/ixgbe_type.h

4132

u32 reqs;

sys/dev/netif/ix/ixgbe_type.h

4133

u32 rsts;

sys/dev/netif/ix/ixgbe_type.h

4139

u32 timeout;

sys/dev/netif/ix/ixgbe_type.h

4140

u32 usec_delay;

sys/dev/netif/ix/ixgbe_type.h

4141

u32 v2p_mailbox;

sys/dev/netif/ix/ixgbe_type.h

4156

const u32 *mvals;

sys/dev/netif/ix/ixgbe_type.h

4288

u32 logs;

sys/dev/netif/ix/ixgbe_type.h

4289

u32 clear_off;

sys/dev/netif/ix/ixgbe_type.h

696

u32 link_speed;

sys/dev/netif/ix/ixgbe_x540.c

1003

s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_x540.c

1005

u32 macc_reg;

sys/dev/netif/ix/ixgbe_x540.c

1006

u32 ledctl_reg;

sys/dev/netif/ix/ixgbe_x540.c

1044

s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)

sys/dev/netif/ix/ixgbe_x540.c

1046

u32 macc_reg;

sys/dev/netif/ix/ixgbe_x540.c

1047

u32 ledctl_reg;

sys/dev/netif/ix/ixgbe_x540.c

215

u32 ctrl, i;

sys/dev/netif/ix/ixgbe_x540.c

216

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_x540.c

366

u32 eec;

sys/dev/netif/ix/ixgbe_x540.c

689

u32 flup;

sys/dev/netif/ix/ixgbe_x540.c

736

u32 i;

sys/dev/netif/ix/ixgbe_x540.c

737

u32 reg;

sys/dev/netif/ix/ixgbe_x540.c

766

s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_x540.c

768

u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;

sys/dev/netif/ix/ixgbe_x540.c

769

u32 fwmask = swmask << 5;

sys/dev/netif/ix/ixgbe_x540.c

770

u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;

sys/dev/netif/ix/ixgbe_x540.c

771

u32 timeout = 200;

sys/dev/netif/ix/ixgbe_x540.c

772

u32 hwmask = 0;

sys/dev/netif/ix/ixgbe_x540.c

773

u32 swfw_sync;

sys/dev/netif/ix/ixgbe_x540.c

774

u32 i;

sys/dev/netif/ix/ixgbe_x540.c

838

u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |

sys/dev/netif/ix/ixgbe_x540.c

863

void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_x540.c

865

u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);

sys/dev/netif/ix/ixgbe_x540.c

866

u32 swfw_sync;

sys/dev/netif/ix/ixgbe_x540.c

891

u32 timeout = 2000;

sys/dev/netif/ix/ixgbe_x540.c

892

u32 i;

sys/dev/netif/ix/ixgbe_x540.c

893

u32 swsm;

sys/dev/netif/ix/ixgbe_x540.c

948

u32 swsm;

sys/dev/netif/ix/ixgbe_x540.c

974

u32 rmask;

sys/dev/netif/ix/ixgbe_x540.h

61

s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_x540.h

62

void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_x540.h

65

s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_x540.h

66

s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);

sys/dev/netif/ix/ixgbe_x550.c

1019

u32 eec;

sys/dev/netif/ix/ixgbe_x550.c

1064

IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);

sys/dev/netif/ix/ixgbe_x550.c

1065

IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));

sys/dev/netif/ix/ixgbe_x550.c

1080

u32 pfvfspoof;

sys/dev/netif/ix/ixgbe_x550.c

1102

static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)

sys/dev/netif/ix/ixgbe_x550.c

1104

u32 i, command = 0;

sys/dev/netif/ix/ixgbe_x550.c

1134

s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

1135

u32 device_type, u32 data)

sys/dev/netif/ix/ixgbe_x550.c

1137

u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;

sys/dev/netif/ix/ixgbe_x550.c

1138

u32 command, error;

sys/dev/netif/ix/ixgbe_x550.c

1180

s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

1181

u32 device_type, u32 *data)

sys/dev/netif/ix/ixgbe_x550.c

1183

u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;

sys/dev/netif/ix/ixgbe_x550.c

1184

u32 command, error;

sys/dev/netif/ix/ixgbe_x550.c

1236

status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,

sys/dev/netif/ix/ixgbe_x550.c

1274

status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,

sys/dev/netif/ix/ixgbe_x550.c

1295

s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

1296

u32 device_type, u32 data)

sys/dev/netif/ix/ixgbe_x550.c

1311

status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,

sys/dev/netif/ix/ixgbe_x550.c

1325

s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

1326

u32 device_type, u32 *data)

sys/dev/netif/ix/ixgbe_x550.c

1343

status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,

sys/dev/netif/ix/ixgbe_x550.c

1361

u32 reg;

sys/dev/netif/ix/ixgbe_x550.c

1384

u32 reg;

sys/dev/netif/ix/ixgbe_x550.c

1406

void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)

sys/dev/netif/ix/ixgbe_x550.c

1408

u32 idx, reg, num_qs, start_q, bitmask;

sys/dev/netif/ix/ixgbe_x550.c

1446

void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)

sys/dev/netif/ix/ixgbe_x550.c

1448

u32 wqbr;

sys/dev/netif/ix/ixgbe_x550.c

1449

u32 i, j, reg, q, shift, vf, idx;

sys/dev/netif/ix/ixgbe_x550.c

1636

u32 link_ctrl;

sys/dev/netif/ix/ixgbe_x550.c

1654

u32 flx_mask_st20;

sys/dev/netif/ix/ixgbe_x550.c

1685

u32 lval, sval, flx_val;

sys/dev/netif/ix/ixgbe_x550.c

1754

u32 lval, sval, flx_val;

sys/dev/netif/ix/ixgbe_x550.c

180

u32 retry;

sys/dev/netif/ix/ixgbe_x550.c

1960

u32 status;

sys/dev/netif/ix/ixgbe_x550.c

2047

u32 status;

sys/dev/netif/ix/ixgbe_x550.c

2146

u32 reg_val;

sys/dev/netif/ix/ixgbe_x550.c

2199

u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/netif/ix/ixgbe_x550.c

2223

u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/netif/ix/ixgbe_x550.c

2391

u32 hlreg0;

sys/dev/netif/ix/ixgbe_x550.c

2429

u32 ctrl = 0;

sys/dev/netif/ix/ixgbe_x550.c

2430

u32 i;

sys/dev/netif/ix/ixgbe_x550.c

2432

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_x550.c

253

u32 swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/netif/ix/ixgbe_x550.c

2560

u32 status;

sys/dev/netif/ix/ixgbe_x550.c

2670

u32 reg_val;

sys/dev/netif/ix/ixgbe_x550.c

2722

u32 reg_slice, reg_phy_int, slice_offset;

sys/dev/netif/ix/ixgbe_x550.c

2822

u32 reg_val;

sys/dev/netif/ix/ixgbe_x550.c

2893

u32 reg_val;

sys/dev/netif/ix/ixgbe_x550.c

2950

u32 ret;

sys/dev/netif/ix/ixgbe_x550.c

2989

u32 status;

sys/dev/netif/ix/ixgbe_x550.c

3051

u32 reg_val;

sys/dev/netif/ix/ixgbe_x550.c

3120

const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;

sys/dev/netif/ix/ixgbe_x550.c

3141

status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),

sys/dev/netif/ix/ixgbe_x550.c

3164

const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;

sys/dev/netif/ix/ixgbe_x550.c

3166

u32 current_word = 0;

sys/dev/netif/ix/ixgbe_x550.c

3169

u32 i;

sys/dev/netif/ix/ixgbe_x550.c

3197

status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),

sys/dev/netif/ix/ixgbe_x550.c

3206

u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +

sys/dev/netif/ix/ixgbe_x550.c

3208

u32 value = IXGBE_READ_REG(hw, reg);

sys/dev/netif/ix/ixgbe_x550.c

3253

status = ixgbe_host_interface_command(hw, (u32 *)&buffer,

sys/dev/netif/ix/ixgbe_x550.c

329

u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/netif/ix/ixgbe_x550.c

3300

u32 i = 0;

sys/dev/netif/ix/ixgbe_x550.c

3340

u32 buffer_size)

sys/dev/netif/ix/ixgbe_x550.c

3376

if (buffer && ((u32)start + (u32)length > buffer_size))

sys/dev/netif/ix/ixgbe_x550.c

3407

s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)

sys/dev/netif/ix/ixgbe_x550.c

3605

status = ixgbe_host_interface_command(hw, (u32 *)&buffer,

sys/dev/netif/ix/ixgbe_x550.c

3712

u32 rxctrl, pfdtxgswc;

sys/dev/netif/ix/ixgbe_x550.c

3734

status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,

sys/dev/netif/ix/ixgbe_x550.c

3762

u32 save_autoneg;

sys/dev/netif/ix/ixgbe_x550.c

3904

u32 pause, asm_dir, reg_val;

sys/dev/netif/ix/ixgbe_x550.c

3993

u32 link_s1, lp_an_page_low, an_cntl_1;

sys/dev/netif/ix/ixgbe_x550.c

402

u32 (*data)[FW_PHY_ACT_DATA_COUNT])

sys/dev/netif/ix/ixgbe_x550.c

4083

u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/netif/ix/ixgbe_x550.c

4138

u32 an_cntl = 0;

sys/dev/netif/ix/ixgbe_x550.c

422

rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,

sys/dev/netif/ix/ixgbe_x550.c

4224

u32 esdp;

sys/dev/netif/ix/ixgbe_x550.c

4244

s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_x550.c

4267

void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_x550.c

4284

static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_x550.c

4286

u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;

sys/dev/netif/ix/ixgbe_x550.c

43

static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);

sys/dev/netif/ix/ixgbe_x550.c

4334

static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)

sys/dev/netif/ix/ixgbe_x550.c

4336

u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;

sys/dev/netif/ix/ixgbe_x550.c

4358

s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

4359

u32 device_type, u16 *phy_data)

sys/dev/netif/ix/ixgbe_x550.c

4362

u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/netif/ix/ixgbe_x550.c

4386

s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

4387

u32 device_type, u16 phy_data)

sys/dev/netif/ix/ixgbe_x550.c

4390

u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/netif/ix/ixgbe_x550.c

44

static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);

sys/dev/netif/ix/ixgbe_x550.c

4419

u32 status;

sys/dev/netif/ix/ixgbe_x550.c

4485

u32 status;

sys/dev/netif/ix/ixgbe_x550.c

4541

s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)

sys/dev/netif/ix/ixgbe_x550.c

4566

s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)

sys/dev/netif/ix/ixgbe_x550.c

461

u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/netif/ix/ixgbe_x550.c

4628

ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,

sys/dev/netif/ix/ixgbe_x550.c

4655

u32 fwsm;

sys/dev/netif/ix/ixgbe_x550.c

516

u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/netif/ix/ixgbe_x550.c

522

static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

523

u32 device_type, u16 *phy_data)

sys/dev/netif/ix/ixgbe_x550.c

529

static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.c

530

u32 device_type, u16 phy_data)

sys/dev/netif/ix/ixgbe_x550.c

702

u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/netif/ix/ixgbe_x550.c

887

u32 reg, high_pri_tc;

sys/dev/netif/ix/ixgbe_x550.c

935

u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;

sys/dev/netif/ix/ixgbe_x550.c

990

u32 reg;

sys/dev/netif/ix/ixgbe_x550.h

105

s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.h

106

u32 device_type, u16 *phy_data);

sys/dev/netif/ix/ixgbe_x550.h

107

s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.h

108

u32 device_type, u16 phy_data);

sys/dev/netif/ix/ixgbe_x550.h

123

s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx);

sys/dev/netif/ix/ixgbe_x550.h

124

s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx);

sys/dev/netif/ix/ixgbe_x550.h

48

s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size);

sys/dev/netif/ix/ixgbe_x550.h

65

s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.h

66

u32 device_type, u32 data);

sys/dev/netif/ix/ixgbe_x550.h

67

s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.h

68

u32 device_type, u32 *data);

sys/dev/netif/ix/ixgbe_x550.h

73

s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.h

74

u32 device_type, u32 data);

sys/dev/netif/ix/ixgbe_x550.h

75

s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/netif/ix/ixgbe_x550.h

76

u32 device_type, u32 *data);

sys/dev/netif/ix/ixgbe_x550.h

79

void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap);

sys/dev/netif/ix/ixgbe_x550.h

80

void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf);

sys/dev/netif/ix/ixgbe_x550.h

96

s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask);

sys/dev/netif/ix/ixgbe_x550.h

97

void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask);

sys/dev/raid/asr/osd_util.h

190

uLONG u32;

sys/dev/raid/mpr/mpr.c

124

u32 low;

sys/dev/raid/mpr/mpr.c

125

u32 high;

sys/dev/raid/mpr/mpr.c

2196

mpr_sas_log_info(struct mpr_softc *sc , u32 log_info)

sys/dev/raid/mpr/mpr.c

2199

u32 loginfo;

sys/dev/raid/mpr/mpr.c

2201

u32 subcode:16;

sys/dev/raid/mpr/mpr.c

2202

u32 code:8;

sys/dev/raid/mpr/mpr.c

2203

u32 originator:4;

sys/dev/raid/mpr/mpr.c

2204

u32 bus_type:4;

sys/dev/raid/mpr/mpr.c

3236

u32 sge_flags;

sys/dev/raid/mpr/mpr.c

912

u32 cntdn, count;

sys/dev/raid/mpr/mpr.c

913

u32 int_status;

sys/dev/raid/mpr/mpr.c

914

u32 doorbell;

sys/dev/raid/mpr/mpr_config.c

1185

*mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address)

sys/dev/raid/mpr/mpr_config.c

1316

*mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, u16 handle)

sys/dev/raid/mpr/mpr_config.c

1475

Mpi2RaidPhysDiskPage0_t *config_page, u32 page_address)

sys/dev/raid/mpr/mpr_config.c

644

*mpi_reply, Mpi2SasDevicePage0_t *config_page, u32 form, u16 handle)

sys/dev/raid/mpr/mpr_config.c

781

*mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle)

sys/dev/raid/mpr/mpr_config.c

918

*mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle)

sys/dev/raid/mpr/mpr_mapping.c

1147

u32 map_idx, index, device_info;

sys/dev/raid/mpr/mpr_mapping.c

1324

u32 map_idx, index;

sys/dev/raid/mpr/mpr_mapping.c

1468

u32 start_idx = et_entry->start_index;

sys/dev/raid/mpr/mpr_mapping.c

1490

u32 remove_idx;

sys/dev/raid/mpr/mpr_mapping.c

1579

u32 search_idx, map_idx;

sys/dev/raid/mpr/mpr_mapping.c

1580

u32 entry;

sys/dev/raid/mpr/mpr_mapping.c

1836

u32 search_idx, map_idx;

sys/dev/raid/mpr/mpr_mapping.c

1837

u32 entry;

sys/dev/raid/mpr/mpr_mapping.c

2211

u32 map_idx, dev_idx;

sys/dev/raid/mpr/mpr_mapping.c

2212

u32 start_idx = 0, end_idx = 0; /* XXX swildner: warning fix */

sys/dev/raid/mpr/mpr_mapping.c

2219

u32 phy_bits = 0;

sys/dev/raid/mpr/mpr_mapping.c

2398

u32 i;

sys/dev/raid/mpr/mpr_mapping.c

2403

u32 start_idx = 0, end_idx = 0;

sys/dev/raid/mpr/mpr_mapping.c

241

_mapping_get_ir_maprange(struct mpr_softc *sc, u32 *start_idx, u32 *end_idx)

sys/dev/raid/mpr/mpr_mapping.c

2664

u32 map_idx;

sys/dev/raid/mpr/mpr_mapping.c

2703

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mpr/mpr_mapping.c

2749

u32 saved_phy_bits;

sys/dev/raid/mpr/mpr_mapping.c

2999

u32 map_idx, flags;

sys/dev/raid/mpr/mpr_mapping.c

340

static u32

sys/dev/raid/mpr/mpr_mapping.c

343

u32 map_idx, high_idx = MPR_MAPTABLE_BAD_IDX;

sys/dev/raid/mpr/mpr_mapping.c

345

u32 start_idx, end_idx, start_idx_ir, end_idx_ir;

sys/dev/raid/mpr/mpr_mapping.c

379

static u32

sys/dev/raid/mpr/mpr_mapping.c

382

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mpr/mpr_mapping.c

401

static u32

sys/dev/raid/mpr/mpr_mapping.c

404

u32 map_idx;

sys/dev/raid/mpr/mpr_mapping.c

422

static u32

sys/dev/raid/mpr/mpr_mapping.c

425

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mpr/mpr_mapping.c

444

static u32

sys/dev/raid/mpr/mpr_mapping.c

447

u32 map_idx;

sys/dev/raid/mpr/mpr_mapping.c

467

static u32

sys/dev/raid/mpr/mpr_mapping.c

471

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mpr/mpr_mapping.c

472

u32 high_idx = MPR_MAPTABLE_BAD_IDX;

sys/dev/raid/mpr/mpr_mapping.c

510

static u32

sys/dev/raid/mpr/mpr_mapping.c

511

_mapping_get_free_mt_idx(struct mpr_softc *sc, u32 start_idx)

sys/dev/raid/mpr/mpr_mapping.c

513

u32 map_idx, max_idx = sc->max_devices;

sys/dev/raid/mpr/mpr_mapping.c

539

_mapping_get_dpm_idx_from_id(struct mpr_softc *sc, u64 id, u32 phy_bits)

sys/dev/raid/mpr/mpr_mapping.c

567

static u32

sys/dev/raid/mpr/mpr_mapping.c

575

u32 map_idx;

sys/dev/raid/mpr/mpr_mapping.c

645

_mapping_update_ir_missing_cnt(struct mpr_softc *sc, u32 map_idx,

sys/dev/raid/mpr/mpr_mapping.c

759

u32 i;

sys/dev/raid/mpr/mpr_mapping.c

801

_mapping_inc_missing_count(struct mpr_softc *sc, u32 map_idx)

sys/dev/raid/mpr/mpr_mapping.c

860

u32 map_idx;

sys/dev/raid/mpr/mpr_mapping.c

890

u32 map_idx;

sys/dev/raid/mpr/mpr_mapping.c

914

static u32

sys/dev/raid/mpr/mpr_mapping.c

919

u32 skip_count, end_of_table, map_idx, enc_idx;

sys/dev/raid/mpr/mpr_mapping.c

921

u32 start_idx = MPR_MAPTABLE_BAD_IDX;

sys/dev/raid/mpr/mpr_mapping.h

120

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD);

sys/dev/raid/mpr/mpr_sas.c

2235

u32 response_info;

sys/dev/raid/mpr/mpr_sas.c

2243

u32 log_info = le32toh(mpi_reply->IOCLogInfo);

sys/dev/raid/mpr/mpr_sas_lsi.c

1033

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD)

sys/dev/raid/mpr/mpr_sas_lsi.c

1037

u32 *bufferptr;

sys/dev/raid/mpr/mpr_sas_lsi.c

1041

u32 ioc_status;

sys/dev/raid/mpr/mpr_sas_lsi.c

1094

bufferptr = (u32 *)buffer;

sys/dev/raid/mpr/mpr_sas_lsi.c

111

static u32 event_count;

sys/dev/raid/mpr/mpr_sas_lsi.c

1128

Mpi2SataPassthroughReply_t *mpi_reply, char *id_buffer, int sz, u32 devinfo)

sys/dev/raid/mpr/mpr_sas_lsi.c

121

u32 devinfo);

sys/dev/raid/mpr/mpr_sas_lsi.c

124

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD);

sys/dev/raid/mpr/mpr_sas_lsi.c

1275

u32 device_info, parent_devinfo = 0;

sys/dev/raid/mpr/mpr_sas_lsi.c

1601

u32 start_idx, end_idx;

sys/dev/raid/mpr/mpr_sas_lsi.c

487

u32 state;

sys/dev/raid/mpr/mpr_sas_lsi.c

807

u32 device_info, parent_devinfo = 0;

sys/dev/raid/mpr/mpr_sas_lsi.c

94

u32 high;

sys/dev/raid/mpr/mpr_sas_lsi.c

95

u32 low;

sys/dev/raid/mpr/mprvar.h

115

u32 device_info;

sys/dev/raid/mpr/mprvar.h

116

u32 phy_bits;

sys/dev/raid/mpr/mprvar.h

143

u32 start_index;

sys/dev/raid/mpr/mprvar.h

144

u32 phy_bits;

sys/dev/raid/mpr/mprvar.h

791

*mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address);

sys/dev/raid/mpr/mprvar.h

797

Mpi2SasDevicePage0_t *, u32 , u16 );

sys/dev/raid/mpr/mprvar.h

799

*mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle);

sys/dev/raid/mpr/mprvar.h

801

*mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle);

sys/dev/raid/mpr/mprvar.h

805

Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form,

sys/dev/raid/mpr/mprvar.h

811

u32 page_address);

sys/dev/raid/mps/mps_config.c

1018

*mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address)

sys/dev/raid/mps/mps_config.c

1138

*mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, u16 handle)

sys/dev/raid/mps/mps_config.c

1283

Mpi2RaidPhysDiskPage0_t *config_page, u32 page_address)

sys/dev/raid/mps/mps_config.c

473

raid_vol_pg0, (u32)raid_vol_pg0->DevHandle)) {

sys/dev/raid/mps/mps_config.c

779

*mpi_reply, Mpi2SasDevicePage0_t *config_page, u32 form, u16 handle)

sys/dev/raid/mps/mps_mapping.c

1016

u32 start_idx = et_entry->start_index;

sys/dev/raid/mps/mps_mapping.c

1037

u32 remove_idx;

sys/dev/raid/mps/mps_mapping.c

1119

u32 search_idx, map_idx;

sys/dev/raid/mps/mps_mapping.c

1120

u32 entry;

sys/dev/raid/mps/mps_mapping.c

1465

u32 map_idx, dev_idx, start_idx, end_idx;

sys/dev/raid/mps/mps_mapping.c

1472

u32 phy_bits = 0;

sys/dev/raid/mps/mps_mapping.c

1597

u32 i;

sys/dev/raid/mps/mps_mapping.c

1603

u32 start_idx, end_idx;

sys/dev/raid/mps/mps_mapping.c

1823

u32 map_idx;

sys/dev/raid/mps/mps_mapping.c

1862

u32 map_idx;

sys/dev/raid/mps/mps_mapping.c

1907

u32 saved_phy_bits;

sys/dev/raid/mps/mps_mapping.c

2091

Mpi2EventDataIrConfigChangeList_t *event_data, int evt_idx, u32 *map_idx,

sys/dev/raid/mps/mps_mapping.c

2095

u32 st_idx, end_idx, mt_idx = *map_idx;

sys/dev/raid/mps/mps_mapping.c

2150

u32 map_idx, flags;

sys/dev/raid/mps/mps_mapping.c

221

_mapping_get_ir_maprange(struct mps_softc *sc, u32 *start_idx, u32 *end_idx)

sys/dev/raid/mps/mps_mapping.c

320

static u32

sys/dev/raid/mps/mps_mapping.c

323

u32 map_idx, high_idx = MPS_ENCTABLE_BAD_IDX;

sys/dev/raid/mps/mps_mapping.c

325

u32 start_idx, end_idx, start_idx_ir, end_idx_ir;

sys/dev/raid/mps/mps_mapping.c

358

static u32

sys/dev/raid/mps/mps_mapping.c

361

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mps/mps_mapping.c

380

static u32

sys/dev/raid/mps/mps_mapping.c

383

u32 map_idx;

sys/dev/raid/mps/mps_mapping.c

401

static u32

sys/dev/raid/mps/mps_mapping.c

404

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mps/mps_mapping.c

423

static u32

sys/dev/raid/mps/mps_mapping.c

426

u32 map_idx;

sys/dev/raid/mps/mps_mapping.c

446

static u32

sys/dev/raid/mps/mps_mapping.c

450

u32 start_idx, end_idx, map_idx;

sys/dev/raid/mps/mps_mapping.c

451

u32 high_idx = MPS_MAPTABLE_BAD_IDX;

sys/dev/raid/mps/mps_mapping.c

478

static u32

sys/dev/raid/mps/mps_mapping.c

479

_mapping_get_free_mt_idx(struct mps_softc *sc, u32 start_idx)

sys/dev/raid/mps/mps_mapping.c

481

u32 map_idx, max_idx = sc->max_devices;

sys/dev/raid/mps/mps_mapping.c

506

_mapping_get_dpm_idx_from_id(struct mps_softc *sc, u64 id, u32 phy_bits)

sys/dev/raid/mps/mps_mapping.c

534

static u32

sys/dev/raid/mps/mps_mapping.c

558

_mapping_update_ir_missing_cnt(struct mps_softc *sc, u32 map_idx,

sys/dev/raid/mps/mps_mapping.c

648

u32 i;

sys/dev/raid/mps/mps_mapping.c

689

u32 map_idx;

sys/dev/raid/mps/mps_mapping.c

743

static u32

sys/dev/raid/mps/mps_mapping.c

748

u32 skip_count, end_of_table, map_idx, enc_idx;

sys/dev/raid/mps/mps_mapping.c

750

u32 start_idx = MPS_MAPTABLE_BAD_IDX;

sys/dev/raid/mps/mps_mapping.c

888

u32 map_idx, index, device_info;

sys/dev/raid/mps/mps_mapping.h

69

u64 *sas_address, u16 handle, u32 device_info);

sys/dev/raid/mps/mps_sas_lsi.c

108

static u32 event_count;

sys/dev/raid/mps/mps_sas_lsi.c

117

u32 devinfo);

sys/dev/raid/mps/mps_sas_lsi.c

119

u64 *sas_address, u16 handle, u32 device_info);

sys/dev/raid/mps/mps_sas_lsi.c

387

u32 state;

sys/dev/raid/mps/mps_sas_lsi.c

589

u32 device_info, parent_devinfo = 0;

sys/dev/raid/mps/mps_sas_lsi.c

686

u64 *sas_address, u16 handle, u32 device_info)

sys/dev/raid/mps/mps_sas_lsi.c

690

u32 *bufferptr;

sys/dev/raid/mps/mps_sas_lsi.c

694

u32 ioc_status;

sys/dev/raid/mps/mps_sas_lsi.c

730

bufferptr = (u32 *)buffer;

sys/dev/raid/mps/mps_sas_lsi.c

760

Mpi2SataPassthroughReply_t *mpi_reply, char *id_buffer, int sz, u32 devinfo)

sys/dev/raid/mps/mps_sas_lsi.c

878

u32 start_idx, end_idx;

sys/dev/raid/mps/mps_sas_lsi.c

92

u32 high;

sys/dev/raid/mps/mps_sas_lsi.c

93

u32 low;

sys/dev/raid/mps/mpsvar.h

137

u32 device_info;

sys/dev/raid/mps/mpsvar.h

138

u32 phy_bits;

sys/dev/raid/mps/mpsvar.h

166

u32 start_index;

sys/dev/raid/mps/mpsvar.h

167

u32 phy_bits;

sys/dev/raid/mps/mpsvar.h

713

*mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address);

sys/dev/raid/mps/mpsvar.h

718

Mpi2SasDevicePage0_t *, u32 , u16 );

sys/dev/raid/mps/mpsvar.h

722

Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form,

sys/dev/raid/mps/mpsvar.h

728

u32 page_address);

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

115

ena_addr->mem_addr_low = (u32)addr;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1158

io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1335

io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1340

(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1345

(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1455

int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1498

u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1523

u32 ver;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1524

u32 ctrl_ver;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1525

u32 ctrl_ver_masked;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1609

u32 mask_value = 0;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

166

u32 addr_low, addr_high, aenq_caps;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1668

u32 addr_low, addr_high;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1682

u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1725

admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1993

ENA_REG_WRITE32(dev->bus, (u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2002

u32 func_queue)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2020

u32 stat, timeout, cap, reset_val;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2123

u32 len)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2279

const u8 *key, u16 key_len, u32 init_val)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2593

int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2597

u32 tbl_size;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2677

u32 debug_area_size)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

272

comp_ctx->comp_size = (u32)comp_size_in_bytes;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2781

u32 tx_coalesce_usecs)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2795

u32 rx_coalesce_usecs)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

70

#define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

71

#define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

712

static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

717

u32 mmio_read_reg, ret, i;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

719

u32 timeout = mmio_read->reg_read_to;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

865

static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

868

u32 val, i;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

892

u32 feature_mask = 1 << feature_id;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

906

u32 control_buff_size)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

93

u32 comp_size;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

1077

u32 rx_delay_interval,

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

1078

u32 tx_delay_interval,

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

1112

u32 len);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

1115

u32 funct_queue);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

150

u32 __iomem *unmask_reg;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

153

u32 __iomem *cq_head_db_reg;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

156

u32 __iomem *numa_node_cfg_reg;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

161

u32 msix_vector;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

201

u32 __iomem *db_addr;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

207

u32 msix_vector;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

220

u32 tx_max_header_size;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

240

u32 __iomem *db_addr;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

249

u32 aborted_cmd;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

250

u32 submitted_cmd;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

251

u32 completed_cmd;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

252

u32 out_of_space;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

253

u32 no_completion;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

262

u32 completion_timeout;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

299

u32 reg_read_to; /* in us */

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

319

u32 hash_init_val;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

333

u32 debug_area_size;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

353

u32 tx_max_header_size;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

360

u32 supported_features;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

361

u32 dma_addr_bits;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

366

u32 intr_moder_tx_interval;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

385

u32 msix_vector;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

615

int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

687

const u8 *key, u16 key_len, u32 init_val);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

810

int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

826

u32 debug_area_size);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

924

u32 tx_coalesce_usecs);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

934

u32 rx_coalesce_usecs);

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

239

u32 last = 0;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

491

desc->buff_addr_lo = (u32)ena_bufs->paddr;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

584

desc->buff_addr_lo = (u32)ena_buf->paddr;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

70

u32 offset;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

85

u32 dst_offset;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

76

u32 hash;

sys/dev/virtual/amazon/ena/ena.c

2645

u32 mss;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

467

static __inline u16 Lo16(u32 val)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

472

static __inline u16 Hi16(u32 val)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

530

static void tkip_mixing_phase1(u16 *TTAK, const u8 *TK, const u8 *TA, u32 IV32)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

605

u32 i, j, k, crc;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

665

u32 i, j, k, crc;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

727

static __inline u32 rotl(u32 val, int bits)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

733

static __inline u32 rotr(u32 val, int bits)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

739

static __inline u32 xswap(u32 val)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

758

static __inline u32 get_le32_split(u8 b0, u8 b1, u8 b2, u8 b3)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

763

static __inline u32 get_le32(const u8 *p)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

769

static __inline void put_le32(u8 *p, u32 v)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

820

u32 l, r;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

952

(u32)(key->wk_keytsc >> 16));

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

972

u32 iv32;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

981

iv32 = (u32) (ctx->rx_rsc >> 16);

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

984

if (iv32 != (u32)(key->wk_keyrsc[tid] >> 16) || !ctx->rx_phase1_done) {

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

995

if (iv32 != (u32)(key->wk_keyrsc[tid] >> 16)) {

sys/vfs/hammer2/xxhash/xxhash.c

168

typedef union { U32 u32; U64 u64; } __attribute__((packed)) unalign;

sys/vfs/hammer2/xxhash/xxhash.c

170

static U32 XXH_read32(const void* ptr) { return ((const unalign*)ptr)->u32; }