sys/arch/arm64/dev/apldc.c

235

HSET4(sc, DC_IRQ_MASK, 1 << ih->ih_irq);

sys/arch/arm64/dev/aplintc.c

294

HSET4(sc, AIC2_CONFIG, AIC2_CONFIG_ENABLE);

sys/arch/arm64/dev/aplmca.c

505

HSET4(sc, MCA_STATUS(ad->ad_cluster), MCA_STATUS_MCLK_EN);

sys/arch/arm64/dev/aplmca.c

506

HSET4(sc, MCA_SYNCGEN_STATUS(ad->ad_cluster),

sys/arch/arm64/dev/aplmca.c

508

HSET4(sc, MCA_SERDES_STATUS(ad->ad_cluster, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplnco.c

162

HSET4(sc, NCO_CTRL(idx), NCO_CTRL_ENABLE);

sys/arch/arm64/dev/aplpinctrl.c

266

HSET4(sc, GPIO_PIN(pin), GPIO_PIN_DATA);

sys/arch/arm64/dev/aplspi.c

158

HSET4(sc, SPI_PINCFG, SPI_PINCFG_KEEP_CS);

sys/arch/arm64/dev/rpiclock.c

299

HSET4(sc, base + PLL_SYS_FBDIV_INT - PLL_SYS_PWR,

sys/arch/arm64/dev/rpiclock.c

305

HSET4(sc, base, 1 << PLL_CS_REFDIV_SHIFT);

sys/arch/arm64/dev/rpiclock.c

582

HSET4(sc, clk->ctrl_reg, CLK_CTRL_ENABLE);

sys/arch/arm64/dev/rpipwm.c

174

HSET4(sc, CHAN_CTRL(chan), CHAN_CTRL_INVERT);

sys/arch/arm64/dev/rpipwm.c

179

HSET4(sc, GLOBAL_CTRL, GLOBAL_CTRL_CHAN_EN(chan));

sys/arch/arm64/dev/rpipwm.c

184

HSET4(sc, GLOBAL_CTRL, GLOBAL_CTRL_SET_UPDATE);

sys/arch/armv7/exynos/exiic.c

267

HSET4(sc, I2C_CON, I2C_CON_ACK);

sys/arch/armv7/imx/imxtemp.c

189

HSET4(sc, TEMPMON_TEMPSENSE0, TEMPMON_TEMPSENSE0_MEASURE_TEMP);

sys/arch/armv7/imx/imxtemp.c

206

HSET4(sc, TEMPMON_TEMPSENSE0, TEMPMON_TEMPSENSE0_POWER_DOWN);

sys/arch/armv7/marvell/mvagc.c

112

HSET4(sc, 0, (1 << id));

sys/arch/armv7/marvell/mvodog.c

102

HSET4(sc, sc->sc_rstout_mask_ioh, 0, RSTOUT_MASK);

sys/arch/armv7/omap/amdisplay.c

335

HSET4(sc, LCD_CLKC_ENABLE, LCD_CLKC_ENABLE_DMA_CLK_EN

sys/arch/armv7/omap/amdisplay.c

340

HSET4(sc, LCD_CLKC_RESET, LCD_CLKC_RESET_MAIN_RST);

sys/arch/armv7/omap/amdisplay.c

367

HSET4(sc, LCD_RASTER_CTRL, LCD_RASTER_CTRL_LCDEN);

sys/arch/armv7/omap/amdisplay.c

409

HSET4(sc, LCD_RASTER_CTRL, 0x02 << LCD_RASTER_CTRL_PALMODE_SHAMT);

sys/arch/armv7/omap/amdisplay.c

410

HSET4(sc, LCD_RASTER_CTRL, LCD_RASTER_CTRL_LCDEN);

sys/arch/armv7/omap/amdisplay.c

440

HSET4(sc, LCD_CLKC_RESET, LCD_CLKC_RESET_MAIN_RST);

sys/arch/armv7/omap/amdisplay.c

443

HSET4(sc, LCD_RASTER_CTRL, LCD_RASTER_CTRL_LCDEN);

sys/arch/armv7/omap/ommmc.c

1116

HSET4(sc, MMCHS_SYSCTL, mask);

sys/arch/armv7/omap/ommmc.c

354

HSET4(sc, MMCHS_CAPA, MMCHS_CAPA_VS18 | MMCHS_CAPA_VS30);

sys/arch/armv7/omap/ommmc.c

544

HSET4(sc, MMCHS_CON, MMCHS_CON_INIT);

sys/arch/armv7/omap/ommmc.c

555

HSET4(sc, MMCHS_SYSCTL, 0xe << MMCHS_SYSCTL_DTO_SH);

sys/arch/armv7/omap/ommmc.c

666

HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP);

sys/arch/armv7/omap/ommmc.c

752

HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE);

sys/arch/armv7/omap/ommmc.c

759

HSET4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_ICE);

sys/arch/armv7/omap/ommmc.c

773

HSET4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN);

sys/arch/armv7/omap/ommmc.c

791

HSET4(sc, MMCHS_CON, MMCHS_CON_DW8);

sys/arch/armv7/omap/ommmc.c

796

HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);

sys/arch/armv7/omap/ommmc.c

812

HSET4(sc, MMCHS_IE, MMCHS_STAT_CIRQ);

sys/arch/armv7/omap/ommmc.c

813

HSET4(sc, MMCHS_ISE, MMCHS_STAT_CIRQ);

sys/arch/armv7/omap/omrng.c

144

HSET4(sc, RNG_FRODETUNE, detune);

sys/arch/riscv64/dev/sfgpio.c

168

HSET4(sc, GPIO_OUTPUT_EN, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

171

HSET4(sc, GPIO_INPUT_EN, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

208

HSET4(sc, GPIO_OUTPUT_VAL, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

224

HSET4(sc, GPIO_RISE_IP, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

227

HSET4(sc, GPIO_FALL_IP, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

230

HSET4(sc, GPIO_HIGH_IP, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

233

HSET4(sc, GPIO_LOW_IP, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

269

HSET4(sc, GPIO_INPUT_EN, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

273

HSET4(sc, GPIO_RISE_IP, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

274

HSET4(sc, GPIO_RISE_IE, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

277

HSET4(sc, GPIO_FALL_IP, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

278

HSET4(sc, GPIO_FALL_IE, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

281

HSET4(sc, GPIO_HIGH_IP, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

282

HSET4(sc, GPIO_HIGH_IE, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

285

HSET4(sc, GPIO_LOW_IP, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

286

HSET4(sc, GPIO_LOW_IE, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

316

HSET4(sc, GPIO_RISE_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

319

HSET4(sc, GPIO_FALL_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

322

HSET4(sc, GPIO_HIGH_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

325

HSET4(sc, GPIO_LOW_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfuart.c

354

HSET4(sc, UART_IE, UART_IE_TXWM);

sys/arch/riscv64/dev/sfuart.c

409

HSET4(sc, UART_IE, UART_IE_RXWM);

sys/arch/riscv64/dev/smtclock.c

413

HSET4(sc, clock->reg, (1U << clock->bit));

sys/arch/riscv64/dev/smtgpio.c

134

HSET4(sc, offset + GPIO_PDR, (1U << pin));

sys/arch/riscv64/dev/smtiic.c

148

HSET4(sc, ICR, ICR_SCLE | ICR_GCD);

sys/arch/riscv64/dev/smtiic.c

150

HSET4(sc, ICR, ICR_MODE_FAST);

sys/arch/riscv64/dev/smtiic.c

189

HSET4(sc, ICR, ICR_IUE);

sys/arch/riscv64/dev/smtiic.c

206

HSET4(sc, ICR, ICR_START);

sys/arch/riscv64/dev/smtiic.c

215

HSET4(sc, ICR, ICR_STOP);

sys/arch/riscv64/dev/smtiic.c

234

HSET4(sc, ICR, ICR_START);

sys/arch/riscv64/dev/smtiic.c

236

HSET4(sc, ICR, ICR_TB);

sys/arch/riscv64/dev/smtiic.c

258

HSET4(sc, ICR, ICR_STOP);

sys/arch/riscv64/dev/smtiic.c

260

HSET4(sc, ICR, ICR_ACKNAK);

sys/arch/riscv64/dev/smtiic.c

262

HSET4(sc, ICR, ICR_TB);

sys/arch/riscv64/dev/smtiic.c

281

HSET4(sc, ICR, ICR_STOP);

sys/arch/riscv64/dev/smtiic.c

283

HSET4(sc, ICR, ICR_TB);

sys/arch/riscv64/dev/stfclock.c

1109

HSET4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

1129

HSET4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

483

HSET4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

618

HSET4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

638

HSET4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

833

HSET4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

853

HSET4(sc, offset, bits);

sys/dev/acpi/dwgpio.c

226

HSET4(sc, GPIO_SWPORTA_DR, (1 << pin));

sys/dev/acpi/dwgpio.c

245

HSET4(sc, GPIO_INTTYPE_LEVEL, 1 << pin);

sys/dev/acpi/dwgpio.c

249

HSET4(sc, GPIO_INT_POLARITY, 1 << pin);

sys/dev/acpi/dwgpio.c

254

HSET4(sc, GPIO_INTEN, 1 << pin);

sys/dev/acpi/qcgpio.c

463

HSET4(sc, off + TLMM_GPIO_IN_OUT(pin),

sys/dev/acpi/qcgpio.c

531

HSET4(sc, off + TLMM_GPIO_INTR_CFG(pin),

sys/dev/fdt/amlclock.c

316

HSET4(sc, offset, HHI_SYS_CPU_CLK_DYN_ENABLE);

sys/dev/fdt/amlclock.c

325

HSET4(sc, offset, HHI_SYS_CPU_CLK_POSTMUX0);

sys/dev/fdt/amlclock.c

347

HSET4(sc, offset, HHI_SYS_CPU_CLK_DYN_ENABLE);

sys/dev/fdt/amlclock.c

356

HSET4(sc, offset, HHI_SYS_CPU_CLK_POSTMUX1);

sys/dev/fdt/amlclock.c

392

HSET4(sc, offset, HHI_SYS_DPLL_RESET);

sys/dev/fdt/amlclock.c

403

HSET4(sc, offset, HHI_SYS_DPLL_RESET);

sys/dev/fdt/amlclock.c

404

HSET4(sc, offset, HHI_SYS_DPLL_EN);

sys/dev/fdt/amlclock.c

607

HSET4(sc, sc->sc_gates[idx].reg,

sys/dev/fdt/amldwusb.c

180

HSET4(sc, USB_R5, USB_R5_ID_DIG_EN_0);

sys/dev/fdt/amldwusb.c

181

HSET4(sc, USB_R5, USB_R5_ID_DIG_EN_1);

sys/dev/fdt/amldwusb.c

206

HSET4(sc, U2P_R0(i), U2P_R0_POWER_ON_RESET);

sys/dev/fdt/amldwusb.c

209

HSET4(sc, U2P_R0(i), U2P_R0_HOST_DEVICE);

sys/dev/fdt/amldwusb.c

240

HSET4(sc, USB_R1, USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);

sys/dev/fdt/amliic.c

233

HSET4(sc, I2C_M_CONTROL, I2C_M_CONTROL_START);

sys/dev/fdt/amlmmc.c

534

HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK);

sys/dev/fdt/amlmmc.c

537

HSET4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR);

sys/dev/fdt/amlpwm.c

220

HSET4(sc, PWM_MISC_REG_AB, (idx == 0) ? PWM_A_EN : PWM_B_EN);

sys/dev/fdt/amlreset.c

109

HSET4(sc, RESET0_LEVEL + bank * 4, (1 << bit));

sys/dev/fdt/amltemp.c

158

HSET4(sc, TS_CFG_REG1, TS_CFG_REG1_ANA_EN_VCM |

sys/dev/fdt/amluart.c

234

HSET4(sc, UART_CONTROL, UART_CONTROL_CLEAR_ERROR);

sys/dev/fdt/amluart.c

406

HSET4(sc, UART_CONTROL,

sys/dev/fdt/bcm2711_pcie.c

549

HSET4(sc, PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT);

sys/dev/fdt/bcmstbgpio.c

171

HSET4(sc, GIO_IODIR(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

208

HSET4(sc, GIO_DATA(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

374

HSET4(sc, GIO_MASK(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

387

HSET4(sc, GIO_MASK(bank), 1U << pin);

sys/dev/fdt/bcmstbrescal.c

114

HSET4(sc, RESCAL_START, RESCAL_START_BIT);

sys/dev/fdt/dwdog.c

112

HSET4(sc, WDT_CR, WDT_CR_WDT_EN);

sys/dev/fdt/dwmmc.c

393

HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_ALL_RESET);

sys/dev/fdt/dwmmc.c

405

HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);

sys/dev/fdt/dwmmc.c

579

HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO);

sys/dev/fdt/dwmmc.c

589

HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO);

sys/dev/fdt/dwmmc.c

648

HSET4(sc, SDMMC_PWREN, 1);

sys/dev/fdt/dwmmc.c

726

HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT);

sys/dev/fdt/dwmmc.c

730

HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);

sys/dev/fdt/dwmmc.c

761

HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR);

sys/dev/fdt/dwmmc.c

771

HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC |

sys/dev/fdt/dwmmc.c

773

HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_FB | SDMMC_BMOD_DE);

sys/dev/fdt/dwmmc.c

849

HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR);

sys/dev/fdt/dwmmc.c

958

HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_FIFO_RESET);

sys/dev/fdt/dwpcie.c

1434

HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);

sys/dev/fdt/dwpcie.c

1462

HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);

sys/dev/fdt/dwpcie.c

2078

HSET4(sc, PCIE_MSI_INTR_MASK(dm->dm_vec / 32),

sys/dev/fdt/dwpcie.c

644

HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);

sys/dev/fdt/dwpcie.c

656

HSET4(sc, PPB_REG_IOSTATUS,

sys/dev/fdt/if_fec.c

354

HSET4(sc, ENET_ECR, ENET_ECR_RESET);

sys/dev/fdt/if_fec.c

634

HSET4(sc, ENET_ECR, ENET_ECR_RESET);

sys/dev/fdt/if_fec.c

709

HSET4(sc, ENET_ECR, ENET_ECR_EN1588);

sys/dev/fdt/if_fec.c

747

HSET4(sc, ENET_ECR, ENET_ECR_RESET);

sys/dev/fdt/imxccm.c

1487

HSET4(sc, reg, 0x3 << (2 * pos));

sys/dev/fdt/imxccm.c

386

HSET4(sc, CCM_CCSR, CCM_CCSR_PLL1_SW_CLK_SEL);

sys/dev/fdt/imxccm.c

390

HSET4(sc, CCM_CCSR, CCM_CCSR_STEP_SEL);

sys/dev/fdt/imxccm.c

392

HSET4(sc, CCM_CCSR, CCM_CCSR_PLL1_SW_CLK_SEL);

sys/dev/fdt/imxesdhc.c

1122

HSET4(sc, SDHC_SYS_CTRL, mask);

sys/dev/fdt/imxesdhc.c

1150

HSET4(sc, SDHC_INT_SIGNAL_EN,

sys/dev/fdt/imxesdhc.c

584

HSET4(sc, SDHC_SYS_CTRL, 0xe << SDHC_SYS_CTRL_DTOCV_SHIFT);

sys/dev/fdt/imxesdhc.c

719

HSET4(sc, SDHC_SYS_CTRL,

sys/dev/fdt/imxesdhc.c

763

HSET4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT);

sys/dev/fdt/imxesdhc.c

764

HSET4(sc, SDHC_INT_SIGNAL_EN, SDHC_INT_STATUS_CINT);

sys/dev/fdt/imxesdhc.c

776

HSET4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT);

sys/dev/fdt/imxesdhc.c

978

HSET4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_ADMA2);

sys/dev/fdt/imxspi.c

358

HSET4(sc, SPI_CONREG, SPI_CONREG_XCH);

sys/dev/fdt/imxtmu.c

127

HSET4(sc, TMU_MM_TER, TMU_MM_TER_EN);

sys/dev/fdt/mvgpio.c

112

HSET4(sc, GPIO_DOUTEN, (1 << pin));

sys/dev/fdt/mvgpio.c

149

HSET4(sc, GPIO_DOUT, (1 << pin));

sys/dev/fdt/mviic.c

146

HSET4(sc, ICR, ICR_MODE_FAST);

sys/dev/fdt/mviic.c

149

HSET4(sc, ICR, ICR_ENABLE);

sys/dev/fdt/mviic.c

216

HSET4(sc, ICR, ICR_START);

sys/dev/fdt/mviic.c

225

HSET4(sc, ICR, ICR_STOP);

sys/dev/fdt/mviic.c

243

HSET4(sc, ICR, ICR_START);

sys/dev/fdt/mviic.c

245

HSET4(sc, ICR, ICR_TX_BYTE);

sys/dev/fdt/mviic.c

267

HSET4(sc, ICR, ICR_STOP);

sys/dev/fdt/mviic.c

269

HSET4(sc, ICR, ICR_NAK);

sys/dev/fdt/mviic.c

271

HSET4(sc, ICR, ICR_TX_BYTE);

sys/dev/fdt/mviic.c

289

HSET4(sc, ICR, ICR_STOP);

sys/dev/fdt/mviic.c

291

HSET4(sc, ICR, ICR_TX_BYTE);

sys/dev/fdt/mvkpcie.c

381

HSET4(sc, PCIE_CORE_CTRL0, PCIE_CORE_CTRL0_IS_RC);

sys/dev/fdt/mvkpcie.c

411

HSET4(sc, PCIE_CORE_CTRL2, PCIE_CORE_CTRL2_MSI_ENABLE);

sys/dev/fdt/mvkpcie.c

424

HSET4(sc, PCIE_CORE_CTRL2, PCIE_CORE_CTRL2_OB_WIN_ENABLE);

sys/dev/fdt/mvkpcie.c

425

HSET4(sc, PIO_CTRL, PIO_CTRL_ADDR_WIN_DISABLE);

sys/dev/fdt/mvkpcie.c

429

HSET4(sc, PCIE_CORE_CTRL0, PCIE_CORE_CTRL0_LINK_TRAINING);

sys/dev/fdt/mvkpcie.c

430

HSET4(sc, PCIE_LINK_CTRL_STAT, PCIE_LINK_CTRL_STAT_LINK_TRAINING);

sys/dev/fdt/mvkpcie.c

446

HSET4(sc, PCIE_CMD, PCI_COMMAND_IO_ENABLE |

sys/dev/fdt/mvkpcie.c

966

HSET4(sc, PCIE_CORE_ISR1_MASK, PCIE_CORE_ISR1_MASK_INTX(ih->ih_irq));

sys/dev/fdt/mvpinctrl.c

289

HSET4(sc, GPIO_DIRECTION, (1 << pin));

sys/dev/fdt/mvpinctrl.c

327

HSET4(sc, GPIO_OUTPUT, (1 << pin));

sys/dev/fdt/mvrng.c

111

HSET4(sc, RNG_CONTROL, RNG_CONTROL_TRNG_EN);

sys/dev/fdt/mvrng.c

131

HSET4(sc, RNG_FRODETUNE, detune);

sys/dev/fdt/mvspi.c

134

HSET4(sc, SPI_CFG, SPI_CFG_FIFO_FLUSH);

sys/dev/fdt/mvspi.c

184

HSET4(sc, SPI_CFG, mvspi_clkdiv(sc, conf->sc_freq));

sys/dev/fdt/mvspi.c

187

HSET4(sc, SPI_CFG, SPI_CFG_CPHA);

sys/dev/fdt/mvspi.c

189

HSET4(sc, SPI_CFG, SPI_CFG_CPOL);

sys/dev/fdt/mvspi.c

228

HSET4(sc, SPI_CTRL, SPI_CTRL_CS(cs));

sys/dev/fdt/mvuart.c

335

HSET4(sc, MVUART_CTRL, MVUART_CTRL_TX_RDY_INT);

sys/dev/fdt/mvuart.c

425

HSET4(sc, MVUART_CTRL, MVUART_CTRL_RX_RDY_INT);

sys/dev/fdt/qcgpio_fdt.c

191

HSET4(sc, TLMM_GPIO_INTR_CFG(pin),

sys/dev/fdt/qcgpio_fdt.c

210

HSET4(sc, TLMM_GPIO_CFG(pin), TLMM_GPIO_CFG_OUT_EN);

sys/dev/fdt/qcgpio_fdt.c

248

HSET4(sc, TLMM_GPIO_IN_OUT(pin),

sys/dev/fdt/qcgpio_fdt.c

346

HSET4(sc, TLMM_GPIO_INTR_CFG(pin),

sys/dev/fdt/qcpdc.c

207

HSET4(sc, PDC_INTR_ENABLE(pin), PDC_INTR_ENABLE_BIT(pin));

sys/dev/fdt/rkgpio.c

222

HSET4(sc, GPIO_SWPORTA_DDR, (1 << pin));

sys/dev/fdt/rkgpio.c

270

HSET4(sc, GPIO_SWPORTA_DR, (1 << pin));

sys/dev/fdt/rkgpio.c

389

HSET4(sc, GPIO_INTTYPE_LEVEL, 1 << irqno);

sys/dev/fdt/rkgpio.c

390

HSET4(sc, GPIO_INT_POLARITY, 1 << irqno);

sys/dev/fdt/rkgpio.c

393

HSET4(sc, GPIO_INTTYPE_LEVEL, 1 << irqno);

sys/dev/fdt/rkgpio.c

398

HSET4(sc, GPIO_INT_POLARITY, 1 << irqno);

sys/dev/fdt/rkgpio.c

436

HSET4(sc, GPIO_INTMASK, 1 << ih->ih_irq);

sys/dev/fdt/rkgpio.c

515

HSET4(sc, GPIO_INTMASK, 1 << ih->ih_irq);

sys/dev/fdt/rkiic.c

186

HSET4(sc, RKI2C_CON, RKI2C_CON_I2C_EN);

sys/dev/fdt/rkiic.c

204

HSET4(sc, RKI2C_IPD, RKI2C_IPD_START);

sys/dev/fdt/rkiic.c

205

HSET4(sc, RKI2C_CON, RKI2C_CON_START);

sys/dev/fdt/rkiic.c

223

HSET4(sc, RKI2C_IPD, RKI2C_IPD_STOP);

sys/dev/fdt/rkiic.c

224

HSET4(sc, RKI2C_CON, RKI2C_CON_STOP);

sys/dev/fdt/rkiic.c

296

HSET4(sc, RKI2C_CON, RKI2C_CON_NAK);

sys/dev/fdt/rkpwm.c

175

HSET4(sc, PWM_V2_CTRL, PWM_V2_CTRL_INACTIVE_POSITIVE);

sys/dev/fdt/rkpwm.c

177

HSET4(sc, PWM_V2_CTRL, PWM_V2_CTRL_DUTY_POSITIVE);

sys/dev/fdt/rkpwm.c

179

HSET4(sc, PWM_V2_CTRL, PWM_V2_CTRL_ENABLE | PWM_V2_CTRL_CONTINUOUS);

sys/dev/fdt/rkspi.c

280

HSET4(sc, SPI_CTRLR0, SPI_CTRLR0_XFM_RO);

sys/dev/fdt/rkspi.c

283

HSET4(sc, SPI_SER, SPI_SER_CS(sc->sc_cs));

sys/dev/fdt/rkusbdpphy.c

328

HSET4(sc, USBDP_COMBO_PHY_REG(0xe3), USBDP_COMBO_PHY_INIT_RSTN);

sys/dev/fdt/sxirintc.c

105

HSET4(sc, RINTC_IRQ_ENABLE, RINTC_IRQ_ENABLE_NMI);

sys/dev/fdt/sxirsb.c

233

HSET4(sc, RSB_CTRL, RSB_CTRL_START_TRANS);

sys/dev/fdt/sxirsb.c

284

HSET4(sc, RSB_CTRL, RSB_CTRL_START_TRANS);

sys/dev/ic/qcuart.c

295

HSET4(sc, GENI_M_IRQ_EN, GENI_M_IRQ_CMD_DONE);

sys/dev/ic/qcuart.c

348

HSET4(sc, GENI_S_IRQ_EN,

sys/dev/ic/qcuart.c

350

HSET4(sc, GENI_M_IRQ_EN, GENI_M_IRQ_SEC_IRQ);