sys/arch/arm64/dev/apldc.c

244

HCLR4(sc, DC_IRQ_MASK, 1 << ih->ih_irq);

sys/arch/arm64/dev/aplmca.c

222

HCLR4(sc, MCA_SERDES_STATUS(i, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplmca.c

224

HCLR4(sc, MCA_SYNCGEN_STATUS(i), MCA_SYNCGEN_STATUS_EN);

sys/arch/arm64/dev/aplmca.c

225

HCLR4(sc, MCA_STATUS(i), MCA_STATUS_MCLK_EN);

sys/arch/arm64/dev/aplmca.c

539

HCLR4(sc, MCA_SERDES_STATUS(ad->ad_cluster, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplmca.c

541

HCLR4(sc, MCA_SYNCGEN_STATUS(ad->ad_cluster),

sys/arch/arm64/dev/aplmca.c

543

HCLR4(sc, MCA_STATUS(ad->ad_cluster), MCA_STATUS_MCLK_EN);

sys/arch/arm64/dev/aplnco.c

164

HCLR4(sc, NCO_CTRL(idx), NCO_CTRL_ENABLE);

sys/arch/arm64/dev/aplpinctrl.c

268

HCLR4(sc, GPIO_PIN(pin), GPIO_PIN_DATA);

sys/arch/arm64/dev/aplspi.c

156

HCLR4(sc, SPI_SHIFTCFG, SPI_SHIFTCFG_OVERRIDE_CS);

sys/arch/arm64/dev/aplspi.c

157

HCLR4(sc, SPI_PINCFG, SPI_PINCFG_CS_IDLE_VAL);

sys/arch/arm64/dev/rpiclock.c

296

HCLR4(sc, base + PLL_SYS_FBDIV_INT - PLL_SYS_PWR,

sys/arch/arm64/dev/rpiclock.c

584

HCLR4(sc, clk->ctrl_reg, CLK_CTRL_ENABLE);

sys/arch/arm64/dev/rpipwm.c

176

HCLR4(sc, CHAN_CTRL(chan), CHAN_CTRL_INVERT);

sys/arch/arm64/dev/rpipwm.c

181

HCLR4(sc, GLOBAL_CTRL, GLOBAL_CTRL_CHAN_EN(chan));

sys/arch/armv7/exynos/exiic.c

313

HCLR4(sc, I2C_CON, I2C_CON_ACK);

sys/arch/armv7/exynos/exiic.c

342

HCLR4(sc, I2C_CON, I2C_CON_INTPENDING);

sys/arch/armv7/imx/imxtemp.c

188

HCLR4(sc, TEMPMON_TEMPSENSE0, TEMPMON_TEMPSENSE0_POWER_DOWN);

sys/arch/armv7/imx/imxtemp.c

205

HCLR4(sc, TEMPMON_TEMPSENSE0, TEMPMON_TEMPSENSE0_MEASURE_TEMP);

sys/arch/armv7/marvell/mvagc.c

114

HCLR4(sc, 0, (1 << id));

sys/arch/armv7/marvell/mvodog.c

103

HCLR4(sc, sc->sc_rstout_ioh, 0, RSTOUT_ENABLE);

sys/arch/armv7/marvell/mvodog.c

104

HCLR4(sc, sc->sc_reg_ioh, 0, WDT_ENABLE);

sys/arch/armv7/omap/amdisplay.c

278

HCLR4(sc, LCD_RASTER_CTRL, LCD_RASTER_CTRL_LCDEN);

sys/arch/armv7/omap/amdisplay.c

342

HCLR4(sc, LCD_CLKC_RESET, LCD_CLKC_RESET_MAIN_RST);

sys/arch/armv7/omap/amdisplay.c

406

HCLR4(sc, LCD_RASTER_CTRL, LCD_RASTER_CTRL_LCDEN);

sys/arch/armv7/omap/amdisplay.c

408

HCLR4(sc, LCD_RASTER_CTRL, LCD_RASTER_CTRL_PALMODE);

sys/arch/armv7/omap/amdisplay.c

442

HCLR4(sc, LCD_CLKC_RESET, LCD_CLKC_RESET_MAIN_RST);

sys/arch/armv7/omap/ommmc.c

1231

HCLR4(sc, MMCHS_STAT, MMCHS_STAT_CIRQ);

sys/arch/armv7/omap/ommmc.c

549

HCLR4(sc, MMCHS_CON, MMCHS_CON_INIT);

sys/arch/armv7/omap/ommmc.c

569

HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8);

sys/arch/armv7/omap/ommmc.c

570

HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);

sys/arch/armv7/omap/ommmc.c

631

HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP);

sys/arch/armv7/omap/ommmc.c

734

HCLR4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN);

sys/arch/armv7/omap/ommmc.c

754

HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE);

sys/arch/armv7/omap/ommmc.c

793

HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8);

sys/arch/armv7/omap/ommmc.c

798

HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);

sys/arch/armv7/omap/ommmc.c

815

HCLR4(sc, MMCHS_IE, MMCHS_STAT_CIRQ);

sys/arch/armv7/omap/ommmc.c

816

HCLR4(sc, MMCHS_ISE, MMCHS_STAT_CIRQ);

sys/arch/riscv64/dev/sfgpio.c

169

HCLR4(sc, GPIO_INPUT_EN, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

172

HCLR4(sc, GPIO_OUTPUT_EN, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

210

HCLR4(sc, GPIO_OUTPUT_VAL, (1 << pin));

sys/arch/riscv64/dev/sfgpio.c

338

HCLR4(sc, GPIO_RISE_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

341

HCLR4(sc, GPIO_FALL_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

344

HCLR4(sc, GPIO_HIGH_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfgpio.c

347

HCLR4(sc, GPIO_LOW_IE, (1 << ih->ih_pin));

sys/arch/riscv64/dev/sfuart.c

344

HCLR4(sc, UART_IE, UART_IE_TXWM);

sys/arch/riscv64/dev/sfuart.c

468

HCLR4(sc, UART_IE, UART_IE_TXWM | UART_IE_RXWM);

sys/arch/riscv64/dev/smtclock.c

415

HCLR4(sc, clock->reg, (1U << clock->bit));

sys/arch/riscv64/dev/smtgpio.c

136

HCLR4(sc, offset + GPIO_PDR, (1U << pin));

sys/arch/riscv64/dev/smtiic.c

198

HCLR4(sc, ICR, ICR_IUE);

sys/arch/riscv64/dev/smtiic.c

227

HCLR4(sc, ICR, ICR_START);

sys/arch/riscv64/dev/smtiic.c

228

HCLR4(sc, ICR, ICR_STOP);

sys/arch/riscv64/dev/smtiic.c

229

HCLR4(sc, ICR, ICR_ACKNAK);

sys/arch/riscv64/dev/smtiic.c

254

HCLR4(sc, ICR, ICR_START);

sys/arch/riscv64/dev/smtiic.c

255

HCLR4(sc, ICR, ICR_STOP);

sys/arch/riscv64/dev/smtiic.c

256

HCLR4(sc, ICR, ICR_ACKNAK);

sys/arch/riscv64/dev/smtiic.c

276

HCLR4(sc, ICR, ICR_START);

sys/arch/riscv64/dev/smtiic.c

277

HCLR4(sc, ICR, ICR_STOP);

sys/arch/riscv64/dev/smtiic.c

278

HCLR4(sc, ICR, ICR_ACKNAK);

sys/arch/riscv64/dev/stfclock.c

1111

HCLR4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

1131

HCLR4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

485

HCLR4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

620

HCLR4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

640

HCLR4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

835

HCLR4(sc, idx * 4, 1U << 31);

sys/arch/riscv64/dev/stfclock.c

855

HCLR4(sc, offset, bits);

sys/dev/acpi/dwgpio.c

228

HCLR4(sc, GPIO_SWPORTA_DR, (1 << pin));

sys/dev/acpi/dwgpio.c

247

HCLR4(sc, GPIO_INTTYPE_LEVEL, 1 << pin);

sys/dev/acpi/dwgpio.c

251

HCLR4(sc, GPIO_INT_POLARITY, 1 << pin);

sys/dev/acpi/dwgpio.c

253

HCLR4(sc, GPIO_SWPORTA_DDR, 1 << pin);

sys/dev/acpi/dwgpio.c

255

HCLR4(sc, GPIO_INTMASK, 1 << pin);

sys/dev/acpi/qcgpio.c

466

HCLR4(sc, off + TLMM_GPIO_IN_OUT(pin),

sys/dev/acpi/qcgpio.c

545

HCLR4(sc, off + TLMM_GPIO_INTR_CFG(pin),

sys/dev/fdt/amlclock.c

327

HCLR4(sc, offset, HHI_SYS_CPU_CLK_POSTMUX0);

sys/dev/fdt/amlclock.c

358

HCLR4(sc, offset, HHI_SYS_CPU_CLK_POSTMUX1);

sys/dev/fdt/amlclock.c

393

HCLR4(sc, offset, HHI_SYS_DPLL_EN);

sys/dev/fdt/amlclock.c

405

HCLR4(sc, offset, HHI_SYS_DPLL_RESET);

sys/dev/fdt/amlclock.c

610

HCLR4(sc, sc->sc_gates[idx].reg,

sys/dev/fdt/amldwusb.c

211

HCLR4(sc, U2P_R0(i), U2P_R0_POWER_ON_RESET);

sys/dev/fdt/amliic.c

240

HCLR4(sc, I2C_M_CONTROL, I2C_M_CONTROL_START);

sys/dev/fdt/amlmmc.c

539

HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_DDR);

sys/dev/fdt/amlmmc.c

547

HCLR4(sc, SD_EMMC_CFG, SD_EMMC_CFG_STOP_CLOCK);

sys/dev/fdt/amlpwm.c

191

HCLR4(sc, PWM_MISC_REG_AB, (idx == 0) ? PWM_A_EN : PWM_B_EN);

sys/dev/fdt/amlreset.c

107

HCLR4(sc, RESET0_LEVEL + bank * 4, (1 << bit));

sys/dev/fdt/amluart.c

466

HCLR4(sc, UART_CONTROL,

sys/dev/fdt/amlusbphy.c

165

HCLR4(sc, PHY_R21, PHY_R21_USB2_OTG_ACA_EN);

sys/dev/fdt/bcm2711_pcie.c

551

HCLR4(sc, PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT);

sys/dev/fdt/bcmstbgpio.c

169

HCLR4(sc, GIO_IODIR(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

210

HCLR4(sc, GIO_DATA(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

398

HCLR4(sc, GIO_MASK(bank), 1U << pin);

sys/dev/fdt/bcmstbrescal.c

128

HCLR4(sc, RESCAL_START, RESCAL_START_BIT);

sys/dev/fdt/dwdog.c

110

HCLR4(sc, WDT_CR, WDT_CR_RESP_MODE | WDT_CR_WDT_EN);

sys/dev/fdt/dwmmc.c

565

HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO);

sys/dev/fdt/dwmmc.c

581

HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO);

sys/dev/fdt/dwmmc.c

650

HCLR4(sc, SDMMC_PWREN, 0);

sys/dev/fdt/dwmmc.c

723

HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT|SDMMC_CTYPE_4BIT);

sys/dev/fdt/dwmmc.c

727

HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);

sys/dev/fdt/dwmmc.c

743

HCLR4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC |

sys/dev/fdt/dwpcie.c

1438

HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);

sys/dev/fdt/dwpcie.c

1466

HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);

sys/dev/fdt/dwpcie.c

2067

HCLR4(sc, PCIE_MSI_INTR_MASK(vec / 32), (1U << (vec % 32)));

sys/dev/fdt/dwpcie.c

660

HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);

sys/dev/fdt/imxccm.c

1326

HCLR4(sc, sc->sc_predivs[idx].reg,

sys/dev/fdt/imxccm.c

1489

HCLR4(sc, reg, 0x3 << (2 * pos));

sys/dev/fdt/imxccm.c

378

HCLR4(sc, CCM_CCSR, CCM_CCSR_PLL1_SW_CLK_SEL);

sys/dev/fdt/imxccm.c

380

HCLR4(sc, CCM_CCSR, CCM_CCSR_STEP_SEL);

sys/dev/fdt/imxccm.c

384

HCLR4(sc, CCM_CCSR, CCM_CCSR_STEP_SEL);

sys/dev/fdt/imxesdhc.c

1119

HCLR4(sc, SDHC_VEND_SPEC, SDHC_VEND_SPEC_FRC_SDCLK_ON);

sys/dev/fdt/imxesdhc.c

1193

HCLR4(sc, SDHC_INT_SIGNAL_EN,

sys/dev/fdt/imxesdhc.c

1225

HCLR4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT);

sys/dev/fdt/imxesdhc.c

600

HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK);

sys/dev/fdt/imxesdhc.c

603

HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DTW_MASK);

sys/dev/fdt/imxesdhc.c

711

HCLR4(sc, SDHC_VEND_SPEC, SDHC_VEND_SPEC_FRC_SDCLK_ON);

sys/dev/fdt/imxesdhc.c

718

HCLR4(sc, SDHC_SYS_CTRL, SDHC_SYS_CTRL_CLOCK_MASK);

sys/dev/fdt/imxesdhc.c

766

HCLR4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT);

sys/dev/fdt/imxesdhc.c

767

HCLR4(sc, SDHC_INT_SIGNAL_EN, SDHC_INT_STATUS_CINT);

sys/dev/fdt/imxesdhc.c

977

HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK);

sys/dev/fdt/imxesdhc.c

983

HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK);

sys/dev/fdt/imxpwm.c

191

HCLR4(sc, PWM_CR, PWM_CR_EN);

sys/dev/fdt/mvdog.c

100

HCLR4(sc, CNTR_CTRL(CNTR_RETRIGGER), CNTR_CTRL_ENABLE);

sys/dev/fdt/mvdog.c

99

HCLR4(sc, CNTR_CTRL(CNTR_WDOG), CNTR_CTRL_ENABLE);

sys/dev/fdt/mvgpio.c

110

HCLR4(sc, GPIO_DOUTEN, (1 << pin));

sys/dev/fdt/mvgpio.c

151

HCLR4(sc, GPIO_DOUT, (1 << pin));

sys/dev/fdt/mviic.c

141

HCLR4(sc, ICR, ICR_RESET);

sys/dev/fdt/mviic.c

237

HCLR4(sc, ICR, ICR_START);

sys/dev/fdt/mviic.c

238

HCLR4(sc, ICR, ICR_STOP);

sys/dev/fdt/mviic.c

263

HCLR4(sc, ICR, ICR_START);

sys/dev/fdt/mviic.c

264

HCLR4(sc, ICR, ICR_STOP);

sys/dev/fdt/mviic.c

265

HCLR4(sc, ICR, ICR_NAK);

sys/dev/fdt/mviic.c

285

HCLR4(sc, ICR, ICR_START);

sys/dev/fdt/mviic.c

286

HCLR4(sc, ICR, ICR_STOP);

sys/dev/fdt/mviic.c

306

HCLR4(sc, ICR, ICR_ENABLE);

sys/dev/fdt/mvkpcie.c

361

HCLR4(sc, PCIE_CORE_CTRL0, PCIE_CORE_CTRL0_LINK_TRAINING);

sys/dev/fdt/mvkpcie.c

954

HCLR4(sc, PCIE_CORE_ISR1_MASK, PCIE_CORE_ISR1_MASK_INTX(irq));

sys/dev/fdt/mvpinctrl.c

291

HCLR4(sc, GPIO_DIRECTION, (1 << pin));

sys/dev/fdt/mvpinctrl.c

329

HCLR4(sc, GPIO_OUTPUT, (1 << pin));

sys/dev/fdt/mvspi.c

146

HCLR4(sc, SPI_CFG, SPI_CFG_FIFO_ENABLE);

sys/dev/fdt/mvspi.c

147

HCLR4(sc, SPI_CFG, SPI_CFG_BYTE_LEN);

sys/dev/fdt/mvspi.c

183

HCLR4(sc, SPI_CFG, SPI_CFG_PRESCALE_MASK);

sys/dev/fdt/mvspi.c

230

HCLR4(sc, SPI_CTRL, SPI_CTRL_CS(cs));

sys/dev/fdt/mvuart.c

249

HCLR4(sc, MVUART_CTRL, MVUART_CTRL_TX_RDY_INT);

sys/dev/fdt/mvuart.c

486

HCLR4(sc, MVUART_CTRL, MVUART_CTRL_RX_RDY_INT |

sys/dev/fdt/qcgpio_fdt.c

182

HCLR4(sc, TLMM_GPIO_INTR_CFG(pin),

sys/dev/fdt/qcgpio_fdt.c

212

HCLR4(sc, TLMM_GPIO_CFG(pin), TLMM_GPIO_CFG_OUT_EN);

sys/dev/fdt/qcgpio_fdt.c

251

HCLR4(sc, TLMM_GPIO_IN_OUT(pin),

sys/dev/fdt/qcgpio_fdt.c

360

HCLR4(sc, TLMM_GPIO_INTR_CFG(pin),

sys/dev/fdt/qcpdc.c

132

HCLR4(sc, PDC_INTR_ENABLE(sc->sc_pr[i].pin_base + j),

sys/dev/fdt/qcpdc.c

221

HCLR4(sc, PDC_INTR_ENABLE(ih->ih_pin), PDC_INTR_ENABLE_BIT(ih->ih_pin));

sys/dev/fdt/rkgpio.c

224

HCLR4(sc, GPIO_SWPORTA_DDR, (1 << pin));

sys/dev/fdt/rkgpio.c

272

HCLR4(sc, GPIO_SWPORTA_DR, (1 << pin));

sys/dev/fdt/rkgpio.c

394

HCLR4(sc, GPIO_INT_POLARITY, 1 << irqno);

sys/dev/fdt/rkgpio.c

397

HCLR4(sc, GPIO_INTTYPE_LEVEL, 1 << irqno);

sys/dev/fdt/rkgpio.c

401

HCLR4(sc, GPIO_INTTYPE_LEVEL, 1 << irqno);

sys/dev/fdt/rkgpio.c

402

HCLR4(sc, GPIO_INT_POLARITY, 1 << irqno);

sys/dev/fdt/rkgpio.c

408

HCLR4(sc, GPIO_SWPORTA_DDR, 1 << irqno);

sys/dev/fdt/rkgpio.c

409

HCLR4(sc, GPIO_INTMASK, 1 << irqno);

sys/dev/fdt/rkgpio.c

497

HCLR4(sc, GPIO_INTMASK, 1 << ih->ih_irq);

sys/dev/fdt/rkiic.c

195

HCLR4(sc, RKI2C_CON, RKI2C_CON_I2C_EN);

sys/dev/fdt/rkiic.c

211

HCLR4(sc, RKI2C_CON, RKI2C_CON_START);

sys/dev/fdt/rkiic.c

230

HCLR4(sc, RKI2C_CON, RKI2C_CON_STOP);

sys/dev/fdt/rkpwm.c

157

HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_ENABLE | PWM_V2_CTRL_CONTINUOUS);

sys/dev/fdt/rkpwm.c

171

HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_INACTIVE_POSITIVE);

sys/dev/fdt/rkpwm.c

172

HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_DUTY_POSITIVE);

sys/dev/fdt/rkspi.c

278

HCLR4(sc, SPI_CTRLR0, SPI_CTRLR0_XFM_RO);

sys/dev/fdt/rkspi.c

314

HCLR4(sc, SPI_SER, SPI_SER_CS(sc->sc_cs));

sys/dev/fdt/rkspi.c

320

HCLR4(sc, SPI_SER, SPI_SER_CS(sc->sc_cs));

sys/dev/fdt/sxirintc.c

108

HCLR4(sc, RINTC_IRQ_ENABLE, RINTC_IRQ_ENABLE_NMI);