IPL_SERIAL
irqmasks[IPL_SERIAL]);
psc->sc_ih = intr_claim(pa->pa_irq, IPL_SERIAL, "com",
asc->sc_ih = podulebus_irq_establish(aa->aa_irq, IPL_SERIAL, comintr,
ssc->sc_ih = pci_intr_establish(sa->sa_pc, ih, IPL_SERIAL,
if (ipl2spl_table[IPL_SERIAL] < needpsl) {
"from 0x%x to 0x%x\n", ipl2spl_table[IPL_SERIAL], needpsl);
ipl2spl_table[IPL_SERIAL] = needpsl;
if (ipl2spl_table[IPL_SERIAL] < needpsl) {
device_xname(self), ipl2spl_table[IPL_SERIAL],
ipl2spl_table[IPL_SERIAL] = needpsl;
intr_establish(5, IST_LEVEL, IPL_SERIAL, lev5_intr, NULL);
intr_establish(6, IST_LEVEL, IPL_SERIAL, exter_intr, &isr_exter);
IPL_SERIAL, true, plcomintr, sc, device_xname(self));
mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL);
sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL,
at91_intr_establish(sa->sa_pid, IPL_SERIAL, INTR_HIGH_LEVEL, dbgu_intr, sc);
sc->sc_ih = at91_intr_establish(sc->sc_pid, IPL_SERIAL, INTR_HIGH_LEVEL,
ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL, FDT_INTR_MPSAFE,
IPL_SERIAL, true, comintr, sc, device_xname(self));
intr_establish(sc->sc_irq[CLPSCOM_TXINT], IPL_SERIAL, 0,
IPL_SERIAL, 0, clpscom_rxintr, sc);
IPL_SERIAL, 0, clpscom_msintr, sc);
ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL, FDT_INTR_MPSAFE,
sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL,
intr_establish(obio->obio_intr, IPL_SERIAL, IST_LEVEL_HIGH,
IPL_SERIAL, IST_LEVEL_HIGH, comintr, &sc->sc_com);
IPL_SERIAL, IST_LEVEL_LOW, lpc_com_intr, &sc->sc_com);
ih = intr_establish(obio->obio_intr, IPL_SERIAL,
sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL,
IPL_SERIAL, FDT_INTR_MPSAFE, comintr, sc, device_xname(self));
sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL,
sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SERIAL);
IPL_SERIAL, IST_LEVEL, sscomtxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomrxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomrxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomtxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomrxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomrxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomtxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomrxintr, sc);
IPL_SERIAL, IST_LEVEL, sscomrxintr, sc);
sa11x0_intr_establish(0, sa->sa_intr, 1, IPL_SERIAL, sacomintr, sc);
sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL,
ssc->ssc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SERIAL,
if (fdtbus_intr_establish(phandle, 0, IPL_SERIAL, IST_LEVEL,
ixp425_intr_establish(uart_irq[sa->sa_index], IPL_SERIAL, comintr, sc);
pxa2x0_intr_establish(pxa->pxa_intr, IPL_SERIAL, comintr, sc);
extirq_level[i] = IPL_SERIAL;
_splraise(IPL_SERIAL);
extirq_level[irqno] = IPL_SERIAL;
pxa2x0_update_intr_masks(irqno, IPL_SERIAL);
footbridge_imask[IPL_HIGH], footbridge_imask[IPL_SERIAL]);
cpu_intr_establish(maa->ma_level, IPL_SERIAL, comintr, sc);
icu_intr_establish(maa->ma_irq, IST_EDGE, IPL_SERIAL, zshard, zsc);
#define IPL_ZS IPL_SERIAL
if (intr_establish(aa->aa_irq, IPL_SERIAL, 0, wmcom_intr, sc) == NULL) {
osc->sc_ih = becc_intr_establish(oba->oba_irq, IPL_SERIAL,
ep93xx_intr_establish(sa->sa_intr, IPL_SERIAL, armadillo9com_intr, sc);
osc->sc_ih = i80321_intr_establish(oba->oba_irq, IPL_SERIAL,
isc->sc_ih = ifpga_intr_establish(ifa->ifa_irq, IPL_SERIAL,
osc->sc_ih = iq80310_intr_establish(oba->oba_irq, IPL_SERIAL,
iq80310_imask[IPL_SERIAL] |= iq80310_imask[IPL_HIGH];
osc->sc_ih = i80321_intr_establish(oba->oba_irq, IPL_SERIAL,
ixp12x0_intr_establish(IXP12X0_INTR_UART, IPL_SERIAL, ixpcomintr, sc);
osc->sc_ih = i80321_intr_establish(oba->oba_irq, IPL_SERIAL,
osc->sc_ih = i80321_intr_establish(oba->oba_irq, IPL_SERIAL,
sc->spi_ih = s3c24x0_intr_establish(spia->spia_intr, IPL_SERIAL,
ep93xx_intr_establish(sa->sa_intr, IPL_SERIAL, epcomintr, sc);
intr_establish(oa->oa_irq, IST_EDGE, IPL_SERIAL, comintr, sc);
intr_establish_xname(eaa->elb_irq, IST_LEVEL, IPL_SERIAL, comintr, sc,
if ((sc->sc_ih = intr_establish(vaa->vaa_intr, IST_LEVEL, IPL_SERIAL,
intr_establish(irq, IST_LEVEL, IPL_SERIAL, pckbcintr, sc);
#define IPL_ZS IPL_SERIAL
sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc);
psc->sc_ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_SERIAL,
osc->sc_ih = i80321_intr_establish(oba->oba_irq, IPL_SERIAL,
#define IPL_ZS IPL_SERIAL
intr_establish_xname(interrupts[0], IST_LEVEL, IPL_SERIAL, comintr, sc,
asc->sc_ih = au_intr_establish(asc->sc_irq, 0, IPL_SERIAL, IST_LEVEL,
[IPL_SERIAL] = MIPS_SOFT_INT_MASK |
sc->sc_ih = octeon_intr_establish(CIU_INT_MPI, IPL_SERIAL, octmpi_intr, sc);
IPL_SERIAL, comintr, sc_com);
ch->ch_intrhand = cpu_intr_establish(intr, IPL_SERIAL, sbscn_intr, ch);
mmeye_intr_establish(ma->ma_irq1, IST_LEVEL, IPL_SERIAL, comintr, sc);
#define IPL_ZS IPL_SERIAL
footbridge_imask[IPL_HIGH], footbridge_imask[IPL_SERIAL]);
#define IPL_ZS IPL_SERIAL
hb_intr_establish(intlevel, INTST1_SCC, IPL_SERIAL, zshard_hb, zsc);
#define IPL_ZS IPL_SERIAL
#define IPL_ZS IPL_SERIAL
dsc->dsc_ih = intr_establish(cnl->cnl_intrs[0], IPL_SERIAL,
intr_establish_xname(oaa->opb_irq, IST_LEVEL, IPL_SERIAL, comintr, sc,
intr_establish_xname(sc->sc_irq, IST_LEVEL, IPL_SERIAL, ecc_plb_intr,
isc->sc_ih = mca_intr_establish(idaa->idaa_mc, irq, IPL_SERIAL,
intr_establish_xname(epicirq + I8259_ICU, IST_LEVEL, IPL_SERIAL,
mutex_init(&sc->sc_replk, MUTEX_DEFAULT, IPL_SERIAL);
intr_establish_xname(epicirq + I8259_ICU, IST_LEVEL, IPL_SERIAL,
IST_LEVEL, IPL_SERIAL, mbtnintr, sc, intr_xname);
intc_intr_establish(SH_INTEVT_SCI_ERI, IST_LEVEL, IPL_SERIAL, sciintr,
intc_intr_establish(SH_INTEVT_SCI_RXI, IST_LEVEL, IPL_SERIAL, sciintr,
intc_intr_establish(SH_INTEVT_SCI_TXI, IST_LEVEL, IPL_SERIAL, sciintr,
intc_intr_establish(SH_INTEVT_SCI_TEI, IST_LEVEL, IPL_SERIAL, sciintr,
intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
(void)bus_intr_establish(iot, ea->ea_intr[0], IPL_SERIAL,
IPL_SERIAL, comintr, sc);
IPL_SERIAL, jsc_pckbdintr, jsc);
bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, zshard, zsc);
IPL_SERIAL, comintr, sc);
IPL_SERIAL, lptintr, sc);
bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, zshard, zsc);
#define IPL_ZS IPL_SERIAL
bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc);
#define IPL_ZS IPL_SERIAL
mutex_init(&ms->ms_lock, MUTEX_DEFAULT, IPL_SERIAL);
#define IPL_ZS IPL_SERIAL
IPL_SERIAL, true, comintr, sc, device_xname(self));
csc->cc_ih = Cardbus_intr_establish(ct, IPL_SERIAL, comintr, sc);
IPL_SERIAL, FDT_INTR_MPSAFE, comintr, sc, device_xname(self));
ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_SERIAL,
IPL_SERIAL, 0, pcfiic_intr, &sc->sc_pcfdev,
sc->sc_ih = intr_establish(irq, IST_LEVEL, IPL_SERIAL, comintr,
#ifndef IPL_SERIAL
IST_EDGE, IPL_SERIAL, addcomintr, sc);
IST_EDGE, IPL_SERIAL, astintr, sc);
IST_EDGE, IPL_SERIAL, bocaintr, sc);
IPL_SERIAL, comintr, sc, device_xname(sc->sc_dev));
IPL_SERIAL, comintr, sc);
IPL_SERIAL, ioat66intr, sc);
IST_EDGE, IPL_SERIAL, moxa_isaintr, sc);
IPL_SERIAL, rtfpsintr, sc);
IST_EDGE, IPL_SERIAL, tcomintr, sc);
ipa->ipa_irq[0].type, IPL_SERIAL, comintr, sc);
marvell_intr_establish(mva->mva_irq, IPL_SERIAL, comintr, sc);
(void)marvell_intr_establish(IRQ_SDMA, IPL_SERIAL, gtmpsc_intr, gt);
isc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_SERIAL,
IPL_SERIAL, comintr, sc);
IPL_SERIAL, comintr, sc, device_xname(self));
psc->sc_ih = pcmcia_intr_establish(pf, IPL_SERIAL, comintr, sc);
sc->sc_ih = pcmcia_intr_establish(sc->sc_pf, IPL_SERIAL,
podulebus_irq_establish(pa->pa_ih, IPL_SERIAL, comintr, sc,
(void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL,
sa->sa_intr[PARALLEL_INTR].oi_pri, IPL_SERIAL, spif_ppcintr, sc);
sa->sa_intr[SERIAL_INTR].oi_pri, IPL_SERIAL, spif_stcintr, sc);