PCI_COMMAND_MASTER_ENABLE
csr |= PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0);
PCI_COMMAND_MASTER_ENABLE |
PCI_COMMAND_MASTER_ENABLE |
reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
csr |= PCI_COMMAND_MASTER_ENABLE;
csr &= ~PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE)) {
PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE;
enable |= PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
data |= PCI_COMMAND_MASTER_ENABLE;
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_MASTER_ENABLE | data);
PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE));
PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
x |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
enable |= PCI_COMMAND_MASTER_ENABLE;
| PCI_COMMAND_MASTER_ENABLE
PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_PARITY_ENABLE);
| PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_PARITY_ENABLE);
PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE
reg |= PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE); /* XXX: good guess needed */
csc->cc_csr = PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE |
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE |
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
csr = PCI_COMMAND_MASTER_ENABLE;
csr = PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
command |= PCI_COMMAND_MASTER_ENABLE;
if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) {
PCI_COMMAND_MASTER_ENABLE)) !=
PCI_COMMAND_MASTER_ENABLE)) {
PCI_COMMAND_MASTER_ENABLE));
PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_MASTER_ENABLE;
reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
reg | PCI_COMMAND_MASTER_ENABLE);
reg | PCI_COMMAND_MASTER_ENABLE);
v | PCI_COMMAND_MASTER_ENABLE);
v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE);
data |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
command |= PCI_COMMAND_MASTER_ENABLE;
reg | PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE;
reg | PCI_COMMAND_MASTER_ENABLE);
reg | PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE |
| PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE;
csr &= ~(PCI_COMMAND_MASTER_ENABLE |
csr &= ~(PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE);
cmd |= PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE);
command |= PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) {
PCI_COMMAND_MASTER_ENABLE);
command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
preg |= PCI_COMMAND_MASTER_ENABLE;
if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) ||
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) {
reg |= PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
(PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE));
PCI_COMMAND_MASTER_ENABLE);
csr |= (PCI_COMMAND_MASTER_ENABLE |
data |= PCI_COMMAND_MASTER_ENABLE;
data |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
csr |= (PCI_COMMAND_MASTER_ENABLE |
csr | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
command |= PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE;
psc->psc_csr = PCI_COMMAND_MASTER_ENABLE |
PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
command |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
if (!(command & PCI_COMMAND_MASTER_ENABLE)) {
PCI_COMMAND_MASTER_ENABLE);
preg |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
preg |= PCI_COMMAND_MASTER_ENABLE;
data |= PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
command |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_PARITY_ENABLE;
reg | PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE;
data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
if (!(pci_cmd_word & PCI_COMMAND_MASTER_ENABLE)) {
pci_cmd_word |= PCI_COMMAND_MASTER_ENABLE;
reg | PCI_COMMAND_MASTER_ENABLE);
reg | PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE;
if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) ||
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE);
command |= PCI_COMMAND_MASTER_ENABLE;
command &= ~PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
| PCI_COMMAND_MASTER_ENABLE);
csr &= ~PCI_COMMAND_MASTER_ENABLE;
csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE;
cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
PCI_COMMAND_MASTER_ENABLE);
onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
cmd |= PCI_COMMAND_MASTER_ENABLE;
cmd |= PCI_COMMAND_MASTER_ENABLE;
cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
csr |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0)
reg | PCI_COMMAND_MASTER_ENABLE);
if (!(pci_cmd_word & PCI_COMMAND_MASTER_ENABLE)) {
pci_cmd_word |= PCI_COMMAND_MASTER_ENABLE;
cmd |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE);
if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) !=
(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
csr | PCI_COMMAND_MASTER_ENABLE);
cmd |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);