arch/mips/include/asm/mach-rc32434/rb.h
46
u32 timing;
drivers/ata/ahci.c
1877
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
drivers/ata/ahci.c
1901
rc = sata_link_hardreset(link, timing, deadline, &online,
drivers/ata/ahci_qoriq.c
127
rc = sata_link_hardreset(link, timing, deadline, &online,
drivers/ata/ahci_qoriq.c
91
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
drivers/ata/ahci_xgene.c
350
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
drivers/ata/ahci_xgene.c
367
rc = sata_link_hardreset(link, timing, deadline, online,
drivers/ata/libahci.c
1595
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
drivers/ata/libahci.c
1612
rc = sata_link_hardreset(link, timing, deadline, online,
drivers/ata/libata-core.c
3818
const unsigned int *timing = sata_ehc_deb_timing(ehc);
drivers/ata/libata-core.c
3827
rc = sata_link_resume(link, timing, deadline);
drivers/ata/libata-sata.c
624
int sata_link_hardreset(struct ata_link *link, const unsigned int *timing,
drivers/ata/libata-sata.c
666
rc = sata_link_resume(link, timing, deadline);
drivers/ata/libata-sata.c
726
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
drivers/ata/libata-sata.c
730
rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
drivers/ata/libata-sff.c
1965
const unsigned int *timing = sata_ehc_deb_timing(ehc);
drivers/ata/libata-sff.c
1969
rc = sata_link_hardreset(link, timing, deadline, &online,
drivers/ata/pata_artop.c
103
static const u16 timing[2][5] = {
drivers/ata/pata_artop.c
109
pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
drivers/ata/pata_artop.c
157
static const u8 timing[2][5] = {
drivers/ata/pata_artop.c
163
pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
drivers/ata/pata_cmd640.c
116
timing->reg58[adev->devno] = (t.active << 4) | t.recover;
drivers/ata/pata_cmd640.c
134
struct cmd640_reg *timing = ap->private_data;
drivers/ata/pata_cmd640.c
136
if (ap->port_no != 0 && adev->devno != timing->last) {
drivers/ata/pata_cmd640.c
137
pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]);
drivers/ata/pata_cmd640.c
138
timing->last = adev->devno;
drivers/ata/pata_cmd640.c
154
struct cmd640_reg *timing;
drivers/ata/pata_cmd640.c
156
timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL);
drivers/ata/pata_cmd640.c
157
if (timing == NULL)
drivers/ata/pata_cmd640.c
159
timing->last = -1; /* Force a load */
drivers/ata/pata_cmd640.c
160
ap->private_data = timing;
drivers/ata/pata_cmd640.c
54
struct cmd640_reg *timing = ap->private_data;
drivers/ata/pata_cs5530.c
101
iowrite32(timing, base + 0x04);
drivers/ata/pata_cs5530.c
103
if (timing & 0x00100000)
drivers/ata/pata_cs5530.c
108
iowrite32(timing, base + 0x0C);
drivers/ata/pata_cs5530.c
76
u32 tuning, timing = 0;
drivers/ata/pata_cs5530.c
84
timing = 0x00921250;break;
drivers/ata/pata_cs5530.c
86
timing = 0x00911140;break;
drivers/ata/pata_cs5530.c
88
timing = 0x00911030;break;
drivers/ata/pata_cs5530.c
90
timing = 0x00077771;break;
drivers/ata/pata_cs5530.c
92
timing = 0x00012121;break;
drivers/ata/pata_cs5530.c
94
timing = 0x00002020;break;
drivers/ata/pata_cs5530.c
99
timing |= (tuning & 0x80000000UL);
drivers/ata/pata_hpt366.c
126
return clocks->timing;
drivers/ata/pata_hpt366.c
30
u32 timing;
drivers/ata/pata_hpt37x.c
214
return clocks->timing;
drivers/ata/pata_hpt37x.c
30
u32 timing;
drivers/ata/pata_hpt37x.c
428
u32 reg, timing, mask;
drivers/ata/pata_hpt37x.c
438
timing = hpt37x_find_mode(ap, mode);
drivers/ata/pata_hpt37x.c
441
reg = (reg & ~mask) | (timing & mask);
drivers/ata/pata_hpt3x2n.c
101
return clocks->timing;
drivers/ata/pata_hpt3x2n.c
191
u32 reg, timing, mask;
drivers/ata/pata_hpt3x2n.c
201
timing = hpt3x2n_find_mode(ap, mode);
drivers/ata/pata_hpt3x2n.c
204
reg = (reg & ~mask) | (timing & mask);
drivers/ata/pata_hpt3x2n.c
36
u32 timing;
drivers/ata/pata_imx.c
57
struct ata_timing timing;
drivers/ata/pata_imx.c
68
ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
drivers/ata/pata_imx.c
74
writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
drivers/ata/pata_imx.c
75
writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
drivers/ata/pata_imx.c
76
writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
drivers/ata/pata_it821x.c
127
static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
drivers/ata/pata_it821x.c
136
conf = timing >> 8;
drivers/ata/pata_it821x.c
138
conf = timing & 0xFF;
drivers/ata/pata_it821x.c
155
static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
drivers/ata/pata_it821x.c
165
conf = timing >> 8;
drivers/ata/pata_it821x.c
167
conf = timing & 0xFF;
drivers/ata/pata_legacy.c
65
unsigned long timing;
drivers/ata/pata_mpc52xx.c
273
struct mpc52xx_ata_timings *timing = &priv->timings[dev];
drivers/ata/pata_mpc52xx.c
288
timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
drivers/ata/pata_mpc52xx.c
289
timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
drivers/ata/pata_mpc52xx.c
335
struct mpc52xx_ata_timings *timing = &priv->timings[device];
drivers/ata/pata_mpc52xx.c
337
out_be32(®s->pio1, timing->pio1);
drivers/ata/pata_mpc52xx.c
338
out_be32(®s->pio2, timing->pio2);
drivers/ata/pata_mpc52xx.c
339
out_be32(®s->mdma1, timing->mdma1);
drivers/ata/pata_mpc52xx.c
340
out_be32(®s->mdma2, timing->mdma2);
drivers/ata/pata_mpc52xx.c
341
out_be32(®s->udma1, timing->udma1);
drivers/ata/pata_mpc52xx.c
342
out_be32(®s->udma2, timing->udma2);
drivers/ata/pata_mpc52xx.c
343
out_be32(®s->udma3, timing->udma3);
drivers/ata/pata_mpc52xx.c
344
out_be32(®s->udma4, timing->udma4);
drivers/ata/pata_mpc52xx.c
345
out_be32(®s->udma5, timing->udma5);
drivers/ata/pata_ns87415.c
56
int timing = 0x44 + 2 * unit;
drivers/ata/pata_ns87415.c
72
pci_write_config_word(dev, timing, clocking);
drivers/ata/pata_octeon_cf.c
131
struct ata_timing timing;
drivers/ata/pata_octeon_cf.c
150
BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T));
drivers/ata/pata_octeon_cf.c
152
t2 = timing.active;
drivers/ata/pata_octeon_cf.c
160
pause = (int)timing.cycle - (int)timing.active -
drivers/ata/pata_octeon_cf.c
161
(int)timing.setup - trh;
drivers/ata/pata_octeon_cf.c
225
const struct ata_timing *timing;
drivers/ata/pata_octeon_cf.c
227
timing = ata_timing_find_mode(dev->dma_mode);
drivers/ata/pata_octeon_cf.c
228
T0 = timing->cycle;
drivers/ata/pata_octeon_cf.c
229
Td = timing->active;
drivers/ata/pata_octeon_cf.c
230
Tkr = timing->recover;
drivers/ata/pata_octeon_cf.c
231
dma_ackh = timing->dmack_hold;
drivers/ata/pata_sis.c
341
u16 timing;
drivers/ata/pata_sis.c
346
pci_read_config_word(pdev, drive_pci, &timing);
drivers/ata/pata_sis.c
351
timing &= ~0x870F;
drivers/ata/pata_sis.c
352
timing |= mwdma_bits[speed];
drivers/ata/pata_sis.c
356
timing &= ~0x6000;
drivers/ata/pata_sis.c
357
timing |= udma_bits[speed];
drivers/ata/pata_sis.c
359
pci_write_config_word(pdev, drive_pci, timing);
drivers/ata/pata_sis.c
380
u16 timing;
drivers/ata/pata_sis.c
386
pci_read_config_word(pdev, drive_pci, &timing);
drivers/ata/pata_sis.c
391
timing &= ~0x870F;
drivers/ata/pata_sis.c
392
timing |= mwdma_bits[speed];
drivers/ata/pata_sis.c
396
timing &= ~0xF000;
drivers/ata/pata_sis.c
397
timing |= udma_bits[speed];
drivers/ata/pata_sis.c
399
pci_write_config_word(pdev, drive_pci, timing);
drivers/ata/pata_sis.c
419
u8 timing;
drivers/ata/pata_sis.c
423
pci_read_config_byte(pdev, drive_pci + 1, &timing);
drivers/ata/pata_sis.c
430
timing &= ~0x8F;
drivers/ata/pata_sis.c
431
timing |= udma_bits[speed];
drivers/ata/pata_sis.c
433
pci_write_config_byte(pdev, drive_pci + 1, timing);
drivers/ata/pata_sis.c
453
u8 timing;
drivers/ata/pata_sis.c
457
pci_read_config_byte(pdev, drive_pci + 1, &timing);
drivers/ata/pata_sis.c
464
timing &= ~0x8F;
drivers/ata/pata_sis.c
465
timing |= udma_bits[speed];
drivers/ata/pata_sis.c
467
pci_write_config_byte(pdev, drive_pci + 1, timing);
drivers/ata/pata_sl82c105.c
122
int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
drivers/ata/pata_sl82c105.c
125
pci_write_config_word(pdev, timing, dma_timing[dma]);
drivers/ata/pata_sl82c105.c
127
pci_read_config_word(pdev, timing, &dummy);
drivers/ata/pata_sl82c105.c
85
int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
drivers/ata/pata_sl82c105.c
87
pci_write_config_word(pdev, timing, pio_timing[pio]);
drivers/ata/pata_sl82c105.c
89
pci_read_config_word(pdev, timing, &dummy);
drivers/ata/pata_triflex.c
100
timing = 0x0204;break;
drivers/ata/pata_triflex.c
102
timing = 0x0404;break;
drivers/ata/pata_triflex.c
104
timing = 0x0508;break;
drivers/ata/pata_triflex.c
106
timing = 0x0808;break;
drivers/ata/pata_triflex.c
111
triflex_timing |= (timing << (16 * is_slave));
drivers/ata/pata_triflex.c
76
u32 timing = 0;
drivers/ata/pata_triflex.c
88
timing = 0x0103;break;
drivers/ata/pata_triflex.c
90
timing = 0x0203;break;
drivers/ata/pata_triflex.c
92
timing = 0x0808;break;
drivers/ata/pata_triflex.c
96
timing = 0x0F0F;break;
drivers/ata/pata_triflex.c
98
timing = 0x0202;break;
drivers/ata/pata_via.c
501
u32 timing;
drivers/ata/pata_via.c
508
pci_read_config_dword(pdev, 0x50, &timing);
drivers/ata/pata_via.c
509
timing |= 0x80008;
drivers/ata/pata_via.c
510
pci_write_config_dword(pdev, 0x50, timing);
drivers/ata/pata_via.c
514
pci_read_config_dword(pdev, 0x50, &timing);
drivers/ata/pata_via.c
515
timing &= ~0x80008;
drivers/ata/pata_via.c
516
pci_write_config_dword(pdev, 0x50, timing);
drivers/ata/sata_highbank.c
389
static const unsigned int timing[] = { 5, 100, 500};
drivers/ata/sata_highbank.c
409
rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
drivers/ata/sata_inic162x.c
622
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
drivers/ata/sata_inic162x.c
633
rc = sata_link_resume(link, timing, deadline);
drivers/ata/sata_mv.c
3606
const unsigned int *timing =
drivers/ata/sata_mv.c
3609
rc = sata_link_hardreset(link, timing, deadline + extra,
drivers/ata/sata_nv.c
1563
const unsigned int *timing = sata_ehc_deb_timing(ehc);
drivers/ata/sata_nv.c
1571
rc = sata_link_resume(link, timing, deadline);
drivers/clk/tegra/clk-tegra124-emc.c
120
struct emc_timing *timing = NULL;
drivers/clk/tegra/clk-tegra124-emc.c
136
timing = tegra->timings + i;
drivers/clk/tegra/clk-tegra124-emc.c
138
if (timing->rate < req->rate && i != t - 1)
drivers/clk/tegra/clk-tegra124-emc.c
141
if (timing->rate > req->max_rate) {
drivers/clk/tegra/clk-tegra124-emc.c
147
if (timing->rate < req->min_rate)
drivers/clk/tegra/clk-tegra124-emc.c
150
req->rate = timing->rate;
drivers/clk/tegra/clk-tegra124-emc.c
154
if (timing) {
drivers/clk/tegra/clk-tegra124-emc.c
155
req->rate = timing->rate;
drivers/clk/tegra/clk-tegra124-emc.c
210
struct emc_timing *timing)
drivers/clk/tegra/clk-tegra124-emc.c
221
pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
drivers/clk/tegra/clk-tegra124-emc.c
222
timing->parent_rate, __clk_get_name(timing->parent));
drivers/clk/tegra/clk-tegra124-emc.c
224
if (emc_get_parent(&tegra->hw) == timing->parent_index &&
drivers/clk/tegra/clk-tegra124-emc.c
225
clk_get_rate(timing->parent) != timing->parent_rate) {
drivers/clk/tegra/clk-tegra124-emc.c
227
__clk_get_name(timing->parent),
drivers/clk/tegra/clk-tegra124-emc.c
228
clk_get_rate(timing->parent),
drivers/clk/tegra/clk-tegra124-emc.c
229
timing->parent_rate);
drivers/clk/tegra/clk-tegra124-emc.c
235
err = clk_set_rate(timing->parent, timing->parent_rate);
drivers/clk/tegra/clk-tegra124-emc.c
238
__clk_get_name(timing->parent), timing->parent_rate,
drivers/clk/tegra/clk-tegra124-emc.c
244
err = clk_prepare_enable(timing->parent);
drivers/clk/tegra/clk-tegra124-emc.c
250
div = timing->parent_rate / (timing->rate / 2) - 2;
drivers/clk/tegra/clk-tegra124-emc.c
252
err = tegra->prepare_timing_change(emc, timing->rate);
drivers/clk/tegra/clk-tegra124-emc.c
254
clk_disable_unprepare(timing->parent);
drivers/clk/tegra/clk-tegra124-emc.c
263
car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
drivers/clk/tegra/clk-tegra124-emc.c
272
tegra->complete_timing_change(emc, timing->rate);
drivers/clk/tegra/clk-tegra124-emc.c
274
clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
drivers/clk/tegra/clk-tegra124-emc.c
277
tegra->prev_parent = timing->parent;
drivers/clk/tegra/clk-tegra124-emc.c
294
struct emc_timing *timing;
drivers/clk/tegra/clk-tegra124-emc.c
297
timing = tegra->timings + i;
drivers/clk/tegra/clk-tegra124-emc.c
298
if (timing->ram_code != ram_code)
drivers/clk/tegra/clk-tegra124-emc.c
301
if (emc_parent_clk_sources[timing->parent_index] !=
drivers/clk/tegra/clk-tegra124-emc.c
304
return timing;
drivers/clk/tegra/clk-tegra124-emc.c
308
timing = tegra->timings + i;
drivers/clk/tegra/clk-tegra124-emc.c
309
if (timing->ram_code != ram_code)
drivers/clk/tegra/clk-tegra124-emc.c
312
if (emc_parent_clk_sources[timing->parent_index] !=
drivers/clk/tegra/clk-tegra124-emc.c
315
return timing;
drivers/clk/tegra/clk-tegra124-emc.c
325
struct emc_timing *timing = NULL;
drivers/clk/tegra/clk-tegra124-emc.c
345
timing = tegra->timings + i;
drivers/clk/tegra/clk-tegra124-emc.c
350
if (!timing) {
drivers/clk/tegra/clk-tegra124-emc.c
356
emc_parent_clk_sources[timing->parent_index] &&
drivers/clk/tegra/clk-tegra124-emc.c
357
clk_get_rate(timing->parent) != timing->parent_rate) {
drivers/clk/tegra/clk-tegra124-emc.c
381
return emc_set_timing(tegra, timing);
drivers/clk/tegra/clk-tegra124-emc.c
387
struct emc_timing *timing,
drivers/clk/tegra/clk-tegra124-emc.c
399
timing->rate = tmp;
drivers/clk/tegra/clk-tegra124-emc.c
407
timing->parent_rate = tmp;
drivers/clk/tegra/clk-tegra124-emc.c
409
timing->parent = of_clk_get_by_name(node, "emc-parent");
drivers/clk/tegra/clk-tegra124-emc.c
410
if (IS_ERR(timing->parent)) {
drivers/clk/tegra/clk-tegra124-emc.c
412
return PTR_ERR(timing->parent);
drivers/clk/tegra/clk-tegra124-emc.c
415
timing->parent_index = 0xff;
drivers/clk/tegra/clk-tegra124-emc.c
417
__clk_get_name(timing->parent));
drivers/clk/tegra/clk-tegra124-emc.c
420
node, __clk_get_name(timing->parent));
drivers/clk/tegra/clk-tegra124-emc.c
421
clk_put(timing->parent);
drivers/clk/tegra/clk-tegra124-emc.c
425
timing->parent_index = i;
drivers/clk/tegra/clk-tegra124-emc.c
461
struct emc_timing *timing = timings_ptr + (i++);
drivers/clk/tegra/clk-tegra124-emc.c
463
err = load_one_timing_from_dt(tegra, timing, child);
drivers/clk/tegra/clk-tegra124-emc.c
469
timing->ram_code = ram_code;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10038
if (!new_stream->timing.h_total || !new_stream->timing.v_total)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11514
get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state)))
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11537
= get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
618
stream->adjust.v_total_max : stream->timing.v_total;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
619
refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
620
100LL, (v_total * stream->timing.h_total));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6739
dst.width = stream->timing.h_addressable;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6740
dst.height = stream->timing.v_addressable;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6759
dst.x = (stream->timing.h_addressable - dst.width) / 2;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6760
dst.y = (stream->timing.v_addressable - dst.height) / 2;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6969
struct dc_crtc_timing *timing_out = &stream->timing;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7021
timing_out->vic = old_stream->timing.vic;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7022
timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7023
timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7197
master->timing.flags.VSYNC_POSITIVE_POLARITY ?
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7212
refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7213
(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7373
stream->timing.flags.DSC = 0;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7436
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7445
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7448
stream->timing.dsc_cfg = dsc_cfg;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7449
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7450
stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7460
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7463
stream->timing.dsc_cfg = dsc_cfg;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7464
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7507
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7509
&stream->timing.dsc_cfg)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7510
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7515
timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7537
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7539
&stream->timing.dsc_cfg)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7540
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7554
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7557
timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, DC_LINK_ENCODING_HDMI_FRL);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7567
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7569
&stream->timing.dsc_cfg)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7570
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7579
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7581
if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7582
stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7584
if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7585
stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7587
if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7588
stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7655
stream->timing.flags.LTE_340MCSC_SCRAMBLE =
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7721
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7723
stream->timing = *aconnector->timing_requested;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8476
dc_pixel_encoding_to_str(stream->timing.pixel_encoding),
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8477
dc_color_depth_to_str(stream->timing.display_color_depth),
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8890
if (stream->timing.flags.DSC != 1) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9673
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9677
timing = &acrtc_state->stream->timing;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9687
timing->v_total *
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9688
timing->h_total,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9689
timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9949
if (!new_stream->timing.h_total || !new_stream->timing.v_total)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1110
switch (dm_crtc_state->stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1901
pipe_ctx->stream->timing.h_addressable,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2085
pipe_ctx->stream->timing.v_addressable,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1497
&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1499
&& pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1502
pipe_ctx->stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1503
pipe_ctx->stream->timing.pixel_encoding,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1506
pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1507
pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1514
*aconnector->timing_requested = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
147
v_total = stream->timing.v_total;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
148
h_total = stream->timing.h_total;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
151
stream->timing.pix_clk_100hz);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
188
v_total = stream->timing.v_total;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
189
h_total = stream->timing.h_total;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
192
stream->timing.pix_clk_100hz);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1226
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1228
&stream->timing.dsc_cfg)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1230
if (stream->sink->dsc_caps.dsc_dec_caps.is_vic_all_bpp && min_bpp_x16 <= stream->timing.dsc_cfg.bits_per_pixel) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1232
params->bw_range.max_target_bpp_x16 = min(stream->timing.dsc_cfg.bits_per_pixel, dsc_policy->max_target_bpp * 16);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1234
params->bw_range.max_kbps = (params->bw_range.max_target_bpp_x16 * stream->timing.pix_clk_100hz + 159) / 160;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1235
params->bw_range.min_kbps = (params->bw_range.min_target_bpp_x16 * stream->timing.pix_clk_100hz + 159) / 160;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1237
min_bpp_x16 <= stream->timing.dsc_cfg.bits_per_pixel &&
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1238
max_bpp_x16 >= stream->timing.dsc_cfg.bits_per_pixel) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1240
params->bw_range.max_target_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1241
params->bw_range.max_kbps = (params->bw_range.max_target_bpp_x16 * stream->timing.pix_clk_100hz + 159) / 160;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1306
stream->timing.flags.DSC = 0;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1308
params[count].timing = &stream->timing;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1319
dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1332
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1335
params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1620
if (stream->timing.flags.DSC == 1)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1865
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1871
&stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1953
dc_bandwidth_in_kbps_from_timing(&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
2031
&stream->timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
2033
&stream->timing.dsc_cfg)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
2034
stream->timing.flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
2042
switch (stream->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
2058
((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
874
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
924
memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
930
params[i].timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
932
¶ms[i].timing->dsc_cfg)) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
933
params[i].timing->flags.DSC = 1;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
936
params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
938
params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
941
params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
944
params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
946
params[i].timing->flags.DSC = 0;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
948
params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
960
params[i].timing->flags.DSC,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
961
params[i].timing->dsc_cfg.bits_per_pixel,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
982
(int) kbps, param.timing,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
159
calculate_replay_link_off_frame_count(link, stream->timing.v_total,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
160
stream->timing.h_total);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
162
nom_coasting_vtotal = stream->timing.v_total;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
426
__entry->stream_w = stream->timing.h_addressable;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
427
__entry->stream_h = stream->timing.v_addressable;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
280
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
281
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
282
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
299
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
300
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
301
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
321
stream->timing.v_total = 2250;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
322
stream->timing.h_total = 4400;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
323
stream->timing.pix_clk_100hz = 5940000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
352
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
353
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
354
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
366
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
367
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
368
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
381
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
382
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
383
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
402
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
403
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
404
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
436
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
437
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
438
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
471
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
472
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
473
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
508
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
509
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
510
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
555
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
556
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
557
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
597
stream->timing.v_total = 1125;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
598
stream->timing.h_total = 2200;
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
599
stream->timing.pix_clk_100hz = 1485000;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2822
data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2823
data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2824
data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2921
data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2922
data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2923
pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2924
if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2990
data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2992
data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
157
cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
158
cfg->v_refresh /= stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
159
cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
160
/ stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
166
const struct dc_crtc_timing *timing =
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
167
&context->streams[0]->timing;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
171
timing->h_total * 10000 / timing->pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
89
uint32_t vertical_total_min = stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
94
vertical_blank_in_pixels = stream->timing.h_total *
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
96
- stream->timing.v_addressable);
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
98
* 10000 / stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
288
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
508
if (pipe->stream->timing.h_addressable == width &&
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
509
pipe->stream->timing.v_addressable == height &&
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
587
pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
590
refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
591
curr_pipe_ctx->stream->timing.v_total * (uint64_t)curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
592
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
593
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
278
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
379
&stream->timing, dc_link_get_highest_encoding_format(link));
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
402
if (pipe->stream->timing.h_addressable == width &&
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
403
pipe->stream->timing.v_addressable == height &&
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
478
pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
481
refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
482
curr_pipe_ctx->stream->timing.v_total
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
483
* (uint64_t) curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
484
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
485
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/core/dc.c
2375
context->streams[i]->timing.h_addressable,
drivers/gpu/drm/amd/display/dc/core/dc.c
2376
context->streams[i]->timing.v_addressable,
drivers/gpu/drm/amd/display/dc/core/dc.c
2377
context->streams[i]->timing.h_total,
drivers/gpu/drm/amd/display/dc/core/dc.c
2378
context->streams[i]->timing.v_total,
drivers/gpu/drm/amd/display/dc/core/dc.c
2379
context->streams[i]->timing.pix_clk_100hz / 10);
drivers/gpu/drm/amd/display/dc/core/dc.c
3476
struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/core/dc.c
3477
uint32_t old_dsc_enabled = stream->timing.flags.DSC;
drivers/gpu/drm/amd/display/dc/core/dc.c
3485
stream->timing.dsc_cfg = *update->dsc_config;
drivers/gpu/drm/amd/display/dc/core/dc.c
3486
stream->timing.flags.DSC = enable_dsc;
drivers/gpu/drm/amd/display/dc/core/dc.c
3489
stream->timing.dsc_cfg = old_dsc_cfg;
drivers/gpu/drm/amd/display/dc/core/dc.c
3490
stream->timing.flags.DSC = old_dsc_enabled;
drivers/gpu/drm/amd/display/dc/core/dc.c
3978
if (!stream->timing.flags.DSC || !dsc)
drivers/gpu/drm/amd/display/dc/core/dc.c
3990
dsc_cfg->pic_width = (stream->timing.h_addressable +
drivers/gpu/drm/amd/display/dc/core/dc.c
3992
stream->timing.h_border_left +
drivers/gpu/drm/amd/display/dc/core/dc.c
3993
stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/core/dc.c
3994
dsc_cfg->pic_height = stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/core/dc.c
3995
stream->timing.v_border_top +
drivers/gpu/drm/amd/display/dc/core/dc.c
3996
stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/core/dc.c
3997
dsc_cfg->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/core/dc.c
3998
dsc_cfg->color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc.c
4000
dsc_cfg->dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/core/dc.c
4006
stream->timing.pix_clk_100hz > 480000)
drivers/gpu/drm/amd/display/dc/core/dc.c
4038
dsc_pps_cfg.pic_width = stream->timing.h_addressable +
drivers/gpu/drm/amd/display/dc/core/dc.c
4039
stream->timing.h_border_left + stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/core/dc.c
4040
dsc_pps_cfg.pic_height = stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/core/dc.c
4041
stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/core/dc.c
4042
dsc_pps_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/core/dc.c
4043
dsc_pps_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc.c
4045
dsc_pps_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/core/dc.c
4064
&stream->timing,
drivers/gpu/drm/amd/display/dc/core/dc.c
664
param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
665
param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
668
param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
669
param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
683
param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7502
state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/core/dc.c
7526
if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7558
if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7563
struct dc_dsc_config *dsc_cfg = &pipe_ctx->stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/core/dc.c
761
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/core/dc.c
7658
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/core/dc.c
7672
state->opp[i].fmt_pixel_encoding = timing->pixel_encoding;
drivers/gpu/drm/amd/display/dc/core/dc.c
7675
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7677
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7683
state->opp[i].fmt_cbcr_bit_reduction_bypass = (timing->pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7684
state->opp[i].fmt_stereosync_override = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7687
if (timing->display_color_depth < COLOR_DEPTH_121212) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7692
state->opp[i].fmt_spatial_dither_depth = timing->display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc.c
7704
if (timing->display_color_depth < COLOR_DEPTH_121212) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7706
state->opp[i].fmt_truncate_depth = timing->display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc.c
7716
state->opp[i].fmt_clamp_color_format = timing->pixel_encoding;
drivers/gpu/drm/amd/display/dc/core/dc.c
7719
if (timing->pixel_encoding != PIXEL_ENCODING_RGB) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7728
state->opp[i].fmt_bit_depth_control = timing->display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc.c
7731
state->opp[i].oppbuf_active_width = timing->h_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
7744
if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7753
if (timing->dsc_cfg.num_slices_h > 0) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7776
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/core/dc.c
7784
state->optc[i].otg_field_number_cntl = (timing->flags.INTERLACE) ? 1 : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7788
state->optc[i].otg_h_total = timing->h_total;
drivers/gpu/drm/amd/display/dc/core/dc.c
7789
state->optc[i].otg_h_blank_start = timing->h_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
7790
state->optc[i].otg_h_blank_end = timing->h_total - timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/core/dc.c
7791
state->optc[i].otg_h_sync_start = timing->h_addressable + timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/core/dc.c
7792
state->optc[i].otg_h_sync_end = timing->h_addressable + timing->h_front_porch + timing->h_sync_width;
drivers/gpu/drm/amd/display/dc/core/dc.c
7793
state->optc[i].otg_h_sync_polarity = timing->flags.HSYNC_POSITIVE_POLARITY ? 0 : 1;
drivers/gpu/drm/amd/display/dc/core/dc.c
7797
state->optc[i].otg_v_total = timing->v_total;
drivers/gpu/drm/amd/display/dc/core/dc.c
7798
state->optc[i].otg_v_blank_start = timing->v_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
7799
state->optc[i].otg_v_blank_end = timing->v_total - timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/core/dc.c
7800
state->optc[i].otg_v_sync_start = timing->v_addressable + timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/core/dc.c
7801
state->optc[i].otg_v_sync_end = timing->v_addressable + timing->v_front_porch + timing->v_sync_width;
drivers/gpu/drm/amd/display/dc/core/dc.c
7802
state->optc[i].otg_v_sync_polarity = timing->flags.VSYNC_POSITIVE_POLARITY ? 0 : 1;
drivers/gpu/drm/amd/display/dc/core/dc.c
7807
state->optc[i].otg_v_total_max = timing->v_total + 100; /* Typical DRR range */
drivers/gpu/drm/amd/display/dc/core/dc.c
7808
state->optc[i].otg_v_total_min = timing->v_total - 50;
drivers/gpu/drm/amd/display/dc/core/dc.c
7809
state->optc[i].otg_v_total_mid = timing->v_total;
drivers/gpu/drm/amd/display/dc/core/dc.c
7824
if (timing->dsc_cfg.num_slices_h > 0) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7826
state->optc[i].optc_dsc_bytes_per_pixel = timing->dsc_cfg.bits_per_pixel / 16; /* Convert to bytes */
drivers/gpu/drm/amd/display/dc/core/dc.c
7827
state->optc[i].optc_dsc_slice_width = timing->h_addressable / timing->dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/core/dc.c
7835
state->optc[i].otg_stereo_enable = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7836
state->optc[i].otg_interlace_enable = timing->flags.INTERLACE ? 1 : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7842
state->optc[i].optc_segment_width = (pipe_ctx->next_odm_pipe) ? (timing->h_addressable / 2) : timing->h_addressable;
drivers/gpu/drm/amd/display/dc/core/dc.c
7844
state->optc[i].otg_vstartup_start = timing->v_addressable + 10;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2000
struct timing_generator *tg, struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2004
seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2067
seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2612
const struct dc_crtc_timing *timing = params->set_odm_bypass_params.timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2615
tg->funcs->set_odm_bypass(tg, timing);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2724
dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_padding +
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2725
stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2726
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2727
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2728
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2730
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2776
struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2780
tg->funcs->set_vtg_params(tg, timing, program_fp2);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
3386
struct dc_crtc_timing *timing = params->hubp_setup2_params.timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
3389
hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
3745
(struct dc_crtc_timing *)params->hpo_frl_stream_enc_set_dsc_config_params.timing,
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
4526
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
4533
seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
5002
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
5008
seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.timing = timing;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
5154
refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
5156
uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
5157
uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1021
*dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1493
enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1522
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1544
pipe_ctx->stream->dst.x += timing->h_border_left;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1545
pipe_ctx->stream->dst.y += timing->v_border_top;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1711
pipe_ctx->stream->dst.x -= timing->h_border_left;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1712
pipe_ctx->stream->dst.y -= timing->v_border_top;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2216
const struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2225
timing = &otg_master->stream->timing;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2227
h_active = timing->h_addressable +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2228
timing->h_border_left +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2229
timing->h_border_right +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2235
otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2242
timing->pixel_encoding == PIXEL_ENCODING_YCBCR422;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2263
odm_slice_dst.height = stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2264
stream->timing.v_border_bottom +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2265
stream->timing.v_border_top;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2284
opp, pipe_ctx->stream->timing.pixel_encoding,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3721
&cur_stream->timing,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3722
&new_stream->timing,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3890
static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3892
uint32_t pix_clk = timing->pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3895
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3897
if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3898
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3928
&stream->timing) / 10;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3931
stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3933
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4061
if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4221
if (stream->timing.pix_clk_100hz < 6000000)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4616
const struct dc_crtc_timing *timing, struct dsc_padding_params *dsc_padding_params)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4622
timing->pix_clk_100hz,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4624
timing->h_addressable,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4625
timing->h_border_left,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4626
timing->h_border_right,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4627
timing->h_total,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4628
(timing->h_addressable + dsc_padding_params->dsc_hactive_padding),
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4633
dsc_padding_params->dsc_htotal_padding = dsc_padding_params->dsc_htotal_padding - timing->h_total;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4659
pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4664
if (stream && stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4665
hactive = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4668
if (hactive % stream->timing.dsc_cfg.num_slices_h != 0) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4669
ceil_slice_width = (hactive / stream->timing.dsc_cfg.num_slices_h) + 1;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4672
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420 && ceil_slice_width % 2 != 0)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4676
(uint8_t)(ceil_slice_width * stream->timing.dsc_cfg.num_slices_h - hactive);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4678
if (stream->timing.h_total - hactive - pipe_ctx->dsc_padding_params.dsc_hactive_padding < 32)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4681
dc_update_modified_pix_clock_for_dsc_with_padding(stream, &stream->timing, &pipe_ctx->dsc_padding_params);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4798
unsigned int vic = pipe_ctx->stream->timing.vic;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4799
unsigned int rid = pipe_ctx->stream->timing.rid;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4800
unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4813
color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4828
switch (stream->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4895
aspect = stream->timing.aspect_ratio;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4953
if (pipe_ctx->stream->timing.hdmi_vic != 0)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4955
format = stream->timing.timing_3d_format;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4959
switch (pipe_ctx->stream->timing.hdmi_vic) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5008
hdmi_info.bits.bar_top = (uint16_t)stream->timing.v_border_top;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5009
hdmi_info.bits.bar_bottom = (uint16_t)(stream->timing.v_total
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5010
- stream->timing.v_border_bottom + 1);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5011
hdmi_info.bits.bar_left = (uint16_t)stream->timing.h_border_left;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5012
hdmi_info.bits.bar_right = (uint16_t)(stream->timing.h_total
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5013
- stream->timing.h_border_right + 1);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5107
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5115
const struct dc_crtc_timing *tg = timing;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5144
&stream->timing,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5339
stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5344
switch (stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5360
stream->timing.display_color_depth >= COLOR_DEPTH_101010) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5479
if (!tg->funcs->validate_timing(tg, &stream->timing))
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5494
&stream->timing);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5814
h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5815
h_blank_end = h_blank_start - stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5821
divisible = (stream->timing.h_total % 2 == 0) &&
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5824
(stream->timing.h_sync_width % 2 == 0);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5878
if (sec_pipe->stream->timing.flags.DSC == 1) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
649
stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
650
stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
652
if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
653
stream1->timing.v_total > 60)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
655
if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
656
stream2->timing.v_total > 60)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
659
stream1->timing.h_total *
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
660
stream1->timing.v_total *
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
661
stream2->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
662
frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
663
frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
664
frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
681
if (stream1->timing.h_total != stream2->timing.h_total)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
684
if (stream1->timing.v_total != stream2->timing.v_total)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
687
if (stream1->timing.h_addressable
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
688
!= stream2->timing.h_addressable)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
691
if (stream1->timing.v_addressable
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
692
!= stream2->timing.v_addressable)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
695
if (stream1->timing.v_front_porch
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
696
!= stream2->timing.v_front_porch)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
699
if (stream1->timing.pix_clk_100hz
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
700
!= stream2->timing.pix_clk_100hz)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
1195
return (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
1241
if (stream->timing.v_total * stream->timing.h_total == 0)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
1244
int current_refresh_hz = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
1252
int safe_refresh_v_total = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, safe_refresh_hz*(long long)stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
1255
return (((int) stream->timing.v_total - safe_refresh_v_total) >= 0) ? (stream->timing.v_total - safe_refresh_v_total) : 0;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
1257
return ((safe_refresh_v_total - (int) stream->timing.v_total) >= 0) ? (safe_refresh_v_total - stream->timing.v_total) : 0;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
154
stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
156
memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
157
stream->timing.dsc_cfg.num_slices_h = 0;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
158
stream->timing.dsc_cfg.num_slices_v = 0;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
159
stream->timing.dsc_cfg.bits_per_pixel = 128;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
160
stream->timing.dsc_cfg.block_pred_enable = 1;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
161
stream->timing.dsc_cfg.linebuf_depth = 9;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
162
stream->timing.dsc_cfg.version_minor = 2;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
163
stream->timing.dsc_cfg.ycbcr422_simple = 0;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
65
(stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
72
pix_clk = stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
73
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
77
if (stream->timing.pixel_encoding != PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
78
switch (stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
94
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
95
stream->timing.h_addressable > 4096)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
961
stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
962
stream->timing.h_total,
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
963
stream->timing.v_total,
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
964
dc_pixel_encoding_to_str(stream->timing.pixel_encoding),
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
965
dc_color_depth_to_str(stream->timing.display_color_depth));
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
97
if (stream->timing.rid != 0)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
972
stream->timing.flags.DSC,
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
973
stream->timing.dsc_cfg.mst_pbn);
drivers/gpu/drm/amd/display/dc/dc.h
2141
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1264
cntl->data.line_time_in_ns = 1u + (uint32_t)(div64_u64(stream->timing.h_total * 1000000ull,
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1265
stream->timing.pix_clk_100hz / 10));
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1267
cntl->data.v_total_max = stream->adjust.v_total_max > stream->timing.v_total ?
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1269
stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
498
min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000);
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
500
config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
592
struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
594
struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
610
phantom_timing = &phantom_stream->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
692
pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
693
pipe_data->pipe_config.vblank_data.vblank_start = (uint16_t)(vblank_pipe->stream->timing.v_total -
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
694
vblank_pipe->stream->timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
695
pipe_data->pipe_config.vblank_data.vtotal = (uint16_t)vblank_pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
696
pipe_data->pipe_config.vblank_data.htotal = (uint16_t)vblank_pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
700
(uint16_t)(vblank_pipe->stream->timing.v_total -
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
701
vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable);
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
744
phantom_timing0 = &phantom_stream0->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
745
phantom_timing1 = &phantom_stream1->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
797
struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
804
phantom_timing = &phantom_stream->timing;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
807
pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
808
pipe_data->pipe_config.subvp_data.htotal = (uint16_t)subvp_pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
809
pipe_data->pipe_config.subvp_data.vtotal = (uint16_t)subvp_pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dc_dsc.h
102
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dc_dsc.h
109
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dc_dsc.h
116
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dc_dsc.h
85
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dc_dsc.h
94
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dc_dsc.h
98
uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
134
stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
137
stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
143
spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
drivers/gpu/drm/amd/display/dc/dc_stream.h
180
struct dc_crtc_timing timing;
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
566
(params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
567
(params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
568
&& !params->timing->dsc_cfg.ycbcr422_simple)) {
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
1025
&stream->timing);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
1030
&stream->timing,
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
1036
enc110, &stream->timing);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
1040
enc110, &stream->timing);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
1044
is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB;
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
983
m_vid_l *= param->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
382
copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
179
copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1116
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1125
ASSERT(timing != NULL);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1127
if (!timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1130
hsync_offset = timing->h_border_right + timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1131
h_sync_start = timing->h_addressable + hsync_offset;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1134
if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1138
if (timing->flags.INTERLACE == 1)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1146
if (timing->h_total > tg110->max_h_total ||
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1147
timing->v_total > tg110->max_v_total)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1150
h_blank = (timing->h_total - timing->h_addressable -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1151
timing->h_border_right -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1152
timing->h_border_left);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1157
if (timing->h_front_porch < tg110->min_h_front_porch)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1161
timing->h_addressable -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1162
timing->h_border_right -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1163
timing->h_sync_width);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1414
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1434
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1956
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1972
dce110_timing_generator_program_timing_generator(tg, timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1974
dce110_timing_generator_program_blanking(tg, timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
2023
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
2025
return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
2040
bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
2042
return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
257
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
268
if (timing->flags.HORZ_COUNT_BY_TWO)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
603
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
605
uint32_t vsync_offset = timing->v_border_bottom +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
606
timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
607
uint32_t v_sync_start = timing->v_addressable + vsync_offset;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
609
uint32_t hsync_offset = timing->h_border_right +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
610
timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
611
uint32_t h_sync_start = timing->h_addressable + hsync_offset;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
623
timing->h_total - 1,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
632
timing->v_total - 1,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
644
timing->v_total - 1,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
653
timing->v_total - 1,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
661
tmp = timing->h_total -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
662
(h_sync_start + timing->h_border_left);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
67
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
670
tmp = tmp + timing->h_addressable +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
671
timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
684
tmp = timing->v_total - (v_sync_start + timing->v_border_top);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
692
tmp = tmp + timing->v_addressable + timing->v_border_top +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
693
timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
70
if (timing->flags.INTERLACE == 1) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
71
if (timing->v_front_porch < 2)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
72
timing->v_front_porch = 2;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
74
if (timing->v_front_porch < 1)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
75
timing->v_front_porch = 1;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
129
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
203
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
247
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
259
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
274
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
292
bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
243
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
245
uint32_t vsync_offset = timing->v_border_bottom +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
246
timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
247
uint32_t v_sync_start = timing->v_addressable + vsync_offset;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
249
uint32_t hsync_offset = timing->h_border_right +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
250
timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
251
uint32_t h_sync_start = timing->h_addressable + hsync_offset;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
262
timing->h_total - 1,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
271
timing->v_total - 1,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
279
tmp = timing->h_total -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
280
(h_sync_start + timing->h_border_left);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
288
tmp = tmp + timing->h_addressable +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
289
timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
302
tmp = timing->v_total - (v_sync_start + timing->v_border_top);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
310
tmp = tmp + timing->v_addressable + timing->v_border_top +
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
311
timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
325
timing->h_sync_width,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
332
if (timing->flags.HSYNC_POSITIVE_POLARITY) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
351
timing->v_sync_width,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
358
if (timing->flags.VSYNC_POSITIVE_POLARITY) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
377
timing->flags.INTERLACE,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
386
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
392
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
436
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
452
dce110_timing_generator_program_timing_generator(tg, timing);
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
454
dce110_timing_generator_v_program_blanking(tg, timing);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
103
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
106
uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
108
(timing->v_total - timing->v_addressable -
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
109
timing->v_border_top - timing->v_border_bottom) *
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
115
timing,
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
121
timing->h_sync_width < tg110->min_h_sync_width ||
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
122
timing->v_sync_width < tg110->min_v_sync_width)
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
129
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
131
return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
431
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
435
uint32_t vsync_offset = timing->v_border_bottom +
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
436
timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
437
uint32_t v_sync_start = timing->v_addressable + vsync_offset;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
439
uint32_t hsync_offset = timing->h_border_right +
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
440
timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
441
uint32_t h_sync_start = timing->h_addressable + hsync_offset;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
447
timing->h_total - 1);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
452
timing->v_total - 1);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
460
timing->v_total - 1);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
465
timing->v_total - 1);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
467
tmp1 = timing->h_total -
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
468
(h_sync_start + timing->h_border_left);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
469
tmp2 = tmp1 + timing->h_addressable +
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
470
timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
477
tmp1 = timing->v_total - (v_sync_start + timing->v_border_top);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
478
tmp2 = tmp1 + timing->v_addressable + timing->v_border_top +
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
479
timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
625
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
629
timing->v_total - timing->v_addressable -
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
630
timing->v_border_bottom - timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
696
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
712
dce110_timing_generator_program_timing_generator(tg, timing);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
714
dce120_timing_generator_program_blanking(tg, timing);
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
755
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
109
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
119
program_pix_dur(tg, timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
121
dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
127
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
139
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
109
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
125
program_pix_dur(tg, timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
127
dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
133
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
153
if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
805
&stream->timing);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
810
&stream->timing,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
817
enc10, &stream->timing);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
820
is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB;
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
974
if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
982
m_vid_l *= param->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
459
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
461
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
463
two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
464
&& !timing->dsc_cfg.ycbcr422_simple);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
482
if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) {
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
490
m_vid_l *= param->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
79
return dcn30_link_encoder_validate_hdmi_frl_output(enc10, &stream->timing);
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
277
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
279
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
281
two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
282
&& !timing->dsc_cfg.ycbcr422_simple);
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
312
if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) {
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
321
m_vid_l *= param->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
235
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
237
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
239
two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
240
&& !timing->dsc_cfg.ycbcr422_simple);
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
259
if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
269
m_vid_l *= param->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
267
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
269
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
271
two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
272
&& !timing->dsc_cfg.ycbcr422_simple);
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
291
if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
301
m_vid_l *= param->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
256
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
258
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
260
two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
261
&& !timing->dsc_cfg.ycbcr422_simple);
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
279
if (is_two_pixels_per_containter(¶m->timing)) {
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
286
m_vid_l *= param->timing.pix_clk_100hz / pix_per_container / 10;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1033
v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1039
switch (pipe->stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1217
pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1218
pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1219
vesa_sync_start = pipe->stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1220
pipe->stream->timing.v_border_bottom +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1221
pipe->stream->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1223
asic_blank_end = (pipe->stream->timing.v_total -
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1225
pipe->stream->timing.v_border_top)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1226
* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1229
(pipe->stream->timing.v_border_top +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1230
pipe->stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1231
pipe->stream->timing.v_border_bottom)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1232
* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1247
(pipe->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1249
pipe->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1258
hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1259
hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
422
input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
423
+ pipe->stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
431
input->dest.htotal = pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
432
input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
434
- pipe->stream->timing.h_addressable
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
435
- pipe->stream->timing.h_border_left
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
436
- pipe->stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
438
input->dest.vtotal = pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
439
input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
441
- pipe->stream->timing.v_addressable
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
442
- pipe->stream->timing.v_border_bottom
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
443
- pipe->stream->timing.v_border_top;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
444
input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
738
hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
908
v->htotal[input_idx] = (float)pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
909
v->vtotal[input_idx] = (float)pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
910
v->vactive[input_idx] = (float)(pipe->stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
911
pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
912
v->v_sync_plus_back_porch[input_idx] = (float)(pipe->stream->timing.v_total
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
914
- pipe->stream->timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
915
v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
916
if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
923
v->viewport_width[input_idx] = (float)pipe->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
924
v->viewport_height[input_idx] = (float)pipe->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1210
&context->res_ctx.pipe_ctx[i].stream->timing,
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1356
struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1365
v_total = timing->v_total;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1366
front_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1377
pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1379
pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1384
(v_total - timing->v_addressable
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1385
- timing->v_border_top - timing->v_border_bottom) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1394
pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1396
- timing->h_addressable
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1397
- timing->h_border_left
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1398
- timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1401
- timing->v_addressable
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1402
- timing->v_border_top
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1403
- timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1404
pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1407
timing->h_addressable + timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1409
timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1410
pipes[pipe_cnt].pipe.dest.interlaced = (unsigned char)timing->flags.INTERLACE;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1411
pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1412
if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1482
switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1512
switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1523
if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1524
!res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1535
if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1536
pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1563
pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1566
pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
759
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
785
if (timing->flags.DSC &&
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
814
if (timing->flags.DSC && timing->rid > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
817
frl_params->f_pixel_clock_nominal = (double)timing->pix_clk_100hz * 100;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
818
frl_params->h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
819
frl_params->h_blank = timing->h_total - frl_params->h_active;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
820
frl_params->vic = timing->vic;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
824
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
830
if (timing->flags.DSC) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
832
frl_params->slices = timing->dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
835
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && frl_params->slice_width % 2 != 0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
837
frl_params->bpp_target = timing->dsc_cfg.bits_per_pixel / 16.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
76
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
79
void hpo_fpu_enc3_validate_hdmi_frl_output_timing(const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
284
static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
288
(((double)timing->h_total * 1000.0) /
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
289
((double)timing->pix_clk_100hz / 10.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
296
static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
300
v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
301
v_blank = timing->v_total - v_active;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
302
v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
323
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
330
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
332
num_lines = micro_sec_to_vert_lines(dcn3_14_ip.VBlankNomDefaultUS, timing);
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
337
pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
339
v_back_porch = get_vertical_back_porch(timing);
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
341
pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
348
max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
370
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
375
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1005
refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1006
pipe->stream->timing.v_total * (uint64_t)pipe->stream->timing.h_total - (uint64_t)1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1007
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1008
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1348
if (stream->timing.pix_clk_100hz * 100 <= DCN3_2_VMIN_DISPCLK_HZ)
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1886
if (sec_pipe->stream->timing.flags.DSC == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3380
refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3381
(uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3382
refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3383
refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3428
refresh_rate = (unsigned int)((pipe_ctx->stream->timing.pix_clk_100hz * 100 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3429
pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3430
/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total));
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3438
refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3439
pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3440
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total));
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3560
blank_us = (unsigned int)(((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3561
(double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
505
(ref_pipe->stream->timing.pix_clk_100hz * 100) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
506
(double)ref_pipe->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
542
phantom_stream->timing.v_addressable = phantom_vactive;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
543
phantom_stream->timing.v_front_porch = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
544
phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
545
phantom_stream->timing.v_front_porch +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
546
phantom_stream->timing.v_sync_width +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
548
phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
621
refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
622
pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
623
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total));
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
634
!(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
650
unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
651
(double)(stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
749
microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
750
phantom->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
753
time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
754
(double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
768
vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
769
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
770
vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
771
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
772
vblank1_us = (int32_t)((((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
773
subvp_pipes[0]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
774
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
775
vblank2_us = (int32_t)((((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
776
subvp_pipes[1]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
777
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
855
main_timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
856
phantom_timing = &phantom_stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
857
drr_timing = &drr_pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
948
main_timing = &subvp_pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
949
phantom_timing = &phantom_stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
950
vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
415
static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
419
(((double)timing->h_total * 1000.0) /
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
420
((double)timing->pix_clk_100hz / 10.0));
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
427
static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
431
v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
432
v_blank = timing->v_total - v_active;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
433
v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
456
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
464
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
466
num_lines = micro_sec_to_vert_lines(dcn3_5_ip.VBlankNomDefaultUS, timing);
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
467
v_back_porch = get_vertical_back_porch(timing);
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
471
pipe->stream->adjust.v_total_min > timing->v_total) {
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
474
pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
478
pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
485
max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
507
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
513
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
447
static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
451
(((double)timing->h_total * 1000.0) /
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
452
((double)timing->pix_clk_100hz / 10.0));
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
459
static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
463
v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
464
v_blank = timing->v_total - v_active;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
465
v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
488
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
496
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
498
num_lines = micro_sec_to_vert_lines(dcn3_51_ip.VBlankNomDefaultUS, timing);
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
499
v_back_porch = get_vertical_back_porch(timing);
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
503
pipe->stream->adjust.v_total_min > timing->v_total) {
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
506
pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
510
pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
517
max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
539
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
545
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
10001
mode_lib->ms.cache_display_cfg.timing.VActive,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2712
display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2713
if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2714
display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6284
struct dml_timing_cfg_st *timing,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6291
dml_float_t line_time_us = (dml_float_t) timing->HTotal[plane_idx] / timing->PixelClock[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6292
dml_uint_t vblank_actual = timing->VTotal[plane_idx] - timing->VActive[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6294
dml_uint_t vblank_nom_default_in_line = MicroSecToVertLines(vblank_nom_default_us, timing->HTotal[plane_idx],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6295
timing->PixelClock[plane_idx]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6303
timing->VTotal[plane_idx] - timing->VActive[plane_idx] - timing->VFrontPorch[plane_idx] + 2);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6310
if (timing->Interlace[plane_idx] && !ptoi_supported)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6316
dml_print("DML::%s: VBlankNom = %u\n", __func__, timing->VBlankNom[plane_idx]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6467
mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6476
myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6485
myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6487
myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6488
myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6489
myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6534
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6552
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6553
mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.VRatioPreY[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6666
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6768
CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6789
CalculateWatermarks_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6790
CalculateWatermarks_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6791
CalculateWatermarks_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6792
CalculateWatermarks_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7002
mode_lib->ms.ReadBandwidthLuma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * dml_ceil(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7003
mode_lib->ms.ReadBandwidthChroma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * dml_ceil(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7011
* mode_lib->ms.cache_display_cfg.timing.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7012
/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7017
* mode_lib->ms.cache_display_cfg.timing.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7018
/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7075
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7189
CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7229
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7238
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7252
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7261
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7281
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7282
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7386
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7393
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7501
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_lib->ms.ip.ptoi_supported == true)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7554
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7555
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7628
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 4 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7634
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 2 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7640
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7658
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7659
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7663
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7728
CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7767
mode_lib->ms.cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7826
s->SurfParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7839
s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7840
s->SurfParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7919
(dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7948
mode_lib->ms.cache_display_cfg.timing.PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7973
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / mode_lib->ms.RequiredDISPCLK[j];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7988
mode_lib->ms.cache_display_cfg.timing.HTotal[m]) / mode_lib->ms.RequiredDISPCLK[j]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8006
&mode_lib->ms.cache_display_cfg.timing,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8062
if (mode_lib->ms.cache_display_cfg.timing.RefreshRate[k] > 120)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8073
UseMinimumDCFCLK_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8096
UseMinimumDCFCLK_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8097
UseMinimumDCFCLK_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8100
UseMinimumDCFCLK_params->Interlace = mode_lib->ms.cache_display_cfg.timing.Interlace;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8116
UseMinimumDCFCLK_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8117
UseMinimumDCFCLK_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8464
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8471
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8483
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8508
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8588
mode_lib->ms.cache_display_cfg.timing.HActive,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8603
locals->ReadBandwidthSurfaceLuma[k] = locals->SwathWidthSingleDPPY[k] * locals->BytePerPixelY[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8604
locals->ReadBandwidthSurfaceChroma[k] = locals->SwathWidthSingleDPPC[k] * locals->BytePerPixelC[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8651
CalculateSwathAndDETConfiguration_params->HActive = mode_lib->ms.cache_display_cfg.timing.HActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8688
mode_lib->ms.cache_display_cfg.timing.PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8727
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8728
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8732
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8776
s->SurfaceParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8789
s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8790
s->SurfaceParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8955
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8973
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8998
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9017
((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9027
&mode_lib->ms.cache_display_cfg.timing,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9073
mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9082
myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9091
myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9093
myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9094
myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9095
myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9186
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9203
locals->cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * locals->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9382
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9541
CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9562
CalculateWatermarks_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9563
CalculateWatermarks_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9564
CalculateWatermarks_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9565
CalculateWatermarks_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9602
locals->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9603
mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9604
locals->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9605
mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackFCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9625
mode_lib->ms.cache_display_cfg.timing.PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9657
mode_lib->ms.cache_display_cfg.timing.HTotal,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9663
mode_lib->ms.cache_display_cfg.timing.PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9709
mode_lib->ms.cache_display_cfg.timing.HTotal,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9714
mode_lib->ms.cache_display_cfg.timing.PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9786
s->Tvstartup_margin = (s->MaxVStartupLines[k] - locals->VStartupMin[k]) * mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9804
isInterlaceTiming = (mode_lib->ms.cache_display_cfg.timing.Interlace[k] && !mode_lib->ms.ip.ptoi_supported);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9809
s->dlg_vblank_start = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9810
mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9811
s->LSetup = dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9812
s->blank_lines_remaining = (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k]) - locals->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9822
s->old_MIN_DST_Y_NEXT_START = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9823
mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9824
+ dml_max(1.0, dml_ceil((dml_float_t) locals->WritebackDelay[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9825
+ dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9827
if (((locals->VUpdateOffsetPix[k] + locals->VUpdateWidthPix[k] + locals->VReadyOffsetPix[k]) / (double) mode_lib->ms.cache_display_cfg.timing.HTotal[k]) <=
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9829
dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9830
(int) (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9841
dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9842
dml_print("DML::%s: k=%u, VTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9843
dml_print("DML::%s: k=%u, VActive = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VActive[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9844
dml_print("DML::%s: k=%u, VFrontPorch = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9858
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9861
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9905
CalculateStutterEfficiency_params->Interlace = mode_lib->ms.cache_display_cfg.timing.Interlace;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9918
CalculateStutterEfficiency_params->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9919
CalculateStutterEfficiency_params->VTotal = mode_lib->ms.cache_display_cfg.timing.VTotal;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9920
CalculateStutterEfficiency_params->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9929
CalculateStutterEfficiency_params->VActive = mode_lib->ms.cache_display_cfg.timing.VActive;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9977
mode_lib->ms.cache_display_cfg.timing.Interlace,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9990
mode_lib->ms.cache_display_cfg.timing.HTotal,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9991
mode_lib->ms.cache_display_cfg.timing.VTotal,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9992
mode_lib->ms.cache_display_cfg.timing.PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h
679
struct dml_timing_cfg_st timing;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
537
void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
539
(void)timing;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
541
dml_print("DML: timing_cfg: plane=%d, HTotal = %d\n", i, timing->HTotal[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
542
dml_print("DML: timing_cfg: plane=%d, VTotal = %d\n", i, timing->VTotal[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
543
dml_print("DML: timing_cfg: plane=%d, HActive = %d\n", i, timing->HActive[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
544
dml_print("DML: timing_cfg: plane=%d, VActive = %d\n", i, timing->VActive[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
545
dml_print("DML: timing_cfg: plane=%d, VFrontPorch = %d\n", i, timing->VFrontPorch[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
546
dml_print("DML: timing_cfg: plane=%d, VBlankNom = %d\n", i, timing->VBlankNom[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
547
dml_print("DML: timing_cfg: plane=%d, RefreshRate = %d\n", i, timing->RefreshRate[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
548
dml_print("DML: timing_cfg: plane=%d, PixelClock = %f\n", i, timing->PixelClock[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
549
dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing->Interlace[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
550
dml_print("DML: timing_cfg: plane=%d, DRRDisplay = %d\n", i, timing->DRRDisplay[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h
60
__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
102
timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
103
timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
104
timing->h_front_porch = stream->timing.h_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
105
timing->v_front_porch = stream->timing.v_front_porch > min_v_front_porch ?
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
106
stream->timing.v_front_porch : min_v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
107
timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
109
timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
110
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
111
timing->pixel_clock_khz *= 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
112
timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
113
timing->v_total = stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
114
timing->h_sync_width = stream->timing.h_sync_width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
115
timing->interlaced = (stream->timing.flags.INTERLACE != 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
117
hblank_start = stream->timing.h_total - stream->timing.h_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
119
timing->h_blank_end = hblank_start - stream->timing.h_addressable - pipe_ctx->dsc_padding_params.dsc_hactive_padding
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
120
- stream->timing.h_border_left - stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
122
if (hblank_start < stream->timing.h_addressable)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
123
timing->h_blank_end = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
125
vblank_start = timing->v_total - timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
127
timing->v_blank_end = vblank_start - stream->timing.v_addressable
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
128
- stream->timing.v_border_top - stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
130
timing->drr_config.enabled = stream->ignore_msa_timing_param;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
131
timing->drr_config.drr_active_variable = stream->vrr_active_variable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
132
timing->drr_config.drr_active_fixed = stream->vrr_active_fixed;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
133
timing->drr_config.disallowed = !stream->allow_freesync;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
136
min_hardware_refresh_in_uhz = stream->timing.min_refresh_in_uhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
141
pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
144
(timing->h_total * (long long)calc_max_hardware_v_total(stream)));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
148
uint64_t min_refresh = max((uint64_t)stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
150
timing->drr_config.min_refresh_uhz = (unsigned long)min_refresh;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
155
timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
157
timing->drr_config.max_instant_vtotal_delta = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
159
if (stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
160
timing->dsc.enable = dml2_dsc_enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
161
timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
162
timing->dsc.dsc_compressed_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
164
timing->dsc.enable = dml2_dsc_disable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
166
switch (stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
168
timing->bpc = 6;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
171
timing->bpc = 8;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
174
timing->bpc = 10;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
177
timing->bpc = 12;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
180
timing->bpc = 14;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
183
timing->bpc = 16;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
186
timing->bpc = 9;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
189
timing->bpc = 11;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
192
timing->bpc = 8;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
196
timing->vblank_nom = timing->v_total - timing->v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
226
switch (stream->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
235
if (stream->timing.flags.DSC && !stream->timing.dsc_cfg.ycbcr422_simple)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
388
surface->plane0.width = stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
389
surface->plane0.height = stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
390
surface->plane1.width = stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
391
surface->plane1.height = stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
408
if (stream->timing.h_addressable > 3840)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
411
width = stream->timing.h_addressable; // 4K max
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
413
if (stream->timing.v_addressable > 2160)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
416
height = stream->timing.v_addressable; // 4K max
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
705
stream->dst.height >= stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
823
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
85
max_hw_v_total -= stream->timing.v_front_porch + 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
91
static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
96
const unsigned int min_v_front_porch = (stream->timing.flags.INTERLACE != 0) ? 2 : 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
256
memcpy(&phantom_stream->timing, &main_stream->timing, sizeof(phantom_stream->timing));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
261
phantom_stream->timing.v_front_porch = phantom_stream_descriptor->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
262
phantom_stream->timing.v_addressable = phantom_stream_descriptor->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
263
phantom_stream->timing.v_total = phantom_stream_descriptor->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
264
phantom_stream->timing.flags.DSC = 0; // phantom always has DSC disabled
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
267
phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
270
phantom_stream->src.height = (int)((double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h
425
struct dml2_timing_cfg timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
274
phantom->timing.v_total = meta->v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
275
phantom->timing.v_active = meta->v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
276
phantom->timing.v_front_porch = meta->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
277
phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
278
phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
279
phantom->timing.drr_config.enabled = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
292
(double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c
295
(double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10032
double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10088
line_time = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10255
l->DETBufferingTimeY = l->LinesInDETYRoundedDownToSwath * ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10269
bool isInterlaceTiming = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !p->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10273
l->FrameTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10274
l->VActiveTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10345
SinglePixelClock = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10346
SingleHTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10347
SingleVTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10348
} else if (SinglePixelClock != ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10349
SingleHTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10350
SingleVTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10588
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10654
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10655
mode_lib->mp.vactive_sw_bw_l[k] = mode_lib->mp.SwathWidthSingleDPPY[k] * mode_lib->mp.BytePerPixelY[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10656
mode_lib->mp.vactive_sw_bw_c[k] = mode_lib->mp.SwathWidthSingleDPPC[k] * mode_lib->mp.BytePerPixelC[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10724
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10725
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10729
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10759
s->SurfaceParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10772
s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10773
s->SurfaceParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11053
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->mp.Dispclk;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1107
l->TotalPixelRate += display_cfg->stream_descriptors[k].timing.pixel_clock_khz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1112
l->DETBudgetPerStream[k] = (unsigned int)((double) display_cfg->stream_descriptors[k].timing.pixel_clock_khz * MaxTotalDETInKByte / l->TotalPixelRate);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11138
s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11139
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11209
&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11269
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11274
myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11288
myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11290
myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11291
myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11292
myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11439
double line_time_us = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11440
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11596
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11807
mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11808
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11809
mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11810
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackFCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11820
DML_LOG_VERBOSE("DML::%s: DEBUG PixelClock = %ld kHz\n", __func__, (display_cfg->stream_descriptors[display_cfg->plane_descriptors[0].stream_index].timing.pixel_clock_khz));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11934
s->Tvstartup_margin = (s->MaxVStartupLines[k] - mode_lib->mp.VStartupMin[k]) * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11948
isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11953
s->dlg_vblank_start = ((isInterlaceTiming ? math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11954
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total) - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11955
s->LSetup = math_floor2(4.0 * mode_lib->mp.TSetup[k] / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11956
s->blank_lines_remaining = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active) - mode_lib->mp.VStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11966
if (((mode_lib->mp.VUpdateOffsetPix[k] + mode_lib->mp.VUpdateWidthPix[k] + mode_lib->mp.VReadyOffsetPix[k]) / (double) display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) <=
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11968
math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11969
(int)(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11980
DML_LOG_VERBOSE("DML::%s: k=%u, HTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11981
DML_LOG_VERBOSE("DML::%s: k=%u, VTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11982
DML_LOG_VERBOSE("DML::%s: k=%u, VActive = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11983
DML_LOG_VERBOSE("DML::%s: k=%u, VFrontPorch = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11997
(display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0].input_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11998
/ ((double)display_cfg->stream_descriptors[k].timing.pixel_clock_khz / 1000))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12493
l->timing = &display_cfg->stream_descriptors[display_cfg->plane_descriptors[l->plane_idx].stream_index].timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12499
l->htotal = l->timing->h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12500
l->hactive = l->timing->h_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12501
l->hblank_end = l->timing->h_blank_end;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12502
l->vblank_end = l->timing->v_blank_end;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12503
l->interlaced = l->timing->interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12504
l->pclk_freq_in_mhz = (double)l->timing->pixel_clock_khz / 1000;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12882
base_programming->htotal = (uint16_t)stream_descriptor->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12883
base_programming->vtotal = (uint16_t)stream_descriptor->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12885
stream_descriptor->timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12887
stream_descriptor->timing.v_front_porch -
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12888
stream_descriptor->timing.v_active);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12889
base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12898
stream_descriptor->timing.v_front_porch -
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13026
(int)(display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_idx].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13027
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_idx].stream_index].timing.pixel_clock_khz / 1000) * mode_lib->ms.TWait[plane_idx]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13049
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.pixel_clock_khz / 1000));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13050
phantom_processing_delay_lines = (unsigned int)(phantom_processing_delay_pix / (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13052
display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13064
main_v_blank_lines = display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
161
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
162
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
178
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
179
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
184
DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3559
double pixel_rate_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3703
const struct dml2_timing_cfg *timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3709
double line_time_us = (double)timing->h_total / ((double)timing->pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3710
unsigned int vblank_actual = timing->v_total - timing->v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3712
unsigned int vblank_avail = (timing->vblank_nom == 0) ? vblank_nom_default_in_line : (unsigned int)timing->vblank_nom;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3716
if (timing->interlaced && !ptoi_supported)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3721
DML_LOG_VERBOSE("DML::%s: VBlankNom = %lu\n", __func__, timing->vblank_nom);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
436
PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
437
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && ptoi_supported == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6820
double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6821
double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6832
double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6833
double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7025
((double)p->display_cfg->stream_descriptors[stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7026
(double)p->display_cfg->stream_descriptors[stream_index].timing.pixel_clock_khz * 1000.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7345
(unsigned int)math_ceil(watermarks->DRAMClockChangeWatermark / ((double)stream_descriptor->timing.h_total * 1000.0 / (double)stream_descriptor->timing.pixel_clock_khz));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7347
if (pstate_keepout_dst_lines[i] > stream_descriptor->timing.v_total - 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7348
pstate_keepout_dst_lines[i] = stream_descriptor->timing.v_total - 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7457
s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7480
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7485
myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7499
myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7501
myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7502
myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7503
myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7844
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8147
mode_lib->ms.vactive_sw_bw_l[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8148
mode_lib->ms.vactive_sw_bw_c[k] = mode_lib->ms.SwathWidthCSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8151
display_cfg->plane_descriptors[k].cursor.cursor_bpp / 8.0 / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8154
DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthLuma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8155
DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthChroma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * math_ceil2(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio / 2.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8167
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8168
/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 8.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8173
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8174
/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8219
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8435
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8436
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8438
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8439
mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8459
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8469
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8480
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8490
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8507
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8508
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8517
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8555
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8565
DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8651
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8658
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8739
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8742
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8796
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8797
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
881
SwathWidthY[k] = (unsigned int)(math_min2((double)SwathWidthSingleDPPY[k], math_round((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active / odm_hactive_factor * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio)));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8874
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active > s->NumDSCUnitRequired * (unsigned int)mode_lib->ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
889
DML_LOG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8895
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8896
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8900
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8966
s->SurfParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8979
s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8980
s->SurfParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9164
double line_time_us = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9250
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->ms.RequiredDISPCLK;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9258
bool isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9262
&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9303
unsigned long long refresh_rate = (unsigned long long) ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz * 1000 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9304
(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9305
(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9720
double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9850
p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9851
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9852
p->TimePerMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9853
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9854
p->TimePerMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9855
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9875
p->TimePerChromaMetaChunkNominal[k] = p->meta_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9876
p->TimePerChromaMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9877
p->TimePerChromaMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9910
pixel_clock_mhz = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9913
p->time_per_tdlut_group[k] = 2 * p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / p->tdlut_groups_per_2row_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9942
p->time_per_pte_group_nom_luma[k] = p->DST_Y_PER_PTE_ROW_NOM_L[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9943
p->time_per_pte_group_vblank_luma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9944
p->time_per_pte_group_flip_luma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9968
p->time_per_pte_group_nom_chroma[k] = p->DST_Y_PER_PTE_ROW_NOM_C[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9969
p->time_per_pte_group_vblank_chroma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9970
p->time_per_pte_group_flip_chroma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
1596
const struct dml2_timing_cfg *timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
340
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
341
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
357
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
358
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
364
DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
580
phantom->timing.v_total = meta->v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
581
phantom->timing.v_active = meta->v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
582
phantom->timing.v_front_porch = meta->v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
583
phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
584
phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
585
phantom->timing.drr_config.enabled = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
598
(double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
601
(double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
792
double otg_vline_time_us = (double)stream->timing.h_total / (double)stream->timing.pixel_clock_khz * 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
793
double non_vtotal = stream->timing.vblank_nom + stream->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
475
if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream_descriptors[remap_array[i]].timing, sizeof(struct dml2_timing_cfg))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
483
if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
217
if (memcmp(&display_config->display_config.stream_descriptors[remap_array[i - 1]].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
218
&display_config->display_config.stream_descriptors[remap_array[i]].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
226
if (display_config->display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
250
static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
257
unsigned long h_blank_start = timing->h_total - timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
259
return (timing->h_total % denominator == 0) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
261
(timing->h_blank_end % denominator == 0) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
262
(timing->h_sync_width % denominator == 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
319
else if (!is_h_timing_divisible_by(&display_config->stream_descriptors[i].timing, 2))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
352
odm_load = display_config->stream_descriptors[i].timing.pixel_clock_khz
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
410
if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
429
if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1007
&display_config->display_config.stream_descriptors[j].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1080
if (!stream_descriptor->timing.drr_config.enabled)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1095
if (stream_descriptor->timing.drr_config.max_instant_vtotal_delta > 0 &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1096
stream_pstate_meta->method_drr.stretched_vtotal - stream_pstate_meta->nom_vtotal > (int)stream_descriptor->timing.drr_config.max_instant_vtotal_delta) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1165
if (stream_descriptor->timing.interlaced) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1172
if (microschedule_vlines >= stream_descriptor->timing.v_active ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1556
stream_descriptor->timing.drr_config.enabled &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1557
(stream_descriptor->timing.drr_config.drr_active_fixed || stream_descriptor->timing.drr_config.drr_active_variable)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1562
stream_descriptor->timing.drr_config.enabled &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1563
stream_descriptor->timing.drr_config.drr_active_variable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1568
stream_descriptor->timing.drr_config.enabled &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1569
stream_descriptor->timing.drr_config.drr_active_variable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1574
!stream_descriptor->timing.drr_config.enabled ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1575
stream_descriptor->timing.drr_config.disallowed)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1580
(!stream_descriptor->timing.drr_config.enabled ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1581
(!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable)) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1583
stream_descriptor->timing.drr_config.enabled &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1584
stream_descriptor->timing.drr_config.drr_active_variable))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1702
const struct dml2_timing_cfg *timing = &stream_descriptor->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1712
stream_pstate_meta->otg_vline_time_us = (double)timing->h_total / timing->pixel_clock_khz * 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1713
stream_pstate_meta->nom_vtotal = stream_descriptor->timing.vblank_nom + stream_descriptor->timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1714
stream_pstate_meta->nom_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1715
(stream_pstate_meta->nom_vtotal * timing->h_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1718
stream_pstate_meta->vblank_start = timing->v_blank_end + timing->v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1720
if (stream_descriptor->timing.drr_config.enabled == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1721
if (stream_descriptor->timing.drr_config.min_refresh_uhz != 0.0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1722
stream_pstate_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1723
((double)stream_descriptor->timing.drr_config.min_refresh_uhz * stream_descriptor->timing.h_total) * 1e9);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1726
stream_pstate_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1727
(48000000.0 * stream_descriptor->timing.h_total) * 1e9);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1732
stream_pstate_meta->min_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1733
(stream_pstate_meta->max_vtotal * timing->h_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1760
timing->v_active - math_max2(1.0, stream_pstate_meta->min_allow_width_otg_vlines) - stream_pstate_meta->blackout_otg_vlines));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1770
timing->v_blank_end + stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1809
stream_descriptor->timing.v_blank_end +
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2319
line_time_us = (double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total / (in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2320
vblank_nom_time_us = line_time_us * in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
740
static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
747
unsigned long h_blank_start = timing->h_total - timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
749
return (timing->h_total % denominator == 0) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
751
(timing->h_blank_end % denominator == 0) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
752
(timing->h_sync_width % denominator == 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
811
else if (!is_h_timing_divisible_by(&display_config->stream_descriptors[i].timing, 2))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
846
odm_load = display_config->stream_descriptors[i].timing.pixel_clock_khz
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
904
if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
923
if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
982
master_timing = &display_config->display_config.stream_descriptors[i].timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c
549
temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane0.h_ratio * stream->timing.h_active / odm_combine_factor);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c
555
temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane1.h_ratio * stream->timing.h_active / odm_combine_factor);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c
595
stream->timing.h_active, num_dpps, scaling_transform,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c
606
stream->timing.h_active, num_dpps, scaling_transform,
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
247
refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 +
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
248
pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
249
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total));
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
267
unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
268
(double)(stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
381
microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
382
phantom->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
385
time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
386
(double)(phantom->timing.pix_clk_100hz * 100) * 1000000) +
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
405
vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
406
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
407
vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
408
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
409
vblank1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
410
subvp_pipes[0]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
411
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100) * 1000000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
412
vblank2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
413
subvp_pipes[1]->stream->timing.h_total) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
414
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100) * 1000000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
476
main_timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
477
phantom_timing = &phantom_stream->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
576
schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
579
main_timing = &subvp_pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
580
phantom_timing = &phantom_stream->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
581
vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
702
(ref_pipe->stream->timing.pix_clk_100hz * 100) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
703
(double)ref_pipe->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
71
mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) /
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
712
phantom_stream->timing.v_front_porch = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
714
line_time = phantom_stream->timing.h_total / ((double)phantom_stream->timing.pix_clk_100hz * 100);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
715
fp_and_sync_width_time = (phantom_stream->timing.v_front_porch + phantom_stream->timing.v_sync_width) * line_time;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
729
phantom_stream->timing.v_addressable = phantom_vactive;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
731
phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
732
phantom_stream->timing.v_front_porch +
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
733
phantom_stream->timing.v_sync_width +
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
735
phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
747
memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
804
phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1020
if (in->timing.h_addressable > 3840)
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1023
width = in->timing.h_addressable; // 4K max
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1025
if (in->timing.v_addressable > 2160)
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1028
height = in->timing.v_addressable; // 4K max
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1346
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1411
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
762
out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
763
out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
764
out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
765
out->VFrontPorch[location] = in->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
766
out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
767
if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
769
out->HTotal[location] = in->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
770
out->VTotal[location] = in->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
771
out->Interlace[location] = (in->timing.flags.INTERLACE != 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
772
hblank_start = in->timing.h_total - in->timing.h_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
774
- in->timing.h_addressable
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
775
- in->timing.h_border_left
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
776
- in->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
777
vblank_start = in->timing.v_total - in->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
779
- in->timing.v_addressable
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
780
- in->timing.v_border_top
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
781
- in->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
791
out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
794
out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
818
switch (in->timing.display_color_depth) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
848
switch (in->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
859
if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple)
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
871
if (in->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
872
out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
895
out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
905
out->SurfaceWidthY[location] = in->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
906
out->SurfaceHeightY[location] = in->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
907
out->SurfaceWidthC[location] = in->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
908
out->SurfaceHeightC[location] = in->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
245
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
247
hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
248
vactive = timing->v_addressable + timing->v_border_bottom + timing->v_border_top;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
249
hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
250
vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
252
hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
253
vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
265
pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
266
pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
271
pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
272
pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
273
pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
557
(stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
559
stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
204
struct dml_timing_cfg_st *timing = &mode_lib->ms.cache_display_cfg.timing;
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
211
dml_uint_t htotal = timing->HTotal[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
212
dml_uint_t hactive = timing->HActive[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
213
dml_uint_t hblank_end = timing->HBlankEnd[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
214
dml_uint_t vblank_end = timing->VBlankEnd[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
215
dml_bool_t interlaced = timing->Interlace[plane_idx];
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
216
dml_float_t pclk_freq_in_mhz = (dml_float_t) timing->PixelClock[plane_idx];
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
100
if (timing->flags.DSC)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
101
return dc_dsc_stream_bandwidth_in_kbps(timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
102
timing->dsc_cfg.bits_per_pixel,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
103
timing->dsc_cfg.num_slices_h,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
104
timing->dsc_cfg.is_dp);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
106
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1106
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1129
dc_fixpt_div_int(dc_fixpt_from_int(dsc_div_by_10_round_up(timing->pix_clk_100hz)),
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1131
dc_fixpt_div_int(dc_fixpt_from_int(timing->h_addressable + timing->h_border_left + timing->h_border_right),
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1238
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1248
timing, num_slices_h, is_dp);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1253
bpp_x16 = dc_fixpt_div_int(bpp_x16, timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1300
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1307
uint32_t h_active = timing->h_addressable;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1308
uint32_t h_blank = timing->h_total - timing->h_addressable;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
131
kbps = timing->pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
134
if (timing->flags.Y_ONLY != 1) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1352
if (timing->display_color_depth == COLOR_DEPTH_101010)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1354
if (timing->display_color_depth == COLOR_DEPTH_121212)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1358
if (timing->pixel_encoding == PIXEL_ENCODING_RGB ||
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1359
timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1362
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
137
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1375
pixel_clock = dc_fixpt_div_int(dc_fixpt_from_int(timing->pix_clk_100hz), 10000);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
139
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1416
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_width % 2 != 0) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
144
kbps = apply_128b_132b_stream_overhead(timing, kbps);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1455
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1459
uint32_t preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
147
timing->vic == 0 && timing->hdmi_vic == 0 &&
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1472
uint32_t specs_preferred_bpp_x16 = hdmi_dsc_get_bpp(timing, dsc_caps);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1475
if (timing->vic) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
148
timing->frl_uncompressed_video_bandwidth_in_kbps != 0)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1483
if (timing->vic == 0 && timing->hdmi_vic == 0)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1485
timing, num_slices_h, dsc_caps);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
149
kbps = timing->frl_uncompressed_video_bandwidth_in_kbps;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1510
range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing, link_encoding);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1513
range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1517
range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1535
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1546
num_slices_h, dsc_common_caps, timing, link_encoding, &range)) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1557
target_bandwidth_kbps, timing, num_slices_h,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1731
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1755
dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1756
pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1758
pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1767
is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1782
switch (timing->pixel_encoding) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1814
if (branch_max_throughput_mps && dsc_div_by_10_round_up(timing->pix_clk_100hz) > branch_max_throughput_mps * 1000)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1821
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1861
int pix_clk_per_slice_khz = dsc_div_by_10_round_up(timing->pix_clk_100hz) / min_slices_h;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1899
num_slices_h = hdmi_dsc_get_num_slices(timing);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1943
(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1946
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1965
timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
1997
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2004
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2006
min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2011
timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2019
uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2027
timing, num_slices_h, is_dp);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2029
actual_bandwidth_in_kbps = dc_fixpt_from_fraction(timing->pix_clk_100hz, 10);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2036
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2047
refresh_rate = dc_fixpt_from_int(timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2048
refresh_rate = dc_fixpt_div_int(refresh_rate, timing->h_total);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2049
refresh_rate = dc_fixpt_div_int(refresh_rate, timing->v_total);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2053
max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, timing->v_total);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2061
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2087
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2100
switch (timing->pixel_encoding) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
2109
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && link_encoding == DC_LINK_ENCODING_HDMI_FRL) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
318
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
325
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
331
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
351
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
363
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
501
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
511
if (timing->vic == 0 && timing->hdmi_vic == 0)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
514
vid_id = timing->vic;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
515
switch (timing->hdmi_vic) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
532
if (timing->pixel_encoding == PIXEL_ENCODING_RGB ||
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
533
timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
541
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
549
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
564
static int hdmi_dsc_get_num_slices(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
570
int slice_width = timing->h_addressable;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
573
if (timing->pixel_encoding == PIXEL_ENCODING_RGB ||
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
574
timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
577
adj_pix_clk_mhz = k_slice_adjust * timing->pix_clk_100hz / 10000 / 2;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
578
h_ratio_adj_pix_clk_mhz = adj_pix_clk_mhz * timing->h_addressable / timing->h_total;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
613
slice_width = timing->h_addressable / slice_target;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
62
const struct dc_crtc_timing *timing, const uint32_t kbps)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
620
static int hdmi_dsc_get_bpp(const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
639
if (timing->display_color_depth == COLOR_DEPTH_101010)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
641
if (timing->display_color_depth == COLOR_DEPTH_121212)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
645
if (timing->pixel_encoding == PIXEL_ENCODING_RGB ||
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
646
timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
649
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
661
num_slices = hdmi_dsc_get_num_slices(timing);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
665
slice_width = timing->h_addressable / num_slices;
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
686
preset_found = get_vic_preset_bpp(timing, &preset_bpp);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
69
if (!timing->flags.DSC) {
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
74
bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
79
overhead_factor = dc_fixpt_from_int(timing->h_addressable);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
932
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
94
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
947
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
949
min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
952
timing->pixel_encoding, &dsc_common_caps);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
955
is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
960
config.num_slices_h, &dsc_common_caps, timing, link_encoding, range);
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
966
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
970
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
472
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
480
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ||
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
481
(timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
482
&& !timing->dsc_cfg.ycbcr422_simple))
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
498
uint32_t dsc_pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
499
uint32_t h_back = timing->h_total - dsc_pic_width - timing->h_sync_width - timing->h_front_porch;
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
503
uint32_t h_cactive_bytes = timing->dsc_cfg.num_slices_h * (
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
504
(dsc_pic_width / timing->dsc_cfg.num_slices_h * timing->dsc_cfg.bits_per_pixel / 8 + 15) / 16);
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
529
emp_packet.sb[23] = (uint8_t)timing->h_front_porch; /* Hfront[7:0] */
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
530
emp_packet.sb[24] = (uint8_t)(timing->h_front_porch >> 8); /* Hfront[15:8] */
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
531
emp_packet.sb[25] = (uint8_t)timing->h_sync_width; /* Hsync[7:0] */
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
532
emp_packet.sb[26] = (uint8_t)(timing->h_sync_width >> 8); /* Hsync[15:8] */
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
837
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
851
timing,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
855
if (timing->display_color_depth == COLOR_DEPTH_888)
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
857
else if (timing->display_color_depth == COLOR_DEPTH_101010)
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
862
switch (timing->hdmi_vic) {
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
878
frl_params.allow_all_bpp = timing->dsc_cfg.is_vic_all_bpp;
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
879
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
881
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
888
hpo_fpu_enc3_validate_hdmi_frl_output_timing(timing, audio, &frl_params);
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
895
|| (timing->v_addressable + timing->v_border_top + timing->v_border_bottom) <= 576)
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.h
381
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.h
410
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
484
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
492
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ||
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
493
(timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
494
&& !timing->dsc_cfg.ycbcr422_simple))
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
526
uint32_t h_active_padding = timing->h_addressable % timing->dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
528
h_active_padding = timing->dsc_cfg.num_slices_h - h_active_padding;
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
530
uint32_t slice_width = (timing->h_addressable + h_active_padding) / timing->dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
531
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
533
h_active_padding += timing->dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
534
uint32_t dsc_pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right + h_active_padding;
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
535
uint32_t h_back = timing->h_total - dsc_pic_width - timing->h_sync_width - timing->h_front_porch + h_active_padding;
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
539
uint32_t h_cactive_bytes = timing->dsc_cfg.num_slices_h * (
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
541
timing->dsc_cfg.num_slices_h * timing->dsc_cfg.bits_per_pixel + 127) / 128);
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
566
emp_packet.sb[23] = (uint8_t)timing->h_front_porch; /* Hfront[7:0] */
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
567
emp_packet.sb[24] = (uint8_t)(timing->h_front_porch >> 8); /* Hfront[15:8] */
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
568
emp_packet.sb[25] = (uint8_t)timing->h_sync_width; /* Hsync[7:0] */
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
569
emp_packet.sb[26] = (uint8_t)(timing->h_sync_width >> 8); /* Hsync[15:8] */
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.h
287
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1110
hubp->cur_rect.w = param->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1111
hubp->cur_rect.h = param->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
186
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
192
unsigned int htotal = timing->h_total;
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
207
vblank_start = timing->v_total - timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
208
vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
350
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
355
hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
265
struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
362
struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
285
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
290
hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
96
struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1240
dto_params.timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1269
params.timing = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1400
struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1469
stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1476
stream->timing.h_addressable
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1477
+ stream->timing.h_border_left
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1478
+ stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1481
stream->timing.v_addressable
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1482
+ stream->timing.v_border_top
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1483
+ stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1488
(stream->timing.flags.INTERLACE != 0);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1491
(uint16_t)((stream->timing.pix_clk_100hz*100)/
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1492
(stream->timing.h_total*stream->timing.v_total));
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1495
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1504
stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1507
stream->timing.dsc_cfg.bits_per_pixel;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1510
stream->timing.dsc_cfg.num_slices_h;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1515
(stream->timing.pix_clk_100hz)) {
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1598
if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1655
&stream->timing,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1728
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1735
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1787
if (pipe_ctx->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2076
edp_stream->sink, &edp_stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2176
(stream->timing.h_total * 10) /
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2177
stream->timing.pix_clk_100hz +
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2412
params.source_view_width = pipe_ctx->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2413
params.source_view_height = pipe_ctx->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2750
pipe_ctx->stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3238
pipe_ctx->stream->timing.h_total,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3239
pipe_ctx->stream->timing.v_total,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3240
pipe_ctx->stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3324
.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3517
pipes[i].stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
670
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
691
.pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
692
.color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
725
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
739
timing->h_addressable
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
740
+ timing->h_border_left
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
741
+ timing->h_border_right;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
752
dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing);
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
126
params.source_view_width = pipe_ctx->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
127
params.source_view_height = pipe_ctx->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
155
pipe_ctx->stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
257
if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
404
pipe_ctx->stream->timing.h_total,
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
405
pipe_ctx->stream->timing.v_total,
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
406
pipe_ctx->stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1266
&stream->timing,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1295
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
143
lines_to_vupdate = stream->timing.v_total - vpos + vupdate_start;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
148
stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
152
vupdate_end += stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
154
if (lines_to_vupdate > stream->timing.v_total - vupdate_end + vupdate_start)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2031
(pipe_ctx->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2033
pipe_ctx->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2262
lines_to_vupdate = stream->timing.v_total - vpos + vupdate_start;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2267
stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2272
vupdate_end += stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2275
if (lines_to_vupdate > stream->timing.v_total - vupdate_end + vupdate_start)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2402
pipe->stream->timing.pix_clk_100hz * 100 /
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2403
pipe->stream->timing.h_total /
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2404
pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2505
grouped_pipes[i]->stream->timing.pix_clk_100hz =
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2565
grouped_pipes[master]->stream->timing.pix_clk_100hz,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2566
grouped_pipes[i]->stream->timing.pix_clk_100hz,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3211
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3273
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3373
if (context->streams[i]->timing.timing_3d_format
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3532
stream->timing.timing_3d_format;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3561
(stream->timing.flags.RIGHT_EYE_3D_POLARITY != 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3576
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3586
&stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3590
&stream->timing,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3706
.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3968
struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3970
if (timing->flags.INTERLACE == 1) {
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3971
if (timing->v_front_porch < 2)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3972
timing->v_front_porch = 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3974
if (timing->v_front_porch < 1)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3975
timing->v_front_porch = 1;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3981
const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4011
const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4015
*start_line = vupdate_pos - ((vupdate_pos / timing->v_total) * timing->v_total);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4017
*start_line = vupdate_pos + ((-vupdate_pos / timing->v_total) + 1) * timing->v_total - 1;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4018
*end_line = (*start_line + 2) % timing->v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4027
const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4038
*start_line = vline_pos - ((vline_pos / timing->v_total) * timing->v_total);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4040
*start_line = vline_pos + ((-vline_pos / timing->v_total) + 1) * timing->v_total - 1;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4041
*end_line = (*start_line + 2) % timing->v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4045
*end_line = (*start_line + 2) % timing->v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4086
params.timing = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4091
if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4092
params.timing.pix_clk_100hz /= 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1206
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1248
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1261
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1707
&pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1920
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2007
pipe_ctx->stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2479
&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2519
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2712
(pipe_ctx->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2714
pipe_ctx->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2771
pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2779
params.timing = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2790
params.timing.pix_clk_100hz /= 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2799
params.timing.pix_clk_100hz /= 4;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2801
params.timing.pix_clk_100hz /= 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2880
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2897
dto_params.timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3038
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3059
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3061
dto_params.timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3110
timing->h_addressable
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3111
+ timing->h_border_left
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3112
+ timing->h_border_right;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
774
flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
775
stream->timing.h_border_left -
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
776
stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
830
bool interlace = (stream->timing.flags.INTERLACE != 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
835
pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
892
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
894
dto_params.timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
912
&stream->timing,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
947
stream->timing.pixel_encoding,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
959
udelay(stream->timing.v_total * (stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz));
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
603
params.timing = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
609
if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing))
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
610
params.timing.pix_clk_100hz /= 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
67
(pipe_ctx->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
69
pipe_ctx->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1027
stream->adjust.v_total_max : stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1028
unsigned int refresh_hz = (unsigned int)div_u64((unsigned long long)stream->timing.pix_clk_100hz *
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1029
100LL, (v_total * stream->timing.h_total));
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
85
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
562
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
597
if (pipe_ctx->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
103
dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
104
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
105
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
106
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
108
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
193
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
214
update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
335
two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
344
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1044
stream->timing.pix_clk_100hz > 480000;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1070
dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1071
stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1072
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1073
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1074
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1076
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1163
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1171
pipe_ctx->stream->timing.pixel_encoding,
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1178
dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1205
two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1214
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1334
params.timing = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1344
if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1346
params.timing.pix_clk_100hz /= 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1357
params.timing.pix_clk_100hz /= 4;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1358
else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || params.opp_cnt > 1)
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1359
params.timing.pix_clk_100hz /= 2;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1476
struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1478
unsigned int frame_rate = timing->pix_clk_100hz / (timing->h_total * timing->v_total);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1526
struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1528
if (timing)
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1529
params.vertical_blank_start = timing->v_total - timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1552
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1563
pix_clk_mhz = timing->pix_clk_100hz / 10000;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
361
dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
362
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
363
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
364
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
366
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
454
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
476
update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1131
.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1552
&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1639
otg_master->stream->timing.flags.DSC != 0u);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1674
&otg_master->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1682
opp_heads[i]->stream->timing.pixel_encoding,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1717
if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1723
stream->timing.pix_clk_100hz > 480000;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1729
int num_slices_h = stream->timing.dsc_cfg.num_slices_h / opp_cnt;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1766
} else if (otg_master->stream_res.dsc && !otg_master->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1809
hwss_add_optc_set_odm_bypass(seq_state, otg_master->stream_res.tg, &otg_master->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1819
opp_heads[i]->stream->timing.pixel_encoding, resource_is_pipe_type(opp_heads[i], OTG_MASTER));
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1844
params.timing = pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2099
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2228
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2314
pipe_ctx->stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2400
hwss_add_tg_set_vtg_params(seq_state, pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2471
pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2840
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2854
&pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3269
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3286
stream->timing.display_color_depth,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3722
&pipe_ctx->global_sync, &pipe_ctx->stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
746
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
815
struct dc_crtc_timing patched_crtc_timing = stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
898
stream->timing.pixel_encoding,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
968
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
985
timing->h_addressable
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
986
+ timing->h_border_left
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
987
+ timing->h_border_right;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1477
&stream->timing);
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1481
&stream->timing,
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
1981
struct timing_generator *optc, struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
2243
struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
234
const struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
2434
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
313
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
673
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
856
const struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
204
const struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
170
struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
341
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
158
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
194
bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
78
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
111
struct dc_crtc_timing timing;
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
374
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
483
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
337
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
339
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
411
bool enable, const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
433
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
450
bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
499
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/inc/link_service.h
140
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
463
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
127
stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
132
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
139
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
145
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
150
&stream->timing);
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
101
(stream->timing.flags.DSC != 0),
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
52
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
61
timing->h_total - timing->h_addressable),
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
62
dc_fixpt_from_fraction(timing->pix_clk_100hz, 10));
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
98
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
42
temp_stream->timing.h_addressable = stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding;
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
43
temp_stream->timing.h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
52
&temp_stream->timing,
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1113
kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1465
dc_bandwidth_in_kbps_from_timing(&stream->timing,
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1857
bool is_vga_mode = (stream->timing.h_addressable == 640)
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1858
&& (stream->timing.v_addressable == 480);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1863
stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1893
(stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0));
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1905
display_color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1906
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1998
(stream->timing.pix_clk_100hz / 10));
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2167
stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2213
link, pipe_ctx->stream->timing.pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2271
stream->timing.pix_clk_100hz == 6627500) {
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2347
int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing,
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2454
if (pipe_ctx->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2574
!pipe_ctx->stream->timing.flags.DSC &&
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2607
if (pipe_ctx->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2639
if (pipe_ctx->stream->timing.flags.DSC &&
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2668
if (pipe_ctx->stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
645
if (pipe_ctx->stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
737
stream->timing.pix_clk_100hz > 480000;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
749
dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
750
stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
751
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
752
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
753
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
755
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
792
struct dc_crtc_timing patched_crtc_timing = stream->timing;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
799
dsc_cfg.pic_width = stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
839
pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
886
if (!pipe_ctx->stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
902
dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
903
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
904
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
905
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
907
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
931
pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, &dsc_packed_pps[0]);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
950
pipe_ctx->stream_res.hpo_frl_stream_enc, &stream->timing, NULL);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
961
if (!pipe_ctx->stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
984
if (!pipe_ctx->stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c
42
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
124
switch (timing->timing_3d_format) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
135
struct dc_crtc_timing outputTiming = *timing;
drivers/gpu/drm/amd/display/dc/link/link_validation.c
137
if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
144
if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
drivers/gpu/drm/amd/display/dc/link/link_validation.c
153
if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
drivers/gpu/drm/amd/display/dc/link/link_validation.c
156
if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
159
if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
162
if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
165
if (timing->display_color_depth == COLOR_DEPTH_666 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
168
else if (timing->display_color_depth == COLOR_DEPTH_888 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
171
else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
174
else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
177
else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
180
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
183
if (timing->display_color_depth == COLOR_DEPTH_888 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
186
else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
189
else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
192
else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
195
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
198
if (timing->display_color_depth == COLOR_DEPTH_888 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
201
else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
204
else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
207
else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
210
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
213
if (timing->display_color_depth == COLOR_DEPTH_888 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
216
else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
219
else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
222
else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
39
static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
42
uint32_t pxl_clk = timing->pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/link/link_validation.c
44
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
457
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
46
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
460
return dc_bandwidth_in_kbps_from_timing(timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
466
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
474
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
480
if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
481
timing->h_addressable == (uint32_t) 640 &&
drivers/gpu/drm/amd/display/dc/link/link_validation.c
482
timing->v_addressable == (uint32_t) 480)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
49
if (timing->display_color_depth == COLOR_DEPTH_101010)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
493
req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link));
drivers/gpu/drm/amd/display/dc/link/link_validation.c
499
timing->pix_clk_100hz > max_uncompressed_pixel_rate_100hz;
drivers/gpu/drm/amd/display/dc/link/link_validation.c
501
if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
51
else if (timing->display_color_depth == COLOR_DEPTH_121212)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
526
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
541
req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link));
drivers/gpu/drm/amd/display/dc/link/link_validation.c
573
timing, &audio_frl_check,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
58
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
595
} else if (frl_output_valid && timing->dsc_cfg.is_frl) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
607
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
622
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && link->dc->config.no_native422_support) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
628
if (max_pix_clk != 0 && get_tmds_output_pixel_clock_100hz(timing) > max_pix_clk)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
632
if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
drivers/gpu/drm/amd/display/dc/link/link_validation.c
640
timing))
drivers/gpu/drm/amd/display/dc/link/link_validation.c
648
pxl_clk_mhz = (timing->pix_clk_100hz + 10000 - 1) / 10000 ;
drivers/gpu/drm/amd/display/dc/link/link_validation.c
649
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
651
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
659
timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.c
67
if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
drivers/gpu/drm/amd/display/dc/link/link_validation.c
723
timing_bw = dp_get_timing_bandwidth_kbps(&stream->timing, link);
drivers/gpu/drm/amd/display/dc/link/link_validation.c
78
switch (timing->pixel_encoding) {
drivers/gpu/drm/amd/display/dc/link/link_validation.c
856
const struct dc_crtc_timing *timing = audio_params->crtc_timing;
drivers/gpu/drm/amd/display/dc/link/link_validation.c
882
timing->pix_clk_100hz, (long long)timing->h_total * 10);
drivers/gpu/drm/amd/display/dc/link/link_validation.c
99
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/link/link_validation.h
34
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/link/link_validation.h
40
const struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/link/link_validation.h
46
uint32_t link_timing_bandwidth_kbps(const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
1005
struct dc_crtc_timing tmp_timing = stream->timing;
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
978
uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
999
if (stream->timing.flags.DSC) {
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
139
((stream->timing.h_total * 1000000) /
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
140
(stream->timing.pix_clk_100hz / 10)) + 1;
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
321
cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
343
if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0)
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
344
cmd.pr_copy_settings.data.dsc_slice_height = (uint16_t)((pipe_ctx->stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
345
pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
346
pipe_ctx->stream->timing.dsc_cfg.num_slices_v);
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
64
(stream->timing.pix_clk_100hz * (u64)100),
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
65
stream->timing.v_total),
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
66
stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
1801
req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, link_encoding);
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1044
((stream->timing.h_total * 1000000) /
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1045
(stream->timing.pix_clk_100hz / 10)) + 1;
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
816
psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
818
timing.pix_clk_100hz * (u64)100),
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
819
stream->timing.v_total),
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
820
stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
842
psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1029
if (link_stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1056
struct dc_crtc_timing *timing,
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1060
uint32_t h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1061
uint32_t h_blank = timing->h_total - h_active;
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1064
borrow_params->borrow_mode = frl_modify_borrow_mode_for_dsc_padding(timing->pix_clk_100hz,
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1089
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1156
&stream->timing,
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1168
update_borrow_mode_from_dsc_padding(dsc_padding_params, &stream->timing, frl_link_settings);
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
920
frl_validate_mode_timing(link, &link_stream->timing, link_setting);
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
942
temp_stream->timing.h_addressable = link_stream->timing.h_addressable + link_pipe->dsc_padding_params.dsc_hactive_padding;
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
943
temp_stream->timing.h_total = link_stream->timing.h_total + link_pipe->dsc_padding_params.dsc_htotal_padding;
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
948
&temp_stream->timing,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
328
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
332
uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
333
uint32_t space1_size = timing->v_total - timing->v_addressable;
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
335
uint32_t space2_size = timing->v_total - timing->v_addressable;
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
353
if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE)
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
185
const struct dc_crtc_timing *timing);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1253
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1255
(void)timing;
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1286
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1289
optc1_enable_stereo(optc, timing, flags);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1616
bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1618
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1620
two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1621
&& !timing->dsc_cfg.ycbcr422_simple);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
52
static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
54
if (timing->flags.INTERLACE == 1) {
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
55
if (timing->v_front_porch < 2)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
56
timing->v_front_porch = 2;
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
58
if (timing->v_front_porch < 1)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
59
timing->v_front_porch = 1;
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
593
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
600
ASSERT(timing != NULL);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
602
v_blank = (timing->v_total - timing->v_addressable -
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
603
timing->v_border_top - timing->v_border_bottom);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
605
h_blank = (timing->h_total - timing->h_addressable -
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
606
timing->h_border_right -
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
607
timing->h_border_left);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
609
if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
610
timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
611
timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
612
timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
613
timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
614
timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
618
if (timing->flags.INTERLACE == 1)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
626
if (timing->h_total > optc1->max_h_total ||
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
627
timing->v_total > optc1->max_v_total)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
634
if (timing->h_sync_width < optc1->min_h_sync_width ||
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
635
timing->v_sync_width < optc1->min_v_sync_width)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
638
min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
100
timing->v_total > optc1->max_v_total)
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
106
if (timing->h_sync_width < optc1->min_h_sync_width ||
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
107
timing->v_sync_width < optc1->min_v_sync_width)
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
110
min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
70
const struct dc_crtc_timing *timing)
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
77
ASSERT(timing != NULL);
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
79
v_blank = (timing->v_total - timing->v_addressable -
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
80
timing->v_border_top - timing->v_border_bottom);
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
82
h_blank = (timing->h_total - timing->h_addressable -
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
83
timing->h_border_right -
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
84
timing->h_border_left);
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
86
if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
87
timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
88
timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
89
timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
90
timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
91
timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
99
if (timing->h_total > optc1->max_h_total ||
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
882
if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1089
if (context->streams[i]->timing.pixel_encoding
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1172
&stream->timing,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1184
&stream->timing);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1187
stream->timing.h_total,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1188
stream->timing.v_total,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1189
stream->timing.pix_clk_100hz / 10,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
897
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
908
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
910
pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
912
pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
913
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
916
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
919
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
933
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
994
context->streams[0]->timing.h_addressable,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
995
context->streams[0]->timing.v_addressable,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
996
context->streams[0]->timing.pix_clk_100hz / 10);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1034
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1043
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1045
pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1047
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1050
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1052
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1060
stream->clamping.c_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1061
stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1074
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1266
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1281
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1283
pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1285
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1290
else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1297
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1301
pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1314
stream->clamping.c_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1315
stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1337
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1480
if (result == DC_OK && dc_stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1560
if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1698
if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1701
dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1702
+ stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1703
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1704
+ stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1705
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1706
dsc_cfg.color_depth = stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1708
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1908
struct dc_crtc_timing timing;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1913
timing = pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1914
if (timing.h_border_left + timing.h_border_right
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1915
+ timing.v_border_top + timing.v_border_bottom > 0) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1968
(pipe->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1970
pipe->stream->timing.timing_3d_format ==
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1982
if (pipe->stream->timing.h_addressable > 7680 &&
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1983
pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1720
if (sec_pipe->stream->timing.flags.DSC == 1) {
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2049
struct dc_crtc_timing *timing = NULL;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2055
timing = &context->streams[0]->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2057
h_v_total = timing->h_total * timing->v_total;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2061
refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2076
struct dc_crtc_timing *timing = NULL;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2089
timing = &context->streams[0]->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2090
if (timing == NULL)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2093
sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2095
curr_v_blank = timing->v_total - timing->v_addressable;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2097
stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2099
scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2113
min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1812
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1817
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1831
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1840
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1840
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1845
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1855
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1864
&context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1868
split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1885
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1917
bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1954
&& (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1781
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1786
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1796
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1804
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1866
memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2044
struct dc_crtc_timing *timing;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2092
timing = &pipe->stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2098
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2159
switch (timing->display_color_depth) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
3043
if (free_pipe->stream->timing.flags.DSC == 1) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
218
if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
219
pipe->stream->timing.v_addressable != pipe->stream->src.height) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
224
if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
225
pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
266
if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
279
if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
432
struct dc_crtc_timing *timing = NULL;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
446
timing = &fpo_candidate_stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
447
if (timing == NULL)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
452
sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
454
curr_v_blank = timing->v_total - timing->v_addressable;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
456
stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
458
scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
474
min_refresh_100hz = fpo_candidate_stream->timing.min_refresh_in_uhz / 10000;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
490
struct dc_crtc_timing *timing = NULL;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
496
timing = &fpo_candidate_stream->timing;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
497
if (timing == NULL)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
500
h_v_total = timing->h_total * timing->v_total;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
504
refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
597
if (pipe->stream->timing.h_addressable == width &&
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
598
pipe->stream->timing.v_addressable == height &&
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
626
if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
667
refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
668
pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
669
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
670
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
728
refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
729
pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
730
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
731
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1868
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1888
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1890
pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1892
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1895
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1898
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1908
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1662
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1682
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1684
pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1686
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1689
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1692
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1702
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
60
context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) {
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
65
odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz);
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1627
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1647
stream->timing.display_color_depth;
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1649
pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1651
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1654
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1657
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1667
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1011
if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1012
min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1013
(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1046
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1047
in_out_vrr->adjust.v_total_max = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1102
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1103
in_out_vrr->adjust.v_total_max = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1105
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1106
in_out_vrr->adjust.v_total_max = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1108
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1109
in_out_vrr->adjust.v_total_max = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1138
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1139
in_out_vrr->adjust.v_total_max = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
120
* 10000) * stream->timing.h_total,
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
121
stream->timing.pix_clk_100hz));
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1296
unsigned int total = stream->timing.h_total * stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
1299
nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
131
max_hw_v_total -= stream->timing.v_front_porch + 1;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
145
return stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
151
if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) {
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
157
frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
158
stream->timing.h_total), 1000000);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
159
} else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) {
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
165
frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
166
stream->timing.h_total) + (1000000 - 1), 1000000);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
169
frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
170
stream->timing.h_total) + 500000, 1000000);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
174
if (v_total < stream->timing.v_total) {
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
175
ASSERT(v_total < stream->timing.v_total);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
176
v_total = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
198
h_total_up_scaled = stream->timing.h_total * 10000;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
200
* stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
204
duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
205
stream->timing.h_total), 1000);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
209
if (v_total < stream->timing.v_total) {
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
210
ASSERT(v_total < stream->timing.v_total);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
211
v_total = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
287
current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
288
stream->timing.h_total), 1000);
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
291
if (v_total < stream->timing.v_total)
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
292
v_total = stream->timing.v_total;
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
194
switch (stream->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
213
switch (stream->timing.pixel_encoding) {
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
252
switch (stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
303
if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
435
switch (stream->timing.timing_3d_format) {
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
521
format = stream->timing.timing_3d_format;
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
525
if (stream->timing.hdmi_vic != 0
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
526
&& stream->timing.h_total >= 3840
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
527
&& stream->timing.v_total >= 2160
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
566
ASSERT(stream->timing.hdmi_vic <= 0xFF);
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
567
info_packet->sb[5] = (uint8_t)stream->timing.hdmi_vic;
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
601
switch (stream->timing.display_color_depth) {
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
700
info_packet->sb[1] = (stream->timing.v_total & 0x00FF);
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
701
info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
779
(stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
782
timing.pix_clk_100hz * 100),
drivers/gpu/drm/amd/display/modules/power/power_abm.c
784
stream->timing.h_total);
drivers/gpu/drm/amd/display/modules/power/power_psr.c
174
stream->timing.pix_clk_100hz * 100),
drivers/gpu/drm/amd/display/modules/power/power_psr.c
175
stream->timing.v_total),
drivers/gpu/drm/amd/display/modules/power/power_psr.c
176
stream->timing.h_total);
drivers/gpu/drm/amd/display/modules/power/power_psr.c
186
stream->timing.pix_clk_100hz,
drivers/gpu/drm/amd/display/modules/power/power_psr.c
187
stream->timing.v_total,
drivers/gpu/drm/amd/display/modules/power/power_psr.c
188
stream->timing.h_total,
drivers/gpu/drm/amd/display/modules/power/power_psr.c
588
num_vblank_lines = stream->timing.v_total -
drivers/gpu/drm/amd/display/modules/power/power_psr.c
589
stream->timing.v_addressable -
drivers/gpu/drm/amd/display/modules/power/power_psr.c
590
stream->timing.v_border_top -
drivers/gpu/drm/amd/display/modules/power/power_psr.c
591
stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/modules/power/power_psr.c
593
vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
drivers/gpu/drm/amd/display/modules/power/power_psr.c
595
line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
drivers/gpu/drm/amd/display/modules/power/power_psr.c
644
!stream->timing.dsc_cfg.num_slices_v)
drivers/gpu/drm/amd/display/modules/power/power_psr.c
647
pic_height = stream->timing.v_addressable +
drivers/gpu/drm/amd/display/modules/power/power_psr.c
648
stream->timing.v_border_top + stream->timing.v_border_bottom;
drivers/gpu/drm/amd/display/modules/power/power_psr.c
650
if (stream->timing.dsc_cfg.num_slices_v == 0)
drivers/gpu/drm/amd/display/modules/power/power_psr.c
653
slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
drivers/gpu/drm/amd/display/modules/power/power_replay.c
691
* 10000) * stream->timing.h_total,
drivers/gpu/drm/amd/display/modules/power/power_replay.c
692
stream->timing.pix_clk_100hz));
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
704
struct dw_mipi_dsi_dphy_timing timing;
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
710
.timing = { \
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
786
struct dw_mipi_dsi_dphy_timing *timing)
drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
802
*timing = hstt_table[i].timing;
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
856
struct dw_mipi_dsi_dphy_timing timing;
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
861
dsi->lane_mbps, &timing);
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
877
PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
878
PHY_LP2HS_TIME_V131(timing.data_lp2hs));
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
882
PHY_HS2LP_TIME(timing.data_hs2lp) |
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
883
PHY_LP2HS_TIME(timing.data_lp2hs) |
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
888
PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
889
PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
354
struct dw_mipi_dsi2_phy_timing timing;
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
358
dsi2->lane_mbps, &timing);
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
362
regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(timing.data_lp2hs));
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
363
regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(timing.data_hs2lp));
drivers/gpu/drm/drm_edid.c
3114
typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
drivers/gpu/drm/drm_edid.c
3523
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3527
const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
drivers/gpu/drm/drm_edid.c
3573
mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
drivers/gpu/drm/drm_edid.c
3681
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3685
const u8 *t = (const u8 *)timing;
drivers/gpu/drm/drm_edid.c
3729
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3736
if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
drivers/gpu/drm/drm_edid.c
3764
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3778
if (!mode_in_range(newmode, drm_edid, timing) ||
drivers/gpu/drm/drm_edid.c
3793
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3807
if (!mode_in_range(newmode, drm_edid, timing) ||
drivers/gpu/drm/drm_edid.c
3822
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3837
if (!mode_in_range(newmode, drm_edid, timing) ||
drivers/gpu/drm/drm_edid.c
3851
do_inferred_modes(const struct detailed_timing *timing, void *c)
drivers/gpu/drm/drm_edid.c
3854
const struct detailed_non_pixel *data = &timing->data.other_data;
drivers/gpu/drm/drm_edid.c
3857
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
drivers/gpu/drm/drm_edid.c
3862
timing);
drivers/gpu/drm/drm_edid.c
3871
timing);
drivers/gpu/drm/drm_edid.c
3876
timing);
drivers/gpu/drm/drm_edid.c
3884
timing);
drivers/gpu/drm/drm_edid.c
3907
drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
3911
const u8 *est = ((const u8 *)timing) + 6;
drivers/gpu/drm/drm_edid.c
3936
do_established_modes(const struct detailed_timing *timing, void *c)
drivers/gpu/drm/drm_edid.c
3940
if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
drivers/gpu/drm/drm_edid.c
3943
closure->modes += drm_est3_modes(closure->connector, timing);
drivers/gpu/drm/drm_edid.c
3985
do_standard_modes(const struct detailed_timing *timing, void *c)
drivers/gpu/drm/drm_edid.c
3988
const struct detailed_non_pixel *data = &timing->data.other_data;
drivers/gpu/drm/drm_edid.c
3992
if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
drivers/gpu/drm/drm_edid.c
4042
const struct detailed_timing *timing)
drivers/gpu/drm/drm_edid.c
4054
cvt = &(timing->data.other_data.data.cvt[i]);
drivers/gpu/drm/drm_edid.c
4094
do_cvt_mode(const struct detailed_timing *timing, void *c)
drivers/gpu/drm/drm_edid.c
4098
if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
drivers/gpu/drm/drm_edid.c
4101
closure->modes += drm_cvt_modes(closure->connector, timing);
drivers/gpu/drm/drm_edid.c
4124
do_detailed_mode(const struct detailed_timing *timing, void *c)
drivers/gpu/drm/drm_edid.c
4129
if (!is_detailed_timing_descriptor(timing))
drivers/gpu/drm/drm_edid.c
4133
closure->drm_edid, timing);
drivers/gpu/drm/drm_edid.c
5543
match_identity(const struct detailed_timing *timing, void *data)
drivers/gpu/drm/drm_edid.c
5549
const char *desc = timing->data.other_data.data.str.str;
drivers/gpu/drm/drm_edid.c
5550
unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
drivers/gpu/drm/drm_edid.c
5553
!(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
drivers/gpu/drm/drm_edid.c
5554
is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
drivers/gpu/drm/drm_edid.c
5603
monitor_name(const struct detailed_timing *timing, void *data)
drivers/gpu/drm/drm_edid.c
5607
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
drivers/gpu/drm/drm_edid.c
5610
*res = timing->data.other_data.data.str.str;
drivers/gpu/drm/drm_edid.c
6543
void get_monitor_range(const struct detailed_timing *timing, void *c)
drivers/gpu/drm/drm_edid.c
6548
const struct detailed_non_pixel *data = &timing->data.other_data;
drivers/gpu/drm/drm_edid.c
6552
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
drivers/gpu/drm/drm_modes.c
1229
struct display_timing timing;
drivers/gpu/drm/drm_modes.c
1233
ret = of_get_display_timing(np, "panel-timing", &timing);
drivers/gpu/drm/drm_modes.c
1237
videomode_from_timing(&timing, &vm);
drivers/gpu/drm/mediatek/mtk_dsi.c
250
struct mtk_phy_timing *timing = &dsi->phy_timing;
drivers/gpu/drm/mediatek/mtk_dsi.c
252
timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
drivers/gpu/drm/mediatek/mtk_dsi.c
253
timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
drivers/gpu/drm/mediatek/mtk_dsi.c
254
timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
drivers/gpu/drm/mediatek/mtk_dsi.c
255
timing->da_hs_prepare;
drivers/gpu/drm/mediatek/mtk_dsi.c
256
timing->da_hs_trail = timing->da_hs_prepare + 1;
drivers/gpu/drm/mediatek/mtk_dsi.c
258
timing->ta_go = 4 * timing->lpx - 2;
drivers/gpu/drm/mediatek/mtk_dsi.c
259
timing->ta_sure = timing->lpx + 2;
drivers/gpu/drm/mediatek/mtk_dsi.c
260
timing->ta_get = 4 * timing->lpx;
drivers/gpu/drm/mediatek/mtk_dsi.c
261
timing->da_hs_exit = 2 * timing->lpx + 1;
drivers/gpu/drm/mediatek/mtk_dsi.c
263
timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
drivers/gpu/drm/mediatek/mtk_dsi.c
264
timing->clk_hs_post = timing->clk_hs_prepare + 8;
drivers/gpu/drm/mediatek/mtk_dsi.c
265
timing->clk_hs_trail = timing->clk_hs_prepare;
drivers/gpu/drm/mediatek/mtk_dsi.c
266
timing->clk_hs_zero = timing->clk_hs_trail * 4;
drivers/gpu/drm/mediatek/mtk_dsi.c
267
timing->clk_hs_exit = 2 * timing->clk_hs_trail;
drivers/gpu/drm/mediatek/mtk_dsi.c
269
timcon0 = FIELD_PREP(LPX, timing->lpx) |
drivers/gpu/drm/mediatek/mtk_dsi.c
270
FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
drivers/gpu/drm/mediatek/mtk_dsi.c
271
FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
drivers/gpu/drm/mediatek/mtk_dsi.c
272
FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
drivers/gpu/drm/mediatek/mtk_dsi.c
274
timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
drivers/gpu/drm/mediatek/mtk_dsi.c
275
FIELD_PREP(TA_SURE, timing->ta_sure) |
drivers/gpu/drm/mediatek/mtk_dsi.c
276
FIELD_PREP(TA_GET, timing->ta_get) |
drivers/gpu/drm/mediatek/mtk_dsi.c
277
FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
drivers/gpu/drm/mediatek/mtk_dsi.c
280
FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
drivers/gpu/drm/mediatek/mtk_dsi.c
281
FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
drivers/gpu/drm/mediatek/mtk_dsi.c
283
timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
drivers/gpu/drm/mediatek/mtk_dsi.c
284
FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
drivers/gpu/drm/mediatek/mtk_dsi.c
285
FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
drivers/gpu/drm/mediatek/mtk_dsi.c
512
struct mtk_phy_timing *timing = &dsi->phy_timing;
drivers/gpu/drm/mediatek/mtk_dsi.c
529
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
drivers/gpu/drm/mediatek/mtk_dsi.c
530
timing->da_hs_zero + timing->da_hs_exit + 3;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
178
struct dw_mipi_dsi_dphy_timing *timing)
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
187
timing->clk_lp2hs = 23;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
188
timing->clk_hs2lp = 38;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
189
timing->data_lp2hs = 15;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
190
timing->data_hs2lp = 9;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
194
timing->clk_lp2hs = 37;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
195
timing->clk_hs2lp = 135;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
196
timing->data_lp2hs = 50;
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
197
timing->data_hs2lp = 3;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
106
if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
107
timing->h_back_porch += timing->h_front_porch;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
108
timing->h_front_porch = 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
109
timing->v_back_porch += timing->v_front_porch;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
110
timing->v_front_porch = 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
117
if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
118
timing->width = timing->width >> 1;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
119
timing->xres = timing->xres >> 1;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
120
timing->h_back_porch = timing->h_back_porch >> 1;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
121
timing->h_front_porch = timing->h_front_porch >> 1;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
122
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
130
if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
137
timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
139
timing->xres = timing->width;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
140
timing->dce_bytes_per_line = msm_dsc_get_bytes_per_line(dsc);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
144
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
146
u32 active = timing->xres;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
148
timing->h_back_porch + timing->h_front_porch +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
149
timing->hsync_pulse_width;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
153
static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
155
u32 active = timing->yres;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
157
timing->v_back_porch + timing->v_front_porch +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
158
timing->vsync_pulse_width;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
178
const struct dpu_hw_intf_timing_params *timing)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
183
timing->v_back_porch + timing->vsync_pulse_width;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
192
} else if (timing->v_front_porch < needed_vfp_lines) {
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
198
actual_vfp_lines = timing->v_front_porch;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
206
timing->v_front_porch, timing->v_back_porch,
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
207
timing->vsync_pulse_width);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
226
const struct dpu_hw_intf_timing_params *timing)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
238
vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
240
vert_total = get_vertical_total(timing);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
241
horiz_total = get_horizontal_total(timing);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
47
struct dpu_hw_intf_timing_params *timing)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
49
memset(timing, 0, sizeof(*timing));
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
76
timing->width = mode->hdisplay; /* active width */
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
77
timing->height = mode->vdisplay; /* active height */
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
78
timing->xres = timing->width;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
79
timing->yres = timing->height;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
80
timing->h_back_porch = mode->htotal - mode->hsync_end;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
81
timing->h_front_porch = mode->hsync_start - mode->hdisplay;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
82
timing->v_back_porch = mode->vtotal - mode->vsync_end;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
83
timing->v_front_porch = mode->vsync_start - mode->vdisplay;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
84
timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
85
timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
86
timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
87
timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
88
timing->border_clr = 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
89
timing->underflow_clr = 0xff;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
90
timing->hsync_skew = mode->hskew;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
94
timing->hsync_polarity = 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
95
timing->vsync_polarity = 0;
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
98
timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
99
timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
100
timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
106
timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
110
timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
113
temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
116
timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
119
temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
120
temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
125
timing->shared_timings.clk_pre = temp >> 1;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
126
timing->shared_timings.clk_pre_inc_by_2 = true;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
128
timing->shared_timings.clk_pre =
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
130
timing->shared_timings.clk_pre_inc_by_2 = false;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
133
timing->ta_go = 3;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
134
timing->ta_sure = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
135
timing->ta_get = 4;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
138
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
139
timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
140
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
141
timing->hs_zero, timing->hs_prepare, timing->hs_trail,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
142
timing->hs_rqst);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
147
int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
168
timing->hs_halfbyte_en = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
170
timing->hs_halfbyte_en_ckln = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
172
timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
173
pd_ckln = timing->hs_prep_dly_ckln;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
174
timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
175
pd = timing->hs_prep_dly;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
187
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
189
temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
192
timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
197
timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
203
timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
205
temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
208
timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
213
timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
216
timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
220
timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
223
timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
228
timing->shared_timings.clk_post =
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
231
temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
232
temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
233
temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
234
(((timing->hs_rqst_ckln << 3) + 8) * ui);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
239
timing->shared_timings.clk_pre = temp >> 1;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
240
timing->shared_timings.clk_pre_inc_by_2 = 1;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
242
timing->shared_timings.clk_pre =
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
244
timing->shared_timings.clk_pre_inc_by_2 = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
247
timing->ta_go = 3;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
248
timing->ta_sure = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
249
timing->ta_get = 4;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
252
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
253
timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
254
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
255
timing->hs_zero, timing->hs_prepare, timing->hs_trail,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
256
timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
257
timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
258
timing->hs_prep_dly_ckln);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
263
int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
283
timing->hs_halfbyte_en = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
285
timing->hs_halfbyte_en_ckln = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
295
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
297
temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
30
static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
300
timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
305
timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
311
timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
313
temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
316
timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
321
timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
324
timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
328
timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
331
timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
336
timing->shared_timings.clk_post =
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
339
temp = 8 * ui + (timing->clk_prepare << 3) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
340
temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
341
temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
342
(((timing->hs_rqst_ckln << 3) + 8) * ui);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
347
timing->shared_timings.clk_pre = temp >> 1;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
348
timing->shared_timings.clk_pre_inc_by_2 = 1;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
350
timing->shared_timings.clk_pre =
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
352
timing->shared_timings.clk_pre_inc_by_2 = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
355
timing->shared_timings.byte_intf_clk_div_2 = true;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
357
timing->ta_go = 3;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
358
timing->ta_sure = 0;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
359
timing->ta_get = 4;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
362
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
363
timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
364
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
365
timing->hs_zero, timing->hs_prepare, timing->hs_trail,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
366
timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
367
timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
368
timing->hs_prep_dly_ckln);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
37
temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
373
int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
408
timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
410
temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
413
timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
418
timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
424
timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
426
temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
429
timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
434
timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
437
timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
441
timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
446
temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
449
timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
456
temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
459
timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
461
timing->shared_timings.byte_intf_clk_div_2 = true;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
464
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
465
timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
466
timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
471
int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
48
temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
49
timing->clk_zero = clk_z + 8 - temp;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
491
timing->clk_prepare = linear_inter(tmax, tmin, 50, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
495
timing->hs_rqst = linear_inter(tmax, tmin, 1, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
499
timing->hs_exit = linear_inter(tmax, tmin, 10, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
503
timing->shared_timings.clk_post = linear_inter(tmax, tmin, 80, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
507
timing->shared_timings.clk_pre = linear_inter(tmax, tmin, 20, 0, false);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
510
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
511
timing->clk_prepare, timing->hs_exit, timing->hs_rqst);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
52
int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
74
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
769
memcpy(shared_timings, &phy->timing.shared_timings,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
78
timing->hs_rqst = temp;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
80
timing->hs_rqst = max_t(s32, 0, temp - 2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
83
dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
88
timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
94
timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
97
temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
111
struct msm_dsi_dphy_timing timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
130
int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
132
int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
134
int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
136
int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
138
int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
797
struct msm_dsi_dphy_timing *timing = &phy->timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
804
if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
843
writel(timing->hs_halfbyte_en, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
844
writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
845
writel(timing->clk_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
846
writel(timing->clk_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
847
writel(timing->hs_exit, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
848
writel(timing->hs_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
849
writel(timing->hs_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
850
writel(timing->hs_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
851
writel(timing->hs_rqst, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
852
writel(timing->ta_go | (timing->ta_sure << 3), base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
853
writel(timing->ta_get, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
906
struct msm_dsi_dphy_timing *timing,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
911
u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
912
u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
913
u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
914
u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
915
u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
916
u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
917
timing->hs_halfbyte_en;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
919
writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
933
writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
934
DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
936
writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
945
struct msm_dsi_dphy_timing *timing = &phy->timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
953
if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
981
dsi_14nm_dphy_set_timing(phy, timing, i);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
11
struct msm_dsi_dphy_timing *timing)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
112
dsi_20nm_dphy_set_timing(phy, timing);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
15
writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
17
writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
19
writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
21
if (timing->clk_zero & BIT(8))
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
24
writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
26
writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
28
writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
30
writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
32
writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
34
writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
35
DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
37
writel(DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
70
struct msm_dsi_dphy_timing *timing = &phy->timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
78
if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
719
struct msm_dsi_dphy_timing *timing)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
723
writel(DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
725
writel(DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
727
writel(DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
729
if (timing->clk_zero & BIT(8))
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
732
writel(DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
734
writel(DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
736
writel(DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
738
writel(DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
740
writel(DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
742
writel(DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
743
DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
745
writel(DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
800
struct msm_dsi_dphy_timing *timing = &phy->timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
807
if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
818
dsi_28nm_dphy_set_timing(phy, timing);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
469
struct msm_dsi_dphy_timing *timing)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
473
writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
475
writel(DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
477
writel(DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
480
writel(DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
482
writel(DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
484
writel(DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
486
writel(DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
488
writel(DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
490
writel(DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
491
DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
493
writel(DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
575
struct msm_dsi_dphy_timing *timing = &phy->timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
580
if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
613
dsi_28nm_dphy_set_timing(phy, timing);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1149
writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1150
writel(timing->shared_timings.clk_pre,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1152
writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1153
writel(timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1155
writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1161
writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1162
writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1163
writel(timing->clk_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1164
writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1165
writel(timing->hs_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1166
writel(timing->hs_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1167
writel(timing->hs_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1168
writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1172
writel(timing->shared_timings.clk_pre,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1174
writel(timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
963
struct msm_dsi_dphy_timing *timing = &phy->timing;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
975
ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
977
ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
115
unsigned timing[11];
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
140
p->timing[0] = nvbios_rd32(bios, data + 0x00);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
141
p->timing[1] = nvbios_rd32(bios, data + 0x04);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
142
p->timing[2] = nvbios_rd32(bios, data + 0x08);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
143
p->timing[3] = nvbios_rd32(bios, data + 0x0c);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
144
p->timing[4] = nvbios_rd32(bios, data + 0x10);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
145
p->timing[5] = nvbios_rd32(bios, data + 0x14);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
146
p->timing[6] = nvbios_rd32(bios, data + 0x18);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
147
p->timing[7] = nvbios_rd32(bios, data + 0x1c);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
148
p->timing[8] = nvbios_rd32(bios, data + 0x20);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
149
p->timing[9] = nvbios_rd32(bios, data + 0x24);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
150
p->timing[10] = nvbios_rd32(bios, data + 0x28);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
33
u32 timing = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
37
timing = nvbios_rd32(bios, bit_P.offset + 4);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
40
timing = nvbios_rd32(bios, bit_P.offset + 8);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
42
if (timing) {
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
43
*ver = nvbios_rd08(bios, timing + 0);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
46
*hdr = nvbios_rd08(bios, timing + 1);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
47
*cnt = nvbios_rd08(bios, timing + 2);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
48
*len = nvbios_rd08(bios, timing + 3);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
51
return timing;
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
53
*hdr = nvbios_rd08(bios, timing + 1);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
54
*cnt = nvbios_rd08(bios, timing + 5);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
55
*len = nvbios_rd08(bios, timing + 2);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
56
*snr = nvbios_rd08(bios, timing + 4);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
57
*ssz = nvbios_rd08(bios, timing + 3);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
58
return timing;
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
73
u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
74
if (timing && idx < *cnt) {
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
75
timing += *hdr + idx * (*len + (snr * ssz));
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
79
return timing;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
85
CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
86
CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
87
WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
58
WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
59
CL = (ram->next->bios.timing[1] & 0x0000001f);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c
60
WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
140
} rammap, ramcfg, timing;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
170
timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
172
if (!timing.data || ver != 0x10 || timing.size < 0x19) {
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
177
timing.data = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
461
ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
462
ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
463
ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
464
ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
465
ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
466
ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
467
ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
468
ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
469
ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
470
ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
471
ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
566
data = (next->bios.timing[10] & 0x7f000000) >> 24;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
855
ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
856
ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
857
ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
858
ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
859
ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
860
ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
861
ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
862
ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
863
ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
864
ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
865
ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
896
data = (next->bios.timing[10] & 0x7f000000) >> 24;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
348
gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
374
timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
375
timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
379
timing[2] = (T(CWL) - 1) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
383
timing[3] = (cur3 & 0x00ff0000) |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
387
timing[4] = T(20) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
391
timing[5] = T(RFC) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
395
timing[6] = (0x5a + T(CL)) << 16 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
398
timing[7] = (cur7 & 0xff000000) |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
401
timing[8] = cur8 & 0xffffff00;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
408
timing[8] |= T(CL);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
415
timing[0], timing[1], timing[2], timing[3]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
417
timing[4], timing[5], timing[6], timing[7]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
418
nvkm_debug(subdev, " 240: %08x\n", timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
508
u32 timing[9];
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
557
gt215_ram_timing_calc(ram, timing);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
755
ram_wr32(fuc, 0x100220[3], timing[3]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
756
ram_wr32(fuc, 0x100220[1], timing[1]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
757
ram_wr32(fuc, 0x100220[6], timing[6]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
758
ram_wr32(fuc, 0x100220[7], timing[7]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
759
ram_wr32(fuc, 0x100220[2], timing[2]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
760
ram_wr32(fuc, 0x100220[4], timing[4]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
761
ram_wr32(fuc, 0x100220[5], timing[5]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
762
ram_wr32(fuc, 0x100220[0], timing[0]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
763
ram_wr32(fuc, 0x100220[8], timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
104
timing[6] = (0x2b + T(CL) - T(CWL)) << 16 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
109
timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
110
timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
114
timing[2] = (T(CWL) - 1) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
118
timing[3] = (unkt3b - 2 + T(CL)) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
122
timing[4] = (cur4 & 0xffff0000) |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
125
timing[5] = T(RFC) << 24 |
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
129
timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
130
timing[8] = (cur8 & 0xffffff00);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
134
timing[5] |= (T(CL) + 3) << 8;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
135
timing[8] |= (T(CL) - 4);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
138
timing[5] |= (T(CL) + 2) << 8;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
139
timing[8] |= (T(CL) - 2);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
143
timing[0], timing[1], timing[2], timing[3]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
145
timing[4], timing[5], timing[6], timing[7]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
146
nvkm_debug(subdev, " 240: %08x\n", timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
151
nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
159
timing[i] = nvkm_rd32(device, 0x100220 + (i * 4));
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
163
T(CL) = (timing[3] & 0xff) + 1;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
170
T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
176
T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
232
u32 timing[9];
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
276
nv50_ram_timing_calc(ram, timing);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
278
nv50_ram_timing_read(ram, timing);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
389
ram_mask(hwsq, timing[3], 0xffffffff, timing[3]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
390
ram_mask(hwsq, timing[1], 0xffffffff, timing[1]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
391
ram_mask(hwsq, timing[6], 0xffffffff, timing[6]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
392
ram_mask(hwsq, timing[7], 0xffffffff, timing[7]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
393
ram_mask(hwsq, timing[8], 0xffffffff, timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
394
ram_mask(hwsq, timing[0], 0xffffffff, timing[0]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
395
ram_mask(hwsq, timing[2], 0xffffffff, timing[2]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
396
ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
397
ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
73
nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
98
timing[6] = (0x2d + T(CL) - T(CWL) +
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
73
CL = (ram->next->bios.timing[1] & 0x0000001f);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c
74
WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
88
CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
89
CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c
90
WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
drivers/gpu/drm/panel/panel-simple.c
444
struct display_timing *timing;
drivers/gpu/drm/panel/panel-simple.c
456
timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
drivers/gpu/drm/panel/panel-simple.c
457
if (!timing)
drivers/gpu/drm/panel/panel-simple.c
460
ret = of_get_display_timing(np, "panel-timing", timing);
drivers/gpu/drm/panel/panel-simple.c
467
desc->timings = timing;
drivers/gpu/drm/panel/panel-simple.c
475
vm.flags = timing->flags;
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
664
struct dw_mipi_dsi_dphy_timing timing;
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
670
.timing = { \
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
723
struct dw_mipi_dsi_dphy_timing *timing)
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
734
*timing = hstt_table[i].timing;
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
179
struct dw_mipi_dsi2_phy_timing *timing)
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
194
timing->data_lp2hs = tmp;
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
199
timing->data_hs2lp = tmp;
drivers/gpu/drm/sti/sti_awg_utils.c
122
struct awg_timing *timing)
drivers/gpu/drm/sti/sti_awg_utils.c
127
if (timing->trailing_pixels > 0) {
drivers/gpu/drm/sti/sti_awg_utils.c
129
val = timing->blanking_level;
drivers/gpu/drm/sti/sti_awg_utils.c
132
val = timing->trailing_pixels - 1 + AWG_DELAY;
drivers/gpu/drm/sti/sti_awg_utils.c
137
val = timing->blanking_level;
drivers/gpu/drm/sti/sti_awg_utils.c
138
ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET,
drivers/gpu/drm/sti/sti_awg_utils.c
141
if (timing->blanking_pixels > 0) {
drivers/gpu/drm/sti/sti_awg_utils.c
143
val = timing->active_pixels - 1;
drivers/gpu/drm/sti/sti_awg_utils.c
147
val = timing->blanking_level;
drivers/gpu/drm/sti/sti_awg_utils.c
156
struct awg_timing *timing)
drivers/gpu/drm/sti/sti_awg_utils.c
161
if (timing->trailing_lines > 0) {
drivers/gpu/drm/sti/sti_awg_utils.c
163
val = timing->blanking_level;
drivers/gpu/drm/sti/sti_awg_utils.c
166
val = timing->trailing_lines - 1;
drivers/gpu/drm/sti/sti_awg_utils.c
170
tmp_val = timing->active_lines - 1;
drivers/gpu/drm/sti/sti_awg_utils.c
174
ret |= awg_generate_line_signal(fwparams, timing);
drivers/gpu/drm/sti/sti_awg_utils.c
182
if (timing->blanking_lines > 0) {
drivers/gpu/drm/sti/sti_awg_utils.c
184
val = timing->blanking_level;
drivers/gpu/drm/sti/sti_awg_utils.c
187
val = timing->blanking_lines - 1;
drivers/gpu/drm/sti/sti_awg_utils.h
33
struct awg_timing *timing);
drivers/gpu/drm/sti/sti_dvo.c
118
struct awg_timing timing;
drivers/gpu/drm/sti/sti_dvo.c
123
timing.total_lines = mode->vtotal;
drivers/gpu/drm/sti/sti_dvo.c
124
timing.active_lines = mode->vdisplay;
drivers/gpu/drm/sti/sti_dvo.c
125
timing.blanking_lines = mode->vsync_start - mode->vdisplay;
drivers/gpu/drm/sti/sti_dvo.c
126
timing.trailing_lines = mode->vtotal - mode->vsync_start;
drivers/gpu/drm/sti/sti_dvo.c
127
timing.total_pixels = mode->htotal;
drivers/gpu/drm/sti/sti_dvo.c
128
timing.active_pixels = mode->hdisplay;
drivers/gpu/drm/sti/sti_dvo.c
129
timing.blanking_pixels = mode->hsync_start - mode->hdisplay;
drivers/gpu/drm/sti/sti_dvo.c
130
timing.trailing_pixels = mode->htotal - mode->hsync_start;
drivers/gpu/drm/sti/sti_dvo.c
131
timing.blanking_level = BLANKING_LEVEL;
drivers/gpu/drm/sti/sti_dvo.c
133
if (config->awg_fwgen_fct(&fw_gen_params, &timing)) {
drivers/gpu/drm/sti/sti_dvo.c
59
struct awg_timing *timing);
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
471
struct dw_mipi_dsi_dphy_timing *timing)
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
480
timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
481
timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
482
timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
483
timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
drivers/gpu/drm/tegra/dsi.c
1000
err = mipi_dphy_timing_validate(&state->timing, state->period);
drivers/gpu/drm/tegra/dsi.c
362
const struct mipi_dphy_timing *timing)
drivers/gpu/drm/tegra/dsi.c
366
value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
drivers/gpu/drm/tegra/dsi.c
367
DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
drivers/gpu/drm/tegra/dsi.c
368
DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
drivers/gpu/drm/tegra/dsi.c
369
DSI_TIMING_FIELD(timing->hsprepare, period, 1);
drivers/gpu/drm/tegra/dsi.c
372
value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
drivers/gpu/drm/tegra/dsi.c
373
DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
drivers/gpu/drm/tegra/dsi.c
374
DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
drivers/gpu/drm/tegra/dsi.c
375
DSI_TIMING_FIELD(timing->lpx, period, 1);
drivers/gpu/drm/tegra/dsi.c
378
value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
drivers/gpu/drm/tegra/dsi.c
379
DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
drivers/gpu/drm/tegra/dsi.c
38
struct mipi_dphy_timing timing;
drivers/gpu/drm/tegra/dsi.c
383
value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
drivers/gpu/drm/tegra/dsi.c
384
DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
drivers/gpu/drm/tegra/dsi.c
385
DSI_TIMING_FIELD(timing->tago, period, 1);
drivers/gpu/drm/tegra/dsi.c
389
tegra_dsi_set_phy_timing(dsi->slave, period, timing);
drivers/gpu/drm/tegra/dsi.c
933
tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
drivers/gpu/drm/tegra/dsi.c
996
err = mipi_dphy_timing_get_default(&state->timing, state->period);
drivers/gpu/drm/tegra/mipi-phy.c
102
if (timing->hsprepare + timing->hszero < 145 + 10 * period)
drivers/gpu/drm/tegra/mipi-phy.c
105
if ((timing->hssettle < 85 + 6 * period) ||
drivers/gpu/drm/tegra/mipi-phy.c
106
(timing->hssettle > 145 + 10 * period))
drivers/gpu/drm/tegra/mipi-phy.c
109
if (timing->hsskip < 40 || timing->hsskip > 55 + 4 * period)
drivers/gpu/drm/tegra/mipi-phy.c
112
if (timing->hstrail < max(8 * period, 60 + 4 * period))
drivers/gpu/drm/tegra/mipi-phy.c
115
if (timing->init < 100000)
drivers/gpu/drm/tegra/mipi-phy.c
118
if (timing->lpx < 50)
drivers/gpu/drm/tegra/mipi-phy.c
121
if (timing->taget != 5 * timing->lpx)
drivers/gpu/drm/tegra/mipi-phy.c
124
if (timing->tago != 4 * timing->lpx)
drivers/gpu/drm/tegra/mipi-phy.c
127
if (timing->tasure < timing->lpx || timing->tasure > 2 * timing->lpx)
drivers/gpu/drm/tegra/mipi-phy.c
130
if (timing->wakeup < 1000000)
drivers/gpu/drm/tegra/mipi-phy.c
16
int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
drivers/gpu/drm/tegra/mipi-phy.c
19
timing->clkmiss = 0;
drivers/gpu/drm/tegra/mipi-phy.c
20
timing->clkpost = 70 + 52 * period;
drivers/gpu/drm/tegra/mipi-phy.c
21
timing->clkpre = 8;
drivers/gpu/drm/tegra/mipi-phy.c
22
timing->clkprepare = 65;
drivers/gpu/drm/tegra/mipi-phy.c
23
timing->clksettle = 95;
drivers/gpu/drm/tegra/mipi-phy.c
24
timing->clktermen = 0;
drivers/gpu/drm/tegra/mipi-phy.c
25
timing->clktrail = 80;
drivers/gpu/drm/tegra/mipi-phy.c
26
timing->clkzero = 260;
drivers/gpu/drm/tegra/mipi-phy.c
27
timing->dtermen = 0;
drivers/gpu/drm/tegra/mipi-phy.c
28
timing->eot = 0;
drivers/gpu/drm/tegra/mipi-phy.c
29
timing->hsexit = 120;
drivers/gpu/drm/tegra/mipi-phy.c
30
timing->hsprepare = 65 + 5 * period;
drivers/gpu/drm/tegra/mipi-phy.c
31
timing->hszero = 145 + 5 * period;
drivers/gpu/drm/tegra/mipi-phy.c
32
timing->hssettle = 85 + 6 * period;
drivers/gpu/drm/tegra/mipi-phy.c
33
timing->hsskip = 40;
drivers/gpu/drm/tegra/mipi-phy.c
46
timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period);
drivers/gpu/drm/tegra/mipi-phy.c
48
timing->init = 100000;
drivers/gpu/drm/tegra/mipi-phy.c
49
timing->lpx = 60;
drivers/gpu/drm/tegra/mipi-phy.c
50
timing->taget = 5 * timing->lpx;
drivers/gpu/drm/tegra/mipi-phy.c
51
timing->tago = 4 * timing->lpx;
drivers/gpu/drm/tegra/mipi-phy.c
52
timing->tasure = 2 * timing->lpx;
drivers/gpu/drm/tegra/mipi-phy.c
53
timing->wakeup = 1000000;
drivers/gpu/drm/tegra/mipi-phy.c
62
int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
drivers/gpu/drm/tegra/mipi-phy.c
65
if (timing->clkmiss > 60)
drivers/gpu/drm/tegra/mipi-phy.c
68
if (timing->clkpost < (60 + 52 * period))
drivers/gpu/drm/tegra/mipi-phy.c
71
if (timing->clkpre < 8)
drivers/gpu/drm/tegra/mipi-phy.c
74
if (timing->clkprepare < 38 || timing->clkprepare > 95)
drivers/gpu/drm/tegra/mipi-phy.c
77
if (timing->clksettle < 95 || timing->clksettle > 300)
drivers/gpu/drm/tegra/mipi-phy.c
80
if (timing->clktermen > 38)
drivers/gpu/drm/tegra/mipi-phy.c
83
if (timing->clktrail < 60)
drivers/gpu/drm/tegra/mipi-phy.c
86
if (timing->clkprepare + timing->clkzero < 300)
drivers/gpu/drm/tegra/mipi-phy.c
89
if (timing->dtermen > 35 + 4 * period)
drivers/gpu/drm/tegra/mipi-phy.c
92
if (timing->eot > 105 + 12 * period)
drivers/gpu/drm/tegra/mipi-phy.c
95
if (timing->hsexit < 100)
drivers/gpu/drm/tegra/mipi-phy.c
98
if (timing->hsprepare < 40 + 4 * period ||
drivers/gpu/drm/tegra/mipi-phy.c
99
timing->hsprepare > 85 + 6 * period)
drivers/gpu/drm/tegra/mipi-phy.h
43
int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
drivers/gpu/drm/tegra/mipi-phy.h
45
int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
drivers/i2c/busses/i2c-img-scb.c
1153
struct img_i2c_timings timing;
drivers/i2c/busses/i2c-img-scb.c
1175
timing = timings[0];
drivers/i2c/busses/i2c-img-scb.c
1178
timing = timings[i];
drivers/i2c/busses/i2c-img-scb.c
1187
timing = timings[ARRAY_SIZE(timings) - 1];
drivers/i2c/busses/i2c-img-scb.c
1188
i2c->bitrate = timing.max_bitrate;
drivers/i2c/busses/i2c-img-scb.c
1247
data = DIV_ROUND_UP(timing.tckl, clk_period);
drivers/i2c/busses/i2c-img-scb.c
1264
tsdh = DIV_ROUND_UP(timing.tsdh, clk_period);
drivers/i2c/busses/i2c-img-scb.c
1276
data = timing.tpl / clk_period;
drivers/i2c/busses/i2c-img-scb.c
1282
data = timing.tph / clk_period;
drivers/i2c/busses/i2c-img-scb.c
1291
data = timing.tp2s / clk_period;
drivers/i2c/busses/i2c-stm32f7.c
348
struct stm32f7_i2c_timings timing;
drivers/i2c/busses/i2c-stm32f7.c
695
&i2c_dev->timing);
drivers/i2c/busses/i2c-stm32f7.c
749
struct stm32f7_i2c_timings *t = &i2c_dev->timing;
drivers/i2c/busses/i2c-stm32f7.c
750
u32 timing = 0;
drivers/i2c/busses/i2c-stm32f7.c
753
timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
drivers/i2c/busses/i2c-stm32f7.c
754
timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
drivers/i2c/busses/i2c-stm32f7.c
755
timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
drivers/i2c/busses/i2c-stm32f7.c
756
timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
drivers/i2c/busses/i2c-stm32f7.c
757
timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
drivers/i2c/busses/i2c-stm32f7.c
758
writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
drivers/iio/adc/cpcap-adc.c
214
enum cpcap_adc_timing timing;
drivers/iio/adc/cpcap-adc.c
559
switch (req->timing) {
drivers/iio/adc/cpcap-adc.c
598
if (req->timing == CPCAP_ADC_TIMING_IMM) {
drivers/iio/adc/cpcap-adc.c
626
req->timing = CPCAP_ADC_TIMING_IMM;
drivers/iio/light/tcs3414.c
152
*val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000;
drivers/iio/light/tcs3414.c
183
data->timing &= ~TCS3414_INTEG_MASK;
drivers/iio/light/tcs3414.c
184
data->timing |= i;
drivers/iio/light/tcs3414.c
187
data->timing);
drivers/iio/light/tcs3414.c
327
data->timing = TCS3414_INTEG_12MS; /* free running */
drivers/iio/light/tcs3414.c
329
data->timing);
drivers/iio/light/tcs3414.c
55
u8 timing;
drivers/iio/light/tsl2563.c
235
static int tsl2563_adc_shiftbits(u8 timing)
drivers/iio/light/tsl2563.c
239
switch (timing & TSL2563_TIMING_MASK) {
drivers/iio/light/tsl2563.c
251
if (!(timing & TSL2563_TIMING_GAIN16))
drivers/iio/light/tsl2563.c
258
static u32 tsl2563_normalize_adc(u16 adc, u8 timing)
drivers/iio/light/tsl2563.c
260
return adc << tsl2563_adc_shiftbits(timing);
drivers/leds/flash/leds-ktd2692.c
295
led->props.timing = ktd2692_timing;
drivers/leds/leds-expresswire.c
20
fsleep(props->timing.poweroff_us);
drivers/leds/leds-expresswire.c
31
udelay(props->timing.detect_delay_us);
drivers/leds/leds-expresswire.c
33
udelay(props->timing.detect_us);
drivers/leds/leds-expresswire.c
43
udelay(props->timing.data_start_us);
drivers/leds/leds-expresswire.c
49
udelay(props->timing.end_of_data_low_us);
drivers/leds/leds-expresswire.c
51
udelay(props->timing.end_of_data_high_us);
drivers/leds/leds-expresswire.c
58
udelay(props->timing.short_bitset_us);
drivers/leds/leds-expresswire.c
60
udelay(props->timing.long_bitset_us);
drivers/leds/leds-expresswire.c
63
udelay(props->timing.long_bitset_us);
drivers/leds/leds-expresswire.c
65
udelay(props->timing.short_bitset_us);
drivers/leds/leds-sun50i-a100.c
287
struct sun50i_a100_ledc_timing *timing = &priv->timing;
drivers/leds/leds-sun50i-a100.c
289
*timing = sun50i_a100_ledc_default_timing;
drivers/leds/leds-sun50i-a100.c
291
device_property_read_u32(dev, "allwinner,t0h-ns", &timing->t0h_ns);
drivers/leds/leds-sun50i-a100.c
292
device_property_read_u32(dev, "allwinner,t0l-ns", &timing->t0l_ns);
drivers/leds/leds-sun50i-a100.c
293
device_property_read_u32(dev, "allwinner,t1h-ns", &timing->t1h_ns);
drivers/leds/leds-sun50i-a100.c
294
device_property_read_u32(dev, "allwinner,t1l-ns", &timing->t1l_ns);
drivers/leds/leds-sun50i-a100.c
295
device_property_read_u32(dev, "allwinner,treset-ns", &timing->treset_ns);
drivers/leds/leds-sun50i-a100.c
302
const struct sun50i_a100_ledc_timing *timing = &priv->timing;
drivers/leds/leds-sun50i-a100.c
311
control = FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1H, timing->t1h_ns / cycle_ns) |
drivers/leds/leds-sun50i-a100.c
312
FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1L, timing->t1l_ns / cycle_ns) |
drivers/leds/leds-sun50i-a100.c
313
FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0H, timing->t0h_ns / cycle_ns) |
drivers/leds/leds-sun50i-a100.c
314
FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0L, timing->t0l_ns / cycle_ns);
drivers/leds/leds-sun50i-a100.c
317
control = FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_TR, timing->treset_ns / cycle_ns) |
drivers/leds/leds-sun50i-a100.c
90
struct sun50i_a100_ledc_timing timing;
drivers/media/dvb-frontends/stb0899_algo.c
167
s8 timing;
drivers/media/dvb-frontends/stb0899_algo.c
174
timing = stb0899_read_reg(state, STB0899_RTF);
drivers/media/dvb-frontends/stb0899_algo.c
177
if ((lock > 48) && (abs(timing) >= 110)) {
drivers/media/dvb-frontends/stv0900_sw.c
1183
u8 timing;
drivers/media/dvb-frontends/stv0900_sw.c
1187
timing = stv0900_read_reg(intp, TMGREG2);
drivers/media/dvb-frontends/stv0900_sw.c
1191
while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
drivers/media/dvb-frontends/stv0900_sw.c
1192
timing = stv0900_read_reg(intp, TMGREG2);
drivers/media/i2c/bt819.c
175
struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0];
drivers/media/i2c/bt819.c
178
(((timing->vdelay >> 8) & 0x03) << 6) |
drivers/media/i2c/bt819.c
179
(((timing->vactive >> 8) & 0x03) << 4) |
drivers/media/i2c/bt819.c
180
(((timing->hdelay >> 8) & 0x03) << 2) |
drivers/media/i2c/bt819.c
181
((timing->hactive >> 8) & 0x03);
drivers/media/i2c/bt819.c
182
init[0x04 * 2 - 1] = timing->vdelay & 0xff;
drivers/media/i2c/bt819.c
183
init[0x05 * 2 - 1] = timing->vactive & 0xff;
drivers/media/i2c/bt819.c
184
init[0x06 * 2 - 1] = timing->hdelay & 0xff;
drivers/media/i2c/bt819.c
185
init[0x07 * 2 - 1] = timing->hactive & 0xff;
drivers/media/i2c/bt819.c
186
init[0x08 * 2 - 1] = timing->hscale >> 8;
drivers/media/i2c/bt819.c
187
init[0x09 * 2 - 1] = timing->hscale & 0xff;
drivers/media/i2c/bt819.c
238
struct timing *timing = NULL;
drivers/media/i2c/bt819.c
253
timing = &timing_data[1];
drivers/media/i2c/bt819.c
262
timing = &timing_data[0];
drivers/media/i2c/bt819.c
269
(((timing->vdelay >> 8) & 0x03) << 6) |
drivers/media/i2c/bt819.c
270
(((timing->vactive >> 8) & 0x03) << 4) |
drivers/media/i2c/bt819.c
271
(((timing->hdelay >> 8) & 0x03) << 2) |
drivers/media/i2c/bt819.c
272
((timing->hactive >> 8) & 0x03));
drivers/media/i2c/bt819.c
273
bt819_write(decoder, 0x04, timing->vdelay & 0xff);
drivers/media/i2c/bt819.c
274
bt819_write(decoder, 0x05, timing->vactive & 0xff);
drivers/media/i2c/bt819.c
275
bt819_write(decoder, 0x06, timing->hdelay & 0xff);
drivers/media/i2c/bt819.c
276
bt819_write(decoder, 0x07, timing->hactive & 0xff);
drivers/media/i2c/bt819.c
277
bt819_write(decoder, 0x08, (timing->hscale >> 8) & 0xff);
drivers/media/i2c/bt819.c
278
bt819_write(decoder, 0x09, timing->hscale & 0xff);
drivers/media/i2c/bt819.c
70
static struct timing timing_data[] = {
drivers/media/pci/intel/ipu3/ipu3-cio2.c
308
struct cio2_csi2_timing *timing,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
328
timing->clk_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
332
timing->clk_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
336
timing->dat_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
340
timing->dat_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
345
dev_dbg(dev, "freq ct value is %d\n", timing->clk_termen);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
346
dev_dbg(dev, "freq cs value is %d\n", timing->clk_settle);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
347
dev_dbg(dev, "freq dt value is %d\n", timing->dat_termen);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
348
dev_dbg(dev, "freq ds value is %d\n", timing->dat_settle);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
367
struct cio2_csi2_timing timing = { 0 };
drivers/media/pci/intel/ipu3/ipu3-cio2.c
382
r = cio2_csi2_calc_timing(cio2, q, &timing, fmt->bpp, lanes);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
386
writel(timing.clk_termen, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
388
writel(timing.clk_settle, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
392
writel(timing.dat_termen, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
394
writel(timing.dat_settle, q->csi_rx_base +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
169
struct ipu6_isys_csi2_timing *timing, s32 accinv)
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
178
timing->ctermen = calc_timing(CSI2_CSI_RX_DLY_CNT_TERMEN_CLANE_A,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
181
timing->csettle = calc_timing(CSI2_CSI_RX_DLY_CNT_SETTLE_CLANE_A,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
184
timing->dtermen = calc_timing(CSI2_CSI_RX_DLY_CNT_TERMEN_DLANE_A,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
187
timing->dsettle = calc_timing(CSI2_CSI_RX_DLY_CNT_SETTLE_DLANE_A,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
192
timing->ctermen, timing->csettle,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
193
timing->dtermen, timing->dsettle);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
232
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
271
isys->phy_set_power(isys, &cfg, timing, false);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
338
ret = isys->phy_set_power(isys, &cfg, timing, true);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
352
struct ipu6_isys_csi2_timing timing = { };
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
365
ret = ipu6_isys_csi2_calc_timing(csi2, &timing, CSI2_ACCINV);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
369
ret = ipu6_isys_csi2_set_stream(sd, &timing, csi2->nlanes, true);
drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c
461
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
171
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
187
writel(timing->ctermen, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
191
writel(timing->csettle, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
196
writel(timing->dtermen, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
200
writel(timing->dsettle, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
207
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
233
ipu6_isys_csi2_set_timing(isys, timing, port, nlanes);
drivers/media/pci/intel/ipu6/ipu6-isys-mcd-phy.c
667
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys.h
155
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys.h
188
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys.h
193
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/intel/ipu6/ipu6-isys.h
198
const struct ipu6_isys_csi2_timing *timing,
drivers/media/pci/zoran/zoran.h
213
const struct tvnorm *timing;
drivers/media/pci/zoran/zoran.h
51
#define BUZ_MAX_WIDTH (zr->timing->wa)
drivers/media/pci/zoran/zoran.h
52
#define BUZ_MAX_HEIGHT (zr->timing->ha)
drivers/media/pci/zoran/zoran_card.c
1001
zr->timing = zr->card.tvn[ZR_NORM_NTSC];
drivers/media/pci/zoran/zoran_card.c
1004
zr->timing = zr->card.tvn[ZR_NORM_SECAM];
drivers/media/pci/zoran/zoran_card.c
1006
if (!zr->timing) {
drivers/media/pci/zoran/zoran_card.c
1011
zr->timing = zr->card.tvn[ZR_NORM_PAL];
drivers/media/pci/zoran/zoran_card.c
998
zr->timing = zr->card.tvn[ZR_NORM_PAL];
drivers/media/pci/zoran/zoran_device.c
237
tvn = zr->timing;
drivers/media/pci/zoran/zoran_device.c
423
tvn = zr->timing;
drivers/media/pci/zoran/zoran_device.c
651
zr->codec->set_video(zr->codec, zr->timing, &cap,
drivers/media/pci/zoran/zoran_device.c
659
zr->vfe->set_video(zr->vfe, zr->timing, &cap,
drivers/media/pci/zoran/zoran_device.c
684
zr->vfe->set_video(zr->vfe, zr->timing, &cap,
drivers/media/pci/zoran/zoran_device.c
689
zr->codec->set_video(zr->codec, zr->timing, &cap,
drivers/media/pci/zoran/zoran_driver.c
212
zr->timing = zr->card.tvn[ZR_NORM_SECAM];
drivers/media/pci/zoran/zoran_driver.c
214
zr->timing = zr->card.tvn[ZR_NORM_NTSC];
drivers/media/pci/zoran/zoran_driver.c
216
zr->timing = zr->card.tvn[ZR_NORM_PAL];
drivers/media/platform/nuvoton/npcm-video.c
907
struct v4l2_bt_timings *timing)
drivers/media/platform/nuvoton/npcm-video.c
912
if (npcm_video_capres(video, timing->width, timing->height)) {
drivers/media/platform/nuvoton/npcm-video.c
917
video->active_timings = *timing;
drivers/media/platform/nuvoton/npcm-video.c
919
npcm_video_set_linepitch(video, timing->width * video->bytesperpixel);
drivers/media/platform/nuvoton/npcm-video.c
921
video->pix_fmt.width = timing->width ? timing->width : MIN_WIDTH;
drivers/media/platform/nuvoton/npcm-video.c
922
video->pix_fmt.height = timing->height ? timing->height : MIN_HEIGHT;
drivers/media/platform/nuvoton/npcm-video.c
927
npcm_video_kvm_bw(video, timing->pixelclock > VCD_KVM_BW_PCLK);
drivers/media/platform/nuvoton/npcm-video.c
936
timing->width, timing->height, video->bytesperpixel,
drivers/media/platform/nuvoton/npcm-video.c
937
timing->pixelclock, video->bytesperline);
drivers/media/platform/ti/omap/omap_vout.c
1197
struct omap_video_timings *timing;
drivers/media/platform/ti/omap/omap_vout.c
1208
timing = &dssdev->panel.timings;
drivers/media/platform/ti/omap/omap_vout.c
1210
vout->fbuf.fmt.height = timing->y_res;
drivers/media/platform/ti/omap/omap_vout.c
1211
vout->fbuf.fmt.width = timing->x_res;
drivers/media/platform/ti/omap/omap_vout.c
361
struct omap_video_timings *timing;
drivers/media/platform/ti/omap/omap_vout.c
374
timing = &dssdev->panel.timings;
drivers/media/platform/ti/omap/omap_vout.c
384
posy = (timing->y_res - win->w.width) - win->w.left;
drivers/media/platform/ti/omap/omap_vout.c
389
posx = (timing->x_res - win->w.width) - win->w.left;
drivers/media/platform/ti/omap/omap_vout.c
390
posy = (timing->y_res - win->w.height) - win->w.top;
drivers/media/platform/ti/omap/omap_vout.c
396
posx = (timing->x_res - win->w.height) - win->w.top;
drivers/media/platform/ti/omap/omap_vout.c
612
struct omap_video_timings *timing;
drivers/media/platform/ti/omap/omap_vout.c
624
timing = &dssdev->panel.timings;
drivers/media/platform/ti/omap/omap_vout.c
626
vout->fbuf.fmt.height = timing->y_res;
drivers/media/platform/ti/omap/omap_vout.c
627
vout->fbuf.fmt.width = timing->x_res;
drivers/media/platform/ti/omap/omap_vout.c
639
struct omap_video_timings *timing;
drivers/media/platform/ti/omap/omap_vout.c
655
timing = &dssdev->panel.timings;
drivers/media/platform/ti/omap/omap_vout.c
668
vout->fbuf.fmt.height = timing->x_res;
drivers/media/platform/ti/omap/omap_vout.c
669
vout->fbuf.fmt.width = timing->y_res;
drivers/media/platform/ti/omap/omap_vout.c
671
vout->fbuf.fmt.height = timing->y_res;
drivers/media/platform/ti/omap/omap_vout.c
672
vout->fbuf.fmt.width = timing->x_res;
drivers/media/platform/ti/omap/omap_vout.c
822
struct omap_video_timings *timing;
drivers/media/platform/ti/omap/omap_vout.c
844
timing = &dssdev->panel.timings;
drivers/media/platform/ti/omap/omap_vout.c
847
vout->fbuf.fmt.height = timing->x_res;
drivers/media/platform/ti/omap/omap_vout.c
848
vout->fbuf.fmt.width = timing->y_res;
drivers/media/platform/ti/omap/omap_vout.c
850
vout->fbuf.fmt.height = timing->y_res;
drivers/media/platform/ti/omap/omap_vout.c
851
vout->fbuf.fmt.width = timing->x_res;
drivers/media/platform/ti/omap3isp/ispcsi2.c
356
struct isp_csi2_timing_cfg *timing)
drivers/media/platform/ti/omap3isp/ispcsi2.c
362
if (timing->force_rx_mode)
drivers/media/platform/ti/omap3isp/ispcsi2.c
363
reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
365
reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
367
if (timing->stop_state_16x)
drivers/media/platform/ti/omap3isp/ispcsi2.c
368
reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
370
reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
372
if (timing->stop_state_4x)
drivers/media/platform/ti/omap3isp/ispcsi2.c
373
reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
375
reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
377
reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
378
reg |= timing->stop_state_counter <<
drivers/media/platform/ti/omap3isp/ispcsi2.c
379
ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
drivers/media/platform/ti/omap3isp/ispcsi2.c
551
struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
drivers/media/platform/ti/omap3isp/ispcsi2.c
582
timing->ionum = 1;
drivers/media/platform/ti/omap3isp/ispcsi2.c
583
timing->force_rx_mode = 1;
drivers/media/platform/ti/omap3isp/ispcsi2.c
584
timing->stop_state_16x = 1;
drivers/media/platform/ti/omap3isp/ispcsi2.c
585
timing->stop_state_4x = 1;
drivers/media/platform/ti/omap3isp/ispcsi2.c
586
timing->stop_state_counter = 0x1FF;
drivers/media/platform/ti/omap3isp/ispcsi2.c
621
csi2_timing_config(isp, csi2, timing);
drivers/media/platform/ti/omap3isp/ispcsi2.h
138
struct isp_csi2_timing_cfg timing[2];
drivers/media/rc/img-ir/img-ir-hw.c
109
static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing,
drivers/media/rc/img-ir/img-ir-hw.c
112
img_ir_timing_defaults(&timing->pulse, &defaults->pulse);
drivers/media/rc/img-ir/img-ir-hw.c
113
img_ir_timing_defaults(&timing->space, &defaults->space);
drivers/media/rc/img-ir/img-ir-hw.c
203
static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing,
drivers/media/rc/img-ir/img-ir-hw.c
211
hw_period.min = timing->pulse.min + timing->space.min;
drivers/media/rc/img-ir/img-ir-hw.c
212
hw_period.max = timing->pulse.max + timing->space.max;
drivers/media/rc/img-ir/img-ir-hw.c
215
img_ir_timing_range_convert(&hw_pulse, &timing->pulse,
drivers/media/rc/img-ir/img-ir-hw.c
231
static u32 img_ir_free_timing(const struct img_ir_free_timing *timing,
drivers/media/rc/img-ir/img-ir-hw.c
236
if (timing->minlen < 30)
drivers/media/rc/img-ir/img-ir-hw.c
237
minlen = timing->minlen & -2;
drivers/media/rc/img-ir/img-ir-hw.c
241
if (timing->maxlen < 48)
drivers/media/rc/img-ir/img-ir-hw.c
242
maxlen = (timing->maxlen + 1) & -2;
drivers/media/rc/img-ir/img-ir-hw.c
246
ft_min = (timing->ft_min*clock_hz + 999999) / 1000000;
drivers/media/rc/img-ir/img-ir-hw.c
77
static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing,
drivers/media/rc/img-ir/img-ir-hw.c
80
img_ir_timing_preprocess(&timing->pulse, unit);
drivers/media/rc/img-ir/img-ir-hw.c
81
img_ir_timing_preprocess(&timing->space, unit);
drivers/media/test-drivers/vidtv/vidtv_mux.c
121
m->timing.past_jiffies = m->timing.current_jiffies;
drivers/media/test-drivers/vidtv/vidtv_mux.c
122
m->timing.current_jiffies = get_jiffies_64();
drivers/media/test-drivers/vidtv/vidtv_mux.c
124
elapsed_time = jiffies_to_usecs(m->timing.current_jiffies -
drivers/media/test-drivers/vidtv/vidtv_mux.c
125
m->timing.past_jiffies);
drivers/media/test-drivers/vidtv/vidtv_mux.c
128
m->timing.clk += (CLOCK_UNIT_27MHZ / USEC_PER_SEC) * elapsed_time;
drivers/media/test-drivers/vidtv/vidtv_mux.c
240
args.pcr = m->timing.clk;
drivers/media/test-drivers/vidtv/vidtv_mux.c
257
next_pcr_at = m->timing.start_jiffies +
drivers/media/test-drivers/vidtv/vidtv_mux.c
259
m->timing.pcr_period_usecs);
drivers/media/test-drivers/vidtv/vidtv_mux.c
261
return time_after64(m->timing.current_jiffies, next_pcr_at);
drivers/media/test-drivers/vidtv/vidtv_mux.c
271
next_si_at = m->timing.start_jiffies +
drivers/media/test-drivers/vidtv/vidtv_mux.c
273
m->timing.si_period_usecs);
drivers/media/test-drivers/vidtv/vidtv_mux.c
275
return time_after64(m->timing.current_jiffies, next_si_at);
drivers/media/test-drivers/vidtv/vidtv_mux.c
311
args.pcr = m->timing.clk;
drivers/media/test-drivers/vidtv/vidtv_mux.c
471
m->timing.start_jiffies = get_jiffies_64();
drivers/media/test-drivers/vidtv/vidtv_mux.c
495
m->timing.pcr_period_usecs = args->pcr_period_usecs;
drivers/media/test-drivers/vidtv/vidtv_mux.c
496
m->timing.si_period_usecs = args->si_period_usecs;
drivers/media/test-drivers/vidtv/vidtv_mux.c
516
m->timing.current_jiffies = get_jiffies_64();
drivers/media/test-drivers/vidtv/vidtv_mux.h
117
struct vidtv_mux_timing timing;
drivers/memory/samsung/exynos-srom.c
71
u32 timing[6];
drivers/memory/samsung/exynos-srom.c
80
if (of_property_read_u32_array(np, "samsung,srom-timing", timing,
drivers/memory/samsung/exynos-srom.c
81
ARRAY_SIZE(timing)))
drivers/memory/samsung/exynos-srom.c
94
writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
drivers/memory/samsung/exynos-srom.c
95
(timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
drivers/memory/samsung/exynos-srom.c
96
(timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
drivers/memory/samsung/exynos-srom.c
97
(timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
drivers/memory/samsung/exynos-srom.c
98
(timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
drivers/memory/samsung/exynos-srom.c
99
(timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
drivers/memory/samsung/exynos5422-dmc.c
193
#define TIMING_VAL2REG(timing, t_val) \
drivers/memory/samsung/exynos5422-dmc.c
196
__val = (t_val) << (timing)->bit_beg; \
drivers/memory/tegra/mc.c
371
struct tegra_mc_timing *timing = NULL;
drivers/memory/tegra/mc.c
375
timing = &mc->timings[i];
drivers/memory/tegra/mc.c
380
if (!timing) {
drivers/memory/tegra/mc.c
387
mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
drivers/memory/tegra/mc.c
445
struct tegra_mc_timing *timing,
drivers/memory/tegra/mc.c
458
timing->rate = tmp;
drivers/memory/tegra/mc.c
459
timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
drivers/memory/tegra/mc.c
461
if (!timing->emem_data)
drivers/memory/tegra/mc.c
465
timing->emem_data,
drivers/memory/tegra/mc.c
479
struct tegra_mc_timing *timing;
drivers/memory/tegra/mc.c
483
mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
drivers/memory/tegra/mc.c
491
timing = &mc->timings[i++];
drivers/memory/tegra/mc.c
493
err = load_one_timing(mc, timing, child);
drivers/memory/tegra/tegra114-emc.c
489
struct emc_timing *timing = NULL;
drivers/memory/tegra/tegra114-emc.c
494
timing = &emc->timings[i];
drivers/memory/tegra/tegra114-emc.c
499
if (!timing) {
drivers/memory/tegra/tegra114-emc.c
504
return timing;
drivers/memory/tegra/tegra114-emc.c
510
struct emc_timing *timing = tegra114_emc_find_timing(emc, rate);
drivers/memory/tegra/tegra114-emc.c
520
if (!timing)
drivers/memory/tegra/tegra114-emc.c
523
next_dll_enabled = !(timing->emc_mode_1 & 0x1);
drivers/memory/tegra/tegra114-emc.c
558
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
drivers/memory/tegra/tegra114-emc.c
564
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
drivers/memory/tegra/tegra114-emc.c
583
if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
drivers/memory/tegra/tegra114-emc.c
585
writel(timing->emc_ctt_term_ctrl,
drivers/memory/tegra/tegra114-emc.c
591
for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
drivers/memory/tegra/tegra114-emc.c
592
writel(timing->emc_burst_data[i],
drivers/memory/tegra/tegra114-emc.c
595
writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
drivers/memory/tegra/tegra114-emc.c
596
writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
drivers/memory/tegra/tegra114-emc.c
598
tegra_mc_write_emem_configuration(emc->mc, timing->rate);
drivers/memory/tegra/tegra114-emc.c
600
val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
drivers/memory/tegra/tegra114-emc.c
604
if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
drivers/memory/tegra/tegra114-emc.c
605
emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
drivers/memory/tegra/tegra114-emc.c
608
if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
drivers/memory/tegra/tegra114-emc.c
609
emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
drivers/memory/tegra/tegra114-emc.c
612
if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
drivers/memory/tegra/tegra114-emc.c
613
val = timing->emc_auto_cal_config;
drivers/memory/tegra/tegra114-emc.c
623
if (timing->emc_zcal_interval != 0 &&
drivers/memory/tegra/tegra114-emc.c
627
val = (timing->emc_mrs_wait_cnt
drivers/memory/tegra/tegra114-emc.c
633
val = timing->emc_mrs_wait_cnt
drivers/memory/tegra/tegra114-emc.c
643
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
drivers/memory/tegra/tegra114-emc.c
666
if (timing->emc_mode_1 != last->emc_mode_1)
drivers/memory/tegra/tegra114-emc.c
667
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
drivers/memory/tegra/tegra114-emc.c
668
if (timing->emc_mode_2 != last->emc_mode_2)
drivers/memory/tegra/tegra114-emc.c
669
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
drivers/memory/tegra/tegra114-emc.c
671
if (timing->emc_mode_reset != last->emc_mode_reset ||
drivers/memory/tegra/tegra114-emc.c
673
val = timing->emc_mode_reset;
drivers/memory/tegra/tegra114-emc.c
683
if (timing->emc_mode_2 != last->emc_mode_2)
drivers/memory/tegra/tegra114-emc.c
684
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
drivers/memory/tegra/tegra114-emc.c
685
if (timing->emc_mode_1 != last->emc_mode_1)
drivers/memory/tegra/tegra114-emc.c
686
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
drivers/memory/tegra/tegra114-emc.c
687
if (timing->emc_mode_4 != last->emc_mode_4)
drivers/memory/tegra/tegra114-emc.c
688
emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
drivers/memory/tegra/tegra114-emc.c
692
if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
drivers/memory/tegra/tegra114-emc.c
714
struct emc_timing *timing = tegra114_emc_find_timing(emc, rate);
drivers/memory/tegra/tegra114-emc.c
717
if (!timing)
drivers/memory/tegra/tegra114-emc.c
724
if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
drivers/memory/tegra/tegra114-emc.c
725
writel(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra114-emc.c
729
if (timing->emc_cfg & EMC_CFG_PWR_MASK)
drivers/memory/tegra/tegra114-emc.c
730
writel(timing->emc_cfg, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra114-emc.c
733
writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
drivers/memory/tegra/tegra114-emc.c
739
writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
drivers/memory/tegra/tegra114-emc.c
742
emc->last_timing = *timing;
drivers/memory/tegra/tegra114-emc.c
748
struct emc_timing *timing)
drivers/memory/tegra/tegra114-emc.c
753
timing->emc_burst_data[i] =
drivers/memory/tegra/tegra114-emc.c
756
timing->emc_cfg = readl(emc->regs + EMC_CFG);
drivers/memory/tegra/tegra114-emc.c
758
timing->emc_auto_cal_interval = 0;
drivers/memory/tegra/tegra114-emc.c
759
timing->emc_zcal_cnt_long = 0;
drivers/memory/tegra/tegra114-emc.c
760
timing->emc_mode_1 = 0;
drivers/memory/tegra/tegra114-emc.c
761
timing->emc_mode_2 = 0;
drivers/memory/tegra/tegra114-emc.c
762
timing->emc_mode_4 = 0;
drivers/memory/tegra/tegra114-emc.c
763
timing->emc_mode_reset = 0;
drivers/memory/tegra/tegra114-emc.c
826
struct emc_timing *timing,
drivers/memory/tegra/tegra114-emc.c
839
timing->rate = value;
drivers/memory/tegra/tegra114-emc.c
842
timing->emc_burst_data,
drivers/memory/tegra/tegra114-emc.c
843
ARRAY_SIZE(timing->emc_burst_data));
drivers/memory/tegra/tegra114-emc.c
852
err = of_property_read_u32(node, dtprop, &timing->prop); \
drivers/memory/tegra/tegra114-emc.c
921
struct emc_timing *timing;
drivers/memory/tegra/tegra114-emc.c
925
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
drivers/memory/tegra/tegra114-emc.c
933
timing = &emc->timings[i++];
drivers/memory/tegra/tegra114-emc.c
935
err = load_one_timing_from_dt(emc, timing, child);
drivers/memory/tegra/tegra114-emc.c
940
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
drivers/memory/tegra/tegra124-emc.c
560
struct emc_timing *timing = NULL;
drivers/memory/tegra/tegra124-emc.c
565
timing = &emc->timings[i];
drivers/memory/tegra/tegra124-emc.c
570
if (!timing) {
drivers/memory/tegra/tegra124-emc.c
575
return timing;
drivers/memory/tegra/tegra124-emc.c
581
struct emc_timing *timing = tegra124_emc_find_timing(emc, rate);
drivers/memory/tegra/tegra124-emc.c
589
if (!timing)
drivers/memory/tegra/tegra124-emc.c
592
if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
drivers/memory/tegra/tegra124-emc.c
594
else if (!(timing->emc_mode_1 & 0x1))
drivers/memory/tegra/tegra124-emc.c
626
if (!(timing->emc_bgbias_ctl0 &
drivers/memory/tegra/tegra124-emc.c
646
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
drivers/memory/tegra/tegra124-emc.c
652
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
drivers/memory/tegra/tegra124-emc.c
671
if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
drivers/memory/tegra/tegra124-emc.c
673
writel(timing->emc_ctt_term_ctrl,
drivers/memory/tegra/tegra124-emc.c
679
for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
drivers/memory/tegra/tegra124-emc.c
680
writel(timing->emc_burst_data[i],
drivers/memory/tegra/tegra124-emc.c
683
writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
drivers/memory/tegra/tegra124-emc.c
684
writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
drivers/memory/tegra/tegra124-emc.c
686
tegra_mc_write_emem_configuration(emc->mc, timing->rate);
drivers/memory/tegra/tegra124-emc.c
688
val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
drivers/memory/tegra/tegra124-emc.c
692
if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
drivers/memory/tegra/tegra124-emc.c
693
emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
drivers/memory/tegra/tegra124-emc.c
696
if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
drivers/memory/tegra/tegra124-emc.c
697
emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
drivers/memory/tegra/tegra124-emc.c
700
if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
drivers/memory/tegra/tegra124-emc.c
701
val = timing->emc_auto_cal_config;
drivers/memory/tegra/tegra124-emc.c
711
if (timing->emc_zcal_interval != 0 &&
drivers/memory/tegra/tegra124-emc.c
715
val = (timing->emc_mrs_wait_cnt
drivers/memory/tegra/tegra124-emc.c
721
val = timing->emc_mrs_wait_cnt
drivers/memory/tegra/tegra124-emc.c
729
val = timing->emc_cfg_2;
drivers/memory/tegra/tegra124-emc.c
735
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
drivers/memory/tegra/tegra124-emc.c
758
if (timing->emc_mode_1 != last->emc_mode_1)
drivers/memory/tegra/tegra124-emc.c
759
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
drivers/memory/tegra/tegra124-emc.c
760
if (timing->emc_mode_2 != last->emc_mode_2)
drivers/memory/tegra/tegra124-emc.c
761
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
drivers/memory/tegra/tegra124-emc.c
763
if ((timing->emc_mode_reset != last->emc_mode_reset) ||
drivers/memory/tegra/tegra124-emc.c
765
val = timing->emc_mode_reset;
drivers/memory/tegra/tegra124-emc.c
775
if (timing->emc_mode_2 != last->emc_mode_2)
drivers/memory/tegra/tegra124-emc.c
776
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
drivers/memory/tegra/tegra124-emc.c
777
if (timing->emc_mode_1 != last->emc_mode_1)
drivers/memory/tegra/tegra124-emc.c
778
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
drivers/memory/tegra/tegra124-emc.c
779
if (timing->emc_mode_4 != last->emc_mode_4)
drivers/memory/tegra/tegra124-emc.c
780
emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
drivers/memory/tegra/tegra124-emc.c
784
if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
drivers/memory/tegra/tegra124-emc.c
794
if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
drivers/memory/tegra/tegra124-emc.c
795
emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
drivers/memory/tegra/tegra124-emc.c
809
struct emc_timing *timing = tegra124_emc_find_timing(emc, rate);
drivers/memory/tegra/tegra124-emc.c
813
if (!timing)
drivers/memory/tegra/tegra124-emc.c
820
if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
drivers/memory/tegra/tegra124-emc.c
821
writel(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra124-emc.c
825
if (timing->emc_cfg & EMC_CFG_PWR_MASK)
drivers/memory/tegra/tegra124-emc.c
826
writel(timing->emc_cfg, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra124-emc.c
829
writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
drivers/memory/tegra/tegra124-emc.c
833
timing->emc_bgbias_ctl0 &
drivers/memory/tegra/tegra124-emc.c
835
val = timing->emc_bgbias_ctl0;
drivers/memory/tegra/tegra124-emc.c
842
timing->emc_bgbias_ctl0) {
drivers/memory/tegra/tegra124-emc.c
843
writel(timing->emc_bgbias_ctl0,
drivers/memory/tegra/tegra124-emc.c
847
writel(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra124-emc.c
855
writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
drivers/memory/tegra/tegra124-emc.c
858
emc->last_timing = *timing;
drivers/memory/tegra/tegra124-emc.c
864
struct emc_timing *timing)
drivers/memory/tegra/tegra124-emc.c
869
timing->emc_burst_data[i] =
drivers/memory/tegra/tegra124-emc.c
872
timing->emc_cfg = readl(emc->regs + EMC_CFG);
drivers/memory/tegra/tegra124-emc.c
874
timing->emc_auto_cal_interval = 0;
drivers/memory/tegra/tegra124-emc.c
875
timing->emc_zcal_cnt_long = 0;
drivers/memory/tegra/tegra124-emc.c
876
timing->emc_mode_1 = 0;
drivers/memory/tegra/tegra124-emc.c
877
timing->emc_mode_2 = 0;
drivers/memory/tegra/tegra124-emc.c
878
timing->emc_mode_4 = 0;
drivers/memory/tegra/tegra124-emc.c
879
timing->emc_mode_reset = 0;
drivers/memory/tegra/tegra124-emc.c
902
struct emc_timing *timing,
drivers/memory/tegra/tegra124-emc.c
915
timing->rate = value;
drivers/memory/tegra/tegra124-emc.c
918
timing->emc_burst_data,
drivers/memory/tegra/tegra124-emc.c
919
ARRAY_SIZE(timing->emc_burst_data));
drivers/memory/tegra/tegra124-emc.c
928
err = of_property_read_u32(node, dtprop, &timing->prop); \
drivers/memory/tegra/tegra124-emc.c
976
struct emc_timing *timing;
drivers/memory/tegra/tegra124-emc.c
980
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
drivers/memory/tegra/tegra124-emc.c
988
timing = &emc->timings[i++];
drivers/memory/tegra/tegra124-emc.c
990
err = load_one_timing_from_dt(emc, timing, child);
drivers/memory/tegra/tegra124-emc.c
995
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
drivers/memory/tegra/tegra20-emc.c
241
struct emc_timing *timing = NULL;
drivers/memory/tegra/tegra20-emc.c
246
timing = &emc->timings[i];
drivers/memory/tegra/tegra20-emc.c
251
if (!timing) {
drivers/memory/tegra/tegra20-emc.c
256
return timing;
drivers/memory/tegra/tegra20-emc.c
261
struct emc_timing *timing = tegra20_emc_find_timing(emc, rate);
drivers/memory/tegra/tegra20-emc.c
264
if (!timing)
drivers/memory/tegra/tegra20-emc.c
268
__func__, timing->rate, rate);
drivers/memory/tegra/tegra20-emc.c
271
for (i = 0; i < ARRAY_SIZE(timing->data); i++)
drivers/memory/tegra/tegra20-emc.c
272
writel_relaxed(timing->data[i],
drivers/memory/tegra/tegra20-emc.c
338
struct emc_timing *timing,
drivers/memory/tegra/tegra20-emc.c
357
timing->data,
drivers/memory/tegra/tegra20-emc.c
370
timing->rate = rate * 2 * 1000;
drivers/memory/tegra/tegra20-emc.c
373
__func__, node, timing->rate);
drivers/memory/tegra/tegra20-emc.c
395
struct emc_timing *timing;
drivers/memory/tegra/tegra20-emc.c
405
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
drivers/memory/tegra/tegra20-emc.c
410
timing = emc->timings;
drivers/memory/tegra/tegra20-emc.c
416
err = load_one_timing_from_dt(emc, timing++, child);
drivers/memory/tegra/tegra20-emc.c
423
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
drivers/memory/tegra/tegra20-emc.c
659
struct emc_timing *timing = NULL;
drivers/memory/tegra/tegra20-emc.c
682
timing = &emc->timings[i];
drivers/memory/tegra/tegra20-emc.c
686
if (!timing) {
drivers/memory/tegra/tegra20-emc.c
692
return timing->rate;
drivers/memory/tegra/tegra210-emc-cc-r21021.c
113
#define __MOVAVG(timing, dev) \
drivers/memory/tegra/tegra210-emc-cc-r21021.c
114
((timing)->ptfv_list[(dev)])
drivers/memory/tegra/tegra210-emc-cc-r21021.c
116
static bool tegra210_emc_compare_update_delay(struct tegra210_emc_timing *timing,
drivers/memory/tegra/tegra210-emc-cc-r21021.c
119
u32 *curr = &timing->current_dram_clktree[idx];
drivers/memory/tegra/tegra210-emc-cc-r21021.c
120
u32 rate_mhz = timing->rate / 1000;
drivers/memory/tegra/tegra210-emc-cc-r21021.c
125
if (tmdel * 128 * rate_mhz / 1000000 > timing->tree_margin) {
drivers/memory/tegra/tegra210-emc-cc-r21021.c
92
#define __MOVAVG_AC(timing, dev) \
drivers/memory/tegra/tegra210-emc-cc-r21021.c
93
((timing)->ptfv_list[(dev)] / \
drivers/memory/tegra/tegra210-emc-core.c
1225
const struct tegra210_emc_timing *timing;
drivers/memory/tegra/tegra210-emc-core.c
1228
timing = emc->last;
drivers/memory/tegra/tegra210-emc-core.c
1230
timing = emc->next;
drivers/memory/tegra/tegra210-emc-core.c
1232
cmd_pad = timing->burst_regs[EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1233
dq_pad = timing->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1234
rfu1 = timing->burst_regs[EMC_PMACRO_BRICK_CTRL_RFU1_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1235
cfg5 = timing->burst_regs[EMC_FBIO_CFG5_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1236
common_tx = timing->burst_regs[EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1443
void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing)
drivers/memory/tegra/tegra210-emc-core.c
1445
timing->current_dram_clktree[C0D0U0] =
drivers/memory/tegra/tegra210-emc-core.c
1446
timing->trained_dram_clktree[C0D0U0];
drivers/memory/tegra/tegra210-emc-core.c
1447
timing->current_dram_clktree[C0D0U1] =
drivers/memory/tegra/tegra210-emc-core.c
1448
timing->trained_dram_clktree[C0D0U1];
drivers/memory/tegra/tegra210-emc-core.c
1449
timing->current_dram_clktree[C1D0U0] =
drivers/memory/tegra/tegra210-emc-core.c
1450
timing->trained_dram_clktree[C1D0U0];
drivers/memory/tegra/tegra210-emc-core.c
1451
timing->current_dram_clktree[C1D0U1] =
drivers/memory/tegra/tegra210-emc-core.c
1452
timing->trained_dram_clktree[C1D0U1];
drivers/memory/tegra/tegra210-emc-core.c
1453
timing->current_dram_clktree[C1D1U0] =
drivers/memory/tegra/tegra210-emc-core.c
1454
timing->trained_dram_clktree[C1D1U0];
drivers/memory/tegra/tegra210-emc-core.c
1455
timing->current_dram_clktree[C1D1U1] =
drivers/memory/tegra/tegra210-emc-core.c
1456
timing->trained_dram_clktree[C1D1U1];
drivers/memory/tegra/tegra210-emc-core.c
1493
struct tegra210_emc_timing *timing)
drivers/memory/tegra/tegra210-emc-core.c
1495
u32 dsr_cntrl = timing->burst_regs[EMC_DYN_SELF_REF_CONTROL_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1496
u32 pre_ref = timing->burst_regs[EMC_PRE_REFRESH_REQ_CNT_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1497
u32 ref = timing->burst_regs[EMC_REFRESH_INDEX];
drivers/memory/tegra/tegra210-emc-core.c
1532
struct tegra210_emc_timing *timing = NULL;
drivers/memory/tegra/tegra210-emc-core.c
1543
timing = &emc->timings[i];
drivers/memory/tegra/tegra210-emc-core.c
1548
if (!timing)
drivers/memory/tegra/tegra210-emc-core.c
1551
if (rate > 204000000 && !timing->trained)
drivers/memory/tegra/tegra210-emc-core.c
1554
emc->next = timing;
drivers/memory/tegra/tegra210-emc-core.c
1565
emc->last = timing;
drivers/memory/tegra/tegra210-emc-core.c
1933
struct tegra210_emc_timing *timing = &emc->timings[i];
drivers/memory/tegra/tegra210-emc-core.c
1938
config->rate = timing->rate * 1000UL;
drivers/memory/tegra/tegra210-emc-core.c
1939
config->value = timing->clk_src_emc;
drivers/memory/tegra/tegra210-emc-core.c
1941
value = timing->burst_mc_regs[MC_EMEM_ARB_MISC0_INDEX];
drivers/memory/tegra/tegra210-emc.h
1001
struct tegra210_emc_timing *timing);
drivers/memory/tegra/tegra210-emc.h
1013
void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing);
drivers/memory/tegra/tegra30-emc.c
1178
struct emc_timing *timing = NULL;
drivers/memory/tegra/tegra30-emc.c
1201
timing = &emc->timings[i];
drivers/memory/tegra/tegra30-emc.c
1205
if (!timing) {
drivers/memory/tegra/tegra30-emc.c
1211
return timing->rate;
drivers/memory/tegra/tegra30-emc.c
423
struct emc_timing *timing = NULL;
drivers/memory/tegra/tegra30-emc.c
428
timing = &emc->timings[i];
drivers/memory/tegra/tegra30-emc.c
433
if (!timing) {
drivers/memory/tegra/tegra30-emc.c
438
return timing;
drivers/memory/tegra/tegra30-emc.c
441
static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
drivers/memory/tegra/tegra30-emc.c
447
if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
drivers/memory/tegra/tegra30-emc.c
458
if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
drivers/memory/tegra/tegra30-emc.c
469
if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
drivers/memory/tegra/tegra30-emc.c
508
struct emc_timing *timing = emc_find_timing(emc, rate);
drivers/memory/tegra/tegra30-emc.c
521
if (!timing || emc->bad_state)
drivers/memory/tegra/tegra30-emc.c
525
__func__, timing->rate, rate);
drivers/memory/tegra/tegra30-emc.c
540
if (emc->dll_on == !(timing->emc_mode_1 & 0x1))
drivers/memory/tegra/tegra30-emc.c
542
else if (!(timing->emc_mode_1 & 0x1))
drivers/memory/tegra/tegra30-emc.c
547
emc->dll_on = !(timing->emc_mode_1 & 0x1);
drivers/memory/tegra/tegra30-emc.c
549
if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
drivers/memory/tegra/tegra30-emc.c
584
if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
drivers/memory/tegra/tegra30-emc.c
598
if (timing->emc_auto_cal_interval) {
drivers/memory/tegra/tegra30-emc.c
600
val ^= timing->data[74];
drivers/memory/tegra/tegra30-emc.c
619
for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
drivers/memory/tegra/tegra30-emc.c
622
writel_relaxed(timing->data[i],
drivers/memory/tegra/tegra30-emc.c
626
err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
drivers/memory/tegra/tegra30-emc.c
637
val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
drivers/memory/tegra/tegra30-emc.c
641
val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
drivers/memory/tegra/tegra30-emc.c
657
new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
drivers/memory/tegra/tegra30-emc.c
686
writel_relaxed(timing->emc_mode_1,
drivers/memory/tegra/tegra30-emc.c
699
writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
drivers/memory/tegra/tegra30-emc.c
703
if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
drivers/memory/tegra/tegra30-emc.c
704
if (timing->emc_cfg_periodic_qrst)
drivers/memory/tegra/tegra30-emc.c
720
if (timing->emc_mode_1 != emc->emc_mode_1)
drivers/memory/tegra/tegra30-emc.c
721
writel_relaxed(timing->emc_mode_1,
drivers/memory/tegra/tegra30-emc.c
724
if (timing->emc_mode_2 != emc->emc_mode_2)
drivers/memory/tegra/tegra30-emc.c
725
writel_relaxed(timing->emc_mode_2,
drivers/memory/tegra/tegra30-emc.c
728
if (timing->emc_mode_reset != emc->emc_mode_reset ||
drivers/memory/tegra/tegra30-emc.c
730
val = timing->emc_mode_reset;
drivers/memory/tegra/tegra30-emc.c
740
if (timing->emc_mode_2 != emc->emc_mode_2)
drivers/memory/tegra/tegra30-emc.c
741
writel_relaxed(timing->emc_mode_2,
drivers/memory/tegra/tegra30-emc.c
744
if (timing->emc_mode_1 != emc->emc_mode_1)
drivers/memory/tegra/tegra30-emc.c
745
writel_relaxed(timing->emc_mode_1,
drivers/memory/tegra/tegra30-emc.c
749
emc->emc_mode_1 = timing->emc_mode_1;
drivers/memory/tegra/tegra30-emc.c
750
emc->emc_mode_2 = timing->emc_mode_2;
drivers/memory/tegra/tegra30-emc.c
751
emc->emc_mode_reset = timing->emc_mode_reset;
drivers/memory/tegra/tegra30-emc.c
778
struct emc_timing *timing = emc_find_timing(emc, rate);
drivers/memory/tegra/tegra30-emc.c
798
writel_relaxed(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra30-emc.c
802
if (timing->emc_cfg_dyn_self_ref) {
drivers/memory/tegra/tegra30-emc.c
809
writel_relaxed(timing->emc_zcal_cnt_long,
drivers/memory/tegra/tegra30-emc.c
872
struct emc_timing *timing,
drivers/memory/tegra/tegra30-emc.c
885
timing->rate = value;
drivers/memory/tegra/tegra30-emc.c
888
timing->data,
drivers/memory/tegra/tegra30-emc.c
898
timing->prop = of_property_read_bool(node, dtprop);
drivers/memory/tegra/tegra30-emc.c
901
err = of_property_read_u32(node, dtprop, &timing->prop); \
drivers/memory/tegra/tegra30-emc.c
920
dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
drivers/memory/tegra/tegra30-emc.c
965
struct emc_timing *timing;
drivers/memory/tegra/tegra30-emc.c
975
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
drivers/memory/tegra/tegra30-emc.c
981
timing = emc->timings;
drivers/memory/tegra/tegra30-emc.c
984
err = load_one_timing_from_dt(emc, timing++, child);
drivers/memory/tegra/tegra30-emc.c
989
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
drivers/mmc/core/core.c
1279
void mmc_set_timing(struct mmc_host *host, unsigned int timing)
drivers/mmc/core/core.c
1281
host->ios.timing = timing;
drivers/mmc/core/core.c
902
1 << ios->bus_width, ios->timing);
drivers/mmc/core/core.c
999
host->ios.timing = MMC_TIMING_LEGACY;
drivers/mmc/core/core.h
54
void mmc_set_timing(struct mmc_host *host, unsigned int timing);
drivers/mmc/core/debugfs.c
122
switch (ios->timing) {
drivers/mmc/core/debugfs.c
161
seq_printf(s, "timing spec:\t%u (%s)\n", ios->timing, str);
drivers/mmc/core/host.c
187
if (host->ios.timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/core/host.h
64
return card->host->ios.timing == MMC_TIMING_MMC_HS200;
drivers/mmc/core/host.h
69
return card->host->ios.timing == MMC_TIMING_MMC_DDR52;
drivers/mmc/core/host.h
74
return card->host->ios.timing == MMC_TIMING_MMC_HS400;
drivers/mmc/core/host.h
84
return host->ios.timing == MMC_TIMING_SD_EXP ||
drivers/mmc/core/host.h
85
host->ios.timing == MMC_TIMING_SD_EXP_1_2V;
drivers/mmc/core/mmc.c
1521
old_timing = host->ios.timing;
drivers/mmc/core/mmc_ops.c
604
unsigned int timeout_ms, unsigned char timing,
drivers/mmc/core/mmc_ops.c
611
unsigned char old_timing = host->ios.timing;
drivers/mmc/core/mmc_ops.c
654
if (timing)
drivers/mmc/core/mmc_ops.c
655
mmc_set_timing(host, timing);
drivers/mmc/core/mmc_ops.c
659
if (err && timing)
drivers/mmc/core/mmc_ops.h
51
unsigned int timeout_ms, unsigned char timing,
drivers/mmc/core/sd.c
1543
if (host->ios.timing == MMC_TIMING_SD_HS &&
drivers/mmc/core/sd.c
1562
if (host->ios.timing == MMC_TIMING_SD_HS &&
drivers/mmc/core/sd.c
488
unsigned int timing = 0;
drivers/mmc/core/sd.c
492
timing = MMC_TIMING_UHS_SDR104;
drivers/mmc/core/sd.c
496
timing = MMC_TIMING_UHS_DDR50;
drivers/mmc/core/sd.c
500
timing = MMC_TIMING_UHS_SDR50;
drivers/mmc/core/sd.c
504
timing = MMC_TIMING_UHS_SDR25;
drivers/mmc/core/sd.c
508
timing = MMC_TIMING_UHS_SDR12;
drivers/mmc/core/sd.c
523
mmc_set_timing(card->host, timing);
drivers/mmc/core/sd.c
629
switch (card->host->ios.timing) {
drivers/mmc/core/sd.c
693
if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) {
drivers/mmc/core/sd_ops.c
277
host->ios.timing = MMC_TIMING_SD_EXP_1_2V;
drivers/mmc/core/sd_ops.c
279
host->ios.timing = MMC_TIMING_SD_EXP;
drivers/mmc/core/sd_uhs2.c
530
host->ios.timing = MMC_TIMING_UHS2_SPEED_B_HD;
drivers/mmc/core/sd_uhs2.c
534
host->ios.timing = MMC_TIMING_UHS2_SPEED_B;
drivers/mmc/core/sd_uhs2.c
542
host->ios.timing = MMC_TIMING_UHS2_SPEED_A_HD;
drivers/mmc/core/sd_uhs2.c
546
host->ios.timing = MMC_TIMING_UHS2_SPEED_A;
drivers/mmc/core/sd_uhs2.c
56
host->ios.timing = MMC_TIMING_UHS2_SPEED_A;
drivers/mmc/core/sd_uhs2.c
79
host->ios.timing = MMC_TIMING_LEGACY;
drivers/mmc/core/sd_uhs2.c
839
if (host->ios.timing == MMC_TIMING_UHS2_SPEED_B ||
drivers/mmc/core/sd_uhs2.c
840
host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD) {
drivers/mmc/core/sdio.c
521
unsigned int bus_speed, timing;
drivers/mmc/core/sdio.c
534
timing = MMC_TIMING_UHS_SDR12;
drivers/mmc/core/sdio.c
538
timing = MMC_TIMING_UHS_SDR104;
drivers/mmc/core/sdio.c
544
timing = MMC_TIMING_UHS_DDR50;
drivers/mmc/core/sdio.c
551
timing = MMC_TIMING_UHS_SDR50;
drivers/mmc/core/sdio.c
558
timing = MMC_TIMING_UHS_SDR25;
drivers/mmc/core/sdio.c
566
timing = MMC_TIMING_UHS_SDR12;
drivers/mmc/core/sdio.c
584
mmc_set_timing(card->host, timing);
drivers/mmc/core/sdio.c
618
((card->host->ios.timing == MMC_TIMING_UHS_SDR50) ||
drivers/mmc/core/sdio.c
619
(card->host->ios.timing == MMC_TIMING_UHS_SDR104)))
drivers/mmc/host/alcor.c
697
if (ios->timing == MMC_TIMING_LEGACY) {
drivers/mmc/host/atmel-mci.c
1480
if (ios->timing == MMC_TIMING_SD_HS)
drivers/mmc/host/cavium.c
867
if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/cavium.c
880
(ios->timing == MMC_TIMING_MMC_HS)) |
drivers/mmc/host/cqhci-core.c
551
u8 timing;
drivers/mmc/host/cqhci-core.c
555
timing = 0x1;
drivers/mmc/host/cqhci-core.c
559
timing = 0x0;
drivers/mmc/host/cqhci-core.c
562
timing = 0x1;
drivers/mmc/host/cqhci-core.c
574
CQHCI_CMD_TIMING(timing) | CQHCI_RESP_TYPE(resp_type));
drivers/mmc/host/cqhci-core.c
580
mmc_hostname(mmc), mrq->cmd->opcode, timing, resp_type);
drivers/mmc/host/dw_mmc-exynos.c
157
static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
drivers/mmc/host/dw_mmc-exynos.c
171
clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
drivers/mmc/host/dw_mmc-exynos.c
267
static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
drivers/mmc/host/dw_mmc-exynos.c
278
if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/dw_mmc-exynos.c
287
if (timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/dw_mmc-exynos.c
290
} else if (timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/dw_mmc-exynos.c
336
u32 timing = ios->timing, clksel;
drivers/mmc/host/dw_mmc-exynos.c
338
switch (timing) {
drivers/mmc/host/dw_mmc-exynos.c
368
dw_mci_exynos_config_hs400(host, timing);
drivers/mmc/host/dw_mmc-exynos.c
378
u32 timing[2];
drivers/mmc/host/dw_mmc-exynos.c
402
"samsung,dw-mshc-sdr-timing", timing, 2);
drivers/mmc/host/dw_mmc-exynos.c
406
priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
drivers/mmc/host/dw_mmc-exynos.c
409
"samsung,dw-mshc-ddr-timing", timing, 2);
drivers/mmc/host/dw_mmc-exynos.c
413
priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
drivers/mmc/host/dw_mmc-exynos.c
416
"samsung,dw-mshc-hs400-timing", timing, 2);
drivers/mmc/host/dw_mmc-exynos.c
422
priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
drivers/mmc/host/dw_mmc-hi3798cv200.c
32
if (ios->timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/dw_mmc-hi3798cv200.c
33
ios->timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/dw_mmc-hi3798cv200.c
40
if (ios->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/dw_mmc-hi3798cv200.c
47
if (ios->timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/dw_mmc-hi3798cv200.c
53
if (ios->timing == MMC_TIMING_MMC_HS ||
drivers/mmc/host/dw_mmc-hi3798cv200.c
54
ios->timing == MMC_TIMING_LEGACY)
drivers/mmc/host/dw_mmc-hi3798cv200.c
56
else if (ios->timing == MMC_TIMING_MMC_HS200)
drivers/mmc/host/dw_mmc-hi3798mv200.c
38
struct mmc_clk_phase phase = host->phase_map.phase[ios->timing];
drivers/mmc/host/dw_mmc-hi3798mv200.c
42
if (ios->timing == MMC_TIMING_MMC_DDR52
drivers/mmc/host/dw_mmc-hi3798mv200.c
43
|| ios->timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/dw_mmc-hi3798mv200.c
50
if (ios->timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/dw_mmc-hi3798mv200.c
72
ios->timing);
drivers/mmc/host/dw_mmc-k3.c
206
static int dw_mci_hs_set_timing(struct dw_mci *host, int timing,
drivers/mmc/host/dw_mmc-k3.c
220
drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
drivers/mmc/host/dw_mmc-k3.c
221
smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly;
drivers/mmc/host/dw_mmc-k3.c
223
smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
drivers/mmc/host/dw_mmc-k3.c
224
hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
drivers/mmc/host/dw_mmc-k3.c
226
switch (timing) {
drivers/mmc/host/dw_mmc-k3.c
306
dw_mci_hs_set_timing(host, ios->timing, -1);
drivers/mmc/host/dw_mmc-k3.c
370
dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
drivers/mmc/host/dw_mmc-k3.c
384
dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl);
drivers/mmc/host/dw_mmc-rockchip.c
182
struct mmc_clk_phase phase = host->phase_map.phase[ios->timing];
drivers/mmc/host/dw_mmc-rockchip.c
200
ios->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/dw_mmc-rockchip.c
219
if (ios->timing <= MMC_TIMING_SD_HS) {
drivers/mmc/host/dw_mmc-rockchip.c
262
switch (ios->timing) {
drivers/mmc/host/dw_mmc-starfive.c
31
if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
drivers/mmc/host/dw_mmc.c
1351
if (ios->timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/dw_mmc.c
1352
ios->timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/dw_mmc.c
1353
ios->timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/dw_mmc.c
1359
host->timing = ios->timing;
drivers/mmc/host/dw_mmc.c
960
host->timing != MMC_TIMING_MMC_HS400)
drivers/mmc/host/dw_mmc.c
968
if (host->timing != MMC_TIMING_MMC_HS200 &&
drivers/mmc/host/dw_mmc.c
969
host->timing != MMC_TIMING_UHS_SDR104 &&
drivers/mmc/host/dw_mmc.c
970
host->timing != MMC_TIMING_MMC_HS400)
drivers/mmc/host/dw_mmc.h
178
unsigned char timing;
drivers/mmc/host/loongson2-mmc.c
539
if (ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/meson-gx-mmc.c
567
switch (ios->timing) {
drivers/mmc/host/meson-gx-mmc.c
584
switch (ios->timing) {
drivers/mmc/host/mmci.c
1283
if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/mmci.c
1284
host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/mmci.c
492
if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/mmci.c
493
host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/mmci_stm32_sdmmc.c
302
if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/mmci_stm32_sdmmc.c
303
host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/mmci_stm32_sdmmc.c
345
if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50)
drivers/mmc/host/mmci_stm32_sdmmc.c
417
if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
drivers/mmc/host/mmci_stm32_sdmmc.c
418
host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
drivers/mmc/host/mmci_stm32_sdmmc.c
629
if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 &&
drivers/mmc/host/mmci_stm32_sdmmc.c
630
host->mmc->ios.timing != MMC_TIMING_MMC_HS200) ||
drivers/mmc/host/mtk-sd.c
1009
static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
drivers/mmc/host/mtk-sd.c
1028
if (host->timing != timing)
drivers/mmc/host/mtk-sd.c
1040
if (timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/mtk-sd.c
1041
timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/mtk-sd.c
1042
timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/mtk-sd.c
1043
if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/mtk-sd.c
1057
if (timing == MMC_TIMING_MMC_HS400 &&
drivers/mmc/host/mtk-sd.c
1099
host->timing = timing;
drivers/mmc/host/mtk-sd.c
1134
if (timing == MMC_TIMING_MMC_HS400 &&
drivers/mmc/host/mtk-sd.c
1143
timing);
drivers/mmc/host/mtk-sd.c
2183
if (host->mclk != ios->clock || host->timing != ios->timing)
drivers/mmc/host/mtk-sd.c
2184
msdc_set_mclk(host, ios->timing, ios->clock);
drivers/mmc/host/mtk-sd.c
2328
if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/mtk-sd.c
2329
mmc->ios.timing == MMC_TIMING_UHS_SDR104)
drivers/mmc/host/mtk-sd.c
2423
if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/mtk-sd.c
2424
mmc->ios.timing == MMC_TIMING_UHS_SDR104)
drivers/mmc/host/mtk-sd.c
507
unsigned char timing;
drivers/mmc/host/mtk-sd.c
987
switch (host->timing) {
drivers/mmc/host/mvsdio.c
645
if (ios->timing == MMC_TIMING_MMC_HS ||
drivers/mmc/host/mvsdio.c
646
ios->timing == MMC_TIMING_SD_HS)
drivers/mmc/host/omap_hsmmc.c
568
(ios->timing != MMC_TIMING_MMC_DDR52) &&
drivers/mmc/host/omap_hsmmc.c
569
(ios->timing != MMC_TIMING_UHS_DDR50) &&
drivers/mmc/host/omap_hsmmc.c
589
if (ios->timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/omap_hsmmc.c
590
ios->timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/owl-mmc.c
523
if (ios->timing == MMC_TIMING_UHS_DDR50) {
drivers/mmc/host/renesas_sdhi_core.c
149
bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400;
drivers/mmc/host/renesas_sdhi_core.c
221
if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
drivers/mmc/host/renesas_sdhi_core.c
758
host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/renesas_sdhi_core.c
836
if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
drivers/mmc/host/renesas_sdhi_core.c
837
!(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
drivers/mmc/host/renesas_sdhi_core.c
838
!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
drivers/mmc/host/rtsx_pci_sdmmc.c
1014
static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
drivers/mmc/host/rtsx_pci_sdmmc.c
1021
switch (timing) {
drivers/mmc/host/rtsx_pci_sdmmc.c
1103
sd_set_timing(host, ios->timing);
drivers/mmc/host/rtsx_pci_sdmmc.c
1108
switch (ios->timing) {
drivers/mmc/host/rtsx_pci_sdmmc.c
1291
switch (mmc->ios.timing) {
drivers/mmc/host/rtsx_pci_sdmmc.c
1312
if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
drivers/mmc/host/rtsx_pci_sdmmc.c
1313
(mmc->ios.timing == MMC_TIMING_UHS_SDR50))
drivers/mmc/host/rtsx_pci_sdmmc.c
1315
else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/rtsx_usb_sdmmc.c
1081
unsigned char timing, bool *ddr_mode)
drivers/mmc/host/rtsx_usb_sdmmc.c
1089
switch (timing) {
drivers/mmc/host/rtsx_usb_sdmmc.c
1151
sd_set_timing(host, ios->timing, &host->ddr_mode);
drivers/mmc/host/rtsx_usb_sdmmc.c
1156
switch (ios->timing) {
drivers/mmc/host/sdhci-acpi.c
545
unsigned int old_timing = host->timing;
drivers/mmc/host/sdhci-acpi.c
550
if (old_timing != host->timing && amd_host->tuned_clock) {
drivers/mmc/host/sdhci-acpi.c
551
if (host->timing == MMC_TIMING_MMC_HS400 ||
drivers/mmc/host/sdhci-acpi.c
552
host->timing == MMC_TIMING_MMC_HS200) {
drivers/mmc/host/sdhci-acpi.c
563
if (host->timing == MMC_TIMING_MMC_HS400 &&
drivers/mmc/host/sdhci-brcmstb.c
241
unsigned int timing)
drivers/mmc/host/sdhci-brcmstb.c
246
__func__, timing);
drivers/mmc/host/sdhci-brcmstb.c
250
if ((timing == MMC_TIMING_MMC_HS200) ||
drivers/mmc/host/sdhci-brcmstb.c
251
(timing == MMC_TIMING_UHS_SDR104))
drivers/mmc/host/sdhci-brcmstb.c
253
else if (timing == MMC_TIMING_UHS_SDR12)
drivers/mmc/host/sdhci-brcmstb.c
255
else if (timing == MMC_TIMING_SD_HS ||
drivers/mmc/host/sdhci-brcmstb.c
256
timing == MMC_TIMING_MMC_HS ||
drivers/mmc/host/sdhci-brcmstb.c
257
timing == MMC_TIMING_UHS_SDR25)
drivers/mmc/host/sdhci-brcmstb.c
259
else if (timing == MMC_TIMING_UHS_SDR50)
drivers/mmc/host/sdhci-brcmstb.c
261
else if ((timing == MMC_TIMING_UHS_DDR50) ||
drivers/mmc/host/sdhci-brcmstb.c
262
(timing == MMC_TIMING_MMC_DDR52))
drivers/mmc/host/sdhci-brcmstb.c
264
else if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-brcmstb.c
296
static void sdhci_brcmstb_set_72116_uhs_signaling(struct sdhci_host *host, unsigned int timing)
drivers/mmc/host/sdhci-brcmstb.c
306
reg = (timing == MMC_TIMING_MMC_HS200) ? 0 : SDIO_CFG_OP_DLY_DEFAULT;
drivers/mmc/host/sdhci-brcmstb.c
308
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-cadence.c
293
if (host->timing != MMC_TIMING_MMC_HS200)
drivers/mmc/host/sdhci-cadence.c
325
if (host->timing != MMC_TIMING_MMC_HS200 &&
drivers/mmc/host/sdhci-cadence.c
326
host->timing != MMC_TIMING_UHS_SDR104)
drivers/mmc/host/sdhci-cadence.c
355
unsigned int timing)
drivers/mmc/host/sdhci-cadence.c
360
switch (timing) {
drivers/mmc/host/sdhci-cadence.c
385
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-esdhc-imx.c
1163
if (host->timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/sdhci-esdhc-imx.c
1421
static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
drivers/mmc/host/sdhci-esdhc-imx.c
1432
switch (timing) {
drivers/mmc/host/sdhci-esdhc-imx.c
1463
(timing == MMC_TIMING_UHS_SDR104 ||
drivers/mmc/host/sdhci-esdhc-imx.c
1464
timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci-esdhc-imx.c
1465
timing == MMC_TIMING_MMC_HS400))
drivers/mmc/host/sdhci-esdhc-imx.c
1472
esdhc_change_pinstate(host, timing);
drivers/mmc/host/sdhci-esdhc-imx.c
1704
if (host->timing == MMC_TIMING_UHS_SDR50 ||
drivers/mmc/host/sdhci-esdhc-imx.c
1705
host->timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/sdhci-esdhc-imx.c
1718
if (host->timing == MMC_TIMING_UHS_SDR50 ||
drivers/mmc/host/sdhci-esdhc-imx.c
1719
host->timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/sdhci-esdhc-imx.c
2121
ret = esdhc_change_pinstate(host, host->timing);
drivers/mmc/host/sdhci-esdhc-imx.c
2151
if (host->timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/sdhci-esdhc-imx.c
2152
host->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/sdhci-msm.c
1151
if (ios->timing == MMC_TIMING_UHS_SDR50 &&
drivers/mmc/host/sdhci-msm.c
1160
!(ios->timing == MMC_TIMING_MMC_HS400 ||
drivers/mmc/host/sdhci-msm.c
1161
ios->timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci-msm.c
1162
ios->timing == MMC_TIMING_UHS_SDR104) ||
drivers/mmc/host/sdhci-msm.c
1241
if (ios.timing == MMC_TIMING_UHS_SDR50 &&
drivers/mmc/host/sdhci-msm.c
1256
msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing);
drivers/mmc/host/sdhci-msm.c
1427
if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-msm.c
1890
msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing);
drivers/mmc/host/sdhci-msm.c
361
unsigned int timing)
drivers/mmc/host/sdhci-msm.c
369
if (timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/sdhci-msm.c
370
timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/sdhci-msm.c
371
(timing == MMC_TIMING_MMC_HS400 &&
drivers/mmc/host/sdhci-msm.c
380
unsigned int timing)
drivers/mmc/host/sdhci-msm.c
390
mult = msm_get_clock_mult_for_bus_mode(host, clock, timing);
drivers/mmc/host/sdhci-msm.c
395
mmc_hostname(host->mmc), desired_rate, timing);
drivers/mmc/host/sdhci-msm.c
414
mmc_hostname(host->mmc), achieved_rate, timing);
drivers/mmc/host/sdhci-msm.c
918
if (ios.timing == MMC_TIMING_MMC_HS400 ||
drivers/mmc/host/sdhci-of-arasan.c
1036
switch (host->timing) {
drivers/mmc/host/sdhci-of-arasan.c
1082
switch (host->timing) {
drivers/mmc/host/sdhci-of-arasan.c
1150
if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/sdhci-of-arasan.c
1250
clk_data->phase_map.phase[host->timing].in_deg);
drivers/mmc/host/sdhci-of-arasan.c
1252
clk_data->phase_map.phase[host->timing].out_deg);
drivers/mmc/host/sdhci-of-arasan.c
783
switch (host->timing) {
drivers/mmc/host/sdhci-of-arasan.c
852
switch (host->timing) {
drivers/mmc/host/sdhci-of-arasan.c
912
switch (host->timing) {
drivers/mmc/host/sdhci-of-arasan.c
979
switch (host->timing) {
drivers/mmc/host/sdhci-of-aspeed.c
227
params = &sdhci->phase_map.phase[host->timing];
drivers/mmc/host/sdhci-of-aspeed.c
234
params->in_deg, params->out_deg, rate, host->timing);
drivers/mmc/host/sdhci-of-at91.c
101
unsigned int timing)
drivers/mmc/host/sdhci-of-at91.c
105
if (timing == MMC_TIMING_MMC_DDR52) {
drivers/mmc/host/sdhci-of-at91.c
110
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-dwcmshc.c
1340
static void dwcmshc_hpe_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
drivers/mmc/host/sdhci-of-dwcmshc.c
1342
dwcmshc_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-dwcmshc.c
1702
static void sdhci_eic7700_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
drivers/mmc/host/sdhci-of-dwcmshc.c
1710
dwcmshc_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-dwcmshc.c
1713
if (timing == MMC_TIMING_MMC_HS400 && host->clock == 200000000) {
drivers/mmc/host/sdhci-of-dwcmshc.c
1752
static void sdhci_eic7700_set_uhs_wrapper(struct sdhci_host *host, unsigned int timing)
drivers/mmc/host/sdhci-of-dwcmshc.c
1757
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-dwcmshc.c
1759
sdhci_eic7700_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-dwcmshc.c
461
host->mmc->ios.timing & MMC_SIGNAL_VOLTAGE_180)
drivers/mmc/host/sdhci-of-dwcmshc.c
533
unsigned int timing)
drivers/mmc/host/sdhci-of-dwcmshc.c
542
if ((timing == MMC_TIMING_MMC_HS200) ||
drivers/mmc/host/sdhci-of-dwcmshc.c
543
(timing == MMC_TIMING_UHS_SDR104))
drivers/mmc/host/sdhci-of-dwcmshc.c
545
else if (timing == MMC_TIMING_UHS_SDR12)
drivers/mmc/host/sdhci-of-dwcmshc.c
547
else if ((timing == MMC_TIMING_UHS_SDR25) ||
drivers/mmc/host/sdhci-of-dwcmshc.c
548
(timing == MMC_TIMING_MMC_HS))
drivers/mmc/host/sdhci-of-dwcmshc.c
550
else if (timing == MMC_TIMING_UHS_SDR50)
drivers/mmc/host/sdhci-of-dwcmshc.c
552
else if ((timing == MMC_TIMING_UHS_DDR50) ||
drivers/mmc/host/sdhci-of-dwcmshc.c
553
(timing == MMC_TIMING_MMC_DDR52))
drivers/mmc/host/sdhci-of-dwcmshc.c
555
else if (timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/sdhci-of-dwcmshc.c
570
unsigned int timing)
drivers/mmc/host/sdhci-of-dwcmshc.c
575
dwcmshc_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-dwcmshc.c
576
if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-of-dwcmshc.c
791
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci-of-dwcmshc.c
792
host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/sdhci-of-dwcmshc.c
850
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci-of-dwcmshc.c
851
host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-of-dwcmshc.c
854
if (rockchip_pdata->revision == 1 && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/sdhci-of-esdhc.c
1175
unsigned int timing)
drivers/mmc/host/sdhci-of-esdhc.c
1211
if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-of-esdhc.c
1214
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-esdhc.c
670
esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
drivers/mmc/host/sdhci-of-esdhc.c
673
clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
drivers/mmc/host/sdhci-of-esdhc.c
690
(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
drivers/mmc/host/sdhci-of-esdhc.c
744
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
drivers/mmc/host/sdhci-of-k1.c
161
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
drivers/mmc/host/sdhci-of-k1.c
189
static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
drivers/mmc/host/sdhci-of-k1.c
191
if (timing == MMC_TIMING_MMC_HS200)
drivers/mmc/host/sdhci-of-k1.c
194
if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-of-k1.c
197
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-of-k1.c
207
if (mmc->ios.timing <= MMC_TIMING_UHS_SDR50)
drivers/mmc/host/sdhci-of-k1.c
275
!(ios.timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci-of-k1.c
276
ios.timing == MMC_TIMING_UHS_SDR50 ||
drivers/mmc/host/sdhci-of-k1.c
277
ios.timing == MMC_TIMING_UHS_SDR104))
drivers/mmc/host/sdhci-omap.c
116
u8 timing;
drivers/mmc/host/sdhci-omap.c
1249
omap_host->timing = MMC_TIMING_LEGACY;
drivers/mmc/host/sdhci-omap.c
340
if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
drivers/mmc/host/sdhci-omap.c
601
static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
drivers/mmc/host/sdhci-omap.c
610
if (omap_host->timing == timing)
drivers/mmc/host/sdhci-omap.c
615
pinctrl_state = omap_host->pinctrl_state[timing];
drivers/mmc/host/sdhci-omap.c
623
omap_host->timing = timing;
drivers/mmc/host/sdhci-omap.c
662
sdhci_omap_set_timing(omap_host, ios->timing);
drivers/mmc/host/sdhci-omap.c
821
unsigned int timing)
drivers/mmc/host/sdhci-omap.c
830
if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/sdhci-omap.c
836
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-pci-arasan.c
267
switch (host->mmc->ios.timing) {
drivers/mmc/host/sdhci-pci-core.c
1760
if (host->timing == MMC_TIMING_MMC_HS200)
drivers/mmc/host/sdhci-pci-core.c
623
unsigned int timing)
drivers/mmc/host/sdhci-pci-core.c
626
if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
drivers/mmc/host/sdhci-pci-core.c
627
timing = MMC_TIMING_UHS_SDR25;
drivers/mmc/host/sdhci-pci-core.c
628
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-pci-gli.c
1272
if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/sdhci-pci-gli.c
1413
mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
drivers/mmc/host/sdhci-pci-gli.c
1473
mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
drivers/mmc/host/sdhci-pci-gli.c
1714
unsigned int timing)
drivers/mmc/host/sdhci-pci-gli.c
1720
if (timing == MMC_TIMING_MMC_HS200)
drivers/mmc/host/sdhci-pci-gli.c
1722
else if (timing == MMC_TIMING_MMC_HS)
drivers/mmc/host/sdhci-pci-gli.c
1724
else if (timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/sdhci-pci-gli.c
1726
else if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-pci-gli.c
619
if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/sdhci-pci-gli.c
813
if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/sdhci-pci-o2micro.c
329
if ((host->timing != MMC_TIMING_MMC_HS200) &&
drivers/mmc/host/sdhci-pci-o2micro.c
330
(host->timing != MMC_TIMING_UHS_SDR104) &&
drivers/mmc/host/sdhci-pci-o2micro.c
331
(host->timing != MMC_TIMING_UHS_SDR50))
drivers/mmc/host/sdhci-pci-o2micro.c
354
if (host->timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci-pci-o2micro.c
355
host->timing == MMC_TIMING_UHS_SDR104) {
drivers/mmc/host/sdhci-pci-o2micro.c
610
if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
drivers/mmc/host/sdhci-pci-o2micro.c
650
if (host->mmc->ios.timing == MMC_TIMING_SD_EXP_1_2V &&
drivers/mmc/host/sdhci-pci-o2micro.c
684
host->mmc->ios.timing = MMC_TIMING_LEGACY;
drivers/mmc/host/sdhci-sprd.c
101
u8 timing;
drivers/mmc/host/sdhci-sprd.c
332
unsigned int timing)
drivers/mmc/host/sdhci-sprd.c
339
if (timing == host->timing)
drivers/mmc/host/sdhci-sprd.c
345
switch (timing) {
drivers/mmc/host/sdhci-sprd.c
377
sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
drivers/mmc/host/sdhci-sprd.c
649
dll_dly = p[mmc->ios.timing];
drivers/mmc/host/sdhci-sprd.c
676
p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK;
drivers/mmc/host/sdhci-sprd.c
677
p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK);
drivers/mmc/host/sdhci-sprd.c
679
p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK);
drivers/mmc/host/sdhci-sprd.c
680
p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
drivers/mmc/host/sdhci-sprd.c
684
mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]);
drivers/mmc/host/sdhci-sprd.c
687
sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY);
drivers/mmc/host/sdhci-sprd.c
717
index = sdhci_sprd_phy_cfgs[i].timing;
drivers/mmc/host/sdhci-tegra.c
1007
unsigned timing)
drivers/mmc/host/sdhci-tegra.c
1018
switch (timing) {
drivers/mmc/host/sdhci-tegra.c
1053
sdhci_set_uhs_signaling(host, timing);
drivers/mmc/host/sdhci-tegra.c
536
switch (ios->timing) {
drivers/mmc/host/sdhci-uhs2.c
280
(ios->timing == MMC_TIMING_UHS2_SPEED_A ||
drivers/mmc/host/sdhci-uhs2.c
281
ios->timing == MMC_TIMING_UHS2_SPEED_A_HD ||
drivers/mmc/host/sdhci-uhs2.c
282
ios->timing == MMC_TIMING_UHS2_SPEED_B ||
drivers/mmc/host/sdhci-uhs2.c
283
ios->timing == MMC_TIMING_UHS2_SPEED_B_HD))
drivers/mmc/host/sdhci-uhs2.c
288
host->timing = ios->timing;
drivers/mmc/host/sdhci-uhs2.c
307
mmc_hostname(mmc), ios->clock, ios->power_mode, ios->vdd, ios->timing);
drivers/mmc/host/sdhci-uhs2.c
489
if (host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B ||
drivers/mmc/host/sdhci-uhs2.c
490
host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD)
drivers/mmc/host/sdhci-xenon-phy.c
473
if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
drivers/mmc/host/sdhci-xenon-phy.c
520
unsigned char timing)
drivers/mmc/host/sdhci-xenon-phy.c
536
switch (timing) {
drivers/mmc/host/sdhci-xenon-phy.c
575
unsigned char timing)
drivers/mmc/host/sdhci-xenon-phy.c
606
if (timing == MMC_TIMING_LEGACY) {
drivers/mmc/host/sdhci-xenon-phy.c
607
xenon_emmc_phy_slow_mode(host, timing);
drivers/mmc/host/sdhci-xenon-phy.c
622
if (xenon_emmc_phy_slow_mode(host, timing))
drivers/mmc/host/sdhci-xenon-phy.c
644
switch (timing) {
drivers/mmc/host/sdhci-xenon-phy.c
667
if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-xenon-phy.c
776
switch (host->timing) {
drivers/mmc/host/sdhci-xenon-phy.c
828
(ios->timing == priv->timing))
drivers/mmc/host/sdhci-xenon-phy.c
831
xenon_emmc_phy_set(host, ios->timing);
drivers/mmc/host/sdhci-xenon-phy.c
836
priv->timing = ios->timing;
drivers/mmc/host/sdhci-xenon-phy.c
840
if (ios->timing == MMC_TIMING_LEGACY)
drivers/mmc/host/sdhci-xenon.c
199
unsigned int timing)
drivers/mmc/host/sdhci-xenon.c
206
if (timing == MMC_TIMING_MMC_HS200)
drivers/mmc/host/sdhci-xenon.c
208
else if (timing == MMC_TIMING_UHS_SDR104)
drivers/mmc/host/sdhci-xenon.c
210
else if (timing == MMC_TIMING_UHS_SDR12)
drivers/mmc/host/sdhci-xenon.c
212
else if (timing == MMC_TIMING_UHS_SDR25)
drivers/mmc/host/sdhci-xenon.c
214
else if (timing == MMC_TIMING_UHS_SDR50)
drivers/mmc/host/sdhci-xenon.c
216
else if ((timing == MMC_TIMING_UHS_DDR50) ||
drivers/mmc/host/sdhci-xenon.c
217
(timing == MMC_TIMING_MMC_DDR52))
drivers/mmc/host/sdhci-xenon.c
219
else if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci-xenon.c
292
if ((ios->timing == MMC_TIMING_MMC_HS400) ||
drivers/mmc/host/sdhci-xenon.c
293
(ios->timing == MMC_TIMING_MMC_HS200) ||
drivers/mmc/host/sdhci-xenon.c
294
(ios->timing == MMC_TIMING_MMC_HS)) {
drivers/mmc/host/sdhci-xenon.c
361
if (host->timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/sdhci-xenon.c
362
host->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/sdhci-xenon.h
89
unsigned char timing;
drivers/mmc/host/sdhci.c
1876
switch (host->timing) {
drivers/mmc/host/sdhci.c
2297
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
drivers/mmc/host/sdhci.c
2304
if ((timing == MMC_TIMING_MMC_HS200) ||
drivers/mmc/host/sdhci.c
2305
(timing == MMC_TIMING_UHS_SDR104))
drivers/mmc/host/sdhci.c
2307
else if (timing == MMC_TIMING_UHS_SDR12)
drivers/mmc/host/sdhci.c
2309
else if (timing == MMC_TIMING_UHS_SDR25)
drivers/mmc/host/sdhci.c
2311
else if (timing == MMC_TIMING_UHS_SDR50)
drivers/mmc/host/sdhci.c
2313
else if ((timing == MMC_TIMING_UHS_DDR50) ||
drivers/mmc/host/sdhci.c
2314
(timing == MMC_TIMING_MMC_DDR52))
drivers/mmc/host/sdhci.c
2316
else if (timing == MMC_TIMING_MMC_HS400)
drivers/mmc/host/sdhci.c
2322
static bool sdhci_timing_has_preset(unsigned char timing)
drivers/mmc/host/sdhci.c
2324
switch (timing) {
drivers/mmc/host/sdhci.c
2336
static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
drivers/mmc/host/sdhci.c
2339
sdhci_timing_has_preset(timing);
drivers/mmc/host/sdhci.c
2350
(sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
drivers/mmc/host/sdhci.c
2429
host->timing == ios->timing &&
drivers/mmc/host/sdhci.c
2437
if (ios->timing == MMC_TIMING_SD_HS ||
drivers/mmc/host/sdhci.c
2438
ios->timing == MMC_TIMING_MMC_HS ||
drivers/mmc/host/sdhci.c
2439
ios->timing == MMC_TIMING_MMC_HS400 ||
drivers/mmc/host/sdhci.c
2440
ios->timing == MMC_TIMING_MMC_HS200 ||
drivers/mmc/host/sdhci.c
2441
ios->timing == MMC_TIMING_MMC_DDR52 ||
drivers/mmc/host/sdhci.c
2442
ios->timing == MMC_TIMING_UHS_SDR50 ||
drivers/mmc/host/sdhci.c
2443
ios->timing == MMC_TIMING_UHS_SDR104 ||
drivers/mmc/host/sdhci.c
2444
ios->timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/sdhci.c
2445
ios->timing == MMC_TIMING_UHS_SDR25)
drivers/mmc/host/sdhci.c
2493
host->ops->set_uhs_signaling(host, ios->timing);
drivers/mmc/host/sdhci.c
2494
host->timing = ios->timing;
drivers/mmc/host/sdhci.c
2496
if (sdhci_preset_needed(host, ios->timing)) {
drivers/mmc/host/sdhci.c
2930
switch (host->timing) {
drivers/mmc/host/sdhci.h
646
unsigned timing; /* Current timing */
drivers/mmc/host/sdhci.h
861
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
drivers/mmc/host/sdhci_am654.c
260
unsigned char timing)
drivers/mmc/host/sdhci_am654.c
270
sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
drivers/mmc/host/sdhci_am654.c
271
sdhci_am654->itap_del_ena[timing]);
drivers/mmc/host/sdhci_am654.c
278
unsigned char timing = host->mmc->ios.timing;
drivers/mmc/host/sdhci_am654.c
287
otap_del_sel = sdhci_am654->otap_del_sel[timing];
drivers/mmc/host/sdhci_am654.c
294
if (timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/sdhci_am654.c
305
if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
drivers/mmc/host/sdhci_am654.c
309
if (timing == MMC_TIMING_MMC_HS400) {
drivers/mmc/host/sdhci_am654.c
310
sdhci_am654->itap_del_ena[timing] = 0x1;
drivers/mmc/host/sdhci_am654.c
311
sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
drivers/mmc/host/sdhci_am654.c
314
sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
drivers/mmc/host/sdhci_am654.c
315
sdhci_am654->itap_del_ena[timing]);
drivers/mmc/host/sdhci_am654.c
317
sdhci_am654_setup_delay_chain(sdhci_am654, timing);
drivers/mmc/host/sdhci_am654.c
330
unsigned char timing = host->mmc->ios.timing;
drivers/mmc/host/sdhci_am654.c
337
otap_del_sel = sdhci_am654->otap_del_sel[timing];
drivers/mmc/host/sdhci_am654.c
344
itap_del_ena = sdhci_am654->itap_del_ena[timing];
drivers/mmc/host/sdhci_am654.c
345
itap_del_sel = sdhci_am654->itap_del_sel[timing];
drivers/mmc/host/sdhci_am654.c
394
unsigned char timing = host->mmc->ios.timing;
drivers/mmc/host/sdhci_am654.c
399
switch (timing) {
drivers/mmc/host/sdhci_am654.c
533
unsigned char timing = host->mmc->ios.timing;
drivers/mmc/host/sdhci_am654.c
543
sdhci_am654->itap_del_ena[timing] = 0x1;
drivers/mmc/host/sdhci_am654.c
546
sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
drivers/mmc/host/sdhci_am654.c
577
unsigned char timing = host->mmc->ios.timing;
drivers/mmc/host/sdhci_am654.c
593
sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]);
drivers/mmc/host/sdhci_am654.c
595
sdhci_am654->itap_del_sel[timing] = itapdly;
drivers/mmc/host/sh_mmcif.c
1109
host->timing = ios->timing;
drivers/mmc/host/sh_mmcif.c
224
unsigned char timing;
drivers/mmc/host/sh_mmcif.c
885
switch (host->timing) {
drivers/mmc/host/sunplus-mmc.c
251
static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing)
drivers/mmc/host/sunplus-mmc.c
258
switch (timing) {
drivers/mmc/host/sunplus-mmc.c
777
spmmc_set_bus_timing(host, ios->timing);
drivers/mmc/host/sunxi-mmc.c
740
if (ios->timing != MMC_TIMING_UHS_DDR50 &&
drivers/mmc/host/sunxi-mmc.c
741
ios->timing != MMC_TIMING_MMC_DDR52) {
drivers/mmc/host/sunxi-mmc.c
786
if (ios->timing == MMC_TIMING_MMC_DDR52 &&
drivers/mmc/host/sunxi-mmc.c
890
if (ios->timing == MMC_TIMING_UHS_DDR50 ||
drivers/mmc/host/sunxi-mmc.c
891
ios->timing == MMC_TIMING_MMC_DDR52)
drivers/mmc/host/uniphier-sd.c
441
if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR50 ||
drivers/mmc/host/uniphier-sd.c
442
host->mmc->ios.timing == MMC_TIMING_UHS_SDR104)
drivers/mmc/host/usdhi6rol0.c
750
if (ios->timing != MMC_TIMING_UHS_DDR50) {
drivers/mmc/host/usdhi6rol0.c
825
ios->clock, ios->vdd, ios->power_mode, ios->bus_width, ios->timing);
drivers/mmc/host/usdhi6rol0.c
853
if (ios->timing == MMC_TIMING_UHS_DDR50)
drivers/mmc/host/usdhi6rol0.c
860
mode = ios->timing == MMC_TIMING_UHS_DDR50;
drivers/mmc/host/ushc.c
377
ushc_set_bus_freq(ushc, ios->clock, ios->timing == MMC_TIMING_SD_HS);
drivers/mmc/host/via-sdmmc.c
745
if (ios->timing == MMC_TIMING_SD_HS)
drivers/mtd/nand/raw/cadence-nand-controller.c
2367
static int calc_cycl(u32 timing, u32 clock)
drivers/mtd/nand/raw/cadence-nand-controller.c
2369
if (timing == 0 || clock == 0)
drivers/mtd/nand/raw/cadence-nand-controller.c
2372
if ((timing % clock) > 0)
drivers/mtd/nand/raw/cadence-nand-controller.c
2373
return timing / clock;
drivers/mtd/nand/raw/cadence-nand-controller.c
2375
return timing / clock - 1;
drivers/mtd/nand/raw/cafe_nand.c
728
timing[0], timing[1], timing[2]);
drivers/mtd/nand/raw/cafe_nand.c
730
timing[0] = cafe_readl(cafe, NAND_TIMING1);
drivers/mtd/nand/raw/cafe_nand.c
731
timing[1] = cafe_readl(cafe, NAND_TIMING2);
drivers/mtd/nand/raw/cafe_nand.c
732
timing[2] = cafe_readl(cafe, NAND_TIMING3);
drivers/mtd/nand/raw/cafe_nand.c
734
if (timing[0] | timing[1] | timing[2]) {
drivers/mtd/nand/raw/cafe_nand.c
736
timing[0], timing[1], timing[2]);
drivers/mtd/nand/raw/cafe_nand.c
739
timing[0] = timing[1] = timing[2] = 0xffffffff;
drivers/mtd/nand/raw/cafe_nand.c
747
cafe_writel(cafe, timing[0], NAND_TIMING1);
drivers/mtd/nand/raw/cafe_nand.c
748
cafe_writel(cafe, timing[1], NAND_TIMING2);
drivers/mtd/nand/raw/cafe_nand.c
749
cafe_writel(cafe, timing[2], NAND_TIMING3);
drivers/mtd/nand/raw/cafe_nand.c
853
cafe_writel(cafe, timing[0], NAND_TIMING1);
drivers/mtd/nand/raw/cafe_nand.c
854
cafe_writel(cafe, timing[1], NAND_TIMING2);
drivers/mtd/nand/raw/cafe_nand.c
855
cafe_writel(cafe, timing[2], NAND_TIMING3);
drivers/mtd/nand/raw/cafe_nand.c
92
static int timing[3];
drivers/mtd/nand/raw/cafe_nand.c
93
module_param_array(timing, int, &numtimings, 0644);
drivers/mtd/nand/raw/fsl_ifc_nand.c
339
int timing = IFC_FIR_OP_RB;
drivers/mtd/nand/raw/fsl_ifc_nand.c
341
timing = IFC_FIR_OP_RBCD;
drivers/mtd/nand/raw/fsl_ifc_nand.c
347
(timing << IFC_NAND_FIR0_OP2_SHIFT),
drivers/mtd/nand/raw/meson_nand.c
185
struct nand_timing timing;
drivers/mtd/nand/raw/meson_nand.c
274
nfc->timing.twb = meson_chip->twb;
drivers/mtd/nand/raw/meson_nand.c
275
nfc->timing.tadl = meson_chip->tadl;
drivers/mtd/nand/raw/meson_nand.c
276
nfc->timing.tbers_max = meson_chip->tbers_max;
drivers/mtd/nand/raw/meson_nand.c
458
meson_nfc_cmd_idle(nfc, nfc->timing.twb);
drivers/mtd/nand/raw/meson_nand.c
470
cmd = NFC_CMD_RB | NFC_CMD_RB_INT_NO_PIN | nfc->timing.tbers_max;
drivers/mtd/nand/raw/meson_nand.c
488
meson_nfc_cmd_idle(nfc, nfc->timing.twb);
drivers/mtd/nand/raw/meson_nand.c
500
| nfc->param.chip_select | nfc->timing.tbers_max;
drivers/mtd/nand/raw/meson_nand.c
739
meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
drivers/mtd/nand/raw/rockchip-nand-controller.c
159
u32 timing;
drivers/mtd/nand/raw/rockchip-nand-controller.c
290
if (nfc->cur_timing != rknand->timing) {
drivers/mtd/nand/raw/rockchip-nand-controller.c
291
writel(rknand->timing, nfc->regs + NFC_FMWAIT);
drivers/mtd/nand/raw/rockchip-nand-controller.c
292
nfc->cur_timing = rknand->timing;
drivers/mtd/nand/raw/rockchip-nand-controller.c
463
rknand->timing = ACCTIMING(tc2rw, trwpw, trw2c);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1421
unsigned long timing, tar, tclr, thiz, twait;
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1425
timing = DIV_ROUND_UP(tar, hclkp) - 1;
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1426
tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1429
timing = DIV_ROUND_UP(tclr, hclkp) - 1;
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1430
tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1443
timing = DIV_ROUND_UP(twait, hclkp);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1444
tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1459
timing = DIV_ROUND_UP(tset_mem, hclkp);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1460
tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1477
timing = DIV_ROUND_UP(thold_mem, hclkp);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1478
tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1500
timing = DIV_ROUND_UP(tset_att, hclkp);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1501
tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1539
timing = DIV_ROUND_UP(thold_att, hclkp);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1540
tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
drivers/net/can/grcan.c
410
u32 timing = 0;
drivers/net/can/grcan.c
437
timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
drivers/net/can/grcan.c
438
timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
drivers/net/can/grcan.c
439
timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
drivers/net/can/grcan.c
440
timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
drivers/net/can/grcan.c
441
timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
drivers/net/can/grcan.c
442
netdev_info(dev, "setting timing=0x%x\n", timing);
drivers/net/can/grcan.c
443
grcan_write_bits(®s->conf, timing, GRCAN_CONF_TIMING);
drivers/net/wireless/intel/iwlegacy/3945-mac.c
658
le16_to_cpu(il->timing.beacon_interval));
drivers/net/wireless/intel/iwlegacy/3945-mac.c
672
le16_to_cpu(il->timing.beacon_interval));
drivers/net/wireless/intel/iwlegacy/4965.c
1467
u16 beacon_interval = le16_to_cpu(il->timing.beacon_interval);
drivers/net/wireless/intel/iwlegacy/common.c
3644
memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
drivers/net/wireless/intel/iwlegacy/common.c
3646
il->timing.timestamp = cpu_to_le64(il->timestamp);
drivers/net/wireless/intel/iwlegacy/common.c
3647
il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
drivers/net/wireless/intel/iwlegacy/common.c
3655
il->timing.atim_win = 0;
drivers/net/wireless/intel/iwlegacy/common.c
3661
il->timing.beacon_interval = cpu_to_le16(beacon_int);
drivers/net/wireless/intel/iwlegacy/common.c
3666
il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
drivers/net/wireless/intel/iwlegacy/common.c
3668
il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
drivers/net/wireless/intel/iwlegacy/common.c
3671
le16_to_cpu(il->timing.beacon_interval),
drivers/net/wireless/intel/iwlegacy/common.c
3672
le32_to_cpu(il->timing.beacon_init_val),
drivers/net/wireless/intel/iwlegacy/common.c
3673
le16_to_cpu(il->timing.atim_win));
drivers/net/wireless/intel/iwlegacy/common.c
3675
return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
drivers/net/wireless/intel/iwlegacy/common.c
3676
&il->timing);
drivers/net/wireless/intel/iwlegacy/common.h
1241
struct il_rxon_time_cmd timing;
drivers/net/wireless/intel/iwlwifi/dvm/dev.h
491
struct iwl_rxon_time_cmd timing;
drivers/net/wireless/intel/iwlwifi/dvm/devices.c
400
u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
drivers/net/wireless/intel/iwlwifi/dvm/devices.c
561
u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
285
memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd));
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
287
ctx->timing.timestamp = cpu_to_le64(priv->timestamp);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
288
ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
296
ctx->timing.atim_window = 0;
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
303
ctx->timing.beacon_interval =
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
304
priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval;
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
305
beacon_int = le16_to_cpu(ctx->timing.beacon_interval);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
312
ctx->timing.beacon_interval =
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
313
priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval;
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
314
beacon_int = le16_to_cpu(ctx->timing.beacon_interval);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
318
ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
326
ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
328
ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1;
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
332
le16_to_cpu(ctx->timing.beacon_interval),
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
333
le32_to_cpu(ctx->timing.beacon_init_val),
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
334
le16_to_cpu(ctx->timing.atim_window));
drivers/net/wireless/intel/iwlwifi/dvm/rxon.c
337
0, sizeof(ctx->timing), &ctx->timing);
drivers/net/wireless/intel/iwlwifi/fw/api/tdls.h
64
struct iwl_tdls_channel_switch_timing timing;
drivers/net/wireless/intel/iwlwifi/mld/scan.c
533
const struct iwl_mld_scan_timing_params *timing =
drivers/net/wireless/intel/iwlwifi/mld/scan.c
550
gp->max_out_of_time[SCAN_LB_LMAC_IDX] = cpu_to_le32(timing->max_out_time);
drivers/net/wireless/intel/iwlwifi/mld/scan.c
551
gp->suspend_time[SCAN_LB_LMAC_IDX] = cpu_to_le32(timing->suspend_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1296
struct iwl_mvm_scan_timing_params *timing, *hb_timing;
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1299
timing = &scan_timing[params->type];
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1326
cpu_to_le32(timing->max_out_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1328
cpu_to_le32(timing->suspend_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1372
cpu_to_le32(timing->max_out_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1374
cpu_to_le32(timing->suspend_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1379
cpu_to_le32(timing->max_out_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1381
cpu_to_le32(timing->suspend_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1404
struct iwl_mvm_scan_timing_params *timing, *hb_timing;
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1407
timing = &scan_timing[params->type];
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1429
cpu_to_le32(timing->max_out_time);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1431
cpu_to_le32(timing->suspend_time);
drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
360
tail->timing.frame_timestamp = cpu_to_le32(timestamp);
drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
361
tail->timing.switch_time = cpu_to_le32(switch_time);
drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
362
tail->timing.switch_timeout = cpu_to_le32(switch_timeout);
drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
398
tail->timing.max_offchan_duration =
drivers/net/wireless/realtek/rtl8xxxu/8188e.c
1358
static void rtl8188e_set_tx_rpt_timing(struct rtl8xxxu_ra_info *ra, u8 timing)
drivers/net/wireless/realtek/rtl8xxxu/8188e.c
1366
if (timing == DEFAULT_TIMING) {
drivers/net/wireless/realtek/rtl8xxxu/8188e.c
1368
} else if (timing == INCREASE_TIMING) {
drivers/net/wireless/realtek/rtl8xxxu/8188e.c
1371
} else if (timing == DECREASE_TIMING) {
drivers/net/wireless/rsi/rsi_91x_sdio.c
190
host->ios.timing = MMC_TIMING_LEGACY;
drivers/net/wireless/rsi/rsi_91x_sdio.c
297
host->ios.timing = MMC_TIMING_SD_HS;
drivers/nfc/pn533/pn533.c
2645
struct pn533_config_timing timing;
drivers/nfc/pn533/pn533.c
2660
timing.rfu = PN533_CONFIG_TIMING_102;
drivers/nfc/pn533/pn533.c
2661
timing.atr_res_timeout = PN533_CONFIG_TIMING_102;
drivers/nfc/pn533/pn533.c
2662
timing.dep_timeout = PN533_CONFIG_TIMING_204;
drivers/nfc/pn533/pn533.c
2682
(u8 *)&timing, sizeof(timing));
drivers/nvmem/imx-ocotp.c
244
u32 timing;
drivers/nvmem/imx-ocotp.c
284
timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
drivers/nvmem/imx-ocotp.c
285
timing |= strobe_prog & 0x00000FFF;
drivers/nvmem/imx-ocotp.c
286
timing |= (relax << 12) & 0x0000F000;
drivers/nvmem/imx-ocotp.c
287
timing |= (strobe_read << 16) & 0x003F0000;
drivers/nvmem/imx-ocotp.c
289
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
drivers/nvmem/imx-ocotp.c
296
u32 timing;
drivers/nvmem/imx-ocotp.c
307
timing = strobe_prog & 0x00000FFF;
drivers/nvmem/imx-ocotp.c
308
timing |= (fsource << 12) & 0x000FF000;
drivers/nvmem/imx-ocotp.c
310
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
drivers/nvmem/vf610-ocotp.c
118
u32 timing;
drivers/nvmem/vf610-ocotp.c
127
timing = BF(relax, OCOTP_TIMING_RELAX);
drivers/nvmem/vf610-ocotp.c
128
timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ);
drivers/nvmem/vf610-ocotp.c
129
timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG);
drivers/nvmem/vf610-ocotp.c
131
return timing;
drivers/nvmem/vf610-ocotp.c
158
writel(ocotp->timing, base + OCOTP_TIMING);
drivers/nvmem/vf610-ocotp.c
233
ocotp_dev->timing = vf610_ocotp_calculate_timing(ocotp_dev);
drivers/nvmem/vf610-ocotp.c
94
int timing;
drivers/pcmcia/cistpl.c
1131
p = parse_timing(p, q, &entry->timing);
drivers/pcmcia/cistpl.c
1135
entry->timing.wait = 0;
drivers/pcmcia/cistpl.c
1136
entry->timing.ready = 0;
drivers/pcmcia/cistpl.c
1137
entry->timing.reserved = 0;
drivers/pcmcia/cistpl.c
943
static u_char *parse_timing(u_char *p, u_char *q, cistpl_timing_t *timing)
drivers/pcmcia/cistpl.c
953
timing->wait = SPEED_CVT(*p);
drivers/pcmcia/cistpl.c
954
timing->waitscale = exponent[scale & 3];
drivers/pcmcia/cistpl.c
956
timing->wait = 0;
drivers/pcmcia/cistpl.c
961
timing->ready = SPEED_CVT(*p);
drivers/pcmcia/cistpl.c
962
timing->rdyscale = exponent[scale & 7];
drivers/pcmcia/cistpl.c
964
timing->ready = 0;
drivers/pcmcia/cistpl.c
969
timing->reserved = SPEED_CVT(*p);
drivers/pcmcia/cistpl.c
970
timing->rsvscale = exponent[scale];
drivers/pcmcia/cistpl.c
972
timing->reserved = 0;
drivers/pcmcia/pxa2xx_base.c
162
struct soc_pcmcia_timing timing;
drivers/pcmcia/pxa2xx_base.c
165
soc_common_pcmcia_get_timing(skt, &timing);
drivers/pcmcia/pxa2xx_base.c
168
pxa2xx_pcmcia_mcmem(sock, timing.mem, clk),
drivers/pcmcia/pxa2xx_base.c
169
pxa2xx_pcmcia_mcatt(sock, timing.attr, clk),
drivers/pcmcia/pxa2xx_base.c
170
pxa2xx_pcmcia_mcio(sock, timing.io, clk));
drivers/pcmcia/sa11xx_base.c
146
struct soc_pcmcia_timing timing;
drivers/pcmcia/sa11xx_base.c
151
soc_common_pcmcia_get_timing(skt, &timing);
drivers/pcmcia/sa11xx_base.c
153
p+=sprintf(p, "I/O : %uns (%uns)\n", timing.io,
drivers/pcmcia/sa11xx_base.c
156
p+=sprintf(p, "attribute: %uns (%uns)\n", timing.attr,
drivers/pcmcia/sa11xx_base.c
159
p+=sprintf(p, "common : %uns (%uns)\n", timing.mem,
drivers/pcmcia/sa11xx_base.c
81
struct soc_pcmcia_timing timing;
drivers/pcmcia/sa11xx_base.c
86
soc_common_pcmcia_get_timing(skt, &timing);
drivers/pcmcia/sa11xx_base.c
88
bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
drivers/pcmcia/sa11xx_base.c
89
bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
drivers/pcmcia/sa11xx_base.c
90
bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
drivers/pcmcia/soc_common.c
134
struct soc_pcmcia_timing *timing)
drivers/pcmcia/soc_common.c
136
timing->io =
drivers/pcmcia/soc_common.c
138
timing->mem =
drivers/pcmcia/soc_common.c
140
timing->attr =
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1213
const struct samsung_mipi_dphy_timing *timing;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1217
timing = samsung_mipi_dphy_get_timing(samsung);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1241
val |= T_LPX(timing->lpx);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1245
val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1248
val = T_HS_EXIT(timing->hs_exit) | T_CLK_TRAIL(timing->clk_trail_eot);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1251
val = T_CLK_POST(timing->clk_post);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1268
const struct samsung_mipi_dphy_timing *timing;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1272
timing = samsung_mipi_dphy_get_timing(samsung);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1302
val |= T_LPX(timing->lpx);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1309
val = T_HS_ZERO(timing->hs_zero) | T_HS_PREPARE(timing->hs_prepare);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1315
val = T_HS_EXIT(timing->hs_exit) | T_HS_TRAIL(timing->hs_trail_eot);
drivers/spi/spi-aspeed-smc.c
1188
writel(fread_timing_val, aspi->regs + data->timing);
drivers/spi/spi-aspeed-smc.c
1214
writel(fread_timing_val, aspi->regs + data->timing);
drivers/spi/spi-aspeed-smc.c
1461
((chip)->aspi->regs + (chip)->aspi->data->timing + \
drivers/spi/spi-aspeed-smc.c
1569
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
1587
.timing = 0x14,
drivers/spi/spi-aspeed-smc.c
1601
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
1619
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
1638
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
1657
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
1676
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
1694
.timing = CE0_TIMING_COMPENSATION_REG,
drivers/spi/spi-aspeed-smc.c
82
u32 timing;
drivers/staging/greybus/sdio.c
595
u8 timing;
drivers/staging/greybus/sdio.c
642
switch (ios->timing) {
drivers/staging/greybus/sdio.c
645
timing = GB_SDIO_TIMING_LEGACY;
drivers/staging/greybus/sdio.c
648
timing = GB_SDIO_TIMING_MMC_HS;
drivers/staging/greybus/sdio.c
651
timing = GB_SDIO_TIMING_SD_HS;
drivers/staging/greybus/sdio.c
654
timing = GB_SDIO_TIMING_UHS_SDR12;
drivers/staging/greybus/sdio.c
657
timing = GB_SDIO_TIMING_UHS_SDR25;
drivers/staging/greybus/sdio.c
660
timing = GB_SDIO_TIMING_UHS_SDR50;
drivers/staging/greybus/sdio.c
663
timing = GB_SDIO_TIMING_UHS_SDR104;
drivers/staging/greybus/sdio.c
666
timing = GB_SDIO_TIMING_UHS_DDR50;
drivers/staging/greybus/sdio.c
669
timing = GB_SDIO_TIMING_MMC_DDR52;
drivers/staging/greybus/sdio.c
672
timing = GB_SDIO_TIMING_MMC_HS200;
drivers/staging/greybus/sdio.c
675
timing = GB_SDIO_TIMING_MMC_HS400;
drivers/staging/greybus/sdio.c
678
request.timing = timing;
drivers/usb/dwc3/ep0.c
709
} __packed timing;
drivers/usb/dwc3/ep0.c
713
memcpy(&timing, req->buf, sizeof(timing));
drivers/usb/dwc3/ep0.c
715
dwc->u1sel = timing.u1sel;
drivers/usb/dwc3/ep0.c
716
dwc->u1pel = timing.u1pel;
drivers/usb/dwc3/ep0.c
717
dwc->u2sel = le16_to_cpu(timing.u2sel);
drivers/usb/dwc3/ep0.c
718
dwc->u2pel = le16_to_cpu(timing.u2pel);
drivers/video/backlight/ktd2801-backlight.c
71
ktd2801->props.timing = ktd2801_timing;
drivers/video/fbdev/gbefb.c
38
struct gbe_timing_info timing;
drivers/video/fbdev/gbefb.c
411
static void gbefb_setup_flatpanel(struct gbe_timing_info *timing)
drivers/video/fbdev/gbefb.c
417
(timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
drivers/video/fbdev/gbefb.c
419
(timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
drivers/video/fbdev/gbefb.c
427
timing->pll_m = 4;
drivers/video/fbdev/gbefb.c
428
timing->pll_n = 1;
drivers/video/fbdev/gbefb.c
429
timing->pll_p = 0;
drivers/video/fbdev/gbefb.c
456
struct gbe_timing_info *timing)
drivers/video/fbdev/gbefb.c
504
if (timing) {
drivers/video/fbdev/gbefb.c
505
timing->width = var->xres;
drivers/video/fbdev/gbefb.c
506
timing->height = var->yres;
drivers/video/fbdev/gbefb.c
507
timing->pll_m = best_m;
drivers/video/fbdev/gbefb.c
508
timing->pll_n = best_n;
drivers/video/fbdev/gbefb.c
509
timing->pll_p = best_p;
drivers/video/fbdev/gbefb.c
510
timing->cfreq = gbe_pll->clock_rate * 1000 * timing->pll_m /
drivers/video/fbdev/gbefb.c
511
(timing->pll_n << timing->pll_p);
drivers/video/fbdev/gbefb.c
512
timing->htotal = var->left_margin + var->xres +
drivers/video/fbdev/gbefb.c
514
timing->vtotal = var->upper_margin + var->yres +
drivers/video/fbdev/gbefb.c
516
timing->fields_sec = 1000 * timing->cfreq / timing->htotal *
drivers/video/fbdev/gbefb.c
517
1000 / timing->vtotal;
drivers/video/fbdev/gbefb.c
518
timing->hblank_start = var->xres;
drivers/video/fbdev/gbefb.c
519
timing->vblank_start = var->yres;
drivers/video/fbdev/gbefb.c
520
timing->hblank_end = timing->htotal;
drivers/video/fbdev/gbefb.c
521
timing->hsync_start = var->xres + var->right_margin + 1;
drivers/video/fbdev/gbefb.c
522
timing->hsync_end = timing->hsync_start + var->hsync_len;
drivers/video/fbdev/gbefb.c
523
timing->vblank_end = timing->vtotal;
drivers/video/fbdev/gbefb.c
524
timing->vsync_start = var->yres + var->lower_margin + 1;
drivers/video/fbdev/gbefb.c
525
timing->vsync_end = timing->vsync_start + var->vsync_len;
drivers/video/fbdev/gbefb.c
531
static void gbe_set_timing_info(struct gbe_timing_info *timing)
drivers/video/fbdev/gbefb.c
538
SET_GBE_FIELD(DOTCLK, M, val, timing->pll_m - 1);
drivers/video/fbdev/gbefb.c
539
SET_GBE_FIELD(DOTCLK, N, val, timing->pll_n - 1);
drivers/video/fbdev/gbefb.c
540
SET_GBE_FIELD(DOTCLK, P, val, timing->pll_p);
drivers/video/fbdev/gbefb.c
547
SET_GBE_FIELD(VT_XYMAX, MAXX, val, timing->htotal);
drivers/video/fbdev/gbefb.c
548
SET_GBE_FIELD(VT_XYMAX, MAXY, val, timing->vtotal);
drivers/video/fbdev/gbefb.c
553
SET_GBE_FIELD(VT_VSYNC, VSYNC_ON, val, timing->vsync_start);
drivers/video/fbdev/gbefb.c
554
SET_GBE_FIELD(VT_VSYNC, VSYNC_OFF, val, timing->vsync_end);
drivers/video/fbdev/gbefb.c
557
SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start);
drivers/video/fbdev/gbefb.c
558
SET_GBE_FIELD(VT_HSYNC, HSYNC_OFF, val, timing->hsync_end);
drivers/video/fbdev/gbefb.c
561
SET_GBE_FIELD(VT_VBLANK, VBLANK_ON, val, timing->vblank_start);
drivers/video/fbdev/gbefb.c
562
SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end);
drivers/video/fbdev/gbefb.c
566
timing->hblank_start - 5);
drivers/video/fbdev/gbefb.c
568
timing->hblank_end - 3);
drivers/video/fbdev/gbefb.c
573
SET_GBE_FIELD(VT_VCMAP, VCMAP_ON, val, timing->vblank_start);
drivers/video/fbdev/gbefb.c
574
SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end);
drivers/video/fbdev/gbefb.c
577
SET_GBE_FIELD(VT_HCMAP, HCMAP_ON, val, timing->hblank_start);
drivers/video/fbdev/gbefb.c
578
SET_GBE_FIELD(VT_HCMAP, HCMAP_OFF, val, timing->hblank_end);
drivers/video/fbdev/gbefb.c
582
temp = timing->vblank_start - timing->vblank_end - 1;
drivers/video/fbdev/gbefb.c
587
gbefb_setup_flatpanel(timing);
drivers/video/fbdev/gbefb.c
590
if (timing->hblank_end >= 20)
drivers/video/fbdev/gbefb.c
592
timing->hblank_end - 20);
drivers/video/fbdev/gbefb.c
595
timing->htotal - (20 - timing->hblank_end));
drivers/video/fbdev/gbefb.c
600
if (timing->hblank_end >= GBE_CRS_MAGIC)
drivers/video/fbdev/gbefb.c
602
timing->hblank_end - GBE_CRS_MAGIC);
drivers/video/fbdev/gbefb.c
605
timing->htotal - (GBE_CRS_MAGIC -
drivers/video/fbdev/gbefb.c
606
timing->hblank_end));
drivers/video/fbdev/gbefb.c
611
SET_GBE_FIELD(VC_START_XY, VC_STARTX, val, timing->hblank_end - 4);
drivers/video/fbdev/gbefb.c
615
temp = timing->hblank_end - GBE_PIXEN_MAGIC_ON;
drivers/video/fbdev/gbefb.c
617
temp += timing->htotal; /* allow blank to wrap around */
drivers/video/fbdev/gbefb.c
621
((temp + timing->width -
drivers/video/fbdev/gbefb.c
622
GBE_PIXEN_MAGIC_OFF) % timing->htotal));
drivers/video/fbdev/gbefb.c
626
SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end);
drivers/video/fbdev/gbefb.c
627
SET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val, timing->vblank_start);
drivers/video/fbdev/gbefb.c
650
compute_gbe_timing(&info->var, &par->timing);
drivers/video/fbdev/gbefb.c
654
xpmax = par->timing.width;
drivers/video/fbdev/gbefb.c
655
ypmax = par->timing.height;
drivers/video/fbdev/gbefb.c
661
gbe_set_timing_info(&par->timing);
drivers/video/fbdev/gbefb.c
903
struct gbe_timing_info timing;
drivers/video/fbdev/gbefb.c
923
ret = compute_gbe_timing(var, &timing);
drivers/video/fbdev/gbefb.c
985
var->left_margin = timing.htotal - timing.hsync_end;
drivers/video/fbdev/gbefb.c
986
var->right_margin = timing.hsync_start - timing.width;
drivers/video/fbdev/gbefb.c
987
var->upper_margin = timing.vtotal - timing.vsync_end;
drivers/video/fbdev/gbefb.c
988
var->lower_margin = timing.vsync_start - timing.height;
drivers/video/fbdev/gbefb.c
989
var->hsync_len = timing.hsync_end - timing.hsync_start;
drivers/video/fbdev/gbefb.c
990
var->vsync_len = timing.vsync_end - timing.vsync_start;
drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c
144
struct display_timing timing;
drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c
154
r = of_get_display_timing(node, "panel-timing", &timing);
drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c
160
videomode_from_timing(&timing, &vm);
drivers/video/fbdev/pm2fb.c
232
static u32 to3264(u32 timing, int bpp, int is64)
drivers/video/fbdev/pm2fb.c
236
timing *= 3;
drivers/video/fbdev/pm2fb.c
239
timing >>= 1;
drivers/video/fbdev/pm2fb.c
242
timing >>= 1;
drivers/video/fbdev/pm2fb.c
248
timing >>= 1;
drivers/video/fbdev/pm2fb.c
249
return timing;
drivers/video/fbdev/via/hw.c
1458
struct via_display_timing timing;
drivers/video/fbdev/via/hw.c
1461
timing.hor_addr = cxres;
drivers/video/fbdev/via/hw.c
1462
timing.hor_sync_start = timing.hor_addr + var->right_margin + dx;
drivers/video/fbdev/via/hw.c
1463
timing.hor_sync_end = timing.hor_sync_start + var->hsync_len;
drivers/video/fbdev/via/hw.c
1464
timing.hor_total = timing.hor_sync_end + var->left_margin + dx;
drivers/video/fbdev/via/hw.c
1465
timing.hor_blank_start = timing.hor_addr + dx;
drivers/video/fbdev/via/hw.c
1466
timing.hor_blank_end = timing.hor_total - dx;
drivers/video/fbdev/via/hw.c
1467
timing.ver_addr = cyres;
drivers/video/fbdev/via/hw.c
1468
timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy;
drivers/video/fbdev/via/hw.c
1469
timing.ver_sync_end = timing.ver_sync_start + var->vsync_len;
drivers/video/fbdev/via/hw.c
1470
timing.ver_total = timing.ver_sync_end + var->upper_margin + dy;
drivers/video/fbdev/via/hw.c
1471
timing.ver_blank_start = timing.ver_addr + dy;
drivers/video/fbdev/via/hw.c
1472
timing.ver_blank_end = timing.ver_total - dy;
drivers/video/fbdev/via/hw.c
1473
return timing;
drivers/video/fbdev/via/lcd.c
538
struct via_display_timing timing;
drivers/video/fbdev/via/lcd.c
554
timing = var_to_timing(&panel_var, panel_hres, panel_vres);
drivers/video/fbdev/via/lcd.c
557
timing = var_to_timing(&panel_var, set_hres, set_vres);
drivers/video/fbdev/via/lcd.c
565
via_set_primary_timing(&timing);
drivers/video/fbdev/via/lcd.c
567
via_set_secondary_timing(&timing);
drivers/video/fbdev/via/via_modesetting.c
18
void via_set_primary_timing(const struct via_display_timing *timing)
drivers/video/fbdev/via/via_modesetting.c
22
raw.hor_total = timing->hor_total / 8 - 5;
drivers/video/fbdev/via/via_modesetting.c
23
raw.hor_addr = timing->hor_addr / 8 - 1;
drivers/video/fbdev/via/via_modesetting.c
24
raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
drivers/video/fbdev/via/via_modesetting.c
25
raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
drivers/video/fbdev/via/via_modesetting.c
26
raw.hor_sync_start = timing->hor_sync_start / 8;
drivers/video/fbdev/via/via_modesetting.c
27
raw.hor_sync_end = timing->hor_sync_end / 8;
drivers/video/fbdev/via/via_modesetting.c
28
raw.ver_total = timing->ver_total - 2;
drivers/video/fbdev/via/via_modesetting.c
29
raw.ver_addr = timing->ver_addr - 1;
drivers/video/fbdev/via/via_modesetting.c
30
raw.ver_blank_start = timing->ver_blank_start - 1;
drivers/video/fbdev/via/via_modesetting.c
31
raw.ver_blank_end = timing->ver_blank_end - 1;
drivers/video/fbdev/via/via_modesetting.c
32
raw.ver_sync_start = timing->ver_sync_start - 1;
drivers/video/fbdev/via/via_modesetting.c
33
raw.ver_sync_end = timing->ver_sync_end - 1;
drivers/video/fbdev/via/via_modesetting.c
76
void via_set_secondary_timing(const struct via_display_timing *timing)
drivers/video/fbdev/via/via_modesetting.c
80
raw.hor_total = timing->hor_total - 1;
drivers/video/fbdev/via/via_modesetting.c
81
raw.hor_addr = timing->hor_addr - 1;
drivers/video/fbdev/via/via_modesetting.c
82
raw.hor_blank_start = timing->hor_blank_start - 1;
drivers/video/fbdev/via/via_modesetting.c
83
raw.hor_blank_end = timing->hor_blank_end - 1;
drivers/video/fbdev/via/via_modesetting.c
84
raw.hor_sync_start = timing->hor_sync_start - 1;
drivers/video/fbdev/via/via_modesetting.c
85
raw.hor_sync_end = timing->hor_sync_end - 1;
drivers/video/fbdev/via/via_modesetting.c
86
raw.ver_total = timing->ver_total - 1;
drivers/video/fbdev/via/via_modesetting.c
87
raw.ver_addr = timing->ver_addr - 1;
drivers/video/fbdev/via/via_modesetting.c
88
raw.ver_blank_start = timing->ver_blank_start - 1;
drivers/video/fbdev/via/via_modesetting.c
89
raw.ver_blank_end = timing->ver_blank_end - 1;
drivers/video/fbdev/via/via_modesetting.c
90
raw.ver_sync_start = timing->ver_sync_start - 1;
drivers/video/fbdev/via/via_modesetting.c
91
raw.ver_sync_end = timing->ver_sync_end - 1;
drivers/video/fbdev/via/via_modesetting.h
37
void via_set_primary_timing(const struct via_display_timing *timing);
drivers/video/fbdev/via/via_modesetting.h
38
void via_set_secondary_timing(const struct via_display_timing *timing);
include/drm/bridge/dw_mipi_dsi.h
42
struct dw_mipi_dsi_dphy_timing *timing);
include/drm/bridge/dw_mipi_dsi2.h
52
struct dw_mipi_dsi2_phy_timing *timing);
include/linux/greybus/greybus_protocols.h
1469
__u8 timing;
include/linux/leds-expresswire.h
28
struct expresswire_timing timing;
include/linux/libata.h
1258
const unsigned int *timing, unsigned long deadline,
include/linux/libata.h
1289
const unsigned int *timing,
include/linux/mmc/host.h
53
unsigned char timing; /* timing specification used */
include/linux/mmc/host.h
694
return card->host->ios.timing == MMC_TIMING_SD_HS ||
include/linux/mmc/host.h
695
card->host->ios.timing == MMC_TIMING_MMC_HS;
include/linux/mmc/host.h
701
return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 &&
include/linux/mmc/host.h
702
card->host->ios.timing <= MMC_TIMING_UHS_DDR50;
include/linux/mmc/host.h
707
return host->ios.timing == MMC_TIMING_UHS2_SPEED_A ||
include/linux/mmc/host.h
708
host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD ||
include/linux/mmc/host.h
709
host->ios.timing == MMC_TIMING_UHS2_SPEED_B ||
include/linux/mmc/host.h
710
host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD;
include/linux/mmc/host.h
749
return host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD ||
include/linux/mmc/host.h
750
host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD;
include/pcmcia/cistpl.h
460
cistpl_timing_t timing;
sound/pci/sis7019.c
327
if (!voice->timing)
sound/pci/sis7019.c
387
if (voice->timing) {
sound/pci/sis7019.c
389
voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING |
sound/pci/sis7019.c
391
voice->timing = NULL;
sound/pci/sis7019.c
439
if (needed && !voice->timing) {
sound/pci/sis7019.c
441
voice->timing = __sis_alloc_playback_voice(sis);
sound/pci/sis7019.c
442
if (voice->timing)
sound/pci/sis7019.c
445
if (!voice->timing)
sound/pci/sis7019.c
447
voice->timing->substream = substream;
sound/pci/sis7019.c
448
} else if (!needed && voice->timing) {
sound/pci/sis7019.c
450
voice->timing = NULL;
sound/pci/sis7019.c
592
voice = voice->timing;
sound/pci/sis7019.c
687
struct voice *timing = voice->timing;
sound/pci/sis7019.c
688
void __iomem *play_base = timing->ctrl_base;
sound/pci/sis7019.c
689
void __iomem *wave_base = timing->wave_base;
sound/pci/sis7019.c
740
timing->flags |= VOICE_SYNC_TIMING;
sound/pci/sis7019.c
741
timing->sync_base = voice->ctrl_base;
sound/pci/sis7019.c
742
timing->sync_cso = runtime->period_size;
sound/pci/sis7019.c
743
timing->sync_period_size = runtime->period_size;
sound/pci/sis7019.c
744
timing->sync_buffer_size = runtime->buffer_size;
sound/pci/sis7019.c
745
timing->period_size = period_size;
sound/pci/sis7019.c
746
timing->buffer_size = buffer_size;
sound/pci/sis7019.c
747
timing->sso = sso;
sound/pci/sis7019.c
748
timing->vperiod = vperiod;
sound/pci/sis7019.c
760
control = timing->buffer_size - 1;
sound/pci/sis7019.c
762
sso_eso = timing->buffer_size - 1;
sound/pci/sis7019.c
763
sso_eso |= timing->sso << 16;
sound/pci/sis7019.c
812
if (voice->timing) {
sound/pci/sis7019.c
82
struct voice *timing;
sound/soc/renesas/rcar/core.c
548
int shift, int add, int timing)
sound/soc/renesas/rcar/core.c
554
int func_call = (val == timing);
tools/testing/selftests/bpf/benchs/bench_bpf_nop.c
11
struct bpf_bench_timing timing;
tools/testing/selftests/bpf/benchs/bench_bpf_nop.c
53
BENCH_TIMING_INIT(&ctx.timing, skel, 0);
tools/testing/selftests/bpf/benchs/bench_bpf_nop.c
54
bpf_bench_calibrate(&ctx.timing, nop_run_once, NULL);
tools/testing/selftests/bpf/benchs/bench_bpf_nop.c
69
bpf_bench_timing_measure(&ctx.timing, res);
tools/testing/selftests/bpf/benchs/bench_bpf_nop.c
74
bpf_bench_timing_report(&ctx.timing, "bpf-nop", NULL);
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1013
BENCH_TIMING_INIT(&ctx.timing, skel, 0);
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1014
ctx.timing.machine_readable = args.machine_readable;
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1017
ctx.timing.batch_iters = scenarios[args.scenario].fixed_batch_iters;
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1018
skel->bss->batch_iters = ctx.timing.batch_iters;
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1020
bpf_bench_calibrate(&ctx.timing, xdp_lb_run_once, NULL);
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1057
bpf_bench_timing_measure(&ctx.timing, res);
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
1062
bpf_bench_timing_report(&ctx.timing, scenarios[args.scenario].name,
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
348
struct bpf_bench_timing timing;
tools/testing/selftests/bpf/benchs/bench_xdp_lb.c
810
__u64 n = ctx.timing.batch_iters + 1;
tools/testing/selftests/seccomp/seccomp_benchmark.c
217
native = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples;
tools/testing/selftests/seccomp/seccomp_benchmark.c
227
bitmap1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples;
tools/testing/selftests/seccomp/seccomp_benchmark.c
234
bitmap2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples;
tools/testing/selftests/seccomp/seccomp_benchmark.c
241
filter1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples;
tools/testing/selftests/seccomp/seccomp_benchmark.c
248
filter2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples;
