arch/arm/mach-omap1/clock.c

268

u16 regval;

arch/arm/mach-omap1/clock.c

276

regval = __raw_readw(DSP_CKCTL);

arch/arm/mach-omap1/clock.c

277

regval &= ~(3 << clk->rate_offset);

arch/arm/mach-omap1/clock.c

278

regval |= dsor_exp << clk->rate_offset;

arch/arm/mach-omap1/clock.c

279

__raw_writew(regval, DSP_CKCTL);

arch/arm/mach-omap1/clock.c

301

u16 regval;

arch/arm/mach-omap1/clock.c

312

regval = omap_readw(ARM_CKCTL);

arch/arm/mach-omap1/clock.c

313

regval &= ~(3 << clk->rate_offset);

arch/arm/mach-omap1/clock.c

314

regval |= dsor_exp << clk->rate_offset;

arch/arm/mach-omap1/clock.c

315

regval = verify_ckctl_value(regval);

arch/arm/mach-omap1/clock.c

316

omap_writew(regval, ARM_CKCTL);

arch/arm64/include/asm/mpam.h

61

u64 regval = __mpam_regval(partid_d, partid_i, pmg_d, pmg_i);

arch/arm64/include/asm/mpam.h

63

WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval);

arch/arm64/include/asm/mpam.h

70

u64 regval = mpam_get_regval(tsk);

arch/arm64/include/asm/mpam.h

75

if (regval == READ_ONCE(arm64_mpam_global_default))

arch/arm64/include/asm/mpam.h

76

regval = READ_ONCE(per_cpu(arm64_mpam_default, cpu));

arch/arm64/include/asm/mpam.h

79

if (oldregval == regval)

arch/arm64/include/asm/mpam.h

82

write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1);

arch/arm64/include/asm/mpam.h

84

write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1);

arch/arm64/include/asm/mpam.h

88

write_sysreg_s(regval, SYS_MPAM0_EL1);

arch/arm64/include/asm/mpam.h

90

WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval);

arch/arm64/kernel/cpufeature.c

2512

u64 regval = 0;

arch/arm64/kernel/cpufeature.c

2515

regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu));

arch/arm64/kernel/cpufeature.c

2517

write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1);

arch/arm64/kernel/cpufeature.c

2519

write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1);

arch/arm64/kernel/cpufeature.c

2523

write_sysreg_s(regval, SYS_MPAM0_EL1);

arch/arm64/kernel/mpam.c

20

u64 regval;

arch/arm64/kernel/mpam.c

29

regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu));

arch/arm64/kernel/mpam.c

30

write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1);

arch/arm64/kernel/mpam.c

32

write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D),

arch/arm64/kernel/mpam.c

37

write_sysreg_s(regval, SYS_MPAM0_EL1);

arch/arm64/kvm/config.c

1400

u64 regval = kvm->arch.id_regs[map->regidx];

arch/arm64/kvm/config.c

1401

u64 regfld = (regval >> map->shift) & GENMASK(map->width - 1, 0);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

305

p->regval = 0;

arch/arm64/kvm/hyp/nvhe/sys_regs.c

344

p->regval = read_id_reg(vcpu, r);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

354

p->regval = ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE;

arch/arm64/kvm/hyp/nvhe/sys_regs.c

582

params.regval = vcpu_get_reg(vcpu, Rt);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

601

vcpu_set_reg(vcpu, Rt, params.regval);

arch/arm64/kvm/sys_regs.c

1116

val |= p->regval & ARMV8_PMU_PMCR_MASK;

arch/arm64/kvm/sys_regs.c

1124

p->regval = val;

arch/arm64/kvm/sys_regs.c

1137

__vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval);

arch/arm64/kvm/sys_regs.c

1140

p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)

arch/arm64/kvm/sys_regs.c

1162

p->regval = pmceid;

arch/arm64/kvm/sys_regs.c

1258

kvm_pmu_set_counter_value(vcpu, idx, p->regval);

arch/arm64/kvm/sys_regs.c

1260

p->regval = kvm_pmu_get_counter_value(vcpu, idx);

arch/arm64/kvm/sys_regs.c

1293

kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);

arch/arm64/kvm/sys_regs.c

1296

p->regval = __vcpu_sys_reg(vcpu, reg);

arch/arm64/kvm/sys_regs.c

1330

val = p->regval & mask;

arch/arm64/kvm/sys_regs.c

1340

p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);

arch/arm64/kvm/sys_regs.c

1355

u64 val = p->regval & mask;

arch/arm64/kvm/sys_regs.c

1364

p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);

arch/arm64/kvm/sys_regs.c

1381

__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask));

arch/arm64/kvm/sys_regs.c

1384

__vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask));

arch/arm64/kvm/sys_regs.c

1386

p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);

arch/arm64/kvm/sys_regs.c

1404

kvm_pmu_software_increment(vcpu, p->regval & mask);

arch/arm64/kvm/sys_regs.c

1416

(p->regval & ARMV8_PMU_USERENR_MASK));

arch/arm64/kvm/sys_regs.c

1418

p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)

arch/arm64/kvm/sys_regs.c

1687

kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);

arch/arm64/kvm/sys_regs.c

1689

p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);

arch/arm64/kvm/sys_regs.c

2013

p->regval = read_id_reg(vcpu, r);

arch/arm64/kvm/sys_regs.c

2491

p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0);

arch/arm64/kvm/sys_regs.c

2501

p->regval = __vcpu_sys_reg(vcpu, r->reg);

arch/arm64/kvm/sys_regs.c

2581

vcpu_write_sys_reg(vcpu, p->regval, reg);

arch/arm64/kvm/sys_regs.c

2583

p->regval = vcpu_read_sys_reg(vcpu, reg);

arch/arm64/kvm/sys_regs.c

2598

p->regval = get_ccsidr(vcpu, csselr);

arch/arm64/kvm/sys_regs.c

2764

__vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval);

arch/arm64/kvm/sys_regs.c

2766

p->regval = __vcpu_sys_reg(vcpu, SP_EL1);

arch/arm64/kvm/sys_regs.c

2776

vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);

arch/arm64/kvm/sys_regs.c

2778

p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);

arch/arm64/kvm/sys_regs.c

2788

__vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval);

arch/arm64/kvm/sys_regs.c

2790

p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);

arch/arm64/kvm/sys_regs.c

2800

__vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval);

arch/arm64/kvm/sys_regs.c

2802

p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1);

arch/arm64/kvm/sys_regs.c

2868

p->regval = __vcpu_sys_reg(vcpu, ZCR_EL2);

arch/arm64/kvm/sys_regs.c

2870

__vcpu_assign_sys_reg(vcpu, ZCR_EL2, p->regval);

arch/arm64/kvm/sys_regs.c

2882

p->regval = kvm_get_guest_vtr_el2();

arch/arm64/kvm/sys_regs.c

2894

p->regval = vgic_v3_get_misr(vcpu);

arch/arm64/kvm/sys_regs.c

2906

p->regval = vgic_v3_get_eisr(vcpu);

arch/arm64/kvm/sys_regs.c

2918

p->regval = vgic_v3_get_elrsr(vcpu);

arch/arm64/kvm/sys_regs.c

3005

p->regval = old;

arch/arm64/kvm/sys_regs.c

3009

val = p->regval;

arch/arm64/kvm/sys_regs.c

3098

p->regval = read_sysreg(revidr_el1);

arch/arm64/kvm/sys_regs.c

3101

p->regval = read_sysreg(aidr_el1);

arch/arm64/kvm/sys_regs.c

3887

if (__kvm_at_s1e01(vcpu, op, p->regval))

arch/arm64/kvm/sys_regs.c

3905

if (__kvm_at_s1e2(vcpu, op, p->regval))

arch/arm64/kvm/sys_regs.c

3916

if (__kvm_at_s12(vcpu, op, p->regval))

arch/arm64/kvm/sys_regs.c

4069

base = decode_range_tlbi(p->regval, &range, NULL);

arch/arm64/kvm/sys_regs.c

4121

.addr = p->regval,

arch/arm64/kvm/sys_regs.c

4143

kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval);

arch/arm64/kvm/sys_regs.c

4178

kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval);

arch/arm64/kvm/sys_regs.c

4186

.addr = p->regval,

arch/arm64/kvm/sys_regs.c

4391

p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) |

arch/arm64/kvm/sys_regs.c

4865

params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;

arch/arm64/kvm/sys_regs.c

4866

params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;

arch/arm64/kvm/sys_regs.c

4877

vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));

arch/arm64/kvm/sys_regs.c

4878

vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));

arch/arm64/kvm/sys_regs.c

492

vcpu_write_sys_reg(vcpu, p->regval, r->reg);

arch/arm64/kvm/sys_regs.c

494

p->regval = vcpu_read_sys_reg(vcpu, r->reg);

arch/arm64/kvm/sys_regs.c

4956

vcpu_set_reg(vcpu, Rt, params.regval);

arch/arm64/kvm/sys_regs.c

4997

params->regval = 0;

arch/arm64/kvm/sys_regs.c

5001

vcpu_set_reg(vcpu, Rt, params->regval);

arch/arm64/kvm/sys_regs.c

5019

params->regval = vcpu_get_reg(vcpu, Rt);

arch/arm64/kvm/sys_regs.c

5023

vcpu_set_reg(vcpu, Rt, params->regval);

arch/arm64/kvm/sys_regs.c

5309

params.regval = vcpu_get_reg(vcpu, Rt);

arch/arm64/kvm/sys_regs.c

5322

vcpu_set_reg(vcpu, Rt, params.regval);

arch/arm64/kvm/sys_regs.c

574

val |= (p->regval & (mask >> shift)) << shift;

arch/arm64/kvm/sys_regs.c

591

p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;

arch/arm64/kvm/sys_regs.c

645

vgic_v3_dispatch_sgi(vcpu, p->regval, g1);

arch/arm64/kvm/sys_regs.c

661

p->regval = KVM_ICC_SRE_EL2;

arch/arm64/kvm/sys_regs.c

663

p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;

arch/arm64/kvm/sys_regs.c

679

vgic_v3_deactivate(vcpu, p->regval);

arch/arm64/kvm/sys_regs.c

700

p->regval = FIELD_PREP(ICC_IDR0_EL1_PRI_BITS, vcpu->arch.vgic_cpu.num_pri_bits - 1) |

arch/arm64/kvm/sys_regs.c

716

p->regval = FIELD_PREP(ICC_IAFFIDR_EL1_IAFFID, vcpu->vcpu_id);

arch/arm64/kvm/sys_regs.c

727

unsigned long reg = p->regval;

arch/arm64/kvm/sys_regs.c

804

kvm_debug_handle_oslar(vcpu, p->regval);

arch/arm64/kvm/sys_regs.c

815

p->regval = __vcpu_sys_reg(vcpu, r->reg);

arch/arm64/kvm/sys_regs.c

840

p->regval = read_sysreg(dbgauthstatus_el1);

arch/arm64/kvm/sys_regs.c

872

val |= (p->regval & (mask >> shift)) << shift;

arch/arm64/kvm/sys_regs.c

884

p->regval = (*dbg_reg & mask) >> shift;

arch/arm64/kvm/sys_regs.h

140

p->regval = 0;

arch/arm64/kvm/sys_regs.h

26

u64 regval;

arch/mips/loongson2ef/lemote-2f/clock.c

37

int regval;

arch/mips/loongson2ef/lemote-2f/clock.c

45

regval = readl(LOONGSON_CHIPCFG);

arch/mips/loongson2ef/lemote-2f/clock.c

46

regval = (regval & ~0x7) | (pos->driver_data - 1);

arch/mips/loongson2ef/lemote-2f/clock.c

47

writel(regval, LOONGSON_CHIPCFG);

arch/sparc/include/asm/pgtsrmmu.h

112

void srmmu_set_mmureg(unsigned long regval);

arch/sparc/include/asm/turbosparc.h

106

static inline void turbosparc_set_ccreg(unsigned long regval)

arch/sparc/include/asm/turbosparc.h

110

: "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)

arch/sparc/include/asm/turbosparc.h

116

unsigned long regval;

arch/sparc/include/asm/turbosparc.h

119

: "=r" (regval)

arch/sparc/include/asm/turbosparc.h

121

return regval;

arch/sparc/include/asm/viking.h

147

static inline void viking_set_bpreg(unsigned long regval)

arch/sparc/include/asm/viking.h

151

: "r" (regval), "i" (ASI_M_ACTION)

arch/sparc/include/asm/viking.h

157

unsigned long regval;

arch/sparc/include/asm/viking.h

160

: "=r" (regval)

arch/sparc/include/asm/viking.h

162

return regval;

arch/sparc/kernel/auxio_32.c

87

unsigned char regval;

arch/sparc/kernel/auxio_32.c

94

regval = sbus_readb(auxio_register);

arch/sparc/kernel/auxio_32.c

95

sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M,

arch/sparc/kernel/auxio_64.c

36

u8 regval, newval;

arch/sparc/kernel/auxio_64.c

40

regval = (ebus ?

arch/sparc/kernel/auxio_64.c

43

newval = regval | bits_on;

drivers/ata/sata_nv.c

1883

u8 regval;

drivers/ata/sata_nv.c

1886

pci_read_config_byte(pdev, 0x7f, &regval);

drivers/ata/sata_nv.c

1887

regval &= ~(1 << 7);

drivers/ata/sata_nv.c

1888

pci_write_config_byte(pdev, 0x7f, regval);

drivers/ata/sata_nv.c

2397

u8 regval;

drivers/ata/sata_nv.c

2399

pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);

drivers/ata/sata_nv.c

2400

regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;

drivers/ata/sata_nv.c

2401

pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);

drivers/ata/sata_nv.c

2434

u8 regval;

drivers/ata/sata_nv.c

2436

pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);

drivers/ata/sata_nv.c

2437

regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;

drivers/ata/sata_nv.c

2438

pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);

drivers/ata/sata_nv.c

2474

u8 regval;

drivers/ata/sata_nv.c

2477

pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);

drivers/ata/sata_nv.c

2478

regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;

drivers/ata/sata_nv.c

2479

pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);

drivers/bus/mhi/ep/mmio.c

185

u32 regval;

drivers/bus/mhi/ep/mmio.c

187

regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_HIGHER);

drivers/bus/mhi/ep/mmio.c

188

mhi_cntrl->ch_ctx_host_pa = regval;

drivers/bus/mhi/ep/mmio.c

191

regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_LOWER);

drivers/bus/mhi/ep/mmio.c

192

mhi_cntrl->ch_ctx_host_pa |= regval;

drivers/bus/mhi/ep/mmio.c

197

u32 regval;

drivers/bus/mhi/ep/mmio.c

199

regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_HIGHER);

drivers/bus/mhi/ep/mmio.c

200

mhi_cntrl->ev_ctx_host_pa = regval;

drivers/bus/mhi/ep/mmio.c

203

regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_LOWER);

drivers/bus/mhi/ep/mmio.c

204

mhi_cntrl->ev_ctx_host_pa |= regval;

drivers/bus/mhi/ep/mmio.c

209

u32 regval;

drivers/bus/mhi/ep/mmio.c

211

regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_HIGHER);

drivers/bus/mhi/ep/mmio.c

212

mhi_cntrl->cmd_ctx_host_pa = regval;

drivers/bus/mhi/ep/mmio.c

215

regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_LOWER);

drivers/bus/mhi/ep/mmio.c

216

mhi_cntrl->cmd_ctx_host_pa |= regval;

drivers/bus/mhi/ep/mmio.c

223

u32 regval;

drivers/bus/mhi/ep/mmio.c

225

regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h);

drivers/bus/mhi/ep/mmio.c

226

db_offset = regval;

drivers/bus/mhi/ep/mmio.c

229

regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l);

drivers/bus/mhi/ep/mmio.c

230

db_offset |= regval;

drivers/bus/mhi/ep/mmio.c

25

u32 regval;

drivers/bus/mhi/ep/mmio.c

254

u32 regval;

drivers/bus/mhi/ep/mmio.c

259

regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);

drivers/bus/mhi/ep/mmio.c

260

mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);

drivers/bus/mhi/ep/mmio.c

261

mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);

drivers/bus/mhi/ep/mmio.c

268

u32 regval;

drivers/bus/mhi/ep/mmio.c

27

regval = mhi_ep_mmio_read(mhi_cntrl, offset);

drivers/bus/mhi/ep/mmio.c

270

regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);

drivers/bus/mhi/ep/mmio.c

271

mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);

drivers/bus/mhi/ep/mmio.c

272

mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);

drivers/bus/mhi/ep/mmio.c

28

regval &= ~mask;

drivers/bus/mhi/ep/mmio.c

29

regval |= (val << __ffs(mask)) & mask;

drivers/bus/mhi/ep/mmio.c

30

mhi_ep_mmio_write(mhi_cntrl, offset, regval);

drivers/bus/mhi/ep/mmio.c

35

u32 regval;

drivers/bus/mhi/ep/mmio.c

37

regval = mhi_ep_mmio_read(dev, offset);

drivers/bus/mhi/ep/mmio.c

38

regval &= mask;

drivers/bus/mhi/ep/mmio.c

39

regval >>= __ffs(mask);

drivers/bus/mhi/ep/mmio.c

41

return regval;

drivers/bus/mhi/ep/mmio.c

47

u32 regval;

drivers/bus/mhi/ep/mmio.c

49

regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICTRL);

drivers/bus/mhi/ep/mmio.c

50

*state = FIELD_GET(MHICTRL_MHISTATE_MASK, regval);

drivers/bus/mhi/ep/mmio.c

51

*mhi_reset = !!FIELD_GET(MHICTRL_RESET_MASK, regval);

drivers/clk/clk-apple-nco.c

144

static unsigned int applnco_div_translate_inv(struct applnco_tables *tbl, u32 regval)

drivers/clk/clk-apple-nco.c

148

coarse = tbl->inv[FIELD_GET(DIV_COARSE, regval)] + COARSE_DIV_OFFSET;

drivers/clk/clk-apple-nco.c

149

fine = FIELD_GET(DIV_FINE, regval);

drivers/clk/clk-bm1880.c

473

static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate)

drivers/clk/clk-bm1880.c

479

fbdiv = (regval >> 16) & 0xfff;

drivers/clk/clk-bm1880.c

480

refdiv = regval & 0x1f;

drivers/clk/clk-bm1880.c

481

postdiv1 = (regval >> 8) & 0x7;

drivers/clk/clk-bm1880.c

482

postdiv2 = (regval >> 12) & 0x7;

drivers/clk/clk-bm1880.c

496

u32 regval;

drivers/clk/clk-bm1880.c

498

regval = readl(pll_hw->base + pll_hw->pll.reg);

drivers/clk/clk-bm1880.c

499

rate = bm1880_pll_rate_calc(regval, parent_rate);

drivers/clk/hisilicon/clk-hisi-phase.c

31

u32 regval)

drivers/clk/hisilicon/clk-hisi-phase.c

36

if (phase->phase_regvals[i] == regval)

drivers/clk/hisilicon/clk-hisi-phase.c

45

u32 regval;

drivers/clk/hisilicon/clk-hisi-phase.c

47

regval = readl(phase->reg);

drivers/clk/hisilicon/clk-hisi-phase.c

48

regval = (regval & phase->mask) >> phase->shift;

drivers/clk/hisilicon/clk-hisi-phase.c

50

return hisi_phase_regval_to_degrees(phase, regval);

drivers/clk/hisilicon/clk-hisi-phase.c

69

int regval;

drivers/clk/hisilicon/clk-hisi-phase.c

72

regval = hisi_phase_degrees_to_regval(phase, degrees);

drivers/clk/hisilicon/clk-hisi-phase.c

73

if (regval < 0)

drivers/clk/hisilicon/clk-hisi-phase.c

74

return regval;

drivers/clk/hisilicon/clk-hisi-phase.c

80

val |= regval << phase->shift;

drivers/clk/mediatek/clk-fhctl.c

163

unsigned int regval;

drivers/clk/mediatek/clk-fhctl.c

165

regval = readl(pll->pd_addr) >> pll->data->pd_shift;

drivers/clk/mediatek/clk-fhctl.c

166

regval &= POSTDIV_MASK;

drivers/clk/mediatek/clk-fhctl.c

168

return BIT(regval);

drivers/clk/mediatek/clk-fhctl.c

173

unsigned int regval;

drivers/clk/mediatek/clk-fhctl.c

175

regval = readl(pll->pd_addr);

drivers/clk/mediatek/clk-fhctl.c

176

regval &= ~(POSTDIV_MASK << pll->data->pd_shift);

drivers/clk/mediatek/clk-fhctl.c

177

regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;

drivers/clk/mediatek/clk-fhctl.c

178

writel(regval, pll->pd_addr);

drivers/clk/qcom/clk-hfpll.c

36

u32 regval = hd->user_val;

drivers/clk/qcom/clk-hfpll.c

43

regval |= hd->user_vco_mask;

drivers/clk/qcom/clk-hfpll.c

44

regmap_write(regmap, hd->user_reg, regval);

drivers/clk/qcom/clk-krait.c

26

u32 regval;

drivers/clk/qcom/clk-krait.c

30

regval = krait_get_l2_indirect_reg(mux->offset);

drivers/clk/qcom/clk-krait.c

34

regval |= SECCLKAGD;

drivers/clk/qcom/clk-krait.c

35

krait_set_l2_indirect_reg(mux->offset, regval);

drivers/clk/qcom/clk-krait.c

38

regval &= ~(mux->mask << mux->shift);

drivers/clk/qcom/clk-krait.c

39

regval |= (sel & mux->mask) << mux->shift;

drivers/clk/qcom/clk-krait.c

41

regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));

drivers/clk/qcom/clk-krait.c

42

regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);

drivers/clk/qcom/clk-krait.c

44

krait_set_l2_indirect_reg(mux->offset, regval);

drivers/clk/qcom/clk-krait.c

48

regval &= ~SECCLKAGD;

drivers/clk/qcom/clk-krait.c

49

krait_set_l2_indirect_reg(mux->offset, regval);

drivers/clk/sophgo/clk-cv18xx-common.c

59

u32 regval;

drivers/clk/sophgo/clk-cv18xx-common.c

64

WARN_ON(readl_relaxed_poll_timeout(addr, regval, regval & lock,

drivers/clk/sophgo/clk-cv18xx-ip.c

850

u32 regval;

drivers/clk/sophgo/clk-cv18xx-ip.c

855

regval = readl(aclk->common.base + aclk->m.reg);

drivers/clk/sophgo/clk-cv18xx-ip.c

856

factor *= cv1800_clk_regfield_get(regval, &aclk->m);

drivers/clk/sophgo/clk-cv18xx-ip.c

858

regval = readl(aclk->common.base + aclk->n.reg);

drivers/clk/sophgo/clk-cv18xx-ip.c

859

rate *= cv1800_clk_regfield_get(regval, &aclk->n);

drivers/clk/sophgo/clk-cv18xx-pll.c

133

u32 regval, detected = 0;

drivers/clk/sophgo/clk-cv18xx-pll.c

144

regval = readl(pll->common.base + pll->pll_reg);

drivers/clk/sophgo/clk-cv18xx-pll.c

145

regval = PLL_COPY_REG(regval, detected);

drivers/clk/sophgo/clk-cv18xx-pll.c

147

writel(regval, pll->common.base + pll->pll_reg);

drivers/clk/sophgo/clk-cv18xx-pll.c

355

u32 regval;

drivers/clk/sophgo/clk-cv18xx-pll.c

373

regval = readl(pll->common.base + pll->pll_reg);

drivers/clk/sophgo/clk-cv18xx-pll.c

374

regval = PLL_COPY_REG(regval, detected);

drivers/clk/sophgo/clk-cv18xx-pll.c

376

writel(regval, pll->common.base + pll->pll_reg);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

240

u32 value, regh, edged, p5en, p5fedge, regval, regval1;

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

261

regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

262

writel(regval, div_addr + 4);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

446

u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value;

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

501

regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

502

writel(regval, divider->base + WZRD_CLK_CFG_REG(1,

drivers/comedi/drivers/ni_routes.c

416

s8 regval;

drivers/comedi/drivers/ni_routes.c

426

regval = RVi(tables->route_values, src, dest);

drivers/comedi/drivers/ni_routes.c

427

if (!regval)

drivers/comedi/drivers/ni_routes.c

430

return UNMARK(regval);

drivers/comedi/drivers/ni_routes.c

470

s8 regval;

drivers/comedi/drivers/ni_routes.c

484

regval = RVi(rv, B(src), B(dest));

drivers/comedi/drivers/ni_routes.c

490

if (!regval && channel_is_rtsi(dest)) {

drivers/comedi/drivers/ni_routes.c

491

regval = RVi(rv, B(src), B(NI_RGOUT0));

drivers/comedi/drivers/ni_routes.c

492

if (!regval && (RVi(rv, B(src), B(NI_RTSI_BRD(0))) ||

drivers/comedi/drivers/ni_routes.c

496

regval = BIT(6);

drivers/comedi/drivers/ni_routes.c

499

if (!regval)

drivers/comedi/drivers/ni_routes.c

502

return UNMARK(regval);

drivers/counter/ti-ecap-capture.c

102

unsigned int regval;

drivers/counter/ti-ecap-capture.c

105

regmap_read(ecap_dev->regmap, ECAP_ECCTL_REG, &regval);

drivers/counter/ti-ecap-capture.c

108

return regval;

drivers/counter/ti-ecap-capture.c

151

unsigned int regval;

drivers/counter/ti-ecap-capture.c

154

regmap_read(ecap_dev->regmap, reg, &regval);

drivers/counter/ti-ecap-capture.c

157

return regval;

drivers/crypto/ccp/ccp-debugfs.c

196

unsigned int regval;

drivers/crypto/ccp/ccp-debugfs.c

224

regval = ioread32(cmd_q->reg_int_enable);

drivers/crypto/ccp/ccp-debugfs.c

226

if (regval & INT_EMPTY_QUEUE)

drivers/crypto/ccp/ccp-debugfs.c

228

if (regval & INT_QUEUE_STOPPED)

drivers/crypto/ccp/ccp-debugfs.c

230

if (regval & INT_ERROR)

drivers/crypto/ccp/ccp-debugfs.c

232

if (regval & INT_COMPLETION)

drivers/crypto/ccp/ccp-debugfs.c

47

unsigned int regval;

drivers/crypto/ccp/ccp-debugfs.c

63

regval = ioread32(ccp->io_regs + CMD5_PSP_CCP_VERSION);

drivers/crypto/ccp/ccp-debugfs.c

64

oboff += OSCNPRINTF(" Version: %d\n", regval & RI_VERSION_NUM);

drivers/crypto/ccp/ccp-debugfs.c

66

if (regval & RI_AES_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

68

if (regval & RI_3DES_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

70

if (regval & RI_SHA_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

72

if (regval & RI_RSA_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

74

if (regval & RI_ECC_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

76

if (regval & RI_ZDE_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

78

if (regval & RI_ZCE_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

80

if (regval & RI_TRNG_PRESENT)

drivers/crypto/ccp/ccp-debugfs.c

84

(regval & RI_NUM_VQM) >> RI_NVQM_SHIFT);

drivers/crypto/ccp/ccp-debugfs.c

86

(regval & RI_LSB_ENTRIES) >> RI_NLSB_SHIFT);

drivers/crypto/hisilicon/sec/sec_drv.c

255

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

257

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

259

regval |= SEC_Q_ARUSER_CFG_PKG;

drivers/crypto/hisilicon/sec/sec_drv.c

261

regval &= ~SEC_Q_ARUSER_CFG_PKG;

drivers/crypto/hisilicon/sec/sec_drv.c

262

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

270

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

272

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

273

regval |= SEC_Q_AWUSER_CFG_PKG;

drivers/crypto/hisilicon/sec/sec_drv.c

274

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

361

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

363

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

364

regval &= ~(SEC_CTRL2_ENDIAN_BD | SEC_CTRL2_ENDIAN_BD_TYPE);

drivers/crypto/hisilicon/sec/sec_drv.c

365

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

388

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

390

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

391

regval &= ~SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_M;

drivers/crypto/hisilicon/sec/sec_drv.c

392

regval |= (cfg << SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_S) &

drivers/crypto/hisilicon/sec/sec_drv.c

394

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

400

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

402

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

403

regval &= ~SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_M;

drivers/crypto/hisilicon/sec/sec_drv.c

404

regval |= (cfg << SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_S) &

drivers/crypto/hisilicon/sec/sec_drv.c

406

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

412

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

414

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

416

regval |= SEC_CTRL2_CLK_GATE_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

418

regval &= ~SEC_CTRL2_CLK_GATE_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

419

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

425

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

427

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

429

regval |= SEC_COMMON_CNT_CLR_CE_CLEAR;

drivers/crypto/hisilicon/sec/sec_drv.c

431

regval &= ~SEC_COMMON_CNT_CLR_CE_CLEAR;

drivers/crypto/hisilicon/sec/sec_drv.c

432

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

438

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

440

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

442

regval |= SEC_COMMON_CNT_CLR_CE_SNAP_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

444

regval &= ~SEC_COMMON_CNT_CLR_CE_SNAP_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

445

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

474

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

476

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

478

regval &= ~SEC_DEBUG_BD_CFG_WB_NORMAL;

drivers/crypto/hisilicon/sec/sec_drv.c

481

regval &= ~SEC_DEBUG_BD_CFG_WB_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

483

regval |= SEC_DEBUG_BD_CFG_WB_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

485

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

492

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

494

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

496

regval |= SEC_SAA_CTRL_GET_QM_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

498

regval &= ~SEC_SAA_CTRL_GET_QM_EN;

drivers/crypto/hisilicon/sec/sec_drv.c

499

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

522

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

524

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

526

regval |= SEC_Q_ARUSER_CFG_FA;

drivers/crypto/hisilicon/sec/sec_drv.c

527

regval &= ~SEC_Q_ARUSER_CFG_FNA;

drivers/crypto/hisilicon/sec/sec_drv.c

529

regval &= ~SEC_Q_ARUSER_CFG_FA;

drivers/crypto/hisilicon/sec/sec_drv.c

530

regval |= SEC_Q_ARUSER_CFG_FNA;

drivers/crypto/hisilicon/sec/sec_drv.c

533

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

539

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

541

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

543

regval |= SEC_Q_AWUSER_CFG_FA;

drivers/crypto/hisilicon/sec/sec_drv.c

544

regval &= ~SEC_Q_AWUSER_CFG_FNA;

drivers/crypto/hisilicon/sec/sec_drv.c

546

regval &= ~SEC_Q_AWUSER_CFG_FA;

drivers/crypto/hisilicon/sec/sec_drv.c

547

regval |= SEC_Q_AWUSER_CFG_FNA;

drivers/crypto/hisilicon/sec/sec_drv.c

550

writel_relaxed(regval, addr);

drivers/crypto/hisilicon/sec/sec_drv.c

556

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

558

regval = readl_relaxed(base + SEC_Q_CFG_REG);

drivers/crypto/hisilicon/sec/sec_drv.c

560

regval |= SEC_Q_CFG_REORDER;

drivers/crypto/hisilicon/sec/sec_drv.c

562

regval &= ~SEC_Q_CFG_REORDER;

drivers/crypto/hisilicon/sec/sec_drv.c

563

writel_relaxed(regval, base + SEC_Q_CFG_REG);

drivers/crypto/hisilicon/sec/sec_drv.c

569

u32 regval;

drivers/crypto/hisilicon/sec/sec_drv.c

571

regval = readl_relaxed(addr);

drivers/crypto/hisilicon/sec/sec_drv.c

572

regval &= ~SEC_Q_DEPTH_CFG_DEPTH_M;

drivers/crypto/hisilicon/sec/sec_drv.c

573

regval |= (depth << SEC_Q_DEPTH_CFG_DEPTH_S) & SEC_Q_DEPTH_CFG_DEPTH_M;

drivers/crypto/hisilicon/sec/sec_drv.c

575

writel_relaxed(regval, addr);

drivers/dma/amd/ptdma/ptdma-debugfs.c

28

unsigned int regval;

drivers/dma/amd/ptdma/ptdma-debugfs.c

41

regval = ioread32(pt->io_regs + CMD_PT_VERSION);

drivers/dma/amd/ptdma/ptdma-debugfs.c

43

seq_printf(s, " Version: %d\n", regval & RI_VERSION_NUM);

drivers/dma/amd/ptdma/ptdma-debugfs.c

46

seq_printf(s, " Queues: %d\n", (regval & RI_NUM_VQM) >> RI_NVQM_SHIFT);

drivers/dma/amd/ptdma/ptdma-debugfs.c

68

unsigned int regval;

drivers/dma/amd/ptdma/ptdma-debugfs.c

77

regval = readl(cmd_q->reg_control + 0x4);

drivers/dma/amd/ptdma/ptdma-debugfs.c

78

seq_printf(s, " Enabled Interrupts:: status 0x%x\n", regval);

drivers/dma/amd/ptdma/ptdma-debugfs.c

80

regval = ioread32(cmd_q->reg_control + 0x000C);

drivers/dma/amd/ptdma/ptdma-debugfs.c

83

if (regval & INT_EMPTY_QUEUE)

drivers/dma/amd/ptdma/ptdma-debugfs.c

85

if (regval & INT_QUEUE_STOPPED)

drivers/dma/amd/ptdma/ptdma-debugfs.c

87

if (regval & INT_ERROR)

drivers/dma/amd/ptdma/ptdma-debugfs.c

89

if (regval & INT_COMPLETION)

drivers/dma/owl-dma.c

244

u32 regval;

drivers/dma/owl-dma.c

246

regval = readl(pchan->base + reg);

drivers/dma/owl-dma.c

249

regval |= val;

drivers/dma/owl-dma.c

251

regval &= ~val;

drivers/dma/owl-dma.c

253

writel(regval, pchan->base + reg);

drivers/dma/owl-dma.c

268

u32 regval;

drivers/dma/owl-dma.c

270

regval = readl(od->base + reg);

drivers/dma/owl-dma.c

273

regval |= val;

drivers/dma/owl-dma.c

275

regval &= ~val;

drivers/dma/owl-dma.c

277

writel(regval, od->base + reg);

drivers/edac/synopsys_edac.c

1044

regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;

drivers/edac/synopsys_edac.c

1045

regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;

drivers/edac/synopsys_edac.c

1046

writel(regval, priv->baseaddr + ECC_POISON0_OFST);

drivers/edac/synopsys_edac.c

1048

regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;

drivers/edac/synopsys_edac.c

1049

regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;

drivers/edac/synopsys_edac.c

1050

regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;

drivers/edac/synopsys_edac.c

1051

writel(regval, priv->baseaddr + ECC_POISON1_OFST);

drivers/edac/synopsys_edac.c

370

u32 regval, clearval = 0;

drivers/edac/synopsys_edac.c

376

regval = readl(base + STAT_OFST);

drivers/edac/synopsys_edac.c

377

if (!regval)

drivers/edac/synopsys_edac.c

380

p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;

drivers/edac/synopsys_edac.c

381

p->ue_cnt = regval & STAT_UECNT_MASK;

drivers/edac/synopsys_edac.c

383

regval = readl(base + CE_LOG_OFST);

drivers/edac/synopsys_edac.c

384

if (!(p->ce_cnt && (regval & LOG_VALID)))

drivers/edac/synopsys_edac.c

387

p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;

drivers/edac/synopsys_edac.c

388

regval = readl(base + CE_ADDR_OFST);

drivers/edac/synopsys_edac.c

389

p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;

drivers/edac/synopsys_edac.c

390

p->ceinfo.col = regval & ADDR_COL_MASK;

drivers/edac/synopsys_edac.c

391

p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;

drivers/edac/synopsys_edac.c

398

regval = readl(base + UE_LOG_OFST);

drivers/edac/synopsys_edac.c

399

if (!(p->ue_cnt && (regval & LOG_VALID)))

drivers/edac/synopsys_edac.c

402

regval = readl(base + UE_ADDR_OFST);

drivers/edac/synopsys_edac.c

403

p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;

drivers/edac/synopsys_edac.c

404

p->ueinfo.col = regval & ADDR_COL_MASK;

drivers/edac/synopsys_edac.c

405

p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;

drivers/edac/synopsys_edac.c

444

u32 regval, clearval;

drivers/edac/synopsys_edac.c

451

regval = readl(base + ECC_ERRCNT_OFST);

drivers/edac/synopsys_edac.c

452

p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;

drivers/edac/synopsys_edac.c

453

p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;

drivers/edac/synopsys_edac.c

457

regval = readl(base + ECC_STAT_OFST);

drivers/edac/synopsys_edac.c

458

if (!regval)

drivers/edac/synopsys_edac.c

461

p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);

drivers/edac/synopsys_edac.c

463

regval = readl(base + ECC_CEADDR0_OFST);

drivers/edac/synopsys_edac.c

464

p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);

drivers/edac/synopsys_edac.c

465

regval = readl(base + ECC_CEADDR1_OFST);

drivers/edac/synopsys_edac.c

466

p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>

drivers/edac/synopsys_edac.c

468

p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>

drivers/edac/synopsys_edac.c

470

p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);

drivers/edac/synopsys_edac.c

479

regval = readl(base + ECC_UEADDR0_OFST);

drivers/edac/synopsys_edac.c

480

p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);

drivers/edac/synopsys_edac.c

481

regval = readl(base + ECC_UEADDR1_OFST);

drivers/edac/synopsys_edac.c

482

p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>

drivers/edac/synopsys_edac.c

484

p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>

drivers/edac/synopsys_edac.c

486

p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);

drivers/edac/synopsys_edac.c

605

int status, regval;

drivers/edac/synopsys_edac.c

615

regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);

drivers/edac/synopsys_edac.c

616

regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);

drivers/edac/synopsys_edac.c

617

if (!(regval & ECC_CE_UE_INTR_MASK))

drivers/edac/synopsys_edac.c

633

writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);

drivers/edac/synopsys_edac.c

997

int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;

drivers/edac/versal_edac.c

1000

priv->bank_bit[0] = FIELD_GET(MASK_24, regval);

drivers/edac/versal_edac.c

1002

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC11_OFFSET);

drivers/edac/versal_edac.c

1003

priv->bank_bit[1] = (regval & MASK_0);

drivers/edac/versal_edac.c

1004

priv->grp_bit[0] = FIELD_GET(GRP_0_MASK, regval);

drivers/edac/versal_edac.c

1005

priv->grp_bit[1] = FIELD_GET(GRP_1_MASK, regval);

drivers/edac/versal_edac.c

1006

priv->ch_bit = FIELD_GET(CH_0_MASK, regval);

drivers/edac/versal_edac.c

1011

u32 regval;

drivers/edac/versal_edac.c

1013

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC4_OFFSET);

drivers/edac/versal_edac.c

1014

priv->rank_bit[0] = (regval & MASK_0);

drivers/edac/versal_edac.c

1015

priv->rank_bit[1] = FIELD_GET(RANK_1_MASK, regval);

drivers/edac/versal_edac.c

1016

priv->lrank_bit[0] = FIELD_GET(LRANK_0_MASK, regval);

drivers/edac/versal_edac.c

1017

priv->lrank_bit[1] = FIELD_GET(LRANK_1_MASK, regval);

drivers/edac/versal_edac.c

1018

priv->lrank_bit[2] = FIELD_GET(MASK_24, regval);

drivers/edac/versal_edac.c

1083

u32 edac_mc_id, regval;

drivers/edac/versal_edac.c

1100

regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);

drivers/edac/versal_edac.c

1101

num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);

drivers/edac/versal_edac.c

1104

num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);

drivers/edac/versal_edac.c

252

u32 regval;

drivers/edac/versal_edac.c

259

regval = readl(ddrmc_base + ECCR0_CE_ADDR_LO_OFFSET);

drivers/edac/versal_edac.c

260

reghi = regval & ECCR_UE_CE_ADDR_HI_ROW_MASK;

drivers/edac/versal_edac.c

261

p->ceinfo[0].i = regval | reghi << 32;

drivers/edac/versal_edac.c

262

regval = readl(ddrmc_base + ECCR0_CE_ADDR_HI_OFFSET);

drivers/edac/versal_edac.c

269

regval = readl(ddrmc_base + ECCR1_CE_ADDR_LO_OFFSET);

drivers/edac/versal_edac.c

271

p->ceinfo[1].i = regval | reghi << 32;

drivers/edac/versal_edac.c

272

regval = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET);

drivers/edac/versal_edac.c

284

u32 regval;

drivers/edac/versal_edac.c

291

regval = readl(ddrmc_base + ECCR0_UE_ADDR_LO_OFFSET);

drivers/edac/versal_edac.c

294

p->ueinfo[0].i = regval | reghi << 32;

drivers/edac/versal_edac.c

295

regval = readl(ddrmc_base + ECCR0_UE_ADDR_HI_OFFSET);

drivers/edac/versal_edac.c

302

regval = readl(ddrmc_base + ECCR1_UE_ADDR_LO_OFFSET);

drivers/edac/versal_edac.c

304

p->ueinfo[1].i = regval | reghi << 32;

drivers/edac/versal_edac.c

460

int regval;

drivers/edac/versal_edac.c

465

regval = readl(priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);

drivers/edac/versal_edac.c

481

writel(regval, priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);

drivers/edac/versal_edac.c

501

u32 regval;

drivers/edac/versal_edac.c

504

regval = readl(base + XDDR_REG_CONFIG0_OFFSET);

drivers/edac/versal_edac.c

505

width = FIELD_GET(XDDR_REG_CONFIG0_BUS_WIDTH_MASK, regval);

drivers/edac/versal_edac.c

555

u32 regval;

drivers/edac/versal_edac.c

558

regval = readl(priv->ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);

drivers/edac/versal_edac.c

559

regval = FIELD_GET(XDDR_REG_CONFIG0_SIZE_MASK, regval);

drivers/edac/versal_edac.c

561

switch (regval) {

drivers/edac/versal_edac.c

685

u32 index, regval;

drivers/edac/versal_edac.c

726

regval = row & XDDR_NOC_ROW_MATCH_MASK;

drivers/edac/versal_edac.c

727

regval |= FIELD_PREP(XDDR_NOC_COL_MATCH_MASK, col);

drivers/edac/versal_edac.c

728

regval |= FIELD_PREP(XDDR_NOC_BANK_MATCH_MASK, bank);

drivers/edac/versal_edac.c

729

regval |= FIELD_PREP(XDDR_NOC_GRP_MATCH_MASK, grp);

drivers/edac/versal_edac.c

730

writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC14_OFFSET);

drivers/edac/versal_edac.c

732

regval = rank & XDDR_NOC_RANK_MATCH_MASK;

drivers/edac/versal_edac.c

733

regval |= FIELD_PREP(XDDR_NOC_LRANK_MATCH_MASK, lrank);

drivers/edac/versal_edac.c

734

regval |= FIELD_PREP(XDDR_NOC_CH_MATCH_MASK, ch);

drivers/edac/versal_edac.c

735

regval |= (XDDR_NOC_MOD_SEL_MASK | XDDR_NOC_MATCH_EN_MASK);

drivers/edac/versal_edac.c

736

writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC15_OFFSET);

drivers/edac/versal_edac.c

937

static inline void process_bit(struct edac_priv *priv, unsigned int start, u32 regval)

drivers/edac/versal_edac.c

941

rows.i = regval;

drivers/edac/versal_edac.c

951

u32 regval;

drivers/edac/versal_edac.c

954

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC5_OFFSET);

drivers/edac/versal_edac.c

955

process_bit(priv, 0, regval);

drivers/edac/versal_edac.c

957

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC6_OFFSET);

drivers/edac/versal_edac.c

958

process_bit(priv, 5, regval);

drivers/edac/versal_edac.c

960

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC7_OFFSET);

drivers/edac/versal_edac.c

961

process_bit(priv, 10, regval);

drivers/edac/versal_edac.c

963

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC8_OFFSET);

drivers/edac/versal_edac.c

964

rows.i = regval;

drivers/edac/versal_edac.c

973

u32 regval;

drivers/edac/versal_edac.c

976

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC8_OFFSET);

drivers/edac/versal_edac.c

977

priv->col_bit[0] = FIELD_GET(MASK_24, regval);

drivers/edac/versal_edac.c

979

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC9_OFFSET);

drivers/edac/versal_edac.c

980

cols.i = regval;

drivers/edac/versal_edac.c

987

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC10_OFFSET);

drivers/edac/versal_edac.c

988

cols.i = regval;

drivers/edac/versal_edac.c

997

u32 regval;

drivers/edac/versal_edac.c

999

regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC10_OFFSET);

drivers/edac/zynqmp_edac.c

192

int regval;

drivers/edac/zynqmp_edac.c

194

regval = readl(priv->baseaddr + OCM_ISR_OFST);

drivers/edac/zynqmp_edac.c

195

if (!(regval & (OCM_CEINTR_MASK | OCM_UEINTR_MASK))) {

drivers/edac/zynqmp_edac.c

196

WARN_ONCE(1, "Unhandled IRQ%d, ISR: 0x%x", irq, regval);

drivers/edac/zynqmp_edac.c

200

get_error_info(priv->baseaddr, &priv->stat, regval);

drivers/firmware/xilinx/zynqmp-ufs.c

38

u32 regval;

drivers/firmware/xilinx/zynqmp-ufs.c

44

ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, TXRX_CFGRDY_OFFSET, &regval);

drivers/firmware/xilinx/zynqmp-ufs.c

48

regval &= TX_RX_CFG_RDY_MASK;

drivers/firmware/xilinx/zynqmp-ufs.c

49

if (regval)

drivers/firmware/xilinx/zynqmp-ufs.c

66

u32 regval;

drivers/firmware/xilinx/zynqmp-ufs.c

72

ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, &regval);

drivers/firmware/xilinx/zynqmp-ufs.c

76

regval &= SRAM_CSR_INIT_DONE_MASK;

drivers/firmware/xilinx/zynqmp-ufs.c

77

if (regval)

drivers/fpga/altera-cvp.c

578

u32 regval;

drivers/fpga/altera-cvp.c

592

pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, &regval);

drivers/fpga/altera-cvp.c

593

if (!(regval & VSE_CVP_STATUS_CVP_EN)) {

drivers/fpga/altera-cvp.c

596

regval);

drivers/gpio/gpio-max77650.c

55

int mask, regval;

drivers/gpio/gpio-max77650.c

58

regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW;

drivers/gpio/gpio-max77650.c

59

regval |= MAX77650_GPIO_DIR_OUT;

drivers/gpio/gpio-max77650.c

62

MAX77650_REG_CNFG_GPIO, mask, regval);

drivers/gpio/gpio-max77650.c

69

int regval;

drivers/gpio/gpio-max77650.c

71

regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW;

drivers/gpio/gpio-max77650.c

74

MAX77650_GPIO_OUTVAL_MASK, regval);

drivers/gpio/gpio-zynqmp-modepin.c

33

u32 regval = 0;

drivers/gpio/gpio-zynqmp-modepin.c

36

ret = zynqmp_pm_bootmode_read(&regval);

drivers/gpio/gpio-zynqmp-modepin.c

43

if (regval & BIT(pin))

drivers/gpio/gpio-zynqmp-modepin.c

44

return !!(regval & BIT(pin + 8));

drivers/gpio/gpio-zynqmp-modepin.c

46

return !!(regval & BIT(pin + 4));

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1131

block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1854

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1860

seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2368

const uint16_t *matrix = params->set_output_csc_params.regval;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

238

val = output_csc_matrix[i].regval;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

84

uint16_t regval[12];

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1255

OUTPUT_CSC_C11, tbl_entry->regval[0],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1256

OUTPUT_CSC_C12, tbl_entry->regval[1]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1260

OUTPUT_CSC_C11, tbl_entry->regval[2],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1261

OUTPUT_CSC_C12, tbl_entry->regval[3]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1265

OUTPUT_CSC_C11, tbl_entry->regval[4],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1266

OUTPUT_CSC_C12, tbl_entry->regval[5]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1270

OUTPUT_CSC_C11, tbl_entry->regval[6],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1271

OUTPUT_CSC_C12, tbl_entry->regval[7]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1275

OUTPUT_CSC_C11, tbl_entry->regval[8],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1276

OUTPUT_CSC_C12, tbl_entry->regval[9]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1280

OUTPUT_CSC_C11, tbl_entry->regval[10],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1281

OUTPUT_CSC_C12, tbl_entry->regval[11]);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

141

tbl_entry->regval[0],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

147

tbl_entry->regval[1],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

159

tbl_entry->regval[2],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

165

tbl_entry->regval[3],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

177

tbl_entry->regval[4],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

183

tbl_entry->regval[5],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

195

tbl_entry->regval[6],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

201

tbl_entry->regval[7],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

213

tbl_entry->regval[8],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

219

tbl_entry->regval[9],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

231

tbl_entry->regval[10],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

237

tbl_entry->regval[11],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

255

tbl_entry->regval[0],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

261

tbl_entry->regval[1],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

273

tbl_entry->regval[2],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

279

tbl_entry->regval[3],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

291

tbl_entry->regval[4],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

297

tbl_entry->regval[5],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

309

tbl_entry->regval[6],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

315

tbl_entry->regval[7],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

327

tbl_entry->regval[8],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

333

tbl_entry->regval[9],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

345

tbl_entry->regval[10],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

351

tbl_entry->regval[11],

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

517

uint32_t regval[12];

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

545

const uint32_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

552

regval = input_csc_matrix[i].regval;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

555

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

572

value, regval[0], INPUT_CSC_C11_C12_A, INPUT_CSC_C11_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

574

value, regval[1], INPUT_CSC_C11_C12_A, INPUT_CSC_C12_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

579

value, regval[2], INPUT_CSC_C13_C14_A, INPUT_CSC_C13_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

581

value, regval[3], INPUT_CSC_C13_C14_A, INPUT_CSC_C14_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

586

value, regval[4], INPUT_CSC_C21_C22_A, INPUT_CSC_C21_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

588

value, regval[5], INPUT_CSC_C21_C22_A, INPUT_CSC_C22_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

593

value, regval[6], INPUT_CSC_C23_C24_A, INPUT_CSC_C23_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

595

value, regval[7], INPUT_CSC_C23_C24_A, INPUT_CSC_C24_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

600

value, regval[8], INPUT_CSC_C31_C32_A, INPUT_CSC_C31_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

602

value, regval[9], INPUT_CSC_C31_C32_A, INPUT_CSC_C32_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

607

value, regval[10], INPUT_CSC_C33_C34_A, INPUT_CSC_C33_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

609

value, regval[11], INPUT_CSC_C33_C34_A, INPUT_CSC_C34_A);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

615

value, regval[0], INPUT_CSC_C11_C12_B, INPUT_CSC_C11_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

617

value, regval[1], INPUT_CSC_C11_C12_B, INPUT_CSC_C12_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

622

value, regval[2], INPUT_CSC_C13_C14_B, INPUT_CSC_C13_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

624

value, regval[3], INPUT_CSC_C13_C14_B, INPUT_CSC_C14_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

629

value, regval[4], INPUT_CSC_C21_C22_B, INPUT_CSC_C21_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

631

value, regval[5], INPUT_CSC_C21_C22_B, INPUT_CSC_C22_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

636

value, regval[6], INPUT_CSC_C23_C24_B, INPUT_CSC_C23_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

638

value, regval[7], INPUT_CSC_C23_C24_B, INPUT_CSC_C24_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

643

value, regval[8], INPUT_CSC_C31_C32_B, INPUT_CSC_C31_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

645

value, regval[9], INPUT_CSC_C31_C32_B, INPUT_CSC_C32_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

650

value, regval[10], INPUT_CSC_C33_C34_B, INPUT_CSC_C33_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

652

value, regval[11], INPUT_CSC_C33_C34_B, INPUT_CSC_C34_B);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

110

uint32_t regval;

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

114

regval = dm_read_reg(tg->ctx, address);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

115

set_reg_field_value(regval, early_cntl,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

117

dm_write_reg(tg->ctx, address, regval);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

259

uint32_t regval;

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

262

regval = dm_read_reg(tg->ctx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

265

set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

269

set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

273

CRTC_REG(mmCRTC_COUNT_CONTROL), regval);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

600

uint32_t regval;

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

603

regval = dm_read_reg(tg->ctx, address);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

604

set_reg_field_value(regval, early_cntl,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

606

dm_write_reg(tg->ctx, address, regval);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

43

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

53

const uint16_t *regval0 = &(regval[2 * i]);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

54

const uint16_t *regval1 = &(regval[(2 * i) + 1]);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

66

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

78

regval[2 * i] = (uint16_t)regval0;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

79

regval[(2 * i) + 1] = (uint16_t)regval1;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h

118

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h

94

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

399

tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1484

const uint16_t *regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

127

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

137

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

147

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

182

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

205

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

215

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

225

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

251

const uint16_t *regval)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

257

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

297

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

309

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

312

regval = find_color_matrix(colorspace, &arr_size);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

313

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

318

dpp1_cm_program_color_matrix(dpp, regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

376

const uint16_t *regval)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

380

dpp1_cm_program_color_matrix(dpp, regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

495

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

508

regval = dpp_input_csc_matrix[i].regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

512

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

517

regval = tbl_entry->regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

554

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

90

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

96

if (regval == NULL || select == GAMUT_REMAP_BYPASS) {

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

238

tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

163

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

169

if (regval == NULL || select == DCN2_GAMUT_REMAP_BYPASS) {

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

204

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

238

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

260

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

268

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

301

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

314

regval = dpp_input_csc_matrix[i].regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

318

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

323

regval = tbl_entry->regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

358

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

113

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

126

regval = dpp_input_csc_matrix[i].regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

130

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

135

regval = tbl_entry->regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

169

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

375

tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

320

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

326

if (regval == NULL || select == GAMUT_REMAP_BYPASS) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

357

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

367

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

414

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

435

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

443

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

205

tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

178

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

191

regval = dpp_input_csc_matrix[i].regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

195

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

201

regval = tbl_entry->regval;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

227

regval,

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

268

tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

302

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

310

if (regval == NULL || select == CM_GAMUT_REMAP_MODE_BYPASS) {

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

330

regval,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

339

regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

101

REG_SET_2(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

118

REG_SET(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

127

REG_SET(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

163

REG_SET(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

72

uint32_t regval;

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

84

regval = REG_GET_3(gpio.MASK_reg,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

99

REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3129

tbl_entry.regval[i] =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3309

tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

295

tbl_entry.regval[i] =

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

155

const uint16_t *regval;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1953

struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

268

const uint16_t *regval);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

94

uint16_t regval[12];

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

268

uint16_t regval[12];

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

715

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

132

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

144

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

177

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

193

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

200

regval = find_color_matrix(color_space, &arr_size);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

202

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

236

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

295

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1069

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1075

if (regval == NULL || select == GAMUT_REMAP_BYPASS) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1106

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1116

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1162

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1181

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1191

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1306

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1319

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1338

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1351

const uint16_t *regval = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1359

regval = find_color_matrix(color_space, &arr_size);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1361

if (regval == NULL) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1382

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1043

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

303

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

313

if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

339

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

347

if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

373

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

382

if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

408

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

473

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

557

regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

243

const uint16_t *regval,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

249

uint16_t *regval,

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

372

uint32_t regval = enable ? 1 : 0;

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

374

REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);

drivers/gpu/drm/i915/display/intel_display_regs.h

2620

#define DDI_PORT_WIDTH_DECODE(regval) ((regval) == 4 ? 3 : (regval) + 1)

drivers/gpu/drm/i915/display/intel_display_regs.h

2623

#define DDI_PORT_WIDTH_GET(regval) DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2624

(regval)))

drivers/gpu/drm/mediatek/mtk_dsi.c

378

u32 regval, tmp_reg = 0;

drivers/gpu/drm/mediatek/mtk_dsi.c

385

regval = FIELD_PREP(LANE_NUM, tmp_reg);

drivers/gpu/drm/mediatek/mtk_dsi.c

388

regval |= HSTX_CKLP_EN;

drivers/gpu/drm/mediatek/mtk_dsi.c

391

regval |= DIS_EOT;

drivers/gpu/drm/mediatek/mtk_dsi.c

393

writel(regval, dsi->regs + DSI_TXRX_CTRL);

drivers/gpu/drm/tidss/tidss_dispc.c

1530

void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval);

drivers/gpu/drm/tidss/tidss_dispc.c

1541

void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval)

drivers/gpu/drm/tidss/tidss_dispc.c

1544

regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]);

drivers/gpu/drm/tidss/tidss_dispc.c

1545

regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]);

drivers/gpu/drm/tidss/tidss_dispc.c

1546

regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]);

drivers/gpu/drm/tidss/tidss_dispc.c

1552

void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval)

drivers/gpu/drm/tidss/tidss_dispc.c

1554

regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1555

regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]);

drivers/gpu/drm/tidss/tidss_dispc.c

1556

regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]);

drivers/gpu/drm/tidss/tidss_dispc.c

1557

regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1558

regval[4] = CVAL(csc->m[CSC_BCB], 0);

drivers/gpu/drm/tidss/tidss_dispc.c

1560

dispc_csc_offset_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

1564

void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval)

drivers/gpu/drm/tidss/tidss_dispc.c

1566

regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1567

regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1568

regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]);

drivers/gpu/drm/tidss/tidss_dispc.c

1569

regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1570

regval[4] = CVAL(csc->m[CSC_CBB], 0);

drivers/gpu/drm/tidss/tidss_dispc.c

1572

dispc_csc_offset_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

1576

u32 *regval)

drivers/gpu/drm/tidss/tidss_dispc.c

1578

regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1579

regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1580

regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]);

drivers/gpu/drm/tidss/tidss_dispc.c

1581

regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1582

regval[4] = CVAL(csc->m[CSC_BB], 0);

drivers/gpu/drm/tidss/tidss_dispc.c

1584

dispc_csc_offset_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

1598

u32 regval[DISPC_CSC_REGVAL_LEN];

drivers/gpu/drm/tidss/tidss_dispc.c

1601

csc->to_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

1603

if (regval[7] != 0)

drivers/gpu/drm/tidss/tidss_dispc.c

1609

regval[i]);

drivers/gpu/drm/tidss/tidss_dispc.c

1621

u32 regval[DISPC_CSC_REGVAL_LEN];

drivers/gpu/drm/tidss/tidss_dispc.c

1624

csc->to_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

1628

regval[i]);

drivers/gpu/drm/tidss/tidss_dispc.c

2635

u32 *regval)

drivers/gpu/drm/tidss/tidss_dispc.c

2637

regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]);

drivers/gpu/drm/tidss/tidss_dispc.c

2638

regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]);

drivers/gpu/drm/tidss/tidss_dispc.c

2639

regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]);

drivers/gpu/drm/tidss/tidss_dispc.c

2651

u32 regval[DISPC_CSC_REGVAL_LEN];

drivers/gpu/drm/tidss/tidss_dispc.c

2654

dispc_k2g_vp_csc_cpr_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

2658

regval[i]);

drivers/gpu/drm/tidss/tidss_dispc.c

2717

u32 regval[DISPC_CSC_REGVAL_LEN];

drivers/gpu/drm/tidss/tidss_dispc.c

2720

csc->to_regval(csc, regval);

drivers/gpu/drm/tidss/tidss_dispc.c

2722

for (i = 0; i < ARRAY_SIZE(regval); i++)

drivers/gpu/drm/tidss/tidss_dispc.c

2724

regval[i]);

drivers/gpu/ipu-v3/ipu-common.c

289

u32 bursts, regval;

drivers/gpu/ipu-v3/ipu-common.c

327

regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);

drivers/gpu/ipu-v3/ipu-common.c

328

regval &= ~(0x03 << idmac_lock_en_info[i].shift);

drivers/gpu/ipu-v3/ipu-common.c

329

regval |= (bursts << idmac_lock_en_info[i].shift);

drivers/gpu/ipu-v3/ipu-common.c

330

ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);

drivers/hwmon/adc128d818.c

168

u8 reg, regval;

drivers/hwmon/adc128d818.c

178

regval = DIV_ROUND_CLOSEST(clamp_val(val, 0, 2550), 10);

drivers/hwmon/adc128d818.c

179

data->in[index][nr] = regval << 4;

drivers/hwmon/adc128d818.c

181

i2c_smbus_write_byte_data(data->client, reg, regval);

drivers/hwmon/adc128d818.c

209

s8 regval;

drivers/hwmon/adc128d818.c

216

regval = DIV_ROUND_CLOSEST(clamp_val(val, -128000, 127000), 1000);

drivers/hwmon/adc128d818.c

217

data->temp[index] = regval << 1;

drivers/hwmon/adc128d818.c

221

regval);

drivers/hwmon/adc128d818.c

395

u8 regval = 0x0;

drivers/hwmon/adc128d818.c

407

regval |= data->mode << 1;

drivers/hwmon/adc128d818.c

411

regval |= 0x01;

drivers/hwmon/adc128d818.c

414

if (regval != 0x0) {

drivers/hwmon/adc128d818.c

416

regval);

drivers/hwmon/adm9240.c

212

unsigned int regval;

drivers/hwmon/adm9240.c

216

err = regmap_read(data->regmap, ADM9240_REG_VID_FAN_DIV, &regval);

drivers/hwmon/adm9240.c

219

vid = regval & 0x0f;

drivers/hwmon/adm9240.c

220

err = regmap_read(data->regmap, ADM9240_REG_VID4, &regval);

drivers/hwmon/adm9240.c

223

vid |= (regval & 1) << 4;

drivers/hwmon/adm9240.c

232

unsigned int regval;

drivers/hwmon/adm9240.c

235

err = regmap_read(data->regmap, ADM9240_REG_ANALOG_OUT, &regval);

drivers/hwmon/adm9240.c

239

return sprintf(buf, "%d\n", AOUT_FROM_REG(regval));

drivers/hwmon/adm9240.c

309

unsigned int regval;

drivers/hwmon/adm9240.c

367

err = regmap_read(data->regmap, ADM9240_REG_VID_FAN_DIV, &regval);

drivers/hwmon/adm9240.c

370

data->fan_div[0] = (regval >> 4) & 3;

drivers/hwmon/adm9240.c

371

data->fan_div[1] = (regval >> 6) & 3;

drivers/hwmon/adm9240.c

397

unsigned int regval;

drivers/hwmon/adm9240.c

402

err = regmap_read(data->regmap, ADM9240_REG_INT(1), &regval);

drivers/hwmon/adm9240.c

405

*val = !!(regval & BIT(4));

drivers/hwmon/adm9240.c

436

unsigned int regval;

drivers/hwmon/adm9240.c

457

err = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/adm9240.c

460

*val = !!(regval & BIT(channel));

drivers/hwmon/adm9240.c

465

err = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/adm9240.c

468

*val = IN_FROM_REG(regval, channel);

drivers/hwmon/adm9240.c

493

unsigned int regval;

drivers/hwmon/adm9240.c

498

err = regmap_read(data->regmap, ADM9240_REG_FAN(channel), &regval);

drivers/hwmon/adm9240.c

501

if (regval == 255 && data->fan_div[channel] < 3) {

drivers/hwmon/adm9240.c

508

*val = FAN_FROM_REG(regval, BIT(data->fan_div[channel]));

drivers/hwmon/adm9240.c

514

err = regmap_read(data->regmap, ADM9240_REG_FAN_MIN(channel), &regval);

drivers/hwmon/adm9240.c

517

*val = FAN_FROM_REG(regval, BIT(data->fan_div[channel]));

drivers/hwmon/adm9240.c

520

err = regmap_read(data->regmap, ADM9240_REG_INT(0), &regval);

drivers/hwmon/adm9240.c

523

*val = !!(regval & BIT(channel + 6));

drivers/hwmon/adm9240.c

551

unsigned int regval;

drivers/hwmon/adm9240.c

556

err = regmap_read(data->regmap, ADM9240_REG_TEMP, &regval);

drivers/hwmon/adm9240.c

559

temp = regval << 1;

drivers/hwmon/adm9240.c

560

err = regmap_read(data->regmap, ADM9240_REG_TEMP_CONF, &regval);

drivers/hwmon/adm9240.c

563

temp |= regval >> 7;

drivers/hwmon/adm9240.c

567

err = regmap_read(data->regmap, ADM9240_REG_TEMP_MAX(0), &regval);

drivers/hwmon/adm9240.c

570

*val = (s8)regval * 1000;

drivers/hwmon/adm9240.c

573

err = regmap_read(data->regmap, ADM9240_REG_TEMP_MAX(1), &regval);

drivers/hwmon/adm9240.c

576

*val = (s8)regval * 1000;

drivers/hwmon/adm9240.c

579

err = regmap_read(data->regmap, ADM9240_REG_INT(0), &regval);

drivers/hwmon/adm9240.c

582

*val = !!(regval & BIT(4));

drivers/hwmon/ads7828.c

112

unsigned int regval;

drivers/hwmon/ads7828.c

170

regmap_read(data->regmap, data->cmd_byte, &regval);

drivers/hwmon/ads7828.c

58

unsigned int regval;

drivers/hwmon/ads7828.c

61

err = regmap_read(data->regmap, cmd, &regval);

drivers/hwmon/ads7828.c

66

DIV_ROUND_CLOSEST(regval * data->lsb_resol, 1000));

drivers/hwmon/adt7310.c

100

return regval;

drivers/hwmon/adt7310.c

101

*val = regval;

drivers/hwmon/adt7310.c

86

int regval;

drivers/hwmon/adt7310.c

93

regval = adt7310_spi_read_word(spi, reg);

drivers/hwmon/adt7310.c

96

regval = adt7310_spi_read_byte(spi, reg);

drivers/hwmon/adt7310.c

99

if (regval < 0)

drivers/hwmon/adt7410.c

30

int regval;

drivers/hwmon/adt7410.c

37

regval = i2c_smbus_read_word_swapped(client, reg);

drivers/hwmon/adt7410.c

40

regval = i2c_smbus_read_byte_data(client, reg);

drivers/hwmon/adt7410.c

43

if (regval < 0)

drivers/hwmon/adt7410.c

44

return regval;

drivers/hwmon/adt7410.c

45

*val = regval;

drivers/hwmon/adt7470.c

182

u8 regval[2];

drivers/hwmon/adt7470.c

185

err = regmap_bulk_read(data->regmap, reg, &regval, 2);

drivers/hwmon/adt7470.c

189

*val = regval[0] | (regval[1] << 8);

drivers/hwmon/adt7470.c

197

u8 regval[2];

drivers/hwmon/adt7470.c

199

regval[0] = val & 0xFF;

drivers/hwmon/adt7470.c

200

regval[1] = val >> 8;

drivers/hwmon/adt7470.c

202

return regmap_bulk_write(data->regmap, reg, &regval, 2);

drivers/hwmon/adt7x10.c

135

unsigned int regval;

drivers/hwmon/adt7x10.c

146

ret = regmap_read(data->regmap, ADT7X10_REG_TEMP[index], &regval);

drivers/hwmon/adt7x10.c

150

*val = ADT7X10_REG_TO_TEMP(data, regval);

drivers/hwmon/adt7x10.c

186

unsigned int regval;

drivers/hwmon/adt7x10.c

190

ret = regmap_read(data->regmap, ADT7X10_T_ALARM_HIGH, &regval);

drivers/hwmon/adt7x10.c

194

limit = ADT7X10_REG_TO_TEMP(data, regval);

drivers/hwmon/adt7x10.c

197

regval = clamp_val(DIV_ROUND_CLOSEST(limit - hyst, 1000), 0,

drivers/hwmon/adt7x10.c

199

return regmap_write(data->regmap, ADT7X10_T_HYST, regval);

drivers/hwmon/amc6821.c

176

u32 regval;

drivers/hwmon/amc6821.c

194

err = regmap_read(regmap, reg, &regval);

drivers/hwmon/amc6821.c

197

*val = sign_extend32(regval, 7) * 1000;

drivers/hwmon/amc6821.c

205

u32 regval;

drivers/hwmon/amc6821.c

243

err = regmap_read(regmap, reg, &regval);

drivers/hwmon/amc6821.c

246

*val = !!(regval & mask);

drivers/hwmon/amc6821.c

297

u32 regval;

drivers/hwmon/amc6821.c

302

err = regmap_read(regmap, AMC6821_REG_CONF1, &regval);

drivers/hwmon/amc6821.c

305

switch (regval & (AMC6821_CONF1_FDRC0 | AMC6821_CONF1_FDRC1)) {

drivers/hwmon/amc6821.c

321

err = regmap_read(regmap, AMC6821_REG_CONF2, &regval);

drivers/hwmon/amc6821.c

324

*val = !!(regval & AMC6821_CONF2_TACH_MODE);

drivers/hwmon/amc6821.c

327

err = regmap_read(regmap, AMC6821_REG_CONF1, &regval);

drivers/hwmon/amc6821.c

330

switch (regval & (AMC6821_CONF1_FDRC0 | AMC6821_CONF1_FDRC1)) {

drivers/hwmon/amc6821.c

344

err = regmap_read(regmap, AMC6821_REG_DCY, &regval);

drivers/hwmon/amc6821.c

347

*val = regval;

drivers/hwmon/amc6821.c

401

u32 regval;

drivers/hwmon/amc6821.c

424

regval = (regs[1] << 8) | regs[0];

drivers/hwmon/amc6821.c

425

*val = regval ? 6000000 / regval : 0;

drivers/hwmon/amc6821.c

434

u32 regval;

drivers/hwmon/amc6821.c

446

err = regmap_read(regmap, AMC6821_REG_CONF4, &regval);

drivers/hwmon/amc6821.c

449

*val = (regval & AMC6821_CONF4_PSPR) ? 4 : 2;

drivers/hwmon/amc6821.c

555

u8 regval = FIELD_PREP(AMC6821_TEMP_LIMIT_MASK, temps[1] / 4);

drivers/hwmon/amc6821.c

571

regval |= FIELD_PREP(AMC6821_TEMP_SLOPE_MASK, tmp);

drivers/hwmon/amc6821.c

575

regval);

drivers/hwmon/amc6821.c

971

u32 regval;

drivers/hwmon/amc6821.c

988

regval = AMC6821_CONF1_START;

drivers/hwmon/amc6821.c

990

regval |= AMC6821_CONF1_PWMINV;

drivers/hwmon/amc6821.c

995

regval);

drivers/hwmon/asc7621.c

237

u16 regval;

drivers/hwmon/asc7621.c

240

regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]];

drivers/hwmon/asc7621.c

244

(regval == 0 ? -1 : (regval) ==

drivers/hwmon/asc7621.c

245

0xffff ? 0 : 5400000 / regval));

drivers/hwmon/asc7621.c

298

u16 regval;

drivers/hwmon/asc7621.c

302

regval = (data->reg[param->msb[0]] << 8) | (data->reg[param->lsb[0]]);

drivers/hwmon/asc7621.c

306

regval = (regval >> 6) * asc7621_in_scaling[nr] / (0xc0 << 2);

drivers/hwmon/asc7621.c

308

return sprintf(buf, "%u\n", regval);

drivers/hwmon/asc7621.c

405

u8 regval = data->reg[param->msb[0]];

drivers/hwmon/asc7621.c

406

int temp = ((s8) (regval & 0xfc) * 1000) + ((regval & 0x03) * 250);

drivers/hwmon/asc7621.c

451

u8 regval;

drivers/hwmon/asc7621.c

456

regval =

drivers/hwmon/asc7621.c

458

temp = auto_point1 + asc7621_range_map[clamp_val(regval, 0, 15)];

drivers/hwmon/asc7621.c

501

u8 config, altbit, regval;

drivers/hwmon/asc7621.c

510

regval = config | (altbit << 3);

drivers/hwmon/asc7621.c

513

return sprintf(buf, "%u\n", map[clamp_val(regval, 0, 15)]);

drivers/hwmon/asc7621.c

649

u8 regval =

drivers/hwmon/asc7621.c

652

regval = clamp_val(regval, 0, 15);

drivers/hwmon/asc7621.c

654

return sprintf(buf, "%u\n", asc7621_pwm_freq_map[regval]);

drivers/hwmon/asc7621.c

697

u8 regval =

drivers/hwmon/asc7621.c

700

regval = clamp_val(regval, 0, 7);

drivers/hwmon/asc7621.c

702

return sprintf(buf, "%u\n", asc7621_pwm_auto_spinup_map[regval]);

drivers/hwmon/asc7621.c

746

u8 regval =

drivers/hwmon/asc7621.c

748

regval = clamp_val(regval, 0, 7);

drivers/hwmon/asc7621.c

750

return sprintf(buf, "%u\n", asc7621_temp_smoothing_time_map[regval]);

drivers/hwmon/emc1403.c

317

unsigned int regval;

drivers/hwmon/emc1403.c

338

ret = regmap_read(data->regmap, 0x02, &regval);

drivers/hwmon/emc1403.c

341

*val = !!(regval & BIT(5 - 2 * channel));

drivers/hwmon/emc1403.c

343

ret = regmap_read(data->regmap, 0x36, &regval);

drivers/hwmon/emc1403.c

346

*val = !!(regval & BIT(channel));

drivers/hwmon/emc1403.c

351

ret = regmap_read(data->regmap, 0x02, &regval);

drivers/hwmon/emc1403.c

354

*val = !!(regval & BIT(6 - 2 * channel));

drivers/hwmon/emc1403.c

356

ret = regmap_read(data->regmap, 0x35, &regval);

drivers/hwmon/emc1403.c

359

*val = !!(regval & BIT(channel));

drivers/hwmon/emc1403.c

364

ret = regmap_read(data->regmap, 0x02, &regval);

drivers/hwmon/emc1403.c

367

*val = !!(regval & BIT(channel));

drivers/hwmon/emc1403.c

369

ret = regmap_read(data->regmap, 0x37, &regval);

drivers/hwmon/emc1403.c

372

*val = !!(regval & BIT(channel));

drivers/hwmon/emc1403.c

376

ret = regmap_read(data->regmap, 0x1b, &regval);

drivers/hwmon/emc1403.c

379

*val = !!(regval & BIT(channel));

drivers/hwmon/emc1403.c

452

unsigned int regval;

drivers/hwmon/emc1403.c

465

regval = DIV_ROUND_CLOSEST(val, 125);

drivers/hwmon/emc1403.c

466

ret = regmap_write(data->regmap, regh, (regval >> 3) & 0xff);

drivers/hwmon/emc1403.c

469

ret = regmap_write(data->regmap, regl, (regval & 0x07) << 5);

drivers/hwmon/emc1403.c

475

regval = DIV_ROUND_CLOSEST(val, 1000);

drivers/hwmon/emc1403.c

476

ret = regmap_write(data->regmap, regh, regval);

drivers/hwmon/ina209.c

234

u16 regval;

drivers/hwmon/ina209.c

245

regval = ina209_reg_from_interval(data->regs[INA209_CONFIGURATION],

drivers/hwmon/ina209.c

248

regval);

drivers/hwmon/ina209.c

249

data->regs[INA209_CONFIGURATION] = regval;

drivers/hwmon/ina209.c

250

data->update_interval = ina209_interval_from_reg(regval);

drivers/hwmon/ina238.c

259

u32 regval;

drivers/hwmon/ina238.c

262

err = ina238_read_reg24(client, reg, &regval);

drivers/hwmon/ina238.c

267

regval >>= 4;

drivers/hwmon/ina238.c

269

*val = sign_extend32(regval, 19);

drivers/hwmon/ina238.c

279

int err, regval;

drivers/hwmon/ina238.c

282

err = ina238_read_field_s20(data->client, reg, &regval);

drivers/hwmon/ina238.c

289

err = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/ina238.c

292

regval = (s16)regval;

drivers/hwmon/ina238.c

295

*val = DIV_S64_ROUND_CLOSEST((s64)regval * lsb, factor);

drivers/hwmon/ina238.c

409

int regval;

drivers/hwmon/ina238.c

460

err = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/ina238.c

465

*val = !!(regval & mask);

drivers/hwmon/ina238.c

467

*val = DIV_S64_ROUND_CLOSEST((s64)(s16)regval * data->voltage_lsb[channel],

drivers/hwmon/ina238.c

480

int regval;

drivers/hwmon/ina238.c

486

regval = clamp_val(val, S16_MIN, S16_MAX) & 0xffff;

drivers/hwmon/ina238.c

490

return regmap_write(data->regmap, low_regs[channel], regval);

drivers/hwmon/ina238.c

492

return regmap_write(data->regmap, high_regs[channel], regval);

drivers/hwmon/ina238.c

501

int err, regval;

drivers/hwmon/ina238.c

504

err = ina238_read_field_s20(data->client, INA238_CURRENT, &regval);

drivers/hwmon/ina238.c

509

err = regmap_read(data->regmap, INA238_CURRENT, &regval);

drivers/hwmon/ina238.c

512

regval = (s16)regval;

drivers/hwmon/ina238.c

515

*val = DIV_S64_ROUND_CLOSEST((s64)regval * lsb, 1000);

drivers/hwmon/ina238.c

523

int regval;

drivers/hwmon/ina238.c

548

err = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/ina238.c

553

*val = !!(regval & mask);

drivers/hwmon/ina238.c

555

*val = DIV_S64_ROUND_CLOSEST((s64)(s16)regval * data->current_lsb, 1000);

drivers/hwmon/ina238.c

563

int regval;

drivers/hwmon/ina238.c

570

regval = clamp_val(val, S16_MIN, S16_MAX) & 0xffff;

drivers/hwmon/ina238.c

575

regval);

drivers/hwmon/ina238.c

578

regval);

drivers/hwmon/ina238.c

588

int regval;

drivers/hwmon/ina238.c

593

err = ina238_read_reg24(data->client, INA238_POWER, &regval);

drivers/hwmon/ina238.c

597

power = (long long)regval * data->power_lsb;

drivers/hwmon/ina238.c

602

err = ina238_read_reg24(data->client, SQ52206_POWER_PEAK, &regval);

drivers/hwmon/ina238.c

606

power = (long long)regval * data->power_lsb;

drivers/hwmon/ina238.c

611

err = regmap_read(data->regmap, INA238_POWER_LIMIT, &regval);

drivers/hwmon/ina238.c

619

power = ((long long)regval << 8) * data->power_lsb;

drivers/hwmon/ina238.c

624

err = regmap_read(data->regmap, INA238_DIAG_ALERT, &regval);

drivers/hwmon/ina238.c

628

*val = !!(regval & INA238_DIAG_ALERT_POL);

drivers/hwmon/ina238.c

654

static int ina238_temp_from_reg(s16 regval, u8 resolution)

drivers/hwmon/ina238.c

656

return ((regval >> (16 - resolution)) * 1000) >> (resolution - 9);

drivers/hwmon/ina238.c

662

int regval;

drivers/hwmon/ina238.c

667

err = regmap_read(data->regmap, INA238_DIE_TEMP, &regval);

drivers/hwmon/ina238.c

670

*val = ina238_temp_from_reg(regval, data->config->temp_resolution);

drivers/hwmon/ina238.c

673

err = regmap_read(data->regmap, INA238_TEMP_LIMIT, &regval);

drivers/hwmon/ina238.c

677

*val = ina238_temp_from_reg(regval, data->config->temp_resolution);

drivers/hwmon/ina238.c

680

err = regmap_read(data->regmap, INA238_DIAG_ALERT, &regval);

drivers/hwmon/ina238.c

684

*val = !!(regval & INA238_DIAG_ALERT_TMPOL);

drivers/hwmon/ina238.c

705

int regval;

drivers/hwmon/ina238.c

707

regval = ina238_temp_to_reg(val, data->config->temp_resolution);

drivers/hwmon/ina238.c

708

return regmap_write(data->regmap, INA238_TEMP_LIMIT, regval);

drivers/hwmon/ina238.c

714

u64 regval;

drivers/hwmon/ina238.c

717

ret = ina238_read_reg40(data->client, SQ52206_ENERGY, &regval);

drivers/hwmon/ina238.c

722

*energy = regval * data->energy_lsb;

drivers/hwmon/ina2xx.c

270

unsigned int regval)

drivers/hwmon/ina2xx.c

277

val = (s16)regval >> data->config->shunt_voltage_shift;

drivers/hwmon/ina2xx.c

281

val = (regval >> data->config->bus_voltage_shift) *

drivers/hwmon/ina2xx.c

286

val = regval * data->power_lsb_uW;

drivers/hwmon/ina2xx.c

290

val = ((s16)regval >> data->config->current_shift) *

drivers/hwmon/ina2xx.c

295

val = regval;

drivers/hwmon/ina2xx.c

315

unsigned int regval;

drivers/hwmon/ina2xx.c

320

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/ina2xx.c

323

*val = ina2xx_get_value(data, reg, regval);

drivers/hwmon/ina2xx.c

328

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/ina2xx.c

340

if (regval == 0) {

drivers/hwmon/ina2xx.c

362

*val = ina2xx_get_value(data, reg, regval);

drivers/hwmon/ina2xx.c

412

int regval;

drivers/hwmon/ina2xx.c

415

ret = regmap_read(regmap, INA226_MASK_ENABLE, &regval);

drivers/hwmon/ina2xx.c

419

if (regval & mask) {

drivers/hwmon/ina2xx.c

420

ret = regmap_read(regmap, INA226_ALERT_LIMIT, &regval);

drivers/hwmon/ina2xx.c

423

*val = ina2xx_get_value(data, reg, regval);

drivers/hwmon/ina2xx.c

462

u32 regval;

drivers/hwmon/ina2xx.c

467

ret = regmap_read(data->regmap, INA2XX_CONFIG, &regval);

drivers/hwmon/ina2xx.c

471

*val = ina226_reg_to_interval(regval);

drivers/hwmon/ina2xx.c

481

unsigned int regval;

drivers/hwmon/ina2xx.c

484

ret = regmap_read_bypassed(regmap, INA226_MASK_ENABLE, &regval);

drivers/hwmon/ina2xx.c

488

*val = (regval & mask) && (regval & INA226_ALERT_FUNCTION_FLAG);

drivers/hwmon/ina2xx.c

502

unsigned int regval;

drivers/hwmon/ina2xx.c

507

ret = regmap_read(regmap, voltage_reg, &regval);

drivers/hwmon/ina2xx.c

510

*val = ina2xx_get_value(data, voltage_reg, regval);

drivers/hwmon/ina2xx.c

586

unsigned int regval;

drivers/hwmon/ina2xx.c

606

ret = regmap_read(regmap, INA2XX_SHUNT_VOLTAGE, &regval);

drivers/hwmon/ina2xx.c

609

*val = ina2xx_get_value(data, INA2XX_CURRENT, regval);

drivers/hwmon/ina3221.c

223

unsigned int regval;

drivers/hwmon/ina3221.c

226

ret = regmap_read(ina->regmap, reg, &regval);

drivers/hwmon/ina3221.c

235

*val = sign_extend32(regval >> 1, 14);

drivers/hwmon/ina3221.c

237

*val = sign_extend32(regval >> 3, 12);

drivers/hwmon/ina3221.c

255

int regval;

drivers/hwmon/ina3221.c

259

regval = INA3221_CONFIG_AVG(ina->reg_config);

drivers/hwmon/ina3221.c

260

*val = ina3221_avg_samples[regval];

drivers/hwmon/ina3221.c

277

int regval, ret;

drivers/hwmon/ina3221.c

301

ret = ina3221_read_value(ina, reg, &regval);

drivers/hwmon/ina3221.c

309

*val = regval * (is_shunt ? 40 : 8);

drivers/hwmon/ina3221.c

336

int regval, ret;

drivers/hwmon/ina3221.c

364

ret = ina3221_read_value(ina, reg, &regval);

drivers/hwmon/ina3221.c

369

voltage_nv = regval * 40000;

drivers/hwmon/ina3221.c

381

ret = regmap_field_read(ina->fields[reg], &regval);

drivers/hwmon/ina3221.c

384

*val = regval;

drivers/hwmon/ina3221.c

440

int regval;

drivers/hwmon/ina3221.c

472

regval = DIV_ROUND_CLOSEST(voltage_uv, 20) & 0xfffe;

drivers/hwmon/ina3221.c

474

regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8;

drivers/hwmon/ina3221.c

476

return regmap_write(ina->regmap, reg, regval);

drivers/hwmon/intel-m10-bmc-hwmon.c

584

unsigned int regval;

drivers/hwmon/intel-m10-bmc-hwmon.c

587

ret = m10bmc_sys_read(hw->m10bmc, regoff, &regval);

drivers/hwmon/intel-m10-bmc-hwmon.c

598

if (regval == 0xdeadbeef)

drivers/hwmon/intel-m10-bmc-hwmon.c

601

*val = regval * data->multiplier;

drivers/hwmon/isl28022.c

102

ISL28022_REG_BUS, &regval);

drivers/hwmon/isl28022.c

106

*val = (long)(((u16)regval) & 0xFFFC);

drivers/hwmon/isl28022.c

116

ISL28022_REG_SHUNT, &regval);

drivers/hwmon/isl28022.c

121

sign_bit = (regval >> 15) & 0x01;

drivers/hwmon/isl28022.c

122

*val = (long)((((u16)regval) & 0x7FFF) -

drivers/hwmon/isl28022.c

126

sign_bit = (regval >> 14) & 0x01;

drivers/hwmon/isl28022.c

127

*val = (long)((((u16)regval) & 0x3FFF) -

drivers/hwmon/isl28022.c

131

sign_bit = (regval >> 13) & 0x01;

drivers/hwmon/isl28022.c

132

*val = (long)((((u16)regval) & 0x1FFF) -

drivers/hwmon/isl28022.c

136

sign_bit = (regval >> 12) & 0x01;

drivers/hwmon/isl28022.c

137

*val = (long)((((u16)regval) & 0x0FFF) -

drivers/hwmon/isl28022.c

156

unsigned int regval;

drivers/hwmon/isl28022.c

163

ISL28022_REG_CURRENT, &regval);

drivers/hwmon/isl28022.c

166

sign_bit = (regval >> 15) & 0x01;

drivers/hwmon/isl28022.c

167

*val = (((long)(((u16)regval) & 0x7FFF) - (sign_bit * 32768)) *

drivers/hwmon/isl28022.c

180

unsigned int regval;

drivers/hwmon/isl28022.c

186

ISL28022_REG_POWER, &regval);

drivers/hwmon/isl28022.c

189

*val = min(div_u64(51200000ULL * data->gain * regval,

drivers/hwmon/isl28022.c

315

unsigned int regval;

drivers/hwmon/isl28022.c

319

ISL28022_REG_SHUNT, &regval);

drivers/hwmon/isl28022.c

324

seq_printf(seqf, "%d\n", regval * 10);

drivers/hwmon/isl28022.c

93

unsigned int regval;

drivers/hwmon/it87.c

1118

u8 reg, regval;

drivers/hwmon/it87.c

1137

regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);

drivers/hwmon/it87.c

1138

if (!(regval & 0x80)) {

drivers/hwmon/it87.c

1139

regval |= 0x80;

drivers/hwmon/it87.c

1140

it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);

drivers/hwmon/jc42.c

213

unsigned int regval;

drivers/hwmon/jc42.c

218

ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);

drivers/hwmon/jc42.c

222

*val = jc42_temp_from_reg(regval);

drivers/hwmon/jc42.c

225

ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, &regval);

drivers/hwmon/jc42.c

229

*val = jc42_temp_from_reg(regval);

drivers/hwmon/jc42.c

232

ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, &regval);

drivers/hwmon/jc42.c

236

*val = jc42_temp_from_reg(regval);

drivers/hwmon/jc42.c

240

&regval);

drivers/hwmon/jc42.c

244

*val = jc42_temp_from_reg(regval);

drivers/hwmon/jc42.c

247

ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, &regval);

drivers/hwmon/jc42.c

251

temp = jc42_temp_from_reg(regval);

drivers/hwmon/jc42.c

258

&regval);

drivers/hwmon/jc42.c

262

temp = jc42_temp_from_reg(regval);

drivers/hwmon/jc42.c

268

ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);

drivers/hwmon/jc42.c

272

*val = FIELD_GET(JC42_ALARM_MIN, regval);

drivers/hwmon/jc42.c

275

ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);

drivers/hwmon/jc42.c

279

*val = FIELD_GET(JC42_ALARM_MAX, regval);

drivers/hwmon/jc42.c

282

ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);

drivers/hwmon/jc42.c

286

*val = FIELD_GET(JC42_ALARM_CRIT, regval);

drivers/hwmon/jc42.c

300

unsigned int regval;

drivers/hwmon/jc42.c

319

&regval);

drivers/hwmon/jc42.c

330

diff = jc42_temp_from_reg(regval) - val;

drivers/hwmon/k10temp.c

101

void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);

drivers/hwmon/k10temp.c

102

void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);

drivers/hwmon/k10temp.c

132

static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)

drivers/hwmon/k10temp.c

134

pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);

drivers/hwmon/k10temp.c

137

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)

drivers/hwmon/k10temp.c

139

pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);

drivers/hwmon/k10temp.c

151

static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)

drivers/hwmon/k10temp.c

154

F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);

drivers/hwmon/k10temp.c

157

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)

drivers/hwmon/k10temp.c

160

F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);

drivers/hwmon/k10temp.c

168

static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)

drivers/hwmon/k10temp.c

171

ZEN_REPORTED_TEMP_CTRL_BASE, regval))

drivers/hwmon/k10temp.c

172

*regval = 0;

drivers/hwmon/k10temp.c

175

static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval)

drivers/hwmon/k10temp.c

179

return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval);

drivers/hwmon/k10temp.c

184

u32 regval;

drivers/hwmon/k10temp.c

187

data->read_tempreg(data->pdev, &regval);

drivers/hwmon/k10temp.c

188

temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;

drivers/hwmon/k10temp.c

189

if ((regval & data->temp_adjust_mask) ||

drivers/hwmon/k10temp.c

190

(regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)

drivers/hwmon/k10temp.c

231

u32 regval;

drivers/hwmon/k10temp.c

247

ret = read_ccd_temp_reg(data, channel - 2, &regval);

drivers/hwmon/k10temp.c

252

*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;

drivers/hwmon/k10temp.c

262

data->read_htcreg(data->pdev, &regval);

drivers/hwmon/k10temp.c

263

*val = ((regval >> 16) & 0x7f) * 500 + 52000;

drivers/hwmon/k10temp.c

266

data->read_htcreg(data->pdev, &regval);

drivers/hwmon/k10temp.c

267

*val = (((regval >> 16) & 0x7f)

drivers/hwmon/k10temp.c

268

- ((regval >> 24) & 0xf)) * 500 + 52000;

drivers/hwmon/k10temp.c

404

u32 regval;

drivers/hwmon/k10temp.c

418

if (read_ccd_temp_reg(data, i, &regval))

drivers/hwmon/k10temp.c

421

if (regval & ZEN_CCD_TEMP_VALID)

drivers/hwmon/lm75.c

383

unsigned int regval;

drivers/hwmon/lm75.c

413

err = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/lm75.c

421

*val = !!(regval & BIT(13)) == !!(regval & BIT(2));

drivers/hwmon/lm75.c

427

*val = lm75_reg_to_mc(regval, data->resolution);

drivers/hwmon/lm83.c

179

unsigned int regval;

drivers/hwmon/lm83.c

184

err = regmap_read(data->regmap, LM83_REG_TEMP[channel], &regval);

drivers/hwmon/lm83.c

187

*val = (s8)regval * 1000;

drivers/hwmon/lm83.c

190

err = regmap_read(data->regmap, LM83_REG_MAX[channel], &regval);

drivers/hwmon/lm83.c

193

*val = (s8)regval * 1000;

drivers/hwmon/lm83.c

196

err = regmap_read(data->regmap, LM83_REG_R_TCRIT, &regval);

drivers/hwmon/lm83.c

199

*val = (s8)regval * 1000;

drivers/hwmon/lm83.c

202

err = regmap_read(data->regmap, LM83_ALARM_REG[channel], &regval);

drivers/hwmon/lm83.c

205

*val = !!(regval & LM83_MAX_ALARM_BIT[channel]);

drivers/hwmon/lm83.c

208

err = regmap_read(data->regmap, LM83_ALARM_REG[channel], &regval);

drivers/hwmon/lm83.c

211

*val = !!(regval & LM83_CRIT_ALARM_BIT[channel]);

drivers/hwmon/lm83.c

214

err = regmap_read(data->regmap, LM83_ALARM_REG[channel], &regval);

drivers/hwmon/lm83.c

217

*val = !!(regval & LM83_FAULT_BIT[channel]);

drivers/hwmon/lm83.c

228

unsigned int regval;

drivers/hwmon/lm83.c

231

regval = DIV_ROUND_CLOSEST(clamp_val(val, -128000, 127000), 1000);

drivers/hwmon/lm83.c

235

err = regmap_write(data->regmap, LM83_REG_MAX[channel], regval);

drivers/hwmon/lm83.c

240

err = regmap_write(data->regmap, LM83_REG_R_TCRIT, regval);

drivers/hwmon/lm83.c

253

unsigned int regval;

drivers/hwmon/lm83.c

258

err = regmap_read(data->regmap, LM83_REG_R_STATUS1, &regval);

drivers/hwmon/lm83.c

261

*val = regval;

drivers/hwmon/lm83.c

262

err = regmap_read(data->regmap, LM83_REG_R_STATUS2, &regval);

drivers/hwmon/lm83.c

265

*val |= regval << 8;

drivers/hwmon/lm90.c

1340

static int lm90_temp_from_reg(u32 flags, u16 regval, u8 resolution)

drivers/hwmon/lm90.c

1345

val = regval - 0x4000;

drivers/hwmon/lm90.c

1347

val = regval;

drivers/hwmon/lm90.c

1349

val = (s16)regval;

drivers/hwmon/lm90.c

2219

int regval;

drivers/hwmon/lm90.c

2238

regval = i2c_smbus_read_byte_data(client, LM90_REG_STATUS);

drivers/hwmon/lm90.c

2239

if (regval < 0 || (regval & 0x2b))

drivers/hwmon/lm90.c

2243

if (i2c_smbus_read_byte_data(client, LM90_REG_CONVRATE) != regval ||

drivers/hwmon/lm90.c

2244

i2c_smbus_read_byte_data(client, LM90_REG_LOCAL_LOW) != regval ||

drivers/hwmon/lm90.c

2245

i2c_smbus_read_byte_data(client, LM90_REG_REMOTE_LOWH) != regval)

drivers/hwmon/lm92.c

299

int i, regval;

drivers/hwmon/lm92.c

310

regval = i2c_smbus_read_word_data(new_client, man_id_addr);

drivers/hwmon/lm92.c

311

if (regval != 0x0180)

drivers/hwmon/lm92.c

313

regval = i2c_smbus_read_byte_data(new_client, config_addr);

drivers/hwmon/lm92.c

314

if (regval < 0 || (regval & 0xe0))

drivers/hwmon/lm95234.c

171

u32 regval, mask;

drivers/hwmon/lm95234.c

176

ret = regmap_read(regmap, LM95234_REG_ENABLE, &regval);

drivers/hwmon/lm95234.c

179

*val = !!(regval & BIT(channel));

drivers/hwmon/lm95234.c

184

ret = regmap_read(regmap, lm95234_alarm_reg(channel), &regval);

drivers/hwmon/lm95234.c

187

*val = !!(regval & BIT(channel));

drivers/hwmon/lm95234.c

190

ret = regmap_read(regmap, LM95234_REG_STS_TCRIT1, &regval);

drivers/hwmon/lm95234.c

193

*val = !!(regval & BIT(channel));

drivers/hwmon/lm95234.c

198

ret = regmap_read(regmap, LM95234_REG_REM_MODEL, &regval);

drivers/hwmon/lm95234.c

201

*val = (regval & BIT(channel)) ? 1 : 2;

drivers/hwmon/lm95234.c

204

ret = regmap_read(regmap, LM95234_REG_OFFSET(channel - 1), &regval);

drivers/hwmon/lm95234.c

207

*val = sign_extend32(regval, 7) * 500;

drivers/hwmon/lm95234.c

210

ret = regmap_read(regmap, LM95234_REG_STS_FAULT, &regval);

drivers/hwmon/lm95234.c

214

*val = !!(regval & mask);

drivers/hwmon/lm95234.c

217

ret = regmap_read(regmap, lm95234_crit_reg(channel), &regval);

drivers/hwmon/lm95234.c

220

*val = regval * 1000;

drivers/hwmon/lm95234.c

225

ret = regmap_read(regmap, LM95234_REG_TCRIT1(channel), &regval);

drivers/hwmon/lm95234.c

228

*val = regval * 1000;

drivers/hwmon/lm95245.c

163

unsigned int regval;

drivers/hwmon/lm95245.c

193

&regval);

drivers/hwmon/lm95245.c

196

*val = regval * 1000;

drivers/hwmon/lm95245.c

201

ret = regmap_read(regmap, regs[0], &regval);

drivers/hwmon/lm95245.c

204

*val = regval * 1000;

drivers/hwmon/lm95245.c

225

ret = regmap_read(regmap, LM95245_REG_RW_CONFIG2, &regval);

drivers/hwmon/lm95245.c

228

*val = (regval & CFG2_REMOTE_TT) ? 1 : 2;

drivers/hwmon/lm95245.c

237

ret = regmap_read(regmap, LM95245_REG_R_STATUS1, &regval);

drivers/hwmon/lm95245.c

240

*val = !!(regval & STATUS1_ROS);

drivers/hwmon/lm95245.c

243

ret = regmap_read(regmap, LM95245_REG_R_STATUS1, &regval);

drivers/hwmon/lm95245.c

246

*val = !!(regval & (channel ? STATUS1_RTCRIT : STATUS1_LOC));

drivers/hwmon/lm95245.c

249

ret = regmap_read(regmap, LM95245_REG_R_STATUS1, &regval);

drivers/hwmon/lm95245.c

252

*val = !!(regval & STATUS1_DIODE_FAULT);

drivers/hwmon/lm95245.c

264

unsigned int regval;

drivers/hwmon/lm95245.c

281

&regval);

drivers/hwmon/lm95245.c

286

val = regval - val / 1000;

drivers/hwmon/ltc2945.c

265

long long regval;

drivers/hwmon/ltc2945.c

273

regval = ltc2945_val_to_reg(dev, reg, val);

drivers/hwmon/ltc2945.c

274

if (regval < 0)

drivers/hwmon/ltc2945.c

275

return regval;

drivers/hwmon/ltc2945.c

277

regval = clamp_val(regval, 0, 0xffffff);

drivers/hwmon/ltc2945.c

278

regbuf[0] = regval >> 16;

drivers/hwmon/ltc2945.c

279

regbuf[1] = (regval >> 8) & 0xff;

drivers/hwmon/ltc2945.c

280

regbuf[2] = regval;

drivers/hwmon/ltc2945.c

283

regval = clamp_val(regval, 0, 0xfff) << 4;

drivers/hwmon/ltc2945.c

284

regbuf[0] = regval >> 8;

drivers/hwmon/ltc2945.c

285

regbuf[1] = regval & 0xff;

drivers/hwmon/ltc4215.c

79

const u8 regval = data->regs[reg];

drivers/hwmon/ltc4215.c

85

voltage = regval * 151 / 1000;

drivers/hwmon/ltc4215.c

89

voltage = regval * 605 / 10;

drivers/hwmon/ltc4215.c

96

voltage = regval * 482 * 125 / 1000;

drivers/hwmon/ltc4245.c

166

const u8 regval = data->vregs[reg - 0x10];

drivers/hwmon/ltc4245.c

172

voltage = regval * 55;

drivers/hwmon/ltc4245.c

176

voltage = regval * 22;

drivers/hwmon/ltc4245.c

180

voltage = regval * 15;

drivers/hwmon/ltc4245.c

184

voltage = regval * -55;

drivers/hwmon/ltc4245.c

187

voltage = regval * 10;

drivers/hwmon/ltc4245.c

202

const u8 regval = data->vregs[reg - 0x10];

drivers/hwmon/ltc4245.c

223

voltage = regval * 250; /* voltage in uV */

drivers/hwmon/ltc4245.c

227

voltage = regval * 125; /* voltage in uV */

drivers/hwmon/ltc4245.c

231

voltage = regval * 125; /* voltage in uV */

drivers/hwmon/ltc4245.c

235

voltage = regval * 250; /* voltage in uV */

drivers/hwmon/ltc4245.c

288

int regval = data->gpios[channel - 8];

drivers/hwmon/ltc4245.c

290

if (regval < 0)

drivers/hwmon/ltc4245.c

291

return regval;

drivers/hwmon/ltc4245.c

292

*val = regval * 10;

drivers/hwmon/max1619.c

111

u32 regval;

drivers/hwmon/max1619.c

115

ret = regmap_read(regmap, MAX1619_REG_CONVRATE, &regval);

drivers/hwmon/max1619.c

118

*val = update_intervals[regval & 7];

drivers/hwmon/max1619.c

263

int regval;

drivers/hwmon/max1619.c

268

regval = i2c_smbus_read_byte_data(client, MAX1619_REG_CONFIG);

drivers/hwmon/max1619.c

269

if (regval < 0 || (regval & 0x03))

drivers/hwmon/max1619.c

271

regval = i2c_smbus_read_byte_data(client, MAX1619_REG_CONVRATE);

drivers/hwmon/max1619.c

272

if (regval < 0 || regval > 0x07)

drivers/hwmon/max1619.c

274

regval = i2c_smbus_read_byte_data(client, MAX1619_REG_STATUS);

drivers/hwmon/max1619.c

275

if (regval < 0 || (regval & 0x61))

drivers/hwmon/max1619.c

278

regval = i2c_smbus_read_byte_data(client, MAX1619_REG_MAN_ID);

drivers/hwmon/max1619.c

279

if (regval != 0x4d)

drivers/hwmon/max1619.c

281

regval = i2c_smbus_read_byte_data(client, MAX1619_REG_CHIP_ID);

drivers/hwmon/max1619.c

282

if (regval != 0x04)

drivers/hwmon/max1668.c

101

*val = !!(regval & BIT(8 - channel * 2));

drivers/hwmon/max1668.c

103

*val = !!(regval & BIT(6));

drivers/hwmon/max1668.c

61

u32 regval;

drivers/hwmon/max1668.c

66

ret = regmap_read(regmap, MAX1668_REG_TEMP(channel), &regval);

drivers/hwmon/max1668.c

69

*val = sign_extend32(regval, 7) * 1000;

drivers/hwmon/max1668.c

72

ret = regmap_read(regmap, MAX1668_REG_LIML(channel), &regval);

drivers/hwmon/max1668.c

75

*val = sign_extend32(regval, 7) * 1000;

drivers/hwmon/max1668.c

78

ret = regmap_read(regmap, MAX1668_REG_LIMH(channel), &regval);

drivers/hwmon/max1668.c

81

*val = sign_extend32(regval, 7) * 1000;

drivers/hwmon/max1668.c

86

&regval);

drivers/hwmon/max1668.c

90

*val = !!(regval & BIT(9 - channel * 2));

drivers/hwmon/max1668.c

92

*val = !!(regval & BIT(5));

drivers/hwmon/max1668.c

97

&regval);

drivers/hwmon/max31730.c

119

int regval, reg, offset;

drivers/hwmon/max31730.c

153

regval = i2c_smbus_read_byte_data(data->client,

drivers/hwmon/max31730.c

155

if (regval < 0)

drivers/hwmon/max31730.c

156

return regval;

drivers/hwmon/max31730.c

157

*val = !!(regval & BIT(channel));

drivers/hwmon/max31730.c

160

regval = i2c_smbus_read_byte_data(data->client,

drivers/hwmon/max31730.c

162

if (regval < 0)

drivers/hwmon/max31730.c

163

return regval;

drivers/hwmon/max31730.c

164

*val = !!(regval & BIT(channel));

drivers/hwmon/max31730.c

167

regval = i2c_smbus_read_byte_data(data->client,

drivers/hwmon/max31730.c

169

if (regval < 0)

drivers/hwmon/max31730.c

170

return regval;

drivers/hwmon/max31730.c

171

*val = !!(regval & BIT(channel));

drivers/hwmon/max31730.c

176

regval = i2c_smbus_read_word_swapped(data->client, reg);

drivers/hwmon/max31730.c

177

if (regval < 0)

drivers/hwmon/max31730.c

178

return regval;

drivers/hwmon/max31730.c

180

*val = max31730_reg_to_mc(regval);

drivers/hwmon/max31730.c

364

int regval;

drivers/hwmon/max31730.c

366

regval = i2c_smbus_read_byte_data(client, reg + 1);

drivers/hwmon/max31730.c

367

return regval < 0 || (regval & 0x0f);

drivers/hwmon/max31730.c

375

int regval;

drivers/hwmon/max31730.c

382

regval = i2c_smbus_read_byte_data(client, MAX31730_REG_MFG_ID);

drivers/hwmon/max31730.c

383

if (regval != MAX31730_MFG_ID)

drivers/hwmon/max31730.c

385

regval = i2c_smbus_read_byte_data(client, MAX31730_REG_MFG_REV);

drivers/hwmon/max31730.c

386

if (regval != MAX31730_MFG_REV)

drivers/hwmon/max31730.c

84

u8 regval = *confdata;

drivers/hwmon/max31730.c

88

regval |= BIT(channel);

drivers/hwmon/max31730.c

90

regval &= ~BIT(channel);

drivers/hwmon/max31730.c

92

if (regval != *confdata) {

drivers/hwmon/max31730.c

93

err = i2c_smbus_write_byte_data(client, reg, regval);

drivers/hwmon/max31730.c

96

*confdata = regval;

drivers/hwmon/max31760.c

104

*val = FIELD_GET(STATUS_ALARM_MAX(1), regval);

drivers/hwmon/max31760.c

106

*val = FIELD_GET(STATUS_ALARM_MAX(0), regval);

drivers/hwmon/max31760.c

110

ret = regmap_read(state->regmap, REG_STATUS, &regval);

drivers/hwmon/max31760.c

115

*val = FIELD_GET(STATUS_ALARM_CRIT(1), regval);

drivers/hwmon/max31760.c

117

*val = FIELD_GET(STATUS_ALARM_CRIT(0), regval);

drivers/hwmon/max31760.c

153

ret = regmap_read(state->regmap, REG_STATUS, &regval);

drivers/hwmon/max31760.c

158

*val = FIELD_GET(BIT(1), regval);

drivers/hwmon/max31760.c

160

*val = FIELD_GET(BIT(0), regval);

drivers/hwmon/max31760.c

164

ret = regmap_read(state->regmap, REG_CR3, &regval);

drivers/hwmon/max31760.c

169

*val = FIELD_GET(BIT(1), regval);

drivers/hwmon/max31760.c

171

*val = FIELD_GET(BIT(0), regval);

drivers/hwmon/max31760.c

180

ret = regmap_read(state->regmap, REG_PWMV, &regval);

drivers/hwmon/max31760.c

184

*val = regval;

drivers/hwmon/max31760.c

188

ret = regmap_read(state->regmap, REG_CR1, &regval);

drivers/hwmon/max31760.c

192

regval = FIELD_GET(CR1_DRV, regval);

drivers/hwmon/max31760.c

193

if (regval >= ARRAY_SIZE(max31760_pwm_freq))

drivers/hwmon/max31760.c

196

*val = max31760_pwm_freq[regval];

drivers/hwmon/max31760.c

200

ret = regmap_read(state->regmap, REG_CR2, &regval);

drivers/hwmon/max31760.c

204

*val = 2 - FIELD_GET(CR2_DFC, regval);

drivers/hwmon/max31760.c

208

ret = regmap_read(state->regmap, REG_CR1, &regval);

drivers/hwmon/max31760.c

212

switch (FIELD_GET(CR1_TEMP_SRC, regval)) {

drivers/hwmon/max31760.c

417

unsigned int regval;

drivers/hwmon/max31760.c

419

ret = regmap_read(state->regmap, REG_LUT(sda->index), &regval);

drivers/hwmon/max31760.c

423

return sysfs_emit(buf, "%d\n", regval);

drivers/hwmon/max31760.c

451

unsigned int regval;

drivers/hwmon/max31760.c

454

ret = regmap_read(state->regmap, REG_CR1, &regval);

drivers/hwmon/max31760.c

458

return sysfs_emit(buf, "%d\n", (1 + (int)FIELD_GET(CR1_HYST, regval)) * 2000);

drivers/hwmon/max31760.c

81

unsigned int regval;

drivers/hwmon/max31760.c

91

ret = regmap_read(state->regmap, REG_STATUS, &regval);

drivers/hwmon/max31760.c

95

*val = FIELD_GET(STATUS_RDFA, regval);

drivers/hwmon/max31760.c

99

ret = regmap_read(state->regmap, REG_STATUS, &regval);

drivers/hwmon/max6621.c

167

static int max6621_verify_reg_data(struct device *dev, int regval)

drivers/hwmon/max6621.c

169

if (regval >= MAX6621_PECI_ERR_MIN &&

drivers/hwmon/max6621.c

170

regval <= MAX6621_PECI_ERR_MAX) {

drivers/hwmon/max6621.c

172

regval);

drivers/hwmon/max6621.c

177

switch (regval) {

drivers/hwmon/max6621.c

180

regval);

drivers/hwmon/max6621.c

183

dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval);

drivers/hwmon/max6621.c

187

regval);

drivers/hwmon/max6621.c

190

dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval);

drivers/hwmon/max6621.c

193

dev_dbg(dev, "No alert active - err 0x%04x.\n", regval);

drivers/hwmon/max6621.c

205

u32 regval;

drivers/hwmon/max6621.c

215

ret = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/max6621.c

219

ret = max6621_verify_reg_data(dev, regval);

drivers/hwmon/max6621.c

228

temp = (regval >> MAX6621_REG_TEMP_SHIFT);

drivers/hwmon/max6621.c

234

&regval);

drivers/hwmon/max6621.c

238

ret = max6621_verify_reg_data(dev, regval);

drivers/hwmon/max6621.c

242

*val = (regval >> MAX6621_REG_TEMP_SHIFT) *

drivers/hwmon/max6621.c

249

ret = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/max6621.c

253

ret = max6621_verify_reg_data(dev, regval);

drivers/hwmon/max6621.c

257

*val = regval * 1000L;

drivers/hwmon/max6621.c

270

&regval);

drivers/hwmon/max6621.c

274

ret = max6621_verify_reg_data(dev, regval);

drivers/hwmon/max6621.c

277

if (regval == MAX6621_ALERT_DIS)

drivers/hwmon/max6621.c

287

if (regval) {

drivers/hwmon/max6621.c

294

*val = !!regval;

drivers/hwmon/max6697.c

196

u32 regval;

drivers/hwmon/max6697.c

208

ret = regmap_read(regmap, MAX6697_REG_MAX[channel], &regval);

drivers/hwmon/max6697.c

211

*val = ((int)regval - data->temp_offset) * 1000;

drivers/hwmon/max6697.c

214

ret = regmap_read(regmap, MAX6697_REG_CRIT[channel], &regval);

drivers/hwmon/max6697.c

217

*val = ((int)regval - data->temp_offset) * 1000;

drivers/hwmon/max6697.c

220

ret = regmap_read(regmap, MAX6697_REG_MIN, &regval);

drivers/hwmon/max6697.c

223

*val = ((int)regval - data->temp_offset) * 1000;

drivers/hwmon/max6697.c

236

ret = regmap_read(regmap, MAX6697_REG_STAT_FAULT, &regval);

drivers/hwmon/max6697.c

240

*val = !!(regval & BIT(channel - 1));

drivers/hwmon/max6697.c

242

*val = !!(regval & BIT(channel));

drivers/hwmon/max6697.c

245

ret = regmap_read(regmap, MAX6697_REG_STAT_CRIT, &regval);

drivers/hwmon/max6697.c

258

*val = !!(regval & BIT(channel ? channel - 1 : 7));

drivers/hwmon/max6697.c

261

ret = regmap_read(regmap, MAX6697_REG_STAT_ALARM, &regval);

drivers/hwmon/max6697.c

264

*val = !!(regval & BIT(max6697_alarm_channel_map(channel)));

drivers/hwmon/max6697.c

267

ret = regmap_read(regmap, MAX6697_REG_STAT_MIN_ALARM, &regval);

drivers/hwmon/max6697.c

270

*val = !!(regval & BIT(max6697_alarm_channel_map(channel)));

drivers/hwmon/max77705-hwmon.c

55

u32 regval;

drivers/hwmon/max77705-hwmon.c

57

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/max77705-hwmon.c

62

*val = mult_frac((long)sign_extend32(regval, 15), res, 1000000);

drivers/hwmon/max77705-hwmon.c

64

*val = mult_frac((long)regval, res, 1000000);

drivers/hwmon/mlxreg-fan.c

128

u32 regval;

drivers/hwmon/mlxreg-fan.c

141

err = regmap_read(fan->regmap, tacho->prsnt, &regval);

drivers/hwmon/mlxreg-fan.c

151

regval) {

drivers/hwmon/mlxreg-fan.c

158

err = regmap_read(fan->regmap, tacho->reg, &regval);

drivers/hwmon/mlxreg-fan.c

162

if (MLXREG_FAN_GET_FAULT(regval, tacho->mask)) {

drivers/hwmon/mlxreg-fan.c

168

*val = MLXREG_FAN_GET_RPM(regval, fan->divider,

drivers/hwmon/mlxreg-fan.c

173

err = regmap_read(fan->regmap, tacho->reg, &regval);

drivers/hwmon/mlxreg-fan.c

177

*val = MLXREG_FAN_GET_FAULT(regval, tacho->mask);

drivers/hwmon/mlxreg-fan.c

189

err = regmap_read(fan->regmap, pwm->reg, &regval);

drivers/hwmon/mlxreg-fan.c

193

*val = regval;

drivers/hwmon/mlxreg-fan.c

351

u32 regval;

drivers/hwmon/mlxreg-fan.c

354

err = regmap_read(fan->regmap, pwm->reg, &regval);

drivers/hwmon/mlxreg-fan.c

360

*state = MLXREG_FAN_PWM_DUTY2STATE(regval);

drivers/hwmon/mlxreg-fan.c

405

u32 regval;

drivers/hwmon/mlxreg-fan.c

408

err = regmap_read(fan->regmap, data->capability, &regval);

drivers/hwmon/mlxreg-fan.c

415

return data->slot ? (data->slot <= regval ? 1 : 0) : !!(regval & data->bit);

drivers/hwmon/mlxreg-fan.c

421

u32 regval;

drivers/hwmon/mlxreg-fan.c

424

err = regmap_read(fan->regmap, data->reg, &regval);

drivers/hwmon/mlxreg-fan.c

431

return regval != MLXREG_FAN_PWM_NOT_CONNECTED;

drivers/hwmon/mlxreg-fan.c

437

u32 regval;

drivers/hwmon/mlxreg-fan.c

440

err = regmap_read(fan->regmap, data->capability, &regval);

drivers/hwmon/mlxreg-fan.c

453

if (regval > 0 && regval <= MLXREG_FAN_TACHO_DIV_SCALE_MAX)

drivers/hwmon/mlxreg-fan.c

454

fan->divider = regval * MLXREG_FAN_TACHO_DIV_MIN;

drivers/hwmon/mlxreg-fan.c

542

u32 regval;

drivers/hwmon/mlxreg-fan.c

545

err = regmap_read(fan->regmap, pdata->capability, &regval);

drivers/hwmon/mlxreg-fan.c

558

drwr_avail = regval;

drivers/hwmon/mlxreg-fan.c

560

drwr_avail = hweight32(regval);

drivers/hwmon/nct7363.c

112

u8 regval[2];

drivers/hwmon/nct7363.c

122

regval[0] = val >> 5;

drivers/hwmon/nct7363.c

123

regval[1] = val & NCT7363_FANINX_LVAL_MASK;

drivers/hwmon/nct7363.c

127

regval, 2);

drivers/hwmon/nct7363.c

159

unsigned int regval;

drivers/hwmon/nct7363.c

165

NCT7363_REG_FSCPXDUTY(channel), &regval);

drivers/hwmon/nct7363.c

169

*val = (long)regval;

drivers/hwmon/nct7363.c

66

u8 regval[2];

drivers/hwmon/nct7363.c

78

&regval, 2);

drivers/hwmon/nct7363.c

82

cnt = (regval[0] << 5) | (regval[1] & NCT7363_FANINX_LVAL_MASK);

drivers/hwmon/nct7363.c

88

&regval, 2);

drivers/hwmon/nct7363.c

92

cnt = (regval[0] << 5) | (regval[1] & NCT7363_FANINX_LVAL_MASK);

drivers/hwmon/nct7802.c

125

unsigned int regval;

drivers/hwmon/nct7802.c

131

ret = regmap_read(data->regmap, 0x5E, &regval);

drivers/hwmon/nct7802.c

135

return sprintf(buf, "%u\n", !(regval & (1 << sattr->index)));

drivers/hwmon/nct7802.c

535

unsigned int regval;

drivers/hwmon/nct7802.c

538

err = regmap_read(data->regmap, sattr->nr, &regval);

drivers/hwmon/nct7802.c

542

return sprintf(buf, "%u\n", !!(regval & (1 << sattr->index)));

drivers/hwmon/pmbus/pmbus_core.c

1124

u16 regval;

drivers/hwmon/pmbus/pmbus_core.c

1131

regval = pmbus_data2reg_direct(data, sensor, val);

drivers/hwmon/pmbus/pmbus_core.c

1134

regval = pmbus_data2reg_vid(data, sensor, val);

drivers/hwmon/pmbus/pmbus_core.c

1137

regval = pmbus_data2reg_ieee754(data, sensor, val);

drivers/hwmon/pmbus/pmbus_core.c

1141

regval = pmbus_data2reg_linear(data, sensor, val);

drivers/hwmon/pmbus/pmbus_core.c

1144

return regval;

drivers/hwmon/pmbus/pmbus_core.c

1180

u16 regval;

drivers/hwmon/pmbus/pmbus_core.c

1193

regval = status & mask;

drivers/hwmon/pmbus/pmbus_core.c

1194

if (regval) {

drivers/hwmon/pmbus/pmbus_core.c

1196

ret = _pmbus_write_byte_data(client, page, reg, regval);

drivers/hwmon/pmbus/pmbus_core.c

1213

ret = !!(regval && v1 >= v2);

drivers/hwmon/pmbus/pmbus_core.c

1215

ret = !!regval;

drivers/hwmon/pmbus/pmbus_core.c

1267

u16 regval;

drivers/hwmon/pmbus/pmbus_core.c

1274

regval = pmbus_data2reg(data, sensor, val);

drivers/hwmon/pmbus/pmbus_core.c

1275

ret = _pmbus_write_word_data(client, sensor->page, sensor->reg, regval);

drivers/hwmon/pmbus/pmbus_core.c

2328

int regval;

drivers/hwmon/pmbus/pmbus_core.c

2342

regval = _pmbus_read_byte_data(client, page,

drivers/hwmon/pmbus/pmbus_core.c

2344

if (regval < 0 ||

drivers/hwmon/pmbus/pmbus_core.c

2345

(!(regval & (PB_FAN_1_INSTALLED >> ((f & 1) * 4)))))

drivers/hwmon/pmbus/pmbus_core.c

2357

page, f, regval);

drivers/hwmon/spd5118.c

102

u8 regval[2];

drivers/hwmon/spd5118.c

125

err = regmap_bulk_read(regmap, reg, regval, 2);

drivers/hwmon/spd5118.c

129

temp = (regval[1] << 8) | regval[0];

drivers/hwmon/spd5118.c

137

unsigned int mask, regval;

drivers/hwmon/spd5118.c

157

err = regmap_read(regmap, SPD5118_REG_TEMP_STATUS, &regval);

drivers/hwmon/spd5118.c

160

*val = !!(regval & mask);

drivers/hwmon/spd5118.c

168

u32 regval;

drivers/hwmon/spd5118.c

171

err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, &regval);

drivers/hwmon/spd5118.c

174

*val = !(regval & SPD5118_TS_DISABLE);

drivers/hwmon/spd5118.c

207

u8 regval[2];

drivers/hwmon/spd5118.c

229

regval[0] = temp & 0xff;

drivers/hwmon/spd5118.c

230

regval[1] = temp >> 8;

drivers/hwmon/spd5118.c

232

return regmap_bulk_write(regmap, reg, regval, 2);

drivers/hwmon/spd5118.c

489

u32 regval;

drivers/hwmon/spd5118.c

496

err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, &regval);

drivers/hwmon/spd5118.c

589

int regval;

drivers/hwmon/spd5118.c

595

regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE);

drivers/hwmon/spd5118.c

596

if (regval != 0x5118)

drivers/hwmon/spd5118.c

599

regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR);

drivers/hwmon/spd5118.c

600

if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8))

drivers/hwmon/spd5118.c

603

regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY);

drivers/hwmon/spd5118.c

604

if (regval < 0)

drivers/hwmon/spd5118.c

606

if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc))

drivers/hwmon/spd5118.c

609

regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR);

drivers/hwmon/spd5118.c

610

if (regval)

drivers/hwmon/spd5118.c

612

regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR);

drivers/hwmon/spd5118.c

613

if (regval)

drivers/hwmon/spd5118.c

616

regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION);

drivers/hwmon/spd5118.c

617

if (regval < 0 || (regval & 0xc1))

drivers/hwmon/spd5118.c

620

regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG);

drivers/hwmon/spd5118.c

621

if (regval < 0)

drivers/hwmon/spd5118.c

623

if (regval & ~SPD5118_TS_DISABLE)

drivers/hwmon/spd5118.c

633

int err, regval, mode;

drivers/hwmon/spd5118.c

639

regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE);

drivers/hwmon/spd5118.c

640

if (regval < 0 || (regval && regval != 0x5118))

drivers/hwmon/spd5118.c

650

if (!regval) {

drivers/hwmon/spd5118.c

652

regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR);

drivers/hwmon/spd5118.c

653

if (regval)

drivers/hwmon/spd5118.c

672

regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE);

drivers/hwmon/spd5118.c

673

if (regval != 0x5118) {

drivers/hwmon/tmp102.c

103

unsigned int regval;

drivers/hwmon/tmp102.c

125

err = regmap_read(tmp102->regmap, reg, &regval);

drivers/hwmon/tmp102.c

129

*val = tmp102_reg_to_mC(regval);

drivers/hwmon/tmp102.c

298

unsigned int regval;

drivers/hwmon/tmp102.c

326

err = regmap_read(tmp102->regmap, TMP102_CONF_REG, &regval);

drivers/hwmon/tmp102.c

332

if ((regval & ~TMP102_CONFREG_MASK) !=

drivers/hwmon/tmp102.c

338

tmp102->config_orig = regval;

drivers/hwmon/tmp102.c

344

regval &= ~TMP102_CONFIG_CLEAR;

drivers/hwmon/tmp102.c

345

regval |= TMP102_CONFIG_SET;

drivers/hwmon/tmp102.c

347

err = regmap_write(tmp102->regmap, TMP102_CONF_REG, regval);

drivers/hwmon/tmp103.c

55

unsigned int regval;

drivers/hwmon/tmp103.c

72

err = regmap_read(regmap, reg, &regval);

drivers/hwmon/tmp103.c

76

*temp = tmp103_reg_to_mc(regval);

drivers/hwmon/tmp108.c

122

unsigned int regval;

drivers/hwmon/tmp108.c

128

&regval);

drivers/hwmon/tmp108.c

132

regval)];

drivers/hwmon/tmp108.c

146

err = regmap_read(tmp108->regmap, TMP108_REG_TEMP, &regval);

drivers/hwmon/tmp108.c

149

*temp = tmp108_temp_reg_to_mC(regval);

drivers/hwmon/tmp108.c

154

TMP108_REG_TLOW : TMP108_REG_THIGH, &regval);

drivers/hwmon/tmp108.c

157

*temp = tmp108_temp_reg_to_mC(regval);

drivers/hwmon/tmp108.c

161

err = regmap_read(tmp108->regmap, TMP108_REG_CONF, &regval);

drivers/hwmon/tmp108.c

164

*temp = !!(regval & (attr == hwmon_temp_min_alarm ?

drivers/hwmon/tmp108.c

169

err = regmap_read(tmp108->regmap, TMP108_REG_CONF, &regval);

drivers/hwmon/tmp108.c

172

switch (regval & TMP108_CONF_HYSTERESIS_MASK) {

drivers/hwmon/tmp108.c

188

TMP108_REG_TLOW : TMP108_REG_THIGH, &regval);

drivers/hwmon/tmp108.c

191

*temp = tmp108_temp_reg_to_mC(regval);

drivers/hwmon/tmp108.c

208

u32 regval, mask;

drivers/hwmon/tmp108.c

239

&regval);

drivers/hwmon/tmp108.c

243

temp -= tmp108_temp_reg_to_mC(regval);

drivers/hwmon/tmp108.c

245

temp = tmp108_temp_reg_to_mC(regval) - temp;

drivers/hwmon/tmp401.c

145

int regval;

drivers/hwmon/tmp401.c

164

regval = i2c_smbus_read_word_swapped(client, reg);

drivers/hwmon/tmp401.c

165

if (regval < 0)

drivers/hwmon/tmp401.c

166

return regval;

drivers/hwmon/tmp401.c

167

*val = regval;

drivers/hwmon/tmp401.c

172

regval = i2c_smbus_read_byte_data(client, reg);

drivers/hwmon/tmp401.c

173

if (regval < 0)

drivers/hwmon/tmp401.c

174

return regval;

drivers/hwmon/tmp401.c

175

*val = regval << 8;

drivers/hwmon/tmp401.c

180

regval = i2c_smbus_read_byte_data(client, reg);

drivers/hwmon/tmp401.c

181

if (regval < 0)

drivers/hwmon/tmp401.c

182

return regval;

drivers/hwmon/tmp401.c

183

*val = regval;

drivers/hwmon/tmp401.c

187

regval = i2c_smbus_read_byte_data(client, TMP401_STATUS);

drivers/hwmon/tmp401.c

188

if (regval < 0)

drivers/hwmon/tmp401.c

189

return regval;

drivers/hwmon/tmp401.c

193

if (regval & TMP401_STATUS_REMOTE_OPEN)

drivers/hwmon/tmp401.c

197

if (regval & TMP401_STATUS_LOCAL_HIGH)

drivers/hwmon/tmp401.c

199

if (regval & TMP401_STATUS_REMOTE_HIGH)

drivers/hwmon/tmp401.c

203

if (regval & TMP401_STATUS_LOCAL_LOW)

drivers/hwmon/tmp401.c

205

if (regval & TMP401_STATUS_REMOTE_LOW)

drivers/hwmon/tmp401.c

209

if (regval & TMP401_STATUS_LOCAL_CRIT)

drivers/hwmon/tmp401.c

211

if (regval & TMP401_STATUS_REMOTE_CRIT)

drivers/hwmon/tmp401.c

217

regval = i2c_smbus_read_byte_data(client, reg);

drivers/hwmon/tmp401.c

218

if (regval < 0)

drivers/hwmon/tmp401.c

219

return regval;

drivers/hwmon/tmp401.c

220

*val = regval;

drivers/hwmon/tmp401.c

310

unsigned int regval;

drivers/hwmon/tmp401.c

322

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tmp401.c

325

*val = tmp401_register_to_temp(regval, data->extended_range);

drivers/hwmon/tmp401.c

339

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tmp401.c

342

*val = !!(regval & BIT(channel));

drivers/hwmon/tmp401.c

355

unsigned int regval;

drivers/hwmon/tmp401.c

363

regval = tmp401_temp_to_register(val, data->extended_range,

drivers/hwmon/tmp401.c

365

ret = regmap_write(regmap, reg, regval);

drivers/hwmon/tmp401.c

374

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tmp401.c

377

temp = tmp401_register_to_temp(regval, data->extended_range);

drivers/hwmon/tmp401.c

379

regval = ((temp - val) + 500) / 1000;

drivers/hwmon/tmp401.c

380

ret = regmap_write(regmap, TMP401_TEMP_CRIT_HYST, regval);

drivers/hwmon/tmp401.c

392

u32 regval;

drivers/hwmon/tmp401.c

397

ret = regmap_read(data->regmap, TMP401_CONVERSION_RATE, &regval);

drivers/hwmon/tmp401.c

400

*val = (1 << (7 - min(regval, 7))) * 125;

drivers/hwmon/tmp464.c

149

unsigned int regval;

drivers/hwmon/tmp464.c

155

err = regmap_read(regmap, TMP464_THERM_STATUS_REG, &regval);

drivers/hwmon/tmp464.c

158

*val = !!(regval & BIT(channel + 7));

drivers/hwmon/tmp464.c

161

err = regmap_read(regmap, TMP464_THERM2_STATUS_REG, &regval);

drivers/hwmon/tmp464.c

164

*val = !!(regval & BIT(channel + 7));

drivers/hwmon/tmp464.c

175

err = regmap_read(regmap, TMP464_REMOTE_OPEN_REG, &regval);

drivers/hwmon/tmp464.c

178

data->open_reg = regval;

drivers/hwmon/tmp464.c

193

err = regmap_read(regmap, TMP464_THERM_LIMIT[channel], &regval);

drivers/hwmon/tmp464.c

196

*val = temp_from_reg(regval);

drivers/hwmon/tmp464.c

207

err = regmap_read(regmap, TMP464_THERM2_LIMIT[channel], &regval);

drivers/hwmon/tmp464.c

210

*val = temp_from_reg(regval);

drivers/hwmon/tmp464.c

213

err = regmap_read(regmap, TMP464_TEMP_OFFSET_REG(channel), &regval);

drivers/hwmon/tmp464.c

216

*val = temp_from_reg(regval);

drivers/hwmon/tmp464.c

223

err = regmap_read(regmap, TMP464_TEMP_REG(channel), &regval);

drivers/hwmon/tmp464.c

226

*val = temp_from_reg(regval);

drivers/hwmon/tmp464.c

300

unsigned int regval;

drivers/hwmon/tmp464.c

305

err = regmap_read(regmap, TMP464_THERM_LIMIT[0], &regval);

drivers/hwmon/tmp464.c

309

val = clamp_val(temp_from_reg(regval) - val, 0, 255000);

drivers/hwmon/tmp464.c

418

unsigned int regval;

drivers/hwmon/tmp464.c

421

err = regmap_read(regmap, TMP464_LOCK_REG, &regval);

drivers/hwmon/tmp464.c

424

if (regval == TMP464_LOCKED) {

drivers/hwmon/tmp464.c

435

err = regmap_read(regmap, TMP464_CONFIG_REG, &regval);

drivers/hwmon/tmp464.c

438

data->config_orig = regval;

drivers/hwmon/tmp513.c

192

unsigned int regval, long *val)

drivers/hwmon/tmp513.c

196

*val = (regval >> pos) & 1;

drivers/hwmon/tmp513.c

207

*val = sign_extend32(regval,

drivers/hwmon/tmp513.c

217

*val = (regval >> TMP51X_BUS_VOLTAGE_SHIFT) * 4;

drivers/hwmon/tmp513.c

222

*val = regval * data->pwr_lsb_uw;

drivers/hwmon/tmp513.c

226

*val = sign_extend32(regval, 15) * (long)data->curr_lsb_ua;

drivers/hwmon/tmp513.c

238

*val = sign_extend32(regval, 15) >> TMP51X_TEMP_SHIFT;

drivers/hwmon/tmp513.c

243

*val = (regval & TMP51X_HYST_MASK) * 500;

drivers/hwmon/tmp513.c

257

int regval, max_val;

drivers/hwmon/tmp513.c

269

regval = clamp_val(val, -max_val, max_val);

drivers/hwmon/tmp513.c

278

regval = val << TMP51X_BUS_VOLTAGE_SHIFT;

drivers/hwmon/tmp513.c

281

regval = clamp_val(DIV_ROUND_CLOSEST(val, data->pwr_lsb_uw), 0,

drivers/hwmon/tmp513.c

290

regval = DIV_ROUND_CLOSEST(val * 10, 625) << TMP51X_TEMP_SHIFT;

drivers/hwmon/tmp513.c

295

regval = DIV_ROUND_CLOSEST(val, 500);

drivers/hwmon/tmp513.c

305

return regmap_write(data->regmap, reg, regval);

drivers/hwmon/tmp513.c

307

return regmap_update_bits(data->regmap, reg, mask, regval);

drivers/hwmon/tmp513.c

412

u32 regval;

drivers/hwmon/tmp513.c

422

ret = regmap_read(data->regmap, reg, &regval);

drivers/hwmon/tmp513.c

426

return tmp51x_get_value(data, reg, pos, regval, val);

drivers/hwmon/tmp513.c

577

unsigned int regval;

drivers/hwmon/tmp513.c

610

return regmap_read(data->regmap, TMP51X_STATUS, &regval);

drivers/hwmon/tps23861.c

127

unsigned int regval;

drivers/hwmon/tps23861.c

130

err = regmap_read(data->regmap, TEMPERATURE, &regval);

drivers/hwmon/tps23861.c

134

*val = ((long)regval * TEMPERATURE_LSB) - 20000;

drivers/hwmon/tps23861.c

142

__le16 regval;

drivers/hwmon/tps23861.c

149

&regval, 2);

drivers/hwmon/tps23861.c

153

&regval, 2);

drivers/hwmon/tps23861.c

158

raw_val = le16_to_cpu(regval);

drivers/hwmon/tps23861.c

168

__le16 regval;

drivers/hwmon/tps23861.c

179

&regval, 2);

drivers/hwmon/tps23861.c

183

raw_val = le16_to_cpu(regval);

drivers/hwmon/tps23861.c

191

unsigned int regval = 0;

drivers/hwmon/tps23861.c

194

regval |= BIT(channel + 4);

drivers/hwmon/tps23861.c

195

err = regmap_write(data->regmap, POWER_ENABLE, regval);

drivers/hwmon/tps23861.c

202

unsigned int regval = 0;

drivers/hwmon/tps23861.c

205

regval |= BIT(channel);

drivers/hwmon/tps23861.c

206

regval |= BIT(channel + 4);

drivers/hwmon/tps23861.c

207

err = regmap_write(data->regmap, DETECT_CLASS_RESTART, regval);

drivers/hwmon/tps23861.c

460

__le16 regval;

drivers/hwmon/tps23861.c

464

&regval,

drivers/hwmon/tps23861.c

467

raw_val = le16_to_cpu(regval);

drivers/hwmon/tsc1641.c

206

u32 regval;

drivers/hwmon/tsc1641.c

211

ret = regmap_read(data->regmap, TSC1641_CONFIG, &regval);

drivers/hwmon/tsc1641.c

215

*val = tsc1641_reg_to_upd_interval(regval);

drivers/hwmon/tsc1641.c

224

unsigned int regval;

drivers/hwmon/tsc1641.c

227

ret = regmap_read_bypassed(regmap, TSC1641_FLAG, &regval);

drivers/hwmon/tsc1641.c

231

*val = !!(regval & flag);

drivers/hwmon/tsc1641.c

239

unsigned int regval;

drivers/hwmon/tsc1641.c

261

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tsc1641.c

268

if (regval & 0x8000)

drivers/hwmon/tsc1641.c

275

if (sat_flag && (regval == 0x7FFF || !regval))

drivers/hwmon/tsc1641.c

279

*val = regval * TSC1641_VLOAD_LSB_MVOLT;

drivers/hwmon/tsc1641.c

288

int regval;

drivers/hwmon/tsc1641.c

316

ret = regmap_read(regmap, TSC1641_SHUNT_VOLTAGE, &regval);

drivers/hwmon/tsc1641.c

324

if (sat_flag && (regval == 0x7FFF || regval == 0x8000))

drivers/hwmon/tsc1641.c

328

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tsc1641.c

333

*val = DIV_ROUND_CLOSEST((s16)regval * data->current_lsb_ua, 1000);

drivers/hwmon/tsc1641.c

341

unsigned int regval;

drivers/hwmon/tsc1641.c

357

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tsc1641.c

361

*val = regval * TSC1641_POWER_LSB_UWATT;

drivers/hwmon/tsc1641.c

369

unsigned int regval;

drivers/hwmon/tsc1641.c

385

ret = regmap_read(regmap, reg, &regval);

drivers/hwmon/tsc1641.c

390

if (reg == TSC1641_TEMP && regval == 0x8000)

drivers/hwmon/tsc1641.c

394

*val = (s16)regval * TSC1641_TEMP_LSB_MDEGC;

drivers/hwmon/tsc1641.c

402

unsigned int regval;

drivers/hwmon/tsc1641.c

417

regval = DIV_ROUND_CLOSEST(val, TSC1641_VLOAD_LSB_MVOLT);

drivers/hwmon/tsc1641.c

419

return regmap_write(regmap, reg, regval);

drivers/hwmon/tsc1641.c

426

int reg, regval;

drivers/hwmon/tsc1641.c

442

regval = DIV_ROUND_CLOSEST(val * 1000, data->current_lsb_ua);

drivers/hwmon/tsc1641.c

448

regval = clamp_val(regval, SHRT_MIN, SHRT_MAX);

drivers/hwmon/tsc1641.c

450

return regmap_write(regmap, reg, regval & 0xFFFF);

drivers/hwmon/tsc1641.c

457

unsigned int regval;

drivers/hwmon/tsc1641.c

463

regval = DIV_ROUND_CLOSEST(val, TSC1641_POWER_LSB_UWATT);

drivers/hwmon/tsc1641.c

464

return regmap_write(regmap, TSC1641_POL, regval);

drivers/hwmon/tsc1641.c

474

int regval;

drivers/hwmon/tsc1641.c

481

regval = DIV_ROUND_CLOSEST(val, TSC1641_TEMP_LSB_MDEGC);

drivers/hwmon/tsc1641.c

483

return regmap_write(regmap, TSC1641_TOL, regval & 0xFFFF);

drivers/hwmon/w83627ehf.c

1294

int fan3pin, fan4pin, fan5pin, regval;

drivers/hwmon/w83627ehf.c

1325

regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);

drivers/hwmon/w83627ehf.c

1326

if ((regval & (1 << 2)) && fan4pin) {

drivers/hwmon/w83627ehf.c

1330

if (!(regval & (1 << 1)) && fan5pin) {

drivers/hwmon/w83773g.c

101

*val = (regval & 0x04) >> 2;

drivers/hwmon/w83773g.c

144

unsigned int regval;

drivers/hwmon/w83773g.c

147

ret = regmap_read(regmap, W83773_CONVERSION_RATE_REG_READ, &regval);

drivers/hwmon/w83773g.c

151

*val = 16000 >> regval;

drivers/hwmon/w83773g.c

63

unsigned int regval;

drivers/hwmon/w83773g.c

66

ret = regmap_read(regmap, W83773_LOCAL_TEMP, &regval);

drivers/hwmon/w83773g.c

70

*val = temp_of_local(regval);

drivers/hwmon/w83773g.c

94

unsigned int regval;

drivers/hwmon/w83773g.c

97

ret = regmap_read(regmap, W83773_STATUS[index], &regval);

drivers/i2c/busses/i2c-brcmstb.c

273

u32 regval = dev->bsc_regmap->iic_enable;

drivers/i2c/busses/i2c-brcmstb.c

275

dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;

drivers/i2c/busses/i2c-cadence.c

912

u32 regval;

drivers/i2c/busses/i2c-cadence.c

917

regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

918

regval &= ~CDNS_I2C_CR_HOLD;

drivers/i2c/busses/i2c-cadence.c

919

regval |= CDNS_I2C_CR_CLR_FIFO;

drivers/i2c/busses/i2c-cadence.c

920

cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

924

regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

925

cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

927

regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);

drivers/i2c/busses/i2c-cadence.c

928

cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);

drivers/i2c/busses/i2c-imx.c

577

unsigned int regval;

drivers/i2c/busses/i2c-imx.c

589

readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);

drivers/i2c/busses/i2c-imx.c

590

i2c_imx->i2csr = regval;

drivers/i2c/busses/i2c-jz4780.c

185

unsigned short regval;

drivers/i2c/busses/i2c-jz4780.c

191

regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);

drivers/i2c/busses/i2c-jz4780.c

192

if (!(regval & JZ4780_I2C_ENB_I2C))

drivers/i2c/busses/i2c-jz4780.c

198

dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);

drivers/i2c/busses/i2c-jz4780.c

204

unsigned short regval;

drivers/i2c/busses/i2c-jz4780.c

210

regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);

drivers/i2c/busses/i2c-jz4780.c

211

if (regval & JZ4780_I2C_ENB_I2C)

drivers/i2c/busses/i2c-jz4780.c

217

dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);

drivers/i2c/busses/i2c-jz4780.c

223

unsigned short regval;

drivers/i2c/busses/i2c-jz4780.c

227

regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);

drivers/i2c/busses/i2c-jz4780.c

228

if ((regval & JZ4780_I2C_STA_TFE) &&

drivers/i2c/busses/i2c-jz4780.c

229

!(regval & JZ4780_I2C_STA_MSTACT))

drivers/i2c/busses/i2c-jz4780.c

242

address, regval);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1071

u32 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1088

regval = readl(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1089

regval |= PERI_SMBUS_D3_RESET_DIS;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1090

writel(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1105

u32 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1107

regval = readw(p1);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1108

writew(regval, p1);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1110

regval = readl(p2);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1111

regval &= ~PERI_SMBUS_D3_RESET_DIS;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

1112

writel(regval, p2);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

373

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

375

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

378

regval |= SMBALERT_MST_PU;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

380

regval &= ~SMBALERT_MST_PU;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

382

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

388

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

390

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

393

regval |= SMB_CORE_CMD_START;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

395

regval |= SMB_CORE_CMD_STOP;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

397

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

407

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

410

regval = SMB_CORE_CTRL_FW_ACK | SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

412

regval = SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

414

writeb(regval, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

442

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

444

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

445

regval |= CTL_RESET_COUNTERS;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

446

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

452

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

454

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

456

regval &= ~CTL_TRANSFER_DIR;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

458

regval |= CTL_TRANSFER_DIR;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

460

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

481

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

483

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

484

regval |= CTL_RUN;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

485

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

491

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

493

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

494

regval |= SMB_CORE_CMD_M_RUN;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

495

regval |= SMB_CORE_CMD_M_PROCEED;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

496

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

508

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

510

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

512

regval |= SMB_CONFIG1_ASR;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

514

regval &= ~SMB_CONFIG1_ASR;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

515

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

562

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

564

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

566

regval |= SMB_CORE_CMD_READM;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

568

regval &= ~SMB_CORE_CMD_READM;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

570

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

582

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

584

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

586

regval &= ~intr_msk;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

588

regval |= intr_msk;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

590

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

597

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

599

regval = readb(p1);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

601

regval |= I2C_INPUT_EN | I2C_OUTPUT_EN;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

603

regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

605

writeb(regval, p1);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

607

regval = readb(p2);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

609

regval |= I2C_INPUT_EN | I2C_OUTPUT_EN;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

611

regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

613

writeb(regval, p2);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

619

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

621

regval = readb(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

623

regval &= ~CTL_HOST_FIFO_ENTRY;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

625

regval |= CTL_HOST_FIFO_ENTRY;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

627

writeb(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

634

u16 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

636

regval = readw(p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

638

regval &= ~intr_msk;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

640

regval |= intr_msk;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

641

writew(regval, p);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

710

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

719

regval = 0;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

721

regval = readl(p1);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

725

switch (regval) {

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

765

u8 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

771

regval = COMPLETION_MNAKX | COMPLETION_IDLE | COMPLETION_MDONE;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

772

writeb(regval, i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

789

u32 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

873

regval = readb(p2);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

876

if (regval & COMPLETION_MNAKX) {

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

909

u32 regval;

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

977

regval = readb(p2);

drivers/i2c/busses/i2c-mchp-pci1xxxx.c

978

if (regval & COMPLETION_MNAKX) {

drivers/i2c/busses/i2c-mlxcpld.c

493

u32 regval;

drivers/i2c/busses/i2c-mlxcpld.c

502

err = regmap_read(pdata->regmap, data->reg, &regval);

drivers/i2c/busses/i2c-mlxcpld.c

507

switch ((regval & data->mask) >> data->bit) {

drivers/i2c/busses/i2c-owl.c

109

unsigned int regval;

drivers/i2c/busses/i2c-owl.c

111

regval = readl(reg);

drivers/i2c/busses/i2c-owl.c

114

regval |= val;

drivers/i2c/busses/i2c-owl.c

116

regval &= ~val;

drivers/i2c/busses/i2c-owl.c

118

writel(regval, reg);

drivers/i2c/muxes/i2c-mux-mlxcpld.c

100

mux->last_val = err < 0 ? -1 : regval;

drivers/i2c/muxes/i2c-mux-mlxcpld.c

91

u32 regval = chan;

drivers/i2c/muxes/i2c-mux-mlxcpld.c

95

regval += 1;

drivers/i2c/muxes/i2c-mux-mlxcpld.c

98

if (mux->last_val != regval) {

drivers/i2c/muxes/i2c-mux-mlxcpld.c

99

err = mlxcpld_mux_reg_write(muxc->parent, mux, regval);

drivers/i2c/muxes/i2c-mux-pca954x.c

323

u8 regval;

drivers/i2c/muxes/i2c-mux-pca954x.c

326

regval = pca954x_regval(data, chan);

drivers/i2c/muxes/i2c-mux-pca954x.c

328

if (data->last_chan != regval) {

drivers/i2c/muxes/i2c-mux-pca954x.c

329

ret = pca954x_reg_write(muxc->parent, client, regval);

drivers/i2c/muxes/i2c-mux-pca954x.c

330

data->last_chan = ret < 0 ? 0 : regval;

drivers/i3c/master/mipi-i3c-hci/core.c

1020

u32 regval, offset;

drivers/i3c/master/mipi-i3c-hci/core.c

1024

regval = reg_read(HCI_VERSION);

drivers/i3c/master/mipi-i3c-hci/core.c

1025

hci->version_major = (regval >> 8) & 0xf;

drivers/i3c/master/mipi-i3c-hci/core.c

1026

hci->version_minor = (regval >> 4) & 0xf;

drivers/i3c/master/mipi-i3c-hci/core.c

1027

hci->revision = regval & 0xf;

drivers/i3c/master/mipi-i3c-hci/core.c

1031

switch (regval & ~0xf) {

drivers/i3c/master/mipi-i3c-hci/core.c

1047

regval = reg_read(DAT_SECTION);

drivers/i3c/master/mipi-i3c-hci/core.c

1048

offset = FIELD_GET(DAT_TABLE_OFFSET, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

1050

hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

1051

hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;

drivers/i3c/master/mipi-i3c-hci/core.c

1057

regval = reg_read(DCT_SECTION);

drivers/i3c/master/mipi-i3c-hci/core.c

1058

offset = FIELD_GET(DCT_TABLE_OFFSET, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

1060

hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

1061

hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16;

drivers/i3c/master/mipi-i3c-hci/core.c

1067

regval = reg_read(RING_HEADERS_SECTION);

drivers/i3c/master/mipi-i3c-hci/core.c

1068

offset = FIELD_GET(RING_HEADERS_OFFSET, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

1072

regval = reg_read(PIO_SECTION);

drivers/i3c/master/mipi-i3c-hci/core.c

1073

offset = FIELD_GET(PIO_REGS_OFFSET, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

1077

regval = reg_read(EXT_CAPS_SECTION);

drivers/i3c/master/mipi-i3c-hci/core.c

1078

offset = FIELD_GET(EXT_CAPS_OFFSET, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

177

u32 regval;

drivers/i3c/master/mipi-i3c-hci/core.c

183

ret = readx_poll_timeout(reg_read, HC_CONTROL, regval,

drivers/i3c/master/mipi-i3c-hci/core.c

184

!(regval & HC_CONTROL_BUS_ENABLE), 0, BUS_DISABLE_TIMEOUT_US);

drivers/i3c/master/mipi-i3c-hci/core.c

193

u32 regval;

drivers/i3c/master/mipi-i3c-hci/core.c

200

ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,

drivers/i3c/master/mipi-i3c-hci/core.c

201

!(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC);

drivers/i3c/master/mipi-i3c-hci/core.c

209

ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,

drivers/i3c/master/mipi-i3c-hci/core.c

210

!(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC);

drivers/i3c/master/mipi-i3c-hci/core.c

267

u32 regval;

drivers/i3c/master/mipi-i3c-hci/core.c

270

if (readx_poll_timeout_atomic(reg_read, RESET_CONTROL, regval,

drivers/i3c/master/mipi-i3c-hci/core.c

271

!(regval & ALL_QUEUES_RST), 0, 20))

drivers/i3c/master/mipi-i3c-hci/core.c

812

u32 regval;

drivers/i3c/master/mipi-i3c-hci/core.c

829

regval = reg_read(HC_CONTROL);

drivers/i3c/master/mipi-i3c-hci/core.c

831

if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {

drivers/i3c/master/mipi-i3c-hci/core.c

832

regval |= HC_CONTROL_DATA_BIG_ENDIAN;

drivers/i3c/master/mipi-i3c-hci/core.c

833

reg_write(HC_CONTROL, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

834

regval = reg_read(HC_CONTROL);

drivers/i3c/master/mipi-i3c-hci/core.c

835

if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {

drivers/i3c/master/mipi-i3c-hci/core.c

841

if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {

drivers/i3c/master/mipi-i3c-hci/core.c

842

regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;

drivers/i3c/master/mipi-i3c-hci/core.c

843

reg_write(HC_CONTROL, regval);

drivers/i3c/master/mipi-i3c-hci/core.c

844

regval = reg_read(HC_CONTROL);

drivers/i3c/master/mipi-i3c-hci/core.c

845

if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {

drivers/i3c/master/mipi-i3c-hci/dma.c

209

u32 regval;

drivers/i3c/master/mipi-i3c-hci/dma.c

216

regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);

drivers/i3c/master/mipi-i3c-hci/dma.c

217

rh_reg_write(CR_SETUP, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

235

regval = FIELD_PREP(IBI_STATUS_RING_SIZE, rh->ibi_status_entries) |

drivers/i3c/master/mipi-i3c-hci/dma.c

238

rh_reg_write(IBI_SETUP, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

240

regval = rh_reg_read(INTR_SIGNAL_ENABLE);

drivers/i3c/master/mipi-i3c-hci/dma.c

241

regval |= INTR_IBI_READY;

drivers/i3c/master/mipi-i3c-hci/dma.c

242

rh_reg_write(INTR_SIGNAL_ENABLE, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

268

u32 regval;

drivers/i3c/master/mipi-i3c-hci/dma.c

270

regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total);

drivers/i3c/master/mipi-i3c-hci/dma.c

271

rhs_reg_write(CONTROL, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

305

u32 regval;

drivers/i3c/master/mipi-i3c-hci/dma.c

321

regval = rhs_reg_read(CONTROL);

drivers/i3c/master/mipi-i3c-hci/dma.c

322

nr_rings = FIELD_GET(MAX_HEADER_COUNT_CAP, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

350

regval = rh_reg_read(CR_SETUP);

drivers/i3c/master/mipi-i3c-hci/dma.c

351

rh->xfer_struct_sz = FIELD_GET(CR_XFER_STRUCT_SIZE, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

352

rh->resp_struct_sz = FIELD_GET(CR_RESP_STRUCT_SIZE, regval);

drivers/i3c/master/mipi-i3c-hci/dma.c

375

regval = rh_reg_read(IBI_SETUP);

drivers/i3c/master/mipi-i3c-hci/dma.c

376

rh->ibi_status_sz = FIELD_GET(IBI_STATUS_STRUCT_SIZE, regval);

drivers/i3c/master/mipi-i3c-hci/pio.c

774

u32 regval = pio->reg_queue_thresh;

drivers/i3c/master/mipi-i3c-hci/pio.c

776

regval &= ~QUEUE_IBI_STATUS_THLD;

drivers/i3c/master/mipi-i3c-hci/pio.c

777

regval |= FIELD_PREP(QUEUE_IBI_STATUS_THLD, thresh_val);

drivers/i3c/master/mipi-i3c-hci/pio.c

779

if (regval != pio->reg_queue_thresh) {

drivers/i3c/master/mipi-i3c-hci/pio.c

780

pio_reg_write(QUEUE_THLD_CTRL, regval);

drivers/i3c/master/mipi-i3c-hci/pio.c

781

pio->reg_queue_thresh = regval;

drivers/iio/accel/adxl313_core.c

1033

unsigned int regval;

drivers/iio/accel/adxl313_core.c

1037

ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &regval);

drivers/iio/accel/adxl313_core.c

1041

if (FIELD_GET(ADXL313_REG_ACT_ACDC_MSK, regval)) {

drivers/iio/accel/adxl313_core.c

1065

ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &regval);

drivers/iio/accel/adxl313_core.c

1069

if (FIELD_GET(ADXL313_REG_INACT_ACDC_MSK, regval)) {

drivers/iio/accel/adxl313_core.c

128

unsigned int regval;

drivers/iio/accel/adxl313_core.c

131

ret = regmap_read(data->regmap, ADXL313_REG_DEVID0, &regval);

drivers/iio/accel/adxl313_core.c

135

if (regval != ADXL313_DEVID0_ADXL312_314)

drivers/iio/accel/adxl313_core.c

136

dev_warn(dev, "Invalid manufacturer ID: %#02x\n", regval);

drivers/iio/accel/adxl313_core.c

144

unsigned int regval;

drivers/iio/accel/adxl313_core.c

147

ret = regmap_read(data->regmap, ADXL313_REG_DEVID0, &regval);

drivers/iio/accel/adxl313_core.c

151

if (regval != ADXL313_DEVID0)

drivers/iio/accel/adxl313_core.c

152

dev_warn(dev, "Invalid manufacturer ID: 0x%02x\n", regval);

drivers/iio/accel/adxl313_core.c

155

if (regval == ADXL313_DEVID0) {

drivers/iio/accel/adxl313_core.c

156

ret = regmap_read(data->regmap, ADXL313_REG_DEVID1, &regval);

drivers/iio/accel/adxl313_core.c

160

if (regval != ADXL313_DEVID1)

drivers/iio/accel/adxl313_core.c

161

dev_warn(dev, "Invalid mems ID: 0x%02x\n", regval);

drivers/iio/accel/adxl313_core.c

163

ret = regmap_read(data->regmap, ADXL313_REG_PARTID, &regval);

drivers/iio/accel/adxl313_core.c

167

if (regval != ADXL313_PARTID)

drivers/iio/accel/adxl313_core.c

168

dev_warn(dev, "Invalid device ID: 0x%02x\n", regval);

drivers/iio/accel/adxl313_core.c

411

unsigned int regval;

drivers/iio/accel/adxl313_core.c

415

ret = regmap_read(data->regmap, ADXL313_REG_ACT_INACT_CTL, &regval);

drivers/iio/accel/adxl313_core.c

419

coupling = adxl313_act_acdc_msk[type] & regval;

drivers/iio/accel/adxl313_core.c

460

unsigned int regval;

drivers/iio/accel/adxl313_core.c

485

ret = regmap_read(data->regmap, ADXL313_REG_INT_ENABLE, &regval);

drivers/iio/accel/adxl313_core.c

489

int_en = adxl313_act_int_reg[type] & regval;

drivers/iio/accel/adxl313_core.c

616

unsigned int regval;

drivers/iio/accel/adxl313_core.c

635

ADXL313_REG_OFS_AXIS(chan->address), &regval);

drivers/iio/accel/adxl313_core.c

643

*val = sign_extend32(regval, 7) * 4;

drivers/iio/accel/adxl313_core.c

646

ret = regmap_read(data->regmap, ADXL313_REG_BW_RATE, &regval);

drivers/iio/accel/adxl313_core.c

650

ret = FIELD_GET(ADXL313_RATE_MSK, regval) - ADXL313_RATE_BASE;

drivers/iio/accel/adxl313_core.c

814

unsigned int regval;

drivers/iio/accel/adxl313_core.c

819

regval = DIV_ROUND_CLOSEST(MICRO * val + val2, 15625);

drivers/iio/accel/adxl313_core.c

824

regval);

drivers/iio/accel/adxl313_core.c

828

regval);

drivers/iio/accel/adxl313_core.c

917

unsigned int regval;

drivers/iio/accel/adxl313_core.c

920

ret = regmap_read(data->regmap, ADXL313_REG_FIFO_STATUS, &regval);

drivers/iio/accel/adxl313_core.c

924

return FIELD_GET(ADXL313_REG_FIFO_STATUS_ENTRIES_MSK, regval);

drivers/iio/accel/adxl313_core.c

954

unsigned int regval;

drivers/iio/accel/adxl313_core.c

963

regmap_read(data->regmap, ADXL313_REG_INT_SOURCE, &regval);

drivers/iio/accel/adxl345_core.c

1005

unsigned int regval;

drivers/iio/accel/adxl345_core.c

1008

ret = regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, &regval);

drivers/iio/accel/adxl345_core.c

1011

range_old = FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval);

drivers/iio/accel/adxl345_core.c

1069

unsigned int regval;

drivers/iio/accel/adxl345_core.c

1090

ret = regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, &regval);

drivers/iio/accel/adxl345_core.c

1093

range = FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval);

drivers/iio/accel/adxl345_core.c

1099

ADXL345_REG_OFS_AXIS(chan->address), &regval);

drivers/iio/accel/adxl345_core.c

1106

*val = sign_extend32(regval, 7) * 4;

drivers/iio/accel/adxl345_core.c

1110

ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, &regval);

drivers/iio/accel/adxl345_core.c

1113

odr = FIELD_GET(ADXL345_BW_RATE_MSK, regval);

drivers/iio/accel/adxl345_core.c

1558

unsigned int regval = 0;

drivers/iio/accel/adxl345_core.c

1561

ret = regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, &regval);

drivers/iio/accel/adxl345_core.c

1565

return FIELD_GET(ADXL345_REG_FIFO_STATUS_MSK, regval);

drivers/iio/accel/adxl345_core.c

1616

int regval;

drivers/iio/accel/adxl345_core.c

1625

regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, &regval);

drivers/iio/accel/adxl345_core.c

1681

unsigned int regval;

drivers/iio/accel/adxl345_core.c

1706

ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, &regval);

drivers/iio/accel/adxl345_core.c

1710

if (FIELD_GET(ADXL345_REG_ACT_ACDC, regval)) {

drivers/iio/accel/adxl345_core.c

1731

ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, &regval);

drivers/iio/accel/adxl345_core.c

1735

if (FIELD_GET(ADXL345_REG_INACT_ACDC, regval)) {

drivers/iio/accel/adxl345_core.c

1792

unsigned int regval;

drivers/iio/accel/adxl345_core.c

1805

ret = regmap_read(st->regmap, ADXL345_REG_ACT_TAP_STATUS, &regval);

drivers/iio/accel/adxl345_core.c

1809

if (FIELD_GET(ADXL345_TAP_Z_EN, regval))

drivers/iio/accel/adxl345_core.c

1811

else if (FIELD_GET(ADXL345_TAP_Y_EN, regval))

drivers/iio/accel/adxl345_core.c

1813

else if (FIELD_GET(ADXL345_TAP_X_EN, regval))

drivers/iio/accel/adxl345_core.c

1816

if (FIELD_GET(ADXL345_ACT_Z_EN, regval))

drivers/iio/accel/adxl345_core.c

1818

else if (FIELD_GET(ADXL345_ACT_Y_EN, regval))

drivers/iio/accel/adxl345_core.c

1820

else if (FIELD_GET(ADXL345_ACT_X_EN, regval))

drivers/iio/accel/adxl345_core.c

1890

u32 regval;

drivers/iio/accel/adxl345_core.c

1965

ret = regmap_read(st->regmap, ADXL345_REG_DEVID, &regval);

drivers/iio/accel/adxl345_core.c

1969

if (regval != ADXL345_DEVID)

drivers/iio/accel/adxl345_core.c

1971

regval, ADXL345_DEVID);

drivers/iio/accel/adxl345_core.c

382

unsigned int regval;

drivers/iio/accel/adxl345_core.c

387

ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, &regval);

drivers/iio/accel/adxl345_core.c

391

odr = FIELD_GET(ADXL345_BW_RATE_MSK, regval);

drivers/iio/accel/adxl345_core.c

481

unsigned int regval;

drivers/iio/accel/adxl345_core.c

488

ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, &regval);

drivers/iio/accel/adxl345_core.c

492

coupling = adxl345_act_acdc_msk[type] & regval;

drivers/iio/accel/adxl345_core.c

574

unsigned int regval;

drivers/iio/accel/adxl345_core.c

604

ret = regmap_read(st->regmap, ADXL345_REG_INT_ENABLE, &regval);

drivers/iio/accel/adxl345_core.c

608

int_en = adxl345_act_int_reg[type] & regval;

drivers/iio/accel/adxl345_core.c

797

unsigned int regval;

drivers/iio/accel/adxl345_core.c

826

ret = regmap_read(st->regmap, ADXL345_REG_INT_ENABLE, &regval);

drivers/iio/accel/adxl345_core.c

830

*en = adxl345_tap_int_reg[type] & regval;

drivers/iio/accel/adxl345_core.c

887

unsigned int regval;

drivers/iio/accel/adxl345_core.c

906

regval = DIV_ROUND_CLOSEST(val_us, 625);

drivers/iio/accel/adxl345_core.c

908

regval = DIV_ROUND_CLOSEST(val_us, 1250);

drivers/iio/accel/adxl345_core.c

910

return regmap_write(st->regmap, adxl345_tap_time_reg[type], regval);

drivers/iio/accel/adxl355_core.c

297

unsigned int regval;

drivers/iio/accel/adxl355_core.c

305

ret = regmap_read(data->regmap, ADXL355_DEVID_AD_REG, &regval);

drivers/iio/accel/adxl355_core.c

309

if (regval != ADXL355_DEVID_AD_VAL) {

drivers/iio/accel/adxl355_core.c

310

dev_err(data->dev, "Invalid ADI ID 0x%02x\n", regval);

drivers/iio/accel/adxl355_core.c

314

ret = regmap_read(data->regmap, ADXL355_DEVID_MST_REG, &regval);

drivers/iio/accel/adxl355_core.c

318

if (regval != ADXL355_DEVID_MST_VAL) {

drivers/iio/accel/adxl355_core.c

319

dev_err(data->dev, "Invalid MEMS ID 0x%02x\n", regval);

drivers/iio/accel/adxl355_core.c

323

ret = regmap_read(data->regmap, ADXL355_PARTID_REG, &regval);

drivers/iio/accel/adxl355_core.c

327

if (regval != ADXL355_PARTID_VAL)

drivers/iio/accel/adxl355_core.c

328

dev_warn(data->dev, "Invalid DEV ID 0x%02x\n", regval);

drivers/iio/accel/adxl372.c

387

u16 regval;

drivers/iio/accel/adxl372.c

394

regval = be16_to_cpu(raw_regval);

drivers/iio/accel/adxl372.c

395

regval >>= 5;

drivers/iio/accel/adxl372.c

397

*threshold = regval;

drivers/iio/accel/adxl372.c

420

__be16 regval;

drivers/iio/accel/adxl372.c

423

ret = regmap_bulk_read(st->regmap, addr, &regval, sizeof(regval));

drivers/iio/accel/adxl372.c

427

return be16_to_cpu(regval);

drivers/iio/accel/adxl372.c

746

unsigned int regval;

drivers/iio/accel/adxl372.c

749

ret = regmap_read(st->regmap, ADXL372_DEVID, &regval);

drivers/iio/accel/adxl372.c

753

if (regval != ADXL372_DEVID_VAL) {

drivers/iio/accel/adxl372.c

754

dev_err(st->dev, "Invalid chip id %x\n", regval);

drivers/iio/accel/adxl372_i2c.c

24

unsigned int regval;

drivers/iio/accel/adxl372_i2c.c

33

ret = regmap_read(regmap, ADXL372_REVID, &regval);

drivers/iio/accel/adxl372_i2c.c

38

if (regval < 3)

drivers/iio/accel/bma400_core.c

1198

unsigned int intrmask, regval;

drivers/iio/accel/bma400_core.c

1226

regval = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) |

drivers/iio/accel/bma400_core.c

1228

ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), regval);

drivers/iio/accel/bma400_core.c

1245

regval = state ? intrmask : 0;

drivers/iio/accel/bma400_core.c

1246

ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, regval);

drivers/iio/accel/bma400_core.c

1250

ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask, regval);

drivers/iio/accel/bma400_core.c

1254

set_mask_bits(&data->generic_event_en, intrmask, regval);

drivers/iio/accel/bmi088-accel-core.c

224

unsigned int regval;

drivers/iio/accel/bmi088-accel-core.c

234

regval = (index >> 1) + BMI088_ACCEL_MODE_ODR_12_5;

drivers/iio/accel/bmi088-accel-core.c

237

BMI088_ACCEL_MODE_ODR_MASK, regval);

drivers/iio/accel/kionix-kx022a.c

631

unsigned int regval;

drivers/iio/accel/kionix-kx022a.c

648

ret = regmap_read(data->regmap, data->chip_info->odcntl, &regval);

drivers/iio/accel/kionix-kx022a.c

652

if ((regval & KX022A_MASK_ODR) >

drivers/iio/accel/kionix-kx022a.c

658

kx022a_reg2freq(regval, val, val2);

drivers/iio/accel/kionix-kx022a.c

663

ret = regmap_read(data->regmap, data->chip_info->cntl, &regval);

drivers/iio/accel/kionix-kx022a.c

667

kx022a_reg2scale(data, regval, val, val2);

drivers/iio/accel/kxsd9.c

166

unsigned int regval;

drivers/iio/accel/kxsd9.c

192

&regval);

drivers/iio/accel/kxsd9.c

196

*val2 = kxsd9_micro_scales[regval & KXSD9_CTRL_C_FS_MASK];

drivers/iio/adc/ad7291.c

277

u16 regval;

drivers/iio/adc/ad7291.c

280

regval = chip->command;

drivers/iio/adc/ad7291.c

298

regval &= ~AD7291_AUTOCYCLE;

drivers/iio/adc/ad7291.c

299

regval |= chip->c_mask;

drivers/iio/adc/ad7291.c

301

regval |= AD7291_AUTOCYCLE;

drivers/iio/adc/ad7291.c

303

ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);

drivers/iio/adc/ad7291.c

307

chip->command = regval;

drivers/iio/adc/ad7291.c

326

u16 regval;

drivers/iio/adc/ad7291.c

339

regval = chip->command & (~AD7291_VOLTAGE_MASK);

drivers/iio/adc/ad7291.c

340

regval |= BIT(15 - chan->channel);

drivers/iio/adc/ad7291.c

341

ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);

drivers/iio/adc/ad7380.c

1024

static int ad7380_regval_to_osr(unsigned int regval)

drivers/iio/adc/ad7380.c

1026

if (regval >= ARRAY_SIZE(ad7380_oversampling_ratios))

drivers/iio/adc/ad7380.c

1029

return ad7380_oversampling_ratios[regval];

drivers/iio/adc/ad7768-1.c

1520

int ret, regval;

drivers/iio/adc/ad7768-1.c

1526

regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1);

drivers/iio/adc/ad7768-1.c

1528

AD7768_REG_ANALOG2_VCM_MSK, regval);

drivers/iio/adc/ad7768-1.c

1570

unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1);

drivers/iio/adc/ad7768-1.c

1579

AD7768_REG_ANALOG2_VCM_MSK, regval);

drivers/iio/adc/ad7768-1.c

592

u16 regval;

drivers/iio/adc/ad7768-1.c

614

regval = FIELD_PREP(GENMASK(12, 0), dec_rate);

drivers/iio/adc/ad7768-1.c

615

put_unaligned_be16(regval, dec_rate_reg);

drivers/iio/adc/ad7779.c

229

u8 regval, data;

drivers/iio/adc/ad7779.c

235

regval = (data & ~mask) | (val & mask);

drivers/iio/adc/ad7779.c

237

if (regval == data)

drivers/iio/adc/ad7779.c

240

return ad7779_spi_write(st, reg, regval);

drivers/iio/adc/axp20x_adc.c

697

unsigned int regval;

drivers/iio/adc/axp20x_adc.c

700

ret = regmap_read(info->regmap, AXP192_GPIO30_IN_RANGE, &regval);

drivers/iio/adc/axp20x_adc.c

706

regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO0, regval);

drivers/iio/adc/axp20x_adc.c

710

regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO1, regval);

drivers/iio/adc/axp20x_adc.c

714

regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO2, regval);

drivers/iio/adc/axp20x_adc.c

718

regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO3, regval);

drivers/iio/adc/axp20x_adc.c

725

*val = regval ? 700000 : 0;

drivers/iio/adc/axp20x_adc.c

733

unsigned int regval;

drivers/iio/adc/axp20x_adc.c

736

ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, &regval);

drivers/iio/adc/axp20x_adc.c

742

regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO0, regval);

drivers/iio/adc/axp20x_adc.c

746

regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO1, regval);

drivers/iio/adc/axp20x_adc.c

753

*val = regval ? 700000 : 0;

drivers/iio/adc/axp20x_adc.c

889

unsigned int regmask, regval;

drivers/iio/adc/axp20x_adc.c

904

regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO0, !!val);

drivers/iio/adc/axp20x_adc.c

909

regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO1, !!val);

drivers/iio/adc/axp20x_adc.c

914

regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO2, !!val);

drivers/iio/adc/axp20x_adc.c

919

regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO3, !!val);

drivers/iio/adc/axp20x_adc.c

926

return regmap_update_bits(info->regmap, AXP192_GPIO30_IN_RANGE, regmask, regval);

drivers/iio/adc/axp20x_adc.c

934

unsigned int regmask, regval;

drivers/iio/adc/axp20x_adc.c

949

regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO0, !!val);

drivers/iio/adc/axp20x_adc.c

954

regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO1, !!val);

drivers/iio/adc/axp20x_adc.c

961

return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, regmask, regval);

drivers/iio/adc/ina2xx-adc.c

194

unsigned int regval;

drivers/iio/adc/ina2xx-adc.c

198

ret = regmap_read(chip->regmap, chan->address, &regval);

drivers/iio/adc/ina2xx-adc.c

203

*val = (s16) regval;

drivers/iio/adc/ina2xx-adc.c

205

*val = regval;

drivers/iio/adc/max11410.c

356

unsigned int regval;

drivers/iio/adc/max11410.c

368

regval = FIELD_PREP(MAX11410_CTRL_VREFP_BUF_BIT, cfg.buffered_vrefp) |

drivers/iio/adc/max11410.c

376

MAX11410_CTRL_UNIPOLAR_BIT, regval);

drivers/iio/adc/max11410.c

380

regval = FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, cfg.sig_path) |

drivers/iio/adc/max11410.c

382

ret = regmap_write(st->regmap, MAX11410_REG_PGA, regval);

drivers/iio/adc/max9611.c

455

u16 regval;

drivers/iio/adc/max9611.c

467

ret = max9611_read_single(max9611, CONF_TEMP, &regval);

drivers/iio/adc/max9611.c

471

regval &= MAX9611_TEMP_MASK;

drivers/iio/adc/max9611.c

473

if ((regval > MAX9611_TEMP_MAX_POS &&

drivers/iio/adc/max9611.c

474

regval < MAX9611_TEMP_MIN_NEG) ||

drivers/iio/adc/max9611.c

475

regval > MAX9611_TEMP_MAX_NEG) {

drivers/iio/adc/max9611.c

478

regval);

drivers/iio/adc/mcp3911.c

560

u32 regval;

drivers/iio/adc/mcp3911.c

563

ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &regval, 2);

drivers/iio/adc/mcp3911.c

567

regval &= ~MCP3911_CONFIG_VREFEXT;

drivers/iio/adc/mcp3911.c

570

regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1);

drivers/iio/adc/mcp3911.c

573

regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0);

drivers/iio/adc/mcp3911.c

576

regval &= ~MCP3911_CONFIG_CLKEXT;

drivers/iio/adc/mcp3911.c

579

regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1);

drivers/iio/adc/mcp3911.c

582

regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0);

drivers/iio/adc/mcp3911.c

585

ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2);

drivers/iio/adc/mcp3911.c

589

ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, &regval, 2);

drivers/iio/adc/mcp3911.c

594

regval &= ~MCP3911_STATUSCOM_READ;

drivers/iio/adc/mcp3911.c

595

regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);

drivers/iio/adc/mcp3911.c

597

regval &= ~MCP3911_STATUSCOM_DRHIZ;

drivers/iio/adc/mcp3911.c

599

regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0);

drivers/iio/adc/mcp3911.c

601

regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1);

drivers/iio/adc/mcp3911.c

604

regval &= ~MCP3911_STATUSCOM_EN_OFFCAL;

drivers/iio/adc/mcp3911.c

606

ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);

drivers/iio/adc/mcp3911.c

611

ret = mcp3911_read(adc, MCP3911_REG_GAIN, &regval, 1);

drivers/iio/adc/mcp3911.c

617

regval &= ~MCP3911_GAIN_MASK(i);

drivers/iio/adc/mcp3911.c

620

return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1);

drivers/iio/adc/mcp3911.c

626

u32 regval;

drivers/iio/adc/mcp3911.c

629

ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, &regval, 3);

drivers/iio/adc/mcp3911.c

633

regval &= ~MCP3910_CONFIG1_VREFEXT;

drivers/iio/adc/mcp3911.c

636

regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1);

drivers/iio/adc/mcp3911.c

639

regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0);

drivers/iio/adc/mcp3911.c

642

regval &= ~MCP3910_CONFIG1_CLKEXT;

drivers/iio/adc/mcp3911.c

645

regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1);

drivers/iio/adc/mcp3911.c

648

regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0);

drivers/iio/adc/mcp3911.c

651

ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3);

drivers/iio/adc/mcp3911.c

655

ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, &regval, 3);

drivers/iio/adc/mcp3911.c

660

regval &= ~MCP3910_STATUSCOM_READ;

drivers/iio/adc/mcp3911.c

661

regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02);

drivers/iio/adc/mcp3911.c

663

regval &= ~MCP3910_STATUSCOM_DRHIZ;

drivers/iio/adc/mcp3911.c

665

regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0);

drivers/iio/adc/mcp3911.c

667

regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1);

drivers/iio/adc/mcp3911.c

669

ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3);

drivers/iio/adc/mcp3911.c

674

ret = mcp3911_read(adc, MCP3910_REG_GAIN, &regval, 3);

drivers/iio/adc/mcp3911.c

680

regval &= ~MCP3911_GAIN_MASK(i);

drivers/iio/adc/mcp3911.c

682

ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3);

drivers/iio/adc/meson_saradc.c

1001

MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);

drivers/iio/adc/meson_saradc.c

1003

regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,

drivers/iio/adc/meson_saradc.c

1006

MESON_SAR_ADC_REG11_CMV_SEL, regval);

drivers/iio/adc/meson_saradc.c

1048

u32 regval;

drivers/iio/adc/meson_saradc.c

1062

regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);

drivers/iio/adc/meson_saradc.c

1064

MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);

drivers/iio/adc/meson_saradc.c

1125

u32 regval;

drivers/iio/adc/meson_saradc.c

1127

regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);

drivers/iio/adc/meson_saradc.c

1128

cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);

drivers/iio/adc/meson_saradc.c

1129

threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);

drivers/iio/adc/meson_saradc.c

393

u32 regval;

drivers/iio/adc/meson_saradc.c

395

regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);

drivers/iio/adc/meson_saradc.c

397

return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);

drivers/iio/adc/meson_saradc.c

431

u32 regval;

drivers/iio/adc/meson_saradc.c

433

regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);

drivers/iio/adc/meson_saradc.c

435

MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);

drivers/iio/adc/meson_saradc.c

448

int regval, fifo_chan, fifo_val, count;

drivers/iio/adc/meson_saradc.c

460

regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);

drivers/iio/adc/meson_saradc.c

461

fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);

drivers/iio/adc/meson_saradc.c

468

fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);

drivers/iio/adc/meson_saradc.c

497

u32 regval;

drivers/iio/adc/meson_saradc.c

504

regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);

drivers/iio/adc/meson_saradc.c

506

MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);

drivers/iio/adc/meson_saradc.c

509

regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),

drivers/iio/adc/meson_saradc.c

512

MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);

drivers/iio/adc/meson_saradc.c

514

regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,

drivers/iio/adc/meson_saradc.c

518

regval);

drivers/iio/adc/meson_saradc.c

520

regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,

drivers/iio/adc/meson_saradc.c

524

regval);

drivers/iio/adc/meson_saradc.c

528

regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;

drivers/iio/adc/meson_saradc.c

530

regval = 0;

drivers/iio/adc/meson_saradc.c

534

MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);

drivers/iio/adc/meson_saradc.c

849

int regval, i, ret;

drivers/iio/adc/meson_saradc.c

863

regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);

drivers/iio/adc/meson_saradc.c

864

if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)

drivers/iio/adc/meson_saradc.c

909

regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);

drivers/iio/adc/meson_saradc.c

912

regval);

drivers/iio/adc/meson_saradc.c

913

regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);

drivers/iio/adc/meson_saradc.c

916

regval);

drivers/iio/adc/meson_saradc.c

936

regval = 0;

drivers/iio/adc/meson_saradc.c

938

regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);

drivers/iio/adc/meson_saradc.c

939

regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;

drivers/iio/adc/meson_saradc.c

940

regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;

drivers/iio/adc/meson_saradc.c

941

regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);

drivers/iio/adc/meson_saradc.c

953

regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,

drivers/iio/adc/meson_saradc.c

956

MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);

drivers/iio/adc/meson_saradc.c

960

regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;

drivers/iio/adc/meson_saradc.c

962

regval = 0;

drivers/iio/adc/meson_saradc.c

971

regval);

drivers/iio/adc/meson_saradc.c

980

regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,

drivers/iio/adc/meson_saradc.c

984

regval);

drivers/iio/adc/meson_saradc.c

987

regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);

drivers/iio/adc/meson_saradc.c

989

MESON_SAR_ADC_REG11_EOC, regval);

drivers/iio/adc/meson_saradc.c

992

regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,

drivers/iio/adc/meson_saradc.c

995

MESON_SAR_ADC_REG11_VREF_SEL, regval);

drivers/iio/adc/meson_saradc.c

998

regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,

drivers/iio/adc/mt6360-adc.c

145

unsigned int regval;

drivers/iio/adc/mt6360-adc.c

168

ret = regmap_read(mad->regmap, MT6360_REG_PMUCHGCTRL3, &regval);

drivers/iio/adc/mt6360-adc.c

172

regval = (regval & MT6360_AICR_MASK) >> MT6360_AICR_SHFT;

drivers/iio/adc/mt6360-adc.c

173

if (regval < MT6360_AICR_400MA)

drivers/iio/adc/rohm-bd79124.c

379

unsigned int val, regval;

drivers/iio/adc/rohm-bd79124.c

410

regval = FIELD_PREP(BD79124_MSK_CONV_MODE, BD79124_CONV_MODE_AUTO);

drivers/iio/adc/rohm-bd79124.c

413

BD79124_MSK_CONV_MODE, regval);

drivers/iio/adc/rohm-bd79124.c

441

int regval = FIELD_PREP(BD79124_MSK_CONV_MODE,

drivers/iio/adc/rohm-bd79124.c

445

BD79124_MSK_CONV_MODE, regval);

drivers/iio/adc/rohm-bd79124.c

678

unsigned int old_chan_cfg, regval;

drivers/iio/adc/rohm-bd79124.c

687

regval = FIELD_PREP(BD79124_MSK_CONV_MODE,

drivers/iio/adc/rohm-bd79124.c

690

BD79124_MSK_CONV_MODE, regval);

drivers/iio/adc/rohm-bd79124.c

949

unsigned int regval;

drivers/iio/adc/rohm-bd79124.c

980

regval = FIELD_PREP(BD79124_MSK_AUTO_INTERVAL, BD79124_INTERVAL_750_US);

drivers/iio/adc/rohm-bd79124.c

982

BD79124_MSK_AUTO_INTERVAL, regval);

drivers/iio/adc/rohm-bd79124.c

993

regval = FIELD_PREP(BD79124_MSK_CONV_MODE, BD79124_CONV_MODE_MANSEQ);

drivers/iio/adc/rohm-bd79124.c

995

BD79124_MSK_CONV_MODE, regval);

drivers/iio/adc/rtq6056.c

281

unsigned int regval;

drivers/iio/adc/rtq6056.c

285

ret = regmap_read(priv->regmap, addr, &regval);

drivers/iio/adc/rtq6056.c

294

regval >>= devdata->vbus_offset;

drivers/iio/adc/rtq6056.c

295

*val = regval;

drivers/iio/adc/rtq6056.c

298

*val = regval;

drivers/iio/adc/rtq6056.c

302

*val = sign_extend32(regval, 15);

drivers/iio/adc/ti-ads1298.c

286

unsigned int regval;

drivers/iio/adc/ti-ads1298.c

296

ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG3, &regval);

drivers/iio/adc/ti-ads1298.c

301

*val = regval & ADS1298_MASK_CONFIG3_VREF_4V ? 4000 : 2400;

drivers/iio/adc/ti-ads1298.c

304

ret = regmap_read(priv->regmap, ADS1298_REG_CHnSET(channel), &regval);

drivers/iio/adc/ti-ads1298.c

308

pga_idx = FIELD_GET(ADS1298_MASK_CH_PGA, regval);

drivers/iio/adc/ti-ads7138.c

126

u8 reg, u8 regval, u8 opcode)

drivers/iio/adc/ti-ads7138.c

128

u8 buf[3] = { opcode, reg, regval };

drivers/iio/adc/twl4030-madc.c

683

u8 regval;

drivers/iio/adc/twl4030-madc.c

686

&regval, TWL4030_BCI_BCICTL1);

drivers/iio/adc/twl4030-madc.c

695

regval |= regmask;

drivers/iio/adc/twl4030-madc.c

697

regval &= ~regmask;

drivers/iio/adc/twl4030-madc.c

700

regval, TWL4030_BCI_BCICTL1);

drivers/iio/adc/twl4030-madc.c

718

u8 regval;

drivers/iio/adc/twl4030-madc.c

722

&regval, TWL4030_MADC_CTRL1);

drivers/iio/adc/twl4030-madc.c

729

regval |= TWL4030_MADC_MADCON;

drivers/iio/adc/twl4030-madc.c

731

regval &= ~TWL4030_MADC_MADCON;

drivers/iio/adc/twl4030-madc.c

732

ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1);

drivers/iio/adc/twl4030-madc.c

751

u8 regval;

drivers/iio/adc/twl4030-madc.c

796

&regval, TWL4030_BCI_BCICTL1);

drivers/iio/adc/twl4030-madc.c

802

regval |= TWL4030_BCI_MESBAT;

drivers/iio/adc/twl4030-madc.c

804

regval, TWL4030_BCI_BCICTL1);

drivers/iio/adc/twl4030-madc.c

812

ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &regval, TWL4030_REG_GPBR1);

drivers/iio/adc/twl4030-madc.c

820

if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) {

drivers/iio/adc/twl4030-madc.c

822

regval |= TWL4030_GPBR1_MADC_HFCLK_EN;

drivers/iio/adc/twl4030-madc.c

823

ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval,

drivers/iio/adc/twl4030-madc.c

847

ret = twl_i2c_read_u8(TWL_MODULE_USB, &regval,

drivers/iio/adc/twl4030-madc.c

854

regval |= TWL4030_USB_SEL_MADC_MCPC;

drivers/iio/adc/twl4030-madc.c

855

ret = twl_i2c_write_u8(TWL_MODULE_USB, regval,

drivers/iio/adc/xilinx-ams.c

298

u32 val, regval;

drivers/iio/adc/xilinx-ams.c

301

regval = (val & ~mask) | (data & mask);

drivers/iio/adc/xilinx-ams.c

302

writel(regval, ams->ps_base + offset);

drivers/iio/adc/xilinx-ams.c

308

u32 val, regval;

drivers/iio/adc/xilinx-ams.c

311

regval = (val & ~mask) | (data & mask);

drivers/iio/adc/xilinx-ams.c

312

writel(regval, ams->pl_base + offset);

drivers/iio/adc/xilinx-ams.c

317

u32 regval;

drivers/iio/adc/xilinx-ams.c

321

regval = ~(ams->intr_mask | ams->current_masked_alarm);

drivers/iio/adc/xilinx-ams.c

322

writel(regval, ams->base + AMS_IER_0);

drivers/iio/adc/xilinx-ams.c

324

regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));

drivers/iio/adc/xilinx-ams.c

325

writel(regval, ams->base + AMS_IER_1);

drivers/iio/adc/xilinx-ams.c

327

regval = ams->intr_mask | ams->current_masked_alarm;

drivers/iio/adc/xilinx-ams.c

328

writel(regval, ams->base + AMS_IDR_0);

drivers/iio/adc/xilinx-ams.c

330

regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);

drivers/iio/adc/xilinx-ams.c

331

writel(regval, ams->base + AMS_IDR_1);

drivers/iio/adc/xilinx-ams.c

436

u32 regval;

drivers/iio/adc/xilinx-ams.c

458

regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);

drivers/iio/adc/xilinx-ams.c

459

writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);

drivers/iio/adc/xilinx-ams.c

461

regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);

drivers/iio/adc/xilinx-ams.c

462

writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);

drivers/iio/adc/xilinx-ams.c

477

regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);

drivers/iio/adc/xilinx-ams.c

478

writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);

drivers/iio/adc/xilinx-ams.c

480

regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask);

drivers/iio/adc/xilinx-ams.c

481

writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);

drivers/iio/adc/xilinx-ams.c

483

regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);

drivers/iio/adc/xilinx-ams.c

484

writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);

drivers/iio/adc/xilinx-ams.c

639

int val, regval;

drivers/iio/adc/xilinx-ams.c

654

regval = readl(ams->pl_base + AMS_REG_CONFIG4);

drivers/iio/adc/xilinx-ams.c

655

if (FIELD_GET(AMS_VUSER0_MASK, regval))

drivers/iio/adc/xilinx-ams.c

661

regval = readl(ams->pl_base + AMS_REG_CONFIG4);

drivers/iio/adc/xilinx-ams.c

662

if (FIELD_GET(AMS_VUSER1_MASK, regval))

drivers/iio/adc/xilinx-ams.c

668

regval = readl(ams->pl_base + AMS_REG_CONFIG4);

drivers/iio/adc/xilinx-ams.c

669

if (FIELD_GET(AMS_VUSER2_MASK, regval))

drivers/iio/adc/xilinx-ams.c

675

regval = readl(ams->pl_base + AMS_REG_CONFIG4);

drivers/iio/adc/xilinx-ams.c

676

if (FIELD_GET(AMS_VUSER3_MASK, regval))

drivers/iio/addac/ad74115.c

814

unsigned int regval, wait_time;

drivers/iio/addac/ad74115.c

824

regval, regval & AD74115_ADC_DATA_RDY_MASK,

drivers/iio/cdc/ad7746.c

330

u8 regval)

drivers/iio/cdc/ad7746.c

345

regval |= chip->config;

drivers/iio/cdc/ad7746.c

346

ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);

drivers/iio/cdc/ad7746.c

356

} while ((ret == regval) && timeout--);

drivers/iio/cdc/ad7746.c

587

u8 regval;

drivers/iio/cdc/ad7746.c

594

regval = chip->config | FIELD_PREP(AD7746_CONF_MODE_MASK,

drivers/iio/cdc/ad7746.c

596

ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);

drivers/iio/cdc/ad7746.c

725

unsigned char regval = 0;

drivers/iio/cdc/ad7746.c

750

regval |= AD7746_EXCSETUP_NEXCA;

drivers/iio/cdc/ad7746.c

752

regval |= AD7746_EXCSETUP_EXCA;

drivers/iio/cdc/ad7746.c

757

regval |= AD7746_EXCSETUP_NEXCB;

drivers/iio/cdc/ad7746.c

759

regval |= AD7746_EXCSETUP_EXCB;

drivers/iio/cdc/ad7746.c

767

regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 0);

drivers/iio/cdc/ad7746.c

770

regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 1);

drivers/iio/cdc/ad7746.c

773

regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 2);

drivers/iio/cdc/ad7746.c

776

regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 3);

drivers/iio/cdc/ad7746.c

784

regval);

drivers/iio/dac/ad5758.c

227

int regval;

drivers/iio/dac/ad5758.c

229

regval = ad5758_spi_reg_read(st, addr);

drivers/iio/dac/ad5758.c

230

if (regval < 0)

drivers/iio/dac/ad5758.c

231

return regval;

drivers/iio/dac/ad5758.c

233

regval &= ~mask;

drivers/iio/dac/ad5758.c

234

regval |= val;

drivers/iio/dac/ad5758.c

236

return ad5758_spi_reg_write(st, addr, regval);

drivers/iio/dac/ad5758.c

769

int regval, ret;

drivers/iio/dac/ad5758.c

796

regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS);

drivers/iio/dac/ad5758.c

797

if (regval < 0)

drivers/iio/dac/ad5758.c

798

return regval;

drivers/iio/dac/ad5758.c

801

ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval);

drivers/iio/dac/ad5770r.c

192

unsigned int regval;

drivers/iio/dac/ad5770r.c

194

regval = AD5770R_RANGE_OUTPUT_SCALING(out_mode->out_scale) |

drivers/iio/dac/ad5770r.c

198

AD5770R_OUTPUT_RANGE(channel), regval);

drivers/iio/dac/ad5770r.c

203

unsigned int regval;

drivers/iio/dac/ad5770r.c

205

regval = AD5770R_REF_RESISTOR_SEL(st->external_res);

drivers/iio/dac/ad5770r.c

208

regval |= AD5770R_REF_SEL(AD5770R_INT_1_25_V_OUT_OFF);

drivers/iio/dac/ad5770r.c

212

regval |= AD5770R_REF_SEL(AD5770R_EXT_1_25_V);

drivers/iio/dac/ad5770r.c

215

regval |= AD5770R_REF_SEL(AD5770R_EXT_2_5_V);

drivers/iio/dac/ad5770r.c

218

regval = AD5770R_REF_SEL(AD5770R_INT_1_25_V_OUT_OFF);

drivers/iio/dac/ad5770r.c

223

return regmap_write(st->regmap, AD5770R_REFERENCE, regval);

drivers/iio/dac/ad5770r.c

274

unsigned int regval, i;

drivers/iio/dac/ad5770r.c

277

AD5770R_FILTER_RESISTOR(chan->channel), &regval);

drivers/iio/dac/ad5770r.c

282

if (regval == ad5770r_filter_reg_vals[i])

drivers/iio/dac/ad5770r.c

297

unsigned int regval, i;

drivers/iio/dac/ad5770r.c

305

regval = ad5770r_filter_reg_vals[i];

drivers/iio/dac/ad5770r.c

308

regval);

drivers/iio/dac/ad5770r.c

444

unsigned int regval;

drivers/iio/dac/ad5770r.c

455

regval = AD5770R_CFG_SHUTDOWN_B(readin, chan->channel);

drivers/iio/dac/ad5770r.c

458

regval |= AD5770R_CFG_CH0_SINK_EN(readin);

drivers/iio/dac/ad5770r.c

464

regval);

drivers/iio/dac/ad5770r.c

468

regval = AD5770R_CH_SET(readin, chan->channel);

drivers/iio/dac/ad5770r.c

470

BIT(chan->channel), regval);

drivers/iio/dac/ds4424.c

186

unsigned int regval;

drivers/iio/dac/ds4424.c

192

&regval);

drivers/iio/dac/ds4424.c

200

*val = regval & data->chip_info->result_mask;

drivers/iio/dac/ds4424.c

201

if (!(regval & DS4424_DAC_SOURCE))

drivers/iio/dac/ltc2688.c

534

int ret, regval;

drivers/iio/dac/ltc2688.c

537

&regval);

drivers/iio/dac/ltc2688.c

541

return FIELD_GET(LTC2688_CH_DIT_PH_MSK, regval);

drivers/iio/dummy/iio_simple_dummy.c

39

int regval; /* what would be written to hardware */

drivers/iio/gyro/itg3200_core.c

111

ret = itg3200_read_reg_8(indio_dev, ITG3200_REG_DLPF, &regval);

drivers/iio/gyro/itg3200_core.c

115

*val = (regval & ITG3200_DLPF_CFG_MASK) ? 1000 : 8000;

drivers/iio/gyro/itg3200_core.c

119

&regval);

drivers/iio/gyro/itg3200_core.c

123

*val /= regval + 1;

drivers/iio/gyro/itg3200_core.c

90

u8 regval;

drivers/iio/humidity/ens210.c

128

regval = get_unaligned_le24(regval_le);

drivers/iio/humidity/ens210.c

129

if (ens210_crc7(regval) != ((regval >> 17) & 0x7f)) {

drivers/iio/humidity/ens210.c

134

if (!((regval >> 16) & 0x1)) {

drivers/iio/humidity/ens210.c

139

*val = regval & GENMASK(15, 0);

drivers/iio/humidity/ens210.c

97

u32 regval;

drivers/iio/imu/bmi270/bmi270_core.c

1067

int ret, reg, regval;

drivers/iio/imu/bmi270/bmi270_core.c

1076

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/imu/bmi270/bmi270_core.c

1082

return !!FIELD_GET(BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

1086

return !!FIELD_GET(BMI270_INT_MAP_FEAT_NOMOTION_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

1094

regval);

drivers/iio/imu/bmi270/bmi270_core.c

1128

unsigned int raw, mask, regval;

drivers/iio/imu/bmi270/bmi270_core.c

1140

regval = FIELD_PREP(BMI270_STEP_SC26_WTRMRK_MSK, raw);

drivers/iio/imu/bmi270/bmi270_core.c

1142

regval);

drivers/iio/imu/bmi270/bmi270_core.c

1161

regval = FIELD_PREP(BMI270_FEAT_MOTION_THRESHOLD_MSK, raw);

drivers/iio/imu/bmi270/bmi270_core.c

1162

return bmi270_update_feature_reg(data, reg, mask, regval);

drivers/iio/imu/bmi270/bmi270_core.c

1170

regval = FIELD_PREP(BMI270_FEAT_MOTION_DURATION_MSK, raw);

drivers/iio/imu/bmi270/bmi270_core.c

1171

return bmi270_update_feature_reg(data, reg, mask, regval);

drivers/iio/imu/bmi270/bmi270_core.c

1187

u16 regval;

drivers/iio/imu/bmi270/bmi270_core.c

1193

ret = bmi270_read_feature_reg(data, BMI270_SC_26_REG, &regval);

drivers/iio/imu/bmi270/bmi270_core.c

1197

raw = FIELD_GET(BMI270_STEP_SC26_WTRMRK_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

1208

ret = bmi270_read_feature_reg(data, reg, &regval);

drivers/iio/imu/bmi270/bmi270_core.c

1216

raw = FIELD_GET(BMI270_FEAT_MOTION_THRESHOLD_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

1222

ret = bmi270_read_feature_reg(data, reg, &regval);

drivers/iio/imu/bmi270/bmi270_core.c

1226

raw = FIELD_GET(BMI270_FEAT_MOTION_DURATION_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

176

__le16 regval __aligned(IIO_DMA_MINALIGN);

drivers/iio/imu/bmi270/bmi270_core.c

389

data->regval = cpu_to_le16(val);

drivers/iio/imu/bmi270/bmi270_core.c

390

return regmap_bulk_write(data->regmap, reg->addr, &data->regval,

drivers/iio/imu/bmi270/bmi270_core.c

391

sizeof(data->regval));

drivers/iio/imu/bmi270/bmi270_core.c

405

ret = regmap_bulk_read(data->regmap, reg->addr, &data->regval,

drivers/iio/imu/bmi270/bmi270_core.c

406

sizeof(data->regval));

drivers/iio/imu/bmi270/bmi270_core.c

410

*val = le16_to_cpu(data->regval);

drivers/iio/imu/bmi270/bmi270_core.c

418

u16 regval;

drivers/iio/imu/bmi270/bmi270_core.c

421

ret = bmi270_read_feature_reg(data, id, &regval);

drivers/iio/imu/bmi270/bmi270_core.c

425

regval = (regval & ~mask) | (val & mask);

drivers/iio/imu/bmi270/bmi270_core.c

427

return bmi270_write_feature_reg(data, id, regval);

drivers/iio/imu/bmi270/bmi270_core.c

523

u16 axis_msk, axis_field_val, regval;

drivers/iio/imu/bmi270/bmi270_core.c

533

ret = bmi270_read_feature_reg(data, BMI270_ANYMO1_REG, &regval);

drivers/iio/imu/bmi270/bmi270_core.c

541

axis_en = FIELD_GET(BMI270_FEAT_MOTION_Y_EN_MSK, regval) |

drivers/iio/imu/bmi270/bmi270_core.c

542

FIELD_GET(BMI270_FEAT_MOTION_Z_EN_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

547

axis_en = FIELD_GET(BMI270_FEAT_MOTION_X_EN_MSK, regval) |

drivers/iio/imu/bmi270/bmi270_core.c

548

FIELD_GET(BMI270_FEAT_MOTION_Z_EN_MSK, regval);

drivers/iio/imu/bmi270/bmi270_core.c

553

axis_en = FIELD_GET(BMI270_FEAT_MOTION_X_EN_MSK, regval) |

drivers/iio/imu/bmi270/bmi270_core.c

554

FIELD_GET(BMI270_FEAT_MOTION_Y_EN_MSK, regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

774

unsigned int reg, regval;

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

832

&regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

835

st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

841

&regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

845

st->buffer[1] = ((offset & 0xF00) >> 8) | (regval & 0xF0);

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

850

&regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

853

st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

476

unsigned int reg, regval;

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

534

&regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

538

st->buffer[1] = (regval & 0xF0) | ((offset & 0xF00) >> 8);

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

543

&regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

546

st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

552

&regval);

drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c

556

st->buffer[1] = (regval & 0xF0) | ((offset & 0xF00) >> 8);

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1752

unsigned int regval, mask;

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1764

result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, &regval);

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1767

if (regval != st->hw->whoami) {

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1770

if (regval == hw_info[i].whoami) {

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1773

regval, hw_info[i].name,

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1781

regval, st->hw->whoami, st->hw->name);

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1800

regval = INV_MPU6050_BIT_TEMP_RST | INV_MPU6050_BIT_ACCEL_RST |

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

1803

regval);

drivers/iio/light/adux1020.c

252

unsigned int regval;

drivers/iio/light/adux1020.c

263

&regval);

drivers/iio/light/adux1020.c

267

buf[i] = regval;

drivers/iio/light/adux1020.c

366

unsigned int regval;

drivers/iio/light/adux1020.c

393

ADUX1020_REG_LED_CURRENT, &regval);

drivers/iio/light/adux1020.c

397

regval = regval & ADUX1020_LED_CURRENT_MASK;

drivers/iio/light/adux1020.c

399

*val = adux1020_led_currents[regval][0];

drivers/iio/light/adux1020.c

400

*val2 = adux1020_led_currents[regval][1];

drivers/iio/light/adux1020.c

412

&regval);

drivers/iio/light/adux1020.c

416

regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);

drivers/iio/light/adux1020.c

418

*val = adux1020_rates[regval][0];

drivers/iio/light/adux1020.c

419

*val2 = adux1020_rates[regval][1];

drivers/iio/light/adux1020.c

566

unsigned int regval;

drivers/iio/light/adux1020.c

579

ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, &regval);

drivers/iio/light/adux1020.c

583

return !(regval & mask);

drivers/iio/light/adux1020.c

595

unsigned int regval;

drivers/iio/light/adux1020.c

608

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/light/adux1020.c

612

*val = regval;

drivers/iio/light/apds9999.c

100

u8 regval;

drivers/iio/light/apds9999.c

109

regval = FIELD_PREP(APDS9999_LS_RES_MASK, APDS9999_RES_18BIT) |

drivers/iio/light/apds9999.c

112

regval);

drivers/iio/light/bh1750.c

101

BH1750_CHANGE_INT_TIME_L_BIT | regval);

drivers/iio/light/bh1750.c

79

u8 regval;

drivers/iio/light/bh1750.c

93

regval = (val & chip_info->int_time_high_mask) >> 5;

drivers/iio/light/bh1750.c

95

BH1750_CHANGE_INT_TIME_H_BIT | regval);

drivers/iio/light/bh1750.c

99

regval = val & chip_info->int_time_low_mask;

drivers/iio/light/lv0104cs.c

131

static int lv0104cs_write_reg(struct i2c_client *client, u8 regval)

drivers/iio/light/lv0104cs.c

135

ret = i2c_master_send(client, (char *)&regval, sizeof(regval));

drivers/iio/light/lv0104cs.c

138

if (ret != sizeof(regval))

drivers/iio/light/lv0104cs.c

146

__be16 regval;

drivers/iio/light/lv0104cs.c

149

ret = i2c_master_recv(client, (char *)&regval, sizeof(regval));

drivers/iio/light/lv0104cs.c

152

if (ret != sizeof(regval))

drivers/iio/light/lv0104cs.c

155

*adc_output = be16_to_cpu(regval);

drivers/iio/light/lv0104cs.c

163

u8 regval = LV0104CS_REGVAL_MEASURE;

drivers/iio/light/lv0104cs.c

167

regval |= lv0104cs_scales[lv0104cs->scale].regval;

drivers/iio/light/lv0104cs.c

168

regval |= lv0104cs_int_times[lv0104cs->int_time].regval;

drivers/iio/light/lv0104cs.c

169

ret = lv0104cs_write_reg(lv0104cs->client, regval);

drivers/iio/light/lv0104cs.c

309

lv0104cs_calibscales[index].regval);

drivers/iio/light/lv0104cs.c

49

u8 regval;

drivers/iio/light/lv0104cs.c

499

lv0104cs_calibscales[LV0104CS_CALIBSCALE_UNITY].regval);

drivers/iio/light/max44000.c

201

u16 regval;

drivers/iio/light/max44000.c

213

regval = be16_to_cpu(val);

drivers/iio/light/max44000.c

224

if (regval & MAX44000_ALSDATA_OVERFLOW)

drivers/iio/light/max44000.c

227

return regval << MAX44000_ALSTIM_SHIFT(alstim);

drivers/iio/light/max44000.c

243

unsigned int regval;

drivers/iio/light/max44000.c

246

ret = regmap_read(data->regmap, MAX44000_REG_CFG_TX, &regval);

drivers/iio/light/max44000.c

249

regval &= MAX44000_LED_CURRENT_MASK;

drivers/iio/light/max44000.c

250

if (regval >= 8)

drivers/iio/light/max44000.c

251

regval -= 4;

drivers/iio/light/max44000.c

252

return regval;

drivers/iio/light/max44000.c

261

unsigned int regval;

drivers/iio/light/max44000.c

278

ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, &regval);

drivers/iio/light/max44000.c

282

*val = regval;

drivers/iio/light/max44000.c

491

unsigned int regval;

drivers/iio/light/max44000.c

507

ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, &regval);

drivers/iio/light/max44000.c

510

scan.channels[index] = regval;

drivers/iio/light/opt4060.c

1231

unsigned int regval, dev_id;

drivers/iio/light/opt4060.c

1256

ret = regmap_read(chip->regmap, OPT4060_DEVICE_ID, &regval);

drivers/iio/light/opt4060.c

1261

dev_id = FIELD_GET(OPT4060_DEVICE_ID_MASK, regval);

drivers/iio/light/opt4060.c

223

unsigned int regval;

drivers/iio/light/opt4060.c

227

regval = FIELD_PREP(OPT4060_INT_CTRL_INT_CFG, state);

drivers/iio/light/opt4060.c

229

OPT4060_INT_CTRL_INT_CFG, regval);

drivers/iio/light/opt4060.c

498

unsigned int regval;

drivers/iio/light/opt4060.c

501

regval = FIELD_PREP(OPT4060_CTRL_CONV_TIME_MASK, chip->int_time);

drivers/iio/light/opt4060.c

503

OPT4060_CTRL_CONV_TIME_MASK, regval);

drivers/iio/light/opt4060.c

747

unsigned int regval, fault_count_val;

drivers/iio/light/opt4060.c

762

regval = FIELD_PREP(OPT4060_CTRL_FAULT_COUNT_MASK, fault_count_val);

drivers/iio/light/opt4060.c

764

OPT4060_CTRL_FAULT_COUNT_MASK, regval);

drivers/iio/light/opt4060.c

770

u32 regval;

drivers/iio/light/opt4060.c

772

ret = regmap_read(chip->regmap, OPT4060_INT_CTRL, &regval);

drivers/iio/light/opt4060.c

777

*ch_sel = FIELD_GET(OPT4060_INT_CTRL_THRESH_SEL, regval);

drivers/iio/light/opt4060.c

784

u32 regval;

drivers/iio/light/opt4060.c

786

regval = FIELD_PREP(OPT4060_INT_CTRL_THRESH_SEL, ch_sel);

drivers/iio/light/opt4060.c

788

OPT4060_INT_CTRL_THRESH_SEL, regval);

drivers/iio/light/opt4060.c

797

u32 regval;

drivers/iio/light/opt4060.c

799

ret = regmap_read(chip->regmap, OPT4060_THRESHOLD_LOW, &regval);

drivers/iio/light/opt4060.c

804

*th_lo = opt4060_calc_val_from_th_reg(regval);

drivers/iio/light/opt4060.c

806

ret = regmap_read(chip->regmap, OPT4060_THRESHOLD_HIGH, &regval);

drivers/iio/light/opt4060.c

811

*th_hi = opt4060_calc_val_from_th_reg(regval);

drivers/iio/light/si1145.c

596

static int si1145_scale_from_adcgain(int regval)

drivers/iio/light/si1145.c

598

return 128 >> regval;

drivers/iio/light/vcnl4000.c

334

u16 regval;

drivers/iio/light/vcnl4000.c

391

regval = ret | VCNL4040_PS_CONF2_PS_HD;

drivers/iio/light/vcnl4000.c

392

ret = i2c_smbus_write_word_data(client, VCNL4200_PS_CONF1, regval);

drivers/iio/light/vcnl4000.c

401

regval = ret | VCNL4040_CONF3_PS_SAMPLE_16BITS;

drivers/iio/light/vcnl4000.c

402

ret = i2c_smbus_write_word_data(client, VCNL4200_PS_CONF3, regval);

drivers/iio/light/vcnl4000.c

572

u16 regval;

drivers/iio/light/vcnl4000.c

593

regval = FIELD_PREP(VCNL4040_ALS_CONF_IT, i);

drivers/iio/light/vcnl4000.c

594

regval |= (ret & ~VCNL4040_ALS_CONF_IT);

drivers/iio/light/vcnl4000.c

595

return i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF, regval);

drivers/iio/light/vcnl4000.c

621

u16 regval;

drivers/iio/light/vcnl4000.c

641

regval = (ret & ~VCNL4040_PS_CONF2_PS_IT) |

drivers/iio/light/vcnl4000.c

643

return i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, regval);

drivers/iio/light/vcnl4000.c

674

u16 regval;

drivers/iio/light/vcnl4000.c

697

regval = FIELD_PREP(VCNL4040_ALS_CONF_PERS, i);

drivers/iio/light/vcnl4000.c

698

regval |= (ret & ~VCNL4040_ALS_CONF_PERS);

drivers/iio/light/vcnl4000.c

699

return i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF, regval);

drivers/iio/light/vcnl4000.c

728

u16 regval;

drivers/iio/light/vcnl4000.c

754

regval = FIELD_PREP(VCNL4040_CONF1_PS_PERS, i);

drivers/iio/light/vcnl4000.c

755

regval |= (ret & ~VCNL4040_CONF1_PS_PERS);

drivers/iio/light/vcnl4000.c

756

return i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, regval);

drivers/iio/light/vcnl4000.c

780

u16 regval;

drivers/iio/light/vcnl4000.c

796

regval = FIELD_PREP(VCNL4040_PS_CONF3_MPS, i);

drivers/iio/light/vcnl4000.c

797

regval |= (ret & ~VCNL4040_PS_CONF3_MPS);

drivers/iio/light/vcnl4000.c

798

return i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3, regval);

drivers/iio/light/vcnl4000.c

823

u16 regval;

drivers/iio/light/vcnl4000.c

839

regval = (ret & ~VCNL4040_PS_MS_LED_I);

drivers/iio/light/vcnl4000.c

840

regval |= FIELD_PREP(VCNL4040_PS_MS_LED_I, i);

drivers/iio/light/vcnl4000.c

841

return i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3, regval);

drivers/iio/magnetometer/ak8975.c

544

u8 regval;

drivers/iio/magnetometer/ak8975.c

547

regval = (data->cntl_cache & ~data->def->ctrl_masks[CNTL_MODE]) |

drivers/iio/magnetometer/ak8975.c

550

data->def->ctrl_regs[CNTL], regval);

drivers/iio/magnetometer/ak8975.c

554

data->cntl_cache = regval;

drivers/iio/magnetometer/bmc150_magn.c

91

#define BMC150_MAGN_REGVAL_TO_REPXY(regval) (((regval) * 2) + 1)

drivers/iio/magnetometer/bmc150_magn.c

92

#define BMC150_MAGN_REGVAL_TO_REPZ(regval) ((regval) + 1)

drivers/iio/pressure/rohm-bm1390.c

526

u8 regval;

drivers/iio/pressure/rohm-bm1390.c

528

regval = FIELD_PREP(BM1390_MASK_FIFO_LEN,

drivers/iio/pressure/rohm-bm1390.c

532

BM1390_MASK_FIFO_LEN, regval);

drivers/iio/proximity/irsd200.c

168

unsigned int regval;

drivers/iio/proximity/irsd200.c

184

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/proximity/irsd200.c

190

*val = ((int)regval) * scale;

drivers/iio/proximity/irsd200.c

198

unsigned int regval;

drivers/iio/proximity/irsd200.c

220

regval = val / scale;

drivers/iio/proximity/irsd200.c

222

if (regval >= BIT(8))

drivers/iio/proximity/irsd200.c

225

ret = regmap_write(data->regmap, reg, regval);

drivers/iio/proximity/irsd200.c

253

unsigned int regval;

drivers/iio/proximity/irsd200.c

256

ret = regmap_read(data->regmap, IRS_REG_DATA_RATE, &regval);

drivers/iio/proximity/irsd200.c

262

if (regval >= ARRAY_SIZE(irsd200_data_rates))

drivers/iio/proximity/irsd200.c

265

*val = irsd200_data_rates[regval];

drivers/iio/proximity/irsd200.c

322

unsigned int regval;

drivers/iio/proximity/irsd200.c

335

regval = val * data_rate + (val2 * data_rate) / 1000000;

drivers/iio/proximity/irsd200.c

338

if (regval >= BIT(10))

drivers/iio/proximity/irsd200.c

341

buf = cpu_to_le16((u16)regval);

drivers/iio/proximity/irsd200.c

355

unsigned int regval;

drivers/iio/proximity/irsd200.c

358

ret = regmap_read(data->regmap, IRS_REG_NR_COUNT, &regval);

drivers/iio/proximity/irsd200.c

364

*val = regval;

drivers/iio/proximity/irsd200.c

371

unsigned int regval;

drivers/iio/proximity/irsd200.c

378

regval = val;

drivers/iio/proximity/irsd200.c

380

if (regval >= 2) {

drivers/iio/proximity/irsd200.c

392

regval);

drivers/iio/proximity/irsd200.c

397

ret = regmap_write(data->regmap, IRS_REG_NR_COUNT, regval);

drivers/iio/proximity/irsd200.c

408

unsigned int regval;

drivers/iio/proximity/irsd200.c

411

ret = regmap_field_read(data->regfields[IRS_REGF_LP_FILTER], &regval);

drivers/iio/proximity/irsd200.c

418

*val = irsd200_lp_filter_freq[regval];

drivers/iio/proximity/irsd200.c

449

unsigned int regval;

drivers/iio/proximity/irsd200.c

452

ret = regmap_field_read(data->regfields[IRS_REGF_HP_FILTER], &regval);

drivers/iio/proximity/irsd200.c

459

*val = irsd200_hp_filter_freq[regval][0];

drivers/iio/proximity/irsd200.c

460

*val2 = irsd200_hp_filter_freq[regval][1];

drivers/iio/proximity/srf08.c

261

u8 regval;

drivers/iio/proximity/srf08.c

269

regval = ret;

drivers/iio/proximity/srf08.c

273

ret = i2c_smbus_write_byte_data(client, SRF08_WRITE_RANGE, regval);

drivers/iio/proximity/srf08.c

344

u8 regval;

drivers/iio/proximity/srf08.c

351

regval = i;

drivers/iio/proximity/srf08.c

360

ret = i2c_smbus_write_byte_data(client, SRF08_WRITE_MAX_GAIN, regval);

drivers/iio/proximity/sx9310.c

293

unsigned int regval, gain;

drivers/iio/proximity/sx9310.c

296

ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL3, &regval);

drivers/iio/proximity/sx9310.c

303

gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN0_MASK, regval);

drivers/iio/proximity/sx9310.c

307

gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN12_MASK, regval);

drivers/iio/proximity/sx9310.c

320

unsigned int regval;

drivers/iio/proximity/sx9310.c

323

ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &regval);

drivers/iio/proximity/sx9310.c

327

regval = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, regval);

drivers/iio/proximity/sx9310.c

328

*val = sx9310_samp_freq_table[regval].val;

drivers/iio/proximity/sx9310.c

329

*val2 = sx9310_samp_freq_table[regval].val2;

drivers/iio/proximity/sx9310.c

415

unsigned int regval;

drivers/iio/proximity/sx9310.c

422

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/proximity/sx9310.c

426

regval = FIELD_GET(SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK, regval);

drivers/iio/proximity/sx9310.c

427

if (regval >= ARRAY_SIZE(sx9310_pthresh_codes))

drivers/iio/proximity/sx9310.c

430

*val = sx9310_pthresh_codes[regval];

drivers/iio/proximity/sx9310.c

437

unsigned int regval, pthresh;

drivers/iio/proximity/sx9310.c

444

ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL10, &regval);

drivers/iio/proximity/sx9310.c

448

regval = FIELD_GET(SX9310_REG_PROX_CTRL10_HYST_MASK, regval);

drivers/iio/proximity/sx9310.c

449

if (!regval)

drivers/iio/proximity/sx9310.c

450

regval = 5;

drivers/iio/proximity/sx9310.c

453

*val = pthresh >> (5 - regval);

drivers/iio/proximity/sx9310.c

460

unsigned int regval;

drivers/iio/proximity/sx9310.c

463

ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL10, &regval);

drivers/iio/proximity/sx9310.c

467

regval = FIELD_GET(SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK, regval);

drivers/iio/proximity/sx9310.c

468

if (regval)

drivers/iio/proximity/sx9310.c

469

*val = 1 << regval;

drivers/iio/proximity/sx9310.c

478

unsigned int regval;

drivers/iio/proximity/sx9310.c

481

ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL10, &regval);

drivers/iio/proximity/sx9310.c

485

regval = FIELD_GET(SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK, regval);

drivers/iio/proximity/sx9310.c

486

if (regval)

drivers/iio/proximity/sx9310.c

487

*val = 1 << regval;

drivers/iio/proximity/sx9310.c

528

unsigned int regval;

drivers/iio/proximity/sx9310.c

537

regval = i;

drivers/iio/proximity/sx9310.c

545

regval = FIELD_PREP(SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK, regval);

drivers/iio/proximity/sx9310.c

549

SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK, regval);

drivers/iio/proximity/sx9310.c

582

unsigned int regval;

drivers/iio/proximity/sx9310.c

589

regval = FIELD_PREP(SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK, val);

drivers/iio/proximity/sx9310.c

594

regval);

drivers/iio/proximity/sx9310.c

599

unsigned int regval;

drivers/iio/proximity/sx9310.c

606

regval = FIELD_PREP(SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK, val);

drivers/iio/proximity/sx9310.c

611

regval);

drivers/iio/proximity/sx9324.c

1088

unsigned int regval;

drivers/iio/proximity/sx9324.c

1094

ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL1, &regval);

drivers/iio/proximity/sx9324.c

1099

FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval);

drivers/iio/proximity/sx9324.c

389

unsigned int reg, regval;

drivers/iio/proximity/sx9324.c

393

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/proximity/sx9324.c

397

regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);

drivers/iio/proximity/sx9324.c

398

if (regval)

drivers/iio/proximity/sx9324.c

399

regval--;

drivers/iio/proximity/sx9324.c

400

else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||

drivers/iio/proximity/sx9324.c

401

regval > SX9324_REG_PROX_CTRL0_GAIN_8)

drivers/iio/proximity/sx9324.c

404

*val = 1 << regval;

drivers/iio/proximity/sx9324.c

413

unsigned int regval;

drivers/iio/proximity/sx9324.c

415

ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &regval);

drivers/iio/proximity/sx9324.c

419

regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval);

drivers/iio/proximity/sx9324.c

420

*val = sx9324_samp_freq_table[regval].val;

drivers/iio/proximity/sx9324.c

421

*val2 = sx9324_samp_freq_table[regval].val2;

drivers/iio/proximity/sx9324.c

504

unsigned int regval;

drivers/iio/proximity/sx9324.c

514

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/proximity/sx9324.c

518

if (regval <= 1)

drivers/iio/proximity/sx9324.c

519

*val = regval;

drivers/iio/proximity/sx9324.c

521

*val = (regval * regval) / 2;

drivers/iio/proximity/sx9324.c

529

unsigned int regval, pthresh;

drivers/iio/proximity/sx9324.c

536

ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, &regval);

drivers/iio/proximity/sx9324.c

540

regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval);

drivers/iio/proximity/sx9324.c

541

if (!regval)

drivers/iio/proximity/sx9324.c

544

*val = pthresh >> (5 - regval);

drivers/iio/proximity/sx9324.c

551

unsigned int regval;

drivers/iio/proximity/sx9324.c

554

ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, &regval);

drivers/iio/proximity/sx9324.c

558

regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval);

drivers/iio/proximity/sx9324.c

559

if (regval)

drivers/iio/proximity/sx9324.c

560

*val = 1 << regval;

drivers/iio/proximity/sx9324.c

569

unsigned int regval;

drivers/iio/proximity/sx9324.c

572

ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, &regval);

drivers/iio/proximity/sx9324.c

576

regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval);

drivers/iio/proximity/sx9324.c

577

if (regval)

drivers/iio/proximity/sx9324.c

578

*val = 1 << regval;

drivers/iio/proximity/sx9324.c

663

unsigned int regval, val = _val;

drivers/iio/proximity/sx9324.c

670

regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val);

drivers/iio/proximity/sx9324.c

676

regval);

drivers/iio/proximity/sx9324.c

681

unsigned int regval, val = _val;

drivers/iio/proximity/sx9324.c

688

regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val);

drivers/iio/proximity/sx9324.c

694

regval);

drivers/iio/proximity/sx9360.c

283

unsigned int reg, regval;

drivers/iio/proximity/sx9360.c

287

ret = regmap_read(data->regmap, reg, &regval);

drivers/iio/proximity/sx9360.c

291

*val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval);

drivers/iio/proximity/sx9360.c

399

unsigned int regval;

drivers/iio/proximity/sx9360.c

402

ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, &regval);

drivers/iio/proximity/sx9360.c

406

if (regval <= 1)

drivers/iio/proximity/sx9360.c

407

*val = regval;

drivers/iio/proximity/sx9360.c

409

*val = (regval * regval) / 2;

drivers/iio/proximity/sx9360.c

416

unsigned int regval, pthresh;

drivers/iio/proximity/sx9360.c

423

ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, &regval);

drivers/iio/proximity/sx9360.c

427

regval = FIELD_GET(SX9360_REG_PROX_CTRL4_HYST_MASK, regval);

drivers/iio/proximity/sx9360.c

428

if (!regval)

drivers/iio/proximity/sx9360.c

431

*val = pthresh >> (5 - regval);

drivers/iio/proximity/sx9360.c

438

unsigned int regval;

drivers/iio/proximity/sx9360.c

441

ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, &regval);

drivers/iio/proximity/sx9360.c

445

regval = FIELD_GET(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, regval);

drivers/iio/proximity/sx9360.c

446

if (regval)

drivers/iio/proximity/sx9360.c

447

*val = 1 << regval;

drivers/iio/proximity/sx9360.c

456

unsigned int regval;

drivers/iio/proximity/sx9360.c

459

ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, &regval);

drivers/iio/proximity/sx9360.c

463

regval = FIELD_GET(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, regval);

drivers/iio/proximity/sx9360.c

464

if (regval)

drivers/iio/proximity/sx9360.c

465

*val = 1 << regval;

drivers/iio/proximity/sx9360.c

544

unsigned int regval, val = _val;

drivers/iio/proximity/sx9360.c

551

regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val);

drivers/iio/proximity/sx9360.c

556

regval);

drivers/iio/proximity/sx9360.c

561

unsigned int regval, val = _val;

drivers/iio/proximity/sx9360.c

568

regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val);

drivers/iio/proximity/sx9360.c

573

regval);

drivers/iio/proximity/sx9360.c

797

unsigned int regval;

drivers/iio/proximity/sx9360.c

803

ret = regmap_read(data->regmap, SX9360_REG_GNRL_CTRL0, &regval);

drivers/iio/proximity/sx9360.c

808

FIELD_GET(SX9360_REG_GNRL_CTRL0_PHEN_MASK, regval);

drivers/iio/proximity/sx9500.c

267

__be16 regval;

drivers/iio/proximity/sx9500.c

273

ret = regmap_bulk_read(data->regmap, SX9500_REG_USE_MSB, &regval, 2);

drivers/iio/proximity/sx9500.c

277

*val = be16_to_cpu(regval);

drivers/iio/proximity/sx9500.c

361

unsigned int regval;

drivers/iio/proximity/sx9500.c

364

ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, &regval);

drivers/iio/proximity/sx9500.c

370

regval = (regval & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT;

drivers/iio/proximity/sx9500.c

371

*val = sx9500_samp_freq_table[regval].val;

drivers/iio/proximity/sx9500.c

372

*val2 = sx9500_samp_freq_table[regval].val2;

drivers/iio/temperature/max30208.c

132

u8 regval;

drivers/iio/temperature/max30208.c

139

regval = ret | MAX30208_FIFO_CONFIG_RO;

drivers/iio/temperature/max30208.c

141

ret = i2c_smbus_write_byte_data(data->client, MAX30208_FIFO_CONFIG, regval);

drivers/iio/temperature/max30208.c

60

u8 regval;

drivers/iio/temperature/max30208.c

67

regval = ret | MAX30208_TEMP_SENSOR_SETUP_CONV;

drivers/iio/temperature/max30208.c

69

ret = i2c_smbus_write_byte_data(data->client, MAX30208_TEMP_SENSOR_SETUP, regval);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

236

u32 regval, const char *header,

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

239

bool en = regval & BIT(0);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

242

writel(regval, addr_config);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

243

ret = readl_poll_timeout(addr_status, regval,

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

244

en ? regval & BIT(0) : !(regval & BIT(0)),

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

248

header, en ? "en" : "dis", regval);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

250

WRITE_ONCE(*out_enabled, regval & BIT(0));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

254

static inline int cmdqv_write_config(struct tegra241_cmdqv *cmdqv, u32 regval)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

259

regval, "CMDQV: ", NULL);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

262

static inline int vintf_write_config(struct tegra241_vintf *vintf, u32 regval)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

270

regval, header, &vintf->enabled);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

284

static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

291

regval, h, &vcmdq->enabled);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

506

u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx)));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

509

writel(regval & ~CMDQV_CMDQ_ALLOCATED,

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

536

u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx)));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

539

writel(regval | CMDQV_CMDQ_ALLOCATED,

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

546

u32 regval;

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

559

regval = FIELD_PREP(VINTF_HYP_OWN, hyp_own) |

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

561

writel(regval, REG_VINTF(vintf, CONFIG));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

563

ret = vintf_write_config(vintf, regval | VINTF_EN);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

592

u32 regval;

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

596

regval = readl_relaxed(REG_CMDQV(cmdqv, CONFIG));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

597

ret = cmdqv_write_config(cmdqv, regval & ~CMDQV_EN);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

600

ret = cmdqv_write_config(cmdqv, regval | CMDQV_EN);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

607

regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

608

regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

609

writel_relaxed(regval,

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

625

u32 regval;

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

631

regval = readl_relaxed(smmu->base + ARM_SMMU_IDR1);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

633

min_t(u32, CMDQ_MAX_SZ_SHIFT, FIELD_GET(IDR1_CMDQS, regval));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

817

u32 regval;

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

826

regval = readl_relaxed(REG_CMDQV(cmdqv, PARAM));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

829

info->version = FIELD_GET(CMDQV_VER, regval);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

904

u32 regval;

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

915

regval = readl(base + TEGRA241_CMDQV_CONFIG);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

918

writel(regval & ~CMDQV_EN, base + TEGRA241_CMDQV_CONFIG);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

943

regval = readl_relaxed(REG_CMDQV(cmdqv, PARAM));

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

944

cmdqv->num_vintfs = 1 << FIELD_GET(CMDQV_NUM_VINTF_LOG2, regval);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

945

cmdqv->num_vcmdqs = 1 << FIELD_GET(CMDQV_NUM_VCMDQ_LOG2, regval);

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

948

1 << FIELD_GET(CMDQV_NUM_SID_PER_VM_LOG2, regval);

drivers/iommu/mtk_iommu.c

1082

u32 regval;

drivers/iommu/mtk_iommu.c

1089

regval = F_MMU_PREFETCH_RT_REPLACE_MOD |

drivers/iommu/mtk_iommu.c

1092

regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);

drivers/iommu/mtk_iommu.c

1093

regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;

drivers/iommu/mtk_iommu.c

1095

writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);

drivers/iommu/mtk_iommu.c

1103

regval = F_MMU_VLD_PA_RNG(7, 4);

drivers/iommu/mtk_iommu.c

1104

writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);

drivers/iommu/mtk_iommu.c

1113

regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);

drivers/iommu/mtk_iommu.c

1114

regval &= ~F_MMU_WR_THROT_DIS_MASK;

drivers/iommu/mtk_iommu.c

1115

writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);

drivers/iommu/mtk_iommu.c

1120

regval = 0;

drivers/iommu/mtk_iommu.c

1122

regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);

drivers/iommu/mtk_iommu.c

1124

regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;

drivers/iommu/mtk_iommu.c

1126

regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;

drivers/iommu/mtk_iommu.c

1128

writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);

drivers/iommu/mtk_iommu.c

1131

regval = F_L2_MULIT_HIT_EN |

drivers/iommu/mtk_iommu.c

1137

writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);

drivers/iommu/mtk_iommu.c

1139

regval = F_INT_TRANSLATION_FAULT |

drivers/iommu/mtk_iommu.c

1146

writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);

drivers/iommu/mtk_iommu.c

1149

regval = (data->protect_base >> 1) | (data->enable_4GB << 31);

drivers/iommu/mtk_iommu.c

1151

regval = lower_32_bits(data->protect_base) |

drivers/iommu/mtk_iommu.c

1153

writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);

drivers/iommu/mtk_iommu.c

476

u32 int_state, regval, va34_32, pa34_32;

drivers/iommu/mtk_iommu.c

485

regval = readl_relaxed(base + REG_MMU0_INT_ID);

drivers/iommu/mtk_iommu.c

489

regval = readl_relaxed(base + REG_MMU1_INT_ID);

drivers/iommu/mtk_iommu.c

505

fault_larb = F_MMU_INT_ID_COMM_ID(regval);

drivers/iommu/mtk_iommu.c

506

sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);

drivers/iommu/mtk_iommu.c

507

fault_port = F_MMU_INT_ID_PORT_ID(regval);

drivers/iommu/mtk_iommu.c

509

fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);

drivers/iommu/mtk_iommu.c

510

sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);

drivers/iommu/mtk_iommu.c

511

fault_port = F_MMU_INT_ID_PORT_ID(regval);

drivers/iommu/mtk_iommu.c

513

fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);

drivers/iommu/mtk_iommu.c

514

fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);

drivers/iommu/mtk_iommu.c

516

fault_port = F_MMU_INT_ID_PORT_ID(regval);

drivers/iommu/mtk_iommu.c

517

fault_larb = F_MMU_INT_ID_LARB_ID(regval);

drivers/iommu/mtk_iommu.c

527

int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,

drivers/iommu/mtk_iommu.c

532

regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);

drivers/iommu/mtk_iommu.c

533

regval |= F_INT_CLR_BIT;

drivers/iommu/mtk_iommu.c

534

writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);

drivers/iommu/mtk_iommu_v1.c

208

u32 int_state, regval, fault_iova, fault_pa;

drivers/iommu/mtk_iommu_v1.c

217

regval = readl_relaxed(data->base + REG_MMU_INT_ID);

drivers/iommu/mtk_iommu_v1.c

218

fault_larb = MT2701_M4U_TF_LARB(regval);

drivers/iommu/mtk_iommu_v1.c

219

fault_port = MT2701_M4U_TF_PORT(regval);

drivers/iommu/mtk_iommu_v1.c

233

regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);

drivers/iommu/mtk_iommu_v1.c

234

regval |= F_INT_CLR_BIT;

drivers/iommu/mtk_iommu_v1.c

235

writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);

drivers/iommu/mtk_iommu_v1.c

542

u32 regval;

drivers/iommu/mtk_iommu_v1.c

551

regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);

drivers/iommu/mtk_iommu_v1.c

552

writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);

drivers/iommu/mtk_iommu_v1.c

554

regval = F_INT_TRANSLATION_FAULT |

drivers/iommu/mtk_iommu_v1.c

562

writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);

drivers/leds/flash/leds-mt6360.c

397

unsigned int regval;

drivers/leds/flash/leds-mt6360.c

401

ret = regmap_read(priv->regmap, MT6360_REG_ISNK(led->led_no), &regval);

drivers/leds/flash/leds-mt6360.c

404

level = regval & MT6360_ISNK_MASK;

drivers/leds/flash/leds-mt6360.c

406

ret = regmap_read(priv->regmap, MT6360_REG_RGBEN, &regval);

drivers/leds/flash/leds-mt6360.c

410

if (!(regval & MT6360_ISNK_ENMASK(led->led_no)))

drivers/leds/flash/leds-mt6360.c

433

unsigned int regval;

drivers/leds/flash/leds-mt6360.c

437

&regval);

drivers/leds/flash/leds-mt6360.c

440

level = regval & MT6360_ITORCH_MASK;

drivers/leds/flash/leds-mt6360.c

442

ret = regmap_read(priv->regmap, MT6360_REG_FLEDEN, &regval);

drivers/leds/flash/leds-mt6360.c

446

if ((regval & enable_mask) == enable_mask)

drivers/leds/leds-mlxreg.c

102

u32 regval;

drivers/leds/leds-mlxreg.c

115

err = regmap_read(led_pdata->regmap, data->reg, &regval);

drivers/leds/leds-mlxreg.c

123

regval = regval & ~data->mask;

drivers/leds/leds-mlxreg.c

124

regval = (ror32(data->mask, data->bit) == 0xf0) ? ror32(regval,

drivers/leds/leds-mlxreg.c

125

data->bit) : ror32(regval, data->bit + 4);

drivers/leds/leds-mlxreg.c

126

if (regval >= led_data->base_color &&

drivers/leds/leds-mlxreg.c

127

regval <= (led_data->base_color + MLXREG_LED_OFFSET_BLINK_6HZ))

drivers/leds/leds-mlxreg.c

190

u32 regval;

drivers/leds/leds-mlxreg.c

202

&regval);

drivers/leds/leds-mlxreg.c

207

if (!(regval & data->bit))

drivers/leds/leds-mlxreg.c

64

u32 regval;

drivers/leds/leds-mlxreg.c

80

ret = regmap_read(led_pdata->regmap, data->reg, &regval);

drivers/leds/leds-mlxreg.c

86

regval = (regval & data->mask) | nib;

drivers/leds/leds-mlxreg.c

88

ret = regmap_write(led_pdata->regmap, data->reg, regval);

drivers/media/dvb-frontends/cxd2099.c

133

unsigned int regval;

drivers/media/dvb-frontends/cxd2099.c

138

status = regmap_read(ci->regmap, 1, &regval);

drivers/media/dvb-frontends/cxd2099.c

139

ci->regs[reg] = regval;

drivers/media/dvb-frontends/stv0367.c

2746

u32 regval = 0;

drivers/media/dvb-frontends/stv0367.c

2750

regval += (stv0367_readbits(state, F367CAB_SNR_LO)

drivers/media/dvb-frontends/stv0367.c

2755

regval /= 10;

drivers/media/dvb-frontends/stv0367.c

2757

return regval;

drivers/media/dvb-frontends/stv0367.c

2764

u32 regval = 0, temp = 0;

drivers/media/dvb-frontends/stv0367.c

2768

regval = stv0367cab_snr_readreg(fe, 1);

drivers/media/dvb-frontends/stv0367.c

2770

if (regval != 0) {

drivers/media/dvb-frontends/stv0367.c

2773

temp /= regval;

drivers/media/dvb-frontends/stv0367.c

3027

u32 regval, tmpval, snrval = 0;

drivers/media/dvb-frontends/stv0367.c

3035

regval = stv0367cab_snr_readreg(fe, 0);

drivers/media/dvb-frontends/stv0367.c

3038

if (!regval) {

drivers/media/dvb-frontends/stv0367.c

3043

tmpval = (cab_pwr * 320) / regval;

drivers/media/dvb-frontends/stv0900_core.c

609

if (INRANGE(lookup->table[imin].regval, agc_gain,

drivers/media/dvb-frontends/stv0900_core.c

610

lookup->table[imax].regval)) {

drivers/media/dvb-frontends/stv0900_core.c

614

if (INRANGE(lookup->table[imin].regval,

drivers/media/dvb-frontends/stv0900_core.c

616

lookup->table[i].regval))

drivers/media/dvb-frontends/stv0900_core.c

622

rf_lvl = (s32)agc_gain - lookup->table[imin].regval;

drivers/media/dvb-frontends/stv0900_core.c

625

rf_lvl /= (lookup->table[imax].regval -

drivers/media/dvb-frontends/stv0900_core.c

626

lookup->table[imin].regval);

drivers/media/dvb-frontends/stv0900_core.c

628

} else if (agc_gain > lookup->table[0].regval)

drivers/media/dvb-frontends/stv0900_core.c

630

else if (agc_gain < lookup->table[lookup->size-1].regval)

drivers/media/dvb-frontends/stv0900_core.c

665

regval,

drivers/media/dvb-frontends/stv0900_core.c

684

regval = 0;

drivers/media/dvb-frontends/stv0900_core.c

687

regval += MAKEWORD(stv0900_get_bits(intp,

drivers/media/dvb-frontends/stv0900_core.c

694

regval /= 16;

drivers/media/dvb-frontends/stv0900_core.c

697

if (INRANGE(lookup->table[imin].regval,

drivers/media/dvb-frontends/stv0900_core.c

698

regval,

drivers/media/dvb-frontends/stv0900_core.c

699

lookup->table[imax].regval)) {

drivers/media/dvb-frontends/stv0900_core.c

702

if (INRANGE(lookup->table[imin].regval,

drivers/media/dvb-frontends/stv0900_core.c

703

regval,

drivers/media/dvb-frontends/stv0900_core.c

704

lookup->table[i].regval))

drivers/media/dvb-frontends/stv0900_core.c

710

c_n = ((regval - lookup->table[imin].regval)

drivers/media/dvb-frontends/stv0900_core.c

713

/ (lookup->table[imax].regval

drivers/media/dvb-frontends/stv0900_core.c

714

- lookup->table[imin].regval))

drivers/media/dvb-frontends/stv0900_core.c

716

} else if (regval < lookup->table[imin].regval)

drivers/media/dvb-frontends/stv0900_priv.h

48

s32 regval;/* binary value */

drivers/media/dvb-frontends/stv6111.c

348

u8 regval;

drivers/media/dvb-frontends/stv6111.c

350

status = read_reg(state, 9, &regval);

drivers/media/dvb-frontends/stv6111.c

354

if ((regval & mask) == 0)

drivers/media/i2c/adv748x/adv748x-core.c

500

u8 regval = 0;

drivers/media/i2c/adv748x/adv748x-core.c

534

regval |= ADV748X_IO_10_CSI4_EN;

drivers/media/i2c/adv748x/adv748x-core.c

538

regval |= ADV748X_IO_10_CSI1_EN;

drivers/media/i2c/adv748x/adv748x-core.c

541

io_write(state, ADV748X_IO_10, regval);

drivers/media/i2c/gc0308.c

1067

gc0308->mode.out_format = gc0308_formats[i].regval;

drivers/media/i2c/gc0308.c

1287

u64 regval;

drivers/media/i2c/gc0308.c

1360

ret = cci_read(gc0308->regmap, GC0308_CHIP_ID, &regval, NULL);

drivers/media/i2c/gc0308.c

1366

if (regval != 0x9b) {

drivers/media/i2c/gc0308.c

1368

dev_err_probe(dev, ret, "invalid chip ID (%02llx)\n", regval);

drivers/media/i2c/gc0308.c

388

u8 regval;

drivers/media/i2c/gc0308.c

392

{ .code = v4l2_code, .regval = gc0308_regval }

drivers/media/i2c/gc0308.c

907

u8 regval = 0x00;

drivers/media/i2c/gc0308.c

910

regval |= BIT(1);

drivers/media/i2c/gc0308.c

913

regval |= BIT(0);

drivers/media/i2c/gc0308.c

916

GENMASK(1, 0), regval, NULL);

drivers/media/i2c/max2175.c

318

u32 regval;

drivers/media/i2c/max2175.c

321

ret = regmap_read(ctx->regmap, idx, &regval);

drivers/media/i2c/max2175.c

325

*val = regval;

drivers/media/i2c/ov2685.c

110

static struct regval ov2685_1600x1200_regs[] = {

drivers/media/i2c/ov2685.c

286

const struct regval *regs)

drivers/media/i2c/ov2685.c

85

const struct regval *reg_list;

drivers/media/i2c/ov5695.c

126

static const struct regval ov5695_global_regs[] = {

drivers/media/i2c/ov5695.c

301

static const struct regval ov5695_2592x1944_regs[] = {

drivers/media/i2c/ov5695.c

343

static const struct regval ov5695_1920x1080_regs[] = {

drivers/media/i2c/ov5695.c

385

static const struct regval ov5695_1296x972_regs[] = {

drivers/media/i2c/ov5695.c

568

static const struct regval ov5695_1280x720_regs[] = {

drivers/media/i2c/ov5695.c

610

static const struct regval ov5695_640x480_regs[] = {

drivers/media/i2c/ov5695.c

733

const struct regval *regs)

drivers/media/i2c/ov5695.c

92

const struct regval *reg_list;

drivers/media/i2c/ov8858.c

1130

static const struct regval ov8858_1632x1224_regs_4lane[] = {

drivers/media/i2c/ov8858.c

1168

static const struct regval ov8858_3264x2448_regs_4lane[] = {

drivers/media/i2c/ov8858.c

119

const struct regval *global_regs;

drivers/media/i2c/ov8858.c

1269

static int ov8858_write_array(struct ov8858 *ov8858, const struct regval *regs)

drivers/media/i2c/ov8858.c

129

static const struct regval ov8858_global_regs_r1a[] = {

drivers/media/i2c/ov8858.c

1328

const struct regval *reg_list;

drivers/media/i2c/ov8858.c

399

static const struct regval ov8858_global_regs_r2a_2lane[] = {

drivers/media/i2c/ov8858.c

725

static const struct regval ov8858_1632x1224_regs_2lane[] = {

drivers/media/i2c/ov8858.c

770

static const struct regval ov8858_3264x2448_regs_2lane[] = {

drivers/media/i2c/ov8858.c

803

static const struct regval ov8858_global_regs_r2a_4lane[] = {

drivers/media/i2c/ov8858.c

92

const struct regval *mode_2lanes;

drivers/media/i2c/ov8858.c

93

const struct regval *mode_4lanes;

drivers/media/i2c/tw9900.c

106

static const struct regval tw9900_pal_regs[] = {

drivers/media/i2c/tw9900.c

110

static const struct regval tw9900_ntsc_regs[] = {

drivers/media/i2c/tw9900.c

149

const struct regval *regs, int n_regs)

drivers/media/i2c/tw9900.c

69

const struct regval *reg_list;

drivers/media/i2c/tw9900.c

91

static const struct regval tw9900_init_regs[] = {

drivers/media/pci/cx23885/cx23885-417.c

275

u32 regval;

drivers/media/pci/cx23885/cx23885-417.c

280

regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |

drivers/media/pci/cx23885/cx23885-417.c

283

cx_write(MC417_CTL, regval);

drivers/media/pci/cx23885/cx23885-417.c

286

regval = MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

287

cx_write(MC417_OEN, regval);

drivers/media/pci/cx23885/cx23885-417.c

290

regval = MC417_MIWR | MC417_MIRD | MC417_MICS;

drivers/media/pci/cx23885/cx23885-417.c

291

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

311

u32 regval;

drivers/media/pci/cx23885/cx23885-417.c

319

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |

drivers/media/pci/cx23885/cx23885-417.c

321

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

324

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

325

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

328

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |

drivers/media/pci/cx23885/cx23885-417.c

330

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

331

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

332

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

335

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |

drivers/media/pci/cx23885/cx23885-417.c

337

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

338

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

339

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

342

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |

drivers/media/pci/cx23885/cx23885-417.c

344

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

345

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

346

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

349

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |

drivers/media/pci/cx23885/cx23885-417.c

351

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

352

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

353

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

356

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |

drivers/media/pci/cx23885/cx23885-417.c

358

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

359

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

360

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

363

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |

drivers/media/pci/cx23885/cx23885-417.c

365

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

366

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

367

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

376

u32 regval;

drivers/media/pci/cx23885/cx23885-417.c

386

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |

drivers/media/pci/cx23885/cx23885-417.c

388

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

389

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

390

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

393

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |

drivers/media/pci/cx23885/cx23885-417.c

395

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

396

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

397

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

400

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |

drivers/media/pci/cx23885/cx23885-417.c

402

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

403

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

404

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

413

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;

drivers/media/pci/cx23885/cx23885-417.c

414

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

421

regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;

drivers/media/pci/cx23885/cx23885-417.c

422

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

429

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

430

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

433

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;

drivers/media/pci/cx23885/cx23885-417.c

434

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

435

regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;

drivers/media/pci/cx23885/cx23885-417.c

436

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

439

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

440

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

443

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;

drivers/media/pci/cx23885/cx23885-417.c

444

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

445

regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;

drivers/media/pci/cx23885/cx23885-417.c

446

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

449

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

450

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

453

regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;

drivers/media/pci/cx23885/cx23885-417.c

454

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

455

regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;

drivers/media/pci/cx23885/cx23885-417.c

456

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

459

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

460

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

469

u32 regval;

drivers/media/pci/cx23885/cx23885-417.c

477

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |

drivers/media/pci/cx23885/cx23885-417.c

479

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

482

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

483

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

486

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |

drivers/media/pci/cx23885/cx23885-417.c

488

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

489

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

490

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

493

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |

drivers/media/pci/cx23885/cx23885-417.c

495

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

496

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

497

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

500

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |

drivers/media/pci/cx23885/cx23885-417.c

502

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

503

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

504

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

507

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |

drivers/media/pci/cx23885/cx23885-417.c

509

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

510

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

511

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

514

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |

drivers/media/pci/cx23885/cx23885-417.c

516

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

517

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

518

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

521

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |

drivers/media/pci/cx23885/cx23885-417.c

523

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

524

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

525

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

534

u32 regval;

drivers/media/pci/cx23885/cx23885-417.c

544

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |

drivers/media/pci/cx23885/cx23885-417.c

546

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

547

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

548

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

551

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |

drivers/media/pci/cx23885/cx23885-417.c

553

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

554

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

555

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

558

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |

drivers/media/pci/cx23885/cx23885-417.c

560

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

561

regval |= MC417_MICS | MC417_MIWR;

drivers/media/pci/cx23885/cx23885-417.c

562

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

571

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;

drivers/media/pci/cx23885/cx23885-417.c

572

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

575

regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;

drivers/media/pci/cx23885/cx23885-417.c

576

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

583

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

584

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

587

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;

drivers/media/pci/cx23885/cx23885-417.c

588

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

589

regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;

drivers/media/pci/cx23885/cx23885-417.c

590

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

593

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

594

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

597

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;

drivers/media/pci/cx23885/cx23885-417.c

598

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

599

regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;

drivers/media/pci/cx23885/cx23885-417.c

600

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

603

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

604

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

607

regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;

drivers/media/pci/cx23885/cx23885-417.c

608

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

609

regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;

drivers/media/pci/cx23885/cx23885-417.c

610

cx_write(MC417_RWD, regval);

drivers/media/pci/cx23885/cx23885-417.c

613

regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;

drivers/media/pci/cx23885/cx23885-417.c

614

cx_write(MC417_RWD, regval);

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

143

u32 regval;

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

146

regval = readl(reg);

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

147

return regval;

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

152

u32 regval;

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

154

regval = readl(reg + GLB_CTRL);

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

155

writel(GLB_CTRL_SLOT_EN(slot) | regval, reg + GLB_CTRL);

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

160

u32 regval;

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

162

regval = readl(reg + GLB_CTRL);

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

163

regval &= ~GLB_CTRL_L_ENDIAN(1); /* clear */

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

164

writel(GLB_CTRL_L_ENDIAN(le) | regval, reg + GLB_CTRL); /* set */

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c

2900

u32 regval;

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c

2902

regval = readl(reg + GLB_CTRL);

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c

2903

return GLB_CTRL_CUR_VERSION(regval);

drivers/media/rc/meson-ir.c

244

u32 regval;

drivers/media/rc/meson-ir.c

269

regmap_read(ir->reg, IR_DEC_STATUS, &regval);

drivers/media/rc/meson-ir.c

270

regmap_read(ir->reg, IR_DEC_FRAME, &regval);

drivers/media/rc/meson-ir.c

278

regval = FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE - 1);

drivers/media/rc/meson-ir.c

279

regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval);

drivers/media/rc/meson-ir.c

286

regval = FIELD_PREP(IR_DEC_REG2_MODE, timings->hw_protocol);

drivers/media/rc/meson-ir.c

287

regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval);

drivers/media/rc/meson-ir.c

322

regval = FIELD_PREP(IR_DEC_REG0_FRAME_TIME_MAX,

drivers/media/rc/meson-ir.c

325

regval);

drivers/media/rc/meson-ir.c

328

regval = FIELD_PREP(IR_DEC_REG1_FRAME_LEN, timings->code_length - 1);

drivers/media/rc/meson-ir.c

329

regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);

drivers/media/rc/meson-ir.c

332

regval = FIELD_PREP(IR_DEC_LDR_ACTIVE_MAX,

drivers/media/rc/meson-ir.c

337

IR_DEC_LDR_ACTIVE_MIN, regval);

drivers/media/rc/meson-ir.c

340

regval = FIELD_PREP(IR_DEC_LDR_IDLE_MAX, timings->leader_idle_max) |

drivers/media/rc/meson-ir.c

343

IR_DEC_LDR_IDLE_MAX | IR_DEC_LDR_IDLE_MIN, regval);

drivers/media/rc/meson-ir.c

346

regval = FIELD_PREP(IR_DEC_LDR_REPEAT_MAX, timings->repeat_leader_max) |

drivers/media/rc/meson-ir.c

349

IR_DEC_LDR_REPEAT_MIN, regval);

drivers/media/rc/meson-ir.c

355

regval = FIELD_PREP(IR_DEC_BIT_0_MAX, timings->bit0_max) |

drivers/media/rc/meson-ir.c

358

IR_DEC_BIT_0_MAX | IR_DEC_BIT_0_MIN, regval);

drivers/media/rc/meson-ir.c

364

regval = FIELD_PREP(IR_DEC_STATUS_BIT_1_MAX, timings->bit1_max) |

drivers/media/rc/meson-ir.c

367

IR_DEC_STATUS_BIT_1_MIN, regval);

drivers/media/rc/meson-ir.c

378

regval = FIELD_PREP(IR_DEC_DURATN2_MAX, timings->duration2_max) |

drivers/media/rc/meson-ir.c

381

IR_DEC_DURATN2_MAX | IR_DEC_DURATN2_MIN, regval);

drivers/media/rc/meson-ir.c

387

regval = FIELD_PREP(IR_DEC_DURATN3_MAX, timings->duration3_max) |

drivers/media/rc/meson-ir.c

390

IR_DEC_DURATN3_MAX | IR_DEC_DURATN3_MIN, regval);

drivers/media/tuners/xc5000.c

636

u16 regval;

drivers/media/tuners/xc5000.c

678

if (!xc5000_readreg(priv, priv->pll_register_no, &regval))

drivers/media/tuners/xc5000.c

679

dprintk(1, "*** PLL lock status = 0x%04x\n", regval);

drivers/media/usb/em28xx/em28xx-input.c

502

int regval;

drivers/media/usb/em28xx/em28xx-input.c

509

regval = em28xx_read_reg(dev, dev->button_polling_addresses[i]);

drivers/media/usb/em28xx/em28xx-input.c

510

if (regval < 0)

drivers/media/usb/em28xx/em28xx-input.c

526

is_pressed = regval & button->mask;

drivers/media/usb/em28xx/em28xx-input.c

536

(~regval & button->mask)

drivers/media/usb/em28xx/em28xx-input.c

537

| (regval & ~button->mask));

drivers/media/usb/em28xx/em28xx-input.c

568

dev->button_polling_last_values[i] = regval;

drivers/media/usb/stk1160/stk1160-core.c

122

static const struct regval ctl[] = {

drivers/media/usb/stk1160/stk1160-v4l.c

71

static struct regval std525[] = {

drivers/media/usb/stk1160/stk1160-v4l.c

90

static struct regval std625[] = {

drivers/memory/omap-gpmc.c

1100

u32 regval;

drivers/memory/omap-gpmc.c

1104

regval = gpmc_read_reg(GPMC_CONFIG);

drivers/memory/omap-gpmc.c

1106

regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */

drivers/memory/omap-gpmc.c

1108

regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */

drivers/memory/omap-gpmc.c

1109

gpmc_write_reg(GPMC_CONFIG, regval);

drivers/memory/omap-gpmc.c

1292

u32 regval;

drivers/memory/omap-gpmc.c

1298

regval = gpmc_read_reg(GPMC_IRQENABLE);

drivers/memory/omap-gpmc.c

1300

regval |= BIT(hwirq);

drivers/memory/omap-gpmc.c

1302

regval &= ~BIT(hwirq);

drivers/memory/omap-gpmc.c

1303

gpmc_write_reg(GPMC_IRQENABLE, regval);

drivers/memory/omap-gpmc.c

1330

u32 regval;

drivers/memory/omap-gpmc.c

1339

regval = gpmc_read_reg(GPMC_CONFIG);

drivers/memory/omap-gpmc.c

1341

regval &= ~BIT(hwirq);

drivers/memory/omap-gpmc.c

1343

regval |= BIT(hwirq);

drivers/memory/omap-gpmc.c

1345

gpmc_write_reg(GPMC_CONFIG, regval);

drivers/memory/omap-gpmc.c

1403

u32 regval, regvalx;

drivers/memory/omap-gpmc.c

1406

regval = gpmc_read_reg(GPMC_IRQSTATUS);

drivers/memory/omap-gpmc.c

1407

regvalx = regval;

drivers/memory/omap-gpmc.c

1409

if (!regval)

drivers/memory/omap-gpmc.c

1429

gpmc_write_reg(GPMC_IRQSTATUS, regval);

drivers/memory/omap-gpmc.c

1436

u32 regval;

drivers/memory/omap-gpmc.c

1443

regval = gpmc_read_reg(GPMC_IRQSTATUS);

drivers/memory/omap-gpmc.c

1444

gpmc_write_reg(GPMC_IRQSTATUS, regval);

drivers/mfd/tps6105x.c

35

unsigned int regval;

drivers/mfd/tps6105x.c

37

ret = regmap_read(tps6105x->regmap, TPS6105X_REG_0, &regval);

drivers/mfd/tps6105x.c

40

switch (regval >> TPS6105X_REG0_MODE_SHIFT) {

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

100

u32 regval;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

109

ret = read_poll_timeout(readl, regval, !(regval & EEPROM_CMD_EPC_BUSY_BIT),

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

114

if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT)))

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

126

u32 regval;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

144

ret = read_poll_timeout(readl, regval,

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

145

!(regval & EEPROM_CMD_EPC_BUSY_BIT),

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

149

if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) {

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

167

u32 regval;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

183

regval = EEPROM_CMD_EPC_TIMEOUT_BIT | EEPROM_CMD_EPC_WRITE |

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

185

writel(regval, rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

186

writel(EEPROM_CMD_EPC_BUSY_BIT | regval,

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

189

ret = read_poll_timeout(readl, regval,

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

190

!(regval & EEPROM_CMD_EPC_BUSY_BIT),

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

194

if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) {

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

221

u32 regval;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

245

ret = read_poll_timeout(readl, regval,

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

246

!(regval & OTP_STATUS_BUSY_BIT),

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

270

u32 regval;

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

303

ret = read_poll_timeout(readl, regval,

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

304

!(regval & OTP_STATUS_BUSY_BIT),

drivers/mmc/host/dw_mmc-hi3798mv200.c

117

regval = mci_readl(host, TUNING_CTRL);

drivers/mmc/host/dw_mmc-hi3798mv200.c

118

if (err || (regval & SDMMC_TUNING_FIND_EDGE))

drivers/mmc/host/dw_mmc-hi3798mv200.c

98

int regval;

drivers/mmc/host/meson-gx-mmc.c

1078

u32 regval;

drivers/mmc/host/meson-gx-mmc.c

1080

regval = readl(host->regs + SD_EMMC_STATUS);

drivers/mmc/host/meson-gx-mmc.c

1083

return !(FIELD_GET(STATUS_DATI, regval) & 0xf);

drivers/mmc/host/mtk-sd.c

2247

u32 regval = readl(host->top_base + EMMC_TOP_CMD);

drivers/mmc/host/mtk-sd.c

2249

regval &= ~(PAD_CMD_RXDLY | PAD_CMD_RXDLY2);

drivers/mmc/host/mtk-sd.c

2252

regval |= FIELD_PREP(PAD_CMD_RXDLY, value);

drivers/mmc/host/mtk-sd.c

2254

regval |= FIELD_PREP(PAD_CMD_RXDLY, PAD_DELAY_HALF - 1);

drivers/mmc/host/mtk-sd.c

2255

regval |= FIELD_PREP(PAD_CMD_RXDLY2, value - PAD_DELAY_HALF);

drivers/mmc/host/mtk-sd.c

2257

writel(regval, host->top_base + EMMC_TOP_CMD);

drivers/mmc/host/mtk-sd.c

2277

u32 regval = readl(host->top_base + EMMC_TOP_CONTROL);

drivers/mmc/host/mtk-sd.c

2279

regval &= ~(PAD_DAT_RD_RXDLY | PAD_DAT_RD_RXDLY2);

drivers/mmc/host/mtk-sd.c

2282

regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, value);

drivers/mmc/host/mtk-sd.c

2283

regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value);

drivers/mmc/host/mtk-sd.c

2285

regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);

drivers/mmc/host/mtk-sd.c

2286

regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);

drivers/mmc/host/mtk-sd.c

2288

writel(regval, host->top_base + EMMC_TOP_CONTROL);

drivers/mmc/host/omap_hsmmc.c

536

unsigned long regval;

drivers/mmc/host/omap_hsmmc.c

544

regval = OMAP_HSMMC_READ(host->base, SYSCTL);

drivers/mmc/host/omap_hsmmc.c

545

regval = regval & ~(CLKD_MASK | DTO_MASK);

drivers/mmc/host/omap_hsmmc.c

547

regval = regval | (clkdiv << 6) | (DTO << 16);

drivers/mmc/host/omap_hsmmc.c

548

OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);

drivers/mmc/host/omap_hsmmc.c

571

regval = OMAP_HSMMC_READ(host->base, HCTL);

drivers/mmc/host/omap_hsmmc.c

573

regval |= HSPE;

drivers/mmc/host/omap_hsmmc.c

575

regval &= ~HSPE;

drivers/mmc/host/omap_hsmmc.c

577

OMAP_HSMMC_WRITE(host->base, HCTL, regval);

drivers/mmc/host/owl-mmc.c

122

unsigned int regval;

drivers/mmc/host/owl-mmc.c

124

regval = readl(reg);

drivers/mmc/host/owl-mmc.c

127

regval |= val;

drivers/mmc/host/owl-mmc.c

129

regval &= ~val;

drivers/mmc/host/owl-mmc.c

131

writel(regval, reg);

drivers/mmc/host/sdhci-of-arasan.c

1005

u32 regval;

drivers/mmc/host/sdhci-of-arasan.c

1007

regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

1008

regval |= SDHCI_ITAPDLY_CHGWIN;

drivers/mmc/host/sdhci-of-arasan.c

1009

sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

1010

regval |= SDHCI_ITAPDLY_ENABLE;

drivers/mmc/host/sdhci-of-arasan.c

1011

sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

1012

regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1013

regval |= tap_delay;

drivers/mmc/host/sdhci-of-arasan.c

1014

sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

1015

regval &= ~SDHCI_ITAPDLY_CHGWIN;

drivers/mmc/host/sdhci-of-arasan.c

1016

sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

1054

u32 regval;

drivers/mmc/host/sdhci-of-arasan.c

1056

regval = sdhci_readl(host, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1057

regval |= PHY_CTRL_OTAPDLY_ENA_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1058

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1059

regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1060

regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;

drivers/mmc/host/sdhci-of-arasan.c

1061

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1080

u32 regval;

drivers/mmc/host/sdhci-of-arasan.c

1089

regval = sdhci_readl(host, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1090

regval &= ~PHY_CTRL_STRB_SEL_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1091

regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;

drivers/mmc/host/sdhci-of-arasan.c

1092

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1102

regval = sdhci_readl(host, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1103

regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1104

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1105

regval |= PHY_CTRL_ITAPDLY_ENA_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1106

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1107

regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1108

regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;

drivers/mmc/host/sdhci-of-arasan.c

1109

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

1110

regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;

drivers/mmc/host/sdhci-of-arasan.c

1111

sdhci_writel(host, regval, PHY_CTRL_REG1);

drivers/mmc/host/sdhci-of-arasan.c

938

u32 regval;

drivers/mmc/host/sdhci-of-arasan.c

940

regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

941

regval |= SDHCI_OTAPDLY_ENABLE;

drivers/mmc/host/sdhci-of-arasan.c

942

sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);

drivers/mmc/host/sdhci-of-arasan.c

943

regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;

drivers/mmc/host/sdhci-of-arasan.c

944

regval |= tap_delay;

drivers/mmc/host/sdhci-of-arasan.c

945

sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);

drivers/net/ethernet/amd/sunlance.c

464

u16 regval = 0;

drivers/net/ethernet/amd/sunlance.c

475

regval = sbus_readw(lp->lregs + RDP);

drivers/net/ethernet/amd/sunlance.c

477

if (regval & (LE_C0_ERR | LE_C0_IDON))

drivers/net/ethernet/amd/sunlance.c

481

if (i == 100 || (regval & LE_C0_ERR)) {

drivers/net/ethernet/amd/sunlance.c

483

i, regval);

drivers/net/ethernet/amd/sunlance.c

924

u32 regval = lp->init_block_dvma & 0xff000000;

drivers/net/ethernet/amd/sunlance.c

926

sbus_writel(regval, lp->dregs + DMA_TEST);

drivers/net/ethernet/broadcom/sb1250-mac.c

427

int regval;

drivers/net/ethernet/broadcom/sb1250-mac.c

475

regval = 0;

drivers/net/ethernet/broadcom/sb1250-mac.c

478

regval <<= 1;

drivers/net/ethernet/broadcom/sb1250-mac.c

482

regval |= 1;

drivers/net/ethernet/broadcom/sb1250-mac.c

494

return regval;

drivers/net/ethernet/broadcom/sb1250-mac.c

515

u16 regval)

drivers/net/ethernet/broadcom/sb1250-mac.c

528

sbmac_mii_senddata(sbm_mdio, regval, 16);

drivers/net/ethernet/cadence/macb_ptp.c

412

u32 regval;

drivers/net/ethernet/cadence/macb_ptp.c

450

regval = macb_readl(bp, NCR);

drivers/net/ethernet/cadence/macb_ptp.c

451

macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM)));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

72

u32 regval;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

75

pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

76

if (regval & CN23XX_CONFIG_PCIE_DEVCTL_MASK) {

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

89

regval, uncorrectable_err_mask,

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

93

regval |= 0xf; /* Enable Link error reporting */

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

97

pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval);

drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

3625

__be32 regval;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3565

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3577

ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3579

ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3596

ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3598

ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3607

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3621

hsfsts.regval & 0xFFFF);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3623

ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3647

hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3649

hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3653

ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3655

ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3659

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3768

hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3772

ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3798

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3844

hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;

drivers/net/ethernet/intel/e1000e/ich8lan.c

3852

ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);

drivers/net/ethernet/intel/e1000e/ich8lan.c

3873

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4317

pr0.regval = er32flash(ICH_FLASH_PR0);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4321

ew32flash(ICH_FLASH_PR0, pr0.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4328

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4330

ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4375

hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;

drivers/net/ethernet/intel/e1000e/ich8lan.c

4377

hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4387

ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4389

ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4414

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4461

hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)

drivers/net/ethernet/intel/e1000e/ich8lan.c

4464

hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4474

ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4476

ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4497

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4613

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4666

hsflctl.regval =

drivers/net/ethernet/intel/e1000e/ich8lan.c

4669

hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4674

hsflctl.regval << 16);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4676

ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);

drivers/net/ethernet/intel/e1000e/ich8lan.c

4693

hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);

drivers/net/ethernet/intel/e1000e/ich8lan.c

57

u16 regval;

drivers/net/ethernet/intel/e1000e/ich8lan.c

70

u16 regval;

drivers/net/ethernet/intel/e1000e/ich8lan.c

81

u16 regval;

drivers/net/ethernet/intel/e1000e/ich8lan.c

94

u32 regval;

drivers/net/ethernet/intel/e1000e/netdev.c

3619

u32 regval;

drivers/net/ethernet/intel/e1000e/netdev.c

3714

regval = er32(TSYNCTXCTL);

drivers/net/ethernet/intel/e1000e/netdev.c

3715

regval &= ~E1000_TSYNCTXCTL_ENABLED;

drivers/net/ethernet/intel/e1000e/netdev.c

3716

regval |= tsync_tx_ctl;

drivers/net/ethernet/intel/e1000e/netdev.c

3717

ew32(TSYNCTXCTL, regval);

drivers/net/ethernet/intel/e1000e/netdev.c

3719

(regval & E1000_TSYNCTXCTL_ENABLED)) {

drivers/net/ethernet/intel/e1000e/netdev.c

3726

regval = er32(TSYNCRXCTL);

drivers/net/ethernet/intel/e1000e/netdev.c

3727

regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);

drivers/net/ethernet/intel/e1000e/netdev.c

3728

regval |= tsync_rx_ctl;

drivers/net/ethernet/intel/e1000e/netdev.c

3729

ew32(TSYNCRXCTL, regval);

drivers/net/ethernet/intel/e1000e/netdev.c

3732

(regval & (E1000_TSYNCRXCTL_ENABLED |

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1174

u32 tsyntype, regval;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1177

regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1179

regval &= 0;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1180

regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1182

wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1185

regval = rd32(hw, I40E_PRTTSYN_CTL0);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1186

regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1187

wr32(hw, I40E_PRTTSYN_CTL0, regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1263

regval = rd32(hw, I40E_PRTTSYN_CTL0);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1265

regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1267

regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1268

wr32(hw, I40E_PRTTSYN_CTL0, regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1270

regval = rd32(hw, I40E_PFINT_ICR0_ENA);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1272

regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1274

regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1275

wr32(hw, I40E_PFINT_ICR0_ENA, regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1283

regval = rd32(hw, I40E_PRTTSYN_CTL1);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1285

regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1287

regval |= tsyntype;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1288

wr32(hw, I40E_PRTTSYN_CTL1, regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1504

u32 regval;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1511

regval = rd32(hw, I40E_PRTTSYN_CTL0);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1512

regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1513

wr32(hw, I40E_PRTTSYN_CTL0, regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1514

regval = rd32(hw, I40E_PRTTSYN_CTL1);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1515

regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1516

wr32(hw, I40E_PRTTSYN_CTL1, regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1542

u32 regval;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1569

regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1570

regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1571

wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1574

regval = rd32(hw, I40E_PRTTSYN_CTL0);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1575

regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK;

drivers/net/ethernet/intel/i40e/i40e_ptp.c

1576

wr32(hw, I40E_PRTTSYN_CTL0, regval);

drivers/net/ethernet/intel/ice/ice_base.c

225

u32 regval = rd32(hw, GLINT_CTL);

drivers/net/ethernet/intel/ice/ice_base.c

228

if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&

drivers/net/ethernet/intel/ice/ice_base.c

229

(FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) &&

drivers/net/ethernet/intel/ice/ice_base.c

230

(FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) &&

drivers/net/ethernet/intel/ice/ice_base.c

231

(FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) &&

drivers/net/ethernet/intel/ice/ice_base.c

232

(FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US))

drivers/net/ethernet/intel/ice/ice_base.c

235

regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) |

drivers/net/ethernet/intel/ice/ice_base.c

239

wr32(hw, GLINT_CTL, regval);

drivers/net/ethernet/intel/ice/ice_lib.c

1787

int regval = rd32(hw, QRXFLXP_CNTXT(pf_q));

drivers/net/ethernet/intel/ice/ice_lib.c

1790

regval &= ~(QRXFLXP_CNTXT_RXDID_IDX_M |

drivers/net/ethernet/intel/ice/ice_lib.c

1794

regval |= FIELD_PREP(QRXFLXP_CNTXT_RXDID_IDX_M, rxdid);

drivers/net/ethernet/intel/ice/ice_lib.c

1795

regval |= FIELD_PREP(QRXFLXP_CNTXT_RXDID_PRIO_M, prio);

drivers/net/ethernet/intel/ice/ice_lib.c

1799

regval |= QRXFLXP_CNTXT_TS_M;

drivers/net/ethernet/intel/ice/ice_lib.c

1801

wr32(hw, QRXFLXP_CNTXT(pf_q), regval);

drivers/net/ethernet/intel/ice/ice_lib.c

4096

u32 regval;

drivers/net/ethernet/intel/ice/ice_lib.c

4101

regval = rd32(hw, qrx_context_offset);

drivers/net/ethernet/intel/ice/ice_lib.c

4102

regval &= ~BIT(ICE_L2TSEL_BIT_OFFSET);

drivers/net/ethernet/intel/ice/ice_lib.c

4103

regval |= l2tsel_bit;

drivers/net/ethernet/intel/ice/ice_lib.c

4104

wr32(hw, qrx_context_offset, regval);

drivers/net/ethernet/intel/ice/ice_main.c

4516

u32 regval;

drivers/net/ethernet/intel/ice/ice_main.c

4518

regval = rd32(hw, GLFLXP_RXDID_FLAGS(i, 0));

drivers/net/ethernet/intel/ice/ice_main.c

4519

if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)

drivers/net/ethernet/intel/igb/igb_main.c

1469

u32 regval = rd32(E1000_EIAM);

drivers/net/ethernet/intel/igb/igb_main.c

1471

wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);

drivers/net/ethernet/intel/igb/igb_main.c

1473

regval = rd32(E1000_EIAC);

drivers/net/ethernet/intel/igb/igb_main.c

1474

wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);

drivers/net/ethernet/intel/igb/igb_main.c

1500

u32 regval = rd32(E1000_EIAC);

drivers/net/ethernet/intel/igb/igb_main.c

1502

wr32(E1000_EIAC, regval | adapter->eims_enable_mask);

drivers/net/ethernet/intel/igb/igb_main.c

1503

regval = rd32(E1000_EIAM);

drivers/net/ethernet/intel/igb/igb_main.c

1504

wr32(E1000_EIAM, regval | adapter->eims_enable_mask);

drivers/net/ethernet/intel/igb/igb_ptp.c

1009

if (regval[0])

drivers/net/ethernet/intel/igb/igb_ptp.c

1012

igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1]));

drivers/net/ethernet/intel/igb/igb_ptp.c

1047

u64 regval;

drivers/net/ethernet/intel/igb/igb_ptp.c

1065

regval = rd32(E1000_RXSTMPL);

drivers/net/ethernet/intel/igb/igb_ptp.c

1066

regval |= (u64)rd32(E1000_RXSTMPH) << 32;

drivers/net/ethernet/intel/igb/igb_ptp.c

1068

igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);

drivers/net/ethernet/intel/igb/igb_ptp.c

1138

u32 regval;

drivers/net/ethernet/intel/igb/igb_ptp.c

1214

regval = rd32(E1000_RXPBS);

drivers/net/ethernet/intel/igb/igb_ptp.c

1215

regval |= E1000_RXPBS_CFG_TS_EN;

drivers/net/ethernet/intel/igb/igb_ptp.c

1216

wr32(E1000_RXPBS, regval);

drivers/net/ethernet/intel/igb/igb_ptp.c

1221

regval = rd32(E1000_TSYNCTXCTL);

drivers/net/ethernet/intel/igb/igb_ptp.c

1222

regval &= ~E1000_TSYNCTXCTL_ENABLED;

drivers/net/ethernet/intel/igb/igb_ptp.c

1223

regval |= tsync_tx_ctl;

drivers/net/ethernet/intel/igb/igb_ptp.c

1224

wr32(E1000_TSYNCTXCTL, regval);

drivers/net/ethernet/intel/igb/igb_ptp.c

1227

regval = rd32(E1000_TSYNCRXCTL);

drivers/net/ethernet/intel/igb/igb_ptp.c

1228

regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);

drivers/net/ethernet/intel/igb/igb_ptp.c

1229

regval |= tsync_rx_ctl;

drivers/net/ethernet/intel/igb/igb_ptp.c

1230

wr32(E1000_TSYNCRXCTL, regval);

drivers/net/ethernet/intel/igb/igb_ptp.c

1267

regval = rd32(E1000_TXSTMPL);

drivers/net/ethernet/intel/igb/igb_ptp.c

1268

regval = rd32(E1000_TXSTMPH);

drivers/net/ethernet/intel/igb/igb_ptp.c

1269

regval = rd32(E1000_RXSTMPL);

drivers/net/ethernet/intel/igb/igb_ptp.c

1270

regval = rd32(E1000_RXSTMPH);

drivers/net/ethernet/intel/igb/igb_ptp.c

941

u64 regval;

drivers/net/ethernet/intel/igb/igb_ptp.c

944

regval = rd32(E1000_TXSTMPL);

drivers/net/ethernet/intel/igb/igb_ptp.c

945

regval |= (u64)rd32(E1000_TXSTMPH) << 32;

drivers/net/ethernet/intel/igb/igb_ptp.c

947

igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);

drivers/net/ethernet/intel/igb/igb_ptp.c

997

__le64 *regval = (__le64 *)va;

drivers/net/ethernet/intel/igc/igc_main.c

4314

u32 regval = rd32(IGC_EIAC);

drivers/net/ethernet/intel/igc/igc_main.c

4316

wr32(IGC_EIAC, regval | adapter->eims_enable_mask);

drivers/net/ethernet/intel/igc/igc_main.c

4317

regval = rd32(IGC_EIAM);

drivers/net/ethernet/intel/igc/igc_main.c

4318

wr32(IGC_EIAM, regval | adapter->eims_enable_mask);

drivers/net/ethernet/intel/igc/igc_main.c

4336

u32 regval = rd32(IGC_EIAM);

drivers/net/ethernet/intel/igc/igc_main.c

4338

wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);

drivers/net/ethernet/intel/igc/igc_main.c

4340

regval = rd32(IGC_EIAC);

drivers/net/ethernet/intel/igc/igc_main.c

4341

wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);

drivers/net/ethernet/intel/igc/igc_ptp.c

750

struct igc_tx_timestamp_request *tstamp, u64 regval)

drivers/net/ethernet/intel/igc/igc_ptp.c

760

if (igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval))

drivers/net/ethernet/intel/igc/igc_ptp.c

812

u64 regval;

drivers/net/ethernet/intel/igc/igc_ptp.c

824

regval = rd32(IGC_TXSTMPL);

drivers/net/ethernet/intel/igc/igc_ptp.c

825

regval |= (u64)rd32(IGC_TXSTMPH) << 32;

drivers/net/ethernet/intel/igc/igc_ptp.c

854

regval = txstmpl_new;

drivers/net/ethernet/intel/igc/igc_ptp.c

855

regval |= (u64)rd32(IGC_TXSTMPH) << 32;

drivers/net/ethernet/intel/igc/igc_ptp.c

858

igc_ptp_tx_reg_to_stamp(adapter, &adapter->tx_tstamp[0], regval);

drivers/net/ethernet/intel/igc/igc_ptp.c

871

regval = rd32(tstamp->regl);

drivers/net/ethernet/intel/igc/igc_ptp.c

872

regval |= (u64)rd32(tstamp->regh) << 32;

drivers/net/ethernet/intel/igc/igc_ptp.c

874

igc_ptp_tx_reg_to_stamp(adapter, tstamp, regval);

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

1849

static int ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

1859

if (regval & IXGBE_RXCTRL_RXEN)

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

2735

int ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

2737

if (regval & IXGBE_RXCTRL_RXEN)

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

57

int ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1107

regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1108

regval &= ~IXGBE_TSYNCTXCTL_ENABLED;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1109

regval |= tsync_tx_ctl;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1110

IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1113

regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1114

regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1115

regval |= tsync_rx_ctl;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

1116

IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

812

u64 regval = 0;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

814

regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

815

regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

816

ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

883

__le64 regval;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

886

skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, &regval,

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

897

le64_to_cpu(regval));

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

914

u64 regval = 0;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

932

regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

933

regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

935

ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);

drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

991

u32 regval;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

186

u64 regval = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

189

regval = 8 << CN93_SDP_FUNC_SEL_EPF_BIT_POS;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

191

octep_write_csr64(oct, CN93_SDP_EPVF_RING(pf_srn + q), regval);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

193

regval = octep_read_csr64(oct, CN93_SDP_EPVF_RING(pf_srn + q));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

195

CN93_SDP_EPVF_RING(pf_srn + q), regval);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

210

u64 regval = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

213

regval = 8 << CNXK_SDP_FUNC_SEL_EPF_BIT_POS;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

215

octep_write_csr64(oct, CNXK_SDP_EPVF_RING(pf_srn + q), regval);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

217

regval = octep_read_csr64(oct, CNXK_SDP_EPVF_RING(pf_srn + q));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

219

CNXK_SDP_EPVF_RING(pf_srn + q), regval);

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

1167

u64 regval[MAX_REGS_PER_MBOX_MSG];

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

255

u64 regval, curr_rollover_set, nxt_rollover_set;

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

269

regval = readq(ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

270

regval &= ~PTP_CLOCK_CFG_ATOMIC_OP_MASK;

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

271

regval |= (ATOMIC_SET << 26);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

272

writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

278

u64 regval, ptp_clock_hi;

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

305

regval = readq(ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

306

regval &= ~PTP_CLOCK_CFG_ATOMIC_OP_MASK;

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

307

regval |= neg_adj ? (ATOMIC_DEC << 26) : (ATOMIC_INC << 26);

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

308

writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

1866

int lvl, u64 reg, u64 regval)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

1918

if ((oldval & 0x1) == (regval & 0x1)) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

1919

rvu_write64(rvu, blkaddr, reg, regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

1924

if (!(regval & 0x1)) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

1948

rvu_write64(rvu, blkaddr, reg, regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2371

u64 parent_off, regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2410

regval = rvu_read64(rvu, blkaddr, parent_off);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2411

schq = (regval >> 16) & 0x1FF;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2739

int lvl, u64 reg, u64 regval)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2752

parent = (regval >> 16) & 0x1FF;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2865

rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2906

u64 reg, val, regval, schq_regbase, val_mask;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2945

regval = req->regval[idx];

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2950

txsch->lvl, reg, regval))

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2958

regval = (val & val_mask) | (regval & ~val_mask);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2963

req->lvl, reg, regval))

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2970

regval &= ~(0x7FULL << 24);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2971

regval |= ((u64)nixlf << 24);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2979

regval &= ~BIT_ULL(13);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2996

(regval & BIT_ULL(49))) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2999

regval &= ~BIT_ULL(49);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3001

rvu_write64(rvu, blkaddr, reg, regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3010

u64 regval = req->vtag_size;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3021

regval |= BIT_ULL(5);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3023

regval |= BIT_ULL(4);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3026

NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3084

u64 regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3102

regval = size ? vtag : vtag << 32;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3105

NIX_AF_TX_VTAG_DEFX_DATA(index), regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3331

u64 regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3348

regval = (next_idx << 16) | (1 << 12) | prev_mce->channel;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3351

regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3362

regval = (next_idx << 16) | (eol << 12) | mce->channel;

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

3365

regval);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4008

u64 regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4020

regval = rvu_read64(rvu, blkaddr,

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4023

rsp->stat = regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4328

u64 regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4343

regval = rvu_read64(rvu, blkaddr,

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4347

rsp->stat = regval;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4353

regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index,

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4356

if (!(regval & rvu->hw->npc_stat_ena)) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

4362

cntr = regval & 0x1FF;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

644

req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

645

req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

649

req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57),

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

655

req->regval[1] = parent << 16;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

659

req->regval[2] = dwrr_val;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

667

req->regval[0] = (u64)parent << 16;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

670

req->regval[1] = dwrr_val;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

674

req->regval[2] = BIT_ULL(12) | BIT_ULL(13) |

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

680

req->regval[0] = (u64)parent << 16;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

683

req->regval[1] = dwrr_val;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

691

req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

696

req->regval[0] = (u64)parent << 16;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

700

req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

709

req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

721

req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

725

req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

729

req->regval[2] = 0;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

751

req->regval[0] |= BIT_ULL(49);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

106

u64 regval = 0;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

113

regval = FIELD_PREP(TLX_BURST_EXPONENT, (u64)burst_exp) |

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

119

regval = FIELD_PREP(CN10K_TLX_BURST_EXPONENT, (u64)burst_exp) |

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

126

return regval;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

149

req->regval[0] = otx2_get_txschq_rate_regval(nic, maxrate, burst);

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

107

cfg->regval[*num_regs] =

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

113

cfg->regval[*num_regs] = node->parent->child_dwrr_prio << 24 |

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

121

cfg->regval[*num_regs] =

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

131

cfg->regval[*num_regs] =

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

149

cfg->regval[num_regs] = ((u64)pfvf->tx_max_pktlen << 8) |

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

151

cfg->regval[num_regs] |= (0x20ULL << 51) | (0x80ULL << 39) |

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

162

cfg->regval[num_regs] = BIT_ULL(13) | BIT_ULL(12);

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

170

cfg->regval[num_regs] = (u64)hw->tx_link << 16;

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

176

cfg->regval[num_regs] = BIT_ULL(13) | BIT_ULL(12);

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

183

cfg->regval[num_regs] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 |

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

226

cfg->regval[0] = (u64)parent->prio_anchor << 32;

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

227

cfg->regval[0] |= ((parent->child_dwrr_prio != OTX2_QOS_DEFAULT_PRIO) ?

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

94

cfg->regval[*num_regs] = node->parent->schq << 16;

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

99

cfg->regval[*num_regs] = node->prio << 24 |

drivers/net/ethernet/mediatek/mtk_wed_debugfs.c

599

unsigned int regval;

drivers/net/ethernet/mediatek/mtk_wed_debugfs.c

602

ret = regmap_read(hw->regs, hw->debugfs_reg, &regval);

drivers/net/ethernet/mediatek/mtk_wed_debugfs.c

606

*val = regval;

drivers/net/ethernet/microchip/lan743x_main.c

831

int phy_id, int index, u16 regval)

drivers/net/ethernet/microchip/lan743x_main.c

841

val = (u32)regval;

drivers/net/ethernet/microchip/lan743x_main.c

906

int dev_addr, int index, u16 regval)

drivers/net/ethernet/microchip/lan743x_main.c

927

lan743x_csr_write(adapter, MAC_MII_DATA, (u32)regval);

drivers/net/ethernet/microchip/lan865x/lan865x.c

209

u32 regval = 0;

drivers/net/ethernet/microchip/lan865x/lan865x.c

214

regval |= MAC_NET_CFG_PROMISCUOUS_MODE;

drivers/net/ethernet/microchip/lan865x/lan865x.c

215

regval &= (~MAC_NET_CFG_MULTICAST_MODE);

drivers/net/ethernet/microchip/lan865x/lan865x.c

216

regval &= (~MAC_NET_CFG_UNICAST_MODE);

drivers/net/ethernet/microchip/lan865x/lan865x.c

222

regval &= (~MAC_NET_CFG_PROMISCUOUS_MODE);

drivers/net/ethernet/microchip/lan865x/lan865x.c

223

regval |= MAC_NET_CFG_MULTICAST_MODE;

drivers/net/ethernet/microchip/lan865x/lan865x.c

224

regval &= (~MAC_NET_CFG_UNICAST_MODE);

drivers/net/ethernet/microchip/lan865x/lan865x.c

230

regval &= (~MAC_NET_CFG_PROMISCUOUS_MODE);

drivers/net/ethernet/microchip/lan865x/lan865x.c

231

regval |= MAC_NET_CFG_MULTICAST_MODE;

drivers/net/ethernet/microchip/lan865x/lan865x.c

232

regval &= (~MAC_NET_CFG_UNICAST_MODE);

drivers/net/ethernet/microchip/lan865x/lan865x.c

238

ret = oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_NET_CFG, regval);

drivers/net/ethernet/microchip/lan865x/lan865x.c

261

u32 regval;

drivers/net/ethernet/microchip/lan865x/lan865x.c

263

if (oa_tc6_read_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, &regval))

drivers/net/ethernet/microchip/lan865x/lan865x.c

266

regval &= ~(MAC_NET_CTL_TXEN | MAC_NET_CTL_RXEN);

drivers/net/ethernet/microchip/lan865x/lan865x.c

268

if (oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, regval))

drivers/net/ethernet/microchip/lan865x/lan865x.c

292

u32 regval;

drivers/net/ethernet/microchip/lan865x/lan865x.c

294

if (oa_tc6_read_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, &regval))

drivers/net/ethernet/microchip/lan865x/lan865x.c

297

regval |= MAC_NET_CTL_TXEN | MAC_NET_CTL_RXEN;

drivers/net/ethernet/microchip/lan865x/lan865x.c

299

if (oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, regval))

drivers/net/ethernet/microchip/lan865x/lan865x.c

48

u32 regval;

drivers/net/ethernet/microchip/lan865x/lan865x.c

50

regval = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];

drivers/net/ethernet/microchip/lan865x/lan865x.c

52

return oa_tc6_write_register(tc6, LAN865X_REG_MAC_L_SADDR1, regval);

drivers/net/ethernet/microchip/lan865x/lan865x.c

58

u32 regval;

drivers/net/ethernet/microchip/lan865x/lan865x.c

67

regval = (mac[5] << 8) | mac[4];

drivers/net/ethernet/microchip/lan865x/lan865x.c

69

regval);

drivers/net/ethernet/natsemi/natsemi.c

2736

u32 regval = readl(ioaddr + WOLCmd);

drivers/net/ethernet/natsemi/natsemi.c

2748

if (regval & WakePhy)

drivers/net/ethernet/natsemi/natsemi.c

2750

if (regval & WakeUnicast)

drivers/net/ethernet/natsemi/natsemi.c

2752

if (regval & WakeMulticast)

drivers/net/ethernet/natsemi/natsemi.c

2754

if (regval & WakeBroadcast)

drivers/net/ethernet/natsemi/natsemi.c

2756

if (regval & WakeArp)

drivers/net/ethernet/natsemi/natsemi.c

2758

if (regval & WakeMagic)

drivers/net/ethernet/natsemi/natsemi.c

2760

if (regval & WakeMagicSecure) {

drivers/net/ethernet/ni/nixge.c

1004

u32 regval = 0;

drivers/net/ethernet/ni/nixge.c

1006

regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);

drivers/net/ethernet/ni/nixge.c

1007

ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)

drivers/net/ethernet/ni/nixge.c

1009

regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);

drivers/net/ethernet/ni/nixge.c

1010

ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)

drivers/net/ethernet/oa_tc6.c

1228

u32 regval;

drivers/net/ethernet/oa_tc6.c

1231

ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, &regval);

drivers/net/ethernet/oa_tc6.c

1236

regval |= CONFIG0_ZARFE_ENABLE;

drivers/net/ethernet/oa_tc6.c

1238

return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval);

drivers/net/ethernet/oa_tc6.c

404

u32 regval;

drivers/net/ethernet/oa_tc6.c

407

ret = oa_tc6_read_register(tc6, OA_TC6_REG_STDCAP, &regval);

drivers/net/ethernet/oa_tc6.c

411

if (!(regval & STDCAP_DIRECT_PHY_REG_ACCESS))

drivers/net/ethernet/oa_tc6.c

425

u32 regval;

drivers/net/ethernet/oa_tc6.c

430

&regval);

drivers/net/ethernet/oa_tc6.c

434

return regval;

drivers/net/ethernet/oa_tc6.c

469

u32 regval;

drivers/net/ethernet/oa_tc6.c

476

ret = oa_tc6_read_register(tc6, (ret << 16) | regnum, &regval);

drivers/net/ethernet/oa_tc6.c

480

return regval;

drivers/net/ethernet/oa_tc6.c

589

u32 regval;

drivers/net/ethernet/oa_tc6.c

592

ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &regval);

drivers/net/ethernet/oa_tc6.c

599

return regval;

drivers/net/ethernet/oa_tc6.c

604

u32 regval = RESET_SWRESET;

drivers/net/ethernet/oa_tc6.c

607

ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval);

drivers/net/ethernet/oa_tc6.c

612

ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval,

drivers/net/ethernet/oa_tc6.c

613

regval & STATUS0_RESETC,

drivers/net/ethernet/oa_tc6.c

620

return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval);

drivers/net/ethernet/oa_tc6.c

625

u32 regval;

drivers/net/ethernet/oa_tc6.c

628

ret = oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, &regval);

drivers/net/ethernet/oa_tc6.c

632

regval &= ~(INT_MASK0_TX_PROTOCOL_ERR_MASK |

drivers/net/ethernet/oa_tc6.c

637

return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval);

drivers/net/ethernet/oa_tc6.c

695

u32 regval = INT_MASK0_ALL_INTERRUPTS;

drivers/net/ethernet/oa_tc6.c

699

oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval);

drivers/net/ethernet/oa_tc6.c

700

oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &regval);

drivers/net/ethernet/oa_tc6.c

701

oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

23

u32 regval;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

26

regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

30

regval |= SXGBE_TX_JABBER_DISABLE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

31

writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

34

regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

39

regval |= SXGBE_RX_JUMBPKT_ENABLE | SXGBE_RX_ACS_ENABLE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

40

writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG);

drivers/net/ethernet/stmicro/stmmac/common.h

565

void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len);

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

31

u32 regval = readl(ioaddr + PTP_TCR);

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

33

regval &= ~STMMAC_HWTS_CFG_MASK;

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

34

regval |= data;

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

36

writel(regval, ioaddr + PTP_TCR);

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

217

void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len)

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

245

*regval = FIELD_PREP(DMA_AXI_BLEN_MASK, val);

drivers/net/ethernet/sun/sunbmac.c

103

u32 regval;

drivers/net/ethernet/sun/sunbmac.c

109

regval = GLOB_CTRL_B32;

drivers/net/ethernet/sun/sunbmac.c

111

regval = GLOB_CTRL_B16;

drivers/net/ethernet/sun/sunbmac.c

112

sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

112

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

114

regval = readl(pdata->mac_regs + MAC_VLANTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

116

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLRXS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

119

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_DOVLTC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1191

unsigned int reg, regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1196

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1197

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1199

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1207

regval = readl(pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1208

regval = XLGMAC_SET_REG_BITS(regval,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1212

writel(regval, pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

122

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ERSVLM_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1223

unsigned int reg, regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1228

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1229

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1231

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1239

regval = readl(pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1242

regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_TFE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1245

regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_PT_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1248

writel(regval, pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

125

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ESVL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1258

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1260

regval = readl(pdata->mac_regs + MAC_RFCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1261

regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1263

writel(regval, pdata->mac_regs + MAC_RFCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1270

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1272

regval = readl(pdata->mac_regs + MAC_RFCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1273

regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1275

writel(regval, pdata->mac_regs + MAC_RFCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

128

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

130

writel(regval, pdata->mac_regs + MAC_VLANTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1304

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1311

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1312

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RIWT_RWT_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1315

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1330

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1333

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1334

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FEP_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1336

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1343

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1346

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1347

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FUP_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1349

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1362

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1369

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

137

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1370

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_RBSZ_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1373

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1381

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1389

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

139

regval = readl(pdata->mac_regs + MAC_VLANTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1390

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_TSE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1392

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

140

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1401

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1408

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1409

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_SPH_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1411

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1414

regval = readl(pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1415

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_HDSMS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1418

writel(regval, pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

142

writel(regval, pdata->mac_regs + MAC_VLANTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1461

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1464

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1465

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RTC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1467

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1476

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1479

regval = readl(pdata->mac_regs + MTL_OMR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1480

regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_ETSALG_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1482

writel(regval, pdata->mac_regs + MTL_OMR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1486

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1487

regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_ETSCR_TSA_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1489

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

149

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1491

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1492

regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_QWR_QW_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1494

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1498

regval = readl(pdata->mac_regs + MTL_OMR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1499

regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_RAA_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1501

writel(regval, pdata->mac_regs + MTL_OMR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1508

unsigned int reg, regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

151

regval = readl(pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1522

regval = readl(XLGMAC_MTL_REG(pdata, queue,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1524

regval = XLGMAC_SET_REG_BITS(regval,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1528

writel(regval, XLGMAC_MTL_REG(pdata, queue,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

153

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1536

regval = readl(XLGMAC_MTL_REG(pdata, queue,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1538

regval = XLGMAC_SET_REG_BITS(regval,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1542

writel(regval, XLGMAC_MTL_REG(pdata, queue,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

155

writel(regval, pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1555

regval = 0;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

157

regval = readl(pdata->mac_regs + MAC_VLANTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1572

regval |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1577

writel(regval, pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1579

regval = 0;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1586

regval = readl(pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1587

regval |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH |

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1589

writel(regval, pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

159

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTHM_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1592

regval = readl(pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1593

regval |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH |

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1595

writel(regval, pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1598

regval = readl(pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1599

regval |= (MTL_RQDCM2R_Q8MDMACH | MTL_RQDCM2R_Q9MDMACH |

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1601

writel(regval, pdata->mac_regs + reg);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

162

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTIM_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1634

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1641

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1642

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TQS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1644

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

165

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ETV_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1656

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1663

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1664

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RQS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1666

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1677

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1680

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1682

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFA_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1685

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFD_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1687

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1695

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1698

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1699

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TTC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1701

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1711

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1714

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1715

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RSF_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1717

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1727

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

173

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1730

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1731

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TSF_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1733

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1743

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

175

writel(regval, pdata->mac_regs + MAC_VLANTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1750

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1751

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_OSP_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1754

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1764

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1768

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1769

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_PBLX8_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1772

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1780

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1782

regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1783

regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1785

return regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1792

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1799

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1800

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1803

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1811

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1813

regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1814

regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1816

return regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

182

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1823

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1830

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1831

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

1834

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

184

regval = readl(pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

186

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

188

writel(regval, pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2127

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2130

regval = readl(pdata->mac_regs + MMC_CR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2131

regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2133

writel(regval, pdata->mac_regs + MMC_CR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

221

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2259

regval = readl(pdata->mac_regs + MMC_CR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2260

regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2262

writel(regval, pdata->mac_regs + MMC_CR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2267

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2269

regval = readl(pdata->mac_regs + MMC_CR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2271

regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_ROR_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2274

regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_CR_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2276

writel(regval, pdata->mac_regs + MMC_CR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2284

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2288

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2290

if (regval) {

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2297

regval = readl(pdata->mac_regs + MAC_RSSAR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2298

regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_RSSIA_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2300

regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_ADDRT_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2302

regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_CT_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2304

regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_OB_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2306

writel(regval, pdata->mac_regs + MAC_RSSAR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2310

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2313

if (!regval)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

234

regval = readl(pdata->mac_regs + MAC_VLANHTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

236

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANHTR_VLHT_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

238

writel(regval, pdata->mac_regs + MAC_VLANHTR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2386

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2406

regval = readl(pdata->mac_regs + MAC_RSSCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2407

regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2409

writel(regval, pdata->mac_regs + MAC_RSSCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2416

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2421

regval = readl(pdata->mac_regs + MAC_RSSCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2422

regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2424

writel(regval, pdata->mac_regs + MAC_RSSCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

247

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

249

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

251

if (regval == val)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2530

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2539

regval = readl(pdata->mac_regs + MMC_RIER);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2540

regval = XLGMAC_SET_REG_BITS(regval, MMC_RIER_ALL_INTERRUPTS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2542

writel(regval, pdata->mac_regs + MMC_RIER);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2543

regval = readl(pdata->mac_regs + MMC_TIER);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2544

regval = XLGMAC_SET_REG_BITS(regval, MMC_TIER_ALL_INTERRUPTS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2546

writel(regval, pdata->mac_regs + MMC_TIER);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2551

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2553

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2555

if (regval == 0x1)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2558

regval = readl(pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2559

regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2561

writel(regval, pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2568

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

257

regval = readl(pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2570

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2572

if (regval == 0)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2575

regval = readl(pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2576

regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2578

writel(regval, pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

258

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PR_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2585

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2587

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2589

if (regval == 0x2)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2592

regval = readl(pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2593

regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2595

writel(regval, pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

260

writel(regval, pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2602

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2604

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2606

if (regval == 0x3)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2609

regval = readl(pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2610

regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2612

writel(regval, pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

277

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

279

regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

281

if (regval == val)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

287

regval = readl(pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

288

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PM_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

290

writel(regval, pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2946

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2949

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2950

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2952

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2958

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2959

regval = XLGMAC_GET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2961

while (--count && regval)

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2973

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2975

regval = readl(pdata->mac_regs + DMA_SBMR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2977

regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_EAME_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2980

regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_UNDEF_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2982

regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_BLEN_256_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

2984

writel(regval, pdata->mac_regs + DMA_SBMR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

3044

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

3047

regval = readl(pdata->mac_regs + DMA_MR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

3048

regval = XLGMAC_SET_REG_BITS(regval, DMA_MR_SWR_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

3050

writel(regval, pdata->mac_regs + DMA_MR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

375

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

38

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

381

regval = readl(pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

382

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HPF_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

384

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HUC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

386

regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HMC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

388

writel(regval, pdata->mac_regs + MAC_PFR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

395

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

399

regval = readl(pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

40

regval = readl(pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

400

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_JE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

402

writel(regval, pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

41

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

415

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

417

regval = readl(pdata->mac_regs + MAC_VLANIR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

419

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_CSVL_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

421

regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_VLTI_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

423

writel(regval, pdata->mac_regs + MAC_VLANIR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

43

writel(regval, pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

50

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

501

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

509

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

510

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

512

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

517

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

518

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

52

regval = readl(pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

521

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

525

regval = readl(pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

526

regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

528

writel(regval, pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

53

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

535

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

547

regval = readl(pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

548

regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

55

writel(regval, pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

550

writel(regval, pdata->mac_regs + MAC_TCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

554

regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

555

regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

557

writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

566

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

567

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

569

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

605

unsigned int regval, i;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

613

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

614

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

616

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

620

regval = 0;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

622

regval |= (0x02 << (i << 1));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

623

writel(regval, pdata->mac_regs + MAC_RQC0R);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

626

regval = readl(pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

627

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

629

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

631

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

633

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

635

writel(regval, pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

642

u32 regval;

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

645

regval = readl(pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

646

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

648

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

650

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

652

regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

654

writel(regval, pdata->mac_regs + MAC_RCR);

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

669

regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

670

regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,

drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c

672

writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1468

u32 regval;

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1475

regval = (setting << vf_bit);

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1476

wr32m(wx, WX_TDM_MAC_AS(index), regval | BIT(vf_bit), regval);

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1479

wr32m(wx, WX_TDM_VLAN_AS(index), regval | BIT(vf_bit), regval);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

189

u64 regval = 0;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

191

regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPL);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

192

regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPH) << 32;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

194

wx_ptp_convert_to_hwtstamp(wx, &shhwtstamps, regval);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

561

u32 regval;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

629

regval = rd32ptp(wx, WX_TSC_1588_CTL);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

630

regval &= ~WX_TSC_1588_CTL_ENABLED;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

631

regval |= tsync_tx_ctl;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

632

wr32ptp(wx, WX_TSC_1588_CTL, regval);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

635

regval = rd32(wx, WX_PSR_1588_CTL);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

636

regval &= ~(WX_PSR_1588_CTL_ENABLED | WX_PSR_1588_CTL_TYPE_MASK);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

637

regval |= tsync_rx_ctl;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

638

wr32(wx, WX_PSR_1588_CTL, regval);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

856

u64 regval = 0;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

866

regval |= (u64)rd32(wx, WX_PSR_1588_STMPL);

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

867

regval |= (u64)rd32(wx, WX_PSR_1588_STMPH) << 32;

drivers/net/ethernet/wangxun/libwx/wx_ptp.c

869

wx_ptp_convert_to_hwtstamp(wx, skb_hwtstamps(skb), regval);

drivers/net/phy/air_an8801.c

256

u32 req_ns, regval;

drivers/net/phy/air_an8801.c

264

regval = req_ns + (AN8801_PERIOD_UNIT / 2);

drivers/net/phy/air_an8801.c

267

regval >>= AN8801_PERIOD_SHIFT;

drivers/net/phy/air_an8801.c

269

return regval;

drivers/net/phy/micrel.c

1679

int regval;

drivers/net/phy/micrel.c

1682

regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

drivers/net/phy/micrel.c

1684

regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

drivers/net/phy/micrel.c

1686

if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)

drivers/net/phy/micrel.c

1691

if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)

drivers/net/phy/micrel.c

1732

int regval;

drivers/net/phy/micrel.c

1741

regval = phy_read(phydev, MII_STAT1000);

drivers/net/phy/micrel.c

1742

if ((regval & 0xFF) == 0xFF) {

drivers/net/usb/lan78xx.c

2053

u16 regval)

drivers/net/usb/lan78xx.c

2070

val = (u32)regval;

drivers/net/usb/smsc75xx.c

223

int idx, int regval, int in_pm)

drivers/net/usb/smsc75xx.c

238

val = regval;

drivers/net/usb/smsc75xx.c

274

int idx, int regval)

drivers/net/usb/smsc75xx.c

276

__smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);

drivers/net/usb/smsc75xx.c

285

int regval)

drivers/net/usb/smsc75xx.c

287

__smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);

drivers/net/usb/smsc95xx.c

219

int regval)

drivers/net/usb/smsc95xx.c

233

val = regval;

drivers/net/usb/smsc95xx.c

305

u16 regval)

drivers/net/usb/smsc95xx.c

309

smsc95xx_mdio_write(dev, phy_id, idx, regval);

drivers/net/wan/farsync.c

661

unsigned int regval;

drivers/net/wan/farsync.c

690

regval = inl(card->pci_conf + CNTRL_9052);

drivers/net/wan/farsync.c

692

outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);

drivers/net/wan/farsync.c

693

outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);

drivers/net/wireless/ath/ath5k/reset.c

450

u32 regval;

drivers/net/wireless/ath/ath5k/reset.c

478

regval = ioread32(reg);

drivers/net/wireless/ath/ath5k/reset.c

479

iowrite32(regval | val, reg);

drivers/net/wireless/ath/ath5k/reset.c

480

regval = ioread32(reg);

drivers/net/wireless/ath/ath5k/reset.c

484

iowrite32(regval & ~val, reg);

drivers/net/wireless/ath/ath5k/reset.c

485

regval = ioread32(reg);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

410

int delta, currPDADC, regval;

drivers/net/wireless/ath/ath9k/ar9002_calib.c

426

regval = ah->originalGain[i] - delta;

drivers/net/wireless/ath/ath9k/ar9002_calib.c

427

if (regval < 0)

drivers/net/wireless/ath/ath9k/ar9002_calib.c

428

regval = 0;

drivers/net/wireless/ath/ath9k/ar9002_calib.c

432

AR_PHY_TX_GAIN, regval);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

381

u32 regval;

drivers/net/wireless/ath/ath9k/ar9002_phy.c

383

regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

384

antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>

drivers/net/wireless/ath/ath9k/ar9002_phy.c

386

antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>

drivers/net/wireless/ath/ath9k/ar9002_phy.c

388

antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>

drivers/net/wireless/ath/ath9k/ar9002_phy.c

398

u32 regval;

drivers/net/wireless/ath/ath9k/ar9002_phy.c

400

regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

401

regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |

drivers/net/wireless/ath/ath9k/ar9002_phy.c

404

regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)

drivers/net/wireless/ath/ath9k/ar9002_phy.c

406

regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)

drivers/net/wireless/ath/ath9k/ar9002_phy.c

408

regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)

drivers/net/wireless/ath/ath9k/ar9002_phy.c

411

REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

420

u32 regval;

drivers/net/wireless/ath/ath9k/ar9002_phy.c

455

regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

456

regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));

drivers/net/wireless/ath/ath9k/ar9002_phy.c

461

regval &= (~(AR_PHY_9285_FAST_DIV_BIAS));

drivers/net/wireless/ath/ath9k/ar9002_phy.c

462

regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

463

regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

464

regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

465

regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

466

regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

467

REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

469

regval = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

470

regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

471

regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

472

REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3650

u32 regval, value, gpio;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3730

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3731

regval &= (~AR_ANT_DIV_CTRL_ALL);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3732

regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3734

regval &= (~AR_PHY_ANT_DIV_LNADIV);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3735

regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3738

regval |= AR_ANT_DIV_ENABLE;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3742

regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3751

regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3752

regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3763

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3766

regval = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3767

regval &= (~AR_FAST_DIV_ENABLE);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3768

regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3772

regval |= AR_FAST_DIV_ENABLE;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3774

REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3777

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3782

regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3787

regval |= (ATH_ANT_DIV_COMB_LNA1 <<

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3789

regval |= (ATH_ANT_DIV_COMB_LNA2 <<

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3791

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1003

regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1004

REG_WRITE(ah, AR_MCI_COMMAND2, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1006

regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1007

REG_WRITE(ah, AR_MCI_COMMAND2, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1172

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1177

regval = REG_READ(ah, AR_BTCOEX_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1179

if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) {

drivers/net/wireless/ath/ath9k/ar9003_mci.c

865

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_mci.c

867

regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |

drivers/net/wireless/ath/ath9k/ar9003_mci.c

879

REG_WRITE(ah, AR_BTCOEX_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

884

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_mci.c

886

regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |

drivers/net/wireless/ath/ath9k/ar9003_mci.c

898

REG_WRITE(ah, AR_BTCOEX_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

903

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_mci.c

905

regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |

drivers/net/wireless/ath/ath9k/ar9003_mci.c

915

REG_WRITE(ah, AR_BTCOEX_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

923

u32 regval, i;

drivers/net/wireless/ath/ath9k/ar9003_mci.c

981

regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

982

REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

986

regval = REG_READ(ah, AR_MCI_COMMAND2);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

987

regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

988

REG_WRITE(ah, AR_MCI_COMMAND2, regval);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

992

regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

993

REG_WRITE(ah, AR_MCI_COMMAND2, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1498

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1500

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1501

antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1503

antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1505

antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1530

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1532

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1533

regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1538

regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1540

regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1542

regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1544

regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1546

regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1549

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1558

u32 regval;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1564

regval = ar9003_hw_ant_ctrl_common_2_get(ah,

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1567

regval &= ~AR_SWITCH_TABLE_COM2_ALL;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1568

regval |= ah->config.ant_ctrl_comm2g_switch_enable;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1571

AR_SWITCH_TABLE_COM2_ALL, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1580

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1581

regval &= (~AR_ANT_DIV_CTRL_ALL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1582

regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1583

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1589

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1590

regval &= ~AR_PHY_ANT_DIV_LNADIV;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1591

regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1593

regval |= AR_ANT_DIV_ENABLE;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1595

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1600

regval = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1601

regval &= ~AR_FAST_DIV_ENABLE;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1602

regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1604

regval |= AR_FAST_DIV_ENABLE;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1606

REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1609

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1610

regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1618

regval |= (ATH_ANT_DIV_COMB_LNA1 <<

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1620

regval |= (ATH_ANT_DIV_COMB_LNA2 <<

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1622

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1648

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1649

regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1653

regval |= (ATH_ANT_DIV_COMB_LNA1 <<

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1655

regval |= (ATH_ANT_DIV_COMB_LNA2 <<

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1657

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

drivers/net/wireless/ath/ath9k/debug.c

895

u32 regval;

drivers/net/wireless/ath/ath9k/debug.c

898

regval = REG_READ_D(ah, sc->debug.regidx);

drivers/net/wireless/ath/ath9k/debug.c

900

len = sprintf(buf, "0x%08x\n", regval);

drivers/net/wireless/ath/ath9k/debug.c

909

unsigned long regval;

drivers/net/wireless/ath/ath9k/debug.c

912

ret = kstrtoul_from_user(user_buf, count, 0, &regval);

drivers/net/wireless/ath/ath9k/debug.c

917

REG_WRITE_D(ah, sc->debug.regidx, regval);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

365

u32 reg32, regOffset, regChainOffset, regval;

drivers/net/wireless/ath/ath9k/eeprom_9287.c

443

regval = SM(pdGainOverlap_t2,

drivers/net/wireless/ath/ath9k/eeprom_9287.c

456

regval);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

854

u32 regChainOffset, regval;

drivers/net/wireless/ath/ath9k/eeprom_9287.c

918

regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

919

regval &= ~(AR9287_AN_RF2G3_DB1 |

drivers/net/wireless/ath/ath9k/eeprom_9287.c

925

regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |

drivers/net/wireless/ath/ath9k/eeprom_9287.c

932

ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

934

regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

935

regval &= ~(AR9287_AN_RF2G3_DB1 |

drivers/net/wireless/ath/ath9k/eeprom_9287.c

941

regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |

drivers/net/wireless/ath/ath9k/eeprom_9287.c

948

ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);

drivers/net/wireless/ath/ath9k/hw.c

834

u32 regval, pll2_divint, pll2_divfrac, refdiv;

drivers/net/wireless/ath/ath9k/hw.c

867

regval = REG_READ(ah, AR_PHY_PLL_MODE);

drivers/net/wireless/ath/ath9k/hw.c

869

regval |= (0x1 << 22);

drivers/net/wireless/ath/ath9k/hw.c

871

regval |= (0x1 << 16);

drivers/net/wireless/ath/ath9k/hw.c

872

REG_WRITE(ah, AR_PHY_PLL_MODE, regval);

drivers/net/wireless/ath/ath9k/hw.c

879

regval = REG_READ(ah, AR_PHY_PLL_MODE);

drivers/net/wireless/ath/ath9k/hw.c

881

regval = (regval & 0x80071fff) |

drivers/net/wireless/ath/ath9k/hw.c

887

regval = (regval & 0x01c00fff) |

drivers/net/wireless/ath/ath9k/hw.c

894

regval |= (0x6 << 12);

drivers/net/wireless/ath/ath9k/hw.c

896

regval = (regval & 0x80071fff) |

drivers/net/wireless/ath/ath9k/hw.c

901

REG_WRITE(ah, AR_PHY_PLL_MODE, regval);

drivers/net/wireless/broadcom/b43/phy_ht.c

717

u32 regval[64];

drivers/net/wireless/broadcom/b43/phy_ht.c

723

regval[i] = pwr;

drivers/net/wireless/broadcom/b43/phy_ht.c

725

b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);

drivers/net/wireless/broadcom/b43/phy_n.c

4051

u32 regval[64];

drivers/net/wireless/broadcom/b43/phy_n.c

4201

regval[i] = pwr;

drivers/net/wireless/broadcom/b43/phy_n.c

4203

b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

194

#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

195

#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

196

#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

197

#define SBSDIO_CLKAV(regval, alponly) \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

198

(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15082

u16 regval[4];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15115

regval[0] = nphy_def_lnagains[2] + gain_delta[core];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15116

regval[1] = nphy_def_lnagains[3] + gain_delta[core];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15117

regval[2] = nphy_def_lnagains[3] + gain_delta[core];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15118

regval[3] = nphy_def_lnagains[3] + gain_delta[core];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15121

regval[ctr] =

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15125

wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

15577

u16 regval[21];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16003

regval[ctr] = (hpf_code << 8) | 0x7c;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16004

wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16009

regval[0] = 0;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16010

regval[1] = 1;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16011

regval[2] = 1;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16012

regval[3] = 1;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16013

wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16014

wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16017

regval[ctr] = (hpf_code << 8) | 0x74;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16018

wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16023

regval[ctr] = 3 * ctr;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16024

wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16025

wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16028

regval[ctr] = (u16) ctr;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16029

wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16030

wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16915

u16 regval;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16933

regval = 0x000a;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16934

wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16935

wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16938

regval = 0xcdaa;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16939

wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16940

wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16944

regval = 0x0000;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16945

wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16946

wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16948

regval = 0x7aab;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16949

wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16950

wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16952

regval = 0x0800;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16953

wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

16954

wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, &regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

17570

u32 regval[64];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

17755

regval[idx] = (u32) pwr_est;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

17758

regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18796

u32 regval[128];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18815

regval[idx] = iqcomp;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18817

regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18843

regval[idx] = curr_locomp;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18846

regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18975

u16 regval;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18981

regval = read_phy_reg(pi, 0x27d);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18982

pi->nphy_crsminpwr[0] = regval & 0xff;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18983

regval &= 0xff00;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18984

regval |= (u16) minpwr;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18985

write_phy_reg(pi, 0x27d, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18987

regval = read_phy_reg(pi, 0x280);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18988

pi->nphy_crsminpwr[1] = regval & 0xff;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18989

regval &= 0xff00;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18990

regval |= (u16) minpwr;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18991

write_phy_reg(pi, 0x280, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18993

regval = read_phy_reg(pi, 0x283);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18994

pi->nphy_crsminpwr[2] = regval & 0xff;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18995

regval &= 0xff00;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18996

regval |= (u16) minpwr;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

18997

write_phy_reg(pi, 0x283, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19003

regval = read_phy_reg(pi, 0x27d);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19004

regval &= 0xff00;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19005

regval |= pi->nphy_crsminpwr[0];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19006

write_phy_reg(pi, 0x27d, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19008

regval = read_phy_reg(pi, 0x280);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19009

regval &= 0xff00;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19010

regval |= pi->nphy_crsminpwr[1];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19011

write_phy_reg(pi, 0x280, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19013

regval = read_phy_reg(pi, 0x283);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19014

regval &= 0xff00;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19015

regval |= pi->nphy_crsminpwr[2];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19016

write_phy_reg(pi, 0x283, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19627

u16 regval;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19647

regval = read_phy_reg(pi, 0xa2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19648

regval &= ~(0xf << 4);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19649

regval |= ((u16) (rxcore_bitmask & 0x3)) << 4;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19650

write_phy_reg(pi, 0xa2, regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19707

u16 regval, rxen_bits;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19710

regval = read_phy_reg(pi, 0xa2);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

19711

rxen_bits = (regval >> 4) & 0xf;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28157

u16 regval[84];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28188

regval[ctr] = 0;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28190

regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28192

regval);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28310

u16 regval[2];

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28473

regval[0] = (u16) iqcomp_a;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28474

regval[1] = (u16) iqcomp_b;

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

28477

regval);

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

1268

u32 regval;

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

1271

ret = mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &regval, false);

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

1275

*val = regval;

drivers/net/wireless/mediatek/mt76/mt7925/debugfs.c

11

u32 regval = val;

drivers/net/wireless/mediatek/mt76/mt7925/debugfs.c

14

mt7925_mcu_regval(dev, dev->mt76.debugfs_reg, &regval, true);

drivers/net/wireless/mediatek/mt76/mt7925/debugfs.c

24

u32 regval;

drivers/net/wireless/mediatek/mt76/mt7925/debugfs.c

28

ret = mt7925_mcu_regval(dev, dev->mt76.debugfs_reg, &regval, false);

drivers/net/wireless/mediatek/mt76/mt7925/debugfs.c

31

*val = regval;

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

849

u32 regval;

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

852

ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &regval, false);

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

856

*val = regval;

drivers/net/wireless/mediatek/mt76/mt7996/init.c

1217

u32 regval, val = mt76_rr(dev, MT_PAD_GPIO);

drivers/net/wireless/mediatek/mt76/mt7996/init.c

1230

ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), &regval, false);

drivers/net/wireless/mediatek/mt76/mt7996/init.c

1239

adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK);

drivers/net/wireless/mediatek/mt76/mt7996/init.c

1244

adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK);

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c

223

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c

227

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c

229

regval | BIT(13) | BIT(0) | BIT(1));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c

72

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c

77

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c

79

regval | BIT(13) | BIT(0) | BIT(1));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c

100

rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c

94

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c

99

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

424

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

429

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

431

regval | BIT(13) | BIT(0) | BIT(1));

drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c

389

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c

394

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c

396

regval | BIT(13) | BIT(0) | BIT(1));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c

212

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c

217

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c

219

regval | BIT(13) | BIT(0) | BIT(1));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c

104

regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c

106

regval | BIT(13) | BIT(0) | BIT(1));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c

99

u16 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c

290

u8 regval;

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c

295

regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c

296

regval |= FEN_PCIEA;

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c

297

rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c

299

regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);

drivers/net/wireless/realtek/rtw88/rtw8703b.c

984

u32 regval;

drivers/net/wireless/realtek/rtw88/rtw8703b.c

999

ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000,

drivers/net/wireless/realtek/rtw88/rtw8821c.c

843

u8 regval = 0;

drivers/net/wireless/realtek/rtw88/rtw8821c.c

877

regval = 0x3;

drivers/net/wireless/realtek/rtw88/rtw8821c.c

879

regval = (!polarity_inverse ? 0x2 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

881

regval = (!polarity_inverse ? 0x2 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

883

regval = (!polarity_inverse ? 0x1 : 0x2);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

887

regval);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

896

regval = (!polarity_inverse ? 0x2 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

898

regval);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

909

regval = (!polarity_inverse ? 0x0 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

911

regval);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1132

u8 regval = 0;

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1158

regval = 0x3;

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1160

regval = (!polarity_inverse ? 0x2 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1162

regval = (!polarity_inverse ? 0x2 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1164

regval = (!polarity_inverse ? 0x1 : 0x2);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1167

rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1177

regval = (!polarity_inverse ? 0x2 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1178

rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1191

regval = (!polarity_inverse ? 0x0 : 0x1);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1192

rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);

drivers/nvmem/meson-mx-efuse.c

120

regval,

drivers/nvmem/meson-mx-efuse.c

121

(!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),

drivers/nvmem/meson-mx-efuse.c

92

u32 regval;

drivers/nvmem/meson-mx-efuse.c

95

regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);

drivers/nvmem/meson-mx-efuse.c

97

MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);

drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

34

u32 regval;

drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

49

regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN);

drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

51

(regval & ~GENMASK(0, 0)));

drivers/pci/controller/dwc/pcie-histb.c

157

u32 regval;

drivers/pci/controller/dwc/pcie-histb.c

160

regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0);

drivers/pci/controller/dwc/pcie-histb.c

163

return ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) &&

drivers/pci/controller/dwc/pcie-histb.c

170

u32 regval;

drivers/pci/controller/dwc/pcie-histb.c

173

regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7);

drivers/pci/controller/dwc/pcie-histb.c

174

regval |= PCIE_APP_LTSSM_ENABLE;

drivers/pci/controller/dwc/pcie-histb.c

175

histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval);

drivers/pci/controller/dwc/pcie-histb.c

184

u32 regval;

drivers/pci/controller/dwc/pcie-histb.c

189

regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);

drivers/pci/controller/dwc/pcie-histb.c

190

regval &= ~PCIE_DEVICE_TYPE_MASK;

drivers/pci/controller/dwc/pcie-histb.c

191

regval |= PCIE_WM_RC;

drivers/pci/controller/dwc/pcie-histb.c

192

histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);

drivers/phy/allwinner/phy-sun4i-usb.c

569

u32 regval;

drivers/phy/allwinner/phy-sun4i-usb.c

571

regval = readl(data->base + REG_PHY_OTGCTL);

drivers/phy/allwinner/phy-sun4i-usb.c

574

regval &= ~OTGCTL_ROUTE_MUSB;

drivers/phy/allwinner/phy-sun4i-usb.c

577

regval |= OTGCTL_ROUTE_MUSB;

drivers/phy/allwinner/phy-sun4i-usb.c

579

writel(regval, data->base + REG_PHY_OTGCTL);

drivers/phy/hisilicon/phy-hi3670-pcie.c

186

u32 regval;

drivers/phy/hisilicon/phy-hi3670-pcie.c

188

regval = hi3670_apb_phy_readl(phy, reg);

drivers/phy/hisilicon/phy-hi3670-pcie.c

189

regval &= ~mask;

drivers/phy/hisilicon/phy-hi3670-pcie.c

190

regval |= val;

drivers/phy/hisilicon/phy-hi3670-pcie.c

191

hi3670_apb_phy_writel(phy, regval, reg);

drivers/phy/marvell/phy-berlin-sata.c

100

regval = readl(priv->base + HOST_VSA_DATA);

drivers/phy/marvell/phy-berlin-sata.c

101

regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;

drivers/phy/marvell/phy-berlin-sata.c

102

writel(regval, priv->base + HOST_VSA_DATA);

drivers/phy/marvell/phy-berlin-sata.c

122

regval = readl(ctrl_reg + PORT_SCR_CTL);

drivers/phy/marvell/phy-berlin-sata.c

123

regval &= ~GENMASK(7, 4);

drivers/phy/marvell/phy-berlin-sata.c

124

regval |= 0x30;

drivers/phy/marvell/phy-berlin-sata.c

125

writel(regval, ctrl_reg + PORT_SCR_CTL);

drivers/phy/marvell/phy-berlin-sata.c

138

u32 regval;

drivers/phy/marvell/phy-berlin-sata.c

146

regval = readl(priv->base + HOST_VSA_DATA);

drivers/phy/marvell/phy-berlin-sata.c

147

regval |= desc->power_bit;

drivers/phy/marvell/phy-berlin-sata.c

148

writel(regval, priv->base + HOST_VSA_DATA);

drivers/phy/marvell/phy-berlin-sata.c

69

u32 regval;

drivers/phy/marvell/phy-berlin-sata.c

75

regval = readl(ctrl_reg + PORT_VSR_DATA);

drivers/phy/marvell/phy-berlin-sata.c

76

regval &= ~mask;

drivers/phy/marvell/phy-berlin-sata.c

77

regval |= val;

drivers/phy/marvell/phy-berlin-sata.c

78

writel(regval, ctrl_reg + PORT_VSR_DATA);

drivers/phy/marvell/phy-berlin-sata.c

86

u32 regval;

drivers/phy/marvell/phy-berlin-sata.c

94

regval = readl(priv->base + HOST_VSA_DATA);

drivers/phy/marvell/phy-berlin-sata.c

95

regval &= ~desc->power_bit;

drivers/phy/marvell/phy-berlin-sata.c

96

writel(regval, priv->base + HOST_VSA_DATA);

drivers/phy/mscc/phy-ocelot-serdes.c

270

unsigned int regval;

drivers/phy/mscc/phy-ocelot-serdes.c

275

return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval,

drivers/phy/mscc/phy-ocelot-serdes.c

276

(regval & op) != op, 100,

drivers/phy/mscc/phy-ocelot-serdes.c

38

unsigned int regval = 0;

drivers/phy/mscc/phy-ocelot-serdes.c

43

return regmap_read_poll_timeout(regmap, HSIO_MCB_S6G_ADDR_CFG, regval,

drivers/phy/mscc/phy-ocelot-serdes.c

44

(regval & op) != op, 100,

drivers/phy/sophgo/phy-cv1800-usb2.c

46

unsigned int regval = 0;

drivers/phy/sophgo/phy-cv1800-usb2.c

53

regval = PHY_ID_OVERWRITE_EN | PHY_ID_OVERWRITE_MODE_DEVICE;

drivers/phy/sophgo/phy-cv1800-usb2.c

57

regval = PHY_ID_OVERWRITE_EN | PHY_ID_OVERWRITE_MODE_HOST;

drivers/phy/sophgo/phy-cv1800-usb2.c

64

ret = regmap_read(phy->syscon, REG_USB_PHY_CTRL, &regval);

drivers/phy/sophgo/phy-cv1800-usb2.c

68

regval = FIELD_GET(PHY_ID_OVERWRITE_MODE, regval);

drivers/phy/sophgo/phy-cv1800-usb2.c

76

regval);

drivers/phy/tegra/xusb.h

485

u32 regval;

drivers/phy/tegra/xusb.h

488

err = readl_poll_timeout(padctl->regs + offset, regval,

drivers/phy/tegra/xusb.h

489

(regval & mask) == val, 1, us);

drivers/phy/tegra/xusb.h

492

regval);

drivers/pinctrl/cirrus/pinctrl-madera-core.c

432

u16 regval)

drivers/pinctrl/cirrus/pinctrl-madera-core.c

434

regval = (regval & MADERA_GP1_DRV_STR_MASK) >> MADERA_GP1_DRV_STR_SHIFT;

drivers/pinctrl/cirrus/pinctrl-madera-core.c

436

switch (regval) {

drivers/pinctrl/nuvoton/pinctrl-ma35.c

278

u32 i, regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

284

regmap_read(npctl->regmap, setting->offset, &regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

285

regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,

drivers/pinctrl/nuvoton/pinctrl-ma35.c

287

regval |= setting->muxval << setting->shift;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

288

regmap_write(npctl->regmap, setting->offset, regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

304

u32 regval = readl(reg_mode);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

306

regval &= ~MA35_GP_MODE_MASK(gpio);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

307

regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

309

writel(regval, reg_mode);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

314

u32 regval = readl(reg_mode);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

316

return field_get(MA35_GP_MODE_MASK(gpio), regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

336

unsigned int regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

340

regval = readl(reg_dout);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

342

regval |= BIT(gpio);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

344

regval &= ~BIT(gpio);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

345

writel(regval, reg_dout);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

364

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

367

regval = readl(reg_dout) | BIT(gpio);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

369

regval = readl(reg_dout) & ~BIT(gpio);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

371

writel(regval, reg_dout);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

379

u32 reg_offs, bit_offs, regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

391

regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, &regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

392

regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

393

regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

412

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

414

regval = readl(reg_ien);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

416

regval &= ~MA35_GP_INTEN_BOTH(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

418

writel(regval, reg_ien);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

427

u32 bval, regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

430

regval = readl(reg_itype);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

431

regval &= ~BIT(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

432

writel(regval | bval, reg_itype);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

435

regval = readl(reg_ien);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

436

regval &= ~MA35_GP_INTEN_BOTH(hwirq);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

437

writel(regval | bval, reg_ien);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

619

u32 regval, pull_sel = MA35_GP_PUSEL_DISABLE;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

624

regval = readl(base + MA35_GP_REG_PUSEL);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

625

regval &= ~MA35_GP_PUSEL_MASK(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

641

regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

642

writel(regval, base + MA35_GP_REG_PUSEL);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

667

u32 regval, pull_sel;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

672

regval = readl(base + MA35_GP_REG_PUSEL);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

674

pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

707

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

712

regval = readl(base + MA35_GP_REG_SPW);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

714

if (regval & BIT(port))

drivers/pinctrl/nuvoton/pinctrl-ma35.c

725

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

733

regval = readl(base + MA35_GP_REG_SPW);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

736

regval &= ~BIT(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

738

regval |= BIT(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

740

writel(regval, base + MA35_GP_REG_SPW);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

750

u32 regval, ds_val;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

755

regval = readl(base + MA35_GP_DS_REG(port));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

756

ds_val = field_get(MA35_GP_DS_MASK(port), regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

772

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

795

regval = readl(base + MA35_GP_DS_REG(port));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

796

regval &= ~MA35_GP_DS_MASK(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

797

regval |= field_prep(MA35_GP_DS_MASK(port), ds_val);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

799

writel(regval, base + MA35_GP_DS_REG(port));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

808

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

813

regval = readl(base + MA35_GP_REG_SMTEN);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

815

return !!(regval & BIT(port));

drivers/pinctrl/nuvoton/pinctrl-ma35.c

822

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

827

regval = readl(base + MA35_GP_REG_SMTEN);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

830

regval |= BIT(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

832

regval &= ~BIT(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

834

writel(regval, base + MA35_GP_REG_SMTEN);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

843

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

848

regval = readl(base + MA35_GP_REG_SLEWCTL);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

850

return field_get(MA35_GP_SLEWCTL_MASK(port), regval);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

857

u32 regval;

drivers/pinctrl/nuvoton/pinctrl-ma35.c

862

regval = readl(base + MA35_GP_REG_SLEWCTL);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

863

regval &= ~MA35_GP_SLEWCTL_MASK(port);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

864

regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

866

writel(regval, base + MA35_GP_REG_SLEWCTL);

drivers/pinctrl/pinctrl-amd.c

618

u32 regval;

drivers/pinctrl/pinctrl-amd.c

638

regval = readl(regs + i);

drivers/pinctrl/pinctrl-amd.c

640

if (regval & PIN_IRQ_PENDING)

drivers/pinctrl/pinctrl-amd.c

642

irqnr + i, regval);

drivers/pinctrl/pinctrl-amd.c

645

if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))

drivers/pinctrl/pinctrl-amd.c

648

if (!(regval & PIN_IRQ_PENDING) ||

drivers/pinctrl/pinctrl-amd.c

649

!(regval & BIT(INTERRUPT_MASK_OFF)))

drivers/pinctrl/pinctrl-amd.c

661

regval = readl(regs + i);

drivers/pinctrl/pinctrl-amd.c

663

regval &= ~BIT(INTERRUPT_MASK_OFF);

drivers/pinctrl/pinctrl-amd.c

670

writel(regval, regs + i);

drivers/pinctrl/pinctrl-amd.c

680

regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);

drivers/pinctrl/pinctrl-amd.c

681

regval |= EOI_MASK;

drivers/pinctrl/pinctrl-amd.c

682

writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);

drivers/pinctrl/pinctrl-artpec6.c

657

unsigned int regval, val;

drivers/pinctrl/pinctrl-artpec6.c

684

regval = readl(pmx->base + reg);

drivers/pinctrl/pinctrl-artpec6.c

685

regval &= ~ARTPEC6_PINMUX_SEL_MASK;

drivers/pinctrl/pinctrl-artpec6.c

686

regval |= val;

drivers/pinctrl/pinctrl-artpec6.c

687

writel(regval, pmx->base + reg);

drivers/pinctrl/pinctrl-artpec6.c

738

unsigned int regval;

drivers/pinctrl/pinctrl-artpec6.c

751

regval = readl(pmx->base + artpec6_pmx_reg_offset(pin));

drivers/pinctrl/pinctrl-artpec6.c

756

if (!(regval & ARTPEC6_PINMUX_UDC1_MASK))

drivers/pinctrl/pinctrl-artpec6.c

762

if (regval & ARTPEC6_PINMUX_UDC1_MASK)

drivers/pinctrl/pinctrl-artpec6.c

765

regval = regval & ARTPEC6_PINMUX_UDC0_MASK;

drivers/pinctrl/pinctrl-artpec6.c

766

if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) ||

drivers/pinctrl/pinctrl-artpec6.c

767

(param == PIN_CONFIG_BIAS_PULL_DOWN && regval))

drivers/pinctrl/pinctrl-artpec6.c

771

regval = (regval & ARTPEC6_PINMUX_DRV_MASK)

drivers/pinctrl/pinctrl-artpec6.c

773

regval = artpec6_pconf_drive_field_to_mA(regval);

drivers/pinctrl/pinctrl-artpec6.c

774

*config = pinconf_to_config_packed(param, regval);

drivers/pinctrl/pinctrl-artpec6.c

800

unsigned int regval;

drivers/pinctrl/pinctrl-artpec6.c

825

regval = readl(reg);

drivers/pinctrl/pinctrl-artpec6.c

826

regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT);

drivers/pinctrl/pinctrl-artpec6.c

827

writel(regval, reg);

drivers/pinctrl/pinctrl-artpec6.c

837

regval = readl(reg);

drivers/pinctrl/pinctrl-artpec6.c

838

regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT);

drivers/pinctrl/pinctrl-artpec6.c

839

regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */

drivers/pinctrl/pinctrl-artpec6.c

840

writel(regval, reg);

drivers/pinctrl/pinctrl-artpec6.c

850

regval = readl(reg);

drivers/pinctrl/pinctrl-artpec6.c

851

regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT);

drivers/pinctrl/pinctrl-artpec6.c

852

regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */

drivers/pinctrl/pinctrl-artpec6.c

853

writel(regval, reg);

drivers/pinctrl/pinctrl-artpec6.c

864

regval = readl(reg);

drivers/pinctrl/pinctrl-artpec6.c

865

regval &= ~ARTPEC6_PINMUX_DRV_MASK;

drivers/pinctrl/pinctrl-artpec6.c

866

regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT);

drivers/pinctrl/pinctrl-artpec6.c

867

writel(regval, reg);

drivers/pinctrl/pinctrl-bm1880.c

1000

regval |= func->mux_val << mux_offset;

drivers/pinctrl/pinctrl-bm1880.c

1002

writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);

drivers/pinctrl/pinctrl-bm1880.c

1017

u32 *regval, u32 bit_offset)

drivers/pinctrl/pinctrl-bm1880.c

1021

_regval = *regval;

drivers/pinctrl/pinctrl-bm1880.c

1087

*regval = _regval;

drivers/pinctrl/pinctrl-bm1880.c

1158

u32 regval, offset, bit_offset;

drivers/pinctrl/pinctrl-bm1880.c

1162

regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);

drivers/pinctrl/pinctrl-bm1880.c

1167

arg = !!(regval & BIT(bit_offset));

drivers/pinctrl/pinctrl-bm1880.c

1171

arg = !!(regval & BIT(bit_offset));

drivers/pinctrl/pinctrl-bm1880.c

1175

arg = !!(regval & BIT(bit_offset));

drivers/pinctrl/pinctrl-bm1880.c

1179

arg = !!(regval & BIT(bit_offset));

drivers/pinctrl/pinctrl-bm1880.c

1183

arg = !!(regval & BIT(bit_offset));

drivers/pinctrl/pinctrl-bm1880.c

1188

!!(regval & BIT(bit_offset)));

drivers/pinctrl/pinctrl-bm1880.c

1209

u32 regval, offset, bit_offset;

drivers/pinctrl/pinctrl-bm1880.c

1213

regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);

drivers/pinctrl/pinctrl-bm1880.c

1222

regval |= BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1226

regval |= BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1230

regval |= BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1235

regval |= BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1237

regval &= ~BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1242

regval |= BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1244

regval &= ~BIT(bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1250

&regval, bit_offset);

drivers/pinctrl/pinctrl-bm1880.c

1262

writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);

drivers/pinctrl/pinctrl-bm1880.c

996

u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +

drivers/pinctrl/pinctrl-bm1880.c

999

regval &= ~(0x03 << mux_offset);

drivers/pinctrl/pinctrl-equilibrium.c

470

u32 regval, mask;

drivers/pinctrl/pinctrl-equilibrium.c

523

regval = readl(mem);

drivers/pinctrl/pinctrl-equilibrium.c

524

regval = (regval & ~mask) | ((val << offset) & mask);

drivers/pinctrl/pinctrl-equilibrium.c

525

writel(regval, mem);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1146

u32 regval;

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1178

regval = readl(pctl->membase + reg);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1179

regval &= ~(IRQ_CFG_IRQ_MASK << index);

drivers/pinctrl/sunxi/pinctrl-sunxi.c

1180

writel(regval | (mode << index), pctl->membase + reg);

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

374

u32 regval;

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

388

regval = padctl_readl(padctl, lane->offset);

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

391

regval &= ~BIT(lane->iddq);

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

393

regval |= BIT(lane->iddq);

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

395

padctl_writel(padctl, regval, lane->offset);

drivers/platform/mellanox/mlx-platform.c

2953

u32 regval;

drivers/platform/mellanox/mlx-platform.c

2956

err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, &regval);

drivers/platform/mellanox/mlx-platform.c

2963

regval | MLXPLAT_CPLD_LATCH_RST_MASK);

drivers/platform/mellanox/mlx-platform.c

2967

regval & ~MLXPLAT_CPLD_LATCH_RST_MASK);

drivers/platform/mellanox/mlx-platform.c

7410

u32 regval;

drivers/platform/mellanox/mlx-platform.c

7413

ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, &regval);

drivers/platform/mellanox/mlx-platform.c

7415

if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK)

drivers/platform/mellanox/mlx-platform.c

8118

u32 regval;

drivers/platform/mellanox/mlx-platform.c

8122

&regval);

drivers/platform/mellanox/mlx-platform.c

8126

if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {

drivers/platform/mellanox/mlxreg-dpu.c

454

u32 regval;

drivers/platform/mellanox/mlxreg-dpu.c

458

err = regmap_read(regmap, MLXREG_DPU_REG_CONFIG3_OFFSET, &regval);

drivers/platform/mellanox/mlxreg-dpu.c

462

switch (regval) {

drivers/platform/mellanox/mlxreg-hotplug.c

214

u32 regval;

drivers/platform/mellanox/mlxreg-hotplug.c

221

ret = regmap_read(priv->regmap, data->reg, &regval);

drivers/platform/mellanox/mlxreg-hotplug.c

226

regval &= data->mask;

drivers/platform/mellanox/mlxreg-hotplug.c

230

regval = !(regval & data->mask);

drivers/platform/mellanox/mlxreg-hotplug.c

232

regval = !!(regval & data->mask);

drivers/platform/mellanox/mlxreg-hotplug.c

235

return sysfs_emit(buf, "%u\n", regval);

drivers/platform/mellanox/mlxreg-hotplug.c

258

u32 regval;

drivers/platform/mellanox/mlxreg-hotplug.c

273

&regval);

drivers/platform/mellanox/mlxreg-hotplug.c

277

item->mask = GENMASK((regval & item->mask) - 1, 0);

drivers/platform/mellanox/mlxreg-hotplug.c

293

data->capability, &regval);

drivers/platform/mellanox/mlxreg-hotplug.c

297

if (!(regval & data->bit)) {

drivers/platform/mellanox/mlxreg-hotplug.c

348

u32 regval, bit;

drivers/platform/mellanox/mlxreg-hotplug.c

358

ret = regmap_read(priv->regmap, item->reg, &regval);

drivers/platform/mellanox/mlxreg-hotplug.c

363

regval &= item->mask;

drivers/platform/mellanox/mlxreg-hotplug.c

364

asserted = item->cache ^ regval;

drivers/platform/mellanox/mlxreg-hotplug.c

365

item->cache = regval;

drivers/platform/mellanox/mlxreg-hotplug.c

374

if (regval & BIT(bit)) {

drivers/platform/mellanox/mlxreg-hotplug.c

407

u32 regval;

drivers/platform/mellanox/mlxreg-hotplug.c

418

ret = regmap_read(priv->regmap, data->reg, &regval);

drivers/platform/mellanox/mlxreg-hotplug.c

422

regval &= data->mask;

drivers/platform/mellanox/mlxreg-hotplug.c

424

if (item->cache == regval)

drivers/platform/mellanox/mlxreg-hotplug.c

434

if (regval == MLXREG_HOTPLUG_GOOD_HEALTH_MASK) {

drivers/platform/mellanox/mlxreg-hotplug.c

455

item->cache = regval;

drivers/platform/mellanox/mlxreg-hotplug.c

507

u32 regval, aggr_asserted;

drivers/platform/mellanox/mlxreg-hotplug.c

523

ret = regmap_read(priv->regmap, pdata->cell, &regval);

drivers/platform/mellanox/mlxreg-hotplug.c

527

regval &= pdata->mask;

drivers/platform/mellanox/mlxreg-hotplug.c

528

aggr_asserted = priv->aggr_cache ^ regval;

drivers/platform/mellanox/mlxreg-hotplug.c

529

priv->aggr_cache = regval;

drivers/platform/mellanox/mlxreg-hotplug.c

587

u32 regval;

drivers/platform/mellanox/mlxreg-hotplug.c

610

data->capability, &regval);

drivers/platform/mellanox/mlxreg-hotplug.c

614

if (!(regval & data->bit))

drivers/platform/mellanox/mlxreg-io.c

102

*regval |= rol32(val, regsize * i * 8);

drivers/platform/mellanox/mlxreg-io.c

117

u32 regval = 0;

drivers/platform/mellanox/mlxreg-io.c

123

priv->regsize, &regval);

drivers/platform/mellanox/mlxreg-io.c

129

return sysfs_emit(buf, "%u\n", regval);

drivers/platform/mellanox/mlxreg-io.c

143

u32 input_val, regval;

drivers/platform/mellanox/mlxreg-io.c

157

priv->regsize, &regval);

drivers/platform/mellanox/mlxreg-io.c

161

ret = regmap_write(priv->pdata->regmap, data->reg, regval);

drivers/platform/mellanox/mlxreg-io.c

49

bool rw_flag, int regsize, u32 *regval)

drivers/platform/mellanox/mlxreg-io.c

53

ret = regmap_read(regmap, data->reg, regval);

drivers/platform/mellanox/mlxreg-io.c

73

*regval = !!(*regval & ~data->mask);

drivers/platform/mellanox/mlxreg-io.c

76

*regval &= data->mask;

drivers/platform/mellanox/mlxreg-io.c

78

*regval |= ~data->mask;

drivers/platform/mellanox/mlxreg-io.c

84

*regval = ror32(*regval & data->mask, (data->bit - 1));

drivers/platform/mellanox/mlxreg-io.c

89

*regval = (*regval & ~data->mask) | in_val;

drivers/platform/mellanox/mlxreg-lc.c

460

u32 regval;

drivers/platform/mellanox/mlxreg-lc.c

463

err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_pwr, &regval);

drivers/platform/mellanox/mlxreg-lc.c

468

regval |= BIT(mlxreg_lc->data->slot - 1);

drivers/platform/mellanox/mlxreg-lc.c

470

regval &= ~BIT(mlxreg_lc->data->slot - 1);

drivers/platform/mellanox/mlxreg-lc.c

472

err = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_pwr, regval);

drivers/platform/mellanox/mlxreg-lc.c

480

u32 regval;

drivers/platform/mellanox/mlxreg-lc.c

491

err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_ena, &regval);

drivers/platform/mellanox/mlxreg-lc.c

496

regval |= BIT(mlxreg_lc->data->slot - 1);

drivers/platform/mellanox/mlxreg-lc.c

498

regval &= ~BIT(mlxreg_lc->data->slot - 1);

drivers/platform/mellanox/mlxreg-lc.c

500

err = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_ena, regval);

drivers/platform/mellanox/mlxreg-lc.c

646

u32 regval;

drivers/platform/mellanox/mlxreg-lc.c

669

err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_pwr, &regval);

drivers/platform/mellanox/mlxreg-lc.c

673

if (regval & mlxreg_lc->data->mask) {

drivers/platform/mellanox/mlxreg-lc.c

683

err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_sync, &regval);

drivers/platform/mellanox/mlxreg-lc.c

688

if (regval & mlxreg_lc->data->mask) {

drivers/platform/mellanox/mlxreg-lc.c

719

u32 regval;

drivers/platform/mellanox/mlxreg-lc.c

723

err = (!err) ? regmap_read(regmap, MLXREG_LC_REG_CONFIG_OFFSET, &regval) : err;

drivers/platform/mellanox/mlxreg-lc.c

726

regval = (regval & GENMASK(7, 0)) << 8 | (lsb & GENMASK(7, 0));

drivers/platform/mellanox/mlxreg-lc.c

727

switch (regval) {

drivers/platform/x86/intel/plr_tpmi.c

126

u64 regval;

drivers/platform/x86/intel/plr_tpmi.c

131

regval = FIELD_PREP(PLR_MODULE_ID_MASK, tpmi_get_punit_core_number(cpu));

drivers/platform/x86/intel/plr_tpmi.c

132

regval |= PLR_RUN_BUSY;

drivers/platform/x86/intel/plr_tpmi.c

134

plr_write(regval, plr_die, PLR_MAILBOX_INTERFACE);

drivers/platform/x86/intel/plr_tpmi.c

136

ret = readq_poll_timeout(plr_die->base + PLR_MAILBOX_INTERFACE, regval,

drivers/platform/x86/intel/plr_tpmi.c

137

!(regval & PLR_RUN_BUSY), PLR_TIMEOUT_US,

drivers/platform/x86/intel/plr_tpmi.c

149

u64 regval;

drivers/platform/x86/intel/plr_tpmi.c

153

regval = FIELD_PREP(PLR_MODULE_ID_MASK, tpmi_get_punit_core_number(cpu));

drivers/platform/x86/intel/plr_tpmi.c

154

regval |= PLR_RUN_BUSY | PLR_COMMAND_WRITE;

drivers/platform/x86/intel/plr_tpmi.c

158

plr_write(regval, plr_die, PLR_MAILBOX_INTERFACE);

drivers/platform/x86/intel/plr_tpmi.c

160

return readq_poll_timeout(plr_die->base + PLR_MAILBOX_INTERFACE, regval,

drivers/platform/x86/intel/plr_tpmi.c

161

!(regval & PLR_RUN_BUSY), PLR_TIMEOUT_US,

drivers/platform/x86/uniwill/uniwill-acpi.c

1484

unsigned int regval;

drivers/platform/x86/uniwill/uniwill-acpi.c

1517

ret = regmap_read(data->regmap, EC_ADDR_BAT_ALERT, &regval);

drivers/platform/x86/uniwill/uniwill-acpi.c

1521

if (regval) {

drivers/platform/x86/uniwill/uniwill-acpi.c

1530

ret = regmap_read(data->regmap, EC_ADDR_CHARGE_CTRL, &regval);

drivers/platform/x86/uniwill/uniwill-acpi.c

1534

regval = FIELD_GET(CHARGE_CTRL_MASK, regval);

drivers/platform/x86/uniwill/uniwill-acpi.c

1535

val->intval = uniwill_sanitize_battery_threshold(regval);

drivers/power/supply/adp5061.c

177

unsigned int regval;

drivers/power/supply/adp5061.c

180

ret = regmap_read(st->regmap, ADP5061_VINX_SET, &regval);

drivers/power/supply/adp5061.c

184

mode = ADP5061_VINX_SET_ILIM_MODE(regval);

drivers/power/supply/adp5061.c

227

unsigned int regval;

drivers/power/supply/adp5061.c

230

ret = regmap_read(st->regmap, ADP5061_VOLTAGE_TH, &regval);

drivers/power/supply/adp5061.c

234

regval = ((regval & ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK) >> 3);

drivers/power/supply/adp5061.c

235

val->intval = adp5061_vmin[regval] * 1000;

drivers/power/supply/adp5061.c

243

unsigned int regval;

drivers/power/supply/adp5061.c

246

ret = regmap_read(st->regmap, ADP5061_TERM_SET, &regval);

drivers/power/supply/adp5061.c

250

mode = ADP5061_TERM_SET_CHG_VLIM_MODE(regval);

drivers/power/supply/adp5061.c

259

unsigned int regval;

drivers/power/supply/adp5061.c

262

ret = regmap_read(st->regmap, ADP5061_TERM_SET, &regval);

drivers/power/supply/adp5061.c

266

regval = ((regval & ADP5061_TERM_SET_VTRM_MSK) >> 2) - 0x0F;

drivers/power/supply/adp5061.c

267

if (regval >= ARRAY_SIZE(adp5061_vmax))

drivers/power/supply/adp5061.c

268

regval = ARRAY_SIZE(adp5061_vmax) - 1;

drivers/power/supply/adp5061.c

270

val->intval = adp5061_vmax[regval] * 1000;

drivers/power/supply/adp5061.c

337

unsigned int regval;

drivers/power/supply/adp5061.c

340

ret = regmap_read(st->regmap, ADP5061_CHG_CURR, &regval);

drivers/power/supply/adp5061.c

344

regval = ((regval & ADP5061_CHG_CURR_ICHG_MSK) >> 2);

drivers/power/supply/adp5061.c

345

if (regval >= ARRAY_SIZE(adp5061_const_ichg))

drivers/power/supply/adp5061.c

346

regval = ARRAY_SIZE(adp5061_const_ichg) - 1;

drivers/power/supply/adp5061.c

348

val->intval = adp5061_const_ichg[regval] * 1000;

drivers/power/supply/adp5061.c

356

unsigned int regval;

drivers/power/supply/adp5061.c

359

ret = regmap_read(st->regmap, ADP5061_CHG_CURR, &regval);

drivers/power/supply/adp5061.c

363

regval &= ADP5061_CHG_CURR_ITRK_DEAD_MSK;

drivers/power/supply/adp5061.c

364

val->intval = adp5061_prechg_current[regval] * 1000;

drivers/power/supply/adp5061.c

389

unsigned int regval;

drivers/power/supply/adp5061.c

392

ret = regmap_read(st->regmap, ADP5061_VOLTAGE_TH, &regval);

drivers/power/supply/adp5061.c

396

regval &= ADP5061_VOLTAGE_TH_VWEAK_MSK;

drivers/power/supply/adp5061.c

397

val->intval = adp5061_vweak_th[regval] * 1000;

drivers/power/supply/adp5061.c

506

unsigned int regval;

drivers/power/supply/adp5061.c

509

ret = regmap_read(st->regmap, ADP5061_IEND, &regval);

drivers/power/supply/adp5061.c

513

regval = (regval & ADP5061_IEND_IEND_MSK) >> 5;

drivers/power/supply/adp5061.c

514

val->intval = adp5061_iend[regval];

drivers/power/supply/bd99954-charger.c

821

int regval;

drivers/power/supply/bd99954-charger.c

913

&regval, &found);

drivers/power/supply/bd99954-charger.c

926

*(battery_inits[i].data) = regval;

drivers/power/supply/bd99954-charger.c

942

property, &regval,

drivers/power/supply/bd99954-charger.c

957

*(props[i].data) = regval;

drivers/power/supply/ltc4162-l-charger.c

180

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

183

ret = regmap_read(info->regmap, LTC4162L_CHARGER_STATE, &regval);

drivers/power/supply/ltc4162-l-charger.c

189

val->intval = ltc4162l_state_decode(regval);

drivers/power/supply/ltc4162-l-charger.c

210

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

213

ret = regmap_read(info->regmap, LTC4162L_CHARGE_STATUS, &regval);

drivers/power/supply/ltc4162-l-charger.c

217

val->intval = ltc4162l_charge_status_decode(regval);

drivers/power/supply/ltc4162-l-charger.c

243

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

246

ret = regmap_read(info->regmap, LTC4162L_CHARGER_STATE, &regval);

drivers/power/supply/ltc4162-l-charger.c

250

val->intval = ltc4162l_state_to_health(regval);

drivers/power/supply/ltc4162-l-charger.c

258

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

261

ret = regmap_read(info->regmap, LTC4162L_SYSTEM_STATUS_REG, &regval);

drivers/power/supply/ltc4162-l-charger.c

266

val->intval = !!(regval & BIT(2));

drivers/power/supply/ltc4162-l-charger.c

275

unsigned int regval, chem_type;

drivers/power/supply/ltc4162-l-charger.c

278

ret = regmap_read(info->regmap, reg, &regval);

drivers/power/supply/ltc4162-l-charger.c

293

regval *= 1924;

drivers/power/supply/ltc4162-l-charger.c

294

regval *= ltc4162l_get_cell_count(info);

drivers/power/supply/ltc4162-l-charger.c

295

regval /= 10;

drivers/power/supply/ltc4162-l-charger.c

296

val->intval = regval;

drivers/power/supply/ltc4162-l-charger.c

300

regval *= 3848;

drivers/power/supply/ltc4162-l-charger.c

301

regval *= ltc4162l_get_cell_count(info) / 2;

drivers/power/supply/ltc4162-l-charger.c

302

regval /= 10;

drivers/power/supply/ltc4162-l-charger.c

303

val->intval = regval;

drivers/power/supply/ltc4162-l-charger.c

315

unsigned int regval, chem_type;

drivers/power/supply/ltc4162-l-charger.c

318

ret = regmap_read(info->regmap, reg, &regval);

drivers/power/supply/ltc4162-l-charger.c

330

regval *= 192264;

drivers/power/supply/ltc4162-l-charger.c

331

regval *= ltc4162l_get_cell_count(info);

drivers/power/supply/ltc4162-l-charger.c

332

regval /= 1000;

drivers/power/supply/ltc4162-l-charger.c

333

val->intval = regval;

drivers/power/supply/ltc4162-l-charger.c

337

regval *= 128176;

drivers/power/supply/ltc4162-l-charger.c

338

regval *= ltc4162l_get_cell_count(info);

drivers/power/supply/ltc4162-l-charger.c

339

regval /= 1000;

drivers/power/supply/ltc4162-l-charger.c

340

val->intval = regval;

drivers/power/supply/ltc4162-l-charger.c

352

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

355

ret = regmap_read(info->regmap, LTC4162L_IBAT, &regval);

drivers/power/supply/ltc4162-l-charger.c

359

ret = (s16)(regval & 0xFFFF);

drivers/power/supply/ltc4162-l-charger.c

370

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

373

ret = regmap_read(info->regmap, LTC4162L_VIN, &regval);

drivers/power/supply/ltc4162-l-charger.c

377

val->intval = regval * chip_info->vin_resolution_uv;

drivers/power/supply/ltc4162-l-charger.c

386

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

389

ret = regmap_read(info->regmap, LTC4162L_IIN, &regval);

drivers/power/supply/ltc4162-l-charger.c

393

ret = (s16)(regval & 0xFFFF);

drivers/power/supply/ltc4162-l-charger.c

406

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

409

ret = regmap_read(info->regmap, reg, &regval);

drivers/power/supply/ltc4162-l-charger.c

413

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

416

++regval;

drivers/power/supply/ltc4162-l-charger.c

417

val->intval = 10000u * mult_frac(regval, 100000u, info->rsnsb);

drivers/power/supply/ltc4162-l-charger.c

444

unsigned int regval, chem_type;

drivers/power/supply/ltc4162-l-charger.c

448

ret = regmap_read(info->regmap, reg, &regval);

drivers/power/supply/ltc4162-l-charger.c

452

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

469

voltage = 3812500 + (regval * 12500);

drivers/power/supply/ltc4162-l-charger.c

475

voltage = 3412500 + (regval * 12500);

drivers/power/supply/ltc4162-l-charger.c

481

voltage = 6000000 + (regval * 28571);

drivers/power/supply/ltc4162-l-charger.c

495

unsigned int regval, chem_type;

drivers/power/supply/ltc4162-l-charger.c

499

ret = regmap_read(info->regmap, reg, &regval);

drivers/power/supply/ltc4162-l-charger.c

503

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

516

voltage = 3812500 + (regval * 12500);

drivers/power/supply/ltc4162-l-charger.c

522

voltage = 3412500 + (regval * 12500);

drivers/power/supply/ltc4162-l-charger.c

528

voltage = 2000000 + mult_frac(regval, 1000000, 105);

drivers/power/supply/ltc4162-l-charger.c

632

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

635

ret = regmap_read(info->regmap, LTC4162L_IIN_LIMIT_DAC, &regval);

drivers/power/supply/ltc4162-l-charger.c

639

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

642

++regval;

drivers/power/supply/ltc4162-l-charger.c

643

regval *= 5000000u;

drivers/power/supply/ltc4162-l-charger.c

644

regval /= info->rsnsi;

drivers/power/supply/ltc4162-l-charger.c

645

val->intval = 100u * regval;

drivers/power/supply/ltc4162-l-charger.c

653

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

655

regval = mult_frac(value, info->rsnsi, 50000u);

drivers/power/supply/ltc4162-l-charger.c

656

regval /= 10000u;

drivers/power/supply/ltc4162-l-charger.c

657

if (regval)

drivers/power/supply/ltc4162-l-charger.c

658

--regval;

drivers/power/supply/ltc4162-l-charger.c

659

if (regval > 63)

drivers/power/supply/ltc4162-l-charger.c

660

regval = 63;

drivers/power/supply/ltc4162-l-charger.c

662

return regmap_write(info->regmap, LTC4162L_IIN_LIMIT_TARGET, regval);

drivers/power/supply/ltc4162-l-charger.c

668

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

671

ret = regmap_read(info->regmap, LTC4162L_DIE_TEMPERATURE, &regval);

drivers/power/supply/ltc4162-l-charger.c

676

ret = (s16)(regval & 0xFFFF);

drivers/power/supply/ltc4162-l-charger.c

688

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

691

ret = regmap_read(info->regmap, LTC4162L_DIE_TEMPERATURE, &regval);

drivers/power/supply/ltc4162-l-charger.c

696

ret = (s16)(regval & 0xFFFF);

drivers/power/supply/ltc4162-l-charger.c

709

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

712

ret = regmap_read(info->regmap, LTC4162L_CHARGER_CONFIG_BITS, &regval);

drivers/power/supply/ltc4162-l-charger.c

717

if (!(regval & BIT(2))) {

drivers/power/supply/ltc4162-l-charger.c

722

ret = regmap_read(info->regmap, LTC4162L_C_OVER_X_THRESHOLD, &regval);

drivers/power/supply/ltc4162-l-charger.c

726

regval *= chip_info->ibat_resolution_pv;

drivers/power/supply/ltc4162-l-charger.c

727

regval /= info->rsnsb;

drivers/power/supply/ltc4162-l-charger.c

728

val->intval = regval;

drivers/power/supply/ltc4162-l-charger.c

737

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

746

regval = mult_frac(value, info->rsnsb, 14660u);

drivers/power/supply/ltc4162-l-charger.c

747

regval /= 100u;

drivers/power/supply/ltc4162-l-charger.c

749

ret = regmap_write(info->regmap, LTC4162L_C_OVER_X_THRESHOLD, regval);

drivers/power/supply/ltc4162-l-charger.c

776

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

781

ret = regmap_read(info->regmap, LTC4162L_CHARGE_STATUS, &regval);

drivers/power/supply/ltc4162-l-charger.c

787

if (regval & mask) {

drivers/power/supply/ltc4162-l-charger.c

852

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

855

ret = regmap_read(info->regmap, LTC4162L_CONFIG_BITS_REG, &regval);

drivers/power/supply/ltc4162-l-charger.c

859

return sysfs_emit(buf, "%u\n", regval &

drivers/power/supply/ltc4162-l-charger.c

893

unsigned int regval;

drivers/power/supply/ltc4162-l-charger.c

896

ret = regmap_read(info->regmap, LTC4162L_ARM_SHIP_MODE, &regval);

drivers/power/supply/ltc4162-l-charger.c

901

regval == LTC4162L_ARM_SHIP_MODE_MAGIC ? 1 : 0);

drivers/power/supply/max77705_charger.c

144

unsigned int regval;

drivers/power/supply/max77705_charger.c

146

regval = clamp_val(val, clamp_min, clamp_max) / div;

drivers/power/supply/max77705_charger.c

148

return regmap_field_write(chg->rfield[fidx], regval);

drivers/power/supply/max77705_charger.c

46

unsigned int regval, irq_status;

drivers/power/supply/max77705_charger.c

56

err = regmap_field_read(chg->rfield[MAX77705_CHG_CHGIN_LIM], &regval);

drivers/power/supply/max77705_charger.c

60

regval--;

drivers/power/supply/max77705_charger.c

62

err = regmap_field_write(chg->rfield[MAX77705_CHG_CHGIN_LIM], regval);

drivers/power/supply/max77759_charger.c

265

u32 regval, val;

drivers/power/supply/max77759_charger.c

268

ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_02, &regval);

drivers/power/supply/max77759_charger.c

272

regval = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC, regval);

drivers/power/supply/max77759_charger.c

275

regval, &val);

drivers/power/supply/max77759_charger.c

283

u32 regval;

drivers/power/supply/max77759_charger.c

287

cc_max_ua, &regval, &found);

drivers/power/supply/max77759_charger.c

292

MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC, regval);

drivers/power/supply/max77759_charger.c

297

u32 regval, val;

drivers/power/supply/max77759_charger.c

300

ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_04, &regval);

drivers/power/supply/max77759_charger.c

304

regval = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM, regval);

drivers/power/supply/max77759_charger.c

307

regval, &val);

drivers/power/supply/max77759_charger.c

314

u32 regval;

drivers/power/supply/max77759_charger.c

319

fv_mv, &regval, &found);

drivers/power/supply/max77759_charger.c

325

regval);

drivers/power/supply/max77759_charger.c

330

u32 regval, val;

drivers/power/supply/max77759_charger.c

333

ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_09, &regval);

drivers/power/supply/max77759_charger.c

337

regval = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM, regval);

drivers/power/supply/max77759_charger.c

338

regval = umax(regval, chgin_ilim_ranges[0].min_sel);

drivers/power/supply/max77759_charger.c

342

regval, &val);

drivers/power/supply/max77759_charger.c

349

u32 regval;

drivers/power/supply/max77759_charger.c

354

linear_range_get_selector_within(chgin_ilim_ranges, ilim_ua, &regval);

drivers/power/supply/max77759_charger.c

358

regval);

drivers/power/supply/max77759_charger.c

546

u32 regval, fast_chg_curr, fv;

drivers/power/supply/max77759_charger.c

549

ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_00, &regval);

drivers/power/supply/max77759_charger.c

553

chg->mode = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_00_MODE, regval);

drivers/power/supply/max77976_charger.c

126

unsigned int regval;

drivers/power/supply/max77976_charger.c

129

err = regmap_field_read(chg->rfield[CHG_DTLS], &regval);

drivers/power/supply/max77976_charger.c

133

switch (regval) {

drivers/power/supply/max77976_charger.c

164

unsigned int regval;

drivers/power/supply/max77976_charger.c

167

err = regmap_field_read(chg->rfield[CHG_DTLS], &regval);

drivers/power/supply/max77976_charger.c

171

switch (regval) {

drivers/power/supply/max77976_charger.c

202

unsigned int regval;

drivers/power/supply/max77976_charger.c

205

err = regmap_field_read(chg->rfield[BAT_DTLS], &regval);

drivers/power/supply/max77976_charger.c

209

switch (regval) {

drivers/power/supply/max77976_charger.c

236

unsigned int regval;

drivers/power/supply/max77976_charger.c

239

err = regmap_field_read(chg->rfield[CHGIN_OK], &regval);

drivers/power/supply/max77976_charger.c

243

*val = (regval ? 1 : 0);

drivers/power/supply/max77976_charger.c

252

unsigned int regval;

drivers/power/supply/max77976_charger.c

255

err = regmap_field_read(chg->rfield[fidx], &regval);

drivers/power/supply/max77976_charger.c

259

*val = clamp_val(regval * mult, clamp_min, clamp_max);

drivers/power/supply/max77976_charger.c

268

unsigned int regval;

drivers/power/supply/max77976_charger.c

270

regval = clamp_val(val, clamp_min, clamp_max) / div;

drivers/power/supply/max77976_charger.c

272

return regmap_field_write(chg->rfield[fidx], regval);

drivers/power/supply/max8971_charger.c

125

u32 regval;

drivers/power/supply/max8971_charger.c

128

err = regmap_field_read(priv->rfield[CHG_DTLS], &regval);

drivers/power/supply/max8971_charger.c

132

switch (regval) {

drivers/power/supply/max8971_charger.c

160

u32 regval;

drivers/power/supply/max8971_charger.c

163

err = regmap_field_read(priv->rfield[CHG_DTLS], &regval);

drivers/power/supply/max8971_charger.c

167

switch (regval) {

drivers/power/supply/max8971_charger.c

195

u32 regval;

drivers/power/supply/max8971_charger.c

198

err = regmap_field_read(priv->rfield[THM_DTLS], &regval);

drivers/power/supply/max8971_charger.c

202

switch (regval) {

drivers/power/supply/max8971_charger.c

228

u32 regval;

drivers/power/supply/max8971_charger.c

231

err = regmap_read(priv->regmap, MAX8971_REG_CHG_STAT, &regval);

drivers/power/supply/max8971_charger.c

237

*val = !(regval & MAX8971_CHG_MASK);

drivers/power/supply/max8971_charger.c

247

u32 regval;

drivers/power/supply/max8971_charger.c

250

err = regmap_field_read(priv->rfield[fidx], &regval);

drivers/power/supply/max8971_charger.c

254

*val = clamp_val(regval * mult, clamp_min, clamp_max);

drivers/power/supply/max8971_charger.c

262

u32 regval;

drivers/power/supply/max8971_charger.c

264

regval = clamp_val(val, clamp_min, clamp_max) / div;

drivers/power/supply/max8971_charger.c

266

return regmap_field_write(priv->rfield[fidx], regval);

drivers/power/supply/max8971_charger.c

405

u32 regval;

drivers/power/supply/max8971_charger.c

408

err = regmap_field_read(priv->rfield[FCHG_T], &regval);

drivers/power/supply/max8971_charger.c

412

switch (regval) {

drivers/power/supply/max8971_charger.c

415

regval += 3;

drivers/power/supply/max8971_charger.c

419

regval = 0;

drivers/power/supply/max8971_charger.c

423

return sysfs_emit(buf, "%u\n", regval);

drivers/power/supply/max8971_charger.c

455

u32 regval, val;

drivers/power/supply/max8971_charger.c

458

err = regmap_field_read(priv->rfield[TOPOFF_S], &regval);

drivers/power/supply/max8971_charger.c

463

val = regval * 50 + 50;

drivers/power/supply/max8971_charger.c

497

u32 regval;

drivers/power/supply/max8971_charger.c

500

err = regmap_field_read(priv->rfield[TOPOFF_T], &regval);

drivers/power/supply/max8971_charger.c

505

regval *= 10;

drivers/power/supply/max8971_charger.c

507

return sysfs_emit(buf, "%u\n", regval);

drivers/power/supply/mm8013.c

103

val->intval = regval;

drivers/power/supply/mm8013.c

106

ret = regmap_read(chip->regmap, REG_FULL_CHARGE_CAPACITY, &regval);

drivers/power/supply/mm8013.c

110

val->intval = 1000 * regval;

drivers/power/supply/mm8013.c

113

ret = regmap_read(chip->regmap, REG_DESIGN_CAPACITY, &regval);

drivers/power/supply/mm8013.c

117

val->intval = 1000 * regval;

drivers/power/supply/mm8013.c

120

ret = regmap_read(chip->regmap, REG_NOMINAL_CHARGE_CAPACITY, &regval);

drivers/power/supply/mm8013.c

124

val->intval = 1000 * regval;

drivers/power/supply/mm8013.c

127

ret = regmap_read(chip->regmap, REG_MAX_LOAD_CURRENT, &regval);

drivers/power/supply/mm8013.c

131

val->intval = -1000 * (s16)regval;

drivers/power/supply/mm8013.c

134

ret = regmap_read(chip->regmap, REG_AVERAGE_CURRENT, &regval);

drivers/power/supply/mm8013.c

138

val->intval = -1000 * (s16)regval;

drivers/power/supply/mm8013.c

141

ret = regmap_read(chip->regmap, REG_CYCLE_COUNT, &regval);

drivers/power/supply/mm8013.c

145

val->intval = regval;

drivers/power/supply/mm8013.c

148

ret = regmap_read(chip->regmap, REG_FLAGS, &regval);

drivers/power/supply/mm8013.c

152

if (regval & MM8013_FLAG_UT)

drivers/power/supply/mm8013.c

154

else if (regval & (MM8013_FLAG_ODC | MM8013_FLAG_OCC))

drivers/power/supply/mm8013.c

156

else if (regval & (MM8013_FLAG_BATLOW))

drivers/power/supply/mm8013.c

158

else if (regval & MM8013_FLAG_BATHI)

drivers/power/supply/mm8013.c

160

else if (regval & (MM8013_FLAG_OT | MM8013_FLAG_OTD | MM8013_FLAG_OTC))

drivers/power/supply/mm8013.c

166

ret = regmap_read(chip->regmap, REG_TEMPERATURE, &regval);

drivers/power/supply/mm8013.c

170

val->intval = ((s16)regval > 0);

drivers/power/supply/mm8013.c

173

ret = regmap_read(chip->regmap, REG_FLAGS, &regval);

drivers/power/supply/mm8013.c

177

if (regval & MM8013_FLAG_DSG)

drivers/power/supply/mm8013.c

179

else if (regval & MM8013_FLAG_CHG_INH)

drivers/power/supply/mm8013.c

181

else if (regval & MM8013_FLAG_CHG)

drivers/power/supply/mm8013.c

183

else if (regval & MM8013_FLAG_FC)

drivers/power/supply/mm8013.c

189

ret = regmap_read(chip->regmap, REG_TEMPERATURE, &regval);

drivers/power/supply/mm8013.c

193

val->intval = DECIKELVIN_TO_DECIDEGC(regval);

drivers/power/supply/mm8013.c

196

ret = regmap_read(chip->regmap, REG_AVERAGE_TIME_TO_EMPTY, &regval);

drivers/power/supply/mm8013.c

201

if (regval == U16_MAX)

drivers/power/supply/mm8013.c

204

val->intval = regval;

drivers/power/supply/mm8013.c

207

ret = regmap_read(chip->regmap, REG_AVERAGE_TIME_TO_FULL, &regval);

drivers/power/supply/mm8013.c

212

if (regval == U16_MAX)

drivers/power/supply/mm8013.c

215

val->intval = regval;

drivers/power/supply/mm8013.c

218

ret = regmap_read(chip->regmap, REG_VOLTAGE, &regval);

drivers/power/supply/mm8013.c

222

val->intval = 1000 * regval;

drivers/power/supply/mm8013.c

95

u32 regval;

drivers/power/supply/mm8013.c

99

ret = regmap_read(chip->regmap, REG_STATE_OF_CHARGE, &regval);

drivers/power/supply/mt6360_charger.c

161

unsigned int regval;

drivers/power/supply/mt6360_charger.c

163

ret = regmap_read(mci->regmap, MT6360_PMU_FOD_STAT, &regval);

drivers/power/supply/mt6360_charger.c

166

*pwr_rdy = (regval & MT6360_CHRDET_EXT_MASK) ? true : false;

drivers/power/supply/mt6360_charger.c

187

unsigned int regval;

drivers/power/supply/mt6360_charger.c

198

ret = regmap_read(mci->regmap, MT6360_PMU_CHG_STAT, &regval);

drivers/power/supply/mt6360_charger.c

201

regval &= MT6360_CHG_STAT_MASK;

drivers/power/supply/mt6360_charger.c

202

regval >>= MT6360_CHG_STAT_SHFT;

drivers/power/supply/mt6360_charger.c

203

switch (regval) {

drivers/power/supply/mt6360_charger.c

226

unsigned int regval;

drivers/power/supply/mt6360_charger.c

229

ret = regmap_read(mci->regmap, MT6360_PMU_CHG_STAT, &regval);

drivers/power/supply/mt6360_charger.c

233

chg_stat = (regval & MT6360_CHG_STAT_MASK) >> MT6360_CHG_STAT_SHFT;

drivers/power/supply/mt6360_charger.c

236

if (regval & MT6360_VBAT_LVL_MASK)

drivers/power/supply/rn5t618_power.c

308

unsigned int regval;

drivers/power/supply/rn5t618_power.c

312

&regval);

drivers/power/supply/rn5t618_power.c

316

val->intval = FROM_CUR_REG(regval);

drivers/power/supply/rn5t618_power.c

433

unsigned int regval;

drivers/power/supply/rn5t618_power.c

459

RN5T618_REGISET1, &regval);

drivers/power/supply/rn5t618_power.c

463

val->intval = FROM_CUR_REG(regval);

drivers/power/supply/rn5t618_power.c

523

unsigned int regval;

drivers/power/supply/rn5t618_power.c

526

ret = regmap_read(info->rn5t618->regmap, RN5T618_GCHGDET, &regval);

drivers/power/supply/rn5t618_power.c

530

switch (regval & GCHGDET_TYPE_MASK) {

drivers/power/supply/rn5t618_power.c

553

unsigned int regval;

drivers/power/supply/rn5t618_power.c

584

&regval);

drivers/power/supply/rn5t618_power.c

589

if (regval & 2) {

drivers/power/supply/rn5t618_power.c

592

&regval);

drivers/power/supply/rn5t618_power.c

596

val->intval = FROM_CUR_REG(regval);

drivers/power/supply/sbs-manager.c

101

regval = sbsm_read_word(data->client, SBSM_CMD_BATSYSSTATECONT);

drivers/power/supply/sbs-manager.c

102

if (regval < 0)

drivers/power/supply/sbs-manager.c

103

return regval;

drivers/power/supply/sbs-manager.c

104

val->intval = !!(regval & SBSM_BIT_AC_PRESENT);

drivers/power/supply/sbs-manager.c

108

regval = sbsm_read_word(data->client, SBSM_CMD_BATSYSSTATE);

drivers/power/supply/sbs-manager.c

109

if (regval < 0)

drivers/power/supply/sbs-manager.c

110

return regval;

drivers/power/supply/sbs-manager.c

112

if ((regval & SBSM_MASK_CHARGE_BAT) == 0) {

drivers/power/supply/sbs-manager.c

120

regval = sbsm_read_word(data->client, SBSM_CMD_LTC);

drivers/power/supply/sbs-manager.c

121

if (regval < 0)

drivers/power/supply/sbs-manager.c

122

return regval;

drivers/power/supply/sbs-manager.c

123

else if (regval & SBSM_BIT_TURBO)

drivers/power/supply/sbs-manager.c

149

u16 regval;

drivers/power/supply/sbs-manager.c

156

regval = val->intval ==

drivers/power/supply/sbs-manager.c

158

ret = sbsm_write_word(data->client, SBSM_CMD_LTC, regval);

drivers/power/supply/sbs-manager.c

97

int regval = 0;

drivers/power/supply/twl4030_charger.c

216

static int regval2ua(int regval, bool cgain)

drivers/power/supply/twl4030_charger.c

219

return (regval * 16618 - 8500 * 1000) / 5;

drivers/power/supply/twl4030_charger.c

221

return (regval * 16618 - 8500 * 1000) / 10;

drivers/power/supply/ucs1002_power.c

471

int ret, regval;

drivers/power/supply/ucs1002_power.c

477

ret = regmap_read(info->regmap, UCS1002_REG_OTHER_STATUS, &regval);

drivers/power/supply/ucs1002_power.c

482

info->present = regval & F_ADET_PIN;

drivers/power/supply/ucs1002_power.c

544

unsigned int regval;

drivers/power/supply/ucs1002_power.c

565

ret = regmap_read(info->regmap, UCS1002_REG_PRODUCT_ID, &regval);

drivers/power/supply/ucs1002_power.c

571

if (regval != UCS1002_PRODUCT_ID) {

drivers/power/supply/ucs1002_power.c

574

regval, UCS1002_PRODUCT_ID);

drivers/power/supply/ucs1002_power.c

614

ret = regmap_read(info->regmap, UCS1002_REG_PIN_STATUS, &regval);

drivers/power/supply/ucs1002_power.c

627

info->regulator_descriptor->enable_is_inverted = !(regval & F_SEL_PIN);

drivers/rapidio/devices/tsi721.c

1116

u32 regval;

drivers/rapidio/devices/tsi721.c

1212

regval = ioread32(priv->regs + TSI721_IBWIN_LB(i));

drivers/rapidio/devices/tsi721.c

1213

if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) {

drivers/rapidio/devices/tsi721.c

378

u32 regval;

drivers/rapidio/devices/tsi721.c

381

regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));

drivers/rapidio/devices/tsi721.c

382

regval &= ~TSI721_SR_CHINT_IDBQRCV;

drivers/rapidio/devices/tsi721.c

383

iowrite32(regval,

drivers/rapidio/devices/tsi721.c

399

u32 regval;

drivers/rapidio/devices/tsi721.c

450

regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));

drivers/rapidio/devices/tsi721.c

451

regval |= TSI721_SR_CHINT_IDBQRCV;

drivers/rapidio/devices/tsi721.c

452

iowrite32(regval,

drivers/rapidio/rio-scan.c

530

u32 regval;

drivers/rapidio/rio-scan.c

546

hopcount, RIO_COMPONENT_TAG_CSR, &regval);

drivers/rapidio/rio-scan.c

548

if (regval) {

drivers/rapidio/rio-scan.c

549

rdev = rio_get_comptag((regval & 0xffff), NULL);

drivers/rapidio/rio-scan.c

710

u32 regval;

drivers/rapidio/rio-scan.c

713

&regval);

drivers/rapidio/rio-scan.c

714

return (regval & RIO_PORT_GEN_DISCOVERED) ? 1 : 0;

drivers/rapidio/rio.c

1030

u32 regval;

drivers/rapidio/rio.c

1038

&regval);

drivers/rapidio/rio.c

1056

&regval);

drivers/rapidio/rio.c

1057

if (regval & RIO_PORT_N_MNT_RSP_RVAL) {

drivers/rapidio/rio.c

1058

*lnkresp = regval;

drivers/rapidio/rio.c

1082

u32 regval;

drivers/rapidio/rio.c

1095

if (rio_get_input_status(rdev, pnum, &regval)) {

drivers/rapidio/rio.c

1101

pnum, regval);

drivers/rapidio/rio.c

1102

far_ackid = (regval & RIO_PORT_N_MNT_RSP_ASTAT) >> 5;

drivers/rapidio/rio.c

1103

far_linkstat = regval & RIO_PORT_N_MNT_RSP_LSTAT;

drivers/rapidio/rio.c

1106

&regval);

drivers/rapidio/rio.c

1107

pr_debug("RIO_EM: SP%d_ACK_STS_CSR=0x%08x\n", pnum, regval);

drivers/rapidio/rio.c

1108

near_ackid = (regval & RIO_PORT_N_ACK_INBOUND) >> 24;

drivers/rapidio/rio.c

1117

if ((far_ackid != ((regval & RIO_PORT_N_ACK_OUTSTAND) >> 8)) ||

drivers/rapidio/rio.c

1118

(far_ackid != (regval & RIO_PORT_N_ACK_OUTBOUND))) {

drivers/rapidio/rio.c

869

u32 regval;

drivers/rapidio/rio.c

873

&regval);

drivers/rapidio/rio.c

875

regval |= RIO_PORT_N_CTL_LOCKOUT;

drivers/rapidio/rio.c

877

regval &= ~RIO_PORT_N_CTL_LOCKOUT;

drivers/rapidio/rio.c

881

regval);

drivers/rapidio/rio.c

903

u32 regval;

drivers/rapidio/rio.c

919

&regval);

drivers/rapidio/rio.c

923

&regval) < 0)

drivers/rapidio/rio.c

927

regval = regval | RIO_PORT_N_CTL_EN_RX | RIO_PORT_N_CTL_EN_TX;

drivers/rapidio/rio.c

931

ext_ftr_ptr + RIO_PORT_N_CTL_CSR(0, rmap), regval);

drivers/rapidio/rio.c

935

regval) < 0)

drivers/rapidio/switches/idt_gen2.c

199

u32 regval;

drivers/rapidio/switches/idt_gen2.c

205

IDT_RIO_DOMAIN, &regval);

drivers/rapidio/switches/idt_gen2.c

207

*sw_domain = (u8)(regval & 0xff);

drivers/rapidio/switches/idt_gen2.c

215

u32 regval;

drivers/rapidio/switches/idt_gen2.c

240

rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);

drivers/rapidio/switches/idt_gen2.c

242

regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);

drivers/rapidio/switches/idt_gen2.c

258

rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);

drivers/rapidio/switches/idt_gen2.c

260

IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |

drivers/rapidio/switches/idt_gen2.c

280

rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);

drivers/rapidio/switches/idt_gen2.c

282

regval | IDT_LANE_CTRL_GENPW);

drivers/rapidio/switches/idt_gen2.c

299

rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval);

drivers/rapidio/switches/idt_gen2.c

300

rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);

drivers/rapidio/switches/idt_gen2.c

310

rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval);

drivers/rapidio/switches/idt_gen2.c

312

regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);

drivers/rapidio/switches/idt_gen2.c

324

u32 regval, em_perrdet, em_ltlerrdet;

drivers/rapidio/switches/idt_gen2.c

333

IDT_ISLTL_ADDRESS_CAP, &regval);

drivers/rapidio/switches/idt_gen2.c

337

rio_name(rdev), em_ltlerrdet, regval);

drivers/rapidio/switches/idt_gen2.c

354

IDT_PORT_ISERR_DET(portnum), &regval);

drivers/rapidio/switches/idt_gen2.c

357

" errors 0x%x\n", rio_name(rdev), regval);

drivers/rapidio/switches/idt_gen2.c

373

u32 regval;

drivers/rapidio/switches/idt_gen2.c

375

while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) {

drivers/rapidio/switches/idt_gen2.c

376

if (!regval) /* 0 = end of log */

drivers/rapidio/switches/idt_gen2.c

379

"%08x\n", regval);

drivers/rapidio/switches/idtcps.c

105

u32 regval;

drivers/rapidio/switches/idtcps.c

111

IDTCPS_RIO_DOMAIN, &regval);

drivers/rapidio/switches/idtcps.c

113

*sw_domain = (u8)(regval & 0xff);

drivers/regulator/ab8500-ext.c

115

u8 regval;

drivers/regulator/ab8500-ext.c

127

regval = info->update_val_hp;

drivers/regulator/ab8500-ext.c

129

regval = info->update_val;

drivers/regulator/ab8500-ext.c

133

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

143

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

152

u8 regval;

drivers/regulator/ab8500-ext.c

163

regval = info->update_val_hw;

drivers/regulator/ab8500-ext.c

165

regval = 0;

drivers/regulator/ab8500-ext.c

169

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

179

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

188

u8 regval;

drivers/regulator/ab8500-ext.c

196

info->update_bank, info->update_reg, &regval);

drivers/regulator/ab8500-ext.c

206

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

208

if (((regval & info->update_mask) == info->update_val_lp) ||

drivers/regulator/ab8500-ext.c

209

((regval & info->update_mask) == info->update_val_hp))

drivers/regulator/ab8500-ext.c

220

u8 regval;

drivers/regulator/ab8500-ext.c

229

regval = info->update_val_hp;

drivers/regulator/ab8500-ext.c

232

regval = info->update_val_lp;

drivers/regulator/ab8500-ext.c

247

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

258

info->update_mask, regval);

drivers/regulator/ab8500-ext.c

261

info->update_val = regval;

drivers/regulator/ab8500.c

351

u8 regval;

drivers/regulator/ab8500.c

359

info->update_bank, info->update_reg, &regval);

drivers/regulator/ab8500.c

370

info->update_mask, regval);

drivers/regulator/ab8500.c

372

if (regval & info->update_mask)

drivers/regulator/ab8500.c

538

u8 regval;

drivers/regulator/ab8500.c

548

info->voltage_bank, info->voltage_reg, &regval);

drivers/regulator/ab8500.c

560

voltage_shift, regval);

drivers/regulator/ab8500.c

562

return (regval & info->voltage_mask) >> voltage_shift;

drivers/regulator/ab8500.c

570

u8 regval;

drivers/regulator/ab8500.c

580

regval = (u8)selector << voltage_shift;

drivers/regulator/ab8500.c

583

info->voltage_mask, regval);

drivers/regulator/ab8500.c

592

info->voltage_mask, regval);

drivers/regulator/adp5055-regulator.c

284

int id, ret, regval;

drivers/regulator/adp5055-regulator.c

288

ret = regmap_read(adp5055->regmap, ADP5055_CTRL_MODE2, &regval);

drivers/regulator/adp5055-regulator.c

292

if (regval & (ADP5055_MASK_PSM << id))

drivers/regulator/lp8755.c

111

unsigned int regval;

drivers/regulator/lp8755.c

114

ret = regmap_read(rdev->regmap, 0x06, &regval);

drivers/regulator/lp8755.c

119

if (regval & (0x01 << id))

drivers/regulator/lp8755.c

122

ret = regmap_read(rdev->regmap, 0x08 + id, &regval);

drivers/regulator/lp8755.c

127

if (regval & 0x20)

drivers/regulator/lp8755.c

192

unsigned int regval;

drivers/regulator/lp8755.c

197

ret = regmap_read(pchip->regmap, 0x3D, &regval);

drivers/regulator/lp8755.c

200

pchip->mphase = regval & 0x0F;

drivers/regulator/lp8755.c

333

unsigned int regval;

drivers/regulator/lp8755.c

340

ret = regmap_read(pchip->regmap, 0x0F, &regval);

drivers/regulator/lp8755.c

346

pchip->irqmask = regval;

drivers/regulator/lp8755.c

54

unsigned int regval;

drivers/regulator/lp8755.c

57

ret = regmap_read(rdev->regmap, 0x12 + id, &regval);

drivers/regulator/lp8755.c

62

return (regval & 0xff) * 100;

drivers/regulator/max77857-regulator.c

101

ret = regmap_read(rdev->regmap, MAX77857_REG_CONT3, &regval);

drivers/regulator/max77857-regulator.c

105

if (FIELD_GET(MAX77857_CONT3_FPWM, regval))

drivers/regulator/max77857-regulator.c

111

ret = regmap_read(rdev->regmap, MAX77859_REG_CONT2, &regval);

drivers/regulator/max77857-regulator.c

115

if (FIELD_GET(MAX77859_CONT2_FPWM, regval))

drivers/regulator/max77857-regulator.c

95

unsigned int regval;

drivers/regulator/mt6315-regulator.c

101

if (regval & info->lp_mode_mask)

drivers/regulator/mt6315-regulator.c

167

u32 regval;

drivers/regulator/mt6315-regulator.c

170

ret = regmap_read(rdev->regmap, info->status_reg, &regval);

drivers/regulator/mt6315-regulator.c

176

return (regval & BIT(0)) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;

drivers/regulator/mt6315-regulator.c

81

int ret, regval;

drivers/regulator/mt6315-regulator.c

86

ret = regmap_read(rdev->regmap, MT6315_BUCK_TOP_4PHASE_ANA_CON42, &regval);

drivers/regulator/mt6315-regulator.c

92

if ((regval & modeset_mask) == modeset_mask)

drivers/regulator/mt6315-regulator.c

95

ret = regmap_read(rdev->regmap, MT6315_BUCK_TOP_CON1, &regval);

drivers/regulator/mt6323-regulator.c

160

u32 regval;

drivers/regulator/mt6323-regulator.c

163

ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);

drivers/regulator/mt6323-regulator.c

169

return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;

drivers/regulator/mt6323-regulator.c

347

u32 regval;

drivers/regulator/mt6323-regulator.c

353

&regval) < 0) {

drivers/regulator/mt6323-regulator.c

359

if (regval & mt6323_regulators[i].vselctrl_mask) {

drivers/regulator/mt6331-regulator.c

209

u32 regval;

drivers/regulator/mt6331-regulator.c

212

ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);

drivers/regulator/mt6331-regulator.c

218

return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;

drivers/regulator/mt6331-regulator.c

419

u32 regval;

drivers/regulator/mt6331-regulator.c

425

&regval) < 0) {

drivers/regulator/mt6331-regulator.c

431

if (regval & mt6331_regulators[i].vselctrl_mask) {

drivers/regulator/mt6332-regulator.c

185

u32 reg, en_mask, regval;

drivers/regulator/mt6332-regulator.c

196

ret = regmap_read(rdev->regmap, reg, &regval);

drivers/regulator/mt6332-regulator.c

202

return (regval & en_mask) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;

drivers/regulator/mt6332-regulator.c

334

u32 regval;

drivers/regulator/mt6332-regulator.c

340

&regval) < 0) {

drivers/regulator/mt6332-regulator.c

346

if (regval & mt6332_regulators[i].vselctrl_mask) {

drivers/regulator/mt6357-regulator.c

130

int ret, regval;

drivers/regulator/mt6357-regulator.c

133

ret = regmap_read(rdev->regmap, info->da_vsel_reg, &regval);

drivers/regulator/mt6357-regulator.c

141

regval &= info->da_vsel_mask;

drivers/regulator/mt6357-regulator.c

142

regval >>= ffs(info->da_vsel_mask) - 1;

drivers/regulator/mt6357-regulator.c

144

return regval;

drivers/regulator/mt6358-regulator.c

374

int ret, regval;

drivers/regulator/mt6358-regulator.c

376

ret = regmap_read(rdev->regmap, info->da_vsel_reg, &regval);

drivers/regulator/mt6358-regulator.c

384

ret = (regval & info->da_vsel_mask) >> (ffs(info->da_vsel_mask) - 1);

drivers/regulator/mt6358-regulator.c

393

u32 regval;

drivers/regulator/mt6358-regulator.c

395

ret = regmap_read(rdev->regmap, info->status_reg, &regval);

drivers/regulator/mt6358-regulator.c

401

return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;

drivers/regulator/mt6358-regulator.c

433

int ret, regval;

drivers/regulator/mt6358-regulator.c

435

ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);

drivers/regulator/mt6358-regulator.c

442

switch ((regval & info->modeset_mask) >> (ffs(info->modeset_mask) - 1)) {

drivers/regulator/mt6359-regulator.c

274

u32 regval;

drivers/regulator/mt6359-regulator.c

277

ret = regmap_read(rdev->regmap, info->status_reg, &regval);

drivers/regulator/mt6359-regulator.c

283

if (regval & info->qi)

drivers/regulator/mt6359-regulator.c

292

int ret, regval;

drivers/regulator/mt6359-regulator.c

294

ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);

drivers/regulator/mt6359-regulator.c

301

regval &= info->modeset_mask;

drivers/regulator/mt6359-regulator.c

302

regval >>= ffs(info->modeset_mask) - 1;

drivers/regulator/mt6359-regulator.c

304

if (regval == MT6359_BUCK_MODE_FORCE_PWM)

drivers/regulator/mt6359-regulator.c

307

ret = regmap_read(rdev->regmap, info->lp_mode_reg, &regval);

drivers/regulator/mt6359-regulator.c

314

if (regval & info->lp_mode_mask)

drivers/regulator/mt6397-regulator.c

196

int ret, regval;

drivers/regulator/mt6397-regulator.c

198

ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);

drivers/regulator/mt6397-regulator.c

205

regval &= info->modeset_mask;

drivers/regulator/mt6397-regulator.c

206

regval >>= ffs(info->modeset_mask) - 1;

drivers/regulator/mt6397-regulator.c

208

switch (regval) {

drivers/regulator/mt6397-regulator.c

221

u32 regval;

drivers/regulator/mt6397-regulator.c

224

ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);

drivers/regulator/mt6397-regulator.c

230

return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;

drivers/regulator/mt6397-regulator.c

327

u32 regval;

drivers/regulator/mt6397-regulator.c

333

&regval) < 0) {

drivers/regulator/mt6397-regulator.c

339

if (regval & mt6397_regulators[i].vselctrl_mask) {

drivers/regulator/pca9450-regulator.c

340

int ret = 0, regval;

drivers/regulator/pca9450-regulator.c

342

ret = regmap_read(rdev->regmap, dvs->mode_reg, &regval);

drivers/regulator/pca9450-regulator.c

349

if ((regval & dvs->mode_mask) == dvs->mode_mask)

drivers/regulator/rk808-regulator.c

349

int regval, ramp_value, ret;

drivers/regulator/rk808-regulator.c

359

regval = ramp_value << (ffs(rdev->desc->ramp_mask) - 1);

drivers/regulator/rk808-regulator.c

362

rdev->desc->ramp_mask, regval);

drivers/regulator/rk808-regulator.c

373

regval = (ramp_value >> 2) & 0x1 ? rk806_dcdc_rate2[rid].bit : 0;

drivers/regulator/rk808-regulator.c

376

regval);

drivers/regulator/rt5759-regulator.c

80

unsigned int regval;

drivers/regulator/rt5759-regulator.c

83

ret = regmap_read(regmap, RT5759_REG_DCDCCTRL, &regval);

drivers/regulator/rt5759-regulator.c

87

if (regval & RT5759_FPWM_MASK)

drivers/resctrl/mpam_resctrl.c

343

u64 regval = mpam_get_regval(tsk);

drivers/resctrl/mpam_resctrl.c

344

u32 tsk_closid = FIELD_GET(MPAM0_EL1_PARTID_D, regval);

drivers/resctrl/mpam_resctrl.c

355

u64 regval = mpam_get_regval(tsk);

drivers/resctrl/mpam_resctrl.c

356

u32 tsk_closid = FIELD_GET(MPAM0_EL1_PARTID_D, regval);

drivers/resctrl/mpam_resctrl.c

357

u32 tsk_rmid = FIELD_GET(MPAM0_EL1_PMG_D, regval);

drivers/reset/reset-tn48m.c

69

unsigned int regval;

drivers/reset/reset-tn48m.c

72

ret = regmap_read(data->regmap, TN48M_RESET_REG, &regval);

drivers/reset/reset-tn48m.c

76

if (BIT(tn48m_resets[id].bit) & regval)

drivers/rtc/rtc-rx8111.c

167

unsigned int regval;

drivers/rtc/rtc-rx8111.c

171

ret = regmap_read(data->regmap, RX8111_REG_FLAG, &regval);

drivers/rtc/rtc-rx8111.c

177

if (FIELD_GET(RX8111_FLAG_XST_BIT, regval)) {

drivers/rtc/rtc-rx8111.c

183

if (FIELD_GET(RX8111_FLAG_VLF_BIT, regval)) {

drivers/rtc/rtc-rx8111.c

189

ret = regmap_field_read(data->regfields[RX8111_REGF_STOP], &regval);

drivers/rtc/rtc-rx8111.c

195

if (regval) {

drivers/rtc/rtc-rx8111.c

272

unsigned int regval;

drivers/rtc/rtc-rx8111.c

278

ret = rx8111_read_vl_flag(data, &regval);

drivers/rtc/rtc-rx8111.c

282

vlval = regval ? RTC_VL_DATA_INVALID : 0;

drivers/rtc/rtc-rx8111.c

285

&regval);

drivers/rtc/rtc-rx8111.c

289

vlval |= regval ? RTC_VL_BACKUP_LOW : 0;

drivers/sbus/char/display7seg.c

89

u8 regval = 0;

drivers/sbus/char/display7seg.c

91

regval = readb(p->regs);

drivers/sbus/char/display7seg.c

93

regval |= D7S_FLIP;

drivers/sbus/char/display7seg.c

95

regval &= ~D7S_FLIP;

drivers/sbus/char/display7seg.c

96

writeb(regval, p->regs);

drivers/scsi/pm8001/pm80xx_hwi.c

1652

u32 regval;

drivers/scsi/pm8001/pm80xx_hwi.c

1675

regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);

drivers/scsi/pm8001/pm80xx_hwi.c

1677

regval);

drivers/scsi/pm8001/pm80xx_hwi.c

1682

regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);

drivers/scsi/pm8001/pm80xx_hwi.c

1684

regval);

drivers/scsi/pm8001/pm80xx_hwi.c

1686

if ((regval & SPCv_SOFT_RESET_READ_MASK) ==

drivers/scsi/pm8001/pm80xx_hwi.c

1690

regval);

drivers/scsi/pm8001/pm80xx_hwi.c

1694

regval);

drivers/scsi/pm8001/pm80xx_hwi.c

4073

u32 regval;

drivers/scsi/pm8001/pm80xx_hwi.c

4089

regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);

drivers/scsi/pm8001/pm80xx_hwi.c

4090

if ((regval & mipsall_ready) != mipsall_ready) {

drivers/scsi/pm8001/pm80xx_hwi.c

4094

regval);

drivers/scsi/pm8001/pm80xx_hwi.c

4101

regval = pm8001_cr32(pm8001_ha, 0,

drivers/scsi/pm8001/pm80xx_hwi.c

4103

switch (regval) {

drivers/soc/qcom/ice.c

123

u32 regval = qcom_ice_readl(ice, QCOM_ICE_REG_VERSION);

drivers/soc/qcom/ice.c

125

int major = FIELD_GET(GENMASK(31, 24), regval);

drivers/soc/qcom/ice.c

126

int minor = FIELD_GET(GENMASK(23, 16), regval);

drivers/soc/qcom/ice.c

127

int step = FIELD_GET(GENMASK(15, 0), regval);

drivers/soc/qcom/ice.c

155

regval = qcom_ice_readl(ice, QCOM_ICE_REG_FUSE_SETTING);

drivers/soc/qcom/ice.c

156

if (regval & (QCOM_ICE_FUSE_SETTING_MASK |

drivers/soc/qcom/ice.c

196

u32 regval;

drivers/soc/qcom/ice.c

198

regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL);

drivers/soc/qcom/ice.c

201

regval |= 0x7000;

drivers/soc/qcom/ice.c

202

qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL);

drivers/soc/qcom/ice.c

207

u32 regval;

drivers/soc/qcom/ice.c

210

regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL);

drivers/soc/qcom/ice.c

211

regval |= 0xd807100;

drivers/soc/qcom/ice.c

214

qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL);

drivers/soc/qcom/ice.c

232

u32 regval;

drivers/soc/qcom/ice.c

236

regval, !(regval & QCOM_ICE_BIST_STATUS_MASK),

drivers/soc/qcom/ice.c

261

u32 regval;

drivers/soc/qcom/ice.c

275

regval = qcom_ice_readl(ice, QCOM_ICE_REG_CONTROL);

drivers/soc/qcom/ice.c

276

regval &= ~QCOM_ICE_LEGACY_MODE_ENABLED;

drivers/soc/qcom/ice.c

277

qcom_ice_writel(ice, regval, QCOM_ICE_REG_CONTROL);

drivers/soc/qcom/ice.c

279

regval = qcom_ice_readl(ice, QCOM_ICE_REG_HWKM_TZ_KM_CTL);

drivers/soc/qcom/ice.c

280

regval &= ~QCOM_ICE_HWKM_ICE_LEGACY_MODE_ENABLED;

drivers/soc/qcom/ice.c

281

qcom_ice_writel(ice, regval, QCOM_ICE_REG_HWKM_TZ_KM_CTL);

drivers/soc/qcom/ice.c

383

qcom_ice_writel(ice, le32_to_cpu(cfg.regval),

drivers/soc/qcom/ice.c

61

__le32 regval;

drivers/spi/spi-fsl-espi.c

588

u32 regval;

drivers/spi/spi-fsl-espi.c

590

regval = fsl_espi_read_reg(espi, ESPI_SPMODE);

drivers/spi/spi-fsl-espi.c

591

regval &= ~SPMODE_ENABLE;

drivers/spi/spi-fsl-espi.c

592

fsl_espi_write_reg(espi, ESPI_SPMODE, regval);

drivers/spi/spi-fsl-espi.c

601

u32 regval;

drivers/spi/spi-fsl-espi.c

603

regval = fsl_espi_read_reg(espi, ESPI_SPMODE);

drivers/spi/spi-fsl-espi.c

604

regval |= SPMODE_ENABLE;

drivers/spi/spi-fsl-espi.c

605

fsl_espi_write_reg(espi, ESPI_SPMODE, regval);

drivers/spi/spi-fsl-spi.c

535

u32 regval;

drivers/spi/spi-fsl-spi.c

607

regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;

drivers/spi/spi-fsl-spi.c

609

regval &= ~SPMODE_LEN(0xF);

drivers/spi/spi-fsl-spi.c

610

regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);

drivers/spi/spi-fsl-spi.c

613

regval |= SPMODE_OP;

drivers/spi/spi-fsl-spi.c

615

mpc8xxx_spi_write_reg(&reg_base->mode, regval);

drivers/spi/spi-pci1xxxx.c

212

u32 regval;

drivers/spi/spi-pci1xxxx.c

214

return readx_poll_timeout(pci1xxxx_set_sys_lock, par, regval,

drivers/spi/spi-pci1xxxx.c

215

(regval & SPI_SYSLOCK), 100,

drivers/spi/spi-pci1xxxx.c

228

u32 regval;

drivers/spi/spi-pci1xxxx.c

244

regval = readl(spi_bus->reg_base + DEV_REV_REG);

drivers/spi/spi-pci1xxxx.c

245

spi_bus->dev_rev = regval & DEV_REV_MASK;

drivers/spi/spi-pci1xxxx.c

247

regval = readl(spi_bus->reg_base +

drivers/spi/spi-pci1xxxx.c

249

pf_num = regval & SPI_PERI_ENBLE_PF_MASK;

drivers/spi/spi-pci1xxxx.c

282

u32 regval;

drivers/spi/spi-pci1xxxx.c

309

regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);

drivers/spi/spi-pci1xxxx.c

311

writel((regval | (data << (iter * 16))), spi_bus->dma_offset_bar +

drivers/spi/spi-pci1xxxx.c

313

regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);

drivers/spi/spi-pci1xxxx.c

317

regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);

drivers/spi/spi-pci1xxxx.c

318

writel(regval | (data << (iter * 16)), spi_bus->dma_offset_bar +

drivers/spi/spi-pci1xxxx.c

320

regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);

drivers/spi/spi-pci1xxxx.c

371

u32 regval;

drivers/spi/spi-pci1xxxx.c

374

regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

376

regval |= SPI_FORCE_CE;

drivers/spi/spi-pci1xxxx.c

377

regval &= ~SPI_MST_CTL_DEVSEL_MASK;

drivers/spi/spi-pci1xxxx.c

378

regval |= (spi_get_chipselect(spi, 0) << 25);

drivers/spi/spi-pci1xxxx.c

380

regval &= ~SPI_FORCE_CE;

drivers/spi/spi-pci1xxxx.c

382

writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

453

u32 regval;

drivers/spi/spi-pci1xxxx.c

455

regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));

drivers/spi/spi-pci1xxxx.c

456

regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |

drivers/spi/spi-pci1xxxx.c

460

regval |= SPI_MST_CTL_MODE_SEL;

drivers/spi/spi-pci1xxxx.c

462

regval |= FIELD_PREP(SPI_MST_CTL_CMD_LEN_MASK, len);

drivers/spi/spi-pci1xxxx.c

463

regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv);

drivers/spi/spi-pci1xxxx.c

464

writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));

drivers/spi/spi-pci1xxxx.c

469

u32 regval;

drivers/spi/spi-pci1xxxx.c

472

regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

473

regval |= SPI_MST_CTL_GO;

drivers/spi/spi-pci1xxxx.c

474

writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

488

u32 regval;

drivers/spi/spi-pci1xxxx.c

497

regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

498

writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

546

u32 regval;

drivers/spi/spi-pci1xxxx.c

553

regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

554

writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

565

regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

566

writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

588

SPI_DMA_GLOBAL_RD_ENGINE_EN, regval,

drivers/spi/spi-pci1xxxx.c

589

(regval == 0x0), 0, USEC_PER_MSEC);

drivers/spi/spi-pci1xxxx.c

609

SPI_DMA_GLOBAL_WR_ENGINE_EN, regval,

drivers/spi/spi-pci1xxxx.c

610

(regval == 0x0), 0, USEC_PER_MSEC);

drivers/spi/spi-pci1xxxx.c

644

u32 regval;

drivers/spi/spi-pci1xxxx.c

647

regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

648

if (regval & SPI_INTR) {

drivers/spi/spi-pci1xxxx.c

657

writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

696

u32 regval;

drivers/spi/spi-pci1xxxx.c

699

regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS);

drivers/spi/spi-pci1xxxx.c

700

if (regval) {

drivers/spi/spi-pci1xxxx.c

701

if (regval & SPI_DMA_DONE_INT_MASK(p->hw_inst)) {

drivers/spi/spi-pci1xxxx.c

707

if (regval & SPI_DMA_ABORT_INT_MASK(p->hw_inst)) {

drivers/spi/spi-pci1xxxx.c

724

u32 regval;

drivers/spi/spi-pci1xxxx.c

727

regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS);

drivers/spi/spi-pci1xxxx.c

728

if (regval) {

drivers/spi/spi-pci1xxxx.c

729

if (regval & SPI_DMA_DONE_INT_MASK(p->hw_inst)) {

drivers/spi/spi-pci1xxxx.c

740

if (regval & SPI_DMA_ABORT_INT_MASK(p->hw_inst)) {

drivers/spi/spi-pci1xxxx.c

756

u32 regval;

drivers/spi/spi-pci1xxxx.c

759

regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

760

if (regval & SPI_INTR) {

drivers/spi/spi-pci1xxxx.c

764

writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));

drivers/spi/spi-pci1xxxx.c

808

u32 regval;

drivers/spi/spi-pci1xxxx.c

864

regval = readl(spi_bus->reg_base +

drivers/spi/spi-pci1xxxx.c

866

regval &= ~SPI_INTR;

drivers/spi/spi-pci1xxxx.c

867

writel(regval, spi_bus->reg_base +

drivers/spi/spi-pci1xxxx.c

887

regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));

drivers/spi/spi-pci1xxxx.c

889

regval |= (BIT(4));

drivers/spi/spi-pci1xxxx.c

891

regval &= ~(BIT(4));

drivers/spi/spi-pci1xxxx.c

893

writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));

drivers/spi/spi-pci1xxxx.c

901

regval = readl(spi_bus->reg_base +

drivers/spi/spi-pci1xxxx.c

903

regval &= ~SPI_INTR;

drivers/spi/spi-pci1xxxx.c

904

writel(regval, spi_bus->reg_base +

drivers/spi/spi-pci1xxxx.c

949

u32 regval;

drivers/spi/spi-pci1xxxx.c

952

regval = readl(spi_ptr->reg_base +

drivers/spi/spi-pci1xxxx.c

954

regval &= SPI_MST_CTL_DEVSEL_MASK;

drivers/spi/spi-pci1xxxx.c

955

spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;

drivers/spi/spi-pci1xxxx.c

956

regval = readl(spi_ptr->reg_base +

drivers/spi/spi-pci1xxxx.c

958

regval &= SPI_MSI_VECTOR_SEL_MASK;

drivers/spi/spi-pci1xxxx.c

959

spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;

drivers/spi/spi-pci1xxxx.c

961

regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));

drivers/spi/spi-pci1xxxx.c

962

regval &= ~SPI_MST_CTL_DEVSEL_MASK;

drivers/spi/spi-pci1xxxx.c

963

regval |= (spi_sub_ptr->prev_val.dev_sel << 25);

drivers/spi/spi-pci1xxxx.c

964

writel(regval,

drivers/spi/spi-pci1xxxx.c

975

u32 regval = SPI_RESUME_CONFIG;

drivers/spi/spi-pci1xxxx.c

981

writel(regval, spi_ptr->reg_base +

drivers/spi/spi-rb4xx.c

47

u32 regval;

drivers/spi/spi-rb4xx.c

49

regval = spi_ioc;

drivers/spi/spi-rb4xx.c

51

regval |= AR71XX_SPI_IOC_DO;

drivers/spi/spi-rb4xx.c

53

rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);

drivers/spi/spi-rb4xx.c

54

rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);

drivers/spi/spi-rb4xx.c

69

u32 regval;

drivers/spi/spi-rb4xx.c

71

regval = spi_ioc;

drivers/spi/spi-rb4xx.c

73

regval |= AR71XX_SPI_IOC_DO;

drivers/spi/spi-rb4xx.c

75

regval |= AR71XX_SPI_IOC_CS(2);

drivers/spi/spi-rb4xx.c

77

rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);

drivers/spi/spi-rb4xx.c

78

rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);

drivers/spmi/spmi-pmic-arb.c

1169

u32 regval, offset;

drivers/spmi/spmi-pmic-arb.c

1177

regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus,

drivers/spmi/spmi-pmic-arb.c

1179

apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);

drivers/spmi/spmi-pmic-arb.c

1182

regval = readl_relaxed(pmic_arb->core + offset);

drivers/spmi/spmi-pmic-arb.c

1183

if (!regval)

drivers/spmi/spmi-pmic-arb.c

1186

id = (regval >> 8) & PMIC_ARB_PPID_MASK;

drivers/spmi/spmi-pmic-arb.c

1248

u32 regval, offset;

drivers/spmi/spmi-pmic-arb.c

1283

regval = readl_relaxed(ppid_base + offset);

drivers/spmi/spmi-pmic-arb.c

1284

if (!regval)

drivers/spmi/spmi-pmic-arb.c

1286

ppid = (regval >> ppid_shift) & ppid_mask;

drivers/spmi/spmi-pmic-arb.c

1287

is_irq_ee = regval & irq_owner_mask;

drivers/spmi/spmi-pmic-arb.c

1289

regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i));

drivers/spmi/spmi-pmic-arb.c

1290

apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);

drivers/staging/iio/frequency/ad9832.c

129

unsigned long regval;

drivers/staging/iio/frequency/ad9832.c

138

regval = ad9832_calc_freqreg(clk_freq, fout);

drivers/staging/iio/frequency/ad9832.c

139

put_unaligned_be32(regval, regval_bytes);

drivers/staging/iio/frequency/ad9834.c

114

unsigned long regval;

drivers/staging/iio/frequency/ad9834.c

121

regval = ad9834_calc_freqreg(clk_freq, fout);

drivers/staging/iio/frequency/ad9834.c

123

st->freq_data[0] = cpu_to_be16(addr | (regval &

drivers/staging/iio/frequency/ad9834.c

125

st->freq_data[1] = cpu_to_be16(addr | ((regval >>

drivers/thermal/ti-soc-thermal/ti-bandgap.c

1112

rval = &bgp->regval[i];

drivers/thermal/ti-soc-thermal/ti-bandgap.c

1144

rval = &bgp->regval[i];

drivers/thermal/ti-soc-thermal/ti-bandgap.c

568

bgp->regval[id].data = data;

drivers/thermal/ti-soc-thermal/ti-bandgap.c

587

return bgp->regval[id].data;

drivers/thermal/ti-soc-thermal/ti-bandgap.c

841

bgp->regval = devm_kcalloc(&pdev->dev, bgp->conf->sensor_count,

drivers/thermal/ti-soc-thermal/ti-bandgap.c

842

sizeof(*bgp->regval), GFP_KERNEL);

drivers/thermal/ti-soc-thermal/ti-bandgap.c

843

if (!bgp->regval)

drivers/thermal/ti-soc-thermal/ti-bandgap.h

203

struct temp_sensor_regval *regval;

drivers/tty/serial/8250/8250_pci1xxxx.c

173

u32 regval;

drivers/tty/serial/8250/8250_pci1xxxx.c

175

return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval,

drivers/tty/serial/8250/8250_pci1xxxx.c

176

(regval & UART_SYSLOCK),

drivers/tty/serial/8250/8250_pci1xxxx.c

743

u32 regval;

drivers/tty/serial/8250/8250_pci1xxxx.c

754

regval = readl(priv->membase + UART_DEV_REV_REG);

drivers/tty/serial/8250/8250_pci1xxxx.c

755

priv->dev_rev = regval & UART_DEV_REV_MASK;

drivers/tty/serial/ip22zilog.c

135

unsigned char regval;

drivers/tty/serial/ip22zilog.c

137

regval = readb(&channel->control);

drivers/tty/serial/ip22zilog.c

139

if (regval & Rx_CH_AV)

drivers/tty/serial/ip22zilog.c

142

regval = read_zsreg(channel, R1);

drivers/tty/serial/ip22zilog.c

146

if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {

drivers/tty/serial/sunzilog.c

153

unsigned char regval;

drivers/tty/serial/sunzilog.c

155

regval = readb(&channel->control);

drivers/tty/serial/sunzilog.c

157

if (regval & Rx_CH_AV)

drivers/tty/serial/sunzilog.c

160

regval = read_zsreg(channel, R1);

drivers/tty/serial/sunzilog.c

164

if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {

drivers/tty/serial/xilinx_uartps.c

749

unsigned int regval;

drivers/tty/serial/xilinx_uartps.c

755

regval = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

756

regval |= CDNS_UART_CR_TX_DIS;

drivers/tty/serial/xilinx_uartps.c

758

writel(regval, port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

767

unsigned int regval;

drivers/tty/serial/xilinx_uartps.c

773

regval = readl(port->membase + CDNS_UART_CR);

drivers/tty/serial/xilinx_uartps.c

774

regval |= CDNS_UART_CR_RX_DIS;

drivers/tty/serial/xilinx_uartps.c

775

writel(regval, port->membase + CDNS_UART_CR);

drivers/usb/gadget/udc/atmel_usba_udc.c

1186

u32 regval;

drivers/usb/gadget/udc/atmel_usba_udc.c

1189

regval = usba_readl(udc, CTRL);

drivers/usb/gadget/udc/atmel_usba_udc.c

1190

regval = USBA_BFINS(DEV_ADDR, addr, regval);

drivers/usb/gadget/udc/atmel_usba_udc.c

1191

usba_writel(udc, CTRL, regval);

drivers/usb/gadget/udc/tegra-xudc.c

597

u32 regval;

drivers/usb/gadget/udc/tegra-xudc.c

599

return readl_poll_timeout_atomic(xudc->base + offset, regval,

drivers/usb/gadget/udc/tegra-xudc.c

600

(regval & mask) == val, 1, 100);

drivers/usb/host/ohci-at91.c

323

u32 regval;

drivers/usb/host/ohci-at91.c

333

ret = regmap_read(regmap, AT91_SFR_OHCIICR, &regval);

drivers/usb/host/ohci-at91.c

338

regval |= AT91_OHCIICR_USB_SUSPEND;

drivers/usb/host/ohci-at91.c

340

regval &= ~AT91_OHCIICR_USB_SUSPEND;

drivers/usb/host/ohci-at91.c

342

regmap_write(regmap, AT91_SFR_OHCIICR, regval);

drivers/usb/host/xhci-histb.c

52

u32 regval;

drivers/usb/host/xhci-histb.c

56

regval = readl(histb->ctrl + REG_GUSB2PHYCFG0);

drivers/usb/host/xhci-histb.c

57

regval &= ~BIT_UTMI_ULPI;

drivers/usb/host/xhci-histb.c

58

regval &= ~(BIT_UTMI_8_16);

drivers/usb/host/xhci-histb.c

59

regval &= ~BIT_FREECLK_EXIST;

drivers/usb/host/xhci-histb.c

60

writel(regval, histb->ctrl + REG_GUSB2PHYCFG0);

drivers/usb/host/xhci-histb.c

71

regval = readl(histb->ctrl + REG_GUSB3PIPECTL0);

drivers/usb/host/xhci-histb.c

72

regval &= ~USB3_DEEMPHASIS_MASK;

drivers/usb/host/xhci-histb.c

73

regval |= USB3_DEEMPHASIS0;

drivers/usb/host/xhci-histb.c

74

regval |= USB3_TX_MARGIN1;

drivers/usb/host/xhci-histb.c

75

writel(regval, histb->ctrl + REG_GUSB3PIPECTL0);

drivers/usb/typec/rt1719.c

122

__le16 regval;

drivers/usb/typec/rt1719.c

125

ret = regmap_raw_read(data->regmap, reg, &regval, sizeof(regval));

drivers/usb/typec/rt1719.c

129

*val = le16_to_cpu(regval);

drivers/usb/typec/rt1719.c

135

__le32 regval;

drivers/usb/typec/rt1719.c

138

ret = regmap_raw_read(data->regmap, reg, &regval, sizeof(regval));

drivers/usb/typec/rt1719.c

142

*val = le32_to_cpu(regval);

drivers/usb/typec/rt1719.c

148

__le32 regval = cpu_to_le32(val);

drivers/usb/typec/rt1719.c

150

return regmap_raw_write(data->regmap, reg, &regval, sizeof(regval));

drivers/video/fbdev/arkfb.c

1024

regval = vga_rseq(par->state.vgabase, 0x10);

drivers/video/fbdev/arkfb.c

1025

info->screen_size = (1 << (regval >> 6)) << 20;

drivers/video/fbdev/arkfb.c

458

u8 regval;

drivers/video/fbdev/arkfb.c

461

regval = vga_rseq(par->state.vgabase, 0x1C);

drivers/video/fbdev/arkfb.c

464

vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));

drivers/video/fbdev/arkfb.c

470

vga_wseq(par->state.vgabase, 0x1C, regval);

drivers/video/fbdev/arkfb.c

477

u8 regval;

drivers/video/fbdev/arkfb.c

480

regval = vga_rseq(par->state.vgabase, 0x1C);

drivers/video/fbdev/arkfb.c

483

vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));

drivers/video/fbdev/arkfb.c

489

vga_wseq(par->state.vgabase, 0x1C, regval);

drivers/video/fbdev/arkfb.c

496

u8 regval;

drivers/video/fbdev/arkfb.c

505

regval = vga_r(par->state.vgabase, VGA_MIS_R);

drivers/video/fbdev/arkfb.c

506

vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);

drivers/video/fbdev/arkfb.c

616

u8 regval;

drivers/video/fbdev/arkfb.c

683

regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;

drivers/video/fbdev/arkfb.c

684

vga_wseq(par->state.vgabase, 0x18, regval);

drivers/video/fbdev/arkfb.c

960

u8 regval;

drivers/video/fbdev/core/svgalib.c

26

u8 regval, bitval, bitnum;

drivers/video/fbdev/core/svgalib.c

29

regval = vga_rcrt(regbase, regset->regnum);

drivers/video/fbdev/core/svgalib.c

33

regval = regval & ~bitval;

drivers/video/fbdev/core/svgalib.c

35

regval = regval | bitval;

drivers/video/fbdev/core/svgalib.c

39

vga_wcrt(regbase, regset->regnum, regval);

drivers/video/fbdev/core/svgalib.c

47

u8 regval, bitval, bitnum;

drivers/video/fbdev/core/svgalib.c

50

regval = vga_rseq(regbase, regset->regnum);

drivers/video/fbdev/core/svgalib.c

510

u8 regval;

drivers/video/fbdev/core/svgalib.c

54

regval = regval & ~bitval;

drivers/video/fbdev/core/svgalib.c

56

regval = regval | bitval;

drivers/video/fbdev/core/svgalib.c

575

regval = vga_r(regbase, VGA_MIS_R);

drivers/video/fbdev/core/svgalib.c

578

regval = regval & ~0x80;

drivers/video/fbdev/core/svgalib.c

581

regval = regval | 0x80;

drivers/video/fbdev/core/svgalib.c

585

regval = regval & ~0x40;

drivers/video/fbdev/core/svgalib.c

588

regval = regval | 0x40;

drivers/video/fbdev/core/svgalib.c

590

vga_w(regbase, VGA_MIS_W, regval);

drivers/video/fbdev/core/svgalib.c

60

vga_wseq(regbase, regset->regnum, regval);

drivers/video/fbdev/s3fb.c

1198

u8 regval, cr38, cr39;

drivers/video/fbdev/s3fb.c

1271

regval = vga_rcrt(par->state.vgabase, 0x36);

drivers/video/fbdev/s3fb.c

1276

switch ((regval & 0xE0) >> 5) {

drivers/video/fbdev/s3fb.c

1290

switch ((regval & 0xC0) >> 6) {

drivers/video/fbdev/s3fb.c

1299

switch ((regval & 0x60) >> 5) {

drivers/video/fbdev/s3fb.c

1314

regval = vga_rcrt(par->state.vgabase, 0x37);

drivers/video/fbdev/s3fb.c

1315

switch ((regval & 0x60) >> 5) {

drivers/video/fbdev/s3fb.c

1324

info->screen_size = s3_memsizes[regval >> 5] << 10;

drivers/video/fbdev/s3fb.c

1328

regval = vga_rseq(par->state.vgabase, 0x10);

drivers/video/fbdev/s3fb.c

1329

par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);

drivers/video/fbdev/s3fb.c

1330

par->mclk_freq = par->mclk_freq >> (regval >> 5);

drivers/video/fbdev/s3fb.c

466

u8 regval;

drivers/video/fbdev/s3fb.c

477

regval = vga_r(par->state.vgabase, VGA_MIS_R);

drivers/video/fbdev/s3fb.c

478

vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);

drivers/video/fbdev/s3fb.c

496

regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */

drivers/video/fbdev/s3fb.c

497

vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));

drivers/video/fbdev/s3fb.c

498

vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));

drivers/video/fbdev/s3fb.c

499

vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));

drivers/video/fbdev/vt8623fb.c

255

u8 regval;

drivers/video/fbdev/vt8623fb.c

265

regval = vga_r(par->state.vgabase, VGA_MIS_R);

drivers/video/fbdev/vt8623fb.c

266

vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);

drivers/watchdog/da9062_wdt.c

67

unsigned int regval)

drivers/watchdog/da9062_wdt.c

81

regval);

drivers/watchdog/da9063_wdt.c

74

unsigned int regval;

drivers/watchdog/da9063_wdt.c

90

regval = da9063_wdt_timeout_to_sel(timeout);

drivers/watchdog/da9063_wdt.c

93

DA9063_TWDSCALE_MASK, regval);

drivers/watchdog/marvell_gti_wdt.c

111

u64 regval;

drivers/watchdog/marvell_gti_wdt.c

127

regval = readq(priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

128

regval |= GTI_CWD_WDOG_MODE_INT_DEL3T_RST;

drivers/watchdog/marvell_gti_wdt.c

129

writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

137

u64 regval;

drivers/watchdog/marvell_gti_wdt.c

144

regval = readq(priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

145

regval &= ~GTI_CWD_WDOG_MODE_MASK;

drivers/watchdog/marvell_gti_wdt.c

146

writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

155

u64 timeout_wdog, regval;

drivers/watchdog/marvell_gti_wdt.c

178

regval = readq(priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/marvell_gti_wdt.c

179

regval &= GTI_CWD_WDOG_MODE_MASK;

drivers/watchdog/marvell_gti_wdt.c

180

regval |= (timeout_wdog << (GTI_CWD_WDOG_CNT_SHIFT + 8)) |

drivers/watchdog/marvell_gti_wdt.c

182

writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx));

drivers/watchdog/max77620_wdt.c

104

regval = MAX77620_TWD_2s;

drivers/watchdog/max77620_wdt.c

109

regval = MAX77620_TWD_16s;

drivers/watchdog/max77620_wdt.c

114

regval = MAX77620_TWD_64s;

drivers/watchdog/max77620_wdt.c

119

regval = MAX77620_TWD_128s;

drivers/watchdog/max77620_wdt.c

135

MAX77620_TWD_MASK, regval);

drivers/watchdog/max77620_wdt.c

162

unsigned int regval;

drivers/watchdog/max77620_wdt.c

206

ret = regmap_read(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2, &regval);

drivers/watchdog/max77620_wdt.c

212

switch (regval & MAX77620_TWD_MASK) {

drivers/watchdog/max77620_wdt.c

227

if (regval & MAX77620_WDTEN)

drivers/watchdog/max77620_wdt.c

99

u8 regval;

drivers/watchdog/mlx_wdt.c

111

u32 regval, set_time, hw_timeout;

drivers/watchdog/mlx_wdt.c

116

rc = regmap_read(wdt->regmap, reg_data->reg, &regval);

drivers/watchdog/mlx_wdt.c

121

regval = (regval & reg_data->mask) | hw_timeout;

drivers/watchdog/mlx_wdt.c

124

rc = regmap_write(wdt->regmap, reg_data->reg, regval);

drivers/watchdog/mlx_wdt.c

134

regval = timeout & 0xff;

drivers/watchdog/mlx_wdt.c

135

rc = regmap_write(wdt->regmap, reg_data->reg, regval);

drivers/watchdog/mlx_wdt.c

137

regval = (timeout & 0xff00) >> 8;

drivers/watchdog/mlx_wdt.c

139

reg_data->reg + 1, regval);

drivers/watchdog/mlx_wdt.c

169

u32 regval, msb, lsb;

drivers/watchdog/mlx_wdt.c

173

rc = regmap_read(wdt->regmap, reg_data->reg, &regval);

drivers/watchdog/mlx_wdt.c

181

regval = (msb & 0xff) << 8 | (lsb & 0xff);

drivers/watchdog/mlx_wdt.c

184

rc = regmap_read(wdt->regmap, reg_data->reg, &regval);

drivers/watchdog/mlx_wdt.c

189

return rc == 0 ? regval : 0;

drivers/watchdog/mlx_wdt.c

59

u32 regval;

drivers/watchdog/mlx_wdt.c

69

rc = regmap_read(wdt->regmap, reg_data->reg, &regval);

drivers/watchdog/mlx_wdt.c

71

if (regval & ~reg_data->mask) {

drivers/watchdog/ts4800_wdt.c

49

const int regval;

drivers/watchdog/ts4800_wdt.c

90

wdt->feed_val = ts4800_wdt_map[i].regval;

drivers/watchdog/ts72xx_wdt.c

46

unsigned char regval;

drivers/watchdog/ts72xx_wdt.c

54

writeb(priv->regval, priv->control_reg);

drivers/watchdog/ts72xx_wdt.c

83

priv->regval = TS72XX_WDT_CTRL_1SEC;

drivers/watchdog/ts72xx_wdt.c

85

priv->regval = TS72XX_WDT_CTRL_2SEC;

drivers/watchdog/ts72xx_wdt.c

87

priv->regval = TS72XX_WDT_CTRL_4SEC;

drivers/watchdog/ts72xx_wdt.c

90

priv->regval = TS72XX_WDT_CTRL_8SEC;

include/linux/fsl/bestcomm/bestcomm_priv.h

254

u16 regval;

include/linux/fsl/bestcomm/bestcomm_priv.h

256

regval = in_be16(&bcom_eng->regs->PtdCntrl);

include/linux/fsl/bestcomm/bestcomm_priv.h

257

out_be16(&bcom_eng->regs->PtdCntrl, regval | 1);

sound/isa/opti9xx/miro.c

1374

unsigned char regval;

sound/isa/opti9xx/miro.c

1385

regval=inb(miro->mc_base + 4);

sound/isa/opti9xx/miro.c

1386

aci->aci_port = (regval & 0x10) ? 0x344 : 0x354;

sound/sh/aica.c

128

u32 regval;

sound/sh/aica.c

130

regval = readl(ARM_RESET_REGISTER);

sound/sh/aica.c

131

regval |= 1;

sound/sh/aica.c

134

writel(regval, ARM_RESET_REGISTER);

sound/sh/aica.c

138

regval = readl(SPU_REGISTER_BASE + (i * 0x80));

sound/sh/aica.c

139

regval = (regval & ~0x4000) | 0x8000;

sound/sh/aica.c

142

writel(regval, SPU_REGISTER_BASE + (i * 0x80));

sound/sh/aica.c

151

u32 regval = readl(ARM_RESET_REGISTER);

sound/sh/aica.c

152

regval &= ~1;

sound/sh/aica.c

155

writel(regval, ARM_RESET_REGISTER);

sound/soc/apple/mca.c

597

u32 regval, pad;

sound/soc/apple/mca.c

663

regval = FIELD_PREP(DMA_ADAPTER_NCHANS, nchans_ceiled) |

sound/soc/apple/mca.c

670

writel_relaxed(regval, mca->switch_base + REG_DMA_ADAPTER_A(cl->no));

sound/soc/apple/mca.c

673

writel_relaxed(regval,

sound/soc/apple/mca.c

676

writel_relaxed(regval,

sound/soc/bcm/cygnus-pcm.c

395

u32 regval;

sound/soc/bcm/cygnus-pcm.c

409

regval = readl(aio->cygaud->audio + p_rbuf->rdaddr);

sound/soc/bcm/cygnus-pcm.c

410

regval = regval ^ BIT(31);

sound/soc/bcm/cygnus-pcm.c

411

writel(regval, aio->cygaud->audio + p_rbuf->wraddr);

sound/soc/bcm/cygnus-pcm.c

414

regval = readl(aio->cygaud->audio + p_rbuf->wraddr);

sound/soc/bcm/cygnus-pcm.c

415

writel(regval, aio->cygaud->audio + p_rbuf->rdaddr);

sound/soc/codecs/adau7118.c

152

u32 regval;

sound/soc/codecs/adau7118.c

189

regval = ADAU7118_LRCLK_BCLK_POL(0);

sound/soc/codecs/adau7118.c

192

regval = ADAU7118_LRCLK_BCLK_POL(2);

sound/soc/codecs/adau7118.c

195

regval = ADAU7118_LRCLK_BCLK_POL(1);

sound/soc/codecs/adau7118.c

198

regval = ADAU7118_LRCLK_BCLK_POL(3);

sound/soc/codecs/adau7118.c

209

regval);

sound/soc/codecs/adau7118.c

241

u32 regval;

sound/soc/codecs/adau7118.c

247

regval = ADAU7118_SLOT_WIDTH(0);

sound/soc/codecs/adau7118.c

250

regval = ADAU7118_SLOT_WIDTH(2);

sound/soc/codecs/adau7118.c

253

regval = ADAU7118_SLOT_WIDTH(1);

sound/soc/codecs/adau7118.c

262

ADAU7118_SLOT_WIDTH_MASK, regval);

sound/soc/codecs/adau7118.c

280

u32 regval;

sound/soc/codecs/adau7118.c

306

regval = ADAU7118_DATA_FMT(2);

sound/soc/codecs/adau7118.c

310

regval = ADAU7118_DATA_FMT(3);

sound/soc/codecs/adau7118.c

314

regval = ADAU7118_DATA_FMT(4);

sound/soc/codecs/adau7118.c

326

regval);

sound/soc/codecs/adau7118.c

483

u32 clk_map[4], regval;

sound/soc/codecs/adau7118.c

493

regval = ADAU7118_DEC_RATIO(0);

sound/soc/codecs/adau7118.c

496

regval = ADAU7118_DEC_RATIO(1);

sound/soc/codecs/adau7118.c

499

regval = ADAU7118_DEC_RATIO(2);

sound/soc/codecs/adau7118.c

508

ADAU7118_DEC_RATIO_MASK, regval);

sound/soc/codecs/cpcap.c

472

int regval, mask;

sound/soc/codecs/cpcap.c

475

err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);

sound/soc/codecs/cpcap.c

485

switch (regval & mask) {

sound/soc/codecs/cpcap.c

514

int regval = 0, mask;

sound/soc/codecs/cpcap.c

525

regval = BIT(CPCAP_BIT_MIC1_MUX);

sound/soc/codecs/cpcap.c

528

regval = BIT(CPCAP_BIT_HS_MIC_MUX);

sound/soc/codecs/cpcap.c

531

regval = BIT(CPCAP_BIT_EMU_MIC_MUX);

sound/soc/codecs/cpcap.c

534

regval = BIT(CPCAP_BIT_RX_R_ENCODE);

sound/soc/codecs/cpcap.c

541

mask, regval);

sound/soc/codecs/cpcap.c

555

int regval, mask;

sound/soc/codecs/cpcap.c

558

err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);

sound/soc/codecs/cpcap.c

566

switch (regval & mask) {

sound/soc/codecs/cpcap.c

589

int regval = 0, mask;

sound/soc/codecs/cpcap.c

598

regval = BIT(CPCAP_BIT_MIC2_MUX);

sound/soc/codecs/cpcap.c

601

regval = BIT(CPCAP_BIT_RX_L_ENCODE);

sound/soc/codecs/cpcap.c

608

mask, regval);

sound/soc/codecs/cs42l42.c

1030

unsigned int regval;

sound/soc/codecs/cs42l42.c

1079

regval = pll_ratio_table[cs42l42->pll_config].pll_divout;

sound/soc/codecs/cs42l42.c

1082

regval <<

sound/soc/codecs/cs42l42.c

1088

regval,

sound/soc/codecs/cs42l42.c

1089

(regval & 1),

sound/soc/codecs/cs42l84.c

581

unsigned int regval;

sound/soc/codecs/cs42l84.c

628

regval,

sound/soc/codecs/cs42l84.c

629

(regval & CS42L84_PLL_LOCK_STATUS_LOCKED),

sound/soc/codecs/cs42l84.c

635

if (regval & CS42L84_PLL_LOCK_STATUS_ERROR)

sound/soc/codecs/inno_rk3036.c

51

int val, regval;

sound/soc/codecs/inno_rk3036.c

53

regval = snd_soc_component_read(component, INNO_R09);

sound/soc/codecs/inno_rk3036.c

54

val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) &

sound/soc/codecs/inno_rk3036.c

58

val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) &

sound/soc/codecs/max98088.c

1022

u8 regval;

sound/soc/codecs/max98088.c

1043

if (rate_value(rate, &regval))

sound/soc/codecs/max98088.c

1047

M98088_CLKMODE_MASK, regval);

sound/soc/codecs/max98088.c

1612

u8 regval = 0;

sound/soc/codecs/max98088.c

1621

regval |= M98088_DIGMIC_L;

sound/soc/codecs/max98088.c

1624

regval |= M98088_DIGMIC_R;

sound/soc/codecs/max98088.c

1626

max98088->digmic = (regval ? 1 : 0);

sound/soc/codecs/max98088.c

1628

snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);

sound/soc/codecs/max98088.c

1631

regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);

sound/soc/codecs/max98088.c

1633

M98088_REC_LINEMODE_MASK, regval);

sound/soc/codecs/max98088.c

952

u8 regval;

sound/soc/codecs/max98088.c

973

if (rate_value(rate, &regval))

sound/soc/codecs/max98088.c

977

M98088_CLKMODE_MASK, regval);

sound/soc/codecs/max98090.c

1621

u8 regval, tdm_regval;

sound/soc/codecs/max98090.c

1629

regval = 0;

sound/soc/codecs/max98090.c

1646

regval |= M98090_MAS_MASK |

sound/soc/codecs/max98090.c

1650

regval |= M98090_MAS_MASK |

sound/soc/codecs/max98090.c

1654

regval |= M98090_MAS_MASK |

sound/soc/codecs/max98090.c

1663

snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);

sound/soc/codecs/max98090.c

1665

regval = 0;

sound/soc/codecs/max98090.c

1668

regval |= M98090_DLY_MASK;

sound/soc/codecs/max98090.c

1673

regval |= M98090_RJ_MASK;

sound/soc/codecs/max98090.c

1687

regval |= M98090_WCI_MASK;

sound/soc/codecs/max98090.c

1690

regval |= M98090_BCI_MASK;

sound/soc/codecs/max98090.c

1693

regval |= M98090_BCI_MASK|M98090_WCI_MASK;

sound/soc/codecs/max98090.c

1707

regval ^= M98090_BCI_MASK;

sound/soc/codecs/max98090.c

1710

M98090_REG_INTERFACE_FORMAT, regval);

sound/soc/codecs/max98090.c

1712

regval = 0;

sound/soc/codecs/max98090.c

1714

regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT |

sound/soc/codecs/max98090.c

1718

snd_soc_component_write(component, M98090_REG_TDM_FORMAT, regval);

sound/soc/codecs/max98090.c

2066

int regval;

sound/soc/codecs/max98090.c

2068

regval = mute ? M98090_DVM_MASK : 0;

sound/soc/codecs/max98090.c

2070

M98090_DVM_MASK, regval);

sound/soc/codecs/max98095.c

1008

u8 regval;

sound/soc/codecs/max98095.c

1027

if (rate_value(rate, &regval))

sound/soc/codecs/max98095.c

1031

M98095_CLKMODE_MASK, regval);

sound/soc/codecs/max98095.c

1069

u8 regval;

sound/soc/codecs/max98095.c

1088

if (rate_value(rate, &regval))

sound/soc/codecs/max98095.c

1092

M98095_CLKMODE_MASK, regval);

sound/soc/codecs/max98095.c

1164

u8 regval = 0;

sound/soc/codecs/max98095.c

1181

regval |= M98095_DAI_MAS;

sound/soc/codecs/max98095.c

1190

regval |= M98095_DAI_DLY;

sound/soc/codecs/max98095.c

1202

regval |= M98095_DAI_WCI;

sound/soc/codecs/max98095.c

1205

regval |= M98095_DAI_BCI;

sound/soc/codecs/max98095.c

1208

regval |= M98095_DAI_BCI|M98095_DAI_WCI;

sound/soc/codecs/max98095.c

1216

M98095_DAI_WCI, regval);

sound/soc/codecs/max98095.c

1230

u8 regval = 0;

sound/soc/codecs/max98095.c

1247

regval |= M98095_DAI_MAS;

sound/soc/codecs/max98095.c

1256

regval |= M98095_DAI_DLY;

sound/soc/codecs/max98095.c

1268

regval |= M98095_DAI_WCI;

sound/soc/codecs/max98095.c

1271

regval |= M98095_DAI_BCI;

sound/soc/codecs/max98095.c

1274

regval |= M98095_DAI_BCI|M98095_DAI_WCI;

sound/soc/codecs/max98095.c

1282

M98095_DAI_WCI, regval);

sound/soc/codecs/max98095.c

1297

u8 regval = 0;

sound/soc/codecs/max98095.c

1314

regval |= M98095_DAI_MAS;

sound/soc/codecs/max98095.c

1323

regval |= M98095_DAI_DLY;

sound/soc/codecs/max98095.c

1335

regval |= M98095_DAI_WCI;

sound/soc/codecs/max98095.c

1338

regval |= M98095_DAI_BCI;

sound/soc/codecs/max98095.c

1341

regval |= M98095_DAI_BCI|M98095_DAI_WCI;

sound/soc/codecs/max98095.c

1349

M98095_DAI_WCI, regval);

sound/soc/codecs/max98095.c

1780

u8 regval = 0;

sound/soc/codecs/max98095.c

1789

regval |= M98095_DIGMIC_L;

sound/soc/codecs/max98095.c

1792

regval |= M98095_DIGMIC_R;

sound/soc/codecs/max98095.c

1794

snd_soc_component_write(component, M98095_087_CFG_MIC, regval);

sound/soc/codecs/max98095.c

947

u8 regval;

sound/soc/codecs/max98095.c

966

if (rate_value(rate, &regval))

sound/soc/codecs/max98095.c

970

M98095_CLKMODE_MASK, regval);

sound/soc/codecs/tlv320adc3xxx.c

1030

unsigned int regval;

sound/soc/codecs/tlv320adc3xxx.c

1038

ret = regmap_read(adc3xxx->regmap, ADC3XXX_MICBIAS_CTRL, &regval);

sound/soc/codecs/tlv320adc3xxx.c

1041

return ((regval >> adc3xxx_micbias_shift[micbias]) & ADC3XXX_MICBIAS_MASK) !=

sound/soc/codecs/tlv320adc3xxx.c

1044

ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], &regval);

sound/soc/codecs/tlv320adc3xxx.c

1047

return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK);

sound/soc/fsl/fsl_easrc.c

103

ret = regmap_read(easrc->regmap, REG_EASRC_CS1(mc->regbase), &regval[1]);

sound/soc/fsl/fsl_easrc.c

107

ret = regmap_read(easrc->regmap, REG_EASRC_CS2(mc->regbase), &regval[2]);

sound/soc/fsl/fsl_easrc.c

111

ret = regmap_read(easrc->regmap, REG_EASRC_CS3(mc->regbase), &regval[3]);

sound/soc/fsl/fsl_easrc.c

115

ret = regmap_read(easrc->regmap, REG_EASRC_CS4(mc->regbase), &regval[4]);

sound/soc/fsl/fsl_easrc.c

119

ret = regmap_read(easrc->regmap, REG_EASRC_CS5(mc->regbase), &regval[5]);

sound/soc/fsl/fsl_easrc.c

133

unsigned int *regval = (unsigned int *)ucontrol->value.iec958.status;

sound/soc/fsl/fsl_easrc.c

142

GENMASK(31, 0), regval[0], &changed);

sound/soc/fsl/fsl_easrc.c

148

GENMASK(31, 0), regval[1], &changed);

sound/soc/fsl/fsl_easrc.c

154

GENMASK(31, 0), regval[2], &changed);

sound/soc/fsl/fsl_easrc.c

160

GENMASK(31, 0), regval[3], &changed);

sound/soc/fsl/fsl_easrc.c

166

GENMASK(31, 0), regval[4], &changed);

sound/soc/fsl/fsl_easrc.c

172

GENMASK(31, 0), regval[5], &changed);

sound/soc/fsl/fsl_easrc.c

54

unsigned int regval = ucontrol->value.integer.value[0];

sound/soc/fsl/fsl_easrc.c

57

if (regval < EASRC_WIDTH_16_BIT || regval > EASRC_WIDTH_24_BIT)

sound/soc/fsl/fsl_easrc.c

60

ret = (easrc_priv->bps_iec958[mc->regbase] != regval);

sound/soc/fsl/fsl_easrc.c

62

easrc_priv->bps_iec958[mc->regbase] = regval;

sound/soc/fsl/fsl_easrc.c

96

unsigned int *regval = (unsigned int *)ucontrol->value.iec958.status;

sound/soc/fsl/fsl_easrc.c

99

ret = regmap_read(easrc->regmap, REG_EASRC_CS0(mc->regbase), &regval[0]);

sound/soc/qcom/lpass-cdc-dma.c

220

unsigned int regval;

sound/soc/qcom/lpass-cdc-dma.c

227

regval = LPASS_CDC_DMA_INTF_ONE_CHANNEL;

sound/soc/qcom/lpass-cdc-dma.c

230

regval = LPASS_CDC_DMA_INTF_TWO_CHANNEL;

sound/soc/qcom/lpass-cdc-dma.c

233

regval = LPASS_CDC_DMA_INTF_FOUR_CHANNEL;

sound/soc/qcom/lpass-cdc-dma.c

236

regval = LPASS_CDC_DMA_INTF_SIX_CHANNEL;

sound/soc/qcom/lpass-cdc-dma.c

239

regval = LPASS_CDC_DMA_INTF_EIGHT_CHANNEL;

sound/soc/qcom/lpass-cdc-dma.c

250

ret = regmap_fields_write(dmactl->codec_channel, id, regval);

sound/soc/qcom/lpass-cpu.c

144

unsigned int regval;

sound/soc/qcom/lpass-cpu.c

169

regval = LPAIF_I2SCTL_BITWIDTH_16;

sound/soc/qcom/lpass-cpu.c

172

regval = LPAIF_I2SCTL_BITWIDTH_24;

sound/soc/qcom/lpass-cpu.c

175

regval = LPAIF_I2SCTL_BITWIDTH_32;

sound/soc/qcom/lpass-cpu.c

182

ret = regmap_fields_write(i2sctl->bitwidth, id, regval);

sound/soc/qcom/lpass-platform.c

427

unsigned int regval;

sound/soc/qcom/lpass-platform.c

504

regval = LPAIF_DMACTL_WPSCNT_ONE;

sound/soc/qcom/lpass-platform.c

507

regval = LPAIF_DMACTL_WPSCNT_TWO;

sound/soc/qcom/lpass-platform.c

510

regval = LPAIF_DMACTL_WPSCNT_THREE;

sound/soc/qcom/lpass-platform.c

513

regval = LPAIF_DMACTL_WPSCNT_FOUR;

sound/soc/qcom/lpass-platform.c

525

regval = LPAIF_DMACTL_WPSCNT_ONE;

sound/soc/qcom/lpass-platform.c

528

regval = (dai_id == LPASS_DP_RX ?

sound/soc/qcom/lpass-platform.c

533

regval = (dai_id == LPASS_DP_RX ?

sound/soc/qcom/lpass-platform.c

538

regval = (dai_id == LPASS_DP_RX ?

sound/soc/qcom/lpass-platform.c

543

regval = (dai_id == LPASS_DP_RX ?

sound/soc/qcom/lpass-platform.c

559

ret = regmap_fields_write(dmactl->wpscnt, id, regval);

sound/soc/soc-ops.c

690

unsigned int regval = snd_soc_component_read(component, regbase + i);

sound/soc/soc-ops.c

692

val |= (regval & regwmask) << (regwshift * (regcount - i - 1));

sound/soc/soc-ops.c

741

unsigned int regval = (val >> (regwshift * (regcount - i - 1))) &

sound/soc/soc-ops.c

746

regmask, regval);

sound/x86/intel_hdmi_audio.c

252

intelhaddata->aud_config.regval);

sound/x86/intel_hdmi_audio.c

283

union aud_ch_status_0 ch_stat0 = {.regval = 0};

sound/x86/intel_hdmi_audio.c

284

union aud_ch_status_1 ch_stat1 = {.regval = 0};

sound/x86/intel_hdmi_audio.c

321

AUD_CH_STATUS_0, ch_stat0.regval);

sound/x86/intel_hdmi_audio.c

338

AUD_CH_STATUS_1, ch_stat1.regval);

sound/x86/intel_hdmi_audio.c

350

union aud_cfg cfg_val = {.regval = 0};

sound/x86/intel_hdmi_audio.c

351

union aud_buf_config buf_cfg = {.regval = 0};

sound/x86/intel_hdmi_audio.c

359

had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);

sound/x86/intel_hdmi_audio.c

382

had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);

sound/x86/intel_hdmi_audio.c

589

union aud_ctrl_st ctrl_state = {.regval = 0};

sound/x86/intel_hdmi_audio.c

590

union aud_info_frame2 frame2 = {.regval = 0};

sound/x86/intel_hdmi_audio.c

591

union aud_info_frame3 frame3 = {.regval = 0};

sound/x86/intel_hdmi_audio.c

599

had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);

sound/x86/intel_hdmi_audio.c

604

frame2.regval = (substream->runtime->channels - 1) | (ca << 24);

sound/x86/intel_hdmi_audio.c

614

checksum += (frame2.regval >> (i * 8)) & 0xff;

sound/x86/intel_hdmi_audio.c

616

checksum += (frame3.regval >> (i * 8)) & 0xff;

sound/x86/intel_hdmi_audio.c

622

had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);

sound/x86/intel_hdmi_audio.c

623

had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);

sound/x86/intel_hdmi_audio.c

631

had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);

sound/x86/intel_hdmi_lpe_audio.h

124

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

148

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

167

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

182

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

192

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

204

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

223

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

236

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

248

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

265

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

276

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

294

u32 regval;

sound/x86/intel_hdmi_lpe_audio.h

306

u32 regval;