arch/arm/mach-rockchip/pm.c

69

static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,

arch/arm/mach-rockchip/pm.c

78

for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {

arch/arm/mach-rockchip/pm.c

79

regmap_read(grf_regmap, reg_offset[i], &reg);

arch/arm64/kvm/vgic/vgic-its.c

1743

.reg_offset = off, \

arch/arm64/kvm/vgic/vgic-its.c

1752

.reg_offset = off, \

arch/arm64/kvm/vgic/vgic-mmio-v3.c

609

.reg_offset = off, \

arch/arm64/kvm/vgic/vgic-mmio-v3.c

616

.reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \

arch/arm64/kvm/vgic/vgic-mmio.c

826

if (offset < region->reg_offset)

arch/arm64/kvm/vgic/vgic-mmio.c

829

if (offset >= region->reg_offset + region->len)

arch/arm64/kvm/vgic/vgic-mmio.h

69

.reg_offset = off, \

arch/arm64/kvm/vgic/vgic-mmio.h

81

.reg_offset = off, \

arch/arm64/kvm/vgic/vgic-mmio.h

9

unsigned int reg_offset;

arch/arm64/kvm/vgic/vgic-mmio.h

91

.reg_offset = off, \

arch/loongarch/kernel/kgdb.c

110

int reg_offset, reg_size;

arch/loongarch/kernel/kgdb.c

115

reg_offset = dbg_reg_def[regno].offset;

arch/loongarch/kernel/kgdb.c

118

if (reg_offset == -1)

arch/loongarch/kernel/kgdb.c

123

memcpy(mem, (void *)regs + reg_offset, reg_size);

arch/loongarch/kernel/kgdb.c

138

memcpy(mem, (void *)&current->thread.fpu.fcc + reg_offset, reg_size);

arch/loongarch/kernel/kgdb.c

141

memcpy(mem, (void *)&current->thread.fpu.fpr[reg_offset], reg_size);

arch/loongarch/kernel/kgdb.c

153

int reg_offset, reg_size;

arch/loongarch/kernel/kgdb.c

158

reg_offset = dbg_reg_def[regno].offset;

arch/loongarch/kernel/kgdb.c

161

if (reg_offset == -1)

arch/loongarch/kernel/kgdb.c

166

memcpy((void *)regs + reg_offset, mem, reg_size);

arch/loongarch/kernel/kgdb.c

179

memcpy((void *)&current->thread.fpu.fcc + reg_offset, mem, reg_size);

arch/loongarch/kernel/kgdb.c

182

memcpy((void *)&current->thread.fpu.fpr[reg_offset], mem, reg_size);

arch/powerpc/boot/ns16550.c

60

u32 reg_offset;

arch/powerpc/boot/ns16550.c

67

n = getprop(devp, "reg-offset", &reg_offset, sizeof(reg_offset));

arch/powerpc/boot/ns16550.c

68

if (n == sizeof(reg_offset))

arch/powerpc/boot/ns16550.c

69

reg_base += be32_to_cpu(reg_offset);

arch/powerpc/include/asm/tsi108.h

103

static inline u32 tsi108_read_reg(u32 reg_offset)

arch/powerpc/include/asm/tsi108.h

105

return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));

arch/powerpc/include/asm/tsi108.h

108

static inline void tsi108_write_reg(u32 reg_offset, u32 val)

arch/powerpc/include/asm/tsi108.h

110

out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);

arch/powerpc/sysdev/tsi108_pci.c

45

extern u32 tsi108_read_reg(u32 reg_offset);

arch/powerpc/sysdev/tsi108_pci.c

46

extern void tsi108_write_reg(u32 reg_offset, u32 val);

arch/x86/include/asm/uprobes.h

49

u8 reg_offset; /* to the start of pt_regs */

arch/x86/kernel/umip.c

349

int nr_copied, reg_offset, dummy_data_size, umip_inst;

arch/x86/kernel/umip.c

391

reg_offset = insn_get_modrm_rm_off(&insn, regs);

arch/x86/kernel/umip.c

398

if (reg_offset < 0)

arch/x86/kernel/umip.c

401

reg_addr = (unsigned long *)((unsigned long)regs + reg_offset);

arch/x86/kernel/uprobes.c

1351

unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset;

arch/x86/kernel/uprobes.c

1455

u8 opc1 = OPCODE1(insn), reg_offset = 0;

arch/x86/kernel/uprobes.c

1471

reg_offset = offsetof(struct pt_regs, r8);

arch/x86/kernel/uprobes.c

1474

reg_offset = offsetof(struct pt_regs, r9);

arch/x86/kernel/uprobes.c

1477

reg_offset = offsetof(struct pt_regs, r10);

arch/x86/kernel/uprobes.c

1480

reg_offset = offsetof(struct pt_regs, r11);

arch/x86/kernel/uprobes.c

1483

reg_offset = offsetof(struct pt_regs, r12);

arch/x86/kernel/uprobes.c

1486

reg_offset = offsetof(struct pt_regs, r13);

arch/x86/kernel/uprobes.c

1489

reg_offset = offsetof(struct pt_regs, r14);

arch/x86/kernel/uprobes.c

1492

reg_offset = offsetof(struct pt_regs, r15);

arch/x86/kernel/uprobes.c

1501

reg_offset = offsetof(struct pt_regs, ax);

arch/x86/kernel/uprobes.c

1504

reg_offset = offsetof(struct pt_regs, cx);

arch/x86/kernel/uprobes.c

1507

reg_offset = offsetof(struct pt_regs, dx);

arch/x86/kernel/uprobes.c

1510

reg_offset = offsetof(struct pt_regs, bx);

arch/x86/kernel/uprobes.c

1513

reg_offset = offsetof(struct pt_regs, sp);

arch/x86/kernel/uprobes.c

1516

reg_offset = offsetof(struct pt_regs, bp);

arch/x86/kernel/uprobes.c

1519

reg_offset = offsetof(struct pt_regs, si);

arch/x86/kernel/uprobes.c

1522

reg_offset = offsetof(struct pt_regs, di);

arch/x86/kernel/uprobes.c

1527

auprobe->push.reg_offset = reg_offset;

arch/x86/math-emu/get_address.c

32

static int reg_offset[] = {

arch/x86/math-emu/get_address.c

43

#define REG_(x) (*(long *)(reg_offset[(x)] + (u_char *)FPU_info->regs))

arch/x86/mm/extable.c

18

int reg_offset = pt_regs_offset(regs, nr);

arch/x86/mm/extable.c

21

if (WARN_ON_ONCE(reg_offset < 0))

arch/x86/mm/extable.c

24

return (unsigned long *)((unsigned long)regs + reg_offset);

drivers/accel/habanalabs/common/security.c

107

u32 reg_offset;

drivers/accel/habanalabs/common/security.c

115

reg_offset = (mm_reg_addr + offset) - pb_blocks[block_num];

drivers/accel/habanalabs/common/security.c

117

return hl_unset_pb_in_block(hdev, reg_offset, &sgs_array[block_num]);

drivers/accel/habanalabs/common/security.c

137

u32 reg_offset;

drivers/accel/habanalabs/common/security.c

147

reg_offset = (i + offset) - pb_blocks[block_num];

drivers/accel/habanalabs/common/security.c

148

rc |= hl_unset_pb_in_block(hdev, reg_offset,

drivers/accel/habanalabs/common/security.c

75

static int hl_unset_pb_in_block(struct hl_device *hdev, u32 reg_offset,

drivers/accel/habanalabs/common/security.c

78

if ((reg_offset >= HL_BLOCK_SIZE) || (reg_offset & 0x3)) {

drivers/accel/habanalabs/common/security.c

81

reg_offset, HL_BLOCK_SIZE);

drivers/accel/habanalabs/common/security.c

86

(reg_offset & (HL_BLOCK_SIZE - 1)) >> 2);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8038

u32 reg_base, reg_offset, reg_val = 0;

drivers/accel/habanalabs/gaudi2/gaudi2.c

8046

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION3_GENERAL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8047

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8049

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION4_HBM0_FW);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8050

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8052

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION5_HBM1_GC_DATA);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8053

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8055

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION6_HBM2_GC_DATA);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8056

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8058

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION7_HBM3_GC_DATA);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8059

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8061

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION9_PCIE);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8062

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8064

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION10_GENERAL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8065

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8067

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION11_GENERAL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8068

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8070

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION12_GENERAL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8071

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8073

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION13_GENERAL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8074

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8076

reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION14_GENERAL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8077

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/goya/goya.c

3600

u16 reg_offset;

drivers/accel/habanalabs/goya/goya.c

3602

reg_offset = le32_to_cpu(wreg_pkt->ctl) &

drivers/accel/habanalabs/goya/goya.c

3606

dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);

drivers/accel/habanalabs/goya/goya.c

3610

if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {

drivers/accel/habanalabs/goya/goya.c

3612

reg_offset);

drivers/accel/ivpu/ivpu_hw_reg_io.h

63

u32 reg_offset, u32 reg_mask, u32 exp_masked_val, u32 timeout_us,

drivers/accel/ivpu/ivpu_hw_reg_io.h

70

func_name, reg_name, reg_offset, fld_name, exp_masked_val);

drivers/accel/ivpu/ivpu_hw_reg_io.h

73

REG_POLL_SLEEP_US, timeout_us, false, base + reg_offset);

drivers/accel/ivpu/ivpu_hw_reg_io.h

81

func_name, reg_name, reg_offset, fld_name, ret ? "ETIMEDOUT" : "OK", reg_val);

drivers/base/regmap/regmap-debugfs.c

104

unsigned int reg_offset;

drivers/base/regmap/regmap-debugfs.c

167

reg_offset = fpos_offset / map->debugfs_tot_len;

drivers/base/regmap/regmap-debugfs.c

168

*pos = c->min + (reg_offset * map->debugfs_tot_len);

drivers/base/regmap/regmap-debugfs.c

170

return c->base_reg + (reg_offset * map->reg_stride);

drivers/base/regmap/regmap-irq.c

215

unsigned int reg = irq_data->reg_offset / map->reg_stride;

drivers/base/regmap/regmap-irq.c

245

d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;

drivers/base/regmap/regmap-irq.c

286

d->wake_buf[irq_data->reg_offset / map->reg_stride]

drivers/base/regmap/regmap-irq.c

291

d->wake_buf[irq_data->reg_offset / map->reg_stride]

drivers/base/regmap/regmap-irq.c

513

if (data->status_buf[chip->irqs[i].reg_offset /

drivers/base/regmap/regmap-irq.c

693

if (chip->irqs[i].reg_offset % map->reg_stride)

drivers/base/regmap/regmap-irq.c

695

if (chip->irqs[i].reg_offset / map->reg_stride >=

drivers/base/regmap/regmap-irq.c

814

d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]

drivers/bus/stm32_etzpc.c

46

u32 offset, reg_offset, sec_val;

drivers/bus/stm32_etzpc.c

54

reg_offset = ETZPC_DECPROT + 0x4 * (firewall_id / IDS_PER_DECPROT_REGS);

drivers/bus/stm32_etzpc.c

58

sec_val = (readl(ctrl->mmio + reg_offset) >> offset) & ETZPC_PROT_MASK;

drivers/bus/stm32_etzpc.c

61

reg_offset, sec_val);

drivers/bus/stm32_rifsc.c

466

u8 reg_offset = i % IDS_PER_RISC_SEC_PRIV_REGS;

drivers/bus/stm32_rifsc.c

479

dbg_entry->dev_sec = sec_cfgr & BIT(reg_offset) ? true : false;

drivers/bus/stm32_rifsc.c

480

dbg_entry->dev_priv = priv_cfgr & BIT(reg_offset) ? true : false;

drivers/bus/stm32_rifsc.c

673

u32 reg_offset, reg_id, sec_reg_value, cid_reg_value;

drivers/bus/stm32_rifsc.c

687

reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS;

drivers/bus/stm32_rifsc.c

720

if (sec_reg_value & BIT(reg_offset)) {

drivers/char/ipmi/ipmi_si_ls2k.c

100

writew(val, addr + reg_offset);

drivers/char/ipmi/ipmi_si_ls2k.c

110

int reg_offset;

drivers/char/ipmi/ipmi_si_ls2k.c

118

reg_offset = (offset & BIT(0)) ? LS2K_KCS_REG_CMD : LS2K_KCS_REG_DATA_IN;

drivers/char/ipmi/ipmi_si_ls2k.c

119

writew(val, addr + reg_offset);

drivers/char/ipmi/ipmi_si_ls2k.c

47

int reg_offset;

drivers/char/ipmi/ipmi_si_ls2k.c

50

reg_offset = LS2K_KCS_REG_STS;

drivers/char/ipmi/ipmi_si_ls2k.c

53

reg_offset = LS2K_KCS_REG_DATA_OUT;

drivers/char/ipmi/ipmi_si_ls2k.c

56

return readb(addr + reg_offset);

drivers/char/ipmi/ipmi_si_ls2k.c

87

int reg_offset;

drivers/char/ipmi/ipmi_si_ls2k.c

93

reg_offset = LS2K_KCS_REG_CMD;

drivers/char/ipmi/ipmi_si_ls2k.c

96

reg_offset = LS2K_KCS_REG_DATA_IN;

drivers/clk/bcm/clk-kona.c

105

static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset)

drivers/clk/bcm/clk-kona.c

107

return readl(ccu->base + reg_offset);

drivers/clk/bcm/clk-kona.c

112

__ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val)

drivers/clk/bcm/clk-kona.c

114

writel(reg_val, ccu->base + reg_offset);

drivers/clk/bcm/clk-kona.c

166

__ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want)

drivers/clk/bcm/clk-kona.c

175

val = __ccu_read(ccu, reg_offset);

drivers/clk/bcm/clk-kona.c

182

ccu->name, reg_offset, bit, want ? "set" : "clear");

drivers/clk/clk-loongson2.c

103

.reg_offset = _offset, \

drivers/clk/clk-loongson2.c

115

.reg_offset = _offset, \

drivers/clk/clk-loongson2.c

126

.reg_offset = _offset, \

drivers/clk/clk-loongson2.c

339

clk->reg = clp->base + cld->reg_offset;

drivers/clk/clk-loongson2.c

408

clp->base + p->reg_offset,

drivers/clk/clk-loongson2.c

417

clp->base + p->reg_offset,

drivers/clk/clk-loongson2.c

51

u8 reg_offset;

drivers/clk/clk-loongson2.c

65

.reg_offset = _offset, \

drivers/clk/clk-loongson2.c

77

.reg_offset = _offset, \

drivers/clk/clk-loongson2.c

91

.reg_offset = _offset, \

drivers/clk/microchip/clk-mpfs-ccc.c

105

.reg_offset = _offset, \

drivers/clk/microchip/clk-mpfs-ccc.c

121

u32 reg_offset;

drivers/clk/microchip/clk-mpfs-ccc.c

128

.reg_offset = _offset, \

drivers/clk/microchip/clk-mpfs-ccc.c

174

out_hw->reg_offset;

drivers/clk/microchip/clk-mpfs-ccc.c

47

u32 reg_offset;

drivers/clk/microchip/clk-mpfs-ccc.c

76

void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset;

drivers/clk/microchip/clk-mpfs.c

150

void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;

drivers/clk/microchip/clk-mpfs.c

171

.reg_offset = _offset, \

drivers/clk/microchip/clk-mpfs.c

210

.reg_offset = _offset, \

drivers/clk/microchip/clk-mpfs.c

237

msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset;

drivers/clk/microchip/clk-mpfs.c

64

u32 reg_offset;

drivers/clk/microchip/clk-mpfs.c

77

u32 reg_offset;

drivers/clk/nxp/clk-lpc18xx-cgu.c

261

u8 reg_offset;

drivers/clk/nxp/clk-lpc18xx-cgu.c

272

.reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \

drivers/clk/nxp/clk-lpc18xx-cgu.c

586

clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;

drivers/clk/nxp/clk-lpc18xx-cgu.c

587

clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;

drivers/clk/qcom/apcs-msm8916.c

78

a53cc->reg_offset = 0x50;

drivers/clk/qcom/apcs-sdx55.c

75

a7cc->reg_offset = 0x8;

drivers/clk/qcom/clk-regmap-mux-div.c

33

ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,

drivers/clk/qcom/clk-regmap-mux-div.c

38

ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,

drivers/clk/qcom/clk-regmap-mux-div.c

45

ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,

drivers/clk/qcom/clk-regmap-mux-div.c

65

regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);

drivers/clk/qcom/clk-regmap-mux-div.c

72

regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);

drivers/clk/qcom/clk-regmap-mux-div.h

28

u32 reg_offset;

drivers/clk/ti/clkctrl.c

237

if (iter->reg_offset == clkspec->args[0] &&

drivers/clk/ti/clkctrl.c

318

clkctrl_clk->reg_offset = offset;

drivers/clk/ti/clkctrl.c

51

u16 reg_offset;

drivers/clk/ti/clkctrl.c

697

clkctrl_clk->reg_offset = reg_data->offset;

drivers/clocksource/timer-atmel-pit.c

59

static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)

drivers/clocksource/timer-atmel-pit.c

61

return readl_relaxed(base + reg_offset);

drivers/clocksource/timer-atmel-pit.c

64

static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)

drivers/clocksource/timer-atmel-pit.c

66

writel_relaxed(value, base + reg_offset);

drivers/comedi/drivers/comedi_8254.c

131

unsigned int reg_offset = (reg * I8254_IO8) << i8254->regshift;

drivers/comedi/drivers/comedi_8254.c

134

outb(val, iobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

137

return inb(iobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

145

unsigned int reg_offset = (reg * I8254_IO16) << i8254->regshift;

drivers/comedi/drivers/comedi_8254.c

148

outw(val, iobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

151

return inw(iobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

159

unsigned int reg_offset = (reg * I8254_IO32) << i8254->regshift;

drivers/comedi/drivers/comedi_8254.c

162

outl(val, iobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

165

return inl(iobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

175

unsigned int reg_offset = (reg * I8254_IO8) << i8254->regshift;

drivers/comedi/drivers/comedi_8254.c

178

writeb(val, mmiobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

181

return readb(mmiobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

189

unsigned int reg_offset = (reg * I8254_IO16) << i8254->regshift;

drivers/comedi/drivers/comedi_8254.c

192

writew(val, mmiobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

195

return readw(mmiobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

203

unsigned int reg_offset = (reg * I8254_IO32) << i8254->regshift;

drivers/comedi/drivers/comedi_8254.c

206

writel(val, mmiobase + reg_offset);

drivers/comedi/drivers/comedi_8254.c

209

return readl(mmiobase + reg_offset);

drivers/crypto/hisilicon/debugfs.c

1012

base_offset = dregs[i].reg_offset + j * QM_DFX_REGS_LEN;

drivers/crypto/hisilicon/debugfs.c

120

.reg_offset = QM_DFX_BASE,

drivers/crypto/hisilicon/debugfs.c

123

.reg_offset = QM_DFX_STATE1,

drivers/crypto/hisilicon/debugfs.c

126

.reg_offset = QM_DFX_STATE2,

drivers/crypto/hisilicon/debugfs.c

129

.reg_offset = QM_DFX_COMMON,

drivers/crypto/hisilicon/debugfs.c

849

diff_regs[i].reg_offset = cregs[i].reg_offset;

drivers/crypto/hisilicon/debugfs.c

857

base_offset = diff_regs[i].reg_offset +

drivers/crypto/hisilicon/hpre/hpre_main.c

359

.reg_offset = HPRE_DFX_BASE,

drivers/crypto/hisilicon/hpre/hpre_main.c

362

.reg_offset = HPRE_DFX_COMMON1,

drivers/crypto/hisilicon/hpre/hpre_main.c

365

.reg_offset = HPRE_DFX_COMMON2,

drivers/crypto/hisilicon/hpre/hpre_main.c

368

.reg_offset = HPRE_DFX_CORE,

drivers/crypto/hisilicon/sec2/sec_main.c

330

.reg_offset = SEC_DFX_BASE,

drivers/crypto/hisilicon/sec2/sec_main.c

333

.reg_offset = SEC_DFX_COMMON1,

drivers/crypto/hisilicon/sec2/sec_main.c

336

.reg_offset = SEC_DFX_COMMON2,

drivers/crypto/hisilicon/sec2/sec_main.c

339

.reg_offset = SEC_DFX_CORE,

drivers/crypto/hisilicon/zip/zip_main.c

333

.reg_offset = HZIP_CORE_DFX_BASE,

drivers/crypto/hisilicon/zip/zip_main.c

336

.reg_offset = HZIP_CORE_DFX_COMP_0,

drivers/crypto/hisilicon/zip/zip_main.c

339

.reg_offset = HZIP_CORE_DFX_COMP_1,

drivers/crypto/hisilicon/zip/zip_main.c

342

.reg_offset = HZIP_CORE_DFX_DECOMP_0,

drivers/crypto/hisilicon/zip/zip_main.c

345

.reg_offset = HZIP_CORE_DFX_DECOMP_1,

drivers/crypto/hisilicon/zip/zip_main.c

348

.reg_offset = HZIP_CORE_DFX_DECOMP_2,

drivers/crypto/hisilicon/zip/zip_main.c

351

.reg_offset = HZIP_CORE_DFX_DECOMP_3,

drivers/crypto/hisilicon/zip/zip_main.c

354

.reg_offset = HZIP_CORE_DFX_DECOMP_4,

drivers/crypto/hisilicon/zip/zip_main.c

357

.reg_offset = HZIP_CORE_DFX_DECOMP_5,

drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c

28

pm_info_regs[table[i].reg_offset]));

drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.h

16

.reg_offset = PM_INFO_MEMBER_OFF(_reg_), \

drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.h

25

int reg_offset;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

67

reg_msg->reg_offset = reg;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

92

reg_msg->reg_offset = reg;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

486

rsp_rd_wr->reg_offset, rsp_rd_wr->is_write,

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

117

rsp_reg->reg_offset, rsp_reg->is_write,

drivers/extcon/extcon-max77843.c

167

{ .reg_offset = 0, .mask = MAX77843_MUIC_ADC, },

drivers/extcon/extcon-max77843.c

168

{ .reg_offset = 0, .mask = MAX77843_MUIC_ADCERROR, },

drivers/extcon/extcon-max77843.c

169

{ .reg_offset = 0, .mask = MAX77843_MUIC_ADC1K, },

drivers/extcon/extcon-max77843.c

172

{ .reg_offset = 1, .mask = MAX77843_MUIC_CHGTYP, },

drivers/extcon/extcon-max77843.c

173

{ .reg_offset = 1, .mask = MAX77843_MUIC_CHGDETRUN, },

drivers/extcon/extcon-max77843.c

174

{ .reg_offset = 1, .mask = MAX77843_MUIC_DCDTMR, },

drivers/extcon/extcon-max77843.c

175

{ .reg_offset = 1, .mask = MAX77843_MUIC_DXOVP, },

drivers/extcon/extcon-max77843.c

176

{ .reg_offset = 1, .mask = MAX77843_MUIC_VBVOLT, },

drivers/extcon/extcon-max77843.c

179

{ .reg_offset = 2, .mask = MAX77843_MUIC_VBADC, },

drivers/extcon/extcon-max77843.c

180

{ .reg_offset = 2, .mask = MAX77843_MUIC_VDNMON, },

drivers/extcon/extcon-max77843.c

181

{ .reg_offset = 2, .mask = MAX77843_MUIC_DNRES, },

drivers/extcon/extcon-max77843.c

182

{ .reg_offset = 2, .mask = MAX77843_MUIC_MPNACK, },

drivers/extcon/extcon-max77843.c

183

{ .reg_offset = 2, .mask = MAX77843_MUIC_MRXBUFOW, },

drivers/extcon/extcon-max77843.c

184

{ .reg_offset = 2, .mask = MAX77843_MUIC_MRXTRF, },

drivers/extcon/extcon-max77843.c

185

{ .reg_offset = 2, .mask = MAX77843_MUIC_MRXPERR, },

drivers/extcon/extcon-max77843.c

186

{ .reg_offset = 2, .mask = MAX77843_MUIC_MRXRDY, },

drivers/extcon/extcon-rt8973a.c

172

{ .reg_offset = 0, .mask = RT8973A_INT1_ATTACH_MASK, },

drivers/extcon/extcon-rt8973a.c

173

{ .reg_offset = 0, .mask = RT8973A_INT1_DETACH_MASK, },

drivers/extcon/extcon-rt8973a.c

174

{ .reg_offset = 0, .mask = RT8973A_INT1_CHGDET_MASK, },

drivers/extcon/extcon-rt8973a.c

175

{ .reg_offset = 0, .mask = RT8973A_INT1_DCD_T_MASK, },

drivers/extcon/extcon-rt8973a.c

176

{ .reg_offset = 0, .mask = RT8973A_INT1_OVP_MASK, },

drivers/extcon/extcon-rt8973a.c

177

{ .reg_offset = 0, .mask = RT8973A_INT1_CONNECT_MASK, },

drivers/extcon/extcon-rt8973a.c

178

{ .reg_offset = 0, .mask = RT8973A_INT1_ADC_CHG_MASK, },

drivers/extcon/extcon-rt8973a.c

179

{ .reg_offset = 0, .mask = RT8973A_INT1_OTP_MASK, },

drivers/extcon/extcon-rt8973a.c

182

{ .reg_offset = 1, .mask = RT8973A_INT2_UVLOT_MASK,},

drivers/extcon/extcon-rt8973a.c

183

{ .reg_offset = 1, .mask = RT8973A_INT2_POR_MASK, },

drivers/extcon/extcon-rt8973a.c

184

{ .reg_offset = 1, .mask = RT8973A_INT2_OTP_FET_MASK, },

drivers/extcon/extcon-rt8973a.c

185

{ .reg_offset = 1, .mask = RT8973A_INT2_OVP_FET_MASK, },

drivers/extcon/extcon-rt8973a.c

186

{ .reg_offset = 1, .mask = RT8973A_INT2_OCP_LATCH_MASK, },

drivers/extcon/extcon-rt8973a.c

187

{ .reg_offset = 1, .mask = RT8973A_INT2_OCP_MASK, },

drivers/extcon/extcon-rt8973a.c

188

{ .reg_offset = 1, .mask = RT8973A_INT2_OVP_OCP_MASK, },

drivers/extcon/extcon-sm5502.c

208

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, },

drivers/extcon/extcon-sm5502.c

209

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, },

drivers/extcon/extcon-sm5502.c

210

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, },

drivers/extcon/extcon-sm5502.c

211

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, },

drivers/extcon/extcon-sm5502.c

212

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, },

drivers/extcon/extcon-sm5502.c

213

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_EVENT_MASK, },

drivers/extcon/extcon-sm5502.c

214

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_OCP_EVENT_MASK, },

drivers/extcon/extcon-sm5502.c

215

{ .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_OCP_DIS_MASK, },

drivers/extcon/extcon-sm5502.c

218

{ .reg_offset = 1, .mask = SM5502_IRQ_INT2_VBUS_DET_MASK,},

drivers/extcon/extcon-sm5502.c

219

{ .reg_offset = 1, .mask = SM5502_IRQ_INT2_REV_ACCE_MASK, },

drivers/extcon/extcon-sm5502.c

220

{ .reg_offset = 1, .mask = SM5502_IRQ_INT2_ADC_CHG_MASK, },

drivers/extcon/extcon-sm5502.c

221

{ .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_MASK, },

drivers/extcon/extcon-sm5502.c

222

{ .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK, },

drivers/extcon/extcon-sm5502.c

223

{ .reg_offset = 1, .mask = SM5502_IRQ_INT2_MHL_MASK, },

drivers/extcon/extcon-sm5502.c

256

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_ATTACH_MASK, },

drivers/extcon/extcon-sm5502.c

257

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_DETACH_MASK, },

drivers/extcon/extcon-sm5502.c

258

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_CHG_DET_MASK, },

drivers/extcon/extcon-sm5502.c

259

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_DCD_OUT_MASK, },

drivers/extcon/extcon-sm5502.c

260

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_OVP_MASK, },

drivers/extcon/extcon-sm5502.c

261

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_CONNECT_MASK, },

drivers/extcon/extcon-sm5502.c

262

{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_ADC_CHG_MASK, },

drivers/extcon/extcon-sm5502.c

265

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_RID_CHG_MASK,},

drivers/extcon/extcon-sm5502.c

266

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_UVLO_MASK, },

drivers/extcon/extcon-sm5502.c

267

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_POR_MASK, },

drivers/extcon/extcon-sm5502.c

268

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OVP_FET_MASK, },

drivers/extcon/extcon-sm5502.c

269

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OCP_LATCH_MASK, },

drivers/extcon/extcon-sm5502.c

270

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OCP_EVENT_MASK, },

drivers/extcon/extcon-sm5502.c

271

{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK, },

drivers/fpga/socfpga.c

134

static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset)

drivers/fpga/socfpga.c

136

return readl(priv->fpga_base_addr + reg_offset);

drivers/fpga/socfpga.c

139

static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset,

drivers/fpga/socfpga.c

142

writel(value, priv->fpga_base_addr + reg_offset);

drivers/fpga/socfpga.c

146

u32 reg_offset)

drivers/fpga/socfpga.c

148

return __raw_readl(priv->fpga_base_addr + reg_offset);

drivers/fpga/socfpga.c

152

u32 reg_offset, u32 value)

drivers/fpga/socfpga.c

154

__raw_writel(value, priv->fpga_base_addr + reg_offset);

drivers/gpio/gpio-bcm-kona.c

159

u32 val, reg_offset;

drivers/gpio/gpio-bcm-kona.c

170

reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);

drivers/gpio/gpio-bcm-kona.c

172

val = readl(reg_base + reg_offset);

drivers/gpio/gpio-bcm-kona.c

174

writel(val, reg_base + reg_offset);

drivers/gpio/gpio-bcm-kona.c

185

u32 val, reg_offset;

drivers/gpio/gpio-bcm-kona.c

193

reg_offset = GPIO_IN_STATUS(bank_id);

drivers/gpio/gpio-bcm-kona.c

195

reg_offset = GPIO_OUT_STATUS(bank_id);

drivers/gpio/gpio-bcm-kona.c

198

val = readl(reg_base + reg_offset);

drivers/gpio/gpio-bcm-kona.c

245

u32 val, reg_offset;

drivers/gpio/gpio-bcm-kona.c

256

reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);

drivers/gpio/gpio-bcm-kona.c

258

val = readl(reg_base + reg_offset);

drivers/gpio/gpio-bcm-kona.c

260

writel(val, reg_base + reg_offset);

drivers/gpio/gpio-bd72720.c

72

static int bd72720gpi_get(struct bd72720_gpio *bdgpio, unsigned int reg_offset)

drivers/gpio/gpio-bd72720.c

80

shift = BD72720_INT_GPIO1_IN_SRC + reg_offset;

drivers/gpio/gpio-madera.c

28

unsigned int reg_offset = 2 * offset;

drivers/gpio/gpio-madera.c

32

ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_2 + reg_offset,

drivers/gpio/gpio-madera.c

47

unsigned int reg_offset = 2 * offset;

drivers/gpio/gpio-madera.c

50

MADERA_GPIO1_CTRL_2 + reg_offset,

drivers/gpio/gpio-madera.c

58

unsigned int reg_offset = 2 * offset;

drivers/gpio/gpio-madera.c

62

ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_1 + reg_offset,

drivers/gpio/gpio-madera.c

75

unsigned int reg_offset = 2 * offset;

drivers/gpio/gpio-madera.c

80

MADERA_GPIO1_CTRL_2 + reg_offset,

drivers/gpio/gpio-madera.c

86

MADERA_GPIO1_CTRL_1 + reg_offset,

drivers/gpio/gpio-madera.c

95

unsigned int reg_offset = 2 * offset;

drivers/gpio/gpio-madera.c

99

MADERA_GPIO1_CTRL_1 + reg_offset,

drivers/gpio/gpio-pcie-idio-24.c

125

.reg_offset = (_id) / IDIO_24_NGPIO_PER_REG, \

drivers/gpio/gpio-pcie-idio-24.c

182

const unsigned int offset = irq_data->reg_offset;

drivers/gpio/gpio-rtd.c

220

u8 deb_val, deb_index, reg_offset, shift;

drivers/gpio/gpio-rtd.c

250

deb_val = data->info->get_deb_setval(data->info, offset, deb_index, &reg_offset, &shift);

drivers/gpio/gpio-rtd.c

255

writel_relaxed(val, data->base + reg_offset);

drivers/gpio/gpio-rtd.c

320

int reg_offset;

drivers/gpio/gpio-rtd.c

323

reg_offset = rtd_gpio_dir_offset(data, offset);

drivers/gpio/gpio-rtd.c

324

val = readl_relaxed(data->base + reg_offset);

drivers/gpio/gpio-rtd.c

335

int reg_offset;

drivers/gpio/gpio-rtd.c

338

reg_offset = rtd_gpio_dir_offset(data, offset);

drivers/gpio/gpio-rtd.c

342

val = readl_relaxed(data->base + reg_offset);

drivers/gpio/gpio-rtd.c

347

writel_relaxed(val, data->base + reg_offset);

drivers/gpio/gpio-rtd.c

384

int reg_offset, i, j;

drivers/gpio/gpio-rtd.c

396

reg_offset = get_reg_offset(data, i);

drivers/gpio/gpio-rtd.c

403

status = readl_relaxed(data->irq_base + reg_offset);

drivers/gpio/gpio-rtd.c

405

writel_relaxed(status, data->irq_base + reg_offset);

drivers/gpio/gpio-rtd.c

60

u8 *reg_offset, u8 *shift);

drivers/gpio/gpio-rtd.c

73

u8 deb_index, u8 *reg_offset, u8 *shift)

drivers/gpio/gpio-rtd.c

75

*reg_offset = info->deb_offset[offset / 8];

drivers/gpio/gpio-rtd.c

81

u8 deb_index, u8 *reg_offset, u8 *shift)

drivers/gpio/gpio-rtd.c

83

*reg_offset = info->deb_offset[0];

drivers/gpio/gpio-rtd.c

89

u8 deb_index, u8 *reg_offset, u8 *shift)

drivers/gpio/gpio-rtd.c

91

*reg_offset = info->deb_offset[0];

drivers/gpio/gpio-tangier.c

67

u8 reg_offset = offset / 32;

drivers/gpio/gpio-tangier.c

69

return priv->reg_base + reg + reg_offset * 4;

drivers/gpio/gpio-tangier.c

76

u8 reg_offset = offset / 32;

drivers/gpio/gpio-tangier.c

80

return priv->reg_base + reg + reg_offset * 4;

drivers/gpio/gpio-uniphier.c

101

unsigned int bank, reg_offset;

drivers/gpio/gpio-uniphier.c

105

reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;

drivers/gpio/gpio-uniphier.c

107

return !!(readl(priv->regs + reg_offset) & mask);

drivers/gpio/gpio-ws16c48.c

81

.reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \

drivers/gpio/gpio-zynq.c

271

unsigned int reg_offset, bank_num, bank_pin_num;

drivers/gpio/gpio-zynq.c

279

reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);

drivers/gpio/gpio-zynq.c

281

reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);

drivers/gpio/gpio-zynq.c

292

writel_relaxed(state, gpio->base_addr + reg_offset);

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

41

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

42

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

43

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

44

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

45

adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

46

adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

47

adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

48

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

49

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

50

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

51

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1122

uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];

drivers/gpu/drm/amd/amdgpu/amdgpu.h

146

u32 reg_offset;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

537

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

607

u32 sh_num, u32 reg_offset, u32 *value);

drivers/gpu/drm/amd/amdgpu/amdgpu.h

699

u32 reg_offset;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

515

uint32_t reg_offset = get_sdma_rlc_reg_offset(adev, engine, queue);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

516

uint32_t status = RREG32(regSDMA_RLC0_CONTEXT_STATUS + reg_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

517

uint32_t doorbell_off = RREG32(regSDMA_RLC0_DOORBELL_OFFSET + reg_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1028

uint32_t *reg_offset,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1044

*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

58

uint32_t *reg_offset,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1084

uint32_t *reg_offset,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1100

*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

104

uint32_t *reg_offset,

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1540

adev->reg_offset[hw_ip][ip->instance_number] =

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c

55

WREG32((adev->rmmio_remap.reg_offset +

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c

63

(adev->rmmio_remap.reg_offset +

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

486

op_input.read_reg.reg_offset = reg;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

516

op_input.write_reg.reg_offset = reg;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

341

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

346

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

387

(adev->reg_offset[hwip][ip_inst][segment] + (reg))

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

202

uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

204

*adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2); \

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

207

WREG32(reg_offset, value); \

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

1146

offset = adev->reg_offset[UVD_HWIP][ring->me][1];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

107

addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

169

addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

84

((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

96

((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

41

adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

42

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

43

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

44

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

45

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

46

adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

47

adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

48

adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

49

adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

50

adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

51

adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

52

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

53

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

54

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/arct_reg_init.c

55

adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cik.c

1124

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/cik.c

1131

switch (reg_offset) {

drivers/gpu/drm/amd/amdgpu/cik.c

1146

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/cik.c

1155

switch (reg_offset) {

drivers/gpu/drm/amd/amdgpu/cik.c

1192

idx = (reg_offset - mmGB_TILE_MODE0);

drivers/gpu/drm/amd/amdgpu/cik.c

1210

idx = (reg_offset - mmGB_MACROTILE_MODE0);

drivers/gpu/drm/amd/amdgpu/cik.c

1213

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/cik.c

1219

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/cik.c

1227

if (reg_offset != cik_allowed_read_registers[i].reg_offset)

drivers/gpu/drm/amd/amdgpu/cik.c

1231

reg_offset);

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

38

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

39

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

40

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

41

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

42

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

43

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

44

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

45

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

46

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

47

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

48

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

49

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

50

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

51

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

52

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

53

adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

35

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

36

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

37

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

38

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

39

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

40

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

41

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

42

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

43

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

44

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

45

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

46

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

47

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

48

adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

49

adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

50

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

51

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8223

reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8231

reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8240

reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8346

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9668

if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9736

if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7052

if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7120

gc_cp_reg_list_11[reg].reg_offset ==

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1073

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1074

WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1297

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1298

WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

403

u32 reg_offset, split_equal_to_row_size, *tilemode;

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

643

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

644

WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

849

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

850

WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1018

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1019

tile[reg_offset] = 0;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1020

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1021

macrotile[reg_offset] = 0;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1185

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1186

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1187

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1188

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1189

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1368

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1369

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1370

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1371

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1372

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1538

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1539

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1540

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1541

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1542

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

999

u32 reg_offset, split_equal_to_row_size;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2069

u32 reg_offset;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2074

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2075

modearray[reg_offset] = 0;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2077

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2078

mod2array[reg_offset] = 0;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2242

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2243

if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2244

reg_offset != 23)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2245

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2247

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2248

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2249

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2434

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2435

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2437

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2438

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2439

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2623

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2624

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2626

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2627

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2628

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2826

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2827

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2829

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2830

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

2831

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3028

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3029

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3031

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3032

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3033

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3197

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3198

if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3199

reg_offset != 23)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3200

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3202

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3203

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3204

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3374

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3375

if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3376

reg_offset != 23)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3377

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3379

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3380

if (reg_offset != 7)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3381

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5202

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6975

if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7364

if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7408

if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

836

if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1472

if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset ||

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1715

reg = adev->reg_offset[entry->hwip][inst][entry->segment] +

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4604

if (i && gc_cp_reg_list_9_4_3[reg].reg_offset ==

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4667

if (i && gc_cp_reg_list_9_4_3[reg].reg_offset ==

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

34

WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

38

RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

49

(adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

335

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.c

117

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

267

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

104

if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

105

((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

107

ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

109

ring->ring[ptr++] = reg_offset;

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

122

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

124

jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

128

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

130

jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

358

uint32_t reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

370

if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

371

((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

374

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

376

amdgpu_ring_write(ring, reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

402

uint32_t reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

406

if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

407

((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

410

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

412

amdgpu_ring_write(ring, reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

42

static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

46

if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

47

((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

49

ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

51

ring->ring[(*ptr)++] = reg_offset;

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

61

uint32_t reg, reg_offset, val, mask, i;

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

65

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

67

jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

71

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

73

jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

83

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

85

jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

89

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

91

jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

95

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

616

uint32_t reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

628

if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

631

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

633

amdgpu_ring_write(ring, reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

657

uint32_t reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

661

if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

664

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

666

amdgpu_ring_write(ring, reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1123

int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1127

reg_offset, 0x1F);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1130

reg_offset, 0x1F, 0x1F);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1133

reg_offset, 0x1F);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1137

reg_offset, 0x00);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1140

reg_offset, 0x00);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

576

int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

585

reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

588

reg_offset,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

592

reg_offset, lower_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

595

reg_offset, upper_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

598

reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

601

reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

604

reg_offset, 0x00000002L);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

607

reg_offset, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

609

reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

889

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

895

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

907

if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

910

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

912

amdgpu_ring_write(ring, reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

936

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

942

reg_offset = (reg << 2);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

946

if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

949

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

951

amdgpu_ring_write(ring, reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

406

int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

422

reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

425

reg_offset,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

429

reg_offset, lower_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

432

reg_offset, upper_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

435

reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

438

reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

441

reg_offset, 0x00000002L);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

444

reg_offset, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

446

reg_offset);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

665

int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

668

regUVD_JRBC_STATUS, reg_offset) &

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

685

int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

688

regUVD_JRBC_STATUS, reg_offset,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

822

int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

826

reg_offset, 0x1F);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

829

reg_offset, 0x1F, 0x1F);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

832

reg_offset, 0x1F);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

836

reg_offset, 0x00);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

839

reg_offset, 0x00);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

614

misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

619

misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

710

mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

712

adev->reg_offset[MMHUB_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

714

adev->reg_offset[OSSSYS_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

655

misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

660

misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

773

mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

775

adev->reg_offset[MMHUB_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

777

adev->reg_offset[OSSSYS_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

492

static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset)

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

495

uint32_t xcc = (reg_offset & XCC_MID_MASK) ? 4 : 0;

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

499

return ((reg_offset >> 16) & 0x3) + xcc;

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

537

misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

539

mes_v12_1_get_rrmt(input->read_reg.reg_offset,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

543

misc_pkt.read_reg.reg_offset =

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

544

soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

549

misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

551

mes_v12_1_get_rrmt(input->write_reg.reg_offset,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

555

misc_pkt.write_reg.reg_offset =

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

556

soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

706

adev->reg_offset[GC_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

708

adev->reg_offset[MMHUB_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

710

adev->reg_offset[OSSSYS_HWIP][0][i];

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

765

if (mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1241

if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1602

if (mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

102

direct_wt->cmd_header.reg_offset = reg_offset;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

109

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

112

direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

121

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

124

direct_poll->cmd_header.reg_offset = reg_offset;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

61

uint32_t reg_offset : 28;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

66

uint32_t reg_offset : 20;

drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

99

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

245

uint32_t reg_offset : 28;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

250

uint32_t reg_offset : 20;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

283

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

286

direct_wt->cmd_header.reg_offset = reg_offset;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

293

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

296

direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

305

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

308

direct_poll->cmd_header.reg_offset = reg_offset;

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

106

direct_wt.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

116

direct_poll.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

56

uint32_t reg_offset : 28;

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

61

uint32_t reg_offset : 20;

drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h

95

direct_rd_mod_wt.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

107

direct_rd_mod_wt.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

118

direct_wt.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

128

direct_poll.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

68

uint32_t reg_offset : 28;

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h

73

uint32_t reg_offset : 20;

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

106

direct_rd_mod_wt.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

117

direct_wt.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

127

direct_poll.cmd_header.reg_offset = reg; \

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

67

uint32_t reg_offset : 28;

drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h

72

uint32_t reg_offset : 20;

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

494

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

497

adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

61

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

63

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

556

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

559

adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

69

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

71

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

34

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

36

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

479

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

482

adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

397

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

400

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

58

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

60

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

293

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

296

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

38

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

40

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

33

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

35

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

369

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

372

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

411

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

414

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

52

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

54

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

104

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

106

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

795

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

798

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

33

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

337

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

340

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

35

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

37

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

39

adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

474

adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

477

adev->rmmio_remap.reg_offset =

drivers/gpu/drm/amd/amdgpu/nv.c

358

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/nv.c

366

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/nv.c

376

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/nv.c

379

return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/nv.c

381

if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))

drivers/gpu/drm/amd/amdgpu/nv.c

383

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/nv.c

388

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/nv.c

396

if (!adev->reg_offset[en->hwip][en->inst])

drivers/gpu/drm/amd/amdgpu/nv.c

398

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

drivers/gpu/drm/amd/amdgpu/nv.c

399

+ en->reg_offset))

drivers/gpu/drm/amd/amdgpu/nv.c

404

se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2389

sdma_reg_list_4_0[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

446

return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

448

return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

450

return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

452

return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

454

return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

456

return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

458

return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

460

return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

167

uint32_t reg_offset,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

177

if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset)

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

202

uint32_t reg_offset = 0;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

204

reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

205

reg_value = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

211

reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

212

reg_value = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

239

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

244

reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

245

WREG32(reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

246

reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

247

WREG32(reg_offset, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

40

uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0];

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

121

return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1652

uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1653

uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2086

sdma_reg_list_4_4_2[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1681

u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1685

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1688

WREG32(reg_offset, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1897

sdma_reg_list_5_0[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

224

base = adev->reg_offset[GC_HWIP][0][1];

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

228

base = adev->reg_offset[GC_HWIP][0][0];

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

125

base = adev->reg_offset[GC_HWIP][0][1];

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

130

base = adev->reg_offset[GC_HWIP][0][0];

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

134

base = adev->reg_offset[GC_HWIP][0][2];

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1588

u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1591

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1594

WREG32(reg_offset, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1899

sdma_reg_list_5_2[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

133

base = adev->reg_offset[GC_HWIP][0][1];

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

137

base = adev->reg_offset[GC_HWIP][0][0];

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1611

u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1614

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1617

WREG32(reg_offset, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1735

sdma_reg_list_6_0[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

132

base = adev->reg_offset[GC_HWIP][0][1];

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

136

base = adev->reg_offset[GC_HWIP][0][0];

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1545

u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1547

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1550

WREG32(reg_offset, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1667

sdma_reg_list_7_0[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

126

base = adev->reg_offset[GC_HWIP][xcc_id][1];

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

130

base = adev->reg_offset[GC_HWIP][xcc_id][0];

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1482

u32 reg_offset = sdma_v7_1_get_reg_offset(adev, type, regSDMA0_SDMA_CNTL);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1484

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1487

WREG32(reg_offset, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1596

sdma_reg_list_7_1[j].reg_offset));

drivers/gpu/drm/amd/amdgpu/si.c

1173

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/si.c

1180

switch (reg_offset) {

drivers/gpu/drm/amd/amdgpu/si.c

1193

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/si.c

1202

switch (reg_offset) {

drivers/gpu/drm/amd/amdgpu/si.c

1239

idx = (reg_offset - mmGB_TILE_MODE0);

drivers/gpu/drm/amd/amdgpu/si.c

1242

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/si.c

1247

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/si.c

1255

if (reg_offset != si_allowed_read_registers[i].reg_offset)

drivers/gpu/drm/amd/amdgpu/si.c

1259

reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

405

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc15.c

413

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

423

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc15.c

426

return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

428

if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))

drivers/gpu/drm/amd/amdgpu/soc15.c

430

else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))

drivers/gpu/drm/amd/amdgpu/soc15.c

432

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

437

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/soc15.c

445

if (!adev->reg_offset[en->hwip][en->inst])

drivers/gpu/drm/amd/amdgpu/soc15.c

447

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

drivers/gpu/drm/amd/amdgpu/soc15.c

448

+ en->reg_offset))

drivers/gpu/drm/amd/amdgpu/soc15.c

453

se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

481

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

drivers/gpu/drm/amd/amdgpu/soc15.h

57

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/soc15.h

64

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/soc15.h

74

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/soc15.h

83

uint32_t reg_offset;

drivers/gpu/drm/amd/amdgpu/soc15.h

94

#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)

drivers/gpu/drm/amd/amdgpu/soc15.h

98

(adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)

drivers/gpu/drm/amd/amdgpu/soc15_common.h

102

(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

107

(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

118

uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

119

uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

120

uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

139

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)

drivers/gpu/drm/amd/amdgpu/soc15_common.h

153

uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

drivers/gpu/drm/amd/amdgpu/soc15_common.h

155

uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

156

uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

157

uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

158

uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

170

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP, inst)

drivers/gpu/drm/amd/amdgpu/soc15_common.h

174

uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

drivers/gpu/drm/amd/amdgpu/soc15_common.h

180

uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\

drivers/gpu/drm/amd/amdgpu/soc15_common.h

185

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

186

(__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

192

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP, inst)

drivers/gpu/drm/amd/amdgpu/soc15_common.h

195

__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst)

drivers/gpu/drm/amd/amdgpu/soc15_common.h

199

RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

203

WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

36

#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

drivers/gpu/drm/amd/amdgpu/soc15_common.h

38

(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))

drivers/gpu/drm/amd/amdgpu/soc15_common.h

51

__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

53

adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

59

__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

61

adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

67

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

75

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

79

__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

83

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

93

__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

97

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \

drivers/gpu/drm/amd/amdgpu/soc21.c

310

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc21.c

318

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc21.c

328

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc21.c

331

return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc21.c

333

if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)

drivers/gpu/drm/amd/amdgpu/soc21.c

335

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc21.c

340

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/soc21.c

348

if (!adev->reg_offset[en->hwip][en->inst])

drivers/gpu/drm/amd/amdgpu/soc21.c

350

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

drivers/gpu/drm/amd/amdgpu/soc21.c

351

+ en->reg_offset))

drivers/gpu/drm/amd/amdgpu/soc21.c

356

se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc24.c

138

u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc24.c

146

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc24.c

156

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc24.c

159

return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc24.c

161

if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&

drivers/gpu/drm/amd/amdgpu/soc24.c

164

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc24.c

169

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/soc24.c

177

if (!adev->reg_offset[en->hwip][en->inst])

drivers/gpu/drm/amd/amdgpu/soc24.c

179

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

drivers/gpu/drm/amd/amdgpu/soc24.c

180

+ en->reg_offset))

drivers/gpu/drm/amd/amdgpu/soc24.c

185

se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

152

u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

160

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

170

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

173

return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

175

if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) &&

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

178

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

184

u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

192

if (!adev->reg_offset[en->hwip][en->inst])

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

194

else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

195

+ en->reg_offset))

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

200

se_num, sh_num, reg_offset);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

295

memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0],

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

300

memcpy(set_hw_resources.osssys_base, adev->reg_offset[OSSSYS_HWIP][0],

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1303

reg -= p->adev->reg_offset[UVD_HWIP][0][1];

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1304

reg += p->adev->reg_offset[UVD_HWIP][1][1];

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

41

adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

42

adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

43

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

44

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

45

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

46

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

47

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

48

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

49

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

50

adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

51

adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

52

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

53

adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

41

adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

42

adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

43

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

44

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

45

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

46

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

47

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

48

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

49

adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

50

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

51

adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

52

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

53

adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vi.c

746

u32 sh_num, u32 reg_offset)

drivers/gpu/drm/amd/amdgpu/vi.c

753

switch (reg_offset) {

drivers/gpu/drm/amd/amdgpu/vi.c

768

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/vi.c

777

switch (reg_offset) {

drivers/gpu/drm/amd/amdgpu/vi.c

814

idx = (reg_offset - mmGB_TILE_MODE0);

drivers/gpu/drm/amd/amdgpu/vi.c

832

idx = (reg_offset - mmGB_MACROTILE_MODE0);

drivers/gpu/drm/amd/amdgpu/vi.c

835

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/vi.c

841

u32 sh_num, u32 reg_offset, u32 *value)

drivers/gpu/drm/amd/amdgpu/vi.c

849

if (reg_offset != vi_allowed_read_registers[i].reg_offset)

drivers/gpu/drm/amd/amdgpu/vi.c

853

reg_offset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

68

base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

300

uint32_t sch_value, uint32_t que_sleep, uint32_t *reg_offset,

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

308

reg_offset,

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

325

uint32_t reg_offset = 0;

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

350

&reg_offset, &reg_data);

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

356

pm_build_dequeue_wait_counts_packet_info(pm, 0, 0, &reg_offset, &reg_data);

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

366

pm_build_dequeue_wait_counts_packet_info(pm, value, 0, &reg_offset, &reg_data);

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

383

packet->bitfields3.dst_mmreg_addr = reg_offset;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1980

init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1981

init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1982

init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];

drivers/gpu/drm/amd/include/kgd_kfd_interface.h

320

uint32_t *reg_offset,

drivers/gpu/drm/amd/include/mes_v11_api_def.h

590

uint32_t reg_offset;

drivers/gpu/drm/amd/include/mes_v11_api_def.h

595

uint32_t reg_offset;

drivers/gpu/drm/amd/include/mes_v12_api_def.h

748

uint32_t reg_offset;

drivers/gpu/drm/amd/include/mes_v12_api_def.h

754

uint32_t reg_offset;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1410

u16 reg_offset, u32 value)

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1414

return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1419

u16 reg_offset, u32 *value)

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1423

return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

1856

u16 reg_offset, u32 value);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3698

u16 reg_offset, u32 *value)

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3703

si_pi->soft_regs_start + reg_offset, value,

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3709

u16 reg_offset, u32 value)

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3714

si_pi->soft_regs_start + reg_offset,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.c

112

reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.c

113

+ entry[i].reg_offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.c

92

reg = entry[i].reg_offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.h

38

uint32_t reg_offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.h

50

uint32_t reg_offset;

drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h

70

__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h

77

__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \

drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c

302

u32 reg_offset = (master_pipe == 0) ?

drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c

305

malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1028

int reg_offset;

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1040

reg_offset = cmdlist->data[index] & ~0xfffff000;

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1041

if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1043

if (reg_offset % 4)

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1046

switch (reg_offset) {

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1056

reg_type = g2d_get_reg_type(g2d, reg_offset);

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1070

reg_type = g2d_get_reg_type(g2d, reg_offset);

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1080

reg_type = g2d_get_reg_type(g2d, reg_offset);

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1092

reg_type = g2d_get_reg_type(g2d, reg_offset);

drivers/gpu/drm/exynos/exynos_drm_g2d.c

1105

reg_type = g2d_get_reg_type(g2d, reg_offset);

drivers/gpu/drm/exynos/exynos_drm_g2d.c

560

static enum g2d_reg_type g2d_get_reg_type(struct g2d_data *g2d, int reg_offset)

drivers/gpu/drm/exynos/exynos_drm_g2d.c

564

switch (reg_offset) {

drivers/gpu/drm/exynos/exynos_drm_g2d.c

594

reg_offset);

drivers/gpu/drm/exynos/exynos_hdmi.c

726

u32 reg_offset, const u8 *buf, u32 len)

drivers/gpu/drm/exynos/exynos_hdmi.c

728

if ((reg_offset + len) > 32)

drivers/gpu/drm/exynos/exynos_hdmi.c

742

((reg_offset + i)<<2));

drivers/gpu/drm/gma500/intel_gmbus.c

256

int i, reg_offset;

drivers/gpu/drm/gma500/intel_gmbus.c

262

reg_offset = 0;

drivers/gpu/drm/gma500/intel_gmbus.c

264

GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);

drivers/gpu/drm/gma500/intel_gmbus.c

271

GMBUS_REG_WRITE(GMBUS1 + reg_offset,

drivers/gpu/drm/gma500/intel_gmbus.c

277

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

281

if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

284

if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

drivers/gpu/drm/gma500/intel_gmbus.c

287

val = GMBUS_REG_READ(GMBUS3 + reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

301

GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);

drivers/gpu/drm/gma500/intel_gmbus.c

302

GMBUS_REG_WRITE(GMBUS1 + reg_offset,

drivers/gpu/drm/gma500/intel_gmbus.c

307

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

310

if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

313

if (GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

322

GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);

drivers/gpu/drm/gma500/intel_gmbus.c

323

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

327

if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))

drivers/gpu/drm/gma500/intel_gmbus.c

329

if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

drivers/gpu/drm/gma500/intel_gmbus.c

340

GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);

drivers/gpu/drm/gma500/intel_gmbus.c

341

GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);

drivers/gpu/drm/gma500/intel_gmbus.c

347

GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);

drivers/gpu/drm/gma500/intel_gmbus.c

353

GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

499

u8 reg_offset = *(data + 5);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

504

vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7);

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

521

payload_data[0] = reg_offset;

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

533

payload_size, reg_offset);

drivers/gpu/drm/loongson/loongson_device.c

43

.reg_offset = LS7A1000_PLL_GFX_REG,

drivers/gpu/drm/loongson/loongson_device.c

48

.reg_offset = LS7A1000_PIXPLL0_REG,

drivers/gpu/drm/loongson/loongson_device.c

52

.reg_offset = LS7A1000_PIXPLL1_REG,

drivers/gpu/drm/loongson/loongson_device.c

75

.reg_offset = LS7A2000_PLL_GFX_REG,

drivers/gpu/drm/loongson/loongson_device.c

80

.reg_offset = LS7A2000_PIXPLL0_REG,

drivers/gpu/drm/loongson/loongson_device.c

84

.reg_offset = LS7A2000_PIXPLL1_REG,

drivers/gpu/drm/loongson/lsdc_drv.h

78

u32 reg_offset;

drivers/gpu/drm/loongson/lsdc_drv.h

84

u32 reg_offset;

drivers/gpu/drm/loongson/lsdc_gfxpll.c

187

this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset;

drivers/gpu/drm/loongson/lsdc_pixpll.c

480

this->reg_base = gfx->conf_reg_base + gfx->pixpll[index].reg_offset;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

834

u32 reg_offset;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

866

reg_offset = (blk->addr - itcm_base) >> 2;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

868

REG_A6XX_GMU_CM3_ITCM_START + reg_offset,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

871

reg_offset = (blk->addr - dtcm_base) >> 2;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

873

REG_A6XX_GMU_CM3_DTCM_START + reg_offset,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

43

u32 reg_offset;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

728

ctl->reg_offset = ctl_cfg->base[c];

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

88

(void)ctl->reg_offset; /* TODO use this instead of mdp5_write */

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

97

(void)ctl->reg_offset; /* TODO use this instead of mdp5_write */

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

156

uint32_t reg_offset, uint32_t caps)

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

166

hwpipe->reg_offset = reg_offset;

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h

20

uint32_t reg_offset;

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h

44

uint32_t reg_offset, uint32_t caps);

drivers/gpu/drm/radeon/ci_dpm.c

1252

u16 reg_offset, u32 *value)

drivers/gpu/drm/radeon/ci_dpm.c

1257

pi->soft_regs_start + reg_offset,

drivers/gpu/drm/radeon/ci_dpm.c

1263

u16 reg_offset, u32 value)

drivers/gpu/drm/radeon/ci_dpm.c

1268

pi->soft_regs_start + reg_offset,

drivers/gpu/drm/radeon/cik.c

2328

u32 reg_offset, split_equal_to_row_size;

drivers/gpu/drm/radeon/cik.c

2350

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2351

tile[reg_offset] = 0;

drivers/gpu/drm/radeon/cik.c

2352

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2353

macrotile[reg_offset] = 0;

drivers/gpu/drm/radeon/cik.c

2493

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2494

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2495

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2496

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2636

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2637

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2638

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2639

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2861

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2862

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

2863

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

2864

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

3004

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

3005

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/cik.c

3006

for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/cik.c

3007

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

drivers/gpu/drm/radeon/cik_sdma.c

251

u32 rb_cntl, reg_offset;

drivers/gpu/drm/radeon/cik_sdma.c

260

reg_offset = SDMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

262

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

263

rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

265

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

drivers/gpu/drm/radeon/cik_sdma.c

266

WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);

drivers/gpu/drm/radeon/cik_sdma.c

305

uint32_t reg_offset, value;

drivers/gpu/drm/radeon/cik_sdma.c

310

reg_offset = SDMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

312

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

313

value = RREG32(SDMA0_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

318

WREG32(SDMA0_CNTL + reg_offset, value);

drivers/gpu/drm/radeon/cik_sdma.c

332

u32 me_cntl, reg_offset;

drivers/gpu/drm/radeon/cik_sdma.c

342

reg_offset = SDMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

344

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

345

me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

350

WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);

drivers/gpu/drm/radeon/cik_sdma.c

369

u32 reg_offset, wb_offset;

drivers/gpu/drm/radeon/cik_sdma.c

375

reg_offset = SDMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

379

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

383

WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);

drivers/gpu/drm/radeon/cik_sdma.c

384

WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);

drivers/gpu/drm/radeon/cik_sdma.c

392

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

drivers/gpu/drm/radeon/cik_sdma.c

395

WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);

drivers/gpu/drm/radeon/cik_sdma.c

396

WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);

drivers/gpu/drm/radeon/cik_sdma.c

399

WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,

drivers/gpu/drm/radeon/cik_sdma.c

401

WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,

drivers/gpu/drm/radeon/cik_sdma.c

407

WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);

drivers/gpu/drm/radeon/cik_sdma.c

408

WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);

drivers/gpu/drm/radeon/cik_sdma.c

411

WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);

drivers/gpu/drm/radeon/cik_sdma.c

414

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);

drivers/gpu/drm/radeon/cik_sdma.c

421

WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);

drivers/gpu/drm/radeon/ni_dma.c

191

u32 reg_offset, wb_offset;

drivers/gpu/drm/radeon/ni_dma.c

197

reg_offset = DMA0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

201

reg_offset = DMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/ni_dma.c

205

WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);

drivers/gpu/drm/radeon/ni_dma.c

206

WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);

drivers/gpu/drm/radeon/ni_dma.c

214

WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);

drivers/gpu/drm/radeon/ni_dma.c

217

WREG32(DMA_RB_RPTR + reg_offset, 0);

drivers/gpu/drm/radeon/ni_dma.c

218

WREG32(DMA_RB_WPTR + reg_offset, 0);

drivers/gpu/drm/radeon/ni_dma.c

221

WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,

drivers/gpu/drm/radeon/ni_dma.c

223

WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,

drivers/gpu/drm/radeon/ni_dma.c

229

WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);

drivers/gpu/drm/radeon/ni_dma.c

236

WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);

drivers/gpu/drm/radeon/ni_dma.c

238

dma_cntl = RREG32(DMA_CNTL + reg_offset);

drivers/gpu/drm/radeon/ni_dma.c

240

WREG32(DMA_CNTL + reg_offset, dma_cntl);

drivers/gpu/drm/radeon/ni_dma.c

243

WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);

drivers/gpu/drm/radeon/ni_dma.c

245

WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);

drivers/gpu/drm/radeon/rv770_dpm.c

237

u16 reg_offset, u32 *value)

drivers/gpu/drm/radeon/rv770_dpm.c

242

pi->soft_regs_start + reg_offset,

drivers/gpu/drm/radeon/rv770_dpm.c

248

u16 reg_offset, u32 value)

drivers/gpu/drm/radeon/rv770_dpm.c

253

pi->soft_regs_start + reg_offset,

drivers/gpu/drm/radeon/rv770_dpm.h

283

u16 reg_offset, u32 value);

drivers/gpu/drm/radeon/si.c

2474

u32 reg_offset, split_equal_to_row_size;

drivers/gpu/drm/radeon/si.c

2489

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/si.c

2490

tile[reg_offset] = 0;

drivers/gpu/drm/radeon/si.c

2703

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/si.c

2704

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/si.c

2918

for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

drivers/gpu/drm/radeon/si.c

2919

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

drivers/gpu/drm/radeon/si_dpm.c

1688

u16 reg_offset, u32 value);

drivers/gpu/drm/radeon/si_dpm.c

3128

u16 reg_offset, u32 *value)

drivers/gpu/drm/radeon/si_dpm.c

3133

si_pi->soft_regs_start + reg_offset, value,

drivers/gpu/drm/radeon/si_dpm.c

3139

u16 reg_offset, u32 value)

drivers/gpu/drm/radeon/si_dpm.c

3144

si_pi->soft_regs_start + reg_offset,

drivers/gpu/host1x/hw/intr_hw.c

114

u32 reg_offset = id / 64;

drivers/gpu/host1x/hw/intr_hw.c

115

u32 irq_index = reg_offset % host->num_syncpt_irqs;

drivers/gpu/host1x/hw/intr_hw.c

14

static void process_32_syncpts(struct host1x *host, unsigned long val, u32 reg_offset)

drivers/gpu/host1x/hw/intr_hw.c

21

host1x_sync_writel(host, val, HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(reg_offset));

drivers/gpu/host1x/hw/intr_hw.c

22

host1x_sync_writel(host, val, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(reg_offset));

drivers/gpu/host1x/hw/intr_hw.c

25

host1x_intr_handle_interrupt(host, reg_offset * 32 + id);

drivers/gpu/host1x/hw/syncpt_hw.c

79

u32 reg_offset = sp->id / 32;

drivers/gpu/host1x/hw/syncpt_hw.c

86

HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));

drivers/hwtracing/coresight/coresight-ctcu-core.c

106

reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset);

drivers/hwtracing/coresight/coresight-ctcu-core.c

107

if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE)

drivers/hwtracing/coresight/coresight-ctcu-core.c

114

ctcu_program_atid_register(drvdata, reg_offset, bit, enable);

drivers/hwtracing/coresight/coresight-ctcu-core.c

67

static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset,

drivers/hwtracing/coresight/coresight-ctcu-core.c

73

val = ctcu_readl(drvdata, reg_offset);

drivers/hwtracing/coresight/coresight-ctcu-core.c

79

ctcu_writel(drvdata, val, reg_offset);

drivers/hwtracing/coresight/coresight-ctcu-core.c

98

u32 atid_offset, reg_offset;

drivers/hwtracing/coresight/coresight-cti-core.c

345

int reg_offset;

drivers/hwtracing/coresight/coresight-cti-core.c

369

reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :

drivers/hwtracing/coresight/coresight-cti-core.c

390

cti_write_single_reg(drvdata, reg_offset, reg_value);

drivers/hwtracing/coresight/coresight-cti-core.c

440

u32 reg_offset;

drivers/hwtracing/coresight/coresight-cti-core.c

454

reg_offset = CTIAPPSET;

drivers/hwtracing/coresight/coresight-cti-core.c

460

reg_offset = CTIAPPCLEAR;

drivers/hwtracing/coresight/coresight-cti-core.c

466

reg_offset = CTIAPPPULSE;

drivers/hwtracing/coresight/coresight-cti-core.c

475

cti_write_single_reg(drvdata, reg_offset, reg_value);

drivers/hwtracing/coresight/coresight-cti-sysfs.c

261

u32 *pcached_val, int reg_offset)

drivers/hwtracing/coresight/coresight-cti-sysfs.c

268

if ((reg_offset >= 0) && cti_active(config)) {

drivers/hwtracing/coresight/coresight-cti-sysfs.c

270

val = readl_relaxed(drvdata->base + reg_offset);

drivers/hwtracing/coresight/coresight-cti-sysfs.c

287

size_t size, u32 *pcached_val, int reg_offset)

drivers/hwtracing/coresight/coresight-cti-sysfs.c

302

if ((reg_offset >= 0) && cti_active(config))

drivers/hwtracing/coresight/coresight-cti-sysfs.c

303

cti_write_single_reg(drvdata, reg_offset, val);

drivers/i2c/busses/i2c-tegra.c

1135

u32 val, reg, dma_burst, reg_offset;

drivers/i2c/busses/i2c-tegra.c

1152

reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);

drivers/i2c/busses/i2c-tegra.c

1154

slv_config.src_addr = i2c_dev->base_phys + reg_offset;

drivers/i2c/busses/i2c-tegra.c

1163

reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);

drivers/i2c/busses/i2c-tegra.c

1165

slv_config.dst_addr = i2c_dev->base_phys + reg_offset;

drivers/iio/adc/ad7606.c

399

ci->reg_offset = 8;

drivers/iio/adc/ad7606.c

414

ci->reg_offset = 0;

drivers/iio/adc/ad7606.c

425

ci->reg_offset = 5;

drivers/iio/adc/ad7606.c

457

ci->reg_offset = 8;

drivers/iio/adc/ad7606.c

473

ci->reg_offset = 0;

drivers/iio/adc/ad7606.c

484

ci->reg_offset = 5;

drivers/iio/adc/ad7606.c

939

ret = st->write_scale(indio_dev, ch, i + ci->reg_offset);

drivers/iio/adc/ad7606.h

105

unsigned int reg_offset;

drivers/infiniband/hw/irdma/ig3rdma_hw.c

140

static void __iomem *__ig3rdma_get_reg_addr(struct irdma_mmio_region *region, u64 reg_offset)

drivers/infiniband/hw/irdma/ig3rdma_hw.c

142

if (reg_offset >= region->offset &&

drivers/infiniband/hw/irdma/ig3rdma_hw.c

143

reg_offset < (region->offset + region->len)) {

drivers/infiniband/hw/irdma/ig3rdma_hw.c

144

reg_offset -= region->offset;

drivers/infiniband/hw/irdma/ig3rdma_hw.c

146

return region->addr + reg_offset;

drivers/infiniband/hw/irdma/ig3rdma_hw.c

152

void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset)

drivers/infiniband/hw/irdma/ig3rdma_hw.c

157

reg_addr = __ig3rdma_get_reg_addr(&hw->rdma_reg, reg_offset);

drivers/infiniband/hw/irdma/ig3rdma_hw.c

162

reg_addr = __ig3rdma_get_reg_addr(&hw->io_regs[i], reg_offset);

drivers/infiniband/hw/irdma/ig3rdma_hw.h

28

void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset);

drivers/infiniband/hw/irdma/irdma.h

173

void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset);

drivers/infiniband/hw/irdma/virtchnl.c

260

(u32 __iomem *)(uintptr_t)reg_array[rindex].reg_offset;

drivers/infiniband/hw/irdma/virtchnl.c

266

reg_array[rindex].reg_offset);

drivers/infiniband/hw/irdma/virtchnl.h

129

u32 reg_offset;

drivers/input/keyboard/omap4-keypad.c

295

keypad_data->reg_offset = 0x00;

drivers/input/keyboard/omap4-keypad.c

299

keypad_data->reg_offset = 0x10;

drivers/input/keyboard/omap4-keypad.c

81

u32 reg_offset;

drivers/input/keyboard/omap4-keypad.c

93

keypad_data->reg_offset + offset);

drivers/input/keyboard/omap4-keypad.c

99

keypad_data->base + keypad_data->reg_offset + offset);

drivers/input/misc/iqs7222.c

1001

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1010

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1019

.reg_offset = 2,

drivers/input/misc/iqs7222.c

1027

.reg_offset = 2,

drivers/input/misc/iqs7222.c

1035

.reg_offset = 2,

drivers/input/misc/iqs7222.c

1043

.reg_offset = 3,

drivers/input/misc/iqs7222.c

1051

.reg_offset = 3,

drivers/input/misc/iqs7222.c

1060

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1069

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1078

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1088

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1097

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1105

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1113

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1121

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1129

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1137

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1145

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1153

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1162

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1170

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1179

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1187

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1195

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1203

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1212

.reg_offset = 9,

drivers/input/misc/iqs7222.c

1222

.reg_offset = 9,

drivers/input/misc/iqs7222.c

1232

.reg_offset = 9,

drivers/input/misc/iqs7222.c

1242

.reg_offset = 9,

drivers/input/misc/iqs7222.c

1252

.reg_offset = 10,

drivers/input/misc/iqs7222.c

1262

.reg_offset = 10,

drivers/input/misc/iqs7222.c

1272

.reg_offset = 10,

drivers/input/misc/iqs7222.c

1282

.reg_offset = 10,

drivers/input/misc/iqs7222.c

1291

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1301

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1311

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1319

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1327

.reg_offset = 2,

drivers/input/misc/iqs7222.c

1335

.reg_offset = 2,

drivers/input/misc/iqs7222.c

1343

.reg_offset = 3,

drivers/input/misc/iqs7222.c

1352

.reg_offset = 3,

drivers/input/misc/iqs7222.c

1361

.reg_offset = 20,

drivers/input/misc/iqs7222.c

1371

.reg_offset = 21,

drivers/input/misc/iqs7222.c

1381

.reg_offset = 21,

drivers/input/misc/iqs7222.c

1391

.reg_offset = 22,

drivers/input/misc/iqs7222.c

1400

.reg_offset = 23,

drivers/input/misc/iqs7222.c

1408

.reg_offset = 0,

drivers/input/misc/iqs7222.c

1415

.reg_offset = 1,

drivers/input/misc/iqs7222.c

1424

.reg_offset = 2,

drivers/input/misc/iqs7222.c

1432

.reg_offset = 3,

drivers/input/misc/iqs7222.c

1440

.reg_offset = 4,

drivers/input/misc/iqs7222.c

1449

.reg_offset = 5,

drivers/input/misc/iqs7222.c

1457

.reg_offset = 6,

drivers/input/misc/iqs7222.c

1466

.reg_offset = 7,

drivers/input/misc/iqs7222.c

1474

.reg_offset = 8,

drivers/input/misc/iqs7222.c

2069

int reg_offset = iqs7222_props[i].reg_offset;

drivers/input/misc/iqs7222.c

2094

setup[reg_offset] |= BIT(reg_shift);

drivers/input/misc/iqs7222.c

2096

setup[reg_offset] &= ~BIT(reg_shift);

drivers/input/misc/iqs7222.c

2104

setup[reg_offset] &= ~BIT(reg_shift);

drivers/input/misc/iqs7222.c

2106

setup[reg_offset] |= BIT(reg_shift);

drivers/input/misc/iqs7222.c

2127

setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,

drivers/input/misc/iqs7222.c

2129

setup[reg_offset] |= (val / val_pitch << reg_shift);

drivers/input/misc/iqs7222.c

2455

int count, error, reg_offset, i;

drivers/input/misc/iqs7222.c

2490

reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;

drivers/input/misc/iqs7222.c

2493

sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);

drivers/input/misc/iqs7222.c

2496

sldr_setup[5 + reg_offset + i] = 0;

drivers/input/misc/iqs7222.c

2510

sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);

drivers/input/misc/iqs7222.c

2511

sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;

drivers/input/misc/iqs7222.c

2514

sldr_setup[4 + reg_offset] = dev_desc->touch_link;

drivers/input/misc/iqs7222.c

2516

sldr_setup[4 + reg_offset] -= 2;

drivers/input/misc/iqs7222.c

2526

if (reg_offset) {

drivers/input/misc/iqs7222.c

2539

if (!(reg_offset ? sldr_setup[3]

drivers/input/misc/iqs7222.c

2548

if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {

drivers/input/misc/iqs7222.c

2554

if (reg_offset) {

drivers/input/misc/iqs7222.c

2570

if (!reg_offset) {

drivers/input/misc/iqs7222.c

2598

if (!reg_offset)

drivers/input/misc/iqs7222.c

2615

if (reg_offset)

drivers/input/misc/iqs7222.c

2634

: sldr_setup[3 + reg_offset],

drivers/input/misc/iqs7222.c

2636

: sldr_setup[4 + reg_offset],

drivers/input/misc/iqs7222.c

2642

if (!reg_offset)

drivers/input/misc/iqs7222.c

2653

if (i && !reg_offset)

drivers/input/misc/iqs7222.c

2655

else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)

drivers/input/misc/iqs7222.c

810

int reg_offset;

drivers/input/misc/iqs7222.c

824

.reg_offset = 0,

drivers/input/misc/iqs7222.c

832

.reg_offset = 0,

drivers/input/misc/iqs7222.c

840

.reg_offset = 1,

drivers/input/misc/iqs7222.c

848

.reg_offset = 1,

drivers/input/misc/iqs7222.c

855

.reg_offset = 1,

drivers/input/misc/iqs7222.c

862

.reg_offset = 1,

drivers/input/misc/iqs7222.c

869

.reg_offset = 1,

drivers/input/misc/iqs7222.c

878

.reg_offset = 2,

drivers/input/misc/iqs7222.c

885

.reg_offset = 2,

drivers/input/misc/iqs7222.c

893

.reg_offset = 2,

drivers/input/misc/iqs7222.c

901

.reg_offset = 0,

drivers/input/misc/iqs7222.c

909

.reg_offset = 0,

drivers/input/misc/iqs7222.c

917

.reg_offset = 1,

drivers/input/misc/iqs7222.c

925

.reg_offset = 1,

drivers/input/misc/iqs7222.c

933

.reg_offset = 2,

drivers/input/misc/iqs7222.c

941

.reg_offset = 0,

drivers/input/misc/iqs7222.c

949

.reg_offset = 0,

drivers/input/misc/iqs7222.c

956

.reg_offset = 0,

drivers/input/misc/iqs7222.c

963

.reg_offset = 0,

drivers/input/misc/iqs7222.c

970

.reg_offset = 0,

drivers/input/misc/iqs7222.c

977

.reg_offset = 0,

drivers/input/misc/iqs7222.c

984

.reg_offset = 0,

drivers/input/misc/iqs7222.c

992

.reg_offset = 1,

drivers/input/touchscreen/edt-ft5x06.c

101

int reg_offset;

drivers/input/touchscreen/edt-ft5x06.c

1025

if (reg_addr->reg_offset != NO_REGISTER)

drivers/input/touchscreen/edt-ft5x06.c

1026

regmap_read(regmap, reg_addr->reg_offset, &tsdata->offset);

drivers/input/touchscreen/edt-ft5x06.c

1075

reg_addr->reg_offset = WORK_REGISTER_OFFSET;

drivers/input/touchscreen/edt-ft5x06.c

1088

reg_addr->reg_offset = M09_REGISTER_OFFSET;

drivers/input/touchscreen/edt-ft5x06.c

1099

reg_addr->reg_offset = NO_REGISTER;

drivers/input/touchscreen/edt-ft5x06.c

1111

reg_addr->reg_offset = M09_REGISTER_OFFSET;

drivers/input/touchscreen/edt-ft5x06.c

591

if (reg_addr->reg_offset != NO_REGISTER)

drivers/input/touchscreen/edt-ft5x06.c

592

regmap_write(regmap, reg_addr->reg_offset, tsdata->offset);

drivers/input/touchscreen/edt-ft5x06.c

997

if (reg_addr->reg_offset != NO_REGISTER)

drivers/input/touchscreen/edt-ft5x06.c

998

regmap_write(regmap, reg_addr->reg_offset, val);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

80

ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS],

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

86

ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK],

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

92

ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR],

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

694

.reg_offset = qcom_smmu_impl0_reg_offset,

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h

24

const u32 *reg_offset;

drivers/irqchip/irq-bcm2836.c

25

static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,

drivers/irqchip/irq-bcm2836.c

29

void __iomem *reg = intc.base + reg_offset + 4 * cpu;

drivers/irqchip/irq-bcm2836.c

34

static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,

drivers/irqchip/irq-bcm2836.c

38

void __iomem *reg = intc.base + reg_offset + 4 * cpu;

drivers/irqchip/irq-gic-v5-irs.c

30

const u32 reg_offset)

drivers/irqchip/irq-gic-v5-irs.c

32

return readl_relaxed(irs_data->irs_base + reg_offset);

drivers/irqchip/irq-gic-v5-irs.c

36

const u32 val, const u32 reg_offset)

drivers/irqchip/irq-gic-v5-irs.c

38

writel_relaxed(val, irs_data->irs_base + reg_offset);

drivers/irqchip/irq-gic-v5-irs.c

42

const u32 reg_offset)

drivers/irqchip/irq-gic-v5-irs.c

44

return readq_relaxed(irs_data->irs_base + reg_offset);

drivers/irqchip/irq-gic-v5-irs.c

48

const u64 val, const u32 reg_offset)

drivers/irqchip/irq-gic-v5-irs.c

50

writeq_relaxed(val, irs_data->irs_base + reg_offset);

drivers/irqchip/irq-gic-v5-its.c

47

static u32 its_readl_relaxed(struct gicv5_its_chip_data *its_node, const u32 reg_offset)

drivers/irqchip/irq-gic-v5-its.c

49

return readl_relaxed(its_node->its_base + reg_offset);

drivers/irqchip/irq-gic-v5-its.c

53

const u32 reg_offset)

drivers/irqchip/irq-gic-v5-its.c

55

writel_relaxed(val, its_node->its_base + reg_offset);

drivers/irqchip/irq-gic-v5-its.c

59

const u32 reg_offset)

drivers/irqchip/irq-gic-v5-its.c

61

writeq_relaxed(val, its_node->its_base + reg_offset);

drivers/irqchip/irq-gic-v5-iwb.c

23

static u32 iwb_readl_relaxed(struct gicv5_iwb_chip_data *iwb_node, const u32 reg_offset)

drivers/irqchip/irq-gic-v5-iwb.c

25

return readl_relaxed(iwb_node->iwb_base + reg_offset);

drivers/irqchip/irq-gic-v5-iwb.c

29

const u32 reg_offset)

drivers/irqchip/irq-gic-v5-iwb.c

31

writel_relaxed(val, iwb_node->iwb_base + reg_offset);

drivers/irqchip/irq-madera.c

24

.reg_offset = (_reg) - MADERA_IRQ1_STATUS_2, \

drivers/irqchip/irq-meson-gpio.c

245

unsigned int reg_offset;

drivers/irqchip/irq-meson-gpio.c

248

reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;

drivers/irqchip/irq-meson-gpio.c

251

meson_gpio_irq_update_bits(ctl, reg_offset,

drivers/irqchip/irq-meson-gpio.c

260

unsigned int reg_offset;

drivers/irqchip/irq-meson-gpio.c

264

reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);

drivers/irqchip/irq-meson-gpio.c

266

meson_gpio_irq_update_bits(ctl, reg_offset,

drivers/irqchip/irq-owl-sirq.c

111

val = readl_relaxed(data->base + data->params->reg_offset[index]);

drivers/irqchip/irq-owl-sirq.c

116

writel_relaxed(extctl, data->base + data->params->reg_offset[index]);

drivers/irqchip/irq-owl-sirq.c

46

u16 reg_offset[NUM_SIRQ];

drivers/irqchip/irq-owl-sirq.c

59

.reg_offset = { 0, 0, 0 },

drivers/irqchip/irq-owl-sirq.c

65

.reg_offset = { INTC_EXTCTL0, INTC_EXTCTL1, INTC_EXTCTL2 },

drivers/irqchip/irq-owl-sirq.c

98

val = readl_relaxed(data->base + data->params->reg_offset[index]);

drivers/leds/blink/leds-bcm63138.c

100

bcm63138_leds_update_bits(leds, BCM63138_FLASH_RATE_CTRL1 + reg_offset,

drivers/leds/blink/leds-bcm63138.c

108

int reg_offset = (led->pin >> fls((BCM63138_LEDS_PER_REG - 1))) * 4;

drivers/leds/blink/leds-bcm63138.c

111

bcm63138_leds_update_bits(leds, BCM63138_BRIGHT_CTRL1 + reg_offset,

drivers/leds/blink/leds-bcm63138.c

97

int reg_offset = (led->pin >> fls((BCM63138_LEDS_PER_REG - 1))) * 4;

drivers/leds/leds-bd2802.c

149

u8 reg_offset)

drivers/leds/leds-bd2802.c

151

return reg_offset + bd2802_get_base_offset(id, color);

drivers/media/platform/arm/mali-c55/mali-c55-capture.c

208

mali_c55_ctx_write(cap_dev->mali_c55, addr + cap_dev->reg_offset, val);

drivers/media/platform/arm/mali-c55/mali-c55-capture.c

213

return mali_c55_ctx_read(cap_dev->mali_c55, addr + cap_dev->reg_offset);

drivers/media/platform/arm/mali-c55/mali-c55-capture.c

785

cap_dev->reg_offset == MALI_C55_CAP_DEV_DS_REG_OFFSET)

drivers/media/platform/arm/mali-c55/mali-c55-capture.c

847

cap_dev->reg_offset = MALI_C55_CAP_DEV_FR_REG_OFFSET;

drivers/media/platform/arm/mali-c55/mali-c55-capture.c

851

cap_dev->reg_offset = MALI_C55_CAP_DEV_DS_REG_OFFSET;

drivers/media/platform/arm/mali-c55/mali-c55-common.h

152

unsigned int reg_offset;

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

12

#define print_wrapper_reg(dev, base_address, reg_offset)\

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

13

internal_print_wrapper_reg(dev, (base_address), #reg_offset,\

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

14

(reg_offset))

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

15

#define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

17

val = readl((base_address) + (reg_offset));\

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

297

.reg_offset = 0,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

309

.reg_offset = 0x2000,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

321

.reg_offset = 0x10000,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

332

.reg_offset = 0x10000,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

343

.reg_offset = 0x0,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

354

.reg_offset = 0,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c

365

.reg_offset = 0,

drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h

171

unsigned int reg_offset;

drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c

761

pipe->regs = isi->regs + id * isi->pdata->reg_offset;

drivers/media/platform/ti/omap3isp/isp.h

285

u32 reg_offset)

drivers/media/platform/ti/omap3isp/isp.h

287

return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);

drivers/media/platform/ti/omap3isp/isp.h

299

enum isp_mem_resources isp_mmio_range, u32 reg_offset)

drivers/media/platform/ti/omap3isp/isp.h

301

__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);

drivers/memory/pl172.c

58

u32 reg_offset, u32 max, int start)

drivers/memory/pl172.c

73

writel(cycles, pl172->base + reg_offset);

drivers/memory/pl172.c

77

readl(pl172->base + reg_offset));

drivers/memory/samsung/exynos-srom.c

132

srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,

drivers/memory/samsung/exynos-srom.c

134

if (!srom->reg_offset)

drivers/memory/samsung/exynos-srom.c

177

exynos_srom_save(srom->reg_base, srom->reg_offset,

drivers/memory/samsung/exynos-srom.c

186

exynos_srom_restore(srom->reg_base, srom->reg_offset,

drivers/memory/samsung/exynos-srom.c

47

struct exynos_srom_reg_dump *reg_offset;

drivers/mfd/88pm800.c

179

.reg_offset = 1,

drivers/mfd/88pm800.c

183

.reg_offset = 1,

drivers/mfd/88pm800.c

187

.reg_offset = 1,

drivers/mfd/88pm800.c

191

.reg_offset = 1,

drivers/mfd/88pm800.c

196

.reg_offset = 2,

drivers/mfd/88pm800.c

200

.reg_offset = 2,

drivers/mfd/88pm800.c

204

.reg_offset = 2,

drivers/mfd/88pm800.c

208

.reg_offset = 2,

drivers/mfd/88pm800.c

212

.reg_offset = 2,

drivers/mfd/88pm800.c

217

.reg_offset = 3,

drivers/mfd/88pm800.c

221

.reg_offset = 3,

drivers/mfd/88pm800.c

225

.reg_offset = 3,

drivers/mfd/88pm800.c

229

.reg_offset = 3,

drivers/mfd/88pm800.c

233

.reg_offset = 3,

drivers/mfd/88pm805.c

102

.reg_offset = 1,

drivers/mfd/88pm805.c

106

.reg_offset = 1,

drivers/mfd/88pm805.c

110

.reg_offset = 1,

drivers/mfd/88pm805.c

114

.reg_offset = 1,

drivers/mfd/88pm805.c

118

.reg_offset = 1,

drivers/mfd/88pm805.c

98

.reg_offset = 1,

drivers/mfd/as3722.c

101

.reg_offset = 1,

drivers/mfd/as3722.c

105

.reg_offset = 1,

drivers/mfd/as3722.c

109

.reg_offset = 1,

drivers/mfd/as3722.c

113

.reg_offset = 1,

drivers/mfd/as3722.c

117

.reg_offset = 1,

drivers/mfd/as3722.c

123

.reg_offset = 2,

drivers/mfd/as3722.c

127

.reg_offset = 2,

drivers/mfd/as3722.c

131

.reg_offset = 2,

drivers/mfd/as3722.c

135

.reg_offset = 2,

drivers/mfd/as3722.c

139

.reg_offset = 2,

drivers/mfd/as3722.c

143

.reg_offset = 2,

drivers/mfd/as3722.c

147

.reg_offset = 2,

drivers/mfd/as3722.c

151

.reg_offset = 2,

drivers/mfd/as3722.c

157

.reg_offset = 3,

drivers/mfd/as3722.c

161

.reg_offset = 3,

drivers/mfd/as3722.c

165

.reg_offset = 3,

drivers/mfd/as3722.c

169

.reg_offset = 3,

drivers/mfd/as3722.c

173

.reg_offset = 3,

drivers/mfd/as3722.c

177

.reg_offset = 3,

drivers/mfd/as3722.c

181

.reg_offset = 3,

drivers/mfd/as3722.c

185

.reg_offset = 3,

drivers/mfd/as3722.c

89

.reg_offset = 1,

drivers/mfd/as3722.c

93

.reg_offset = 1,

drivers/mfd/as3722.c

97

.reg_offset = 1,

drivers/mfd/axp20x.c

487

[_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }

drivers/mfd/cs47l24-tables.c

101

.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1

drivers/mfd/cs47l24-tables.c

104

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1

drivers/mfd/cs47l24-tables.c

107

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1

drivers/mfd/cs47l24-tables.c

111

.reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1

drivers/mfd/cs47l24-tables.c

114

.reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1

drivers/mfd/cs47l24-tables.c

117

.reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1

drivers/mfd/cs47l24-tables.c

120

.reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1

drivers/mfd/cs47l24-tables.c

123

.reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1

drivers/mfd/cs47l24-tables.c

126

.reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1

drivers/mfd/cs47l24-tables.c

129

.reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1

drivers/mfd/cs47l24-tables.c

132

.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1

drivers/mfd/cs47l24-tables.c

135

.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1

drivers/mfd/cs47l24-tables.c

139

.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1

drivers/mfd/cs47l24-tables.c

142

.reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1

drivers/mfd/cs47l24-tables.c

145

.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1

drivers/mfd/cs47l24-tables.c

148

.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1

drivers/mfd/cs47l24-tables.c

152

.reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1

drivers/mfd/cs47l24-tables.c

155

.reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1

drivers/mfd/cs47l24-tables.c

158

.reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1

drivers/mfd/cs47l24-tables.c

161

.reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1

drivers/mfd/cs47l24-tables.c

164

.reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1

drivers/mfd/cs47l24-tables.c

167

.reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1

drivers/mfd/cs47l24-tables.c

36

[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },

drivers/mfd/cs47l24-tables.c

37

[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

drivers/mfd/cs47l24-tables.c

40

.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1

drivers/mfd/cs47l24-tables.c

43

.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1

drivers/mfd/cs47l24-tables.c

46

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1

drivers/mfd/cs47l24-tables.c

49

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1

drivers/mfd/cs47l24-tables.c

52

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1

drivers/mfd/cs47l24-tables.c

55

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1

drivers/mfd/cs47l24-tables.c

58

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1

drivers/mfd/cs47l24-tables.c

61

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1

drivers/mfd/cs47l24-tables.c

64

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1

drivers/mfd/cs47l24-tables.c

67

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1

drivers/mfd/cs47l24-tables.c

71

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1

drivers/mfd/cs47l24-tables.c

74

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1

drivers/mfd/cs47l24-tables.c

77

.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1

drivers/mfd/cs47l24-tables.c

80

.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1

drivers/mfd/cs47l24-tables.c

83

.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1

drivers/mfd/cs47l24-tables.c

86

.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1

drivers/mfd/cs47l24-tables.c

89

.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1

drivers/mfd/cs47l24-tables.c

92

.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1

drivers/mfd/cs47l24-tables.c

95

.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1

drivers/mfd/cs47l24-tables.c

98

.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1

drivers/mfd/da9052-irq.c

101

.reg_offset = 2,

drivers/mfd/da9052-irq.c

105

.reg_offset = 2,

drivers/mfd/da9052-irq.c

109

.reg_offset = 2,

drivers/mfd/da9052-irq.c

113

.reg_offset = 2,

drivers/mfd/da9052-irq.c

117

.reg_offset = 2,

drivers/mfd/da9052-irq.c

121

.reg_offset = 2,

drivers/mfd/da9052-irq.c

125

.reg_offset = 2,

drivers/mfd/da9052-irq.c

129

.reg_offset = 2,

drivers/mfd/da9052-irq.c

133

.reg_offset = 3,

drivers/mfd/da9052-irq.c

137

.reg_offset = 3,

drivers/mfd/da9052-irq.c

141

.reg_offset = 3,

drivers/mfd/da9052-irq.c

145

.reg_offset = 3,

drivers/mfd/da9052-irq.c

149

.reg_offset = 3,

drivers/mfd/da9052-irq.c

153

.reg_offset = 3,

drivers/mfd/da9052-irq.c

157

.reg_offset = 3,

drivers/mfd/da9052-irq.c

161

.reg_offset = 3,

drivers/mfd/da9052-irq.c

37

.reg_offset = 0,

drivers/mfd/da9052-irq.c

41

.reg_offset = 0,

drivers/mfd/da9052-irq.c

45

.reg_offset = 0,

drivers/mfd/da9052-irq.c

49

.reg_offset = 0,

drivers/mfd/da9052-irq.c

53

.reg_offset = 0,

drivers/mfd/da9052-irq.c

57

.reg_offset = 0,

drivers/mfd/da9052-irq.c

61

.reg_offset = 0,

drivers/mfd/da9052-irq.c

65

.reg_offset = 0,

drivers/mfd/da9052-irq.c

69

.reg_offset = 1,

drivers/mfd/da9052-irq.c

73

.reg_offset = 1,

drivers/mfd/da9052-irq.c

77

.reg_offset = 1,

drivers/mfd/da9052-irq.c

81

.reg_offset = 1,

drivers/mfd/da9052-irq.c

85

.reg_offset = 1,

drivers/mfd/da9052-irq.c

89

.reg_offset = 1,

drivers/mfd/da9052-irq.c

93

.reg_offset = 1,

drivers/mfd/da9052-irq.c

97

.reg_offset = 1,

drivers/mfd/da9055-core.c

223

.reg_offset = 0,

drivers/mfd/da9055-core.c

227

.reg_offset = 0,

drivers/mfd/da9055-core.c

231

.reg_offset = 0,

drivers/mfd/da9055-core.c

235

.reg_offset = 0,

drivers/mfd/da9055-core.c

239

.reg_offset = 1,

drivers/mfd/da9062-core.c

103

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

107

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

111

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

116

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

120

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

124

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

128

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

133

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

137

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

141

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

145

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

149

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

31

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

35

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

39

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

44

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

48

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

52

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

56

.reg_offset = DA9062_REG_EVENT_B_OFFSET,

drivers/mfd/da9062-core.c

61

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

65

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

69

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

73

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

77

.reg_offset = DA9062_REG_EVENT_C_OFFSET,

drivers/mfd/da9062-core.c

95

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9062-core.c

99

.reg_offset = DA9062_REG_EVENT_A_OFFSET,

drivers/mfd/da9150-core.c

258

.reg_offset = 0,

drivers/mfd/da9150-core.c

262

.reg_offset = 0,

drivers/mfd/da9150-core.c

266

.reg_offset = 0,

drivers/mfd/da9150-core.c

270

.reg_offset = 0,

drivers/mfd/da9150-core.c

274

.reg_offset = 0,

drivers/mfd/da9150-core.c

278

.reg_offset = 1,

drivers/mfd/da9150-core.c

282

.reg_offset = 1,

drivers/mfd/da9150-core.c

286

.reg_offset = 1,

drivers/mfd/da9150-core.c

290

.reg_offset = 1,

drivers/mfd/da9150-core.c

294

.reg_offset = 1,

drivers/mfd/da9150-core.c

298

.reg_offset = 1,

drivers/mfd/da9150-core.c

302

.reg_offset = 1,

drivers/mfd/da9150-core.c

306

.reg_offset = 2,

drivers/mfd/da9150-core.c

310

.reg_offset = 2,

drivers/mfd/da9150-core.c

314

.reg_offset = 2,

drivers/mfd/da9150-core.c

318

.reg_offset = 2,

drivers/mfd/da9150-core.c

322

.reg_offset = 2,

drivers/mfd/da9150-core.c

326

.reg_offset = 2,

drivers/mfd/da9150-core.c

330

.reg_offset = 2,

drivers/mfd/da9150-core.c

334

.reg_offset = 2,

drivers/mfd/da9150-core.c

338

.reg_offset = 3,

drivers/mfd/hi655x-pmic.c

24

{ .reg_offset = 0, .mask = OTMP_D1R_INT_MASK },

drivers/mfd/hi655x-pmic.c

25

{ .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK },

drivers/mfd/hi655x-pmic.c

26

{ .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK },

drivers/mfd/hi655x-pmic.c

27

{ .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK },

drivers/mfd/hi655x-pmic.c

28

{ .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK },

drivers/mfd/hi655x-pmic.c

29

{ .reg_offset = 0, .mask = PWRON_D20F_INT_MASK },

drivers/mfd/hi655x-pmic.c

30

{ .reg_offset = 0, .mask = PWRON_D20R_INT_MASK },

drivers/mfd/hi655x-pmic.c

31

{ .reg_offset = 0, .mask = RESERVE_INT_MASK },

drivers/mfd/max14577.c

195

{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },

drivers/mfd/max14577.c

196

{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },

drivers/mfd/max14577.c

197

{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },

drivers/mfd/max14577.c

199

{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },

drivers/mfd/max14577.c

200

{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },

drivers/mfd/max14577.c

201

{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },

drivers/mfd/max14577.c

202

{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },

drivers/mfd/max14577.c

203

{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },

drivers/mfd/max14577.c

205

{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },

drivers/mfd/max14577.c

206

{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },

drivers/mfd/max14577.c

207

{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },

drivers/mfd/max14577.c

208

{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },

drivers/mfd/max14577.c

222

{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },

drivers/mfd/max14577.c

223

{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },

drivers/mfd/max14577.c

224

{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },

drivers/mfd/max14577.c

225

{ .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, },

drivers/mfd/max14577.c

227

{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },

drivers/mfd/max14577.c

228

{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },

drivers/mfd/max14577.c

229

{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },

drivers/mfd/max14577.c

230

{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },

drivers/mfd/max14577.c

231

{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },

drivers/mfd/max14577.c

232

{ .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },

drivers/mfd/max14577.c

234

{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },

drivers/mfd/max14577.c

235

{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },

drivers/mfd/max14577.c

236

{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },

drivers/mfd/max14577.c

237

{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },

drivers/mfd/max14577.c

250

{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T120C_MASK, },

drivers/mfd/max14577.c

251

{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T140C_MASK, },

drivers/mfd/max77650.c

99

.reg_offset = MAX77650_INT_GLBL_OFFSET,

drivers/mfd/max77686.c

116

{ .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },

drivers/mfd/max77686.c

117

{ .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },

drivers/mfd/max77686.c

118

{ .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },

drivers/mfd/max77686.c

119

{ .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },

drivers/mfd/max77686.c

120

{ .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },

drivers/mfd/max77686.c

121

{ .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },

drivers/mfd/max77686.c

122

{ .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },

drivers/mfd/max77686.c

123

{ .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },

drivers/mfd/max77686.c

125

{ .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },

drivers/mfd/max77686.c

126

{ .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, },

drivers/mfd/max77693.c

113

{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },

drivers/mfd/max77693.c

114

{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },

drivers/mfd/max77693.c

115

{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },

drivers/mfd/max77693.c

116

{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },

drivers/mfd/max77693.c

118

{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },

drivers/mfd/max77693.c

119

{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },

drivers/mfd/max77693.c

120

{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },

drivers/mfd/max77693.c

121

{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },

drivers/mfd/max77693.c

122

{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },

drivers/mfd/max77693.c

123

{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },

drivers/mfd/max77693.c

125

{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, },

drivers/mfd/max77693.c

126

{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, },

drivers/mfd/max77693.c

127

{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, },

drivers/mfd/max77693.c

128

{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, },

drivers/mfd/max77693.c

129

{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, },

drivers/mfd/max77693.c

130

{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, },

drivers/mfd/max77843.c

52

{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSUVLO_INT, },

drivers/mfd/max77843.c

53

{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSOVLO_INT, },

drivers/mfd/max77843.c

54

{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TSHDN_INT, },

drivers/mfd/max77843.c

55

{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TM_INT, },

drivers/mfd/max8907.c

115

{ .reg_offset = 0, .mask = 1 << 0, },

drivers/mfd/max8907.c

116

{ .reg_offset = 0, .mask = 1 << 1, },

drivers/mfd/max8907.c

117

{ .reg_offset = 0, .mask = 1 << 2, },

drivers/mfd/max8907.c

118

{ .reg_offset = 1, .mask = 1 << 0, },

drivers/mfd/max8907.c

119

{ .reg_offset = 1, .mask = 1 << 1, },

drivers/mfd/max8907.c

120

{ .reg_offset = 1, .mask = 1 << 2, },

drivers/mfd/max8907.c

121

{ .reg_offset = 1, .mask = 1 << 3, },

drivers/mfd/max8907.c

122

{ .reg_offset = 1, .mask = 1 << 4, },

drivers/mfd/max8907.c

123

{ .reg_offset = 1, .mask = 1 << 5, },

drivers/mfd/max8907.c

124

{ .reg_offset = 1, .mask = 1 << 6, },

drivers/mfd/max8907.c

125

{ .reg_offset = 1, .mask = 1 << 7, },

drivers/mfd/max8907.c

140

{ .reg_offset = 0, .mask = 1 << 0, },

drivers/mfd/max8907.c

141

{ .reg_offset = 0, .mask = 1 << 1, },

drivers/mfd/max8907.c

142

{ .reg_offset = 0, .mask = 1 << 2, },

drivers/mfd/max8907.c

143

{ .reg_offset = 0, .mask = 1 << 3, },

drivers/mfd/max8907.c

144

{ .reg_offset = 0, .mask = 1 << 4, },

drivers/mfd/max8907.c

145

{ .reg_offset = 0, .mask = 1 << 5, },

drivers/mfd/max8907.c

146

{ .reg_offset = 0, .mask = 1 << 6, },

drivers/mfd/max8907.c

147

{ .reg_offset = 0, .mask = 1 << 7, },

drivers/mfd/max8907.c

148

{ .reg_offset = 1, .mask = 1 << 0, },

drivers/mfd/max8907.c

149

{ .reg_offset = 1, .mask = 1 << 1, },

drivers/mfd/max8907.c

163

{ .reg_offset = 0, .mask = 1 << 2, },

drivers/mfd/max8907.c

164

{ .reg_offset = 0, .mask = 1 << 3, },

drivers/mfd/mc13xxx-core.c

443

mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;

drivers/mfd/motorola-cpcap.c

126

unsigned int reg_offset;

drivers/mfd/motorola-cpcap.c

129

reg_offset = irq - irq_base;

drivers/mfd/motorola-cpcap.c

130

reg_offset /= cpcap->regmap_conf->val_bits;

drivers/mfd/motorola-cpcap.c

131

reg_offset *= cpcap->regmap_conf->reg_stride;

drivers/mfd/motorola-cpcap.c

136

rirq->reg_offset = reg_offset;

drivers/mfd/palmas.c

102

.reg_offset = 1,

drivers/mfd/palmas.c

107

.reg_offset = 2,

drivers/mfd/palmas.c

111

.reg_offset = 2,

drivers/mfd/palmas.c

115

.reg_offset = 2,

drivers/mfd/palmas.c

119

.reg_offset = 2,

drivers/mfd/palmas.c

123

.reg_offset = 2,

drivers/mfd/palmas.c

127

.reg_offset = 2,

drivers/mfd/palmas.c

131

.reg_offset = 2,

drivers/mfd/palmas.c

135

.reg_offset = 2,

drivers/mfd/palmas.c

140

.reg_offset = 3,

drivers/mfd/palmas.c

144

.reg_offset = 3,

drivers/mfd/palmas.c

148

.reg_offset = 3,

drivers/mfd/palmas.c

152

.reg_offset = 3,

drivers/mfd/palmas.c

156

.reg_offset = 3,

drivers/mfd/palmas.c

160

.reg_offset = 3,

drivers/mfd/palmas.c

164

.reg_offset = 3,

drivers/mfd/palmas.c

168

.reg_offset = 3,

drivers/mfd/palmas.c

201

.reg_offset = 1,

drivers/mfd/palmas.c

205

.reg_offset = 1,

drivers/mfd/palmas.c

209

.reg_offset = 1,

drivers/mfd/palmas.c

213

.reg_offset = 1,

drivers/mfd/palmas.c

217

.reg_offset = 1,

drivers/mfd/palmas.c

221

.reg_offset = 1,

drivers/mfd/palmas.c

225

.reg_offset = 1,

drivers/mfd/palmas.c

229

.reg_offset = 1,

drivers/mfd/palmas.c

234

.reg_offset = 2,

drivers/mfd/palmas.c

238

.reg_offset = 2,

drivers/mfd/palmas.c

242

.reg_offset = 2,

drivers/mfd/palmas.c

246

.reg_offset = 2,

drivers/mfd/palmas.c

250

.reg_offset = 2,

drivers/mfd/palmas.c

254

.reg_offset = 2,

drivers/mfd/palmas.c

258

.reg_offset = 2,

drivers/mfd/palmas.c

262

.reg_offset = 2,

drivers/mfd/palmas.c

267

.reg_offset = 3,

drivers/mfd/palmas.c

271

.reg_offset = 3,

drivers/mfd/palmas.c

275

.reg_offset = 3,

drivers/mfd/palmas.c

279

.reg_offset = 3,

drivers/mfd/palmas.c

283

.reg_offset = 3,

drivers/mfd/palmas.c

287

.reg_offset = 3,

drivers/mfd/palmas.c

291

.reg_offset = 3,

drivers/mfd/palmas.c

295

.reg_offset = 3,

drivers/mfd/palmas.c

351

reg_add += pmic_ddata->sleep_req_info[id].reg_offset;

drivers/mfd/palmas.c

74

.reg_offset = 1,

drivers/mfd/palmas.c

78

.reg_offset = 1,

drivers/mfd/palmas.c

82

.reg_offset = 1,

drivers/mfd/palmas.c

86

.reg_offset = 1,

drivers/mfd/palmas.c

90

.reg_offset = 1,

drivers/mfd/palmas.c

94

.reg_offset = 1,

drivers/mfd/palmas.c

98

.reg_offset = 1,

drivers/mfd/qcom-pm8008.c

72

.reg_offset = (_off), \

drivers/mfd/rk8xx-core.c

312

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

316

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

320

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

324

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

328

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

332

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

336

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

343

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

347

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

351

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

355

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

359

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

363

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

367

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

371

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

400

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

404

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

408

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

412

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

416

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

420

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

424

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

430

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

434

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

495

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

499

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

503

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

507

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

511

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

515

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

519

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

523

.reg_offset = 0,

drivers/mfd/rk8xx-core.c

529

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

533

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

537

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

541

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

545

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

549

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

553

.reg_offset = 1,

drivers/mfd/rk8xx-core.c

557

.reg_offset = 1,

drivers/mfd/rohm-bd71828.c

26

.reg_offset = (_stat_offset), \

drivers/mfd/tps65090.c

102

.reg_offset = 1,

drivers/mfd/tps65090.c

106

.reg_offset = 1,

drivers/mfd/tps65090.c

110

.reg_offset = 1,

drivers/mfd/tps65090.c

114

.reg_offset = 1,

drivers/mfd/tps65090.c

118

.reg_offset = 1,

drivers/mfd/tps65090.c

90

.reg_offset = 1,

drivers/mfd/tps65090.c

94

.reg_offset = 1,

drivers/mfd/tps65090.c

98

.reg_offset = 1,

drivers/mfd/tps65218.c

161

.reg_offset = 1,

drivers/mfd/tps65218.c

165

.reg_offset = 1,

drivers/mfd/tps65218.c

169

.reg_offset = 1,

drivers/mfd/tps65218.c

173

.reg_offset = 1,

drivers/mfd/tps65218.c

177

.reg_offset = 1,

drivers/mfd/tps65218.c

181

.reg_offset = 1,

drivers/mfd/tps65910.c

100

.reg_offset = 1,

drivers/mfd/tps65910.c

104

.reg_offset = 1,

drivers/mfd/tps65910.c

108

.reg_offset = 1,

drivers/mfd/tps65910.c

112

.reg_offset = 1,

drivers/mfd/tps65910.c

116

.reg_offset = 1,

drivers/mfd/tps65910.c

122

.reg_offset = 2,

drivers/mfd/tps65910.c

126

.reg_offset = 2,

drivers/mfd/tps65910.c

130

.reg_offset = 2,

drivers/mfd/tps65910.c

134

.reg_offset = 2,

drivers/mfd/tps65910.c

138

.reg_offset = 2,

drivers/mfd/tps65910.c

142

.reg_offset = 2,

drivers/mfd/tps65910.c

146

.reg_offset = 2,

drivers/mfd/tps65910.c

150

.reg_offset = 2,

drivers/mfd/tps65910.c

158

.reg_offset = 0,

drivers/mfd/tps65910.c

162

.reg_offset = 0,

drivers/mfd/tps65910.c

166

.reg_offset = 0,

drivers/mfd/tps65910.c

170

.reg_offset = 0,

drivers/mfd/tps65910.c

174

.reg_offset = 0,

drivers/mfd/tps65910.c

178

.reg_offset = 0,

drivers/mfd/tps65910.c

182

.reg_offset = 0,

drivers/mfd/tps65910.c

186

.reg_offset = 0,

drivers/mfd/tps65910.c

192

.reg_offset = 1,

drivers/mfd/tps65910.c

196

.reg_offset = 1,

drivers/mfd/tps65910.c

54

.reg_offset = 0,

drivers/mfd/tps65910.c

58

.reg_offset = 0,

drivers/mfd/tps65910.c

62

.reg_offset = 0,

drivers/mfd/tps65910.c

66

.reg_offset = 0,

drivers/mfd/tps65910.c

70

.reg_offset = 0,

drivers/mfd/tps65910.c

74

.reg_offset = 0,

drivers/mfd/tps65910.c

78

.reg_offset = 0,

drivers/mfd/tps65910.c

82

.reg_offset = 0,

drivers/mfd/tps65910.c

88

.reg_offset = 1,

drivers/mfd/tps65910.c

92

.reg_offset = 1,

drivers/mfd/tps65910.c

96

.reg_offset = 1,

drivers/mfd/twl6040.c

615

{ .reg_offset = 0, .mask = TWL6040_THINT, },

drivers/mfd/twl6040.c

616

{ .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },

drivers/mfd/twl6040.c

617

{ .reg_offset = 0, .mask = TWL6040_HOOKINT, },

drivers/mfd/twl6040.c

618

{ .reg_offset = 0, .mask = TWL6040_HFINT, },

drivers/mfd/twl6040.c

619

{ .reg_offset = 0, .mask = TWL6040_VIBINT, },

drivers/mfd/twl6040.c

620

{ .reg_offset = 0, .mask = TWL6040_READYINT, },

drivers/mfd/wcd934x.c

21

.reg_offset = (_off), \

drivers/mfd/wm5102-tables.c

124

[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },

drivers/mfd/wm5102-tables.c

125

[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },

drivers/mfd/wm5102-tables.c

126

[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },

drivers/mfd/wm5102-tables.c

127

[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

drivers/mfd/wm5102-tables.c

130

.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1

drivers/mfd/wm5102-tables.c

133

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1

drivers/mfd/wm5102-tables.c

136

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1

drivers/mfd/wm5102-tables.c

140

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1

drivers/mfd/wm5102-tables.c

143

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1

drivers/mfd/wm5102-tables.c

146

.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1

drivers/mfd/wm5102-tables.c

149

.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1

drivers/mfd/wm5102-tables.c

152

.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1

drivers/mfd/wm5102-tables.c

155

.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1

drivers/mfd/wm5102-tables.c

158

.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1

drivers/mfd/wm5102-tables.c

161

.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1

drivers/mfd/wm5102-tables.c

164

.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1

drivers/mfd/wm5102-tables.c

167

.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1

drivers/mfd/wm5102-tables.c

170

.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1

drivers/mfd/wm5102-tables.c

173

.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1

drivers/mfd/wm5102-tables.c

176

.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1

drivers/mfd/wm5102-tables.c

179

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1

drivers/mfd/wm5102-tables.c

182

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1

drivers/mfd/wm5102-tables.c

186

.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1

drivers/mfd/wm5102-tables.c

189

.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1

drivers/mfd/wm5102-tables.c

192

.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1

drivers/mfd/wm5102-tables.c

195

.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1

drivers/mfd/wm5102-tables.c

198

.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1

drivers/mfd/wm5102-tables.c

201

.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1

drivers/mfd/wm5102-tables.c

204

.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1

drivers/mfd/wm5102-tables.c

207

.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1

drivers/mfd/wm5102-tables.c

210

.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1

drivers/mfd/wm5102-tables.c

213

.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1

drivers/mfd/wm5102-tables.c

217

.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1

drivers/mfd/wm5102-tables.c

220

.reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1

drivers/mfd/wm5102-tables.c

223

.reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1

drivers/mfd/wm5102-tables.c

226

.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1

drivers/mfd/wm5102-tables.c

229

.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1

drivers/mfd/wm5110-tables.c

310

[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },

drivers/mfd/wm5110-tables.c

311

[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },

drivers/mfd/wm5110-tables.c

312

[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },

drivers/mfd/wm5110-tables.c

313

[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

drivers/mfd/wm5110-tables.c

316

.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

319

.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

322

.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

325

.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

328

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1

drivers/mfd/wm5110-tables.c

331

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1

drivers/mfd/wm5110-tables.c

334

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1

drivers/mfd/wm5110-tables.c

337

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1

drivers/mfd/wm5110-tables.c

340

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1

drivers/mfd/wm5110-tables.c

343

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1

drivers/mfd/wm5110-tables.c

346

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1

drivers/mfd/wm5110-tables.c

349

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1

drivers/mfd/wm5110-tables.c

353

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1

drivers/mfd/wm5110-tables.c

356

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1

drivers/mfd/wm5110-tables.c

359

.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1

drivers/mfd/wm5110-tables.c

362

.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1

drivers/mfd/wm5110-tables.c

365

.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1

drivers/mfd/wm5110-tables.c

368

.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1

drivers/mfd/wm5110-tables.c

371

.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1

drivers/mfd/wm5110-tables.c

374

.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1

drivers/mfd/wm5110-tables.c

377

.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1

drivers/mfd/wm5110-tables.c

380

.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1

drivers/mfd/wm5110-tables.c

383

.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1

drivers/mfd/wm5110-tables.c

386

.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1

drivers/mfd/wm5110-tables.c

389

.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1

drivers/mfd/wm5110-tables.c

392

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1

drivers/mfd/wm5110-tables.c

395

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1

drivers/mfd/wm5110-tables.c

399

.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

402

.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1

drivers/mfd/wm5110-tables.c

405

.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1

drivers/mfd/wm5110-tables.c

408

.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1

drivers/mfd/wm5110-tables.c

411

.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1

drivers/mfd/wm5110-tables.c

414

.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1

drivers/mfd/wm5110-tables.c

417

.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1

drivers/mfd/wm5110-tables.c

420

.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1

drivers/mfd/wm5110-tables.c

423

.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

426

.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

429

.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1

drivers/mfd/wm5110-tables.c

432

.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1

drivers/mfd/wm5110-tables.c

435

.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1

drivers/mfd/wm5110-tables.c

438

.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1

drivers/mfd/wm5110-tables.c

441

.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1

drivers/mfd/wm5110-tables.c

444

.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1

drivers/mfd/wm5110-tables.c

448

.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1

drivers/mfd/wm5110-tables.c

451

.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1

drivers/mfd/wm5110-tables.c

454

.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1

drivers/mfd/wm5110-tables.c

470

[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },

drivers/mfd/wm5110-tables.c

471

[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },

drivers/mfd/wm5110-tables.c

472

[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },

drivers/mfd/wm5110-tables.c

473

[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

drivers/mfd/wm5110-tables.c

476

.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

479

.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

482

.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

485

.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1

drivers/mfd/wm5110-tables.c

488

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1

drivers/mfd/wm5110-tables.c

491

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1

drivers/mfd/wm5110-tables.c

494

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1

drivers/mfd/wm5110-tables.c

497

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1

drivers/mfd/wm5110-tables.c

500

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1

drivers/mfd/wm5110-tables.c

503

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1

drivers/mfd/wm5110-tables.c

506

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1

drivers/mfd/wm5110-tables.c

509

.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1

drivers/mfd/wm5110-tables.c

513

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1

drivers/mfd/wm5110-tables.c

516

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1

drivers/mfd/wm5110-tables.c

519

.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1

drivers/mfd/wm5110-tables.c

522

.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1

drivers/mfd/wm5110-tables.c

525

.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1

drivers/mfd/wm5110-tables.c

528

.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1

drivers/mfd/wm5110-tables.c

531

.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1

drivers/mfd/wm5110-tables.c

534

.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1

drivers/mfd/wm5110-tables.c

537

.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1

drivers/mfd/wm5110-tables.c

540

.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1

drivers/mfd/wm5110-tables.c

543

.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1

drivers/mfd/wm5110-tables.c

546

.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1

drivers/mfd/wm5110-tables.c

549

.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1

drivers/mfd/wm5110-tables.c

552

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1

drivers/mfd/wm5110-tables.c

555

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1

drivers/mfd/wm5110-tables.c

559

.reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1

drivers/mfd/wm5110-tables.c

562

.reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1

drivers/mfd/wm5110-tables.c

565

.reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1

drivers/mfd/wm5110-tables.c

568

.reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1

drivers/mfd/wm5110-tables.c

571

.reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

574

.reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

577

.reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

580

.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1

drivers/mfd/wm5110-tables.c

583

.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1

drivers/mfd/wm5110-tables.c

586

.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1

drivers/mfd/wm5110-tables.c

589

.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1

drivers/mfd/wm5110-tables.c

592

.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1

drivers/mfd/wm5110-tables.c

595

.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1

drivers/mfd/wm5110-tables.c

599

.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1

drivers/mfd/wm5110-tables.c

602

.reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1

drivers/mfd/wm5110-tables.c

605

.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1

drivers/mfd/wm5110-tables.c

608

.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1

drivers/mfd/wm5110-tables.c

612

.reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1

drivers/mfd/wm5110-tables.c

615

.reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1

drivers/mfd/wm5110-tables.c

618

.reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1

drivers/mfd/wm5110-tables.c

621

.reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1

drivers/mfd/wm5110-tables.c

624

.reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1

drivers/mfd/wm5110-tables.c

627

.reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1

drivers/mfd/wm5110-tables.c

630

.reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1

drivers/mfd/wm5110-tables.c

633

.reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1

drivers/mfd/wm5110-tables.c

636

.reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1

drivers/mfd/wm5110-tables.c

639

.reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1

drivers/mfd/wm5110-tables.c

642

.reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1

drivers/mfd/wm5110-tables.c

645

.reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1

drivers/mfd/wm5110-tables.c

648

.reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1

drivers/mfd/wm5110-tables.c

651

.reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1

drivers/mfd/wm5110-tables.c

654

.reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1

drivers/mfd/wm5110-tables.c

657

.reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1

drivers/mfd/wm8994-irq.c

28

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

32

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

36

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

40

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

44

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

48

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

52

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

56

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

60

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

64

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

68

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

72

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

76

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

80

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

84

.reg_offset = 1,

drivers/mfd/wm8994-irq.c

88

.reg_offset = 1,

drivers/mfd/wm8997-tables.c

103

.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1

drivers/mfd/wm8997-tables.c

106

.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1

drivers/mfd/wm8997-tables.c

109

.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1

drivers/mfd/wm8997-tables.c

112

.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1

drivers/mfd/wm8997-tables.c

115

.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1

drivers/mfd/wm8997-tables.c

118

.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1

drivers/mfd/wm8997-tables.c

121

.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1

drivers/mfd/wm8997-tables.c

124

.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1

drivers/mfd/wm8997-tables.c

128

.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1

drivers/mfd/wm8997-tables.c

131

.reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1

drivers/mfd/wm8997-tables.c

134

.reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1

drivers/mfd/wm8997-tables.c

137

.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1

drivers/mfd/wm8997-tables.c

140

.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1

drivers/mfd/wm8997-tables.c

60

[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },

drivers/mfd/wm8997-tables.c

61

[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },

drivers/mfd/wm8997-tables.c

62

[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },

drivers/mfd/wm8997-tables.c

63

[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

drivers/mfd/wm8997-tables.c

66

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1

drivers/mfd/wm8997-tables.c

69

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1

drivers/mfd/wm8997-tables.c

72

.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1

drivers/mfd/wm8997-tables.c

75

.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1

drivers/mfd/wm8997-tables.c

78

.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1

drivers/mfd/wm8997-tables.c

81

.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1

drivers/mfd/wm8997-tables.c

84

.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1

drivers/mfd/wm8997-tables.c

87

.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1

drivers/mfd/wm8997-tables.c

90

.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1

drivers/mfd/wm8997-tables.c

93

.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1

drivers/mfd/wm8997-tables.c

96

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1

drivers/mfd/wm8997-tables.c

99

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1

drivers/mfd/wm8998-tables.c

100

.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1

drivers/mfd/wm8998-tables.c

103

.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1

drivers/mfd/wm8998-tables.c

106

.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1

drivers/mfd/wm8998-tables.c

109

.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1

drivers/mfd/wm8998-tables.c

112

.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1

drivers/mfd/wm8998-tables.c

115

.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1

drivers/mfd/wm8998-tables.c

118

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1

drivers/mfd/wm8998-tables.c

121

.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1

drivers/mfd/wm8998-tables.c

125

.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1

drivers/mfd/wm8998-tables.c

128

.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1

drivers/mfd/wm8998-tables.c

131

.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1

drivers/mfd/wm8998-tables.c

134

.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1

drivers/mfd/wm8998-tables.c

137

.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1

drivers/mfd/wm8998-tables.c

140

.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1

drivers/mfd/wm8998-tables.c

143

.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1

drivers/mfd/wm8998-tables.c

146

.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1

drivers/mfd/wm8998-tables.c

149

.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1

drivers/mfd/wm8998-tables.c

152

.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1

drivers/mfd/wm8998-tables.c

156

.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1

drivers/mfd/wm8998-tables.c

159

.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1

drivers/mfd/wm8998-tables.c

162

.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1

drivers/mfd/wm8998-tables.c

76

[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },

drivers/mfd/wm8998-tables.c

77

[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },

drivers/mfd/wm8998-tables.c

78

[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },

drivers/mfd/wm8998-tables.c

79

[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },

drivers/mfd/wm8998-tables.c

82

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1

drivers/mfd/wm8998-tables.c

85

.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1

drivers/mfd/wm8998-tables.c

88

.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1

drivers/mfd/wm8998-tables.c

91

.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1

drivers/mfd/wm8998-tables.c

94

.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1

drivers/mfd/wm8998-tables.c

97

.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1

drivers/misc/amd-sbi/rmi-core.c

60

u8 reg_offset[4]; /* input value */

drivers/misc/amd-sbi/rmi-core.c

74

u8 reg_offset[4]; /* input value */

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

84

static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset,

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

89

data = readl(base_addr + reg_offset);

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

94

writel(data, base_addr + reg_offset);

drivers/misc/xilinx_sdfec.c

252

u32 reg_offset, u32 bit_num,

drivers/misc/xilinx_sdfec.c

258

reg_val = xsdfec_regread(xsdfec, reg_offset);

drivers/mmc/host/dw_mmc-pltfm.c

74

u32 clk_phase[2] = {0}, reg_offset, reg_shift;

drivers/mmc/host/dw_mmc-pltfm.c

87

of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);

drivers/mmc/host/dw_mmc-pltfm.c

94

regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);

drivers/mmc/host/omap_hsmmc.c

1694

.reg_offset = 0x100,

drivers/mmc/host/omap_hsmmc.c

1697

.reg_offset = 0x100,

drivers/mmc/host/omap_hsmmc.c

1781

pdata->reg_offset = data->reg_offset;

drivers/mmc/host/omap_hsmmc.c

1814

host->mapbase = res->start + pdata->reg_offset;

drivers/mmc/host/omap_hsmmc.c

1815

host->base = base + pdata->reg_offset;

drivers/mmc/host/omap_hsmmc.c

210

u32 reg_offset;

drivers/mtd/nand/raw/cadence-nand-controller.c

611

u32 reg_offset, u32 timeout_us,

drivers/mtd/nand/raw/cadence-nand-controller.c

617

ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset,

drivers/mtd/nand/raw/cadence-nand-controller.c

624

reg_offset, mask, is_clear);

drivers/mtd/nand/raw/rockchip-nand-controller.c

336

int reg_offset = nfc->band_offset;

drivers/mtd/nand/raw/rockchip-nand-controller.c

348

nfc->regs + reg_offset + BANK_CMD);

drivers/mtd/nand/raw/rockchip-nand-controller.c

357

nfc->regs + reg_offset + BANK_ADDR);

drivers/net/ethernet/8390/8390.h

103

u32 *reg_offset; /* Register mapping table */

drivers/net/ethernet/8390/ax88796.c

53

#define EI_SHIFT(x) (ei_local->reg_offset[(x)])

drivers/net/ethernet/8390/ax88796.c

895

ei_local->reg_offset = ax->plat->reg_offsets;

drivers/net/ethernet/8390/ax88796.c

897

ei_local->reg_offset = ax->reg_offsets;

drivers/net/ethernet/8390/ax88796.c

941

ei_local->reg_offset[0x1f] = ax->map2 - ei_local->mem;

drivers/net/ethernet/8390/etherh.c

49

#define EI_SHIFT(x) (ei_local->reg_offset[x])

drivers/net/ethernet/8390/etherh.c

729

ei_local->reg_offset = etherm_regoffsets;

drivers/net/ethernet/8390/etherh.c

732

ei_local->reg_offset = etherh_regoffsets;

drivers/net/ethernet/8390/hydra.c

161

ei_status.reg_offset = hydra_offsets;

drivers/net/ethernet/8390/hydra.c

31

#define EI_SHIFT(x) (ei_local->reg_offset[x])

drivers/net/ethernet/8390/mac8390.c

45

#define EI_SHIFT(x) (ei_local->reg_offset[x])

drivers/net/ethernet/8390/mac8390.c

540

ei_status.reg_offset = back4_offsets;

drivers/net/ethernet/8390/mac8390.c

549

ei_status.reg_offset = back4_offsets;

drivers/net/ethernet/8390/mac8390.c

564

ei_status.reg_offset = back4_offsets;

drivers/net/ethernet/8390/mac8390.c

573

ei_status.reg_offset = fwrd2_offsets;

drivers/net/ethernet/8390/mac8390.c

584

ei_status.reg_offset = fwrd4_offsets;

drivers/net/ethernet/8390/mac8390.c

593

ei_status.reg_offset = fwrd4_offsets;

drivers/net/ethernet/8390/mcf8390.c

388

ei_local->reg_offset = offsets;

drivers/net/ethernet/8390/xsurf100.c

38

#define EI_SHIFT(x) (ei_local->reg_offset[(x)])

drivers/net/ethernet/8390/zorro8390.c

33

#define EI_SHIFT(x) (ei_local->reg_offset[x])

drivers/net/ethernet/8390/zorro8390.c

377

ei_status.reg_offset = zorro8390_offsets;

drivers/net/ethernet/apple/bmac.c

1517

bmread(bmac_devs, reg_entries[i].reg_offset));

drivers/net/ethernet/apple/bmac.c

208

void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )

drivers/net/ethernet/apple/bmac.c

210

out_le16((void __iomem *)dev->base_addr + reg_offset, data);

drivers/net/ethernet/apple/bmac.c

215

unsigned short bmread(struct net_device *dev, unsigned long reg_offset )

drivers/net/ethernet/apple/bmac.c

217

return in_le16((void __iomem *)dev->base_addr + reg_offset);

drivers/net/ethernet/apple/bmac.c

88

unsigned short reg_offset;

drivers/net/ethernet/broadcom/asp2/bcmasp.c

239

int reg_offset;

drivers/net/ethernet/broadcom/asp2/bcmasp.c

245

reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type,

drivers/net/ethernet/broadcom/asp2/bcmasp.c

248

rx_filter_core_wl(priv, val, reg_offset);

drivers/net/ethernet/broadcom/asp2/bcmasp.c

256

int reg_offset;

drivers/net/ethernet/broadcom/asp2/bcmasp.c

262

reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type,

drivers/net/ethernet/broadcom/asp2/bcmasp.c

265

return rx_filter_core_rl(priv, reg_offset);

drivers/net/ethernet/broadcom/asp2/bcmasp_ethtool.c

104

offset = s->reg_offset;

drivers/net/ethernet/broadcom/asp2/bcmasp_ethtool.c

21

u32 reg_offset;

drivers/net/ethernet/broadcom/asp2/bcmasp_ethtool.c

32

.reg_offset = offset, \

drivers/net/ethernet/broadcom/bcmsysport.c

399

val = rxchk_readl(priv, s->reg_offset);

drivers/net/ethernet/broadcom/bcmsysport.c

401

rxchk_writel(priv, 0, s->reg_offset);

drivers/net/ethernet/broadcom/bcmsysport.c

404

val = rbuf_readl(priv, s->reg_offset);

drivers/net/ethernet/broadcom/bcmsysport.c

406

rbuf_writel(priv, 0, s->reg_offset);

drivers/net/ethernet/broadcom/bcmsysport.c

412

val = rdma_readl(priv, s->reg_offset);

drivers/net/ethernet/broadcom/bcmsysport.c

414

rdma_writel(priv, 0, s->reg_offset);

drivers/net/ethernet/broadcom/bcmsysport.h

622

.reg_offset = ofs, \

drivers/net/ethernet/broadcom/bcmsysport.h

630

.reg_offset = ofs, \

drivers/net/ethernet/broadcom/bcmsysport.h

638

.reg_offset = ofs, \

drivers/net/ethernet/broadcom/bcmsysport.h

650

u16 reg_offset;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4167

int reg_offset;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4170

reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4175

val = REG_RD(bp, reg_offset);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4177

REG_WR(bp, reg_offset, val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4194

val = REG_RD(bp, reg_offset);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4196

REG_WR(bp, reg_offset, val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4220

int reg_offset;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4222

reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4225

val = REG_RD(bp, reg_offset);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4227

REG_WR(bp, reg_offset, val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4264

int reg_offset;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4266

reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4269

val = REG_RD(bp, reg_offset);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

4271

REG_WR(bp, reg_offset, val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

6046

int reg_offset, reg_offset_en5;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

6067

reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

6076

REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

6091

reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

6094

REG_WR(bp, reg_offset, U64_LO(section));

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

6095

REG_WR(bp, reg_offset + 4, U64_HI(section));

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c

806

u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c

820

reg_offset += 8*index;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c

826

REG_WR_DMAE(bp, reg_offset, wb_data, 2);

drivers/net/ethernet/broadcom/genet/bcmgenet.c

1023

.reg_offset = offset, \

drivers/net/ethernet/broadcom/genet/bcmgenet.c

1285

val = bcmgenet_umac_readl(priv, s->reg_offset);

drivers/net/ethernet/broadcom/genet/bcmgenet.c

1289

s->reg_offset);

drivers/net/ethernet/broadcom/genet/bcmgenet.c

1292

s->reg_offset);

drivers/net/ethernet/broadcom/genet/bcmgenet.c

986

u16 reg_offset;

drivers/net/ethernet/brocade/bna/bna_hw_defs.h

74

struct bna_reg_offset reg_offset[] = \

drivers/net/ethernet/brocade/bna/bna_hw_defs.h

81

reg_offset[(_pcidev)->pci_func].fn_int_status;\

drivers/net/ethernet/brocade/bna/bna_hw_defs.h

83

reg_offset[(_pcidev)->pci_func].fn_int_mask;\

drivers/net/ethernet/calxeda/xgmac.c

1561

#define XGMAC_HW_STAT(m, reg_offset) \

drivers/net/ethernet/calxeda/xgmac.c

1562

{ #m, reg_offset, true }

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

368

u64 reg_offset;

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

420

reg_offset = NIC_QSET_RQ_0_7_STAT_0_1 | (1 << 3);

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

421

p[i++] = nicvf_queue_reg_read(nic, reg_offset, q);

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

438

reg_offset = NIC_QSET_SQ_0_7_STAT_0_1 | (1 << 3);

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

439

p[i++] = nicvf_queue_reg_read(nic, reg_offset, q);

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

453

reg_offset = NIC_QSET_RBDR_0_1_PREFETCH_STATUS;

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c

454

p[i++] = nicvf_queue_reg_read(nic, reg_offset, q);

drivers/net/ethernet/chelsio/cxgb/espi.c

52

int ch_addr, int reg_offset, u32 wr_data)

drivers/net/ethernet/chelsio/cxgb/espi.c

57

V_REGISTER_OFFSET(reg_offset) |

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

574

u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

605

ret = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

611

dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

615

dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);

drivers/net/ethernet/intel/ice/ice_common.c

3716

u32 receiver_id, reg_offset;

drivers/net/ethernet/intel/ice/ice_common.c

3722

reg_offset = fec_reg[pcs_port][fec_type];

drivers/net/ethernet/intel/ice/ice_common.c

3731

msg.msg_addr_low = lower_16_bits(reg_offset);

drivers/net/ethernet/intel/idpf/idpf.h

883

resource_size_t reg_offset)

drivers/net/ethernet/intel/idpf/idpf.h

885

return adapter->hw.mbx.vaddr + reg_offset;

drivers/net/ethernet/intel/idpf/idpf.h

896

resource_size_t reg_offset)

drivers/net/ethernet/intel/idpf/idpf.h

898

reg_offset -= adapter->dev_ops.static_reg_info[1].start;

drivers/net/ethernet/intel/idpf/idpf.h

900

return adapter->hw.rstat.vaddr + reg_offset;

drivers/net/ethernet/intel/idpf/idpf.h

911

resource_size_t reg_offset)

drivers/net/ethernet/intel/idpf/idpf.h

918

if (reg_offset >= region->addr_start &&

drivers/net/ethernet/intel/idpf/idpf.h

919

reg_offset < (region->addr_start + region->addr_len)) {

drivers/net/ethernet/intel/idpf/idpf.h

924

reg_offset -= region->addr_start;

drivers/net/ethernet/intel/idpf/idpf.h

926

return region->vaddr + reg_offset;

drivers/net/ethernet/intel/igb/e1000_82575.c

2070

u32 reg_val, reg_offset;

drivers/net/ethernet/intel/igb/e1000_82575.c

2074

reg_offset = E1000_DTXSWC;

drivers/net/ethernet/intel/igb/e1000_82575.c

2078

reg_offset = E1000_TXSWC;

drivers/net/ethernet/intel/igb/e1000_82575.c

2084

reg_val = rd32(reg_offset);

drivers/net/ethernet/intel/igb/e1000_82575.c

2096

wr32(reg_offset, reg_val);

drivers/net/ethernet/intel/igb/igb_ethtool.c

1003

u16 reg_offset;

drivers/net/ethernet/intel/igb/igb_ethtool.c

1330

(i * test->reg_offset),

drivers/net/ethernet/intel/igb/igb_ethtool.c

1336

(i * test->reg_offset),

drivers/net/ethernet/intel/igb/igb_ethtool.c

1343

+ (i * test->reg_offset));

drivers/net/ethernet/intel/igb/igb_main.c

10013

u32 reg_val, reg_offset;

drivers/net/ethernet/intel/igb/igb_main.c

10021

reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;

drivers/net/ethernet/intel/igb/igb_main.c

10022

reg_val = rd32(reg_offset);

drivers/net/ethernet/intel/igb/igb_main.c

10029

wr32(reg_offset, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

1488

u16 reg_offset;

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

1495

reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

1499

reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

1516

IXGBE_WRITE_REG(hw, reg_offset, txctrl);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4627

u32 reg_offset, vf_shift, vmolr;

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4649

reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4652

IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4653

IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4654

IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4655

IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

5038

u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

5039

u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

5042

IXGBE_WRITE_REG(hw, reg_offset, vlvfb);

drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c

274

u32 reg_offset = (vf_number < 32) ? 0 : 1;

drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c

280

vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));

drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c

287

vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));

drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c

294

IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), BIT(vf_shift));

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

497

u32 reg_offset, vf_shift, vfre;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

533

reg_offset = vf / 32;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

536

vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

541

IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre);

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

841

u32 reg_offset, vf_shift;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

844

reg_offset = vf / 32;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

846

reg_cur_tx = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

847

reg_cur_rx = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

876

IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg_req_tx);

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

878

IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg_req_rx);

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

886

u32 reg, reg_offset, vf_shift;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

904

reg_offset = vf / 32;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

919

reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

921

IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);

drivers/net/ethernet/marvell/mvneta.c

1638

unsigned int reg_offset;

drivers/net/ethernet/marvell/mvneta.c

1647

reg_offset = last_nibble % 4;

drivers/net/ethernet/marvell/mvneta.c

1653

unicast_reg &= ~(0xff << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

1655

unicast_reg &= ~(0xff << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

1656

unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

3086

unsigned int reg_offset;

drivers/net/ethernet/marvell/mvneta.c

3091

reg_offset = last_byte % 4;

drivers/net/ethernet/marvell/mvneta.c

3097

smc_table_reg &= ~(0xff << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

3099

smc_table_reg &= ~(0xff << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

3100

smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

3121

unsigned int reg_offset;

drivers/net/ethernet/marvell/mvneta.c

3124

reg_offset = crc8 % 4; /* Entry offset within the above reg */

drivers/net/ethernet/marvell/mvneta.c

3130

omc_table_reg &= ~(0xff << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

3132

omc_table_reg &= ~(0xff << (8 * reg_offset));

drivers/net/ethernet/marvell/mvneta.c

3133

omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

1914

u64 reg_offset;

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

697

u64 *reg_offset)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

699

u64 offset = req->reg_offset;

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

731

*reg_offset = (req->reg_offset & 0xFF000) + (lf << 3);

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

767

u64 offset = req->reg_offset;

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

782

rsp->reg_offset = req->reg_offset;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

1122

unsigned int offs = hw_stats->reg_offset;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4847

mac->hw_stats->reg_offset = id * 0x80;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4849

mac->hw_stats->reg_offset = id * 0x40;

drivers/net/ethernet/mediatek/mtk_eth_soc.h

727

u32 reg_offset;

drivers/net/ethernet/natsemi/macsonic.c

299

lp->reg_offset = 0;

drivers/net/ethernet/natsemi/macsonic.c

307

lp->reg_offset = 2;

drivers/net/ethernet/natsemi/macsonic.c

316

lp->reg_offset = 0;

drivers/net/ethernet/natsemi/macsonic.c

320

lp->reg_offset = 2;

drivers/net/ethernet/natsemi/macsonic.c

326

lp->reg_offset);

drivers/net/ethernet/natsemi/macsonic.c

407

int reg_offset, dma_bitmode;

drivers/net/ethernet/natsemi/macsonic.c

415

reg_offset = 2;

drivers/net/ethernet/natsemi/macsonic.c

422

reg_offset = 0;

drivers/net/ethernet/natsemi/macsonic.c

430

reg_offset = 0;

drivers/net/ethernet/natsemi/macsonic.c

438

reg_offset = 0;

drivers/net/ethernet/natsemi/macsonic.c

446

reg_offset = 0;

drivers/net/ethernet/natsemi/macsonic.c

457

lp->reg_offset = reg_offset;

drivers/net/ethernet/natsemi/macsonic.c

463

lp->dma_bitmode ? 32 : 16, lp->reg_offset);

drivers/net/ethernet/natsemi/macsonic.c

69

+ lp->reg_offset))

drivers/net/ethernet/natsemi/macsonic.c

71

+ lp->reg_offset))

drivers/net/ethernet/natsemi/sonic.h

300

int reg_offset;

drivers/net/ethernet/qlogic/qed/qed_cxt.c

2179

u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;

drivers/net/ethernet/qlogic/qed/qed_cxt.c

2280

reg_offset = PSWRQ2_REG_ILT_MEMORY +

drivers/net/ethernet/qlogic/qed/qed_cxt.c

2291

reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),

drivers/net/ethernet/qlogic/qed/qed_cxt.c

2326

u32 reg_offset, elem_size, hw_p_size, elems_per_p;

drivers/net/ethernet/qlogic/qed/qed_cxt.c

2392

reg_offset = PSWRQ2_REG_ILT_MEMORY +

drivers/net/ethernet/qlogic/qed/qed_cxt.c

2401

reg_offset,

drivers/net/ethernet/qlogic/qed/qed_dbg_hsi.h

390

u16 reg_offset; /* offset of this rules registers in the idle check

drivers/net/ethernet/qlogic/qed/qed_debug.c

2152

u32 offset = 0, reg_offset = 0;

drivers/net/ethernet/qlogic/qed/qed_debug.c

2159

while (reg_offset < total_len) {

drivers/net/ethernet/qlogic/qed/qed_debug.c

2160

u32 curr_len = min_t(u32, read_len, total_len - reg_offset);

drivers/net/ethernet/qlogic/qed/qed_debug.c

2167

reg_offset += curr_len;

drivers/net/ethernet/qlogic/qed/qed_debug.c

2170

if (reg_offset < total_len) {

drivers/net/ethernet/qlogic/qed/qed_debug.c

2174

reg_offset += curr_len;

drivers/net/ethernet/qlogic/qed/qed_debug.c

3735

rule->reg_offset;

drivers/net/ethernet/qlogic/qed/qed_debug.c

3875

rule->reg_offset;

drivers/net/ethernet/renesas/sh_eth.c

2082

if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \

drivers/net/ethernet/renesas/sh_eth.c

2206

mdp->reg_offset[TSU_ADRH0] +

drivers/net/ethernet/renesas/sh_eth.c

2729

u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);

drivers/net/ethernet/renesas/sh_eth.c

2733

for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {

drivers/net/ethernet/renesas/sh_eth.c

2734

sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);

drivers/net/ethernet/renesas/sh_eth.c

2756

u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);

drivers/net/ethernet/renesas/sh_eth.c

2764

ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);

drivers/net/ethernet/renesas/sh_eth.c

2773

u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);

drivers/net/ethernet/renesas/sh_eth.c

2785

ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);

drivers/net/ethernet/renesas/sh_eth.c

2847

u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);

drivers/net/ethernet/renesas/sh_eth.c

2854

for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {

drivers/net/ethernet/renesas/sh_eth.c

2855

sh_eth_tsu_read_entry(ndev, reg_offset, addr);

drivers/net/ethernet/renesas/sh_eth.c

3107

bitbang->addr = mdp->addr + mdp->reg_offset[PIR];

drivers/net/ethernet/renesas/sh_eth.c

3153

const u16 *reg_offset = NULL;

drivers/net/ethernet/renesas/sh_eth.c

3157

reg_offset = sh_eth_offset_gigabit;

drivers/net/ethernet/renesas/sh_eth.c

3160

reg_offset = sh_eth_offset_fast_rcar;

drivers/net/ethernet/renesas/sh_eth.c

3163

reg_offset = sh_eth_offset_fast_sh4;

drivers/net/ethernet/renesas/sh_eth.c

3166

reg_offset = sh_eth_offset_fast_sh3_sh2;

drivers/net/ethernet/renesas/sh_eth.c

3170

return reg_offset;

drivers/net/ethernet/renesas/sh_eth.c

3312

mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);

drivers/net/ethernet/renesas/sh_eth.c

3313

if (!mdp->reg_offset) {

drivers/net/ethernet/renesas/sh_eth.c

350

u16 offset = mdp->reg_offset[enum_index];

drivers/net/ethernet/renesas/sh_eth.c

361

u16 offset = mdp->reg_offset[enum_index];

drivers/net/ethernet/renesas/sh_eth.c

378

return mdp->reg_offset[enum_index];

drivers/net/ethernet/renesas/sh_eth.h

532

const u16 *reg_offset;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

414

int reg_offset;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

421

for (reg_offset = START_MAC_REG_OFFSET;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

422

reg_offset <= MAX_MAC_REG_OFFSET; reg_offset += 4) {

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

423

reg_space[reg_ix] = readl(ioaddr + reg_offset);

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

428

for (reg_offset = START_MTL_REG_OFFSET;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

429

reg_offset <= MAX_MTL_REG_OFFSET; reg_offset += 4) {

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

430

reg_space[reg_ix] = readl(ioaddr + reg_offset);

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

435

for (reg_offset = START_DMA_REG_OFFSET;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

436

reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) {

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

437

reg_space[reg_ix] = readl(ioaddr + reg_offset);

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

119

u32 reg_offset, reg_shift;

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

134

ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

233

dwmac->reg_offset = reg_offset;

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

391

u32 reg_offset = dwmac->reg_offset;

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

411

regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

432

regmap_write(sys_mgr_base_addr, reg_offset, ctrl);

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

449

u32 reg_offset = dwmac->reg_offset;

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

467

regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

485

regmap_write(sys_mgr_base_addr, reg_offset, ctrl);

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

61

u32 reg_offset;

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1451

u32 pfvfspoof, reg_offset, vf_shift;

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1454

reg_offset = WX_VF_REG_OFFSET(vf);

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1456

pfvfspoof = rd32(wx, WX_TDM_ETYPE_AS(reg_offset));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1461

wr32(wx, WX_TDM_ETYPE_AS(reg_offset), pfvfspoof);

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1487

u32 reg_offset, vf_shift;

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1508

reg_offset = WX_VF_REG_OFFSET(VMDQ_P(0));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1511

wr32(wx, WX_RDM_VF_RE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1512

wr32(wx, WX_RDM_VF_RE(reg_offset ^ 1), reg_offset - 1);

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1513

wr32(wx, WX_TDM_VF_TE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1514

wr32(wx, WX_TDM_VF_TE(reg_offset ^ 1), reg_offset - 1);

drivers/net/ethernet/wangxun/libwx/wx_mbx.c

166

u32 reg_offset = WX_VF_REG_OFFSET(vf);

drivers/net/ethernet/wangxun/libwx/wx_mbx.c

170

vflre = rd32(wx, WX_VFLRE(reg_offset));

drivers/net/ethernet/wangxun/libwx/wx_mbx.c

173

wr32(wx, WX_VFLREC(reg_offset), BIT(vf_shift));

drivers/net/ethernet/wangxun/ngbe/ngbe_type.h

92

#define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4))

drivers/net/ipa/gsi.c

1139

channel_mask = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1142

iowrite32(channel_mask, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1160

event_mask = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1163

iowrite32(event_mask, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1222

offset = reg_offset(log_reg);

drivers/net/ipa/gsi.c

1227

iowrite32(~0, gsi->virt + reg_offset(clr_reg));

drivers/net/ipa/gsi.c

1270

val = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1299

val = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1305

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1325

event_mask = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1330

iowrite32(event_mask, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1349

val = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1352

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1374

offset = reg_offset(reg);

drivers/net/ipa/gsi.c

1786

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1790

offset = reg_offset(reg);

drivers/net/ipa/gsi.c

1804

timeout = !gsi_command(gsi, reg_offset(reg), val);

drivers/net/ipa/gsi.c

1808

iowrite32(ERROR_INT, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1970

iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1977

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1980

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1983

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1986

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1991

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1994

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

1998

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

200

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

2029

val = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

2073

val = ioread32(gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

2089

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

228

iowrite32(~0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

231

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

243

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

261

iowrite32(~0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

264

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

277

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

290

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

310

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

328

iowrite32(ERROR_INT, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

341

iowrite32(val, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

355

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

358

iowrite32(0, gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

424

timeout = !gsi_command(gsi, reg_offset(reg), val);

drivers/net/ipa/gsi.c

541

timeout = !gsi_command(gsi, reg_offset(reg), val);

drivers/net/ipa/ipa_cmd.c

304

offset = reg_offset(reg);

drivers/net/ipa/ipa_endpoint.c

1652

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_endpoint.c

2023

val = ioread32(ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_interrupt.c

131

offset = reg_offset(reg);

drivers/net/ipa/ipa_interrupt.c

149

iowrite32(pending, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_interrupt.c

161

iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_interrupt.c

270

iowrite32(0, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_interrupt.c

82

offset = reg_offset(reg);

drivers/net/ipa/ipa_main.c

207

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

222

offset = reg_offset(reg);

drivers/net/ipa/ipa_main.c

254

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

269

offset = reg_offset(reg);

drivers/net/ipa/ipa_main.c

310

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

326

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

368

iowrite32(0, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

380

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

393

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

397

offset = reg_offset(reg);

drivers/net/ipa/ipa_main.c

419

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

448

iowrite32(0, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_main.c

467

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_mem.c

121

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_mem.c

333

val = ioread32(ipa->reg_virt + reg_offset(reg));

drivers/net/ipa/ipa_table.c

379

ipa_cmd_register_write_add(trans, reg_offset(reg), val, val, false);

drivers/net/ipa/ipa_uc.c

247

iowrite32(val, ipa->reg_virt + reg_offset(reg));

drivers/net/mdio/mdio-ipq8064.c

53

ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)

drivers/net/mdio/mdio-ipq8064.c

61

((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);

drivers/net/mdio/mdio-ipq8064.c

75

ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)

drivers/net/mdio/mdio-ipq8064.c

83

((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);

drivers/net/mdio/mdio-ipq8064.c

90

if (reg_offset == 31)

drivers/net/wireless/ath/ath.h

128

unsigned int (*read)(void *, u32 reg_offset);

drivers/net/wireless/ath/ath.h

130

void (*write)(void *, u32 val, u32 reg_offset);

drivers/net/wireless/ath/ath.h

133

u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);

drivers/net/wireless/ath/ath10k/qmi.h

68

__le16 reg_offset;

drivers/net/wireless/ath/ath10k/snoc.c

103

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

108

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

113

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

118

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

123

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

128

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

133

.reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

78

.reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

83

.reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

88

.reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

93

.reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath10k/snoc.c

98

.reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),

drivers/net/wireless/ath/ath5k/base.c

231

static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)

drivers/net/wireless/ath/ath5k/base.c

234

return ath5k_hw_reg_read(ah, reg_offset);

drivers/net/wireless/ath/ath5k/base.c

237

static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)

drivers/net/wireless/ath/ath5k/base.c

240

ath5k_hw_reg_write(ah, val, reg_offset);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1102

unsigned int dbg_reg, reg_offset;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1107

reg_offset = queue * 5;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1110

reg_offset = (queue - 6) * 5;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1117

dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1136

unsigned int reg_offset;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1150

reg_offset = i * 5;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1153

reg_offset = (i - 6) * 5;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1156

dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;

drivers/net/wireless/ath/ath9k/htc_drv_init.c

234

static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

239

__be32 val, reg = cpu_to_be32(reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

248

reg_offset, r);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

302

static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

308

cpu_to_be32(reg_offset),

drivers/net/wireless/ath/ath9k/htc_drv_init.c

319

reg_offset, r);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

323

static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

333

cpu_to_be32(reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

346

static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

353

ath9k_regwrite_buffer(hw_priv, val, reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

355

ath9k_regwrite_single(hw_priv, val, reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

384

u32 reg_offset, u32 set, u32 clr)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

396

cpu_to_be32(reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

467

u32 reg_offset, u32 set, u32 clr)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

475

buf.reg = cpu_to_be32(reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

485

reg_offset, ret);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

489

static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)

drivers/net/wireless/ath/ath9k/htc_drv_init.c

498

val = REG_READ(ah, reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

501

REG_WRITE(ah, reg_offset, val);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

507

ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

509

ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr);

drivers/net/wireless/ath/ath9k/init.c

172

static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)

drivers/net/wireless/ath/ath9k/init.c

181

iowrite32(val, sc->mem + reg_offset);

drivers/net/wireless/ath/ath9k/init.c

184

iowrite32(val, sc->mem + reg_offset);

drivers/net/wireless/ath/ath9k/init.c

187

static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)

drivers/net/wireless/ath/ath9k/init.c

197

val = ioread32(sc->mem + reg_offset);

drivers/net/wireless/ath/ath9k/init.c

200

val = ioread32(sc->mem + reg_offset);

drivers/net/wireless/ath/ath9k/init.c

214

static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,

drivers/net/wireless/ath/ath9k/init.c

219

val = ioread32(sc->mem + reg_offset);

drivers/net/wireless/ath/ath9k/init.c

222

iowrite32(val, sc->mem + reg_offset);

drivers/net/wireless/ath/ath9k/init.c

227

static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)

drivers/net/wireless/ath/ath9k/init.c

237

val = __ath9k_reg_rmw(sc, reg_offset, set, clr);

drivers/net/wireless/ath/ath9k/init.c

240

val = __ath9k_reg_rmw(sc, reg_offset, set, clr);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

471

brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

473

void __iomem *address = devinfo->regs + reg_offset;

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

479

brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

481

void __iomem *address = devinfo->regs + reg_offset;

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

488

brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

491

void __iomem *address = devinfo->regs + reg_offset;

drivers/net/wireless/intel/iwlegacy/3945.c

2567

u32 reg_offset;

drivers/net/wireless/intel/iwlegacy/3945.c

2591

for (reg_offset = BSM_SRAM_LOWER_BOUND;

drivers/net/wireless/intel/iwlegacy/3945.c

2592

reg_offset < BSM_SRAM_LOWER_BOUND + len;

drivers/net/wireless/intel/iwlegacy/3945.c

2593

reg_offset += sizeof(u32), image++)

drivers/net/wireless/intel/iwlegacy/3945.c

2594

_il_wr_prph(il, reg_offset, le32_to_cpu(*image));

drivers/net/wireless/intel/iwlegacy/4965.c

338

u32 reg_offset;

drivers/net/wireless/intel/iwlegacy/4965.c

366

for (reg_offset = BSM_SRAM_LOWER_BOUND;

drivers/net/wireless/intel/iwlegacy/4965.c

367

reg_offset < BSM_SRAM_LOWER_BOUND + len;

drivers/net/wireless/intel/iwlegacy/4965.c

368

reg_offset += sizeof(u32), image++)

drivers/net/wireless/intel/iwlegacy/4965.c

369

_il_wr_prph(il, reg_offset, le32_to_cpu(*image));

drivers/net/wireless/marvell/mwifiex/debugfs.c

422

u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX;

drivers/net/wireless/marvell/mwifiex/debugfs.c

428

if (sscanf(buf, "%u %x %x", &reg_type, &reg_offset, &reg_value) != 3) {

drivers/net/wireless/marvell/mwifiex/debugfs.c

433

if (reg_type == 0 || reg_offset == 0) {

drivers/net/wireless/marvell/mwifiex/debugfs.c

438

saved_reg_offset = reg_offset;

drivers/net/wireless/marvell/mwifiex/main.h

1508

u32 reg_offset, u32 reg_value);

drivers/net/wireless/marvell/mwifiex/main.h

1511

u32 reg_offset, u32 *value);

drivers/net/wireless/marvell/mwifiex/sta_ioctl.c

1296

u32 reg_offset, u32 reg_value)

drivers/net/wireless/marvell/mwifiex/sta_ioctl.c

1301

reg_rw.offset = reg_offset;

drivers/net/wireless/marvell/mwifiex/sta_ioctl.c

1315

u32 reg_offset, u32 *value)

drivers/net/wireless/marvell/mwifiex/sta_ioctl.c

1321

reg_rw.offset = reg_offset;

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

52

u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

67

mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

68

mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

139

u32 val, reg_offset;

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

172

reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

174

mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

175

mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1143

u32 val, reg_offset;

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1164

reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1179

mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1180

mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset);

drivers/net/wireless/mediatek/mt76/mt792x_mac.c

39

u32 val, reg_offset;

drivers/net/wireless/mediatek/mt76/mt792x_mac.c

55

reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |

drivers/net/wireless/mediatek/mt76/mt792x_mac.c

58

mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset);

drivers/net/wireless/mediatek/mt76/mt792x_mac.c

59

mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

2098

u32 reg_offset;

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

2118

reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

2121

mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

2122

mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset);

drivers/pci/controller/dwc/pci-keystone.c

160

u32 reg_offset;

drivers/pci/controller/dwc/pci-keystone.c

166

reg_offset = irq % 8;

drivers/pci/controller/dwc/pci-keystone.c

169

ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset),

drivers/pci/controller/dwc/pci-keystone.c

171

ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);

drivers/pci/controller/dwc/pci-keystone.c

200

u32 reg_offset;

drivers/pci/controller/dwc/pci-keystone.c

208

reg_offset = irq % 8;

drivers/pci/controller/dwc/pci-keystone.c

211

ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset),

drivers/pci/controller/dwc/pci-keystone.c

224

u32 reg_offset;

drivers/pci/controller/dwc/pci-keystone.c

232

reg_offset = irq % 8;

drivers/pci/controller/dwc/pci-keystone.c

235

ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset),

drivers/pci/controller/pcie-brcmstb.c

1102

u32 reg_offset = brcm_bar_reg_offset(i);

drivers/pci/controller/pcie-brcmstb.c

1109

writel_relaxed(tmp, base + reg_offset);

drivers/pci/controller/pcie-brcmstb.c

1111

writel_relaxed(upper_32_bits(pci_offset), base + reg_offset + 4);

drivers/pci/controller/pcie-brcmstb.c

1121

reg_offset = brcm_ubus_reg_offset(i);

drivers/pci/controller/pcie-brcmstb.c

1124

writel_relaxed(tmp, base + reg_offset);

drivers/pci/controller/pcie-brcmstb.c

1126

writel_relaxed(tmp, base + reg_offset + 4);

drivers/pci/controller/pcie-iproc.c

405

static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)

drivers/pci/controller/pcie-iproc.c

407

return !!(reg_offset == IPROC_PCIE_REG_INVALID);

drivers/pci/pci-acpi.c

439

u16 reg_offset;

drivers/pci/pci-acpi.c

559

pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);

drivers/pci/pci-acpi.c

567

pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);

drivers/pci/pci-acpi.c

598

hpx3_reg->reg_offset = reg_fields[11].integer.value;

drivers/perf/hisilicon/hisi_pcie_pmu.c

195

static u32 hisi_pcie_pmu_readl(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset,

drivers/perf/hisilicon/hisi_pcie_pmu.c

198

u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hisi_pcie_pmu.c

203

static void hisi_pcie_pmu_writel(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx, u32 val)

drivers/perf/hisilicon/hisi_pcie_pmu.c

205

u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hisi_pcie_pmu.c

210

static u64 hisi_pcie_pmu_readq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx)

drivers/perf/hisilicon/hisi_pcie_pmu.c

212

u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hisi_pcie_pmu.c

217

static void hisi_pcie_pmu_writeq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx, u64 val)

drivers/perf/hisilicon/hisi_pcie_pmu.c

219

u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hns3_pmu.c

736

static u32 hns3_pmu_readl(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx)

drivers/perf/hisilicon/hns3_pmu.c

738

u32 offset = hns3_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hns3_pmu.c

743

static void hns3_pmu_writel(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx,

drivers/perf/hisilicon/hns3_pmu.c

746

u32 offset = hns3_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hns3_pmu.c

751

static u64 hns3_pmu_readq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx)

drivers/perf/hisilicon/hns3_pmu.c

753

u32 offset = hns3_pmu_get_offset(reg_offset, idx);

drivers/perf/hisilicon/hns3_pmu.c

758

static void hns3_pmu_writeq(struct hns3_pmu *hns3_pmu, u32 reg_offset, u32 idx,

drivers/perf/hisilicon/hns3_pmu.c

761

u32 offset = hns3_pmu_get_offset(reg_offset, idx);

drivers/perf/marvell_cn10k_ddr_pmu.c

628

u32 reg_offset;

drivers/perf/marvell_cn10k_ddr_pmu.c

644

reg_offset = DDRC_PERF_CFG(p_data->cfg_base, counter);

drivers/perf/marvell_cn10k_ddr_pmu.c

649

writeq_relaxed(val, pmu->base + reg_offset);

drivers/phy/broadcom/phy-brcm-usb-init.c

446

u32 reg_offset, u32 field)

drivers/phy/broadcom/phy-brcm-usb-init.c

451

brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);

drivers/phy/broadcom/phy-brcm-usb-init.c

456

u32 reg_offset, u32 field)

drivers/phy/broadcom/phy-brcm-usb-init.c

461

brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);

drivers/phy/cadence/phy-cadence-sierra.c

214

#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \

drivers/phy/cadence/phy-cadence-sierra.c

216

(((ln) << 8) << (reg_offset)))

drivers/phy/cadence/phy-cadence-sierra.c

226

#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \

drivers/phy/cadence/phy-cadence-sierra.c

228

(((ln) << 8) << (reg_offset)))

drivers/phy/cadence/phy-cadence-sierra.c

69

#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \

drivers/phy/cadence/phy-cadence-sierra.c

71

(((ln) << 9) << (reg_offset)))

drivers/phy/cadence/phy-cadence-torrent.c

41

#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \

drivers/phy/cadence/phy-cadence-torrent.c

43

(((ln) << 9) << (reg_offset)))

drivers/phy/cadence/phy-cadence-torrent.c

45

#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \

drivers/phy/cadence/phy-cadence-torrent.c

47

(((ln) << 9) << (reg_offset)))

drivers/phy/cadence/phy-cadence-torrent.c

52

#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \

drivers/phy/cadence/phy-cadence-torrent.c

54

(((ln) << 8) << (reg_offset)))

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

533

seq_entry->offset = map.reg_offset;

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

96

u8 reg_offset;

drivers/phy/rockchip/phy-rockchip-emmc.c

108

rk_phy->reg_offset + GRF_EMMCPHY_CON6,

drivers/phy/rockchip/phy-rockchip-emmc.c

113

rk_phy->reg_offset + GRF_EMMCPHY_CON6,

drivers/phy/rockchip/phy-rockchip-emmc.c

166

rk_phy->reg_offset + GRF_EMMCPHY_CON6,

drivers/phy/rockchip/phy-rockchip-emmc.c

179

rk_phy->reg_offset + GRF_EMMCPHY_STATUS,

drivers/phy/rockchip/phy-rockchip-emmc.c

189

rk_phy->reg_offset + GRF_EMMCPHY_CON0,

drivers/phy/rockchip/phy-rockchip-emmc.c

195

rk_phy->reg_offset + GRF_EMMCPHY_CON6,

drivers/phy/rockchip/phy-rockchip-emmc.c

227

rk_phy->reg_offset + GRF_EMMCPHY_STATUS,

drivers/phy/rockchip/phy-rockchip-emmc.c

290

rk_phy->reg_offset + GRF_EMMCPHY_CON6,

drivers/phy/rockchip/phy-rockchip-emmc.c

297

rk_phy->reg_offset + GRF_EMMCPHY_CON0,

drivers/phy/rockchip/phy-rockchip-emmc.c

304

rk_phy->reg_offset + GRF_EMMCPHY_CON0,

drivers/phy/rockchip/phy-rockchip-emmc.c

311

rk_phy->reg_offset + GRF_EMMCPHY_CON2,

drivers/phy/rockchip/phy-rockchip-emmc.c

355

unsigned int reg_offset;

drivers/phy/rockchip/phy-rockchip-emmc.c

371

if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {

drivers/phy/rockchip/phy-rockchip-emmc.c

377

rk_phy->reg_offset = reg_offset;

drivers/phy/rockchip/phy-rockchip-emmc.c

86

unsigned int reg_offset;

drivers/phy/rockchip/phy-rockchip-usb.c

122

ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);

drivers/phy/rockchip/phy-rockchip-usb.c

203

unsigned int reg_offset;

drivers/phy/rockchip/phy-rockchip-usb.c

215

if (of_property_read_u32(child, "reg", &reg_offset)) {

drivers/phy/rockchip/phy-rockchip-usb.c

225

rk_phy->reg_offset = reg_offset;

drivers/phy/rockchip/phy-rockchip-usb.c

234

if (base->pdata->phys[i].reg == reg_offset) {

drivers/phy/rockchip/phy-rockchip-usb.c

67

unsigned int reg_offset;

drivers/phy/rockchip/phy-rockchip-usb.c

82

return regmap_write(phy->base->reg_base, phy->reg_offset, val);

drivers/phy/ti/phy-gmii-sel.c

373

field.reg += priv->reg_offset;

drivers/phy/ti/phy-gmii-sel.c

383

field.reg += priv->reg_offset;

drivers/phy/ti/phy-gmii-sel.c

396

field.reg += priv->reg_offset;

drivers/phy/ti/phy-gmii-sel.c

439

priv->reg_offset = __be32_to_cpu(*offset);

drivers/phy/ti/phy-gmii-sel.c

66

u32 reg_offset;

drivers/pinctrl/freescale/pinctrl-imx1-core.c

116

u32 value, u32 reg_offset)

drivers/pinctrl/freescale/pinctrl-imx1-core.c

118

void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;

drivers/pinctrl/freescale/pinctrl-imx1-core.c

136

u32 reg_offset)

drivers/pinctrl/freescale/pinctrl-imx1-core.c

138

void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;

drivers/pinctrl/freescale/pinctrl-imx1-core.c

149

u32 reg_offset)

drivers/pinctrl/freescale/pinctrl-imx1-core.c

151

void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;

drivers/pinctrl/freescale/pinctrl-imx1-core.c

89

u32 value, u32 reg_offset)

drivers/pinctrl/freescale/pinctrl-imx1-core.c

91

void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;

drivers/pinctrl/intel/pinctrl-baytrail.c

582

u32 reg_offset;

drivers/pinctrl/intel/pinctrl-baytrail.c

591

reg_offset = (offset / 32) * 4;

drivers/pinctrl/intel/pinctrl-baytrail.c

594

reg_offset = 0;

drivers/pinctrl/intel/pinctrl-baytrail.c

597

reg_offset = comm->pad_map[offset] * 16;

drivers/pinctrl/intel/pinctrl-baytrail.c

601

return comm->pad_regs + reg_offset + reg;

drivers/pinctrl/intel/pinctrl-lynxpoint.c

223

int reg_offset;

drivers/pinctrl/intel/pinctrl-lynxpoint.c

233

reg_offset = offset * 8;

drivers/pinctrl/intel/pinctrl-lynxpoint.c

236

reg_offset = (offset / 32) * 4;

drivers/pinctrl/intel/pinctrl-lynxpoint.c

238

return comm->regs + reg_offset + reg;

drivers/pinctrl/mediatek/mtk-eint.c

109

unsigned int reg_offset;

drivers/pinctrl/mediatek/mtk-eint.c

119

reg_offset = eint->regs->pol_clr;

drivers/pinctrl/mediatek/mtk-eint.c

121

reg_offset = eint->regs->pol_set;

drivers/pinctrl/mediatek/mtk-eint.c

122

writel(mask, reg + reg_offset);

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

286

*reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

50

u32 reg_offset[AML_NUM_REG];

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

886

*reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4;

drivers/pinctrl/meson/pinctrl-amlogic-a4.c

977

bank->pc.reg_offset[i] = aml_def_regoffs[i];

drivers/pinctrl/pinctrl-ingenic.c

1140

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

122

unsigned int reg_offset;

drivers/pinctrl/pinctrl-ingenic.c

1480

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

1753

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

2016

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

2250

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

2362

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

2589

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

279

.reg_offset = 0x30,

drivers/pinctrl/pinctrl-ingenic.c

2816

.reg_offset = 0x1000,

drivers/pinctrl/pinctrl-ingenic.c

3291

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

3502

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

3548

jzgc->jzpc->info->reg_offset) + reg, BIT(offset));

drivers/pinctrl/pinctrl-ingenic.c

3554

jzgc->jzpc->info->reg_offset),

drivers/pinctrl/pinctrl-ingenic.c

3832

regmap_write(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

3835

regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

3839

regmap_write(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

3842

regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

3852

regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +

drivers/pinctrl/pinctrl-ingenic.c

3859

regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),

drivers/pinctrl/pinctrl-ingenic.c

3875

regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,

drivers/pinctrl/pinctrl-ingenic.c

388

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

3886

regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);

drivers/pinctrl/pinctrl-ingenic.c

4099

regmap_read(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

4102

regmap_read(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

4201

regmap_write(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

4203

regmap_write(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

4206

regmap_write(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

4208

regmap_write(jzpc->map, offt * jzpc->info->reg_offset +

drivers/pinctrl/pinctrl-ingenic.c

4434

jzgc->reg_base = bank * jzpc->info->reg_offset;

drivers/pinctrl/pinctrl-ingenic.c

4517

regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;

drivers/pinctrl/pinctrl-ingenic.c

490

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

627

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-ingenic.c

792

.reg_offset = 0x100,

drivers/pinctrl/pinctrl-lpc18xx.c

1001

reg_val = readl(scu->base + reg_offset);

drivers/pinctrl/pinctrl-lpc18xx.c

1004

writel(reg_val, scu->base + reg_offset);

drivers/pinctrl/pinctrl-lpc18xx.c

987

u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;

drivers/pinctrl/pinctrl-lpc18xx.c

999

reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);

drivers/pinctrl/pinctrl-st.c

1089

int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;

drivers/pinctrl/pinctrl-st.c

1096

struct reg_field reg = REG_FIELD(reg_offset, 0, 31);

drivers/pinctrl/pinctrl-st.c

1100

reg_offset += 4;

drivers/pinctrl/realtek/pinctrl-rtd.c

307

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

320

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

332

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

345

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

358

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

366

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

400

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

418

reg_off = sconfig_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

435

reg_off = sconfig_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.c

452

reg_off = config_desc->reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.h

29

unsigned int reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.h

41

unsigned int reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.h

58

unsigned int reg_offset;

drivers/pinctrl/realtek/pinctrl-rtd.h

78

.reg_offset = _reg_off, \

drivers/pinctrl/realtek/pinctrl-rtd.h

92

.reg_offset = _reg_off, \

drivers/pinctrl/samsung/pinctrl-exynos-arm.c

27

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

drivers/pinctrl/samsung/pinctrl-exynos-arm.c

32

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

24

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

29

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

35

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

40

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

49

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

58

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

67

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

76

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

85

.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-exynos.c

241

reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];

drivers/pinctrl/samsung/pinctrl-exynos.c

274

reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

72

.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

77

.reg_offset = { 0x00, 0x04, 0x08, },

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

82

.reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

87

.reg_offset = { 0x00, 0x08, 0x0c, },

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

92

.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },

drivers/pinctrl/samsung/pinctrl-s3c64xx.c

97

.reg_offset = { 0x00, 0x04, 0x08, },

drivers/pinctrl/samsung/pinctrl-samsung.c

1018

data = readl(reg + type->reg_offset[PINCFG_TYPE_PUD]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1022

writel(data, reg + type->reg_offset[PINCFG_TYPE_PUD]);

drivers/pinctrl/samsung/pinctrl-samsung.c

1354

const u8 *offs = bank->type->reg_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

1429

const u8 *offs = bank->type->reg_offset;

drivers/pinctrl/samsung/pinctrl-samsung.c

408

data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);

drivers/pinctrl/samsung/pinctrl-samsung.c

411

writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);

drivers/pinctrl/samsung/pinctrl-samsung.c

458

cfg_reg = type->reg_offset[cfg_type];

drivers/pinctrl/samsung/pinctrl-samsung.c

565

data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);

drivers/pinctrl/samsung/pinctrl-samsung.c

569

writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);

drivers/pinctrl/samsung/pinctrl-samsung.c

614

data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);

drivers/pinctrl/samsung/pinctrl-samsung.c

641

+ type->reg_offset[PINCFG_TYPE_FUNC];

drivers/pinctrl/samsung/pinctrl-samsung.h

131

u8 reg_offset[PINCFG_TYPE_NUM];

drivers/platform/x86/amd/pmc/pmc.c

101

iowrite32(val, dev->regbase + reg_offset);

drivers/platform/x86/amd/pmc/pmc.c

94

static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)

drivers/platform/x86/amd/pmc/pmc.c

96

return ioread32(dev->regbase + reg_offset);

drivers/platform/x86/amd/pmc/pmc.c

99

static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)

drivers/platform/x86/amd/pmf/core.c

165

static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset)

drivers/platform/x86/amd/pmf/core.c

167

return ioread32(dev->regbase + reg_offset);

drivers/platform/x86/amd/pmf/core.c

170

static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val)

drivers/platform/x86/amd/pmf/core.c

172

iowrite32(val, dev->regbase + reg_offset);

drivers/platform/x86/intel/pmc/core.c

66

static inline u32 pmc_core_reg_read(struct pmc *pmc, int reg_offset)

drivers/platform/x86/intel/pmc/core.c

68

return readl(pmc->regbase + reg_offset);

drivers/platform/x86/intel/pmc/core.c

71

static inline void pmc_core_reg_write(struct pmc *pmc, int reg_offset,

drivers/platform/x86/intel/pmc/core.c

74

writel(val, pmc->regbase + reg_offset);

drivers/platform/x86/pmc_atom.c

206

static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)

drivers/platform/x86/pmc_atom.c

208

return readl(pmc->regmap + reg_offset);

drivers/platform/x86/pmc_atom.c

211

static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)

drivers/platform/x86/pmc_atom.c

213

writel(val, pmc->regmap + reg_offset);

drivers/power/supply/sbs-battery.c

612

int reg_offset, enum power_supply_property psp,

drivers/power/supply/sbs-battery.c

618

ret = sbs_read_word_data(client, sbs_data[reg_offset].addr);

drivers/power/supply/sbs-battery.c

623

if (sbs_data[reg_offset].min_value < 0)

drivers/power/supply/sbs-battery.c

626

if (ret >= sbs_data[reg_offset].min_value &&

drivers/power/supply/sbs-battery.c

627

ret <= sbs_data[reg_offset].max_value) {

drivers/power/supply/sbs-battery.c

798

int reg_offset, enum power_supply_property psp,

drivers/power/supply/sbs-battery.c

811

ret = sbs_read_word_data(client, sbs_data[reg_offset].addr);

drivers/pwm/pwm-meson.c

243

writel(value, meson->base + channel_data->reg_offset);

drivers/pwm/pwm-meson.c

359

value = readl(meson->base + channel_data->reg_offset);

drivers/pwm/pwm-meson.c

70

u8 reg_offset;

drivers/pwm/pwm-meson.c

79

.reg_offset = REG_PWM_A,

drivers/pwm/pwm-meson.c

88

.reg_offset = REG_PWM_B,

drivers/pwm/pwm-microchip-core.c

72

u8 channel_enable, reg_offset, shift;

drivers/pwm/pwm-microchip-core.c

79

reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);

drivers/pwm/pwm-microchip-core.c

82

channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);

drivers/pwm/pwm-microchip-core.c

86

writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);

drivers/regulator/palmas-regulator.c

322

.reg_offset = _offset, \

drivers/regulator/palmas-regulator.c

358

.reg_offset = _offset, \

drivers/regulator/rk808-regulator.c

383

static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv)

drivers/regulator/rk808-regulator.c

391

reg = rdev->desc->vsel_reg + reg_offset;

drivers/reset/reset-aspeed.c

162

void __iomem *reg_offset = rc->base + rc->info->signal[id].offset;

drivers/reset/reset-aspeed.c

165

writel(rc->info->signal[id].bit, reg_offset);

drivers/reset/reset-aspeed.c

168

writel(readl(reg_offset) & ~rc->info->signal[id].bit, reg_offset);

drivers/reset/reset-aspeed.c

177

void __iomem *reg_offset = rc->base + rc->info->signal[id].offset;

drivers/reset/reset-aspeed.c

180

writel(rc->info->signal[id].bit, reg_offset + 0x04);

drivers/reset/reset-aspeed.c

183

writel(readl(reg_offset) | rc->info->signal[id].bit, reg_offset);

drivers/reset/reset-aspeed.c

192

void __iomem *reg_offset = rc->base + rc->info->signal[id].offset;

drivers/reset/reset-aspeed.c

194

return (readl(reg_offset) & rc->info->signal[id].bit) ? 1 : 0;

drivers/reset/reset-simple.c

117

u32 reg_offset;

drivers/reset/reset-simple.c

126

.reg_offset = 0x20,

drivers/reset/reset-simple.c

168

u32 reg_offset = 0;

drivers/reset/reset-simple.c

188

reg_offset = devdata->reg_offset;

drivers/reset/reset-simple.c

195

data->membase += reg_offset;

drivers/reset/reset-socfpga.c

28

u32 reg_offset = 0x10;

drivers/reset/reset-socfpga.c

50

if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))

drivers/reset/reset-socfpga.c

52

data->membase += reg_offset;

drivers/scsi/FlashPoint.c

4925

u32 reg_offset;

drivers/scsi/FlashPoint.c

4936

reg_offset = hp_aramBase;

drivers/scsi/FlashPoint.c

4961

WR_HARP32(p_port, reg_offset, addr);

drivers/scsi/FlashPoint.c

4962

reg_offset += 4;

drivers/scsi/FlashPoint.c

4964

WR_HARP32(p_port, reg_offset, count);

drivers/scsi/FlashPoint.c

4965

reg_offset += 4;

drivers/soc/qcom/llcc-qcom.c

149

const u32 *reg_offset;

drivers/soc/qcom/llcc-qcom.c

4061

.reg_offset = llcc_v6_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4070

.reg_offset = llcc_v6_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4080

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4089

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4099

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4105

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4111

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4117

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4126

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4136

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4145

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4156

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4167

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4176

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4185

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4194

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4204

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4214

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4223

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4232

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4241

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4250

.reg_offset = llcc_v1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4259

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4268

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4277

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4287

.reg_offset = llcc_v6_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4296

.reg_offset = llcc_v2_1_reg_offset,

drivers/soc/qcom/llcc-qcom.c

4804

u32 slice_offset, reg_offset;

drivers/soc/qcom/llcc-qcom.c

4847

reg_offset = (config->slice_id / 32) * 4;

drivers/soc/qcom/llcc-qcom.c

4851

cfg->reg_offset[LLCC_TRP_WRS_EN] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4858

cfg->reg_offset[LLCC_TRP_WRS_CACHEABLE_EN] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4865

cfg->reg_offset[LLCC_TRP_ALGO_STALE_EN] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4872

cfg->reg_offset[LLCC_TRP_ALGO_STALE_CAP_EN] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4879

cfg->reg_offset[LLCC_TRP_ALGO_MRU0] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4886

cfg->reg_offset[LLCC_TRP_ALGO_MRU1] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4893

cfg->reg_offset[LLCC_TRP_ALGO_ALLOC0] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4900

cfg->reg_offset[LLCC_TRP_ALGO_ALLOC1] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4907

cfg->reg_offset[LLCC_TRP_ALGO_ALLOC2] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

4914

cfg->reg_offset[LLCC_TRP_ALGO_ALLOC3] + reg_offset,

drivers/soc/qcom/llcc-qcom.c

5043

ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);

drivers/soc/qcom/llcc-qcom.c

5083

ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],

drivers/soc/qcom/llcc-qcom.c

57

#define LLCC_V6_TRP_ATTR0_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR0_CFG] + SZ_64 * (n))

drivers/soc/qcom/llcc-qcom.c

58

#define LLCC_V6_TRP_ATTR1_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR1_CFG] + SZ_64 * (n))

drivers/soc/qcom/llcc-qcom.c

59

#define LLCC_V6_TRP_ATTR2_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR2_CFG] + SZ_64 * (n))

drivers/soc/qcom/llcc-qcom.c

60

#define LLCC_V6_TRP_ATTR3_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR3_CFG] + SZ_64 * (n))

drivers/soc/qcom/spm.c

102

.reg_offset = spm_reg_offset_v4_1,

drivers/soc/qcom/spm.c

108

.reg_offset = spm_reg_offset_v4_1,

drivers/soc/qcom/spm.c

114

.reg_offset = spm_reg_offset_v4_1,

drivers/soc/qcom/spm.c

128

.reg_offset = spm_reg_offset_v3_0,

drivers/soc/qcom/spm.c

140

.reg_offset = spm_reg_offset_v3_0,

drivers/soc/qcom/spm.c

151

.reg_offset = spm_reg_offset_v3_0,

drivers/soc/qcom/spm.c

171

.reg_offset = spm_reg_offset_v2_3,

drivers/soc/qcom/spm.c

181

.reg_offset = spm_reg_offset_v2_3,

drivers/soc/qcom/spm.c

199

.reg_offset = spm_reg_offset_v2_1,

drivers/soc/qcom/spm.c

211

.reg_offset = spm_reg_offset_v2_1,

drivers/soc/qcom/spm.c

241

.reg_offset = spm_reg_offset_v1_1,

drivers/soc/qcom/spm.c

259

if (drv->reg_data->reg_offset[reg])

drivers/soc/qcom/spm.c

261

drv->reg_data->reg_offset[reg]);

drivers/soc/qcom/spm.c

270

if (!drv->reg_data->reg_offset[reg])

drivers/soc/qcom/spm.c

275

drv->reg_data->reg_offset[reg]);

drivers/soc/qcom/spm.c

277

drv->reg_data->reg_offset[reg]);

drivers/soc/qcom/spm.c

287

return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);

drivers/soc/qcom/spm.c

531

addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];

drivers/soc/qcom/spm.c

552

if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])

drivers/soc/qcom/spm.c

65

const u16 *reg_offset;

drivers/soc/qcom/spm.c

96

.reg_offset = spm_reg_offset_v4_1,

drivers/soc/ti/pruss.c

311

u32 reg_offset;

drivers/soc/ti/pruss.c

344

ret = of_property_read_u32(clk_mux_np, "reg", &reg_offset);

drivers/soc/ti/pruss.c

348

reg = pruss->cfg_base + reg_offset;

drivers/spi/spi-bcm-qspi.c

789

u32 reg_offset = MSPI_RXRAM;

drivers/spi/spi-bcm-qspi.c

790

u32 lsb_offset = reg_offset + (slot << 3) + 0x4;

drivers/spi/spi-bcm-qspi.c

791

u32 msb_offset = reg_offset + (slot << 3);

drivers/spi/spi-bcm-qspi.c

799

u32 reg_offset = MSPI_RXRAM;

drivers/spi/spi-bcm-qspi.c

800

u32 offset = reg_offset + (slot << 3);

drivers/spi/spi-bcm-qspi.c

811

u32 reg_offset = MSPI_RXRAM;

drivers/spi/spi-bcm-qspi.c

812

u32 lsb_offset = reg_offset + (slot << 3) + 0x4;

drivers/spi/spi-bcm-qspi.c

813

u32 msb_offset = reg_offset + (slot << 3);

drivers/spi/spi-bcm-qspi.c

886

u32 reg_offset = MSPI_TXRAM + (slot << 3);

drivers/spi/spi-bcm-qspi.c

889

bcm_qspi_write(qspi, MSPI, reg_offset, val);

drivers/spi/spi-bcm-qspi.c

895

u32 reg_offset = MSPI_TXRAM;

drivers/spi/spi-bcm-qspi.c

896

u32 msb_offset = reg_offset + (slot << 3);

drivers/spi/spi-bcm-qspi.c

897

u32 lsb_offset = reg_offset + (slot << 3) + 0x4;

drivers/spi/spi-bcm-qspi.c

906

u32 reg_offset = MSPI_TXRAM;

drivers/spi/spi-bcm-qspi.c

907

u32 msb_offset = reg_offset + (slot << 3);

drivers/spi/spi-bcm-qspi.c

915

u32 reg_offset = MSPI_TXRAM;

drivers/spi/spi-bcm-qspi.c

916

u32 msb_offset = reg_offset + (slot << 3);

drivers/spi/spi-bcm-qspi.c

917

u32 lsb_offset = reg_offset + (slot << 3) + 0x4;

drivers/spi/spi-mtk-nor.c

520

int reg_offset = MTK_NOR_REG_PRGDATA_MAX;

drivers/spi/spi-mtk-nor.c

546

for (i = op->cmd.nbytes; i > 0; i--, reg_offset--) {

drivers/spi/spi-mtk-nor.c

547

reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);

drivers/spi/spi-mtk-nor.c

552

for (i = op->addr.nbytes; i > 0; i--, reg_offset--) {

drivers/spi/spi-mtk-nor.c

553

reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);

drivers/spi/spi-mtk-nor.c

559

for (i = 0; i < op->dummy.nbytes; i++, reg_offset--) {

drivers/spi/spi-mtk-nor.c

560

reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);

drivers/spi/spi-mtk-nor.c

564

for (i = 0; i < op->data.nbytes; i++, reg_offset--) {

drivers/spi/spi-mtk-nor.c

565

reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);

drivers/spi/spi-mtk-nor.c

570

for (; reg_offset >= 0; reg_offset--) {

drivers/spi/spi-mtk-nor.c

571

reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);

drivers/spi/spi-mtk-nor.c

588

reg_offset = 0;

drivers/spi/spi-mtk-nor.c

590

for (i = op->data.nbytes - 1; i >= 0; i--, reg_offset++) {

drivers/spi/spi-mtk-nor.c

591

reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);

drivers/spi/spi-mtk-nor.c

661

int reg_offset = MTK_NOR_REG_PRGDATA_MAX;

drivers/spi/spi-mtk-nor.c

669

for (i = 0; i < t->len; i++, reg_offset--) {

drivers/spi/spi-mtk-nor.c

670

reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);

drivers/spi/spi-mtk-nor.c

686

reg_offset = trx_len - 1;

drivers/spi/spi-mtk-nor.c

689

for (i = 0; i < t->len; i++, reg_offset--) {

drivers/spi/spi-mtk-nor.c

690

reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);

drivers/staging/media/meson/vdec/codec_h264.c

366

int reg_offset = (frame_num / 2) * 4;

drivers/staging/media/meson/vdec/codec_h264.c

367

u32 offset_msb = amvdec_read_dos(core, AV_SCRATCH_A + reg_offset);

drivers/staging/media/tegra-video/tegra20.c

232

const unsigned long reg_offset = 0x42c;

drivers/staging/media/tegra-video/tegra20.c

242

val = readl(apb_misc + reg_offset);

drivers/staging/media/tegra-video/tegra20.c

245

writel(val, apb_misc + reg_offset);

drivers/tty/serial/8250/8250_aspeed_vuart.c

384

u32 reg_offset, u32 reg_mask)

drivers/tty/serial/8250/8250_aspeed_vuart.c

395

if (regmap_read(regmap, reg_offset, &value)) {

drivers/tty/serial/amba-pl011.c

104

const u16 *reg_offset;

drivers/tty/serial/amba-pl011.c

127

.reg_offset = pl011_std_offsets,

drivers/tty/serial/amba-pl011.c

142

.reg_offset = pl011_std_offsets,

drivers/tty/serial/amba-pl011.c

157

.reg_offset = pl011_std_offsets,

drivers/tty/serial/amba-pl011.c

205

.reg_offset = pl011_st_offsets,

drivers/tty/serial/amba-pl011.c

263

const u16 *reg_offset;

drivers/tty/serial/amba-pl011.c

2897

uap->reg_offset = vendor->reg_offset;

drivers/tty/serial/amba-pl011.c

292

return uap->reg_offset[reg];

drivers/tty/serial/amba-pl011.c

3021

uap->reg_offset = uap->vendor->reg_offset;

drivers/tty/serial/mxs-auart.c

360

const u16 *reg_offset;

drivers/tty/serial/mxs-auart.c

407

.reg_offset = mxs_asm9260_offsets,

drivers/tty/serial/mxs-auart.c

411

.reg_offset = mxs_stmp37xx_offsets,

drivers/tty/serial/mxs-auart.c

476

return uap->vendor->reg_offset[reg];

drivers/watchdog/marvell_gti_wdt.c

38

#define GTI_CWD_WDOG(reg_offset) (0x8 * (reg_offset))

drivers/watchdog/marvell_gti_wdt.c

59

#define GTI_CWD_POKE(reg_offset) (0x10000 + 0x8 * (reg_offset))

drivers/xen/xen-pciback/conf_space_header.c

350

#define CFG_FIELD_BAR(reg_offset) \

drivers/xen/xen-pciback/conf_space_header.c

352

.offset = reg_offset, \

drivers/xen/xen-pciback/conf_space_header.c

361

#define CFG_FIELD_ROM(reg_offset) \

drivers/xen/xen-pciback/conf_space_header.c

363

.offset = reg_offset, \

fs/xfs/xfs_log.c

1987

uint32_t reg_offset = 0;

fs/xfs/xfs_log.c

2069

reg_offset += rlen;

fs/xfs/xfs_log.c

2070

rlen = reg->i_len - reg_offset;

fs/xfs/xfs_log.c

2080

xlog_write_iovec(data, reg->i_addr + reg_offset, rlen);

include/linux/hisi_acc_qm.h

183

u32 reg_offset;

include/linux/irq.h

1225

u32 val, int reg_offset)

include/linux/irq.h

1228

gc->reg_writel(val, gc->reg_base + reg_offset);

include/linux/irq.h

1230

writel(val, gc->reg_base + reg_offset);

include/linux/irq.h

1234

int reg_offset)

include/linux/irq.h

1237

return gc->reg_readl(gc->reg_base + reg_offset);

include/linux/irq.h

1239

return readl(gc->reg_base + reg_offset);

include/linux/mfd/palmas.h

96

int reg_offset;

include/linux/platform_data/hsmmc-omap.h

46

u16 reg_offset;

include/linux/platform_data/mmc-omap.h

36

u16 reg_offset;

include/linux/regmap.h

1591

unsigned int reg_offset;

include/linux/regmap.h

1597

[_irq] = { .reg_offset = (_off), .mask = (_mask) }

include/linux/regmap.h

1602

.reg_offset = (_id) / (_reg_bits), \

include/sound/cs35l41.h

874

.reg_offset = (CS35L41_ ## _reg) - CS35L41_IRQ1_STATUS1,\

sound/pci/intel8x0.c

1003

if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))

sound/pci/intel8x0.c

1014

if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))

sound/pci/intel8x0.c

2504

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);

sound/pci/intel8x0.c

2507

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);

sound/pci/intel8x0.c

2511

if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)

sound/pci/intel8x0.c

2519

iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,

sound/pci/intel8x0.c

2533

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);

sound/pci/intel8x0.c

2536

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);

sound/pci/intel8x0.c

2608

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0.c

2660

port = ichdev->reg_offset;

sound/pci/intel8x0.c

2676

civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);

sound/pci/intel8x0.c

2677

pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);

sound/pci/intel8x0.c

2682

if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&

sound/pci/intel8x0.c

2683

pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))

sound/pci/intel8x0.c

2960

ichdev->reg_offset = tbl[i].offset;

sound/pci/intel8x0.c

2971

ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;

sound/pci/intel8x0.c

310

unsigned long reg_offset; /* offset to bmaddr */

sound/pci/intel8x0.c

640

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0.c

692

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0.c

787

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0.c

824

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0.c

996

civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);

sound/pci/intel8x0.c

997

ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);

sound/pci/intel8x0m.c

1084

ichdev->reg_offset = tbl[i].offset;

sound/pci/intel8x0m.c

1095

ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;

sound/pci/intel8x0m.c

140

unsigned long reg_offset; /* offset to bmaddr */

sound/pci/intel8x0m.c

370

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0m.c

420

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0m.c

505

unsigned long port = ichdev->reg_offset;

sound/pci/intel8x0m.c

541

ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;

sound/pci/intel8x0m.c

933

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);

sound/pci/intel8x0m.c

936

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);

sound/pci/intel8x0m.c

939

iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);

sound/pci/intel8x0m.c

952

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);

sound/pci/intel8x0m.c

955

iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);

sound/pci/via82xx.c

1024

if (chip->spdif_on && viadev->reg_offset == 0x30)

sound/pci/via82xx.c

1035

outb(chip->playback_volume[viadev->reg_offset / 0x10][0],

sound/pci/via82xx.c

1037

outb(chip->playback_volume[viadev->reg_offset / 0x10][1],

sound/pci/via82xx.c

1165

if (chip->spdif_on && viadev->reg_offset == 0x30) {

sound/pci/via82xx.c

1169

} else if (chip->dxs_fixed && viadev->reg_offset < 0x40) {

sound/pci/via82xx.c

1173

} else if (chip->dxs_src && viadev->reg_offset < 0x40) {

sound/pci/via82xx.c

1239

stream = viadev->reg_offset / 0x10;

sound/pci/via82xx.c

1334

stream = viadev->reg_offset / 0x10;

sound/pci/via82xx.c

1401

static void init_viadev(struct via82xx *chip, int idx, unsigned int reg_offset,

sound/pci/via82xx.c

1404

chip->devs[idx].reg_offset = reg_offset;

sound/pci/via82xx.c

1407

chip->devs[idx].port = chip->port + reg_offset;

sound/pci/via82xx.c

310

unsigned int reg_offset;

sound/pci/via82xx.c

959

((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) |

sound/pci/via82xx_modem.c

205

unsigned int reg_offset;

sound/pci/via82xx_modem.c

813

static void init_viadev(struct via82xx_modem *chip, int idx, unsigned int reg_offset,

sound/pci/via82xx_modem.c

816

chip->devs[idx].reg_offset = reg_offset;

sound/pci/via82xx_modem.c

818

chip->devs[idx].port = chip->port + reg_offset;

sound/soc/amd/acp/acp-i2s.c

540

phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-i2s.c

552

phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-i2s.c

567

phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-i2s.c

579

phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-i2s.c

594

phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-i2s.c

606

phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-legacy-common.c

157

physical_addr = stream->reg_offset + MEM_WINDOW_START;

sound/soc/amd/acp/acp-legacy-common.c

225

phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-legacy-common.c

236

phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-legacy-common.c

250

phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-legacy-common.c

261

phy_addr = I2S_BT_RX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-legacy-common.c

275

phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-legacy-common.c

286

phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;

sound/soc/amd/acp/acp-pdm.c

153

stream->reg_offset = ACP_REGION2_OFFSET;

sound/soc/amd/acp/acp-pdm.c

52

physical_addr = stream->reg_offset + MEM_WINDOW_START;

sound/soc/amd/acp/acp-platform.c

116

stream->reg_offset = 0x02000000;

sound/soc/amd/acp/amd.h

183

u32 reg_offset;

sound/soc/codecs/cs35l45.h

457

.reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \

sound/soc/codecs/wcd9335.c

4949

.reg_offset = 0,

sound/soc/codecs/wm8994.c

2210

int reg_offset, ret;

sound/soc/codecs/wm8994.c

2219

reg_offset = 0;

sound/soc/codecs/wm8994.c

2224

reg_offset = 0x20;

sound/soc/codecs/wm8994.c

2232

reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset);

sound/soc/codecs/wm8994.c

2288

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,

sound/soc/codecs/wm8994.c

2294

+ reg_offset);

sound/soc/codecs/wm8994.c

2315

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,

sound/soc/codecs/wm8994.c

2322

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,

sound/soc/codecs/wm8994.c

2326

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,

sound/soc/codecs/wm8994.c

2329

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,

sound/soc/codecs/wm8994.c

2334

snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,

sound/soc/codecs/wm8994.c

2337

snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,

sound/soc/codecs/wm8994.c

2340

snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,

sound/soc/codecs/wm8994.c

2344

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,

sound/soc/codecs/wm8994.c

2401

snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,

sound/soc/codecs/wm8995.c

1800

int reg_offset, ret;

sound/soc/codecs/wm8995.c

1815

reg_offset = 0;

sound/soc/codecs/wm8995.c

1819

reg_offset = 0x20;

sound/soc/codecs/wm8995.c

1865

snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,

sound/soc/codecs/wm8995.c

1870

snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,

sound/soc/codecs/wm8995.c

1874

snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);

sound/soc/codecs/wm8995.c

1876

snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,

sound/soc/codecs/wm8995.c

1880

snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,

sound/soc/codecs/wm8995.c

1887

snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,

sound/soc/fsl/fsl_sai.c

1124

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

1180

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

1223

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

1269

unsigned char ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

1449

if (sai->soc_data->reg_offset == 8) {

sound/soc/fsl/fsl_sai.c

1670

.reg_offset = 0,

sound/soc/fsl/fsl_sai.c

1681

.reg_offset = 0,

sound/soc/fsl/fsl_sai.c

1692

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1703

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1714

.reg_offset = 0,

sound/soc/fsl/fsl_sai.c

1724

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1735

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1746

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1758

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1769

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1781

.reg_offset = 8,

sound/soc/fsl/fsl_sai.c

1829

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

224

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

309

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

448

unsigned int reg, ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

559

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

760

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

779

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

821

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

90

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.c

936

unsigned int ofs = sai->soc_data->reg_offset;

sound/soc/fsl/fsl_sai.h

244

unsigned int reg_offset;

sound/soc/renesas/rcar/gen.c

198

regf.reg = conf[i].reg_offset;

sound/soc/renesas/rcar/gen.c

38

unsigned int reg_offset;

sound/soc/renesas/rcar/gen.c

46

.reg_offset = offset, \

sound/soc/rockchip/rockchip_i2s.c

27

u32 reg_offset;

sound/soc/rockchip/rockchip_i2s.c

446

regmap_write(i2s->grf, i2s->pins->reg_offset, val);

sound/soc/rockchip/rockchip_i2s.c

643

.reg_offset = 0xe220,

sound/soc/sof/amd/acp-pcm.c

40

platform_params->phy_addr = stream->reg_offset;

sound/soc/sof/amd/acp-stream.c

41

stream->reg_offset = PTE_GRP1_OFFSET;

sound/soc/sof/amd/acp-stream.c

47

stream->reg_offset = PTE_GRP2_OFFSET;

sound/soc/sof/amd/acp-stream.c

53

stream->reg_offset = PTE_GRP3_OFFSET;

sound/soc/sof/amd/acp-stream.c

59

stream->reg_offset = PTE_GRP4_OFFSET;

sound/soc/sof/amd/acp-stream.c

65

stream->reg_offset = PTE_GRP5_OFFSET;

sound/soc/sof/amd/acp-stream.c

71

stream->reg_offset = PTE_GRP6_OFFSET;

sound/soc/sof/amd/acp-stream.c

77

stream->reg_offset = PTE_GRP7_OFFSET;

sound/soc/sof/amd/acp-stream.c

83

stream->reg_offset = PTE_GRP8_OFFSET;

sound/soc/sof/amd/acp-stream.c

93

offsetof(struct scratch_reg_conf, reg_offset);

sound/soc/sof/amd/acp-stream.c

98

phy_addr_offset, stream->reg_offset);

sound/soc/sof/amd/acp-trace.c

60

dtrace_params->buffer.phy_addr = stream->reg_offset;

sound/soc/sof/amd/acp.c

364

unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;

sound/soc/sof/amd/acp.c

368

dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);

sound/soc/sof/amd/acp.c

373

unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;

sound/soc/sof/amd/acp.c

377

snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);

sound/soc/sof/amd/acp.h

181

unsigned int reg_offset[8];

sound/soc/sof/amd/acp.h

196

unsigned int reg_offset;

sound/soc/tegra/tegra210_amx.c

191

amx->soc_data->reg_offset),

sound/soc/tegra/tegra210_amx.c

193

regmap_write(amx->regmap, TEGRA210_AMX_CYA + amx->soc_data->reg_offset, 1);

sound/soc/tegra/tegra210_amx.c

65

regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL + amx->soc_data->reg_offset,

sound/soc/tegra/tegra210_amx.c

694

.reg_offset = TEGRA210_AMX_AUTO_DISABLE_OFFSET,

sound/soc/tegra/tegra210_amx.c

703

.reg_offset = TEGRA210_AMX_AUTO_DISABLE_OFFSET,

sound/soc/tegra/tegra210_amx.c

71

regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA + amx->soc_data->reg_offset,

sound/soc/tegra/tegra210_amx.c

712

.reg_offset = TEGRA264_AMX_AUTO_DISABLE_OFFSET,

sound/soc/tegra/tegra210_amx.h

103

unsigned int reg_offset;