drivers/gpu/drm/adp/adp_drv.c

135

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/adp/adp_drv.c

142

crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);

drivers/gpu/drm/adp/adp_drv.c

143

if (IS_ERR(crtc_state))

drivers/gpu/drm/adp/adp_drv.c

144

return PTR_ERR(crtc_state);

drivers/gpu/drm/adp/adp_drv.c

147

crtc_state,

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

163

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

169

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

171

if (IS_ERR(crtc_state))

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

172

return PTR_ERR(crtc_state);

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

174

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10161

struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10181

if (crtc_state && crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10182

dc_stream_set_cursor_position(crtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10184

update->cursor_position = &crtc_state->stream->cursor_position;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10204

if (crtc_state->cm_is_degamma_srgb &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10211

if (crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10212

if (!dc_stream_set_cursor_attributes(crtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10216

update->cursor_attributes = &crtc_state->stream->cursor_attributes;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10218

if (!dc_stream_set_cursor_position(crtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10222

update->cursor_position = &crtc_state->stream->cursor_position;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10857

static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10860

stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10864

struct dm_crtc_state *crtc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10866

dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11200

struct dm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11233

if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11291

dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11765

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11787

crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11790

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11791

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11796

crtc_state->mode_changed = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12934

struct drm_crtc_state *crtc_state = &dm_crtc_state->base;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12970

if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12997

if (!consider_mode_change && !crtc_state->zpos_changed)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13006

!(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13011

crtc_state->crtc->cursor);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13025

if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13055

plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13056

plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13075

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13080

drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6322

static bool modereset_required(struct drm_crtc_state *crtc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6324

return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6504

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6506

struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6612

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6617

struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8760

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8763

struct drm_atomic_commit *state = crtc_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8767

const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8798

if (!crtc_state->connectors_changed && !crtc_state->mode_changed)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1108

int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1183

int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1188

lut = __extract_blob_lut(crtc_state->degamma_lut, &size);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1196

lut = __extract_blob_lut(crtc_state->gamma_lut, &size);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

586

struct dm_crtc_state *crtc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

635

crtc_state = to_dm_crtc_state(crtc->state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

709

amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

712

if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

741

crtc_state->crc_skip_count = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

768

struct dm_crtc_state *crtc_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

779

crtc_state = to_dm_crtc_state(crtc->state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

780

if (!crtc_state->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

783

stream_state = crtc_state->stream;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

801

if (crtc_state->crc_skip_count < 2) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

802

crtc_state->crc_skip_count += 1;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

62

bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

631

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

635

struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

638

trace_amdgpu_dm_crtc_atomic_check(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

640

amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

643

amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

653

if (crtc_state->enable &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

654

!(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

66

return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

663

if (crtc_state->async_flip &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h

37

bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1353

struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1373

if (crtc_state && crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1379

dc_stream_program_cursor_position(crtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1405

if (crtc_state->cm_is_degamma_srgb &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1412

if (crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1418

if (!dc_stream_program_cursor_attributes(crtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1422

if (!dc_stream_program_cursor_position(crtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

167

__field(const struct drm_crtc_state *, crtc_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

189

__entry->crtc_state = state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

214

__entry->crtc_id, __entry->crtc_state, __entry->state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

44

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

48

const struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2047

enum crtc_state state)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2767

enum crtc_state state = params->tg_wait_for_state_params.state;

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2046

enum crtc_state state)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h

277

enum crtc_state state);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

225

enum crtc_state state)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

758

enum crtc_state state)

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1992

struct timing_generator *tg, enum crtc_state state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

308

enum crtc_state state;

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

126

enum crtc_state state);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

383

enum crtc_state state);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

833

enum crtc_state state)

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

392

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

397

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

80

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

83

struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_state);

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

86

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

89

if (crtc_state->active) {

drivers/gpu/drm/arm/hdlcd_crtc.c

245

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/arm/hdlcd_crtc.c

254

for_each_new_crtc_in_state(state, crtc, crtc_state,

drivers/gpu/drm/arm/hdlcd_crtc.c

257

if (!new_plane_state->fb && crtc_state->active)

drivers/gpu/drm/arm/hdlcd_crtc.c

260

crtc_state,

drivers/gpu/drm/arm/malidp_crtc.c

339

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/arm/malidp_crtc.c

375

drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {

drivers/gpu/drm/arm/malidp_crtc.c

391

drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {

drivers/gpu/drm/arm/malidp_crtc.c

419

if (crtc_state->connectors_changed) {

drivers/gpu/drm/arm/malidp_crtc.c

421

u32 new_mask = crtc_state->connector_mask;

drivers/gpu/drm/arm/malidp_crtc.c

425

crtc_state->connectors_changed = false;

drivers/gpu/drm/arm/malidp_crtc.c

428

ret = malidp_crtc_atomic_check_gamma(crtc, crtc_state);

drivers/gpu/drm/arm/malidp_crtc.c

429

ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, crtc_state);

drivers/gpu/drm/arm/malidp_crtc.c

430

ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, crtc_state);

drivers/gpu/drm/arm/malidp_mw.c

131

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/arm/malidp_mw.c

143

if ((fb->width != crtc_state->mode.hdisplay) ||

drivers/gpu/drm/arm/malidp_mw.c

144

(fb->height != crtc_state->mode.vdisplay)) {

drivers/gpu/drm/arm/malidp_planes.c

265

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/arm/malidp_planes.c

271

if (!crtc_state)

drivers/gpu/drm/arm/malidp_planes.c

274

mc = to_malidp_crtc_state(crtc_state);

drivers/gpu/drm/arm/malidp_planes.c

276

ret = drm_atomic_helper_check_plane_state(state, crtc_state,

drivers/gpu/drm/armada/armada_crtc.c

419

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/armada/armada_crtc.c

423

if (crtc_state->gamma_lut && drm_color_lut_size(crtc_state->gamma_lut) != 256)

drivers/gpu/drm/armada/armada_crtc.c

426

if (crtc_state->color_mgmt_changed)

drivers/gpu/drm/armada/armada_crtc.c

427

crtc_state->planes_changed = true;

drivers/gpu/drm/armada/armada_crtc.c

435

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/armada/armada_crtc.c

441

if (crtc_state->color_mgmt_changed)

drivers/gpu/drm/armada/armada_crtc.c

451

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/armada/armada_crtc.c

463

if (!drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/armada/armada_plane.c

105

interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE;

drivers/gpu/drm/armada/armada_plane.c

89

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/armada/armada_plane.c

98

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/armada/armada_plane.c

99

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c

143

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/ast/ast_dp.c

317

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/ast/ast_dp.c

322

struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);

drivers/gpu/drm/ast/ast_dp.c

386

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/ast/ast_dp.c

389

const struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/ast/ast_dp.c

394

if (drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/ast/ast_mode.c

569

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/ast/ast_mode.c

573

if (!old_fb || (fb->format != old_fb->format) || crtc_state->mode_changed) {

drivers/gpu/drm/ast/ast_mode.c

574

struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);

drivers/gpu/drm/ast/ast_mode.c

701

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/ast/ast_mode.c

702

struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);

drivers/gpu/drm/ast/ast_mode.c

705

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/ast/ast_mode.c

727

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/ast/ast_mode.c

728

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/ast/ast_mode.c

740

if (!crtc_state->enable)

drivers/gpu/drm/ast/ast_mode.c

743

ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/ast/ast_mode.c

747

ast_state = to_ast_crtc_state(crtc_state);

drivers/gpu/drm/ast/ast_mode.c

758

crtc_state->color_mgmt_changed = true;

drivers/gpu/drm/ast/ast_mode.c

760

if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) {

drivers/gpu/drm/ast/ast_mode.c

761

if (crtc_state->gamma_lut->length !=

drivers/gpu/drm/ast/ast_mode.c

764

crtc_state->gamma_lut->length);

drivers/gpu/drm/ast/ast_mode.c

794

if (drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/ast/ast_mode.c

795

vmode = ast_vbios_find_mode(ast, &crtc_state->mode);

drivers/gpu/drm/ast/ast_mode.c

827

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/ast/ast_mode.c

831

struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);

drivers/gpu/drm/ast/ast_mode.c

837

if (crtc_state->enable && crtc_state->color_mgmt_changed) {

drivers/gpu/drm/ast/ast_mode.c

838

if (crtc_state->gamma_lut)

drivers/gpu/drm/ast/ast_mode.c

841

crtc_state->gamma_lut->data);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

730

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

737

crtc_state = drm_atomic_get_new_crtc_state(state, s->crtc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

738

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

740

ret = drm_atomic_helper_check_plane_state(s, crtc_state,

drivers/gpu/drm/bridge/adv7511/adv7511_drv.c

789

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/adv7511/adv7511_drv.c

801

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/adv7511/adv7511_drv.c

802

if (WARN_ON(!crtc_state))

drivers/gpu/drm/bridge/adv7511/adv7511_drv.c

807

adv7511_mode_set(adv, &crtc_state->adjusted_mode);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

870

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

888

if (crtc_state->self_refresh_active && !dp->psr_supported)

drivers/gpu/drm/bridge/analogix/anx7625.c

2547

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/analogix/anx7625.c

2555

anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,

drivers/gpu/drm/bridge/analogix/anx7625.c

2556

&crtc_state->adjusted_mode);

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

710

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

751

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

752

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

893

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

942

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

948

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1757

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1805

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1806

if (WARN_ON(!crtc_state))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1809

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1939

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1960

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1964

const struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1966

struct drm_atomic_commit *state = crtc_state->state;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1997

crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1998

crtc_state->mode_changed = true;

drivers/gpu/drm/bridge/chipone-icn6211.c

597

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/display-connector.c

107

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/display-connector.c

132

prev_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/bridge/display-connector.c

136

crtc_state, conn_state,

drivers/gpu/drm/bridge/display-connector.c

149

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/display-connector.c

170

prev_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/bridge/display-connector.c

174

crtc_state, conn_state, output_fmt,

drivers/gpu/drm/bridge/fsl-ldb.c

131

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/fsl-ldb.c

177

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/bridge/fsl-ldb.c

178

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/fsl-ldb.c

252

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx-ldb-helper.c

35

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx-ldb-helper.h

73

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

104

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

116

next_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

121

crtc_state,

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

58

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

65

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

70

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

308

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

363

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

80

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

88

struct drm_display_mode *adj = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

96

crtc_state, conn_state);

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

105

struct drm_display_mode *adj = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

113

crtc_state, conn_state);

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

127

bridge_state, crtc_state, conn_state);

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

322

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

377

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

96

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

207

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

242

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c

196

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c

220

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c

166

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c

201

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c

79

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

590

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ite-it6263.c

597

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/ite-it6263.c

619

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/bridge/ite-it6263.c

620

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/ite-it6263.c

733

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ite-it6505.c

3127

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/ite-it6505.c

3146

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/ite-it6505.c

3148

if (WARN_ON(!crtc_state))

drivers/gpu/drm/bridge/ite-it6505.c

3151

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/ite-it66121.c

676

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/ite-it66121.c

688

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/bridge/ite-it66121.c

689

if (WARN_ON(!crtc_state))

drivers/gpu/drm/bridge/ite-it66121.c

692

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/ite-it66121.c

745

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ite-it66121.c

767

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ite-it66121.c

819

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/lontium-lt9211.c

462

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/lontium-lt9211.c

519

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/bridge/lontium-lt9211.c

520

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/lontium-lt9211.c

593

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/lontium-lt9611.c

664

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/lontium-lt9611.c

676

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/lontium-lt9611.c

677

if (WARN_ON(!crtc_state))

drivers/gpu/drm/bridge/lontium-lt9611.c

680

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/lontium-lt9611.c

832

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/lvds-codec.c

80

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/nwl-dsi.c

820

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/nwl-dsi.c

823

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/nwl-dsi.c

835

if (crtc_state->active_changed && crtc_state->active)

drivers/gpu/drm/bridge/nwl-dsi.c

836

crtc_state->mode_changed = true;

drivers/gpu/drm/bridge/nwl-dsi.c

928

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/samsung-dsim.c

1737

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/samsung-dsim.c

1764

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/samsung-dsim.c

1768

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/sii902x.c

474

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/sii902x.c

510

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/sii902x.c

513

if (crtc_state->mode.clock < SII902X_MIN_PIXEL_CLOCK_KHZ ||

drivers/gpu/drm/bridge/sii902x.c

514

crtc_state->mode.clock > SII902X_MAX_PIXEL_CLOCK_KHZ)

drivers/gpu/drm/bridge/ssd2825.c

488

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/ssd2825.c

532

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/bridge/ssd2825.c

533

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1527

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1530

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1757

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1764

struct drm_display_mode mode = crtc_state->mode;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2539

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2545

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2546

if (IS_ERR(crtc_state))

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2547

return PTR_ERR(crtc_state);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2549

crtc_state->mode_changed = true;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2658

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2664

struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2787

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2889

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

552

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

564

crtc_state, conn_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

579

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

590

ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

591

&crtc_state->adjusted_mode);

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

594

DRM_MODE_ARG(&crtc_state->mode));

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

702

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

714

crtc_state, conn_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

729

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

740

ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode,

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

741

&crtc_state->adjusted_mode);

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

744

DRM_MODE_ARG(&crtc_state->mode));

drivers/gpu/drm/bridge/tc358767.c

1628

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/tc358767.c

1636

crtc_state->mode.clock * 1000,

drivers/gpu/drm/bridge/tc358767.c

1641

crtc_state->adjusted_mode.clock = adjusted_clock / 1000;

drivers/gpu/drm/bridge/tc358767.c

1644

if (crtc_state->adjusted_mode.clock > 100000)

drivers/gpu/drm/bridge/tc358767.c

1652

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/tc358767.c

1660

crtc_state->mode.clock * 1000,

drivers/gpu/drm/bridge/tc358767.c

1665

crtc_state->adjusted_mode.clock = adjusted_clock / 1000;

drivers/gpu/drm/bridge/tc358767.c

1668

if (crtc_state->adjusted_mode.clock > 154000)

drivers/gpu/drm/bridge/tc358767.c

1884

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/tc358767.c

1908

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/tc358768.c

1232

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/tc358768.c

785

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/tc358768.c

818

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/bridge/tc358768.c

819

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/tc358775.c

385

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/bridge/tc358775.c

387

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/ti-dlpc3433.c

215

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ti-sn65dsi83.c

526

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/bridge/ti-sn65dsi83.c

589

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/bridge/ti-sn65dsi83.c

590

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/ti-sn65dsi83.c

773

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ti-sn65dsi86.c

287

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/bridge/ti-sn65dsi86.c

290

return &crtc_state->adjusted_mode;

drivers/gpu/drm/bridge/ti-tfp410.c

206

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/bridge/ti-tfp410.c

228

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/display/drm_dp_mst_topology.c

4546

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/display/drm_dp_mst_topology.c

4550

if (!crtc_state || !drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/display/drm_dp_mst_topology.c

4553

if (!crtc_state->mode_changed && !crtc_state->connectors_changed)

drivers/gpu/drm/display/drm_dp_mst_topology.c

4603

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/display/drm_dp_mst_topology.c

4618

for_each_new_crtc_in_state(state, crtc, crtc_state, j) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

4621

drm_crtc_commit_get(crtc_state->commit);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4708

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/display/drm_dp_mst_topology.c

4712

crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4713

if (crtc_state && drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

4723

crtc_state = drm_atomic_get_new_crtc_state(state, old_conn_state->crtc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4724

if (crtc_state && drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

5450

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5477

crtc_state = drm_atomic_get_crtc_state(mst_state->base.state, crtc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

5479

if (IS_ERR(crtc_state))

drivers/gpu/drm/display/drm_dp_mst_topology.c

5480

return PTR_ERR(crtc_state);

drivers/gpu/drm/display/drm_dp_mst_topology.c

5485

crtc_state->mode_changed = true;

drivers/gpu/drm/display/drm_hdmi_state_helper.c

352

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/display/drm_hdmi_state_helper.c

363

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/display/drm_hdmi_state_helper.c

364

if (!crtc_state)

drivers/gpu/drm/display/drm_hdmi_state_helper.c

367

return &crtc_state->mode;

drivers/gpu/drm/display/drm_hdmi_state_helper.c

888

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/display/drm_hdmi_state_helper.c

890

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/display/drm_hdmi_state_helper.c

891

if (IS_ERR(crtc_state))

drivers/gpu/drm/display/drm_hdmi_state_helper.c

892

return PTR_ERR(crtc_state);

drivers/gpu/drm/display/drm_hdmi_state_helper.c

894

crtc_state->mode_changed = true;

drivers/gpu/drm/drm_atomic.c

1332

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

1334

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/drm_atomic.c

1336

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic.c

1337

return ERR_CAST(crtc_state);

drivers/gpu/drm/drm_atomic.c

1516

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

1519

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic.c

1520

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic.c

1521

return PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic.c

1537

if (!(crtc_state->connector_mask & drm_connector_mask(connector)))

drivers/gpu/drm/drm_atomic.c

1918

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

1924

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic.c

1925

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic.c

1926

return PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic.c

1936

ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL);

drivers/gpu/drm/drm_atomic.c

1940

crtc_state->active = false;

drivers/gpu/drm/drm_atomic.c

1954

ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);

drivers/gpu/drm/drm_atomic.c

1958

crtc_state->active = true;

drivers/gpu/drm/drm_atomic.c

2016

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

2033

for_each_new_crtc_in_state(state, crtc, crtc_state, i)

drivers/gpu/drm/drm_atomic.c

2034

drm_atomic_crtc_print_state(p, crtc_state);

drivers/gpu/drm/drm_atomic.c

369

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

374

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic.c

375

if (crtc_state)

drivers/gpu/drm/drm_atomic.c

376

return crtc_state;

drivers/gpu/drm/drm_atomic.c

382

crtc_state = crtc->funcs->atomic_duplicate_state(crtc);

drivers/gpu/drm/drm_atomic.c

383

if (!crtc_state)

drivers/gpu/drm/drm_atomic.c

386

state->crtcs[index].state_to_destroy = crtc_state;

drivers/gpu/drm/drm_atomic.c

388

state->crtcs[index].new_state = crtc_state;

drivers/gpu/drm/drm_atomic.c

390

crtc_state->state = state;

drivers/gpu/drm/drm_atomic.c

393

crtc->base.id, crtc->name, crtc_state, state);

drivers/gpu/drm/drm_atomic.c

395

return crtc_state;

drivers/gpu/drm/drm_atomic.c

487

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

506

crtc_state = drm_atomic_get_new_crtc_state(state->state,

drivers/gpu/drm/drm_atomic.c

509

if (writeback_job->fb && !crtc_state->active) {

drivers/gpu/drm/drm_atomic.c

583

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic.c

585

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/drm_atomic.c

587

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic.c

588

return ERR_CAST(crtc_state);

drivers/gpu/drm/drm_atomic_helper.c

100

if (WARN_ON(!crtc_state))

drivers/gpu/drm/drm_atomic_helper.c

103

crtc_state->planes_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

167

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

199

crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

205

if (!crtc_state->connector_mask) {

drivers/gpu/drm/drm_atomic_helper.c

206

ret = drm_atomic_set_mode_prop_for_crtc(crtc_state,

drivers/gpu/drm/drm_atomic_helper.c

211

crtc_state->active = false;

drivers/gpu/drm/drm_atomic_helper.c

2112

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

2119

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/drm_atomic_helper.c

2120

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/drm_atomic_helper.c

225

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

240

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

242

crtc_state->encoder_mask &=

drivers/gpu/drm/drm_atomic_helper.c

251

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

253

crtc_state->encoder_mask |=

drivers/gpu/drm/drm_atomic_helper.c

265

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

285

crtc_state = drm_atomic_get_new_crtc_state(state, encoder_crtc);

drivers/gpu/drm/drm_atomic_helper.c

286

crtc_state->connectors_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

301

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

3028

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

3030

crtc_state = old_plane_state->crtc->state;

drivers/gpu/drm/drm_atomic_helper.c

3032

if (drm_atomic_crtc_needs_modeset(crtc_state) &&

drivers/gpu/drm/drm_atomic_helper.c

308

crtc_state = drm_atomic_get_new_crtc_state(state, old_connector_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

309

crtc_state->connectors_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

313

crtc_state = drm_atomic_get_new_crtc_state(state, new_connector_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

314

crtc_state->connectors_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

327

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/drm_atomic_helper.c

352

added_by_user && crtc_state->active) {

drivers/gpu/drm/drm_atomic_helper.c

3562

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

3573

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3574

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3575

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_helper.c

3579

crtc_state->active = false;

drivers/gpu/drm/drm_atomic_helper.c

3581

ret = drm_atomic_set_mode_prop_for_crtc(crtc_state, NULL);

drivers/gpu/drm/drm_atomic_helper.c

3638

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

3647

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3648

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3649

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_helper.c

3653

crtc_state->connectors_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

3737

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

3739

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3740

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3741

err = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_helper.c

3938

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

3941

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3942

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic_helper.c

3943

return PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_helper.c

3945

crtc_state->event = event;

drivers/gpu/drm/drm_atomic_helper.c

3946

crtc_state->async_flip = flags & DRM_MODE_PAGE_FLIP_ASYNC;

drivers/gpu/drm/drm_atomic_helper.c

3959

if (!crtc_state->active) {

drivers/gpu/drm/drm_atomic_helper.c

4038

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

404

crtc_state->connectors_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

4051

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

4052

if (WARN_ON(!crtc_state)) {

drivers/gpu/drm/drm_atomic_helper.c

4056

crtc_state->target_vblank = target;

drivers/gpu/drm/drm_atomic_helper.c

4087

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_atomic_helper.c

558

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

565

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

566

if (!crtc_state)

drivers/gpu/drm/drm_atomic_helper.c

568

if (!crtc_state->mode_changed && !crtc_state->connectors_changed)

drivers/gpu/drm/drm_atomic_helper.c

571

mode = &crtc_state->mode;

drivers/gpu/drm/drm_atomic_helper.c

585

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/drm_atomic_helper.c

588

drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) {

drivers/gpu/drm/drm_atomic_helper.c

594

if ((crtc_state->encoder_mask & drm_enc->possible_clones) !=

drivers/gpu/drm/drm_atomic_helper.c

595

crtc_state->encoder_mask) {

drivers/gpu/drm/drm_atomic_helper.c

597

crtc->base.id, crtc_state->encoder_mask);

drivers/gpu/drm/drm_atomic_helper.c

85

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_helper.c

88

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/drm_atomic_helper.c

894

const struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_atomic_helper.c

907

WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

91

if (WARN_ON(!crtc_state))

drivers/gpu/drm/drm_atomic_helper.c

923

if (!crtc_state->enable && !can_update_disabled) {

drivers/gpu/drm/drm_atomic_helper.c

94

crtc_state->planes_changed = true;

drivers/gpu/drm/drm_atomic_helper.c

942

if (crtc_state->enable)

drivers/gpu/drm/drm_atomic_helper.c

943

drm_mode_get_hv_timing(&crtc_state->mode, &clip.x2, &clip.y2);

drivers/gpu/drm/drm_atomic_helper.c

98

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

984

int drm_atomic_helper_check_crtc_primary_plane(struct drm_crtc_state *crtc_state)

drivers/gpu/drm/drm_atomic_helper.c

986

struct drm_crtc *crtc = crtc_state->crtc;

drivers/gpu/drm/drm_atomic_helper.c

991

drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

drivers/gpu/drm/drm_atomic_state_helper.c

104

crtc->state = crtc_state;

drivers/gpu/drm/drm_atomic_state_helper.c

117

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/drm_atomic_state_helper.c

123

__drm_atomic_helper_crtc_reset(crtc, crtc_state);

drivers/gpu/drm/drm_atomic_state_helper.c

598

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_state_helper.c

605

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_state_helper.c

606

if (!crtc_state)

drivers/gpu/drm/drm_atomic_state_helper.c

610

crtc_state->mode_changed = true;

drivers/gpu/drm/drm_atomic_state_helper.c

623

crtc_state->connectors_changed = true;

drivers/gpu/drm/drm_atomic_state_helper.c

74

__drm_atomic_helper_crtc_state_reset(struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_atomic_state_helper.c

77

crtc_state->crtc = crtc;

drivers/gpu/drm/drm_atomic_state_helper.c

78

crtc_state->background_color = DRM_ARGB64_PREP(0xffff, 0, 0, 0);

drivers/gpu/drm/drm_atomic_state_helper.c

96

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/drm_atomic_state_helper.c

98

if (crtc_state)

drivers/gpu/drm/drm_atomic_state_helper.c

99

__drm_atomic_helper_crtc_state_reset(crtc_state, crtc);

drivers/gpu/drm/drm_atomic_uapi.c

1139

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

1163

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_uapi.c

1164

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_atomic_uapi.c

1165

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_uapi.c

1178

crtc_state->active = active;

drivers/gpu/drm/drm_atomic_uapi.c

1238

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

1240

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_atomic_uapi.c

1241

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_atomic_uapi.c

1242

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_uapi.c

1247

ret = drm_atomic_crtc_get_property(crtc, crtc_state,

drivers/gpu/drm/drm_atomic_uapi.c

1254

crtc_state, prop, prop_value);

drivers/gpu/drm/drm_atomic_uapi.c

1422

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

1430

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/drm_atomic_uapi.c

1433

fence_ptr = get_out_fence_for_crtc(crtc_state->state, crtc);

drivers/gpu/drm/drm_atomic_uapi.c

1442

crtc_state->event = e;

drivers/gpu/drm/drm_atomic_uapi.c

1446

struct drm_pending_vblank_event *e = crtc_state->event;

drivers/gpu/drm/drm_atomic_uapi.c

1455

crtc_state->event = NULL;

drivers/gpu/drm/drm_atomic_uapi.c

1484

crtc_state->event->base.fence = fence;

drivers/gpu/drm/drm_atomic_uapi.c

1546

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

1558

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/drm_atomic_uapi.c

1559

struct drm_pending_vblank_event *event = crtc_state->event;

drivers/gpu/drm/drm_atomic_uapi.c

1567

crtc_state->event = NULL;

drivers/gpu/drm/drm_atomic_uapi.c

1593

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

1596

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/drm_atomic_uapi.c

1597

crtc_state->async_flip = true;

drivers/gpu/drm/drm_atomic_uapi.c

194

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

199

crtc_state = drm_atomic_get_crtc_state(plane_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

201

if (WARN_ON(IS_ERR(crtc_state)))

drivers/gpu/drm/drm_atomic_uapi.c

202

return PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_uapi.c

204

crtc_state->plane_mask &= ~drm_plane_mask(plane);

drivers/gpu/drm/drm_atomic_uapi.c

210

crtc_state = drm_atomic_get_crtc_state(plane_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

212

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic_uapi.c

213

return PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_uapi.c

214

crtc_state->plane_mask |= drm_plane_mask(plane);

drivers/gpu/drm/drm_atomic_uapi.c

316

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_atomic_uapi.c

322

crtc_state = drm_atomic_get_new_crtc_state(conn_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

325

crtc_state->connector_mask &=

drivers/gpu/drm/drm_atomic_uapi.c

333

crtc_state = drm_atomic_get_crtc_state(conn_state->state, crtc);

drivers/gpu/drm/drm_atomic_uapi.c

334

if (IS_ERR(crtc_state))

drivers/gpu/drm/drm_atomic_uapi.c

335

return PTR_ERR(crtc_state);

drivers/gpu/drm/drm_atomic_uapi.c

337

crtc_state->connector_mask |=

drivers/gpu/drm/drm_blend.c

464

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/drm_blend.c

466

struct drm_atomic_commit *state = crtc_state->state;

drivers/gpu/drm/drm_blend.c

485

drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

drivers/gpu/drm/drm_blend.c

506

crtc_state->zpos_changed = true;

drivers/gpu/drm/drm_bridge.c

1041

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_bridge.c

1048

bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/drm_bridge.c

1054

crtc_state, conn_state);

drivers/gpu/drm/drm_bridge.c

1058

if (!bridge->funcs->mode_fixup(bridge, &crtc_state->mode,

drivers/gpu/drm/drm_bridge.c

1059

&crtc_state->adjusted_mode))

drivers/gpu/drm/drm_bridge.c

1068

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_bridge.c

1079

cur_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/drm_bridge.c

1091

prev_bridge, crtc_state,

drivers/gpu/drm/drm_bridge.c

1119

crtc_state,

drivers/gpu/drm/drm_bridge.c

1137

crtc_state, conn_state,

drivers/gpu/drm/drm_bridge.c

1188

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_bridge.c

1201

last_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/drm_bridge.c

1216

crtc_state,

drivers/gpu/drm/drm_bridge.c

1237

ret = select_bus_fmt_recursive(bridge, last_bridge, crtc_state,

drivers/gpu/drm/drm_bridge.c

1314

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/drm_bridge.c

1325

ret = drm_atomic_bridge_chain_select_bus_fmts(bridge, crtc_state,

drivers/gpu/drm/drm_bridge.c

1343

crtc_state->state);

drivers/gpu/drm/drm_bridge.c

1345

ret = drm_atomic_bridge_check(iter, crtc_state, conn_state);

drivers/gpu/drm/drm_client_modeset.c

1095

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_client_modeset.c

1097

crtc_state->active = false;

drivers/gpu/drm/drm_color_mgmt.c

284

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_color_mgmt.c

325

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_color_mgmt.c

326

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_color_mgmt.c

327

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_color_mgmt.c

332

replaced = drm_property_replace_blob(&crtc_state->degamma_lut,

drivers/gpu/drm/drm_color_mgmt.c

334

replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);

drivers/gpu/drm/drm_color_mgmt.c

335

replaced |= drm_property_replace_blob(&crtc_state->gamma_lut,

drivers/gpu/drm/drm_color_mgmt.c

337

crtc_state->color_mgmt_changed |= replaced;

drivers/gpu/drm/drm_crtc.c

986

bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state)

drivers/gpu/drm/drm_crtc.c

988

if (!crtc_state)

drivers/gpu/drm/drm_crtc.c

991

return hweight32(crtc_state->encoder_mask) > 1;

drivers/gpu/drm/drm_damage_helper.c

72

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_damage_helper.c

75

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/drm_damage_helper.c

78

if (WARN_ON(!crtc_state))

drivers/gpu/drm/drm_damage_helper.c

81

if (drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/drm_fb_helper.c

855

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_fb_helper.c

884

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_fb_helper.c

885

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_fb_helper.c

886

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_fb_helper.c

895

replaced = drm_property_replace_blob(&crtc_state->degamma_lut,

drivers/gpu/drm/drm_fb_helper.c

897

replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);

drivers/gpu/drm/drm_fb_helper.c

898

replaced |= drm_property_replace_blob(&crtc_state->gamma_lut,

drivers/gpu/drm/drm_fb_helper.c

900

crtc_state->color_mgmt_changed |= replaced;

drivers/gpu/drm/drm_framebuffer.c

1044

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_framebuffer.c

1051

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/drm_framebuffer.c

1057

crtc_state->active = false;

drivers/gpu/drm/drm_framebuffer.c

1058

ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL);

drivers/gpu/drm/drm_mipi_dbi.c

439

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_mipi_dbi.c

442

if (!crtc_state->enable)

drivers/gpu/drm/drm_mipi_dbi.c

445

ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/drm_plane_helper.c

121

struct drm_crtc_state crtc_state = {

drivers/gpu/drm/drm_plane_helper.c

128

ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,

drivers/gpu/drm/drm_self_refresh_helper.c

111

crtc_state->active = false;

drivers/gpu/drm/drm_self_refresh_helper.c

112

crtc_state->self_refresh_active = true;

drivers/gpu/drm/drm_self_refresh_helper.c

191

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_self_refresh_helper.c

195

for_each_old_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/drm_self_refresh_helper.c

196

if (crtc_state->self_refresh_active) {

drivers/gpu/drm/drm_self_refresh_helper.c

204

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/drm_self_refresh_helper.c

209

if (crtc_state->self_refresh_active)

drivers/gpu/drm/drm_self_refresh_helper.c

79

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_self_refresh_helper.c

93

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/drm_self_refresh_helper.c

94

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/drm_self_refresh_helper.c

95

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/drm_self_refresh_helper.c

99

if (!crtc_state->enable)

drivers/gpu/drm/drm_simple_kms_helper.c

177

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/drm_simple_kms_helper.c

181

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/drm_simple_kms_helper.c

184

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/drm_simple_kms_helper.c

197

return pipe->funcs->check(pipe, plane_state, crtc_state);

drivers/gpu/drm/drm_simple_kms_helper.c

58

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_simple_kms_helper.c

61

if (!crtc_state->enable)

drivers/gpu/drm/drm_simple_kms_helper.c

64

ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/drm_vblank_helper.c

55

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/drm_vblank_helper.c

60

event = crtc_state->event;

drivers/gpu/drm/drm_vblank_helper.c

61

crtc_state->event = NULL;

drivers/gpu/drm/exynos/exynos_drm_crtc.c

53

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/exynos/exynos_drm_crtc.c

57

if (!crtc_state->enable)

drivers/gpu/drm/exynos/exynos_drm_crtc.c

61

return exynos_crtc->ops->atomic_check(exynos_crtc, crtc_state);

drivers/gpu/drm/exynos/exynos_drm_plane.c

61

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/exynos/exynos_drm_plane.c

63

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/gma500/gma_display.c

506

kfree(gma_crtc->crtc_state);

drivers/gpu/drm/gma500/gma_display.c

580

struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;

drivers/gpu/drm/gma500/gma_display.c

585

if (!crtc_state) {

drivers/gpu/drm/gma500/gma_display.c

590

crtc_state->saveDSPCNTR = REG_READ(map->cntr);

drivers/gpu/drm/gma500/gma_display.c

591

crtc_state->savePIPECONF = REG_READ(map->conf);

drivers/gpu/drm/gma500/gma_display.c

592

crtc_state->savePIPESRC = REG_READ(map->src);

drivers/gpu/drm/gma500/gma_display.c

593

crtc_state->saveFP0 = REG_READ(map->fp0);

drivers/gpu/drm/gma500/gma_display.c

594

crtc_state->saveFP1 = REG_READ(map->fp1);

drivers/gpu/drm/gma500/gma_display.c

595

crtc_state->saveDPLL = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

596

crtc_state->saveHTOTAL = REG_READ(map->htotal);

drivers/gpu/drm/gma500/gma_display.c

597

crtc_state->saveHBLANK = REG_READ(map->hblank);

drivers/gpu/drm/gma500/gma_display.c

598

crtc_state->saveHSYNC = REG_READ(map->hsync);

drivers/gpu/drm/gma500/gma_display.c

599

crtc_state->saveVTOTAL = REG_READ(map->vtotal);

drivers/gpu/drm/gma500/gma_display.c

600

crtc_state->saveVBLANK = REG_READ(map->vblank);

drivers/gpu/drm/gma500/gma_display.c

601

crtc_state->saveVSYNC = REG_READ(map->vsync);

drivers/gpu/drm/gma500/gma_display.c

602

crtc_state->saveDSPSTRIDE = REG_READ(map->stride);

drivers/gpu/drm/gma500/gma_display.c

605

crtc_state->saveDSPSIZE = REG_READ(map->size);

drivers/gpu/drm/gma500/gma_display.c

606

crtc_state->saveDSPPOS = REG_READ(map->pos);

drivers/gpu/drm/gma500/gma_display.c

608

crtc_state->saveDSPBASE = REG_READ(map->base);

drivers/gpu/drm/gma500/gma_display.c

612

crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));

drivers/gpu/drm/gma500/gma_display.c

623

struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;

drivers/gpu/drm/gma500/gma_display.c

628

if (!crtc_state) {

drivers/gpu/drm/gma500/gma_display.c

633

if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {

drivers/gpu/drm/gma500/gma_display.c

635

crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/gma_display.c

640

REG_WRITE(map->fp0, crtc_state->saveFP0);

drivers/gpu/drm/gma500/gma_display.c

643

REG_WRITE(map->fp1, crtc_state->saveFP1);

drivers/gpu/drm/gma500/gma_display.c

646

REG_WRITE(map->dpll, crtc_state->saveDPLL);

drivers/gpu/drm/gma500/gma_display.c

650

REG_WRITE(map->htotal, crtc_state->saveHTOTAL);

drivers/gpu/drm/gma500/gma_display.c

651

REG_WRITE(map->hblank, crtc_state->saveHBLANK);

drivers/gpu/drm/gma500/gma_display.c

652

REG_WRITE(map->hsync, crtc_state->saveHSYNC);

drivers/gpu/drm/gma500/gma_display.c

653

REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);

drivers/gpu/drm/gma500/gma_display.c

654

REG_WRITE(map->vblank, crtc_state->saveVBLANK);

drivers/gpu/drm/gma500/gma_display.c

655

REG_WRITE(map->vsync, crtc_state->saveVSYNC);

drivers/gpu/drm/gma500/gma_display.c

656

REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);

drivers/gpu/drm/gma500/gma_display.c

658

REG_WRITE(map->size, crtc_state->saveDSPSIZE);

drivers/gpu/drm/gma500/gma_display.c

659

REG_WRITE(map->pos, crtc_state->saveDSPPOS);

drivers/gpu/drm/gma500/gma_display.c

661

REG_WRITE(map->src, crtc_state->savePIPESRC);

drivers/gpu/drm/gma500/gma_display.c

662

REG_WRITE(map->base, crtc_state->saveDSPBASE);

drivers/gpu/drm/gma500/gma_display.c

663

REG_WRITE(map->conf, crtc_state->savePIPECONF);

drivers/gpu/drm/gma500/gma_display.c

667

REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);

drivers/gpu/drm/gma500/gma_display.c

668

REG_WRITE(map->base, crtc_state->saveDSPBASE);

drivers/gpu/drm/gma500/gma_display.c

674

REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);

drivers/gpu/drm/gma500/psb_intel_display.c

489

gma_crtc->crtc_state =

drivers/gpu/drm/gma500/psb_intel_display.c

491

if (!gma_crtc->crtc_state) {

drivers/gpu/drm/gma500/psb_intel_drv.h

162

struct psb_intel_crtc_state *crtc_state;

drivers/gpu/drm/gud/gud_pipe.c

460

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/gud/gud_pipe.c

473

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/gud/gud_pipe.c

475

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/gud/gud_pipe.c

486

crtc_state->mode_changed = true;

drivers/gpu/drm/gud/gud_pipe.c

488

mode = &crtc_state->mode;

drivers/gpu/drm/gud/gud_pipe.c

492

crtc_state->mode_changed = true;

drivers/gpu/drm/gud/gud_pipe.c

494

if (!crtc_state->mode_changed && !crtc_state->connectors_changed)

drivers/gpu/drm/gud/gud_pipe.c

498

if (hweight32(crtc_state->connector_mask) != 1)

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

100

if (!crtc_state->enable)

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

104

crtc_state->adjusted_mode.hdisplay ||

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

106

crtc_state->adjusted_mode.vdisplay) {

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

79

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

86

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

87

if (IS_ERR(crtc_state))

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

88

return PTR_ERR(crtc_state);

drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c

683

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

768

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

786

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

787

if (IS_ERR(crtc_state))

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

788

return PTR_ERR(crtc_state);

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

801

if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

802

crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

110

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

114

crtc_state->mode.hdisplay,

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

115

crtc_state->mode.vdisplay,

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

145

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

149

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

151

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

1031

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

1079

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

1131

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

1226

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

1233

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/g4x_dp.c

1235

ret = intel_dp_compute_config(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/g4x_dp.c

1239

g4x_dp_set_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/g4x_dp.c

320

static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

322

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/g4x_dp.c

324

if (crtc_state->has_pch_encoder) {

drivers/gpu/drm/i915/display/g4x_dp.c

325

intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/g4x_dp.c

326

intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/g4x_dp.c

328

intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,

drivers/gpu/drm/i915/display/g4x_dp.c

329

&crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/g4x_dp.c

330

intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,

drivers/gpu/drm/i915/display/g4x_dp.c

331

&crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/g4x_dp.c

466

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

472

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/g4x_dp.c

479

intel_audio_codec_enable(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/g4x_dp.c

576

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

604

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

617

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

645

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

657

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

663

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

802

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

808

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

824

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

904

vlv_set_phy_signal_level(encoder, crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

910

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_dp.c

987

chv_set_phy_signal_level(encoder, crtc_state,

drivers/gpu/drm/i915/display/g4x_hdmi.c

108

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/g4x_hdmi.c

118

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/g4x_hdmi.c

120

if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state))

drivers/gpu/drm/i915/display/g4x_hdmi.c

130

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/g4x_hdmi.c

134

struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);

drivers/gpu/drm/i915/display/g4x_hdmi.c

135

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/g4x_hdmi.c

138

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/g4x_hdmi.c

141

crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);

drivers/gpu/drm/i915/display/g4x_hdmi.c

143

crtc_state->has_hdmi_sink =

drivers/gpu/drm/i915/display/g4x_hdmi.c

144

intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/g4x_hdmi.c

146

return intel_hdmi_compute_config(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/g4x_hdmi.c

232

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/g4x_hdmi.c

238

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/g4x_hdmi.c

241

drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);

drivers/gpu/drm/i915/display/g4x_hdmi.c

246

intel_audio_codec_enable(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/g4x_hdmi.c

28

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/g4x_hdmi.c

31

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/g4x_hdmi.c

33

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/g4x_hdmi.c

39

if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range)

drivers/gpu/drm/i915/display/g4x_hdmi.c

46

if (crtc_state->pipe_bpp > 24)

drivers/gpu/drm/i915/display/g4x_hdmi.c

51

if (crtc_state->has_hdmi_sink)

drivers/gpu/drm/i915/display/g4x_hdmi.c

623

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/g4x_hdmi.c

642

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/g4x_hdmi.c

643

crtc_state->mode_changed = true;

drivers/gpu/drm/i915/display/hsw_ips.c

19

static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.c

192

static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.c

194

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/hsw_ips.c

199

if (crtc_state->pipe_bpp > 24)

drivers/gpu/drm/i915/display/hsw_ips.c

205

static int _hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.c

207

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

21

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

210

return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);

drivers/gpu/drm/i915/display/hsw_ips.c

216

int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.c

218

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

221

if (!hsw_crtc_state_ips_capable(crtc_state))

drivers/gpu/drm/i915/display/hsw_ips.c

224

min_cdclk = _hsw_ips_min_cdclk(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

24

if (!crtc_state->ips_enabled)

drivers/gpu/drm/i915/display/hsw_ips.c

240

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/hsw_ips.c

243

crtc_state->ips_enabled = false;

drivers/gpu/drm/i915/display/hsw_ips.c

245

if (!hsw_crtc_state_ips_capable(crtc_state))

drivers/gpu/drm/i915/display/hsw_ips.c

248

if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq)

drivers/gpu/drm/i915/display/hsw_ips.c

260

if (crtc_state->crc_enabled)

drivers/gpu/drm/i915/display/hsw_ips.c

264

if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))

drivers/gpu/drm/i915/display/hsw_ips.c

267

crtc_state->ips_enabled = true;

drivers/gpu/drm/i915/display/hsw_ips.c

272

void hsw_ips_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.c

274

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

275

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/hsw_ips.c

281

crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;

drivers/gpu/drm/i915/display/hsw_ips.c

288

crtc_state->ips_enabled = true;

drivers/gpu/drm/i915/display/hsw_ips.c

306

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/hsw_ips.c

315

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/hsw_ips.c

317

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/hsw_ips.c

320

if (crtc_state->uapi.commit &&

drivers/gpu/drm/i915/display/hsw_ips.c

321

!try_wait_for_completion(&crtc_state->uapi.commit->hw_done))

drivers/gpu/drm/i915/display/hsw_ips.c

324

hsw_ips_enable(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

33

!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));

drivers/gpu/drm/i915/display/hsw_ips.c

65

bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.c

67

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.c

70

if (!crtc_state->ips_enabled)

drivers/gpu/drm/i915/display/hsw_ips.h

16

bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.h

22

int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.h

25

void hsw_ips_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/hsw_ips.h

28

static inline bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.h

45

static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/hsw_ips.h

54

static inline void hsw_ips_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

327

i9xx_plane_check(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

337

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

373

static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

375

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

376

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/i9xx_plane.c

379

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/i9xx_plane.c

382

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/i9xx_plane.c

391

static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

414

static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

427

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/i9xx_plane.c

429

i9xx_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/i9xx_plane.c

432

if (crtc_state->double_wide)

drivers/gpu/drm/i915/display/i9xx_plane.c

440

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

469

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

478

dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

482

crtc_state->async_flip_planes & BIT(plane->id))

drivers/gpu/drm/i915/display/i9xx_plane.c

524

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

533

i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

534

i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

539

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

555

dspcntr = i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

602

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

607

u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

620

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1024

static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1027

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1031

struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1040

static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1043

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1050

struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1059

static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1063

static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1066

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1072

if (!intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1073

dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1075

dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1080

struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1083

wm = g4x_compute_wm(crtc_state, plane_state, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1096

wm = ilk_compute_fbc_wm(crtc_state, plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1112

dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

1115

dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

1122

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1123

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1124

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1129

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,

drivers/gpu/drm/i915/display/i9xx_wm.c

1130

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1136

static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1139

const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1144

static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1147

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1152

return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

1153

g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

1154

g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1200

static int _g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1202

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1203

struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

1204

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

drivers/gpu/drm/i915/display/i9xx_wm.c

1210

if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))

drivers/gpu/drm/i915/display/i9xx_wm.c

1213

raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1218

if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))

drivers/gpu/drm/i915/display/i9xx_wm.c

1221

raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1229

if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))

drivers/gpu/drm/i915/display/i9xx_wm.c

1232

raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1263

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

1278

if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

1285

return _g4x_compute_pipe_wm(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1455

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

1459

crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;

drivers/gpu/drm/i915/display/i9xx_wm.c

1468

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

1471

if (!crtc_state->wm.need_postvbl_update)

drivers/gpu/drm/i915/display/i9xx_wm.c

1475

crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

1511

static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1518

&crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/i9xx_wm.c

1524

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

1528

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/i9xx_wm.c

1554

static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1556

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1557

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1559

&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];

drivers/gpu/drm/i915/display/i9xx_wm.c

1560

struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

1561

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

drivers/gpu/drm/i915/display/i9xx_wm.c

1666

static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1669

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1673

struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1682

static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1685

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1691

if (!intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1692

dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1697

struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1698

int wm = vlv_compute_wm_level(crtc_state, plane_state, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1709

dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

1716

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1717

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1718

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1723

static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1727

&crtc_state->wm.vlv.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1729

&crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

1734

static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)

drivers/gpu/drm/i915/display/i9xx_wm.c

1736

return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

1737

vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

1738

vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

1739

vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1742

static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1744

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1745

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1746

struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

1748

&crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

1749

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

drivers/gpu/drm/i915/display/i9xx_wm.c

1764

const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

1767

if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))

drivers/gpu/drm/i915/display/i9xx_wm.c

1802

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

1817

if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

1830

if (intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

1843

&crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

1846

ret = vlv_compute_fifo(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1850

if (intel_crtc_needs_modeset(crtc_state) ||

drivers/gpu/drm/i915/display/i9xx_wm.c

1853

crtc_state->fifo_changed = true;

drivers/gpu/drm/i915/display/i9xx_wm.c

1856

return _vlv_compute_pipe_wm(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1867

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

1870

&crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

1874

if (!crtc_state->fifo_changed)

drivers/gpu/drm/i915/display/i9xx_wm.c

2108

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

2112

crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;

drivers/gpu/drm/i915/display/i9xx_wm.c

2121

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

2124

if (!crtc_state->wm.need_postvbl_update)

drivers/gpu/drm/i915/display/i9xx_wm.c

2128

crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

2446

static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2456

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2461

method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);

drivers/gpu/drm/i915/display/i9xx_wm.c

2466

method2 = ilk_wm_method2(crtc_state->pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2467

crtc_state->hw.pipe_mode.crtc_htotal,

drivers/gpu/drm/i915/display/i9xx_wm.c

2478

static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2488

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2493

method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);

drivers/gpu/drm/i915/display/i9xx_wm.c

2494

method2 = ilk_wm_method2(crtc_state->pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2495

crtc_state->hw.pipe_mode.crtc_htotal,

drivers/gpu/drm/i915/display/i9xx_wm.c

2505

static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2514

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2519

return ilk_wm_method2(crtc_state->pixel_rate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2520

crtc_state->hw.pipe_mode.crtc_htotal,

drivers/gpu/drm/i915/display/i9xx_wm.c

2526

static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2532

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2711

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2729

result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,

drivers/gpu/drm/i915/display/i9xx_wm.c

2731

result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);

drivers/gpu/drm/i915/display/i9xx_wm.c

2735

result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

2738

result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);

drivers/gpu/drm/i915/display/i9xx_wm.c

284

static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

286

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

287

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

288

struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2922

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

2933

pipe_wm = &crtc_state->wm.ilk.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

2935

intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2944

pipe_wm->pipe_enabled = crtc_state->hw.active;

drivers/gpu/drm/i915/display/i9xx_wm.c

2945

pipe_wm->sprites_enabled = crtc_state->active_planes & BIT(PLANE_SPRITE0);

drivers/gpu/drm/i915/display/i9xx_wm.c

2946

pipe_wm->sprites_scaled = crtc_state->scaled_planes & BIT(PLANE_SPRITE0);

drivers/gpu/drm/i915/display/i9xx_wm.c

2959

ilk_compute_wm_level(display, crtc, 0, crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2970

ilk_compute_wm_level(display, crtc, level, crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

3467

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3471

crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;

drivers/gpu/drm/i915/display/i9xx_wm.c

3480

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3483

if (!crtc_state->wm.need_postvbl_update)

drivers/gpu/drm/i915/display/i9xx_wm.c

3487

crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

3496

struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/i9xx_wm.c

3497

struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

3541

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3543

crtc_state = intel_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/i9xx_wm.c

3544

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

3545

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

3547

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3552

crtc_state->inherited = true;

drivers/gpu/drm/i915/display/i9xx_wm.c

3582

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3622

for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3623

crtc_state->wm.need_postvbl_update = true;

drivers/gpu/drm/i915/display/i9xx_wm.c

3626

to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;

drivers/gpu/drm/i915/display/i9xx_wm.c

3773

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3801

raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

3809

raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

3819

raw = &crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

3828

g4x_raw_plane_wm_set(crtc_state, level,

drivers/gpu/drm/i915/display/i9xx_wm.c

3830

g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

3834

crtc_state->wm.g4x.optimal = *active;

drivers/gpu/drm/i915/display/i9xx_wm.c

3835

crtc_state->wm.g4x.intermediate = *active;

drivers/gpu/drm/i915/display/i9xx_wm.c

3866

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3878

&crtc_state->wm.g4x.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

3888

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3892

ret = _g4x_compute_pipe_wm(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

3895

crtc_state->wm.g4x.intermediate =

drivers/gpu/drm/i915/display/i9xx_wm.c

3896

crtc_state->wm.g4x.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

3897

crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

3955

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3959

&crtc_state->wm.vlv.fifo_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3964

vlv_get_fifo_size(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

3971

&crtc_state->wm.vlv.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

3987

vlv_raw_plane_wm_set(crtc_state, level,

drivers/gpu/drm/i915/display/i9xx_wm.c

3991

crtc_state->wm.vlv.optimal = *active;

drivers/gpu/drm/i915/display/i9xx_wm.c

3992

crtc_state->wm.vlv.intermediate = *active;

drivers/gpu/drm/i915/display/i9xx_wm.c

4018

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

4030

&crtc_state->wm.vlv.raw[level];

drivers/gpu/drm/i915/display/i9xx_wm.c

4037

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

4041

ret = _vlv_compute_pipe_wm(crtc_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

4044

crtc_state->wm.vlv.intermediate =

drivers/gpu/drm/i915/display/i9xx_wm.c

4045

crtc_state->wm.vlv.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

4046

crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;

drivers/gpu/drm/i915/display/i9xx_wm.c

968

static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

975

&crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/i9xx_wm.c

982

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

998

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/icl_dsi.c

1064

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1079

divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;

drivers/gpu/drm/i915/display/icl_dsi.c

1138

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1150

gen11_dsi_setup_dphy_timings(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1157

gen11_dsi_setup_timings(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1163

gen11_dsi_setup_timeouts(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1166

gen11_dsi_configure_transcoder(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1206

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/icl_dsi.c

1221

gen11_dsi_program_esc_clk_div(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1284

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/icl_dsi.c

1288

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/icl_dsi.c

1302

intel_backlight_enable(crtc_state, conn_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1305

intel_panel_prepare(crtc_state, conn_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1307

intel_crtc_vblank_on(crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1596

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1602

if (!crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1605

intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/icl_dsi.c

1618

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1621

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/icl_dsi.c

1626

use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);

drivers/gpu/drm/i915/display/icl_dsi.c

1630

if (crtc_state->pipe_bpp < 8 * 3)

drivers/gpu/drm/i915/display/icl_dsi.c

1636

vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/icl_dsi.c

1638

ret = intel_dsc_compute_params(crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1655

intel_dsc_enable_on_crtc(crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

1714

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1766

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

1768

if (crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/icl_dsi.c

1770

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/icl_dsi.c

225

void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

227

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

231

mode_flags = crtc_state->mode_flags;

drivers/gpu/drm/i915/display/icl_dsi.c

345

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

350

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/icl_dsi.c

351

bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/icl_dsi.c

359

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

368

afe_clk_khz = afe_clk(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.c

546

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

570

if (afe_clk(encoder, crtc_state) <= 800000) {

drivers/gpu/drm/i915/display/icl_dsi.c

587

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

610

if (afe_clk(encoder, crtc_state) <= 800000) {

drivers/gpu/drm/i915/display/icl_dsi.c

671

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

675

struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/icl_dsi.c

875

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

880

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/icl_dsi.c

898

if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/icl_dsi.c

899

mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/icl_dsi.c

922

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/icl_dsi.c

923

bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

drivers/gpu/drm/i915/display/icl_dsi.c

927

byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);

drivers/gpu/drm/i915/display/icl_dsi.h

15

void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

104

static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

110

int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_alpm.c

115

return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +

drivers/gpu/drm/i915/display/intel_alpm.c

121

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

128

_lnl_compute_aux_less_wake_time(crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

129

aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,

drivers/gpu/drm/i915/display/intel_alpm.c

131

silence_period = get_silence_period_symbols(crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

133

lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

143

crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;

drivers/gpu/drm/i915/display/intel_alpm.c

144

crtc_state->alpm_state.silence_period_sym_clocks = silence_period;

drivers/gpu/drm/i915/display/intel_alpm.c

145

crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;

drivers/gpu/drm/i915/display/intel_alpm.c

151

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

161

intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5);

drivers/gpu/drm/i915/display/intel_alpm.c

166

if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

172

crtc_state->alpm_state.check_entry_lines = check_entry_lines;

drivers/gpu/drm/i915/display/intel_alpm.c

192

static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

194

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

203

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

213

io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +

drivers/gpu/drm/i915/display/intel_alpm.c

226

&crtc_state->hw.adjusted_mode, io_wake_time);

drivers/gpu/drm/i915/display/intel_alpm.c

228

&crtc_state->hw.adjusted_mode, fast_wake_time);

drivers/gpu/drm/i915/display/intel_alpm.c

234

if (!_lnl_compute_alpm_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

241

crtc_state->alpm_state.io_wake_lines = max(io_wake_lines, 7);

drivers/gpu/drm/i915/display/intel_alpm.c

242

crtc_state->alpm_state.fast_wake_lines = max(fast_wake_lines, 7);

drivers/gpu/drm/i915/display/intel_alpm.c

247

int intel_alpm_lobf_min_guardband(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

249

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_alpm.c

259

waketime_in_lines = max(crtc_state->alpm_state.io_wake_lines,

drivers/gpu/drm/i915/display/intel_alpm.c

260

crtc_state->alpm_state.aux_less_wake_lines);

drivers/gpu/drm/i915/display/intel_alpm.c

262

if (!crtc_state->has_lobf)

drivers/gpu/drm/i915/display/intel_alpm.c

265

return first_sdp_position + waketime_in_lines + crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_alpm.c

268

static bool intel_alpm_lobf_is_window1_sufficient(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

270

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_alpm.c

279

crtc_state->vrr.guardband +

drivers/gpu/drm/i915/display/intel_alpm.c

280

crtc_state->set_context_latency);

drivers/gpu/drm/i915/display/intel_alpm.c

282

return window1 > crtc_state->alpm_state.check_entry_lines;

drivers/gpu/drm/i915/display/intel_alpm.c

286

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

288

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_alpm.c

291

if (!crtc_state->has_lobf)

drivers/gpu/drm/i915/display/intel_alpm.c

294

if (!intel_alpm_lobf_is_window1_sufficient(crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

295

crtc_state->has_lobf = false;

drivers/gpu/drm/i915/display/intel_alpm.c

315

waketime_in_lines = crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_alpm.c

317

waketime_in_lines = crtc_state->alpm_state.aux_less_wake_lines;

drivers/gpu/drm/i915/display/intel_alpm.c

319

crtc_state->has_lobf = (crtc_state->set_context_latency + crtc_state->vrr.guardband) >

drivers/gpu/drm/i915/display/intel_alpm.c

324

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_alpm.c

346

if (crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_alpm.c

350

!intel_vrr_is_fixed_rr(crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

357

if (!intel_alpm_compute_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

360

crtc_state->has_lobf = true;

drivers/gpu/drm/i915/display/intel_alpm.c

363

static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

381

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

384

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

387

if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_alpm.c

388

!crtc_state->has_lobf))

drivers/gpu/drm/i915/display/intel_alpm.c

396

if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

40

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

400

ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);

drivers/gpu/drm/i915/display/intel_alpm.c

403

u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

405

if (crtc_state->link_off_after_as_sdp_when_pr_active)

drivers/gpu/drm/i915/display/intel_alpm.c

407

if (crtc_state->disable_as_sdp_when_pr_active)

drivers/gpu/drm/i915/display/intel_alpm.c

416

ALPM_CTL_EXTENDED_FAST_WAKE_TIME(crtc_state->alpm_state.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_alpm.c

419

if (crtc_state->has_lobf) {

drivers/gpu/drm/i915/display/intel_alpm.c

42

return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||

drivers/gpu/drm/i915/display/intel_alpm.c

424

alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);

drivers/gpu/drm/i915/display/intel_alpm.c

43

(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));

drivers/gpu/drm/i915/display/intel_alpm.c

431

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

433

lnl_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

434

intel_dp->alpm.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

438

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

447

if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

452

crtc_state->alpm_state.silence_period_sym_clocks);

drivers/gpu/drm/i915/display/intel_alpm.c

455

crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |

drivers/gpu/drm/i915/display/intel_alpm.c

457

crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |

drivers/gpu/drm/i915/display/intel_alpm.c

459

crtc_state->alpm_state.lfps_half_cycle_num_of_syms);

drivers/gpu/drm/i915/display/intel_alpm.c

493

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

497

if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)

drivers/gpu/drm/i915/display/intel_alpm.c

502

if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&

drivers/gpu/drm/i915/display/intel_alpm.c

51

static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

53

return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /

drivers/gpu/drm/i915/display/intel_alpm.c

535

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_alpm.c

550

crtc_state = to_intel_crtc_state(crtc->state);

drivers/gpu/drm/i915/display/intel_alpm.c

551

cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

57

static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_alpm.c

60

if (crtc_state->port_clock < 540000) {

drivers/gpu/drm/i915/display/intel_alpm.c

69

static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

73

get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,

drivers/gpu/drm/i915/display/intel_alpm.c

79

static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_alpm.c

81

return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /

drivers/gpu/drm/i915/display/intel_alpm.h

20

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.h

22

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_alpm.h

25

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.h

27

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.h

30

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.h

36

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.h

40

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.h

41

int intel_alpm_lobf_min_guardband(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_atomic.c

125

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_atomic.c

132

crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);

drivers/gpu/drm/i915/display/intel_atomic.c

146

crtc_state->mode_changed = true;

drivers/gpu/drm/i915/display/intel_atomic.c

202

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_atomic.c

204

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_atomic.c

205

if (intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_atomic.c

239

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_atomic.c

241

crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);

drivers/gpu/drm/i915/display/intel_atomic.c

242

if (!crtc_state)

drivers/gpu/drm/i915/display/intel_atomic.c

245

__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_atomic.c

248

if (crtc_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_atomic.c

249

drm_property_blob_get(crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

250

if (crtc_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_atomic.c

251

drm_property_blob_get(crtc_state->hw.ctm);

drivers/gpu/drm/i915/display/intel_atomic.c

252

if (crtc_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_atomic.c

253

drm_property_blob_get(crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

255

if (crtc_state->pre_csc_lut)

drivers/gpu/drm/i915/display/intel_atomic.c

256

drm_property_blob_get(crtc_state->pre_csc_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

257

if (crtc_state->post_csc_lut)

drivers/gpu/drm/i915/display/intel_atomic.c

258

drm_property_blob_get(crtc_state->post_csc_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

260

if (crtc_state->dp_tunnel_ref.tunnel)

drivers/gpu/drm/i915/display/intel_atomic.c

261

drm_dp_tunnel_ref_get(crtc_state->dp_tunnel_ref.tunnel,

drivers/gpu/drm/i915/display/intel_atomic.c

262

&crtc_state->dp_tunnel_ref);

drivers/gpu/drm/i915/display/intel_atomic.c

264

crtc_state->update_pipe = false;

drivers/gpu/drm/i915/display/intel_atomic.c

265

crtc_state->update_m_n = false;

drivers/gpu/drm/i915/display/intel_atomic.c

266

crtc_state->update_lrr = false;

drivers/gpu/drm/i915/display/intel_atomic.c

267

crtc_state->disable_cxsr = false;

drivers/gpu/drm/i915/display/intel_atomic.c

268

crtc_state->update_wm_pre = false;

drivers/gpu/drm/i915/display/intel_atomic.c

269

crtc_state->update_wm_post = false;

drivers/gpu/drm/i915/display/intel_atomic.c

270

crtc_state->fifo_changed = false;

drivers/gpu/drm/i915/display/intel_atomic.c

271

crtc_state->preload_luts = false;

drivers/gpu/drm/i915/display/intel_atomic.c

272

crtc_state->wm.need_postvbl_update = false;

drivers/gpu/drm/i915/display/intel_atomic.c

273

crtc_state->do_async_flip = false;

drivers/gpu/drm/i915/display/intel_atomic.c

274

crtc_state->fb_bits = 0;

drivers/gpu/drm/i915/display/intel_atomic.c

275

crtc_state->update_planes = 0;

drivers/gpu/drm/i915/display/intel_atomic.c

276

crtc_state->dsb_color = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

277

crtc_state->dsb_commit = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

278

crtc_state->use_dsb = false;

drivers/gpu/drm/i915/display/intel_atomic.c

280

return &crtc_state->uapi;

drivers/gpu/drm/i915/display/intel_atomic.c

283

static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_atomic.c

285

drm_property_blob_put(crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

286

drm_property_blob_put(crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

287

drm_property_blob_put(crtc_state->hw.ctm);

drivers/gpu/drm/i915/display/intel_atomic.c

289

drm_property_blob_put(crtc_state->pre_csc_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

290

drm_property_blob_put(crtc_state->post_csc_lut);

drivers/gpu/drm/i915/display/intel_atomic.c

292

crtc_state->hw.degamma_lut = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

293

crtc_state->hw.gamma_lut = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

294

crtc_state->hw.ctm = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

295

crtc_state->pre_csc_lut = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

296

crtc_state->post_csc_lut = NULL;

drivers/gpu/drm/i915/display/intel_atomic.c

299

void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_atomic.c

301

intel_crtc_put_color_blobs(crtc_state);

drivers/gpu/drm/i915/display/intel_atomic.c

316

struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);

drivers/gpu/drm/i915/display/intel_atomic.c

318

drm_WARN_ON(crtc->dev, crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_atomic.c

319

drm_WARN_ON(crtc->dev, crtc_state->dsb_commit);

drivers/gpu/drm/i915/display/intel_atomic.c

321

__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_atomic.c

322

intel_crtc_free_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_atomic.c

323

if (crtc_state->dp_tunnel_ref.tunnel)

drivers/gpu/drm/i915/display/intel_atomic.c

324

drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref);

drivers/gpu/drm/i915/display/intel_atomic.c

325

kfree(crtc_state);

drivers/gpu/drm/i915/display/intel_atomic.c

368

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_atomic.c

369

crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);

drivers/gpu/drm/i915/display/intel_atomic.c

370

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_atomic.c

371

return ERR_CAST(crtc_state);

drivers/gpu/drm/i915/display/intel_atomic.c

373

return to_intel_crtc_state(crtc_state);

drivers/gpu/drm/i915/display/intel_atomic.h

45

void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

1003

if (intel_crtc_has_dp_encoder(crtc_state) &&

drivers/gpu/drm/i915/display/intel_audio.c

1004

crtc_state->port_clock >= 540000 &&

drivers/gpu/drm/i915/display/intel_audio.c

1005

crtc_state->lane_count == 4) {

drivers/gpu/drm/i915/display/intel_audio.c

1030

intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_audio.c

1031

min_cdclk = max(min_cdclk, crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_audio.c

189

static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

191

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

193

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_audio.c

219

static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

225

if (crtc_state->pipe_bpp == 36) {

drivers/gpu/drm/i915/display/intel_audio.c

228

} else if (crtc_state->pipe_bpp == 30) {

drivers/gpu/drm/i915/display/intel_audio.c

238

crtc_state->port_clock == hdmi_ncts_table[i].clock) {

drivers/gpu/drm/i915/display/intel_audio.c

256

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

259

u32 *eld = (u32 *)crtc_state->eld;

drivers/gpu/drm/i915/display/intel_audio.c

270

len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size);

drivers/gpu/drm/i915/display/intel_audio.c

292

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

296

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_audio.c

297

const u32 *eld = (const u32 *)crtc_state->eld;

drivers/gpu/drm/i915/display/intel_audio.c

306

len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size);

drivers/gpu/drm/i915/display/intel_audio.c

322

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

325

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

340

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

344

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

355

tmp |= audio_config_hdmi_pixel_clock(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

357

n = audio_config_hdmi_get_n(crtc_state, rate);

drivers/gpu/drm/i915/display/intel_audio.c

382

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

384

if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_audio.c

385

hsw_dp_audio_config_update(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

387

hsw_hdmi_audio_config_update(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

390

static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

393

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

394

enum transcoder trans = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

400

enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);

drivers/gpu/drm/i915/display/intel_audio.c

446

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

456

h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;

drivers/gpu/drm/i915/display/intel_audio.c

457

h_total = crtc_state->hw.adjusted_mode.crtc_htotal;

drivers/gpu/drm/i915/display/intel_audio.c

458

pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_audio.c

459

vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_audio.c

463

link_clk = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_audio.c

464

lanes = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_audio.c

493

static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

498

h_active = crtc_state->hw.adjusted_mode.hdisplay;

drivers/gpu/drm/i915/display/intel_audio.c

499

h_total = crtc_state->hw.adjusted_mode.htotal;

drivers/gpu/drm/i915/display/intel_audio.c

500

pixel_clk = crtc_state->hw.adjusted_mode.clock;

drivers/gpu/drm/i915/display/intel_audio.c

501

link_clk = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_audio.c

502

lanes = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_audio.c

509

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

512

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

526

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_audio.c

527

crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&

drivers/gpu/drm/i915/display/intel_audio.c

528

crtc_state->hw.adjusted_mode.vdisplay >= 2160) {

drivers/gpu/drm/i915/display/intel_audio.c

531

hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

543

samples_room = calc_samples_room(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

554

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

558

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_audio.c

559

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

564

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))

drivers/gpu/drm/i915/display/intel_audio.c

565

enable_audio_dsc_wa(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

567

intel_audio_sdp_split_update(crtc_state, true);

drivers/gpu/drm/i915/display/intel_audio.c

592

hsw_audio_config_update(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

660

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

664

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_audio.c

692

(intel_crtc_has_dp_encoder(crtc_state) ?

drivers/gpu/drm/i915/display/intel_audio.c

694

audio_config_hdmi_pixel_clock(crtc_state)));

drivers/gpu/drm/i915/display/intel_audio.c

700

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

706

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_audio.c

717

BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld));

drivers/gpu/drm/i915/display/intel_audio.c

718

memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));

drivers/gpu/drm/i915/display/intel_audio.c

72

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

720

crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;

drivers/gpu/drm/i915/display/intel_audio.c

736

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.c

741

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_audio.c

743

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

747

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_audio.c

755

drm_eld_size(crtc_state->eld));

drivers/gpu/drm/i915/display/intel_audio.c

758

display->audio.funcs->audio_codec_enable(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_audio.c

765

BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld));

drivers/gpu/drm/i915/display/intel_audio.c

766

memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld));

drivers/gpu/drm/i915/display/intel_audio.c

773

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))

drivers/gpu/drm/i915/display/intel_audio.c

779

intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,

drivers/gpu/drm/i915/display/intel_audio.c

78

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

780

crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_audio.c

781

intel_crtc_has_dp_encoder(crtc_state));

drivers/gpu/drm/i915/display/intel_audio.c

839

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

842

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_audio.c

850

memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld));

drivers/gpu/drm/i915/display/intel_audio.c

856

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

860

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_audio.c

864

display->audio.funcs->audio_codec_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

990

int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_audio.c

992

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_audio.c

995

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_audio.h

18

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.h

21

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_audio.h

27

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_audio.h

30

int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_backlight.c

1614

static void intel_pwm_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

1620

panel->backlight.pwm_funcs->enable(crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_backlight.c

1652

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

1664

__intel_backlight_enable(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_backlight.c

474

static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

519

static void pch_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

525

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_backlight.c

569

static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

610

static void i965_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

647

static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

653

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_backlight.c

679

static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

685

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_backlight.c

731

static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

762

static void ext_pwm_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

773

static void __intel_backlight_enable(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

790

panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level);

drivers/gpu/drm/i915/display/intel_backlight.c

796

void intel_backlight_enable(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.c

802

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_backlight.c

811

__intel_backlight_enable(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_backlight.h

23

void intel_backlight_enable(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_backlight.h

27

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_bios.c

3571

static bool fill_dsc(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_bios.c

3575

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_bios.c

3576

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_bios.c

3593

crtc_state->pipe_bpp = bpc * 3;

drivers/gpu/drm/i915/display/intel_bios.c

3595

crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,

drivers/gpu/drm/i915/display/intel_bios.c

3621

&crtc_state->dsc.slice_config)))

drivers/gpu/drm/i915/display/intel_bios.c

3624

if (crtc_state->hw.adjusted_mode.crtc_hdisplay %

drivers/gpu/drm/i915/display/intel_bios.c

3625

intel_dsc_line_slice_count(&crtc_state->dsc.slice_config) != 0)

drivers/gpu/drm/i915/display/intel_bios.c

3628

crtc_state->hw.adjusted_mode.crtc_hdisplay,

drivers/gpu/drm/i915/display/intel_bios.c

3629

intel_dsc_line_slice_count(&crtc_state->dsc.slice_config));

drivers/gpu/drm/i915/display/intel_bios.c

3650

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_bios.c

3666

return fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);

drivers/gpu/drm/i915/display/intel_bios.h

70

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_bw.c

1399

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_bw.c

1401

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_bw.c

1402

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_bw.c

1405

intel_crtc_bw_data_rate(crtc_state);

drivers/gpu/drm/i915/display/intel_bw.c

1407

intel_crtc_bw_num_active_planes(crtc_state);

drivers/gpu/drm/i915/display/intel_bw.c

1427

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_bw.c

1432

intel_bw_crtc_update(bw_state, crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

101

if (crtc_state->joiner_pipes) {

drivers/gpu/drm/i915/display/intel_casf.c

106

crtc_state->pch_pfit.casf.enable = true;

drivers/gpu/drm/i915/display/intel_casf.c

116

crtc_state->pch_pfit.casf.strength =

drivers/gpu/drm/i915/display/intel_casf.c

117

min(crtc_state->hw.sharpness_strength, 0xEF) + 0x10;

drivers/gpu/drm/i915/display/intel_casf.c

119

intel_casf_compute_win_size(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

121

intel_casf_scaler_compute_coeff(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

126

void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

128

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

129

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_casf.c

136

crtc_state->pch_pfit.casf.strength = 0;

drivers/gpu/drm/i915/display/intel_casf.c

138

crtc_state->pch_pfit.casf.strength =

drivers/gpu/drm/i915/display/intel_casf.c

140

crtc_state->pch_pfit.casf.enable = true;

drivers/gpu/drm/i915/display/intel_casf.c

141

crtc_state->pch_pfit.casf.win_size =

drivers/gpu/drm/i915/display/intel_casf.c

151

static u32 casf_coeff(const struct intel_crtc_state *crtc_state, int tap)

drivers/gpu/drm/i915/display/intel_casf.c

156

value = crtc_state->pch_pfit.casf.coeff[tap];

drivers/gpu/drm/i915/display/intel_casf.c

169

static void intel_casf_write_coeff(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

171

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

172

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_casf.c

173

int id = crtc_state->scaler_state.scaler_id;

drivers/gpu/drm/i915/display/intel_casf.c

189

tmp = casf_coeff(crtc_state, tap);

drivers/gpu/drm/i915/display/intel_casf.c

192

tmp |= casf_coeff(crtc_state, tap) << 16;

drivers/gpu/drm/i915/display/intel_casf.c

217

static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

224

if (crtc_state->pch_pfit.casf.win_size == 0)

drivers/gpu/drm/i915/display/intel_casf.c

226

else if (crtc_state->pch_pfit.casf.win_size == 1)

drivers/gpu/drm/i915/display/intel_casf.c

236

convert_sharpness_coeff_binary(&crtc_state->pch_pfit.casf.coeff[i],

drivers/gpu/drm/i915/display/intel_casf.c

241

void intel_casf_setup(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

243

intel_casf_filter_lut_load(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

244

intel_casf_write_coeff(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

64

static void intel_casf_filter_lut_load(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

66

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

67

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_casf.c

78

static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

80

const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_casf.c

84

crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_3X3;

drivers/gpu/drm/i915/display/intel_casf.c

86

crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_5X5;

drivers/gpu/drm/i915/display/intel_casf.c

88

crtc_state->pch_pfit.casf.win_size = SHARPNESS_FILTER_SIZE_7X7;

drivers/gpu/drm/i915/display/intel_casf.c

91

static void intel_casf_scaler_compute_coeff(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

93

int intel_casf_compute_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_casf.c

95

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_casf.c

97

if (crtc_state->hw.sharpness_strength == 0)

drivers/gpu/drm/i915/display/intel_casf.h

13

int intel_casf_compute_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_casf.h

14

void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_casf.h

15

void intel_casf_setup(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2912

static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate)

drivers/gpu/drm/i915/display/intel_cdclk.c

2914

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2915

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

drivers/gpu/drm/i915/display/intel_cdclk.c

2921

static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cdclk.c

2923

return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate);

drivers/gpu/drm/i915/display/intel_cdclk.c

2926

static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cdclk.c

2928

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_cdclk.c

2934

min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);

drivers/gpu/drm/i915/display/intel_cdclk.c

2939

int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cdclk.c

2943

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_cdclk.c

2946

min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

2947

min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

2948

min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

2949

min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

2950

min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

2951

min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

2952

min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

2953

min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_cdclk.c

3152

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_cdclk.c

3156

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3159

if (crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_cdclk.c

3160

min_voltage_level = crtc_state->min_voltage_level;

drivers/gpu/drm/i915/display/intel_cdclk.c

3247

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_cdclk.c

3254

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3255

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_cdclk.c

3258

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_cdclk.c

3265

switch (crtc_state->port_clock / 2) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3556

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_cdclk.c

3561

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_cdclk.c

3562

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_cdclk.c

3563

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

3565

if (intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_cdclk.c

3676

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_cdclk.c

3680

if (crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_cdclk.c

3682

if (crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_cdclk.c

3685

cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk;

drivers/gpu/drm/i915/display/intel_cdclk.c

3686

cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;

drivers/gpu/drm/i915/display/intel_cdclk.c

4218

static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk)

drivers/gpu/drm/i915/display/intel_cdclk.c

4220

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4241

static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cdclk.c

4244

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4245

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

drivers/gpu/drm/i915/display/intel_cdclk.c

4246

int cdclk = calc_cdclk(crtc_state, min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

4251

unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cdclk.c

4254

return intel_cdclk_prefill_adjustment_worst(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4257

unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cdclk.c

4259

int clock = crtc_state->hw.pipe_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_cdclk.c

4273

min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock);

drivers/gpu/drm/i915/display/intel_cdclk.c

4275

return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk);

drivers/gpu/drm/i915/display/intel_cdclk.c

4278

int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cdclk.c

4282

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.c

4283

const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_cdclk.c

4284

int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);

drivers/gpu/drm/i915/display/intel_cdclk.h

72

unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.h

73

unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cdclk.h

74

int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cdclk.h

78

int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1001

icl_load_csc_matrix(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1005

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1017

if (!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_color.c

1018

ilk_load_csc_matrix(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1022

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1024

ilk_load_csc_matrix(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1028

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1031

i9xx_set_pipeconf(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1035

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1037

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1041

ilk_set_pipeconf(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1044

crtc_state->csc_mode);

drivers/gpu/drm/i915/display/intel_color.c

1048

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1050

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1054

crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1057

crtc_state->csc_mode);

drivers/gpu/drm/i915/display/intel_color.c

1074

static void i9xx_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1076

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1077

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1085

crtc_state->gamma_enable = true;

drivers/gpu/drm/i915/display/intel_color.c

1088

crtc_state->csc_enable = true;

drivers/gpu/drm/i915/display/intel_color.c

1091

static void hsw_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1093

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1095

crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1096

crtc_state->csc_mode = ilk_read_csc_mode(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1098

i9xx_get_config(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1101

static void skl_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1103

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1104

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1107

crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1108

crtc_state->csc_mode = ilk_read_csc_mode(crtc);

drivers/gpu/drm/i915/display/intel_color.c

1113

crtc_state->gamma_enable = true;

drivers/gpu/drm/i915/display/intel_color.c

1116

crtc_state->csc_enable = true;

drivers/gpu/drm/i915/display/intel_color.c

1119

crtc_state->hw.background_color = color & GENMASK(29, 0);

drivers/gpu/drm/i915/display/intel_color.c

1139

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1141

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1142

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1144

u32 val = crtc_state->hw.background_color;

drivers/gpu/drm/i915/display/intel_color.c

1146

if (crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_color.c

1147

ilk_load_csc_matrix(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1149

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_color.c

1151

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_color.c

1155

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1157

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

drivers/gpu/drm/i915/display/intel_color.c

1161

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1163

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1164

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1167

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), crtc_state->hw.background_color);

drivers/gpu/drm/i915/display/intel_color.c

1169

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1171

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

drivers/gpu/drm/i915/display/intel_color.c

1174

static void icl_color_post_update(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1176

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1177

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1301

static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1303

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1304

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1306

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

1314

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1341

static void i965_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1343

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1344

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1346

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

1354

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1359

static void ilk_lut_write(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1362

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1364

if (crtc_state->dsb_color)

drivers/gpu/drm/i915/display/intel_color.c

1365

intel_dsb_reg_write(crtc_state->dsb_color, reg, val);

drivers/gpu/drm/i915/display/intel_color.c

1370

static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1373

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1375

if (crtc_state->dsb_color)

drivers/gpu/drm/i915/display/intel_color.c

1376

intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val);

drivers/gpu/drm/i915/display/intel_color.c

1381

static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1384

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1412

ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),

drivers/gpu/drm/i915/display/intel_color.c

1414

if (crtc_state->dsb_color)

drivers/gpu/drm/i915/display/intel_color.c

1415

ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),

drivers/gpu/drm/i915/display/intel_color.c

1420

static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1423

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1429

ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i),

drivers/gpu/drm/i915/display/intel_color.c

1433

static void ilk_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1435

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1436

const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1439

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

1441

ilk_load_lut_8(crtc_state, blob);

drivers/gpu/drm/i915/display/intel_color.c

1444

ilk_load_lut_10(crtc_state, blob);

drivers/gpu/drm/i915/display/intel_color.c

1447

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1465

static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1469

const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1475

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1477

ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1485

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1490

static void bdw_load_lut_10(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1494

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1499

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1501

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1506

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1513

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1517

static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1519

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1523

ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);

drivers/gpu/drm/i915/display/intel_color.c

1524

ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);

drivers/gpu/drm/i915/display/intel_color.c

1525

ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);

drivers/gpu/drm/i915/display/intel_color.c

1528

static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1530

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1534

ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);

drivers/gpu/drm/i915/display/intel_color.c

1535

ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);

drivers/gpu/drm/i915/display/intel_color.c

1536

ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);

drivers/gpu/drm/i915/display/intel_color.c

1539

static void ivb_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1541

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1542

const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1545

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

1547

ilk_load_lut_8(crtc_state, blob);

drivers/gpu/drm/i915/display/intel_color.c

1550

ivb_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE |

drivers/gpu/drm/i915/display/intel_color.c

1552

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1553

ivb_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE |

drivers/gpu/drm/i915/display/intel_color.c

1557

ivb_load_lut_10(crtc_state, blob,

drivers/gpu/drm/i915/display/intel_color.c

1559

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1562

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1567

static void bdw_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1569

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1570

const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1573

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

1575

ilk_load_lut_8(crtc_state, blob);

drivers/gpu/drm/i915/display/intel_color.c

1578

bdw_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE |

drivers/gpu/drm/i915/display/intel_color.c

1580

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1581

bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE |

drivers/gpu/drm/i915/display/intel_color.c

1585

bdw_load_lut_10(crtc_state, blob,

drivers/gpu/drm/i915/display/intel_color.c

1587

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1590

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1626

static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1629

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1630

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1640

ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1642

ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1660

ilk_lut_write_indexed(crtc_state, PRE_CSC_GAMC_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1667

ilk_lut_write_indexed(crtc_state, PRE_CSC_GAMC_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1671

ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0);

drivers/gpu/drm/i915/display/intel_color.c

1674

static void glk_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1676

const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1677

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1680

glk_load_degamma_lut(crtc_state, pre_csc_lut);

drivers/gpu/drm/i915/display/intel_color.c

1682

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

1684

ilk_load_lut_8(crtc_state, post_csc_lut);

drivers/gpu/drm/i915/display/intel_color.c

1687

bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0));

drivers/gpu/drm/i915/display/intel_color.c

1688

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1689

glk_load_lut_ext2_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1692

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1698

ivb_load_lut_max(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

1701

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1705

ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);

drivers/gpu/drm/i915/display/intel_color.c

1706

ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);

drivers/gpu/drm/i915/display/intel_color.c

1707

ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);

drivers/gpu/drm/i915/display/intel_color.c

1711

icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1713

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1714

const struct drm_property_blob *blob = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1726

ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1728

ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1735

ilk_lut_write_indexed(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1737

ilk_lut_write_indexed(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1741

ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1746

icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1748

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1749

const struct drm_property_blob *blob = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1765

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1767

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1774

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1776

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1795

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1797

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1801

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

drivers/gpu/drm/i915/display/intel_color.c

1806

ivb_load_lut_max(crtc_state, entry);

drivers/gpu/drm/i915/display/intel_color.c

1809

static void icl_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1811

const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1812

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1815

glk_load_degamma_lut(crtc_state, pre_csc_lut);

drivers/gpu/drm/i915/display/intel_color.c

1817

switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_color.c

1819

ilk_load_lut_8(crtc_state, post_csc_lut);

drivers/gpu/drm/i915/display/intel_color.c

1822

icl_program_gamma_superfine_segment(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1823

icl_program_gamma_multi_segment(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1824

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1825

glk_load_lut_ext2_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1828

bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0));

drivers/gpu/drm/i915/display/intel_color.c

1829

ivb_load_lut_ext_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1830

glk_load_lut_ext2_max(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1833

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

1838

static void vlv_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1840

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1842

if (crtc_state->wgc_enable)

drivers/gpu/drm/i915/display/intel_color.c

1843

vlv_load_wgc_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

1845

i965_load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1916

static void chv_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1918

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1919

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1920

const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1921

const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

1923

if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)

drivers/gpu/drm/i915/display/intel_color.c

1924

chv_load_cgm_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

1926

if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)

drivers/gpu/drm/i915/display/intel_color.c

1929

if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)

drivers/gpu/drm/i915/display/intel_color.c

1932

i965_load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1935

crtc_state->cgm_mode);

drivers/gpu/drm/i915/display/intel_color.c

1938

void intel_color_load_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1940

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1942

if (crtc_state->dsb_color)

drivers/gpu/drm/i915/display/intel_color.c

1945

display->color.funcs->load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1949

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1951

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1954

display->color.funcs->color_commit_noarm(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1958

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1960

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1962

display->color.funcs->color_commit_arm(dsb, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1965

void intel_color_post_update(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1967

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1970

display->color.funcs->color_post_update(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1973

void intel_color_modeset(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1975

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1977

intel_color_load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1978

intel_color_commit_noarm(NULL, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1979

intel_color_commit_arm(NULL, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1982

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

1986

plane->disable_arm(NULL, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1990

bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1992

return crtc_state->dsb_color;

drivers/gpu/drm/i915/display/intel_color.c

1995

bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

1997

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

1999

return crtc_state->dsb_color && !HAS_DOUBLE_BUFFERED_LUT(display);

drivers/gpu/drm/i915/display/intel_color.c

2002

bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2004

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2006

return crtc_state->dsb_color && HAS_DOUBLE_BUFFERED_LUT(display);

drivers/gpu/drm/i915/display/intel_color.c

2013

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2016

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_color.c

2017

intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

2020

if (!intel_crtc_needs_color_update(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

2023

if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)

drivers/gpu/drm/i915/display/intel_color.c

2027

crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);

drivers/gpu/drm/i915/display/intel_color.c

2029

crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);

drivers/gpu/drm/i915/display/intel_color.c

2031

if (!intel_color_uses_dsb(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

2034

display->color.funcs->load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2036

if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {

drivers/gpu/drm/i915/display/intel_color.c

2037

intel_vrr_send_push(crtc_state->dsb_color, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2038

intel_dsb_wait_for_delayed_vblank(state, crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_color.c

2039

intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2040

intel_dsb_interrupt(crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_color.c

2043

if (intel_color_uses_gosub_dsb(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

2044

intel_dsb_gosub_finish(crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_color.c

2046

intel_dsb_finish(crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_color.c

2049

void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2051

if (crtc_state->dsb_color) {

drivers/gpu/drm/i915/display/intel_color.c

2052

intel_dsb_cleanup(crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_color.c

2053

crtc_state->dsb_color = NULL;

drivers/gpu/drm/i915/display/intel_color.c

2057

void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2059

if (crtc_state->dsb_color)

drivers/gpu/drm/i915/display/intel_color.c

2060

intel_dsb_wait(crtc_state->dsb_color);

drivers/gpu/drm/i915/display/intel_color.c

2134

void intel_color_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2136

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2138

display->color.funcs->get_config(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2140

display->color.funcs->read_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2143

display->color.funcs->read_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2146

bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

2151

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2157

if (!is_pre_csc_lut && crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

2160

return display->color.funcs->lut_equal(crtc_state, blob1, blob2,

drivers/gpu/drm/i915/display/intel_color.c

2165

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2174

return crtc_state->active_planes & BIT(plane->id) ||

drivers/gpu/drm/i915/display/intel_color.c

2219

static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2221

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2222

const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

drivers/gpu/drm/i915/display/intel_color.c

2230

static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2232

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2237

static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2239

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2240

const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

drivers/gpu/drm/i915/display/intel_color.c

2248

static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2250

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2275

static int _check_luts(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

2278

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2279

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

2280

const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

drivers/gpu/drm/i915/display/intel_color.c

2281

const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;

drivers/gpu/drm/i915/display/intel_color.c

2285

if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) {

drivers/gpu/drm/i915/display/intel_color.c

2292

degamma_length = intel_degamma_lut_size(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2293

gamma_length = intel_gamma_lut_size(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2306

static int check_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2308

return _check_luts(crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

2309

intel_degamma_lut_tests(crtc_state),

drivers/gpu/drm/i915/display/intel_color.c

2310

intel_gamma_lut_tests(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

2313

static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2315

if (!crtc_state->gamma_enable ||

drivers/gpu/drm/i915/display/intel_color.c

2316

lut_is_legacy(crtc_state->hw.gamma_lut))

drivers/gpu/drm/i915/display/intel_color.c

2349

void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2351

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2356

crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2358

crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2361

crtc_state->post_csc_lut == crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2362

crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2363

crtc_state->pre_csc_lut != display->color.glk_linear_degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2365

!ilk_lut_limited_range(crtc_state) &&

drivers/gpu/drm/i915/display/intel_color.c

2366

crtc_state->post_csc_lut != NULL &&

drivers/gpu/drm/i915/display/intel_color.c

2367

crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2368

} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {

drivers/gpu/drm/i915/display/intel_color.c

2370

crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2371

crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2373

!ilk_lut_limited_range(crtc_state) &&

drivers/gpu/drm/i915/display/intel_color.c

2374

crtc_state->post_csc_lut != crtc_state->hw.degamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2375

crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2379

static void intel_assign_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2381

drm_property_replace_blob(&crtc_state->pre_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2382

crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2383

drm_property_replace_blob(&crtc_state->post_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2384

crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2391

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2395

ret = check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2399

crtc_state->gamma_enable =

drivers/gpu/drm/i915/display/intel_color.c

2400

crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2401

!crtc_state->c8_planes;

drivers/gpu/drm/i915/display/intel_color.c

2403

crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2406

crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) {

drivers/gpu/drm/i915/display/intel_color.c

2407

ret = i9xx_check_lut_10(crtc, crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2416

intel_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2418

crtc_state->preload_luts = intel_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2430

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2434

ret = check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2438

crtc_state->gamma_enable =

drivers/gpu/drm/i915/display/intel_color.c

2439

crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2440

!crtc_state->c8_planes;

drivers/gpu/drm/i915/display/intel_color.c

2442

crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2444

crtc_state->wgc_enable = crtc_state->hw.ctm;

drivers/gpu/drm/i915/display/intel_color.c

2450

intel_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2452

vlv_assign_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2454

crtc_state->preload_luts = vlv_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2459

static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2463

if (crtc_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

2465

if (crtc_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_color.c

2467

if (crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2468

!lut_is_legacy(crtc_state->hw.gamma_lut))

drivers/gpu/drm/i915/display/intel_color.c

2492

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2496

ret = check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2504

crtc_state->gamma_enable =

drivers/gpu/drm/i915/display/intel_color.c

2505

lut_is_legacy(crtc_state->hw.gamma_lut) &&

drivers/gpu/drm/i915/display/intel_color.c

2506

!crtc_state->c8_planes;

drivers/gpu/drm/i915/display/intel_color.c

2508

crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;

drivers/gpu/drm/i915/display/intel_color.c

2510

crtc_state->cgm_mode = chv_cgm_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2516

crtc_state->wgc_enable = false;

drivers/gpu/drm/i915/display/intel_color.c

2522

intel_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2524

chv_assign_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2526

crtc_state->preload_luts = chv_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2531

static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2533

return (crtc_state->hw.gamma_lut ||

drivers/gpu/drm/i915/display/intel_color.c

2534

crtc_state->hw.degamma_lut) &&

drivers/gpu/drm/i915/display/intel_color.c

2535

!crtc_state->c8_planes;

drivers/gpu/drm/i915/display/intel_color.c

2538

static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2540

return crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

drivers/gpu/drm/i915/display/intel_color.c

2541

ilk_csc_limited_range(crtc_state) ||

drivers/gpu/drm/i915/display/intel_color.c

2542

crtc_state->hw.ctm;

drivers/gpu/drm/i915/display/intel_color.c

2545

static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2547

if (!crtc_state->gamma_enable ||

drivers/gpu/drm/i915/display/intel_color.c

2548

lut_is_legacy(crtc_state->hw.gamma_lut))

drivers/gpu/drm/i915/display/intel_color.c

2554

static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2562

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

drivers/gpu/drm/i915/display/intel_color.c

2565

if (crtc_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

2572

static int ilk_assign_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2574

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2576

if (ilk_lut_limited_range(crtc_state)) {

drivers/gpu/drm/i915/display/intel_color.c

2579

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_color.c

2580

drm_color_lut_size(crtc_state->hw.gamma_lut),

drivers/gpu/drm/i915/display/intel_color.c

2585

drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2589

drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2594

if (crtc_state->hw.degamma_lut ||

drivers/gpu/drm/i915/display/intel_color.c

2595

crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) {

drivers/gpu/drm/i915/display/intel_color.c

2596

drm_property_replace_blob(&crtc_state->pre_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2597

crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2598

drm_property_replace_blob(&crtc_state->post_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2599

crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2601

drm_property_replace_blob(&crtc_state->pre_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2602

crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2603

drm_property_replace_blob(&crtc_state->post_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2614

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2618

ret = check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2622

if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {

drivers/gpu/drm/i915/display/intel_color.c

2629

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

drivers/gpu/drm/i915/display/intel_color.c

2630

crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

2637

crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2639

crtc_state->csc_enable = ilk_csc_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2641

crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2643

crtc_state->csc_mode = ilk_csc_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2649

ret = ilk_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2653

ilk_assign_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2655

crtc_state->preload_luts = intel_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2660

static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2662

if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

2665

return ilk_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2668

static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2670

bool limited_color_range = ilk_csc_limited_range(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2676

if (crtc_state->hw.degamma_lut ||

drivers/gpu/drm/i915/display/intel_color.c

2677

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

drivers/gpu/drm/i915/display/intel_color.c

2684

static int ivb_assign_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2686

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2689

if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT)

drivers/gpu/drm/i915/display/intel_color.c

2690

return ilk_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2692

drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);

drivers/gpu/drm/i915/display/intel_color.c

2693

drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);

drivers/gpu/drm/i915/display/intel_color.c

2695

degamma_lut = create_resized_lut(display, crtc_state->hw.degamma_lut, 512,

drivers/gpu/drm/i915/display/intel_color.c

2700

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut, 512,

drivers/gpu/drm/i915/display/intel_color.c

2701

ilk_lut_limited_range(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

2707

drm_property_replace_blob(&crtc_state->pre_csc_lut, degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2708

drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2720

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2724

ret = check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2728

if (crtc_state->c8_planes && crtc_state->hw.degamma_lut) {

drivers/gpu/drm/i915/display/intel_color.c

2735

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

drivers/gpu/drm/i915/display/intel_color.c

2736

crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

2743

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

drivers/gpu/drm/i915/display/intel_color.c

2744

crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {

drivers/gpu/drm/i915/display/intel_color.c

2751

crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2753

crtc_state->csc_enable = ilk_csc_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2755

crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2757

crtc_state->csc_mode = ivb_csc_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2763

ret = ivb_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2767

ilk_assign_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2769

crtc_state->preload_luts = intel_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2774

static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2776

if (!crtc_state->gamma_enable ||

drivers/gpu/drm/i915/display/intel_color.c

2777

lut_is_legacy(crtc_state->hw.gamma_lut))

drivers/gpu/drm/i915/display/intel_color.c

2783

static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2785

return crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2786

!crtc_state->c8_planes &&

drivers/gpu/drm/i915/display/intel_color.c

2787

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_color.c

2790

static int glk_assign_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2792

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2794

if (glk_use_pre_csc_lut_for_gamma(crtc_state)) {

drivers/gpu/drm/i915/display/intel_color.c

2797

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_color.c

2803

drm_property_replace_blob(&crtc_state->pre_csc_lut, gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2804

drm_property_replace_blob(&crtc_state->post_csc_lut, NULL);

drivers/gpu/drm/i915/display/intel_color.c

2811

if (ilk_lut_limited_range(crtc_state)) {

drivers/gpu/drm/i915/display/intel_color.c

2814

gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_color.c

2815

drm_color_lut_size(crtc_state->hw.gamma_lut),

drivers/gpu/drm/i915/display/intel_color.c

2820

drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2824

drm_property_replace_blob(&crtc_state->post_csc_lut, crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2827

drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_color.c

2835

if (crtc_state->csc_enable && !crtc_state->pre_csc_lut)

drivers/gpu/drm/i915/display/intel_color.c

2836

drm_property_replace_blob(&crtc_state->pre_csc_lut,

drivers/gpu/drm/i915/display/intel_color.c

2842

static int glk_check_luts(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2844

u32 degamma_tests = intel_degamma_lut_tests(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2845

u32 gamma_tests = intel_gamma_lut_tests(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2847

if (glk_use_pre_csc_lut_for_gamma(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

2850

return _check_luts(crtc_state, degamma_tests, gamma_tests);

drivers/gpu/drm/i915/display/intel_color.c

2857

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2861

ret = glk_check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2865

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

drivers/gpu/drm/i915/display/intel_color.c

2866

crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

2873

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

drivers/gpu/drm/i915/display/intel_color.c

2874

crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {

drivers/gpu/drm/i915/display/intel_color.c

2881

crtc_state->gamma_enable =

drivers/gpu/drm/i915/display/intel_color.c

2882

!glk_use_pre_csc_lut_for_gamma(crtc_state) &&

drivers/gpu/drm/i915/display/intel_color.c

2883

crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2884

!crtc_state->c8_planes;

drivers/gpu/drm/i915/display/intel_color.c

2887

crtc_state->csc_enable =

drivers/gpu/drm/i915/display/intel_color.c

2888

glk_use_pre_csc_lut_for_gamma(crtc_state) ||

drivers/gpu/drm/i915/display/intel_color.c

2889

crtc_state->hw.degamma_lut ||

drivers/gpu/drm/i915/display/intel_color.c

2890

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

drivers/gpu/drm/i915/display/intel_color.c

2891

crtc_state->hw.ctm || ilk_csc_limited_range(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2893

crtc_state->gamma_mode = glk_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2895

crtc_state->csc_mode = 0;

drivers/gpu/drm/i915/display/intel_color.c

2901

ret = glk_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2905

ilk_assign_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2907

crtc_state->preload_luts = intel_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2912

static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2914

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2917

if (crtc_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

2920

if (crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

2921

!crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

2924

if (!crtc_state->hw.gamma_lut ||

drivers/gpu/drm/i915/display/intel_color.c

2925

lut_is_legacy(crtc_state->hw.gamma_lut))

drivers/gpu/drm/i915/display/intel_color.c

2940

static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2944

if (crtc_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_color.c

2947

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

drivers/gpu/drm/i915/display/intel_color.c

2948

crtc_state->limited_color_range)

drivers/gpu/drm/i915/display/intel_color.c

2957

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_color.c

2961

ret = check_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2965

crtc_state->gamma_mode = icl_gamma_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2967

crtc_state->csc_mode = icl_csc_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2969

intel_assign_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2971

icl_assign_csc(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

2973

crtc_state->preload_luts = intel_can_preload_luts(state, crtc);

drivers/gpu/drm/i915/display/intel_color.c

2978

static int i9xx_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2980

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

2983

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

2989

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

2994

static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

2999

static int i965_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3001

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3004

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

301

static void ilk_read_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3010

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3028

static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

303

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3030

if (crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3033

return crtc_state->gamma_enable &&

drivers/gpu/drm/i915/display/intel_color.c

3034

(crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0;

drivers/gpu/drm/i915/display/intel_color.c

3037

static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3039

return crtc_state->gamma_enable &&

drivers/gpu/drm/i915/display/intel_color.c

3040

(crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0;

drivers/gpu/drm/i915/display/intel_color.c

3043

static int ilk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3045

if (!ilk_has_post_csc_lut(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

3048

return ilk_gamma_mode_precision(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

305

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_color.c

3051

static int ilk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3053

if (!ilk_has_pre_csc_lut(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

3056

return ilk_gamma_mode_precision(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3059

static int ivb_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

306

ilk_read_pipe_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

3061

if (crtc_state->gamma_enable &&

drivers/gpu/drm/i915/display/intel_color.c

3062

crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)

drivers/gpu/drm/i915/display/intel_color.c

3065

return ilk_post_csc_lut_precision(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3068

static int ivb_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3070

if (crtc_state->gamma_enable &&

drivers/gpu/drm/i915/display/intel_color.c

3071

crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)

drivers/gpu/drm/i915/display/intel_color.c

3074

return ilk_pre_csc_lut_precision(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3077

static int chv_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3079

if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)

drivers/gpu/drm/i915/display/intel_color.c

3082

return i965_post_csc_lut_precision(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3085

static int chv_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3087

if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)

drivers/gpu/drm/i915/display/intel_color.c

309

static void skl_read_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3093

static int glk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3095

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3098

return ilk_gamma_mode_precision(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3101

static int glk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3103

if (!crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_color.c

3109

static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

311

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3111

if (crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3114

return crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE;

drivers/gpu/drm/i915/display/intel_color.c

3117

static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3119

return crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE;

drivers/gpu/drm/i915/display/intel_color.c

3122

static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3124

if (!icl_has_post_csc_lut(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

3127

switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_color.c

3135

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3140

static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3142

if (!icl_has_pre_csc_lut(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

3207

static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

3216

i9xx_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3219

if (crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT)

drivers/gpu/drm/i915/display/intel_color.c

3223

i9xx_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3226

static bool i965_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

3233

i9xx_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3236

i965_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3239

static bool chv_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

3246

chv_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3249

chv_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3252

static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

3259

ilk_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

326

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_color.c

3262

ilk_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3265

static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

327

ilk_read_pipe_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

3272

ivb_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3275

ivb_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3278

static bool glk_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

3285

glk_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3288

glk_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3291

static bool icl_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

3300

icl_pre_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3303

if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==

drivers/gpu/drm/i915/display/intel_color.c

3308

icl_post_csc_lut_precision(crtc_state));

drivers/gpu/drm/i915/display/intel_color.c

3368

static void i9xx_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3370

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3372

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3375

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

3377

crtc_state->post_csc_lut = i9xx_read_lut_8(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3380

crtc_state->post_csc_lut = i9xx_read_lut_10(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3383

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3420

static void i965_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3422

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3424

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3427

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

3429

crtc_state->post_csc_lut = i9xx_read_lut_8(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3432

crtc_state->post_csc_lut = i965_read_lut_10p6(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3435

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3492

static void chv_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3494

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3495

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3497

crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

3499

i9xx_get_config(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3502

static void chv_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3504

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3506

if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)

drivers/gpu/drm/i915/display/intel_color.c

3507

crtc_state->pre_csc_lut = chv_read_cgm_degamma(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3509

if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)

drivers/gpu/drm/i915/display/intel_color.c

3510

crtc_state->post_csc_lut = chv_read_cgm_gamma(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3512

i965_read_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3565

static void ilk_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3567

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3569

crtc_state->csc_mode = ilk_read_csc_mode(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3571

i9xx_get_config(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

3574

static void ilk_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3576

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3578

ilk_has_post_csc_lut(crtc_state) ?

drivers/gpu/drm/i915/display/intel_color.c

3579

&crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

3581

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3584

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

3592

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3635

static void ivb_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3637

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3639

ilk_has_post_csc_lut(crtc_state) ?

drivers/gpu/drm/i915/display/intel_color.c

3640

&crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

3642

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3645

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

3650

crtc_state->pre_csc_lut =

drivers/gpu/drm/i915/display/intel_color.c

3653

crtc_state->post_csc_lut =

drivers/gpu/drm/i915/display/intel_color.c

3661

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3702

static void bdw_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3704

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3706

ilk_has_post_csc_lut(crtc_state) ?

drivers/gpu/drm/i915/display/intel_color.c

3707

&crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;

drivers/gpu/drm/i915/display/intel_color.c

3709

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3712

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

3717

crtc_state->pre_csc_lut =

drivers/gpu/drm/i915/display/intel_color.c

3720

crtc_state->post_csc_lut =

drivers/gpu/drm/i915/display/intel_color.c

3728

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3775

static void glk_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3777

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3779

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_color.c

3780

crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3782

if (!crtc_state->gamma_enable && !crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

3785

switch (crtc_state->gamma_mode) {

drivers/gpu/drm/i915/display/intel_color.c

3787

crtc_state->post_csc_lut = ilk_read_lut_8(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3790

crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));

drivers/gpu/drm/i915/display/intel_color.c

3793

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

3840

static void icl_read_luts(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

3842

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

3844

if (icl_has_pre_csc_lut(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

3845

crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3847

if (!icl_has_post_csc_lut(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

3850

switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_color.c

3852

crtc_state->post_csc_lut = ilk_read_lut_8(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3855

crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));

drivers/gpu/drm/i915/display/intel_color.c

3858

crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc);

drivers/gpu/drm/i915/display/intel_color.c

3861

MISSING_CASE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_color.c

401

static void icl_read_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

403

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

410

if (crtc_state->csc_mode & ICL_CSC_ENABLE)

drivers/gpu/drm/i915/display/intel_color.c

411

ilk_read_pipe_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

413

if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)

drivers/gpu/drm/i915/display/intel_color.c

414

icl_read_output_csc(crtc, &crtc_state->output_csc);

drivers/gpu/drm/i915/display/intel_color.c

417

static bool ilk_limited_range(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

419

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

429

return crtc_state->limited_color_range;

drivers/gpu/drm/i915/display/intel_color.c

432

static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

434

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

436

if (!ilk_limited_range(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

439

if (crtc_state->c8_planes)

drivers/gpu/drm/i915/display/intel_color.c

443

return crtc_state->hw.gamma_lut;

drivers/gpu/drm/i915/display/intel_color.c

445

return crtc_state->hw.gamma_lut &&

drivers/gpu/drm/i915/display/intel_color.c

446

(crtc_state->hw.degamma_lut || crtc_state->hw.ctm);

drivers/gpu/drm/i915/display/intel_color.c

449

static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

451

if (!ilk_limited_range(crtc_state))

drivers/gpu/drm/i915/display/intel_color.c

454

return !ilk_lut_limited_range(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

467

static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

471

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

472

const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;

drivers/gpu/drm/i915/display/intel_color.c

49

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

527

static void ilk_assign_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

529

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

530

bool limited_color_range = ilk_csc_limited_range(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

532

if (crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

533

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

drivers/gpu/drm/i915/display/intel_color.c

535

ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, limited_color_range);

drivers/gpu/drm/i915/display/intel_color.c

536

} else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {

drivers/gpu/drm/i915/display/intel_color.c

537

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

drivers/gpu/drm/i915/display/intel_color.c

539

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);

drivers/gpu/drm/i915/display/intel_color.c

541

drm_WARN_ON(display->drm, !crtc_state->csc_enable);

drivers/gpu/drm/i915/display/intel_color.c

543

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_limited_range);

drivers/gpu/drm/i915/display/intel_color.c

544

} else if (crtc_state->csc_enable) {

drivers/gpu/drm/i915/display/intel_color.c

553

ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);

drivers/gpu/drm/i915/display/intel_color.c

555

intel_csc_clear(&crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

560

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

562

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

564

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_color.c

565

ilk_update_pipe_csc(dsb, crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

568

static void icl_assign_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

570

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

572

if (crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

573

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);

drivers/gpu/drm/i915/display/intel_color.c

575

ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, false);

drivers/gpu/drm/i915/display/intel_color.c

577

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);

drivers/gpu/drm/i915/display/intel_color.c

579

intel_csc_clear(&crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

58

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

582

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {

drivers/gpu/drm/i915/display/intel_color.c

583

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);

drivers/gpu/drm/i915/display/intel_color.c

585

ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);

drivers/gpu/drm/i915/display/intel_color.c

586

} else if (crtc_state->limited_color_range) {

drivers/gpu/drm/i915/display/intel_color.c

587

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);

drivers/gpu/drm/i915/display/intel_color.c

589

ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);

drivers/gpu/drm/i915/display/intel_color.c

591

drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);

drivers/gpu/drm/i915/display/intel_color.c

593

intel_csc_clear(&crtc_state->output_csc);

drivers/gpu/drm/i915/display/intel_color.c

598

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

600

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

602

if (crtc_state->csc_mode & ICL_CSC_ENABLE)

drivers/gpu/drm/i915/display/intel_color.c

603

ilk_update_pipe_csc(dsb, crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

605

if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)

drivers/gpu/drm/i915/display/intel_color.c

606

icl_update_output_csc(dsb, crtc, &crtc_state->output_csc);

drivers/gpu/drm/i915/display/intel_color.c

63

void (*color_post_update)(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

638

static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

641

const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;

drivers/gpu/drm/i915/display/intel_color.c

699

static void vlv_read_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

70

void (*load_luts)(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

701

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

703

if (crtc_state->wgc_enable)

drivers/gpu/drm/i915/display/intel_color.c

704

vlv_read_wgc_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

707

static void vlv_assign_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

709

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

711

if (crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

712

drm_WARN_ON(display->drm, !crtc_state->wgc_enable);

drivers/gpu/drm/i915/display/intel_color.c

714

vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

716

drm_WARN_ON(display->drm, crtc_state->wgc_enable);

drivers/gpu/drm/i915/display/intel_color.c

718

intel_csc_clear(&crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

730

static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

733

const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;

drivers/gpu/drm/i915/display/intel_color.c

75

void (*read_luts)(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

79

bool (*lut_equal)(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.c

795

static void chv_read_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

797

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

799

if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)

drivers/gpu/drm/i915/display/intel_color.c

800

chv_read_cgm_csc(crtc, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

803

static void chv_assign_csc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.c

805

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

807

drm_WARN_ON(display->drm, crtc_state->wgc_enable);

drivers/gpu/drm/i915/display/intel_color.c

809

if (crtc_state->hw.ctm) {

drivers/gpu/drm/i915/display/intel_color.c

810

drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);

drivers/gpu/drm/i915/display/intel_color.c

812

chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);

drivers/gpu/drm/i915/display/intel_color.c

814

drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);

drivers/gpu/drm/i915/display/intel_color.c

816

crtc_state->csc = chv_cgm_csc_matrix_identity;

drivers/gpu/drm/i915/display/intel_color.c

87

void (*read_csc)(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

91

void (*get_config)(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.c

991

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_color.h

27

void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

28

bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

29

bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

30

bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

31

void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

33

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

35

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

36

void intel_color_post_update(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

37

void intel_color_load_luts(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

38

void intel_color_modeset(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

39

void intel_color_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_color.h

40

bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_color.h

44

void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

151

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crt.c

153

crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);

drivers/gpu/drm/i915/display/intel_crt.c

155

crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

157

crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_crt.c

161

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crt.c

163

lpt_pch_get_config(crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

165

hsw_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

167

crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

drivers/gpu/drm/i915/display/intel_crt.c

171

crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);

drivers/gpu/drm/i915/display/intel_crt.c

177

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

182

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crt.c

183

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_crt.c

291

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

296

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

303

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

307

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crt.c

310

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

314

hsw_fdi_link_train(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

316

intel_ddi_enable_transcoder_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

321

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

325

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crt.c

328

drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_crt.c

330

intel_ddi_enable_transcoder_func(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

332

intel_enable_transcoder(crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

336

intel_crtc_vblank_on(crtc_state);

drivers/gpu/drm/i915/display/intel_crt.c

338

intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);

drivers/gpu/drm/i915/display/intel_crt.c

348

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

351

intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);

drivers/gpu/drm/i915/display/intel_crt.c

401

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

405

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_crt.c

410

crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_crt.c

411

crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_crt.c

417

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

421

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_crt.c

426

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/intel_crt.c

427

if (!intel_link_bw_compute_pipe_bpp(crtc_state))

drivers/gpu/drm/i915/display/intel_crt.c

430

crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_crt.c

436

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crt.c

441

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_crt.c

451

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/intel_crt.c

452

if (!intel_link_bw_compute_pipe_bpp(crtc_state))

drivers/gpu/drm/i915/display/intel_crt.c

455

crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_crt.c

460

if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) {

drivers/gpu/drm/i915/display/intel_crt.c

466

crtc_state->pipe_bpp = 24;

drivers/gpu/drm/i915/display/intel_crt.c

470

crtc_state->port_clock = 135000 * 2;

drivers/gpu/drm/i915/display/intel_crt.c

472

crtc_state->enhanced_framing = true;

drivers/gpu/drm/i915/display/intel_crt.c

474

adjusted_mode->crtc_clock = lpt_iclkip(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

101

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

109

if (crtc_state->mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 |

drivers/gpu/drm/i915/display/intel_crtc.c

118

(crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))

drivers/gpu/drm/i915/display/intel_crtc.c

129

void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

131

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

133

crtc->vblank_psr_notify = intel_psr_needs_vblank_notification(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

137

intel_crtc_max_vblank_count(crtc_state));

drivers/gpu/drm/i915/display/intel_crtc.c

148

void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

150

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

151

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

170

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_crtc.c

172

crtc_state = kmalloc_obj(*crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

174

if (crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

175

intel_crtc_state_reset(crtc_state, crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

177

return crtc_state;

drivers/gpu/drm/i915/display/intel_crtc.c

180

void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crtc.c

183

memset(crtc_state, 0, sizeof(*crtc_state));

drivers/gpu/drm/i915/display/intel_crtc.c

185

__drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);

drivers/gpu/drm/i915/display/intel_crtc.c

187

crtc_state->cpu_transcoder = INVALID_TRANSCODER;

drivers/gpu/drm/i915/display/intel_crtc.c

188

crtc_state->master_transcoder = INVALID_TRANSCODER;

drivers/gpu/drm/i915/display/intel_crtc.c

189

crtc_state->hsw_workaround_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_crtc.c

190

crtc_state->scaler_state.scaler_id = -1;

drivers/gpu/drm/i915/display/intel_crtc.c

191

crtc_state->mst_master_transcoder = INVALID_TRANSCODER;

drivers/gpu/drm/i915/display/intel_crtc.c

192

crtc_state->max_link_bpp_x16 = INT_MAX;

drivers/gpu/drm/i915/display/intel_crtc.c

197

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_crtc.c

204

crtc_state = intel_crtc_state_alloc(crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

205

if (!crtc_state) {

drivers/gpu/drm/i915/display/intel_crtc.c

210

crtc->base.state = &crtc_state->uapi;

drivers/gpu/drm/i915/display/intel_crtc.c

211

crtc->config = crtc_state;

drivers/gpu/drm/i915/display/intel_crtc.c

490

static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

492

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

494

return crtc_state->hw.active &&

drivers/gpu/drm/i915/display/intel_crtc.c

495

!crtc_state->preload_luts &&

drivers/gpu/drm/i915/display/intel_crtc.c

496

!intel_crtc_needs_modeset(crtc_state) &&

drivers/gpu/drm/i915/display/intel_crtc.c

497

(intel_crtc_needs_color_update(crtc_state) &&

drivers/gpu/drm/i915/display/intel_crtc.c

499

!intel_color_uses_dsb(crtc_state) &&

drivers/gpu/drm/i915/display/intel_crtc.c

500

!crtc_state->use_dsb;

drivers/gpu/drm/i915/display/intel_crtc.c

506

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_crtc.c

507

container_of(work, typeof(*crtc_state), vblank_work);

drivers/gpu/drm/i915/display/intel_crtc.c

508

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

512

intel_color_load_luts(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

514

if (crtc_state->uapi.event) {

drivers/gpu/drm/i915/display/intel_crtc.c

516

drm_crtc_send_vblank_event(&crtc->base, crtc_state->uapi.event);

drivers/gpu/drm/i915/display/intel_crtc.c

518

crtc_state->uapi.event = NULL;

drivers/gpu/drm/i915/display/intel_crtc.c

524

static void intel_crtc_vblank_work_init(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

526

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

528

drm_vblank_work_init(&crtc_state->vblank_work, &crtc->base,

drivers/gpu/drm/i915/display/intel_crtc.c

539

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_crtc.c

542

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_crtc.c

543

if (!intel_crtc_needs_vblank_work(crtc_state))

drivers/gpu/drm/i915/display/intel_crtc.c

546

drm_vblank_work_flush(&crtc_state->vblank_work);

drivers/gpu/drm/i915/display/intel_crtc.c

687

void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

689

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

692

if (!crtc_state->uapi.event)

drivers/gpu/drm/i915/display/intel_crtc.c

698

drm_crtc_arm_vblank_event(&crtc->base, crtc_state->uapi.event);

drivers/gpu/drm/i915/display/intel_crtc.c

701

crtc_state->uapi.event = NULL;

drivers/gpu/drm/i915/display/intel_crtc.c

704

void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crtc.c

707

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

711

*event = crtc_state->uapi.event;

drivers/gpu/drm/i915/display/intel_crtc.c

714

crtc_state->uapi.event = NULL;

drivers/gpu/drm/i915/display/intel_crtc.c

862

unsigned int intel_crtc_bw_num_active_planes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

868

return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));

drivers/gpu/drm/i915/display/intel_crtc.c

871

unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

873

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

874

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_crtc.c

886

data_rate += crtc_state->data_rate[plane_id];

drivers/gpu/drm/i915/display/intel_crtc.c

889

data_rate += crtc_state->data_rate_y[plane_id];

drivers/gpu/drm/i915/display/intel_crtc.c

896

int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.c

898

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.c

903

return DIV_ROUND_UP_ULL(mul_u32_u32(intel_crtc_bw_data_rate(crtc_state), 10), 512);

drivers/gpu/drm/i915/display/intel_crtc.c

99

u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_crtc.h

36

void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.h

37

void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crtc.h

39

u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.h

44

void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_crtc.h

47

void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.h

48

void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.h

68

unsigned int intel_crtc_bw_num_active_planes(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.h

69

unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc.h

70

int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.h

13

void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

137

static int intel_check_cursor(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

153

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

166

-crtc_state->pipe_src.x1,

drivers/gpu/drm/i915/display/intel_cursor.c

167

-crtc_state->pipe_src.y1);

drivers/gpu/drm/i915/display/intel_cursor.c

198

static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cursor.c

202

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_cursor.c

226

static int i845_check_cursor(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

234

ret = intel_check_cursor(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

276

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

287

i845_cursor_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

292

pos = intel_cursor_position(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_cursor.c

317

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cursor.c

319

i845_cursor_update_arm(dsb, plane, crtc_state, NULL);

drivers/gpu/drm/i915/display/intel_cursor.c

379

static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cursor.c

381

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

382

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_cursor.c

388

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_cursor.c

391

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_cursor.c

41

static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

470

static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

479

ret = intel_check_cursor(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

534

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cursor.c

539

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/intel_cursor.c

547

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

552

int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1;

drivers/gpu/drm/i915/display/intel_cursor.c

56

y - crtc_state->psr2_su_area.y1);

drivers/gpu/drm/i915/display/intel_cursor.c

566

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

572

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/intel_cursor.c

576

if (crtc_state->enable_psr2_su_region_et) {

drivers/gpu/drm/i915/display/intel_cursor.c

577

u32 val = intel_cursor_position(crtc_state, plane_state,

drivers/gpu/drm/i915/display/intel_cursor.c

586

if (crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_cursor.c

587

wa_16021440873(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

589

i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

618

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cursor.c

623

const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;

drivers/gpu/drm/i915/display/intel_cursor.c

625

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/intel_cursor.c

651

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

663

i9xx_cursor_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

669

pos = intel_cursor_position(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_cursor.c

693

skl_write_cursor_wm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

696

i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

698

i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

720

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cursor.c

722

i9xx_cursor_update_arm(dsb, plane, crtc_state, NULL);

drivers/gpu/drm/i915/display/intel_cursor.c

815

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_cursor.c

830

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_cursor.c

831

intel_crtc_needs_modeset(crtc_state) ||

drivers/gpu/drm/i915/display/intel_cursor.c

832

intel_crtc_needs_fastset(crtc_state) ||

drivers/gpu/drm/i915/display/intel_cursor.c

833

crtc_state->joiner_pipes)

drivers/gpu/drm/i915/display/intel_cursor.c

881

ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

909

crtc_state->active_planes = new_crtc_state->active_planes;

drivers/gpu/drm/i915/display/intel_cursor.c

911

intel_vblank_evade_init(crtc_state, crtc_state, &evade);

drivers/gpu/drm/i915/display/intel_cursor.c

913

intel_psr_lock(crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

920

intel_psr_wait_for_idle_locked(crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

932

intel_plane_update_noarm(NULL, plane, crtc_state, new_plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

933

intel_plane_update_arm(NULL, plane, crtc_state, new_plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

935

intel_plane_disable_arm(NULL, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_cursor.c

940

intel_psr_unlock(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

1968

intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

1971

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

1972

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

1976

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2150

static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2155

bool is_dp = intel_crtc_has_dp_encoder(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2159

tables = intel_c10pll_tables_get(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2164

crtc_state->port_clock, crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2167

if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2172

crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2176

hw_state->cx0pll.lane_count = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2445

intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2448

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2450

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2451

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2465

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2613

intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2616

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2620

tables = intel_c20_pll_tables_get(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2628

if (intel_dpll_clock_matches(crtc_state->port_clock, clock))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2635

static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2641

table = intel_c20_pll_find_table(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2647

intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2652

static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2657

bool is_dp = intel_crtc_has_dp_encoder(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2661

hw_state->cx0pll.lane_count = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2668

err = intel_c20pll_calc_state_from_table(crtc_state, encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2673

err = intel_c20_compute_hdmi_tmds_pll(display, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2680

is_dp, crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2687

int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2694

return intel_c10pll_calc_state(crtc_state, encoder, hw_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2695

return intel_c20pll_calc_state(crtc_state, encoder, hw_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3419

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3424

intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3433

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3441

!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3592

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

425

static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

427

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

428

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_cx0_phy.c

429

(crtc_state->port_clock == 540000 ||

drivers/gpu/drm/i915/display/intel_cx0_phy.c

430

crtc_state->port_clock == 810000))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

439

static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

441

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

442

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_cx0_phy.c

443

(crtc_state->port_clock == 540000 ||

drivers/gpu/drm/i915/display/intel_cx0_phy.c

444

crtc_state->port_clock == 810000))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

479

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

495

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

506

C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

510

C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),

drivers/gpu/drm/i915/display/intel_cx0_phy.c

514

for (ln = 0; ln < crtc_state->lane_count; ln++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

515

int level = intel_ddi_level(encoder, crtc_state, ln);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

38

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

40

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

47

int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.h

60

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

84

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

86

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

118

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

120

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

121

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

126

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

138

&crtc_state->wm.skl.plane_ddb[plane_id],

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

139

crtc_state->data_rate[plane_id]);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

143

&crtc_state->wm.skl.plane_ddb_y[plane_id],

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

144

crtc_state->data_rate[plane_id]);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

239

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

242

skl_crtc_calc_dbuf_bw(&dbuf_bw_state->dbuf_bw[crtc->pipe], crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1000

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1004

intel_ddi_main_link_aux_domain(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1015

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1026

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))

drivers/gpu/drm/i915/display/intel_ddi.c

1037

main_link_aux_power_domain_get(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1041

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1043

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1044

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

1061

void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1063

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1064

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

1093

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

1100

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi.c

1109

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1129

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1135

intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1157

static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

1160

if (crtc_state->port_clock > 600000)

drivers/gpu/drm/i915/display/intel_ddi.c

1163

if (crtc_state->lane_count == 4)

drivers/gpu/drm/i915/display/intel_ddi.c

1170

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1178

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1182

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {

drivers/gpu/drm/i915/display/intel_ddi.c

1203

int level = intel_ddi_level(encoder, crtc_state, ln);

drivers/gpu/drm/i915/display/intel_ddi.c

1215

int level = intel_ddi_level(encoder, crtc_state, ln);

drivers/gpu/drm/i915/display/intel_ddi.c

1226

int level = intel_ddi_level(encoder, crtc_state, ln);

drivers/gpu/drm/i915/display/intel_ddi.c

1235

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1248

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi.c

1264

icl_combo_phy_loadgen_select(crtc_state, ln));

drivers/gpu/drm/i915/display/intel_ddi.c

1277

icl_ddi_combo_vswing_program(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1286

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1296

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1311

level = intel_ddi_level(encoder, crtc_state, 2*ln+0);

drivers/gpu/drm/i915/display/intel_ddi.c

1317

level = intel_ddi_level(encoder, crtc_state, 2*ln+1);

drivers/gpu/drm/i915/display/intel_ddi.c

1328

level = intel_ddi_level(encoder, crtc_state, 2*ln+0);

drivers/gpu/drm/i915/display/intel_ddi.c

1337

level = intel_ddi_level(encoder, crtc_state, 2*ln+1);

drivers/gpu/drm/i915/display/intel_ddi.c

135

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1357

crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1365

crtc_state->port_clock > 500000 ?

drivers/gpu/drm/i915/display/intel_ddi.c

1372

crtc_state->port_clock > 500000 ?

drivers/gpu/drm/i915/display/intel_ddi.c

1387

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1397

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1407

crtc_state->port_clock == 594000) ||

drivers/gpu/drm/i915/display/intel_ddi.c

1409

crtc_state->port_clock == 162000)) {

drivers/gpu/drm/i915/display/intel_ddi.c

1420

level = intel_ddi_level(encoder, crtc_state, 2*ln+0);

drivers/gpu/drm/i915/display/intel_ddi.c

143

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1430

level = intel_ddi_level(encoder, crtc_state, 2*ln+1);

drivers/gpu/drm/i915/display/intel_ddi.c

1446

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_ddi.c

1491

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

1496

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

1507

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

1514

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1518

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi.c

1521

level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

1532

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1536

int level = intel_ddi_level(encoder, crtc_state, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1541

skl_ddi_set_iboost(encoder, crtc_state, level);

drivers/gpu/drm/i915/display/intel_ddi.c

1544

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi.c

1603

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1606

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

1647

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1650

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

166

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

169

int level = intel_ddi_level(encoder, crtc_state, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1691

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1694

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

175

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_ddi.c

1757

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1760

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

1801

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1804

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

1816

icl_ddi_combo_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

1844

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1847

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

1855

icl_pll_to_ddi_clk_sel(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

1952

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

1955

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

2020

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2023

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

2087

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2090

encoder->enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2174

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2176

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2202

width = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_ddi.c

2265

tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2267

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))

drivers/gpu/drm/i915/display/intel_ddi.c

2268

return crtc_state->mst_master_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

2270

return crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

2274

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2280

tgl_dp_tp_transcoder(crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

2286

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2292

tgl_dp_tp_transcoder(crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

2298

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2302

intel_de_write(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2307

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2311

if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2317

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2322

if (!crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_ddi.c

2333

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2338

if (!crtc_state->fec_enable)

drivers/gpu/drm/i915/display/intel_ddi.c

2376

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2383

if (!crtc_state->fec_enable)

drivers/gpu/drm/i915/display/intel_ddi.c

2387

ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2390

ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2413

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2419

if (!crtc_state->fec_enable)

drivers/gpu/drm/i915/display/intel_ddi.c

2422

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2428

ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2435

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2438

ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false);

drivers/gpu/drm/i915/display/intel_ddi.c

2442

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2445

ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2454

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2458

if (!crtc_state->fec_enable)

drivers/gpu/drm/i915/display/intel_ddi.c

2461

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

2463

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

2467

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2476

crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_ddi.c

2533

static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2535

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2536

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

2543

if (crtc_state->splitter.enable) {

drivers/gpu/drm/i915/display/intel_ddi.c

2545

dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);

drivers/gpu/drm/i915/display/intel_ddi.c

2546

if (crtc_state->splitter.link_count == 2)

drivers/gpu/drm/i915/display/intel_ddi.c

2589

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2596

val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

2598

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

2625

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2629

bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_ddi.c

2634

crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_ddi.c

2635

crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

2641

intel_ddi_init_dp_buf_reg(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2656

intel_ddi_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2662

intel_ddi_enable_transcoder_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2669

intel_ddi_config_transcoder_func(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2674

intel_ddi_mso_configure(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

268

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

2682

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2686

crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2693

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2696

intel_dp_pcon_dsc_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

270

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

271

int clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_ddi.c

2717

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2720

if (!is_trans_port_sync_mode(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

2721

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2724

intel_ddi_enable_fec(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2727

if (!is_mst && intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

2729

ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_ddi.c

2731

intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2735

intel_dsc_dp_pps_write(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2740

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2746

bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_ddi.c

2750

crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_ddi.c

2751

crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

2757

intel_ddi_init_dp_buf_reg(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2784

intel_ddi_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2794

icl_program_mg_dp_mode(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2810

intel_ddi_enable_transcoder_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2816

intel_ddi_config_transcoder_func(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2827

encoder->set_signal_levels(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2833

intel_ddi_power_up_lanes(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2838

intel_ddi_mso_configure(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2843

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2847

crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2853

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2856

intel_dp_pcon_dsc_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2865

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2868

if (!is_trans_port_sync_mode(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

2869

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2872

intel_ddi_enable_fec(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2874

if (!is_mst && intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

2876

ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_ddi.c

2878

intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2882

intel_dsc_dp_pps_write(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2887

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2894

bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_ddi.c

2903

crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_ddi.c

2904

crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

2910

intel_ddi_init_dp_buf_reg(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2914

intel_ddi_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2922

icl_program_mg_dp_mode(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2925

hsw_prepare_dp_ddi_buffers(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2927

encoder->set_signal_levels(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2929

intel_ddi_power_up_lanes(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2933

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2937

crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2938

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2939

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2941

!is_trans_port_sync_mode(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

2942

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2944

intel_ddi_enable_fec(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2947

intel_ddi_enable_transcoder_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2948

intel_dsc_dp_pps_write(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2954

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2961

crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2967

mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2969

tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2971

hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2976

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))

drivers/gpu/drm/i915/display/intel_ddi.c

2977

intel_ddi_set_dp_msa(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2982

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

2990

intel_ddi_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2996

icl_program_mg_dp_mode(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2998

intel_ddi_enable_transcoder_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3001

crtc_state->has_infoframe,

drivers/gpu/drm/i915/display/intel_ddi.c

3002

crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3025

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3029

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

3032

drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3036

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3037

intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3042

intel_ddi_pre_enable_dp(state, encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3049

crtc_state->has_infoframe,

drivers/gpu/drm/i915/display/intel_ddi.c

3050

crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3096

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3108

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3109

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

3113

intel_ddi_disable_fec(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3118

intel_ddi_wait_for_fec_status(encoder, crtc_state, false);

drivers/gpu/drm/i915/display/intel_ddi.c

3326

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3332

if (!crtc_state->sync_mode_slaves_mask)

drivers/gpu/drm/i915/display/intel_ddi.c

3348

crtc_state->cpu_transcoder)

drivers/gpu/drm/i915/display/intel_ddi.c

3358

crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3363

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3372

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3375

intel_edp_backlight_on(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3377

intel_panel_prepare(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3380

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3382

trans_port_sync_stop_link_train(state, encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3406

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3416

crtc_state->hdmi_high_tmds_clock_ratio,

drivers/gpu/drm/i915/display/intel_ddi.c

3417

crtc_state->hdmi_scrambling))

drivers/gpu/drm/i915/display/intel_ddi.c

3423

hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3428

encoder->set_signal_levels(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3465

intel_ddi_power_up_lanes(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3486

port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

3494

buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

3508

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3513

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

3514

bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);

drivers/gpu/drm/i915/display/intel_ddi.c

3517

if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3518

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_ddi.c

3527

intel_ddi_enable_transcoder_func(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3529

intel_vrr_transcoder_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3532

if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3535

intel_ddi_clear_act_sent(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

354

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3540

intel_ddi_wait_for_act_sent(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3544

intel_enable_transcoder(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3546

intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

3548

for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_ddi.c

3556

intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3558

intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3560

intel_hdcp_enable(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

361

intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |

drivers/gpu/drm/i915/display/intel_ddi.c

3621

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3624

intel_ddi_set_dp_msa(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3626

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3628

intel_backlight_update(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3633

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3636

intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3641

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3645

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&

drivers/gpu/drm/i915/display/intel_ddi.c

3647

intel_ddi_update_pipe_dp(state, encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3650

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi.c

3651

intel_ddi_update_pipe_hdmi(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3654

intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3662

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_ddi.c

3671

intel_crtc_joined_pipe_mask(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

3683

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3691

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

3693

intel_tc_port_get_link(dig_port, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

3697

main_link_aux_power_domain_get(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

370

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

3704

intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

3707

crtc_state->lane_lat_optim_mask);

drivers/gpu/drm/i915/display/intel_ddi.c

3730

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3732

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3741

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3747

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||

drivers/gpu/drm/i915/display/intel_ddi.c

3748

intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3752

if (crtc_state->enhanced_framing)

drivers/gpu/drm/i915/display/intel_ddi.c

3755

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

3756

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3762

encoder->set_signal_levels(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3765

mtl_port_buf_ctl_program(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

377

intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_ddi.c

3778

intel_alpm_port_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3784

intel_lnl_mac_transmit_lfps(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3788

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3795

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3800

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||

drivers/gpu/drm/i915/display/intel_ddi.c

3801

intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

3805

if (crtc_state->enhanced_framing)

drivers/gpu/drm/i915/display/intel_ddi.c

3808

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

3809

intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3820

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3827

temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

383

int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_ddi.c

3848

intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);

drivers/gpu/drm/i915/display/intel_ddi.c

3852

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3858

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

3872

dp_tp_status_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_ddi.c

3891

static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3893

if (crtc_state->port_clock > 594000)

drivers/gpu/drm/i915/display/intel_ddi.c

3899

static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3901

if (crtc_state->port_clock > 594000)

drivers/gpu/drm/i915/display/intel_ddi.c

3907

static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3909

if (crtc_state->port_clock > 594000)

drivers/gpu/drm/i915/display/intel_ddi.c

3915

void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3917

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3920

crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3922

crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3924

crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3926

crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3958

static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

3960

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3965

crtc_state->master_transcoder =

drivers/gpu/drm/i915/display/intel_ddi.c

3966

bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3980

crtc_state->cpu_transcoder)

drivers/gpu/drm/i915/display/intel_ddi.c

3981

crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3987

crtc_state->master_transcoder != INVALID_TRANSCODER &&

drivers/gpu/drm/i915/display/intel_ddi.c

3988

crtc_state->sync_mode_slaves_mask);

drivers/gpu/drm/i915/display/intel_ddi.c

3992

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

3997

crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);

drivers/gpu/drm/i915/display/intel_ddi.c

3999

crtc_state->lane_count =

drivers/gpu/drm/i915/display/intel_ddi.c

4002

crtc_state->lane_count = 4;

drivers/gpu/drm/i915/display/intel_ddi.c

4006

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4009

crtc_state->has_hdmi_sink = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4011

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_ddi.c

4012

intel_hdmi_infoframes_enabled(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4014

if (crtc_state->infoframes.enable)

drivers/gpu/drm/i915/display/intel_ddi.c

4015

crtc_state->has_infoframe = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4018

crtc_state->hdmi_scrambling = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4020

crtc_state->hdmi_high_tmds_clock_ratio = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4022

intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);

drivers/gpu/drm/i915/display/intel_ddi.c

4026

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4031

crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);

drivers/gpu/drm/i915/display/intel_ddi.c

4032

crtc_state->enhanced_framing =

drivers/gpu/drm/i915/display/intel_ddi.c

4033

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

drivers/gpu/drm/i915/display/intel_ddi.c

4038

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4042

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

4044

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

4047

crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);

drivers/gpu/drm/i915/display/intel_ddi.c

4049

crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);

drivers/gpu/drm/i915/display/intel_ddi.c

4050

crtc_state->lane_count =

drivers/gpu/drm/i915/display/intel_ddi.c

4055

crtc_state->mst_master_transcoder =

drivers/gpu/drm/i915/display/intel_ddi.c

4058

intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_ddi.c

4059

intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/intel_ddi.c

4061

crtc_state->enhanced_framing =

drivers/gpu/drm/i915/display/intel_ddi.c

4062

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

drivers/gpu/drm/i915/display/intel_ddi.c

4066

crtc_state->fec_enable =

drivers/gpu/drm/i915/display/intel_ddi.c

4068

dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

4071

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_ddi.c

4072

intel_lspcon_infoframes_enabled(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4074

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_ddi.c

4075

intel_hdmi_infoframes_enabled(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4079

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4083

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

4084

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

4086

crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_ddi.c

4087

crtc_state->lane_count =

drivers/gpu/drm/i915/display/intel_ddi.c

4091

crtc_state->mst_master_transcoder =

drivers/gpu/drm/i915/display/intel_ddi.c

4094

intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_ddi.c

4097

crtc_state->fec_enable =

drivers/gpu/drm/i915/display/intel_ddi.c

4099

dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

4101

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_ddi.c

4102

intel_hdmi_infoframes_enabled(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

420

void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4228

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

423

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4233

struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];

drivers/gpu/drm/i915/display/intel_ddi.c

424

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

4243

icl_set_active_port_dpll(crtc_state, port_dpll_id);

drivers/gpu/drm/i915/display/intel_ddi.c

4245

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_ddi.c

4246

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4255

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4264

port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];

drivers/gpu/drm/i915/display/intel_ddi.c

427

if (!intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

4274

icl_set_active_port_dpll(crtc_state, port_dpll_id);

drivers/gpu/drm/i915/display/intel_ddi.c

4276

if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))

drivers/gpu/drm/i915/display/intel_ddi.c

4277

crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4279

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_ddi.c

4280

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4282

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4292

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4296

mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,

drivers/gpu/drm/i915/display/intel_ddi.c

4301

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4306

mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,

drivers/gpu/drm/i915/display/intel_ddi.c

4309

mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY,

drivers/gpu/drm/i915/display/intel_ddi.c

4314

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4316

intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);

drivers/gpu/drm/i915/display/intel_ddi.c

4317

crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);

drivers/gpu/drm/i915/display/intel_ddi.c

4319

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4323

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4325

intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4326

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4330

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4332

intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4333

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4337

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4339

intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

434

switch (crtc_state->pipe_bpp) {

drivers/gpu/drm/i915/display/intel_ddi.c

4340

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4344

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4346

intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4347

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4352

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4355

const struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_ddi.c

4368

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4373

return encoder->port_pll_type(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4377

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4393

port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];

drivers/gpu/drm/i915/display/intel_ddi.c

4399

icl_set_active_port_dpll(crtc_state, port_dpll_id);

drivers/gpu/drm/i915/display/intel_ddi.c

4401

if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))

drivers/gpu/drm/i915/display/intel_ddi.c

4402

crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);

drivers/gpu/drm/i915/display/intel_ddi.c

4404

crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_ddi.c

4405

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4409

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4411

icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4412

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4416

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4418

intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4419

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4423

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4425

intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4426

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4430

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4432

intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4433

intel_ddi_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4437

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4441

crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4443

if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||

drivers/gpu/drm/i915/display/intel_ddi.c

4444

(!crtc_state && intel_encoder_is_dp(encoder)))

drivers/gpu/drm/i915/display/intel_ddi.c

4445

intel_dp_sync_state(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4449

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

4457

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4461

if (intel_crtc_has_dp_encoder(crtc_state) &&

drivers/gpu/drm/i915/display/intel_ddi.c

4462

!intel_dp_initial_fastset_check(encoder, crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

4470

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

448

MISSING_CASE(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_ddi.c

453

drm_WARN_ON(display->drm, crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_ddi.c

454

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);

drivers/gpu/drm/i915/display/intel_ddi.c

456

if (crtc_state->limited_color_range)

drivers/gpu/drm/i915/display/intel_ddi.c

4589

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_ddi.c

4598

crtc_state = intel_atomic_get_new_crtc_state(state,

drivers/gpu/drm/i915/display/intel_ddi.c

4601

crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

4603

transcoders |= BIT(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4610

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4618

if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

4619

ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_ddi.c

4626

crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);

drivers/gpu/drm/i915/display/intel_ddi.c

4629

port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

4637

crtc_state->master_transcoder = TRANSCODER_EDP;

drivers/gpu/drm/i915/display/intel_ddi.c

4639

crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;

drivers/gpu/drm/i915/display/intel_ddi.c

464

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)

drivers/gpu/drm/i915/display/intel_ddi.c

4641

if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {

drivers/gpu/drm/i915/display/intel_ddi.c

4642

crtc_state->master_transcoder = INVALID_TRANSCODER;

drivers/gpu/drm/i915/display/intel_ddi.c

4643

crtc_state->sync_mode_slaves_mask =

drivers/gpu/drm/i915/display/intel_ddi.c

4644

port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

473

if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))

drivers/gpu/drm/i915/display/intel_ddi.c

4752

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_ddi.c

4775

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_ddi.c

4778

!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));

drivers/gpu/drm/i915/display/intel_ddi.c

4780

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_ddi.c

4783

if (!crtc_state->hdmi_high_tmds_clock_ratio &&

drivers/gpu/drm/i915/display/intel_ddi.c

4784

!crtc_state->hdmi_scrambling)

drivers/gpu/drm/i915/display/intel_ddi.c

4799

crtc_state->hdmi_high_tmds_clock_ratio &&

drivers/gpu/drm/i915/display/intel_ddi.c

4801

crtc_state->hdmi_scrambling)

drivers/gpu/drm/i915/display/intel_ddi.c

489

intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

492

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

493

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

499

if (enable && intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

513

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

515

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

516

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

518

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

529

switch (crtc_state->pipe_bpp) {

drivers/gpu/drm/i915/display/intel_ddi.c

531

MISSING_CASE(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_ddi.c

547

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)

drivers/gpu/drm/i915/display/intel_ddi.c

549

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)

drivers/gpu/drm/i915/display/intel_ddi.c

562

if (crtc_state->pch_pfit.force_thru)

drivers/gpu/drm/i915/display/intel_ddi.c

576

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_ddi.c

577

if (crtc_state->has_hdmi_sink)

drivers/gpu/drm/i915/display/intel_ddi.c

582

if (crtc_state->hdmi_scrambling)

drivers/gpu/drm/i915/display/intel_ddi.c

584

if (crtc_state->hdmi_high_tmds_clock_ratio)

drivers/gpu/drm/i915/display/intel_ddi.c

587

temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

588

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {

drivers/gpu/drm/i915/display/intel_ddi.c

590

temp |= (crtc_state->fdi_lanes - 1) << 1;

drivers/gpu/drm/i915/display/intel_ddi.c

591

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||

drivers/gpu/drm/i915/display/intel_ddi.c

592

intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

593

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

597

temp |= DDI_PORT_WIDTH(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

602

master = crtc_state->mst_master_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

610

temp |= DDI_PORT_WIDTH(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_ddi.c

614

crtc_state->master_transcoder != INVALID_TRANSCODER) {

drivers/gpu/drm/i915/display/intel_ddi.c

616

bdw_trans_port_sync_master_select(crtc_state->master_transcoder);

drivers/gpu/drm/i915/display/intel_ddi.c

626

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

628

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

629

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

632

enum transcoder master_transcoder = crtc_state->master_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

650

crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

660

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

662

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

663

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

666

intel_ddi_config_transcoder_dp2(crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

668

ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

680

void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

682

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

683

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_ddi.c

684

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_ddi.c

704

if (!intel_dp_mst_is_master_trans(crtc_state)) {

drivers/gpu/drm/i915/display/intel_ddi.c

715

if (intel_dp_mst_is_slave_trans(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

716

intel_ddi_config_transcoder_dp2(crtc_state, false);

drivers/gpu/drm/i915/display/intel_ddi.c

719

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_ddi.c

955

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

972

if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state))

drivers/gpu/drm/i915/display/intel_ddi.c

975

(intel_crtc_has_dp_encoder(crtc_state) ||

drivers/gpu/drm/i915/display/intel_ddi.c

984

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.c

988

intel_ddi_main_link_aux_domain(dig_port, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

27

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

30

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

32

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

39

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

42

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.h

45

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

50

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

52

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

55

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

61

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

63

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

64

void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

66

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

67

void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

69

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.h

71

void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.h

74

void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.h

76

void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.h

82

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1212

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1215

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1217

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1225

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1228

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1230

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1232

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1260

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1263

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1265

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1274

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1277

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1279

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1288

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1291

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1293

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1302

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1305

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1307

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1316

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1319

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1321

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1330

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1333

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1335

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1344

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1347

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1349

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1358

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1367

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1370

if (crtc_state->port_clock > 540000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1378

return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1383

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1386

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1388

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1389

return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1391

return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1396

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1399

if (crtc_state->port_clock > 270000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1410

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1413

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1416

return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1421

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1424

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1432

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1435

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1437

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1439

return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1446

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1449

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1457

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1460

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1462

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1464

return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1471

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1476

if (crtc_state->port_clock > 270000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1492

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1495

if (crtc_state->port_clock > 540000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1506

return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1511

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1514

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1516

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1517

return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1519

return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1524

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1527

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1537

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1540

if (crtc_state->port_clock > 540000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1550

return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1555

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1558

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1560

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1561

return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1563

return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1568

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1571

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1579

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1582

if (crtc_state->port_clock > 540000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1593

return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1598

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1601

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1603

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1604

return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1606

return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1611

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1614

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1622

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1625

if (crtc_state->port_clock > 540000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1632

return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1637

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1640

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1642

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1643

return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1645

return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1650

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1653

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1661

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1664

if (crtc_state->port_clock > 540000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1675

return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1680

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1683

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1685

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1686

return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1688

return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1693

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1696

if (crtc_state->port_clock > 270000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1707

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1710

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1713

return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1718

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1721

if (crtc_state->port_clock > 270000) {

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1732

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1735

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1738

return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1743

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1746

if (intel_crtc_has_dp_encoder(crtc_state) &&

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1747

intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1755

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1763

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1766

if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1768

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1776

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1779

if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1781

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1857

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1860

return encoder->get_buf_trans(encoder, crtc_state, n_entries);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h

82

const struct intel_crtc_state *crtc_state, int *n_entries);

drivers/gpu/drm/i915/display/intel_display.c

1106

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

1108

u8 update_planes = crtc_state->update_planes;

drivers/gpu/drm/i915/display/intel_display.c

1123

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

1125

u8 update_planes = crtc_state->update_planes;

drivers/gpu/drm/i915/display/intel_display.c

1339

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

135

static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1354

crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_display.c

136

static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1361

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

137

static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1376

crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_display.c

1383

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

139

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1398

crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_display.c

141

static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

143

return (crtc_state->active_planes &

drivers/gpu/drm/i915/display/intel_display.c

1473

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

1488

crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_display.c

1492

static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

1494

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

1495

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

1497

if (crtc_state->has_pch_encoder) {

drivers/gpu/drm/i915/display/intel_display.c

1499

&crtc_state->fdi_m_n);

drivers/gpu/drm/i915/display/intel_display.c

1500

} else if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

1502

&crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_display.c

1504

&crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/intel_display.c

1507

intel_set_transcoder_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1509

ilk_set_pipeconf(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1587

static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

1589

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1591

return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;

drivers/gpu/drm/i915/display/intel_display.c

1603

static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

1605

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1606

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

1609

HSW_LINETIME(crtc_state->linetime) |

drivers/gpu/drm/i915/display/intel_display.c

1610

HSW_IPS_LINETIME(crtc_state->ips_linetime));

drivers/gpu/drm/i915/display/intel_display.c

1613

static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

1615

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1617

intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_display.c

1619

HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));

drivers/gpu/drm/i915/display/intel_display.c

1622

static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

1624

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1625

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

1626

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

1628

if (crtc_state->has_pch_encoder) {

drivers/gpu/drm/i915/display/intel_display.c

1630

&crtc_state->fdi_m_n);

drivers/gpu/drm/i915/display/intel_display.c

1631

} else if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

1633

&crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_display.c

1635

&crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/intel_display.c

1638

intel_set_transcoder_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1642

crtc_state->pixel_multiplier - 1);

drivers/gpu/drm/i915/display/intel_display.c

1644

hsw_set_frame_start_delay(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1646

hsw_set_transconf(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

177

is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

179

return crtc_state->master_transcoder != INVALID_TRANSCODER;

drivers/gpu/drm/i915/display/intel_display.c

183

is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

185

return crtc_state->sync_mode_slaves_mask != 0;

drivers/gpu/drm/i915/display/intel_display.c

189

is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

191

return is_trans_port_sync_master(crtc_state) ||

drivers/gpu/drm/i915/display/intel_display.c

192

is_trans_port_sync_slave(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

195

static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

1967

static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

197

return ffs(crtc_state->joiner_pipes) - 1;

drivers/gpu/drm/i915/display/intel_display.c

1970

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

1971

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

1972

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

1978

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_display.c

1983

if (crtc_state->pch_pfit.enabled ||

drivers/gpu/drm/i915/display/intel_display.c

1984

crtc_state->pch_pfit.force_thru)

drivers/gpu/drm/i915/display/intel_display.c

1988

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_display.c

1994

if (HAS_DDI(display) && crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_display.c

1997

if (crtc_state->intel_dpll)

drivers/gpu/drm/i915/display/intel_display.c

2000

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_display.c

2004

void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

2007

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2008

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2012

get_crtc_power_domains(crtc_state, &domains);

drivers/gpu/drm/i915/display/intel_display.c

2039

static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

204

static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2041

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2042

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

2044

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

2046

&crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_display.c

2048

&crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/intel_display.c

2051

intel_set_transcoder_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2053

i9xx_set_pipeconf(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

206

return hweight8(crtc_state->joiner_pipes) >= 2;

drivers/gpu/drm/i915/display/intel_display.c

209

static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

211

if (!is_bigjoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

214

return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

217

static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

219

if (!is_bigjoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2209

static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2211

u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_display.c

2219

if (!crtc_state->pch_pfit.enabled)

drivers/gpu/drm/i915/display/intel_display.c

222

return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

2223

drm_rect_width(&crtc_state->pipe_src) << 16,

drivers/gpu/drm/i915/display/intel_display.c

2224

drm_rect_height(&crtc_state->pipe_src) << 16);

drivers/gpu/drm/i915/display/intel_display.c

2226

return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,

drivers/gpu/drm/i915/display/intel_display.c

225

bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2251

static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2253

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2257

crtc_state->pixel_rate =

drivers/gpu/drm/i915/display/intel_display.c

2258

crtc_state->hw.pipe_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_display.c

2260

crtc_state->pixel_rate =

drivers/gpu/drm/i915/display/intel_display.c

2261

ilk_pipe_pixel_rate(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2264

static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

2267

int num_pipes = intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

227

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2281

static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

2284

int overlap = crtc_state->splitter.pixel_overlap;

drivers/gpu/drm/i915/display/intel_display.c

2285

int n = crtc_state->splitter.link_count;

drivers/gpu/drm/i915/display/intel_display.c

2287

if (!crtc_state->splitter.enable)

drivers/gpu/drm/i915/display/intel_display.c

229

if (!is_bigjoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2305

static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2307

struct drm_display_mode *mode = &crtc_state->hw.mode;

drivers/gpu/drm/i915/display/intel_display.c

2308

struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_display.c

2309

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_display.c

2318

intel_splitter_adjust_timings(crtc_state, pipe_mode);

drivers/gpu/drm/i915/display/intel_display.c

232

return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2330

mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *

drivers/gpu/drm/i915/display/intel_display.c

2331

intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2332

mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_display.c

2335

intel_joiner_adjust_timings(crtc_state, pipe_mode);

drivers/gpu/drm/i915/display/intel_display.c

2338

intel_crtc_compute_pixel_rate(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2342

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2344

encoder->get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2346

intel_crtc_readout_derived_state(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2349

static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

235

bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2351

int num_pipes = intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2357

width = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_display.c

2358

height = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_display.c

2360

drm_rect_init(&crtc_state->pipe_src, 0, 0,

drivers/gpu/drm/i915/display/intel_display.c

2364

static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2366

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2367

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2369

intel_joiner_compute_pipe_src(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

237

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2377

if (drm_rect_width(&crtc_state->pipe_src) & 1) {

drivers/gpu/drm/i915/display/intel_display.c

2378

if (crtc_state->double_wide) {

drivers/gpu/drm/i915/display/intel_display.c

2385

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&

drivers/gpu/drm/i915/display/intel_display.c

239

if (!is_bigjoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2397

static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2399

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2400

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2401

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_display.c

2402

struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_display.c

2412

intel_splitter_adjust_timings(crtc_state, pipe_mode);

drivers/gpu/drm/i915/display/intel_display.c

2415

intel_joiner_adjust_timings(crtc_state, pipe_mode);

drivers/gpu/drm/i915/display/intel_display.c

242

return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2428

crtc_state->double_wide = true;

drivers/gpu/drm/i915/display/intel_display.c

2437

str_yes_no(crtc_state->double_wide));

drivers/gpu/drm/i915/display/intel_display.c

2444

static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2446

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

245

u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2453

intel_psr_min_set_context_latency(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

2462

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

2465

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_display.c

2468

set_context_latency = intel_crtc_set_context_latency(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

247

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2480

crtc_state->set_context_latency = set_context_latency;

drivers/gpu/drm/i915/display/intel_display.c

2489

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

249

if (!is_bigjoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2501

ret = intel_crtc_compute_pipe_src(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2505

ret = intel_crtc_compute_pipe_mode(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2509

intel_crtc_compute_pixel_rate(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2511

if (crtc_state->has_pch_encoder)

drivers/gpu/drm/i915/display/intel_display.c

2512

return ilk_fdi_compute_config(crtc, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2514

intel_vrr_compute_guardband(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

252

return bigjoiner_primary_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

255

u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

257

return bigjoiner_secondary_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

260

bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

262

return intel_crtc_num_joined_pipes(crtc_state) >= 4;

drivers/gpu/drm/i915/display/intel_display.c

265

static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2659

transcoder_has_vrr(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2661

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2662

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

2667

static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2669

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

267

if (!intel_crtc_is_ultrajoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2670

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2672

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

2673

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_display.c

2691

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))

drivers/gpu/drm/i915/display/intel_display.c

270

return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

2707

crtc_state->set_context_latency);

drivers/gpu/drm/i915/display/intel_display.c

2716

crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_display.c

273

bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

275

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

277

return intel_crtc_is_ultrajoiner(crtc_state) &&

drivers/gpu/drm/i915/display/intel_display.c

2773

crtc_state->min_hblank);

drivers/gpu/drm/i915/display/intel_display.c

2777

static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2779

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

278

BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2780

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

2781

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_display.c

2800

crtc_state->set_context_latency);

drivers/gpu/drm/i915/display/intel_display.c

2809

crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_display.c

2836

intel_vrr_set_fixed_rr_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2837

intel_vrr_transcoder_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2840

static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2842

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2843

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2844

int width = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_display.c

2845

int height = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_display.c

2855

static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2857

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2858

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

286

static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

288

if (!intel_crtc_is_ultrajoiner(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

291

return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

294

bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2940

static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2942

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2943

int num_pipes = intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2950

primary_pipe = joiner_primary_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2951

width = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_display.c

2953

drm_rect_translate_to(&crtc_state->pipe_src,

drivers/gpu/drm/i915/display/intel_display.c

296

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

2972

void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

2974

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2975

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

298

return intel_crtc_is_ultrajoiner(crtc_state) &&

drivers/gpu/drm/i915/display/intel_display.c

2983

if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

2986

if (crtc_state->double_wide)

drivers/gpu/drm/i915/display/intel_display.c

299

BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

2993

if (crtc_state->dither && crtc_state->pipe_bpp != 30)

drivers/gpu/drm/i915/display/intel_display.c

2997

switch (crtc_state->pipe_bpp) {

drivers/gpu/drm/i915/display/intel_display.c

3000

MISSING_CASE(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_display.c

3014

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {

drivers/gpu/drm/i915/display/intel_display.c

3016

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))

drivers/gpu/drm/i915/display/intel_display.c

302

u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3025

crtc_state->limited_color_range)

drivers/gpu/drm/i915/display/intel_display.c

3028

val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_display.c

3030

if (crtc_state->wgc_enable)

drivers/gpu/drm/i915/display/intel_display.c

3033

val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

drivers/gpu/drm/i915/display/intel_display.c

304

if (crtc_state->joiner_pipes)

drivers/gpu/drm/i915/display/intel_display.c

305

return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

310

bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

312

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

314

return crtc_state->joiner_pipes &&

drivers/gpu/drm/i915/display/intel_display.c

315

crtc->pipe != joiner_primary_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3172

void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3174

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3175

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

318

bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3182

if (!intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

3185

switch (crtc_state->pipe_bpp) {

drivers/gpu/drm/i915/display/intel_display.c

3188

MISSING_CASE(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_display.c

320

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

3204

if (crtc_state->dither)

drivers/gpu/drm/i915/display/intel_display.c

3207

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

drivers/gpu/drm/i915/display/intel_display.c

3216

drm_WARN_ON(display->drm, crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_display.c

3217

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);

drivers/gpu/drm/i915/display/intel_display.c

3219

if (crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_display.c

322

return crtc_state->joiner_pipes &&

drivers/gpu/drm/i915/display/intel_display.c

3220

!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))

drivers/gpu/drm/i915/display/intel_display.c

3223

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

drivers/gpu/drm/i915/display/intel_display.c

3226

val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);

drivers/gpu/drm/i915/display/intel_display.c

3228

val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

drivers/gpu/drm/i915/display/intel_display.c

3229

val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);

drivers/gpu/drm/i915/display/intel_display.c

323

crtc->pipe == joiner_primary_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3235

static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3237

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3238

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_display.c

3245

if (!intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

3248

if (display->platform.haswell && crtc_state->dither)

drivers/gpu/drm/i915/display/intel_display.c

3252

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

drivers/gpu/drm/i915/display/intel_display.c

3259

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

drivers/gpu/drm/i915/display/intel_display.c

326

int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3267

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3269

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3270

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

3273

switch (crtc_state->pipe_bpp) {

drivers/gpu/drm/i915/display/intel_display.c

328

return hweight8(intel_crtc_joined_pipe_mask(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

3289

MISSING_CASE(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_display.c

3293

if (crtc_state->dither)

drivers/gpu/drm/i915/display/intel_display.c

3296

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||

drivers/gpu/drm/i915/display/intel_display.c

3297

crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)

drivers/gpu/drm/i915/display/intel_display.c

3300

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

drivers/gpu/drm/i915/display/intel_display.c

3304

if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

331

u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

333

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

335

return BIT(crtc->pipe) | crtc_state->joiner_pipes;

drivers/gpu/drm/i915/display/intel_display.c

338

struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

340

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

342

if (intel_crtc_is_joiner_secondary(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

343

return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

345

return to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

3957

static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

3959

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

3960

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

3969

crtc_state->joiner_pipes = primary_pipe | secondary_pipes;

drivers/gpu/drm/i915/display/intel_display.c

4068

bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

4070

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4071

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

4073

if (!display->modeset.funcs->get_pipe_config(crtc, crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

4076

crtc_state->hw.active = true;

drivers/gpu/drm/i915/display/intel_display.c

4078

intel_crtc_readout_derived_state(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4134

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

4148

crtc_state = intel_crtc_state_alloc(crtc);

drivers/gpu/drm/i915/display/intel_display.c

4149

if (!crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

4154

if (!intel_crtc_get_pipe_config(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

4155

intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_display.c

4160

intel_encoder_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4162

intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_display.c

4164

intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_display.c

4199

static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

4202

&crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_display.c

4205

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_display.c

4214

static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

4218

&crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_display.c

4221

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_display.c

4230

static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

4232

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4234

&crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_display.c

4237

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_display.c

4241

crtc_state->pixel_rate);

drivers/gpu/drm/i915/display/intel_display.c

4255

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4260

crtc_state->linetime = skl_linetime_wm(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4262

crtc_state->linetime = hsw_linetime_wm(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4271

crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

4281

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4286

intel_crtc_needs_modeset(crtc_state) &&

drivers/gpu/drm/i915/display/intel_display.c

4287

!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_display.c

4288

crtc_state->update_wm_post = true;

drivers/gpu/drm/i915/display/intel_display.c

4290

if (intel_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

4309

if (intel_crtc_needs_modeset(crtc_state) ||

drivers/gpu/drm/i915/display/intel_display.c

4310

intel_crtc_needs_fastset(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

4311

ret = skl_update_scaler_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4361

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

4363

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4382

crtc_state->max_pipe_bpp = min(crtc_state->pipe_bpp, max_edid_bpp);

drivers/gpu/drm/i915/display/intel_display.c

4384

if (target_pipe_bpp < crtc_state->pipe_bpp) {

drivers/gpu/drm/i915/display/intel_display.c

4391

crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_display.c

4393

crtc_state->pipe_bpp = target_pipe_bpp;

drivers/gpu/drm/i915/display/intel_display.c

4420

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4426

crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);

drivers/gpu/drm/i915/display/intel_display.c

4435

ret = compute_sink_pipe_bpp(connector_state, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4516

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4519

WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

4521

drm_property_replace_blob(&crtc_state->hw.degamma_lut,

drivers/gpu/drm/i915/display/intel_display.c

4522

crtc_state->uapi.degamma_lut);

drivers/gpu/drm/i915/display/intel_display.c

4523

drm_property_replace_blob(&crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_display.c

4524

crtc_state->uapi.gamma_lut);

drivers/gpu/drm/i915/display/intel_display.c

4525

drm_property_replace_blob(&crtc_state->hw.ctm,

drivers/gpu/drm/i915/display/intel_display.c

4526

crtc_state->uapi.ctm);

drivers/gpu/drm/i915/display/intel_display.c

4527

crtc_state->hw.background_color =

drivers/gpu/drm/i915/display/intel_display.c

4528

intel_color_background_color_drm_to_hw(crtc_state->uapi.background_color);

drivers/gpu/drm/i915/display/intel_display.c

4535

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4538

WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

4540

crtc_state->hw.enable = crtc_state->uapi.enable;

drivers/gpu/drm/i915/display/intel_display.c

4541

crtc_state->hw.active = crtc_state->uapi.active;

drivers/gpu/drm/i915/display/intel_display.c

4542

drm_mode_copy(&crtc_state->hw.mode,

drivers/gpu/drm/i915/display/intel_display.c

4543

&crtc_state->uapi.mode);

drivers/gpu/drm/i915/display/intel_display.c

4544

drm_mode_copy(&crtc_state->hw.adjusted_mode,

drivers/gpu/drm/i915/display/intel_display.c

4545

&crtc_state->uapi.adjusted_mode);

drivers/gpu/drm/i915/display/intel_display.c

4546

crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;

drivers/gpu/drm/i915/display/intel_display.c

4547

crtc_state->hw.sharpness_strength = crtc_state->uapi.sharpness_strength;

drivers/gpu/drm/i915/display/intel_display.c

4637

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4647

intel_crtc_free_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4649

err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

4661

saved_state->uapi = crtc_state->uapi;

drivers/gpu/drm/i915/display/intel_display.c

4662

saved_state->inherited = crtc_state->inherited;

drivers/gpu/drm/i915/display/intel_display.c

4663

saved_state->scaler_state = crtc_state->scaler_state;

drivers/gpu/drm/i915/display/intel_display.c

4664

saved_state->intel_dpll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_display.c

4665

saved_state->dpll_hw_state = crtc_state->dpll_hw_state;

drivers/gpu/drm/i915/display/intel_display.c

4666

memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,

drivers/gpu/drm/i915/display/intel_display.c

4668

saved_state->crc_enabled = crtc_state->crc_enabled;

drivers/gpu/drm/i915/display/intel_display.c

4671

saved_state->wm = crtc_state->wm;

drivers/gpu/drm/i915/display/intel_display.c

4673

memcpy(crtc_state, saved_state, sizeof(*crtc_state));

drivers/gpu/drm/i915/display/intel_display.c

4687

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4694

crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

drivers/gpu/drm/i915/display/intel_display.c

4696

crtc_state->framestart_delay = 1;

drivers/gpu/drm/i915/display/intel_display.c

4703

if (!(crtc_state->hw.adjusted_mode.flags &

drivers/gpu/drm/i915/display/intel_display.c

4705

crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;

drivers/gpu/drm/i915/display/intel_display.c

4707

if (!(crtc_state->hw.adjusted_mode.flags &

drivers/gpu/drm/i915/display/intel_display.c

4709

crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;

drivers/gpu/drm/i915/display/intel_display.c

4715

crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe);

drivers/gpu/drm/i915/display/intel_display.c

4716

crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];

drivers/gpu/drm/i915/display/intel_display.c

4718

if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {

drivers/gpu/drm/i915/display/intel_display.c

4722

FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));

drivers/gpu/drm/i915/display/intel_display.c

4723

crtc_state->bw_constrained = true;

drivers/gpu/drm/i915/display/intel_display.c

4726

base_bpp = crtc_state->pipe_bpp;

drivers/gpu/drm/i915/display/intel_display.c

4736

drm_mode_get_hv_timing(&crtc_state->hw.mode,

drivers/gpu/drm/i915/display/intel_display.c

4738

drm_rect_init(&crtc_state->pipe_src, 0, 0,

drivers/gpu/drm/i915/display/intel_display.c

4760

crtc_state->output_types |=

drivers/gpu/drm/i915/display/intel_display.c

4761

BIT(encoder->compute_output_type(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

4764

crtc_state->output_types |= BIT(encoder->type);

drivers/gpu/drm/i915/display/intel_display.c

4768

crtc_state->port_clock = 0;

drivers/gpu/drm/i915/display/intel_display.c

4769

crtc_state->pixel_multiplier = 1;

drivers/gpu/drm/i915/display/intel_display.c

4772

drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,

drivers/gpu/drm/i915/display/intel_display.c

4786

ret = encoder->compute_config(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

4799

if (!crtc_state->port_clock)

drivers/gpu/drm/i915/display/intel_display.c

4800

crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock

drivers/gpu/drm/i915/display/intel_display.c

4801

* crtc_state->pixel_multiplier;

drivers/gpu/drm/i915/display/intel_display.c

4816

crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&

drivers/gpu/drm/i915/display/intel_display.c

4817

!crtc_state->dither_force_disable;

drivers/gpu/drm/i915/display/intel_display.c

4821

base_bpp, crtc_state->pipe_bpp, crtc_state->dither);

drivers/gpu/drm/i915/display/intel_display.c

4830

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

4846

ret = encoder->compute_config_late(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

5538

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

5542

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

5565

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_display.c

5589

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5592

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_display.c

5593

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5594

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5596

if (!crtc_state->hw.enable ||

drivers/gpu/drm/i915/display/intel_display.c

5597

intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5600

ret = intel_modeset_pipe(state, crtc_state, reason);

drivers/gpu/drm/i915/display/intel_display.c

5609

intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

5611

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_display.c

5613

crtc_state->update_pipe = false;

drivers/gpu/drm/i915/display/intel_display.c

5614

crtc_state->update_m_n = false;

drivers/gpu/drm/i915/display/intel_display.c

5615

crtc_state->update_lrr = false;

drivers/gpu/drm/i915/display/intel_display.c

5636

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5639

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_display.c

5640

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5641

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5643

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_display.c

5644

intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5647

ret = intel_modeset_pipe(state, crtc_state, reason);

drivers/gpu/drm/i915/display/intel_display.c

5651

intel_crtc_flag_modeset(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5653

crtc_state->update_planes |= crtc_state->active_planes;

drivers/gpu/drm/i915/display/intel_display.c

5654

crtc_state->async_flip_planes = 0;

drivers/gpu/drm/i915/display/intel_display.c

5655

crtc_state->do_async_flip = false;

drivers/gpu/drm/i915/display/intel_display.c

5677

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

5680

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

5681

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5685

crtc_state->uapi.connectors_changed = true;

drivers/gpu/drm/i915/display/intel_display.c

5704

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5711

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

5712

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_display.c

5713

!intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5717

other_crtc_state = crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5720

first_crtc_state = crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5731

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_display.c

5732

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5733

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

5735

crtc_state->hsw_workaround_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_display.c

5737

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_display.c

5738

intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

5759

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5762

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

5763

if (crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_display.c

5775

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5778

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

5779

if (crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_display.c

581

void intel_set_plane_visible(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.c

5847

struct intel_crtc_state __maybe_unused *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

5850

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

590

crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);

drivers/gpu/drm/i915/display/intel_display.c

592

crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);

drivers/gpu/drm/i915/display/intel_display.c

595

void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

597

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

605

crtc_state->enabled_planes = 0;

drivers/gpu/drm/i915/display/intel_display.c

606

crtc_state->active_planes = 0;

drivers/gpu/drm/i915/display/intel_display.c

609

crtc_state->uapi.plane_mask) {

drivers/gpu/drm/i915/display/intel_display.c

610

crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);

drivers/gpu/drm/i915/display/intel_display.c

611

crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);

drivers/gpu/drm/i915/display/intel_display.c

619

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

6235

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display.c

6252

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_display.c

6253

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

6254

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

6258

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

6259

affected_pipes |= crtc_state->joiner_pipes;

drivers/gpu/drm/i915/display/intel_display.c

6260

if (intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

6261

modeset_pipes |= crtc_state->joiner_pipes;

drivers/gpu/drm/i915/display/intel_display.c

6265

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_display.c

6266

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

6267

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

6273

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_display.c

6275

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_display.c

6286

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_display.c

6288

if (intel_crtc_needs_modeset(crtc_state) &&

drivers/gpu/drm/i915/display/intel_display.c

6289

intel_crtc_is_joiner_primary(crtc_state))

drivers/gpu/drm/i915/display/intel_display.c

629

intel_plane_set_invisible(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_display.c

630

intel_set_plane_visible(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_display.c

631

intel_plane_fixup_bitmasks(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

635

if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&

drivers/gpu/drm/i915/display/intel_display.c

636

hsw_ips_disable(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

637

crtc_state->ips_enabled = false;

drivers/gpu/drm/i915/display/intel_display.c

658

if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)

drivers/gpu/drm/i915/display/intel_display.c

661

intel_plane_disable_arm(NULL, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

6616

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

6620

if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)

drivers/gpu/drm/i915/display/intel_display.c

6623

if (crtc_state->has_pch_encoder) {

drivers/gpu/drm/i915/display/intel_display.c

676

static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

678

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

679

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.c

7175

static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

7177

if (crtc_state->dsb_commit)

drivers/gpu/drm/i915/display/intel_display.c

7178

intel_dsb_wait(crtc_state->dsb_commit);

drivers/gpu/drm/i915/display/intel_display.c

7180

intel_color_wait_commit(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

7183

static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

7185

if (crtc_state->dsb_commit) {

drivers/gpu/drm/i915/display/intel_display.c

7186

intel_dsb_cleanup(crtc_state->dsb_commit);

drivers/gpu/drm/i915/display/intel_display.c

7187

crtc_state->dsb_commit = NULL;

drivers/gpu/drm/i915/display/intel_display.c

7190

intel_color_cleanup_commit(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

768

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

777

primary_crtc = intel_primary_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

804

static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

806

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

808

if (!crtc_state->nv12_planes)

drivers/gpu/drm/i915/display/intel_display.c

818

static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

820

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

823

if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)

drivers/gpu/drm/i915/display/intel_display.c

829

static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

8291

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

8294

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

8295

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

8299

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_display.c

8300

crtc_state->inherited = false;

drivers/gpu/drm/i915/display/intel_display.c

8302

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_display.c

831

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

8315

crtc_state->uapi.color_mgmt_changed = true;

drivers/gpu/drm/i915/display/intel_display.c

8318

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_display.c

8320

!encoder->initial_fastset_check(encoder, crtc_state)) {

drivers/gpu/drm/i915/display/intel_display.c

834

if (is_hdr_mode(crtc_state) &&

drivers/gpu/drm/i915/display/intel_display.c

835

crtc_state->active_planes & BIT(PLANE_CURSOR) &&

drivers/gpu/drm/i915/display/intel_display.c

861

static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display.c

863

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

865

return crtc_state->uapi.async_flip && intel_display_vtd_active(display) &&

drivers/gpu/drm/i915/display/intel_display.c

873

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display.c

887

encoder->audio_enable(encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_display.h

314

crtc_state) \

drivers/gpu/drm/i915/display/intel_display.h

315

for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \

drivers/gpu/drm/i915/display/intel_display.h

316

((crtc_state)->uapi.plane_mask)) \

drivers/gpu/drm/i915/display/intel_display.h

318

to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))

drivers/gpu/drm/i915/display/intel_display.h

340

#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state) \

drivers/gpu/drm/i915/display/intel_display.h

342

_intel_modeset_primary_pipes(crtc_state), \

drivers/gpu/drm/i915/display/intel_display.h

343

_intel_modeset_secondary_pipes(crtc_state), \

drivers/gpu/drm/i915/display/intel_display.h

346

#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state) \

drivers/gpu/drm/i915/display/intel_display.h

348

_intel_modeset_primary_pipes(crtc_state), \

drivers/gpu/drm/i915/display/intel_display.h

349

_intel_modeset_secondary_pipes(crtc_state), \

drivers/gpu/drm/i915/display/intel_display.h

376

u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

377

bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

378

bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

379

bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

380

bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

381

bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

382

bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

383

bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

384

u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

385

u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

386

u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

387

struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

388

bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

393

void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

394

void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

405

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

452

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

458

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

461

void intel_set_plane_visible(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.h

464

void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

480

void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display.h

519

int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1021

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1037

crtc_state = to_intel_crtc_state(crtc->state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1038

seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1087

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1103

crtc_state = to_intel_crtc_state(crtc->state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1105

intel_output_format_name(crtc_state->output_format));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1233

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1240

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1241

seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

413

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

422

crtc_state->scaler_state.scaler_users,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

423

crtc_state->scaler_state.scaler_id,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

424

crtc_state->hw.scaling_filter,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

425

crtc_state->hw.sharpness_strength);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

429

&crtc_state->scaler_state.scalers[i];

drivers/gpu/drm/i915/display/intel_display_debugfs.c

548

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

556

str_yes_no(crtc_state->uapi.enable),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

557

str_yes_no(crtc_state->uapi.active),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

558

DRM_MODE_ARG(&crtc_state->uapi.mode));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

561

str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

563

DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

565

DRM_MODE_ARG(&crtc_state->hw.pipe_mode));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

568

DRM_RECT_ARG(&crtc_state->pipe_src),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

569

str_yes_no(crtc_state->dither), crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

571

crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

576

u32 background = crtc_state->hw.background_color;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

581

if (crtc_state->joiner_pipes)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

583

crtc_state->joiner_pipes,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

584

intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master");

drivers/gpu/drm/i915/display/intel_display_debugfs.c

586

intel_vdsc_state_dump(&p, 1, crtc_state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

589

crtc_state->uapi.encoder_mask)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

674

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

682

entry = &crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/intel_display_debugfs.c

688

entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];

drivers/gpu/drm/i915/display/intel_display_debugfs.c

782

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

788

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

789

commit = crtc_state->uapi.commit;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

796

if (!ret && crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

801

intel_crtc_arm_fifo_underrun(crtc, crtc_state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

906

struct intel_crtc_state *crtc_state = NULL;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

940

crtc_state = to_intel_crtc_state(crtc->state);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

942

str_yes_no(crtc_state->dsc.compression_enable));

drivers/gpu/drm/i915/display/intel_display_driver.c

710

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_display_driver.c

724

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/i915/display/intel_display_driver.c

730

crtc_state->mode_changed = true;

drivers/gpu/drm/i915/display/intel_display_types.h

1622

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1627

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1632

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1637

int (*check_plane)(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1640

int (*min_cdclk)(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1644

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1659

#define to_intel_crtc_state(crtc_state) \

drivers/gpu/drm/i915/display/intel_display_types.h

1660

container_of_const((crtc_state), struct intel_crtc_state, uapi)

drivers/gpu/drm/i915/display/intel_display_types.h

1903

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1905

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1908

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1912

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

2011

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

2015

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

2020

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

215

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

2222

intel_crtc_has_type(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

2225

return crtc_state->output_types & BIT(type);

drivers/gpu/drm/i915/display/intel_display_types.h

2229

intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_types.h

2231

return crtc_state->output_types &

drivers/gpu/drm/i915/display/intel_display_types.h

2238

intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_types.h

2240

return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_display_types.h

2244

intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_types.h

2246

return crtc_state->update_pipe;

drivers/gpu/drm/i915/display/intel_display_types.h

2250

intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_types.h

2252

return crtc_state->uapi.color_mgmt_changed ||

drivers/gpu/drm/i915/display/intel_display_types.h

2253

intel_crtc_needs_fastset(crtc_state) ||

drivers/gpu/drm/i915/display/intel_display_types.h

2254

intel_crtc_needs_modeset(crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

236

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

243

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

250

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

278

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

288

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

290

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

293

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_display_types.h

308

void (*enable)(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

539

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

767

static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dmc.c

769

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

776

if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_dmc.c

782

void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dmc.c

784

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

785

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dmc.c

792

if (!can_enable_pipedmc(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dmc.c

793

intel_dmc_disable_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

817

void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dmc.c

819

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.c

820

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dmc.h

24

void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dmc.h

25

void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

129

bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

131

return drm_dp_is_uhbr_rate(crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_dp.c

1798

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

1803

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&

drivers/gpu/drm/i915/display/intel_dp.c

1804

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

1807

return intel_dsc_source_support(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

1811

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

1814

int clock = crtc_state->hw.adjusted_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_dp.c

1832

if (intel_hdmi_bpc_possible(crtc_state, bpc,

drivers/gpu/drm/i915/display/intel_dp.c

1834

intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,

drivers/gpu/drm/i915/display/intel_dp.c

1843

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

1850

bpc = crtc_state->max_pipe_bpp / 3;

drivers/gpu/drm/i915/display/intel_dp.c

1858

max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,

drivers/gpu/drm/i915/display/intel_dp.c

1894

static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

1898

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

2052

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

2055

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_dp.c

2065

vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_dp.c

2069

ret = intel_dsc_compute_params(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

2483

bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2486

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

2494

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_dp.c

2497

return dsc_enabled_on_crtc || intel_dsc_enabled_on_link(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

2500

void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

2502

crtc_state->fec_enable = false;

drivers/gpu/drm/i915/display/intel_dp.c

2504

crtc_state->dsc.compression_enable = false;

drivers/gpu/drm/i915/display/intel_dp.c

2505

crtc_state->dsc.compressed_bpp_x16 = 0;

drivers/gpu/drm/i915/display/intel_dp.c

2507

memset(&crtc_state->dsc.slice_config, 0, sizeof(crtc_state->dsc.slice_config));

drivers/gpu/drm/i915/display/intel_dp.c

2508

memset(&crtc_state->dsc.config, 0, sizeof(crtc_state->dsc.config));

drivers/gpu/drm/i915/display/intel_dp.c

2704

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2711

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

2712

const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp.c

2716

max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,

drivers/gpu/drm/i915/display/intel_dp.c

2729

crtc_state->output_format);

drivers/gpu/drm/i915/display/intel_dp.c

2735

intel_crtc_num_joined_pipes(crtc_state),

drivers/gpu/drm/i915/display/intel_dp.c

2736

crtc_state->output_format,

drivers/gpu/drm/i915/display/intel_dp.c

2795

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2801

bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_dp.c

2813

limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);

drivers/gpu/drm/i915/display/intel_dp.c

2823

limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);

drivers/gpu/drm/i915/display/intel_dp.c

2825

limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2830

if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp.c

2839

crtc_state)));

drivers/gpu/drm/i915/display/intel_dp.c

2863

limits->pipe.max_bpp = clamp(crtc_state->pipe_bpp, limits->pipe.min_bpp,

drivers/gpu/drm/i915/display/intel_dp.c

2869

if (limits->pipe.max_bpp != crtc_state->pipe_bpp)

drivers/gpu/drm/i915/display/intel_dp.c

2873

crtc_state->pipe_bpp, limits->pipe.max_bpp);

drivers/gpu/drm/i915/display/intel_dp.c

2891

intel_dp_test_compute_config(intel_dp, crtc_state, limits);

drivers/gpu/drm/i915/display/intel_dp.c

2894

crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2899

int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

2902

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

2903

int link_bpp_x16 = crtc_state->dsc.compression_enable ?

drivers/gpu/drm/i915/display/intel_dp.c

2904

crtc_state->dsc.compressed_bpp_x16 :

drivers/gpu/drm/i915/display/intel_dp.c

2905

fxp_q4_from_int(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_dp.c

2907

return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp.c

3026

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3030

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp.c

3034

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

3039

if (crtc_state->fec_enable &&

drivers/gpu/drm/i915/display/intel_dp.c

3040

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

3058

crtc_state->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,

drivers/gpu/drm/i915/display/intel_dp.c

3061

ret = intel_dp_compute_link_for_joined_pipes(encoder, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3068

crtc_state->joiner_pipes = 0;

drivers/gpu/drm/i915/display/intel_dp.c

3073

bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3079

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

3088

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

drivers/gpu/drm/i915/display/intel_dp.c

3097

return crtc_state->pipe_bpp != 18 &&

drivers/gpu/drm/i915/display/intel_dp.c

3116

static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3120

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3122

if (crtc_state->has_panel_replay) {

drivers/gpu/drm/i915/display/intel_dp.c

3141

switch (crtc_state->output_format) {

drivers/gpu/drm/i915/display/intel_dp.c

3187

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

drivers/gpu/drm/i915/display/intel_dp.c

3194

vsc->bpc = crtc_state->pipe_bpp / 3;

drivers/gpu/drm/i915/display/intel_dp.c

3202

vsc->dynamic_range = crtc_state->limited_color_range ?

drivers/gpu/drm/i915/display/intel_dp.c

3211

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

3222

if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp.c

3226

return intel_vrr_possible(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3230

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

3232

struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;

drivers/gpu/drm/i915/display/intel_dp.c

3234

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

3241

if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

3244

crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);

drivers/gpu/drm/i915/display/intel_dp.c

3250

as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3252

if (crtc_state->cmrr.enable) {

drivers/gpu/drm/i915/display/intel_dp.c

3256

} else if (crtc_state->vrr.enable) {

drivers/gpu/drm/i915/display/intel_dp.c

3276

as_sdp->coasting_vtotal = crtc_state->vrr.vmax;

drivers/gpu/drm/i915/display/intel_dp.c

3280

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3286

!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&

drivers/gpu/drm/i915/display/intel_dp.c

3287

!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_dp.c

3290

vsc = &crtc_state->infoframes.vsc;

drivers/gpu/drm/i915/display/intel_dp.c

3292

crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);

drivers/gpu/drm/i915/display/intel_dp.c

3296

if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {

drivers/gpu/drm/i915/display/intel_dp.c

3297

intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3299

} else if (crtc_state->has_panel_replay) {

drivers/gpu/drm/i915/display/intel_dp.c

3307

} else if (crtc_state->has_sel_update) {

drivers/gpu/drm/i915/display/intel_dp.c

3342

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3347

struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;

drivers/gpu/drm/i915/display/intel_dp.c

3360

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_dp.c

3456

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3463

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

3469

crtc_state->sink_format = sink_format;

drivers/gpu/drm/i915/display/intel_dp.c

3470

crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);

drivers/gpu/drm/i915/display/intel_dp.c

3472

return intel_dp_compute_link_config(encoder, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3478

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3486

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

3490

ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3498

ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3503

ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3508

ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

3532

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

3544

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {

drivers/gpu/drm/i915/display/intel_dp.c

3559

int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3562

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3564

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp.c

3566

int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;

drivers/gpu/drm/i915/display/intel_dp.c

3571

int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;

drivers/gpu/drm/i915/display/intel_dp.c

3572

bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_dp.c

3573

int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3584

if (!is_mst && !intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

3587

if (crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_dp.c

3598

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.c

3599

link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_dp.c

3601

link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format,

drivers/gpu/drm/i915/display/intel_dp.c

3602

crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_dp.c

3628

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp.c

3635

(crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_dp.c

3636

crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&

drivers/gpu/drm/i915/display/intel_dp.c

3637

crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));

drivers/gpu/drm/i915/display/intel_dp.c

3643

crtc_state->min_hblank = min_hblank;

drivers/gpu/drm/i915/display/intel_dp.c

3783

void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

3786

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

3794

intel_backlight_enable(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

4111

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

4120

if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {

drivers/gpu/drm/i915/display/intel_dp.c

4125

intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);

drivers/gpu/drm/i915/display/intel_dp.c

4127

if (crtc_state) {

drivers/gpu/drm/i915/display/intel_dp.c

4129

intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

4135

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

4146

crtc_state->port_clock) < 0) {

drivers/gpu/drm/i915/display/intel_dp.c

4150

crtc_state->uapi.connectors_changed = true;

drivers/gpu/drm/i915/display/intel_dp.c

4161

if (crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_dp.c

4165

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_dp.c

4173

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_dp.c

4398

intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

4400

int vactive = crtc_state->hw.adjusted_mode.vdisplay;

drivers/gpu/drm/i915/display/intel_dp.c

4407

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

4416

return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,

drivers/gpu/drm/i915/display/intel_dp.c

4423

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

4428

int output_format = crtc_state->output_format;

drivers/gpu/drm/i915/display/intel_dp.c

4441

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

4468

slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

4472

num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

4476

slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,

drivers/gpu/drm/i915/display/intel_dp.c

4479

bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

4497

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

4518

if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {

drivers/gpu/drm/i915/display/intel_dp.c

4519

switch (crtc_state->output_format) {

drivers/gpu/drm/i915/display/intel_dp.c

4530

MISSING_CASE(crtc_state->output_format);

drivers/gpu/drm/i915/display/intel_dp.c

4533

} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {

drivers/gpu/drm/i915/display/intel_dp.c

4534

switch (crtc_state->output_format) {

drivers/gpu/drm/i915/display/intel_dp.c

4541

MISSING_CASE(crtc_state->output_format);

drivers/gpu/drm/i915/display/intel_dp.c

5224

intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5232

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

drivers/gpu/drm/i915/display/intel_dp.c

5360

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5368

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp.c

5374

len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);

drivers/gpu/drm/i915/display/intel_dp.c

5378

&crtc_state->infoframes.drm.drm,

drivers/gpu/drm/i915/display/intel_dp.c

5382

len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,

drivers/gpu/drm/i915/display/intel_dp.c

5393

dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);

drivers/gpu/drm/i915/display/intel_dp.c

5398

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5402

intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp.c

5420

if (!enable || !crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_dp.c

5429

intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);

drivers/gpu/drm/i915/display/intel_dp.c

5430

intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);

drivers/gpu/drm/i915/display/intel_dp.c

5432

intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);

drivers/gpu/drm/i915/display/intel_dp.c

5542

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5551

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp.c

5555

dig_port->read_infoframe(encoder, crtc_state, type, &sdp,

drivers/gpu/drm/i915/display/intel_dp.c

5610

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5619

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp.c

5623

dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));

drivers/gpu/drm/i915/display/intel_dp.c

5632

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5641

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp.c

5645

dig_port->read_infoframe(encoder, crtc_state, type, &sdp,

drivers/gpu/drm/i915/display/intel_dp.c

5657

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5662

intel_read_dp_vsc_sdp(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5663

&crtc_state->infoframes.vsc);

drivers/gpu/drm/i915/display/intel_dp.c

5666

intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5667

&crtc_state->infoframes.drm.drm);

drivers/gpu/drm/i915/display/intel_dp.c

5670

intel_read_dp_as_sdp(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

5671

&crtc_state->infoframes.as_sdp);

drivers/gpu/drm/i915/display/intel_dp.c

5944

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp.c

5958

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_dp.c

5961

!intel_crtc_has_dp_encoder(crtc_state));

drivers/gpu/drm/i915/display/intel_dp.c

5963

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_dp.c

6791

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

6795

if (crtc_state && crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_dp.c

6854

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp.c

6873

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_dp.c

6874

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_dp.c

6894

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp.c

6897

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_dp.c

6898

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

6899

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

6901

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_dp.c

6904

if (!(transcoders & BIT(crtc_state->cpu_transcoder)))

drivers/gpu/drm/i915/display/intel_dp.c

6907

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_dp.c

6917

transcoders &= ~BIT(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp.c

7551

int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp.c

7553

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7554

int guardband = intel_crtc_vblank_length(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7555

int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);

drivers/gpu/drm/i915/display/intel_dp.c

7567

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

7573

intel_psr_compute_config_late(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7575

ret = intel_dp_sdp_compute_config_late(crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7579

intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7585

int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type)

drivers/gpu/drm/i915/display/intel_dp.c

7596

return crtc_state->vrr.vsync_start + 1;

drivers/gpu/drm/i915/display/intel_dp.c

7604

int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

7610

crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp.c

7613

intel_dp_get_lines_for_sdp(crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

7617

crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_dp.c

7619

intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));

drivers/gpu/drm/i915/display/intel_dp.c

7621

if (crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp.c

7624

intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));

drivers/gpu/drm/i915/display/intel_dp.h

108

int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

136

bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

139

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

142

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

179

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

183

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

187

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

189

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

193

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

202

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

219

int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

226

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

228

int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

41

bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

48

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

55

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

66

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

79

bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

81

void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

92

bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.h

99

void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

303

intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

306

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

333

panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

492

intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

509

panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1004

if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1022

intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1024

if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1029

if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1036

if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1054

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1065

intel_dp_is_uhbr(crtc_state));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1067

training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1073

if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1090

crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1098

crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1105

intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1107

if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1124

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1132

if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1146

crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1154

crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1193

if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1197

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1210

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1214

if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1218

lane_count = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1219

if (crtc_state->enhanced_framing)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1236

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1267

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1275

intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1278

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1279

ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1298

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1303

if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1306

if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1315

crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1340

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1347

i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1405

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1411

lane_count = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1412

link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1414

lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1427

static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1431

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1432

return reduce_link_params_in_bw_order(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1435

return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1440

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1452

if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1464

crtc_state->lane_count, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1475

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1488

} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1493

intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1501

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1510

ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1518

ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1521

intel_dp->set_idle_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1524

ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1526

intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1536

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1550

if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1565

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1566

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1572

if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1596

if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1616

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1619

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1668

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1698

drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1724

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1730

ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1738

if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1739

intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1745

crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1757

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1778

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1799

intel_dp_prepare_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1801

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1802

passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1804

passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1836

if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1848

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1856

if (!intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

338

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

349

voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

393

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

401

lane = min(lane, crtc_state->lane_count - 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

404

for (lane = 0; lane < crtc_state->lane_count; lane++)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

413

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

424

lane = min(lane, crtc_state->lane_count - 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

429

for (lane = 0; lane < crtc_state->lane_count; lane++) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

441

voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

449

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

454

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

455

return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

458

return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

487

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

494

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

498

crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

505

crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

511

u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

533

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

541

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

546

memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

547

len = crtc_state->lane_count + 1;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

569

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

579

intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

608

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

613

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

617

crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

624

crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

630

encoder->set_signal_levels(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

635

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

640

intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

641

return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

646

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

654

intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

657

intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

659

return ret == crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

696

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

700

for (lane = 0; lane < crtc_state->lane_count; lane++) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

703

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

730

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

732

return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

733

(crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_dp_link_training.c

738

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

754

crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

755

crtc_state->vrr.in_range,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

756

intel_dp_pr_with_as_sdp_enabled(intel_dp, crtc_state));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

796

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

803

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

817

} else if (crtc_state->port_clock == 810000) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

835

} else if (crtc_state->port_clock >= 540000) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

848

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

852

intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

856

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

859

intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

860

crtc_state->enhanced_framing,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

861

intel_dp_use_post_lt_adj_req(intel_dp, crtc_state));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

870

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

875

intel_dp->prepare_link_retrain(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

877

intel_dp_compute_rate(intel_dp, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

911

intel_dp_update_downspread_ctrl(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

912

intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

918

static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

924

for (lane = 0; lane < crtc_state->lane_count; lane++) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

927

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

960

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

971

intel_dp_is_uhbr(crtc_state));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

974

if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

28

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

32

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

36

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

40

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

42

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

55

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1195

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1198

crtc_state->port_clock, crtc_state->lane_count))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1204

crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1269

static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1271

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1282

if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1283

set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1287

if (intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1288

set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1289

else if (crtc_state->fec_enable)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1290

clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1292

if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1293

set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1390

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1394

return intel_dp_initial_fastset_check(primary_encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

143

static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

146

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

148

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp_mst.c

150

if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)

drivers/gpu/drm/i915/display/intel_dp_mst.c

173

return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,

drivers/gpu/drm/i915/display/intel_dp_mst.c

178

static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

182

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp_mst.c

186

flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;

drivers/gpu/drm/i915/display/intel_dp_mst.c

188

return intel_dp_link_bw_overhead(crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_mst.c

189

crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_mst.c

196

static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1968

bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1970

return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1973

bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1975

return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

1976

crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_dp_mst.c

202

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp_mst.c

205

intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_mst.c

207

crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_mst.c

227

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_mst.c

230

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp_mst.c

231

int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

239

static void mst_stream_update_slots(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

242

u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?

drivers/gpu/drm/i915/display/intel_dp_mst.c

249

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

254

struct drm_atomic_commit *state = crtc_state->uapi.state;

drivers/gpu/drm/i915/display/intel_dp_mst.c

259

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp_mst.c

260

bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

drivers/gpu/drm/i915/display/intel_dp_mst.c

281

mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_mst.c

282

crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_mst.c

284

mst_stream_update_slots(crtc_state, mst_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

292

crtc_state->fec_enable = intel_dp_needs_8b10b_fec(crtc_state, dsc);

drivers/gpu/drm/i915/display/intel_dp_mst.c

300

if (crtc_state->fec_enable && dsc &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

301

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

304

max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));

drivers/gpu/drm/i915/display/intel_dp_mst.c

315

dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

338

intel_dp_output_format_link_bpp_x16(crtc_state->output_format,

drivers/gpu/drm/i915/display/intel_dp_mst.c

341

local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

344

intel_dp_mst_compute_m_n(crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

347

&crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_dp_mst.c

354

remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

383

remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_mst.c

394

drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_dp_mst.c

395

crtc_state->dp_m_n.tu = remote_tu;

drivers/gpu/drm/i915/display/intel_dp_mst.c

406

crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,

drivers/gpu/drm/i915/display/intel_dp_mst.c

407

4 / crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_mst.c

409

if (crtc_state->dp_m_n.tu <= 64)

drivers/gpu/drm/i915/display/intel_dp_mst.c

410

slots = crtc_state->dp_m_n.tu;

drivers/gpu/drm/i915/display/intel_dp_mst.c

419

drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_dp_mst.c

432

crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);

drivers/gpu/drm/i915/display/intel_dp_mst.c

434

crtc_state->dsc.compressed_bpp_x16 = bpp_x16;

drivers/gpu/drm/i915/display/intel_dp_mst.c

443

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

447

crtc_state->lane_count = limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

448

crtc_state->port_clock = limits->max_rate;

drivers/gpu/drm/i915/display/intel_dp_mst.c

454

return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

461

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

468

crtc_state->pipe_bpp = limits->pipe.max_bpp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

474

crtc_state->lane_count = limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

475

crtc_state->port_clock = limits->max_rate;

drivers/gpu/drm/i915/display/intel_dp_mst.c

477

return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

493

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

497

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dp_mst.c

511

if (!intel_dp_mst_dsc_get_slice_count(connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

520

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

525

const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp_mst.c

528

if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))

drivers/gpu/drm/i915/display/intel_dp_mst.c

532

if (intel_dp_supports_dsc(intel_dp, connector, crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

580

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

588

crtc_state, false, dsc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

594

crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

786

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp_mst.c

793

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_dp_mst.c

795

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_dp_mst.c

798

transcoders |= BIT(crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

845

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dp_mst.c

849

if (drm_WARN_ON(display->drm, !crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

852

if (intel_dsc_enabled_on_link(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

929

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

936

crtc_state->mst_master_transcoder =

drivers/gpu/drm/i915/display/intel_dp_mst.c

970

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp_mst.c

988

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_dp_mst.c

989

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

990

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

997

crtc_state->uapi.mode_changed = true;

drivers/gpu/drm/i915/display/intel_dp_mst.h

22

bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.h

23

bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_mst.h

35

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_test.c

221

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_test.c

226

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp_test.c

236

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_test.c

297

intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_test.c

307

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_test.c

321

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_test.c

324

intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_test.c

326

intel_dp_phy_pattern_update(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_test.c

329

intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_test.c

417

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp_test.c

431

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_dp_test.c

434

!intel_crtc_has_dp_encoder(crtc_state));

drivers/gpu/drm/i915/display/intel_dp_test.c

436

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_dp_test.c

475

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dp_test.c

480

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&

drivers/gpu/drm/i915/display/intel_dp_test.c

481

!intel_dp_mst_is_master_trans(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_test.c

484

intel_dp_process_phy_request(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

150

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

152

int stream_bw = intel_dp_config_required_rate(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

352

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

394

if (crtc_state) {

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

395

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

567

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

570

if (!crtc_state->dp_tunnel_ref.tunnel)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

579

crtc_state->dp_tunnel_ref.tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

581

return intel_dp_tunnel_atomic_add_group_state(state, crtc_state->dp_tunnel_ref.tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

642

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

646

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

647

int required_rate = intel_dp_config_required_rate(crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

668

&crtc_state->dp_tunnel_ref);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

684

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

686

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

689

if (!crtc_state->dp_tunnel_ref.tunnel)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

693

crtc_state->dp_tunnel_ref.tunnel,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

698

drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

774

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

779

encoder = intel_get_crtc_new_encoder(state, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

790

intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

796

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

798

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

800

struct drm_dp_tunnel *tunnel = crtc_state->dp_tunnel_ref.tunnel;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

803

if (!intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

814

queue_retry_work(state, tunnel, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

30

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

43

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

45

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

71

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

92

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

99

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1011

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1021

__chv_data_lane_soft_reset(encoder, crtc_state, false);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1073

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1101

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1129

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1134

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

296

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

304

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

318

for (lane = 0; lane < crtc_state->lane_count; lane++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

319

int level = intel_ddi_level(encoder, crtc_state, lane);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

327

for (lane = 0; lane < crtc_state->lane_count; lane++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

328

int level = intel_ddi_level(encoder, crtc_state, lane);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

342

for (lane = 0; lane < crtc_state->lane_count; lane++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

343

int level = intel_ddi_level(encoder, crtc_state, lane);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

716

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

736

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

749

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

757

for (i = 0; i < crtc_state->lane_count; i++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

765

for (i = 0; i < crtc_state->lane_count; i++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

788

for (i = 0; i < crtc_state->lane_count; i++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

802

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

812

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

828

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

845

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

857

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

863

__chv_data_lane_soft_reset(encoder, crtc_state, reset);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

868

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

872

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

877

intel_dp_unused_lane_mask(crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

893

__chv_data_lane_soft_reset(encoder, crtc_state, true);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

923

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

949

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

966

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

973

for (i = 0; i < crtc_state->lane_count; i++) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

975

if (crtc_state->lane_count == 1)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

983

if (crtc_state->port_clock > 270000)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

985

else if (crtc_state->port_clock > 135000)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

987

else if (crtc_state->port_clock > 67500)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

989

else if (crtc_state->port_clock > 33750)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

998

if (crtc_state->lane_count > 2) {

drivers/gpu/drm/i915/display/intel_dpio_phy.h

131

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

137

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

142

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.h

146

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.h

158

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

164

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.h

168

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpio_phy.h

33

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

51

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

55

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

58

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

60

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

66

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpio_phy.h

70

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

72

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpio_phy.h

83

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1000

return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1003

static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

1007

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1012

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))

drivers/gpu/drm/i915/display/intel_dpll.c

1019

dpll |= (crtc_state->pixel_multiplier - 1)

drivers/gpu/drm/i915/display/intel_dpll.c

1023

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||

drivers/gpu/drm/i915/display/intel_dpll.c

1024

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll.c

1027

if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll.c

1061

if (crtc_state->sdvo_tv_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1063

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&

drivers/gpu/drm/i915/display/intel_dpll.c

1072

static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

1076

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1077

struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1087

hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);

drivers/gpu/drm/i915/display/intel_dpll.c

1090

hw_state->dpll_md = i965_dpll_md(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1093

static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

1097

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1102

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1128

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))

drivers/gpu/drm/i915/display/intel_dpll.c

1131

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&

drivers/gpu/drm/i915/display/intel_dpll.c

1140

static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

1144

struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1149

hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);

drivers/gpu/drm/i915/display/intel_dpll.c

1156

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1159

intel_get_crtc_new_encoder(state, crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1163

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1171

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1175

if (!crtc_state->has_pch_encoder)

drivers/gpu/drm/i915/display/intel_dpll.c

1176

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1185

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1188

intel_get_crtc_new_encoder(state, crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1191

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1200

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1203

intel_get_crtc_new_encoder(state, crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1206

ret = intel_mpllb_calc_state(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_dpll.c

1210

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1215

static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1217

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1219

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&

drivers/gpu/drm/i915/display/intel_dpll.c

1224

if (crtc_state->sdvo_tv_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1246

static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

1250

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1255

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))

drivers/gpu/drm/i915/display/intel_dpll.c

1260

dpll |= (crtc_state->pixel_multiplier - 1)

drivers/gpu/drm/i915/display/intel_dpll.c

1263

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||

drivers/gpu/drm/i915/display/intel_dpll.c

1264

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll.c

1267

if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll.c

1285

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))

drivers/gpu/drm/i915/display/intel_dpll.c

1309

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&

drivers/gpu/drm/i915/display/intel_dpll.c

1318

static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

1322

struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1323

int factor = ilk_fb_cb_factor(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1328

hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);

drivers/gpu/drm/i915/display/intel_dpll.c

1335

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1342

if (!crtc_state->has_pch_encoder)

drivers/gpu/drm/i915/display/intel_dpll.c

1345

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1368

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1369

!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1370

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1373

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1375

ilk_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1376

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1382

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1383

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1391

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1395

if (!crtc_state->has_pch_encoder)

drivers/gpu/drm/i915/display/intel_dpll.c

1401

static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1403

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1413

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1419

void vlv_compute_dpll(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1421

struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1423

hw_state->dpll = vlv_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1424

hw_state->dpll_md = i965_dpll_md(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1427

static u32 chv_dpll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1429

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1439

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1445

void chv_compute_dpll(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1447

struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1449

hw_state->dpll = chv_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1450

hw_state->dpll_md = i965_dpll_md(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1456

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1461

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1462

!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1463

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1466

chv_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1468

chv_compute_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1471

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1474

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1475

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1483

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1488

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1489

!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1490

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1493

vlv_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1495

vlv_compute_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1498

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll.c

1501

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1502

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1511

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1516

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1528

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||

drivers/gpu/drm/i915/display/intel_dpll.c

1529

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1531

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1538

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1539

!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1540

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1543

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1545

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1546

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1548

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1550

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))

drivers/gpu/drm/i915/display/intel_dpll.c

1551

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1560

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1565

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1578

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1579

!pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1580

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1583

pnv_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1585

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1586

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1588

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1589

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1598

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1603

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1616

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1617

!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1618

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1621

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1623

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1624

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1626

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1628

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))

drivers/gpu/drm/i915/display/intel_dpll.c

1629

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1638

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1643

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1652

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1658

if (!crtc_state->clock_set &&

drivers/gpu/drm/i915/display/intel_dpll.c

1659

!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1660

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1663

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1665

i8xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1666

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1668

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1669

crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1726

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1730

drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));

drivers/gpu/drm/i915/display/intel_dpll.c

1732

memset(&crtc_state->dpll_hw_state, 0,

drivers/gpu/drm/i915/display/intel_dpll.c

1733

sizeof(crtc_state->dpll_hw_state));

drivers/gpu/drm/i915/display/intel_dpll.c

1735

if (!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_dpll.c

1752

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll.c

1756

drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));

drivers/gpu/drm/i915/display/intel_dpll.c

1757

drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1759

if (!crtc_state->hw.enable || crtc_state->intel_dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

1810

void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1812

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1813

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1814

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1818

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

1889

static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1891

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1892

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1893

const struct dpll *clock = &crtc_state->dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1938

if (crtc_state->port_clock == 162000 ||

drivers/gpu/drm/i915/display/intel_dpll.c

1939

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||

drivers/gpu/drm/i915/display/intel_dpll.c

1940

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll.c

1945

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_dpll.c

1961

if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll.c

1970

static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1972

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1973

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1974

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1985

void vlv_enable_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

1987

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1988

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1989

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

1992

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

2002

vlv_prepare_pll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2003

_vlv_enable_pll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2010

static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

2012

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2013

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

2014

const struct dpll *clock = &crtc_state->dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

2099

static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

2101

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2102

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

2103

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

2131

void chv_enable_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

2133

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2134

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

2135

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

2138

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

2148

chv_prepare_pll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2149

_chv_enable_pll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2193

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_dpll.c

2195

crtc_state = intel_crtc_state_alloc(crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

2196

if (!crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

2199

crtc_state->cpu_transcoder = (enum transcoder)pipe;

drivers/gpu/drm/i915/display/intel_dpll.c

2200

crtc_state->pixel_multiplier = 1;

drivers/gpu/drm/i915/display/intel_dpll.c

2201

crtc_state->dpll = *dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

2202

crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);

drivers/gpu/drm/i915/display/intel_dpll.c

2205

chv_compute_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2206

chv_enable_pll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2208

vlv_compute_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2209

vlv_enable_pll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2212

intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_dpll.c

2260

void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

2262

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

2263

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

2271

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_dpll.c

376

static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

378

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

379

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

424

void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

426

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

427

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

428

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

433

int refclk = i9xx_pll_refclk(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

513

crtc_state->port_clock = port_clock;

drivers/gpu/drm/i915/display/intel_dpll.c

516

void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

518

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

519

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

522

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

541

crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);

drivers/gpu/drm/i915/display/intel_dpll.c

544

void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.c

546

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

547

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

550

const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;

drivers/gpu/drm/i915/display/intel_dpll.c

575

crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);

drivers/gpu/drm/i915/display/intel_dpll.c

622

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

625

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

627

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {

drivers/gpu/drm/i915/display/intel_dpll.c

656

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

661

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

667

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

drivers/gpu/drm/i915/display/intel_dpll.c

714

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

719

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

725

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

drivers/gpu/drm/i915/display/intel_dpll.c

770

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

775

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

784

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

drivers/gpu/drm/i915/display/intel_dpll.c

864

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

869

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

921

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

926

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

977

bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

983

return chv_find_best_dpll(limit, crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.c

984

crtc_state->port_clock, refclk,

drivers/gpu/drm/i915/display/intel_dpll.c

998

static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll.h

28

void vlv_compute_dpll(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

29

void chv_compute_dpll(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

35

void chv_enable_pll(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

37

void vlv_enable_pll(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

39

void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

40

void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

41

bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll.h

45

void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

46

void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.h

47

void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1061

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1063

struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1066

hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1073

crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1074

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1083

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1087

&crtc_state->dpll_hw_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1093

hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1095

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1096

int clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1111

hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1113

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1116

int clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1169

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1171

struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1173

if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1186

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1189

return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1222

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1225

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1227

else if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1228

return hsw_ddi_lcpll_compute_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1229

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1239

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1243

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1245

else if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1246

pll = hsw_ddi_lcpll_get_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1247

else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1254

pll, &crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1256

crtc_state->intel_dpll = pll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1827

static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1829

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1830

struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1834

ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1859

crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1860

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1866

skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1868

struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1876

switch (crtc_state->port_clock / 2) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1942

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1945

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1946

return skl_ddi_hdmi_pll_dividers(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1947

else if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1948

return skl_ddi_dp_set_dpll_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1957

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1961

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1963

&crtc_state->dpll_hw_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1967

&crtc_state->dpll_hw_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1975

pll, &crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1977

crtc_state->intel_dpll = pll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2280

bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2283

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2290

if (!bxt_find_best_dpll(crtc_state, clk_div))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2298

static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2301

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2306

if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2315

clk_div->dot != crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2318

static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2321

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2322

struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2323

int clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2406

bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2410

bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2412

return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2416

bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2418

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2422

bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2424

ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2428

crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2429

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2438

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2441

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2442

return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2443

else if (intel_crtc_has_dp_encoder(crtc_state))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2444

return bxt_ddi_dp_set_dpll_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2454

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2467

pll, &crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2469

crtc_state->intel_dpll = pll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2723

static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2726

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2731

int clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2745

static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2748

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

275

void intel_dpll_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

277

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

278

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

279

struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

280

unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2809

icl_calc_wrpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2812

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2814

u32 afe_clock = crtc_state->port_clock * 5;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3021

static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3024

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3027

int clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3035

bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

321

void intel_dpll_disable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

323

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

324

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

325

struct intel_dpll *pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

326

unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3306

void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3310

&crtc_state->icl_port_dplls[port_dpll_id];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3312

crtc_state->intel_dpll = port_dpll->pll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3313

crtc_state->dpll_hw_state = port_dpll->hw_state;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3320

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3334

icl_set_active_port_dpll(crtc_state, port_dpll_id);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3341

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3344

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3348

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3349

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3350

ret = icl_calc_wrpll(crtc_state, &pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3352

ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3360

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3362

crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3373

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3376

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3433

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3438

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3442

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3443

ret = icl_calc_tbt_pll(crtc_state, &pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3449

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3450

ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3457

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3459

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3461

crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3471

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3474

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3478

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3487

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3504

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3521

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3524

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4477

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4480

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4483

ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4488

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4490

crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4500

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4507

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4510

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4511

ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4518

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4520

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4522

crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4652

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4655

&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4658

ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4663

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4665

crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4675

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4682

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4685

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4686

ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4693

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4695

icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4697

crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4969

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4972

if (crtc_state->hw.active && crtc_state->intel_dpll == pll)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

632

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

648

&crtc_state->dpll_hw_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

658

pll, &crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

660

crtc_state->intel_dpll = pll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

425

void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

436

void intel_dpll_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

437

void intel_dpll_disable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.c

132

static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_drrs.c

134

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.c

135

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

141

crtc_state->joiner_pipes)

drivers/gpu/drm/i915/display/intel_drrs.c

153

void intel_drrs_activate(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_drrs.c

155

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_drrs.c

157

if (!crtc_state->has_drrs)

drivers/gpu/drm/i915/display/intel_drrs.c

160

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_drrs.c

163

if (intel_crtc_is_joiner_secondary(crtc_state))

drivers/gpu/drm/i915/display/intel_drrs.c

168

crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_drrs.c

169

crtc->drrs.m_n = crtc_state->dp_m_n;

drivers/gpu/drm/i915/display/intel_drrs.c

170

crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;

drivers/gpu/drm/i915/display/intel_drrs.c

171

crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.c

315

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_drrs.c

322

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_drrs.c

328

crtc_state->cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_drrs.c

331

str_yes_no(crtc_state->has_drrs));

drivers/gpu/drm/i915/display/intel_drrs.c

356

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_drrs.c

364

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_drrs.c

366

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_drrs.c

367

!crtc_state->has_drrs)

drivers/gpu/drm/i915/display/intel_drrs.c

370

commit = crtc_state->uapi.commit;

drivers/gpu/drm/i915/display/intel_drrs.c

380

intel_drrs_activate(crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.c

382

intel_drrs_deactivate(crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.h

23

void intel_drrs_activate(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_drrs.h

24

void intel_drrs_deactivate(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

173

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dsb.c

177

return intel_vrr_vmax_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

179

return intel_mode_vtotal(&crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_dsb.c

186

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dsb.c

190

return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) -

drivers/gpu/drm/i915/display/intel_dsb.c

191

intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency);

drivers/gpu/drm/i915/display/intel_dsb.c

197

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dsb.c

200

return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_dsb.c

206

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dsb.c

210

return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;

drivers/gpu/drm/i915/display/intel_dsb.c

744

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dsb.c

746

int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,

drivers/gpu/drm/i915/display/intel_dsb.c

759

if (crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_dsb.c

762

if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {

drivers/gpu/drm/i915/display/intel_dsb.c

763

int vblank_delay = crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_dsb.c

766

vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

774

vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

782

vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

787

vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

792

int vblank_delay = crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_dsb.c

794

end = intel_vrr_vmin_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

798

end = intel_vrr_vmax_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_dsb.c

802

int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_dsb.c

804

end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_dsb.c

888

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_dsb.c

891

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_dsb.c

907

intel_vrr_safe_window_start(crtc_state),

drivers/gpu/drm/i915/display/intel_dsb.c

908

intel_vrr_vmin_safe_window_end(crtc_state));

drivers/gpu/drm/i915/display/intel_dsb.c

915

wait_scanlines = crtc_state->set_context_latency + 1;

drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c

128

static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_fbc.c

1444

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_fbc.c

1457

fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_fbc.c

1510

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1521

if (intel_crtc_needs_modeset(crtc_state) ||

drivers/gpu/drm/i915/display/intel_fbc.c

1539

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_fbc.c

1558

crtc_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1564

static int _intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1566

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1570

return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);

drivers/gpu/drm/i915/display/intel_fbc.c

1584

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1632

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_fbc.c

1634

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {

drivers/gpu/drm/i915/display/intel_fbc.c

1639

if (crtc_state->double_wide) {

drivers/gpu/drm/i915/display/intel_fbc.c

1656

if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) {

drivers/gpu/drm/i915/display/intel_fbc.c

1664

crtc_state->has_psr && !crtc_state->has_panel_replay) {

drivers/gpu/drm/i915/display/intel_fbc.c

1725

if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) {

drivers/gpu/drm/i915/display/intel_fbc.c

1735

int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1737

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1738

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_fbc.c

1745

min_cdclk = _intel_fbc_min_cdclk(crtc_state);

drivers/gpu/drm/i915/display/intel_fbc.c

2104

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_fbc.c

2118

if (intel_crtc_needs_fastset(crtc_state) &&

drivers/gpu/drm/i915/display/intel_fbc.h

32

int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_fbdev.c

384

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

392

if (!crtc_state->uapi.active) {

drivers/gpu/drm/i915/display/intel_fbdev.c

423

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

429

if (!crtc_state->uapi.active) {

drivers/gpu/drm/i915/display/intel_fbdev.c

444

cur_size = crtc_state->uapi.adjusted_mode.crtc_hdisplay;

drivers/gpu/drm/i915/display/intel_fbdev.c

455

cur_size = crtc_state->uapi.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_fbdev.c

461

crtc_state->uapi.adjusted_mode.crtc_hdisplay,

drivers/gpu/drm/i915/display/intel_fbdev.c

462

crtc_state->uapi.adjusted_mode.crtc_vdisplay,

drivers/gpu/drm/i915/display/intel_fbdev.c

493

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

500

if (!crtc_state->uapi.active)

drivers/gpu/drm/i915/display/intel_fdi.c

1006

temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

drivers/gpu/drm/i915/display/intel_fdi.c

122

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

126

display->fdi.funcs->fdi_link_train(crtc, crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

177

static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

179

if (crtc_state->hw.enable && crtc_state->has_pch_encoder)

drivers/gpu/drm/i915/display/intel_fdi.c

180

return crtc_state->fdi_lanes;

drivers/gpu/drm/i915/display/intel_fdi.c

26

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

370

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_fdi.c

372

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_fdi.c

375

if (!crtc_state->has_pch_encoder ||

drivers/gpu/drm/i915/display/intel_fdi.c

376

!intel_crtc_needs_modeset(crtc_state) ||

drivers/gpu/drm/i915/display/intel_fdi.c

377

!crtc_state->hw.enable)

drivers/gpu/drm/i915/display/intel_fdi.c

380

ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);

drivers/gpu/drm/i915/display/intel_fdi.c

413

static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

415

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

416

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_fdi.c

422

if (crtc_state->fdi_lanes > 2)

drivers/gpu/drm/i915/display/intel_fdi.c

478

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

493

assert_transcoder_enabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_fdi.c

509

temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

drivers/gpu/drm/i915/display/intel_fdi.c

579

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

608

temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

drivers/gpu/drm/i915/display/intel_fdi.c

714

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

721

ivb_update_fdi_bc_bifurcation(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

764

temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

drivers/gpu/drm/i915/display/intel_fdi.c

849

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

851

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

855

intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_fdi.c

857

hsw_prepare_dp_ddi_buffers(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

875

FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

drivers/gpu/drm/i915/display/intel_fdi.c

885

drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);

drivers/gpu/drm/i915/display/intel_fdi.c

886

intel_ddi_enable_clock(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

904

((crtc_state->fdi_lanes - 1) << 1) |

drivers/gpu/drm/i915/display/intel_fdi.c

994

void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_fdi.c

996

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.c

997

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_fdi.h

30

void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.h

33

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_fdi.h

38

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

201

static int intel_flipq_exec_time_lines(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_flipq.c

203

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

205

return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,

drivers/gpu/drm/i915/display/intel_flipq.c

285

void intel_flipq_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_flipq.c

287

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

288

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_flipq.c

290

int scanline = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode) -

drivers/gpu/drm/i915/display/intel_flipq.c

291

intel_flipq_exec_time_lines(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

298

intel_flipq_exec_time_lines(crtc_state));

drivers/gpu/drm/i915/display/intel_flipq.c

314

void intel_flipq_disable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_flipq.c

316

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_flipq.c

317

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_flipq.h

23

void intel_flipq_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_hdcp.c

2511

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdcp.c

2527

_intel_hdcp_enable(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_hdcp.c

2561

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdcp.c

2620

_intel_hdcp_enable(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_hdcp.c

2691

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_hdcp.c

2704

crtc_state = drm_atomic_get_new_crtc_state(new_state->state,

drivers/gpu/drm/i915/display/intel_hdcp.c

2711

if (drm_atomic_crtc_needs_modeset(crtc_state) &&

drivers/gpu/drm/i915/display/intel_hdcp.c

2729

crtc_state->mode_changed = true;

drivers/gpu/drm/i915/display/intel_hdcp.h

39

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1000

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_hdmi.c

1005

reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1013

intel_de_write(display, reg, crtc_state->infoframes.gcp);

drivers/gpu/drm/i915/display/intel_hdmi.c

1019

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_hdmi.c

1022

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

1025

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_hdmi.c

1030

reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1038

crtc_state->infoframes.gcp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1042

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1047

if (display->platform.g4x || !crtc_state->has_infoframe)

drivers/gpu/drm/i915/display/intel_hdmi.c

1050

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_hdmi.c

1054

if (crtc_state->pipe_bpp > 24)

drivers/gpu/drm/i915/display/intel_hdmi.c

1055

crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;

drivers/gpu/drm/i915/display/intel_hdmi.c

1058

if (gcp_default_phase_possible(crtc_state->pipe_bpp,

drivers/gpu/drm/i915/display/intel_hdmi.c

1059

&crtc_state->hw.adjusted_mode))

drivers/gpu/drm/i915/display/intel_hdmi.c

1060

crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;

drivers/gpu/drm/i915/display/intel_hdmi.c

1065

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1069

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

1105

if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))

drivers/gpu/drm/i915/display/intel_hdmi.c

1111

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1113

&crtc_state->infoframes.avi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1114

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1116

&crtc_state->infoframes.spd);

drivers/gpu/drm/i915/display/intel_hdmi.c

1117

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1119

&crtc_state->infoframes.hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1124

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1128

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

1154

if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))

drivers/gpu/drm/i915/display/intel_hdmi.c

1160

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1162

&crtc_state->infoframes.avi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1163

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1165

&crtc_state->infoframes.spd);

drivers/gpu/drm/i915/display/intel_hdmi.c

1166

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1168

&crtc_state->infoframes.hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1173

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1177

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

1212

if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))

drivers/gpu/drm/i915/display/intel_hdmi.c

1218

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1220

&crtc_state->infoframes.avi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1221

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1223

&crtc_state->infoframes.spd);

drivers/gpu/drm/i915/display/intel_hdmi.c

1224

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1226

&crtc_state->infoframes.hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1230

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1235

crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1238

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_hdmi.c

1248

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1250

&crtc_state->infoframes.drm);

drivers/gpu/drm/i915/display/intel_hdmi.c

1255

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1260

crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1264

crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_hdmi.c

1277

if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))

drivers/gpu/drm/i915/display/intel_hdmi.c

1283

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1285

&crtc_state->infoframes.avi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1286

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1288

&crtc_state->infoframes.spd);

drivers/gpu/drm/i915/display/intel_hdmi.c

1289

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1291

&crtc_state->infoframes.hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

1292

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

1294

&crtc_state->infoframes.drm);

drivers/gpu/drm/i915/display/intel_hdmi.c

1856

static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_hdmi.c

1858

return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;

drivers/gpu/drm/i915/display/intel_hdmi.c

2124

bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2127

struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);

drivers/gpu/drm/i915/display/intel_hdmi.c

2133

if (connector_state->base.crtc != crtc_state->uapi.crtc)

drivers/gpu/drm/i915/display/intel_hdmi.c

2137

crtc_state->sink_format))

drivers/gpu/drm/i915/display/intel_hdmi.c

2144

static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)

drivers/gpu/drm/i915/display/intel_hdmi.c

2146

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

2148

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_hdmi.c

2154

if (intel_hdmi_is_ycbcr420(crtc_state) &&

drivers/gpu/drm/i915/display/intel_hdmi.c

2160

return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);

drivers/gpu/drm/i915/display/intel_hdmi.c

2164

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2174

bpc = max(crtc_state->pipe_bpp / 3, 8);

drivers/gpu/drm/i915/display/intel_hdmi.c

2186

crtc_state->sink_format);

drivers/gpu/drm/i915/display/intel_hdmi.c

2188

if (hdmi_bpc_possible(crtc_state, bpc) &&

drivers/gpu/drm/i915/display/intel_hdmi.c

2191

crtc_state->has_hdmi_sink) == MODE_OK)

drivers/gpu/drm/i915/display/intel_hdmi.c

2199

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2204

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_hdmi.c

2210

bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,

drivers/gpu/drm/i915/display/intel_hdmi.c

2215

crtc_state->port_clock =

drivers/gpu/drm/i915/display/intel_hdmi.c

2216

intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);

drivers/gpu/drm/i915/display/intel_hdmi.c

2223

crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);

drivers/gpu/drm/i915/display/intel_hdmi.c

2227

bpc, crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_hdmi.c

2232

bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2238

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_hdmi.c

2247

if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

drivers/gpu/drm/i915/display/intel_hdmi.c

2252

return crtc_state->has_hdmi_sink &&

drivers/gpu/drm/i915/display/intel_hdmi.c

226

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2261

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2268

if (!crtc_state->has_hdmi_sink)

drivers/gpu/drm/i915/display/intel_hdmi.c

2278

intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_hdmi.c

2280

return crtc_state->sink_format;

drivers/gpu/drm/i915/display/intel_hdmi.c

2284

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2289

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_hdmi.c

2292

crtc_state->has_hdmi_sink, sink_format) != MODE_OK)

drivers/gpu/drm/i915/display/intel_hdmi.c

2295

crtc_state->sink_format = sink_format;

drivers/gpu/drm/i915/display/intel_hdmi.c

2296

crtc_state->output_format = intel_hdmi_output_format(crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

2298

return intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);

drivers/gpu/drm/i915/display/intel_hdmi.c

2302

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2308

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_hdmi.c

2313

ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,

drivers/gpu/drm/i915/display/intel_hdmi.c

2321

ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,

drivers/gpu/drm/i915/display/intel_hdmi.c

2326

ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,

drivers/gpu/drm/i915/display/intel_hdmi.c

2331

ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,

drivers/gpu/drm/i915/display/intel_hdmi.c

2339

static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_hdmi.c

2341

return crtc_state->uapi.encoder_mask &&

drivers/gpu/drm/i915/display/intel_hdmi.c

2342

!is_power_of_2(crtc_state->uapi.encoder_mask);

drivers/gpu/drm/i915/display/intel_hdmi.c

2365

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

2371

!intel_hdmi_is_cloned(crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

262

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

294

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

300

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

3206

intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

3228

int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_hdmi.c

3239

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||

drivers/gpu/drm/i915/display/intel_hdmi.c

3240

crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)

drivers/gpu/drm/i915/display/intel_hdmi.c

3295

slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);

drivers/gpu/drm/i915/display/intel_hdmi.c

333

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

338

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

369

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

375

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

411

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

416

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

443

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

449

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

483

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

488

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.c

519

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

525

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_hdmi.c

551

if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&

drivers/gpu/drm/i915/display/intel_hdmi.c

552

!crtc_state->has_panel_replay && type == DP_SDP_VSC))

drivers/gpu/drm/i915/display/intel_hdmi.c

563

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

567

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_hdmi.c

621

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_hdmi.c

628

val = dig_port->infoframes_enabled(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

664

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

672

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_hdmi.c

689

dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);

drivers/gpu/drm/i915/display/intel_hdmi.c

693

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

701

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_hdmi.c

705

dig_port->read_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

727

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

730

struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;

drivers/gpu/drm/i915/display/intel_hdmi.c

732

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_hdmi.c

736

if (!crtc_state->has_infoframe)

drivers/gpu/drm/i915/display/intel_hdmi.c

739

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_hdmi.c

747

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

drivers/gpu/drm/i915/display/intel_hdmi.c

749

else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)

drivers/gpu/drm/i915/display/intel_hdmi.c

757

drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_hdmi.c

758

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);

drivers/gpu/drm/i915/display/intel_hdmi.c

760

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {

drivers/gpu/drm/i915/display/intel_hdmi.c

763

crtc_state->limited_color_range ?

drivers/gpu/drm/i915/display/intel_hdmi.c

784

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

787

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.c

788

struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;

drivers/gpu/drm/i915/display/intel_hdmi.c

791

if (!crtc_state->has_infoframe)

drivers/gpu/drm/i915/display/intel_hdmi.c

794

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_hdmi.c

816

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

820

&crtc_state->infoframes.hdmi.vendor.hdmi;

drivers/gpu/drm/i915/display/intel_hdmi.c

825

if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)

drivers/gpu/drm/i915/display/intel_hdmi.c

828

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_hdmi.c

833

&crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_hdmi.c

846

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

850

struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;

drivers/gpu/drm/i915/display/intel_hdmi.c

856

if (!crtc_state->has_infoframe)

drivers/gpu/drm/i915/display/intel_hdmi.c

862

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_hdmi.c

881

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

938

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

940

&crtc_state->infoframes.avi);

drivers/gpu/drm/i915/display/intel_hdmi.c

941

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

943

&crtc_state->infoframes.spd);

drivers/gpu/drm/i915/display/intel_hdmi.c

944

intel_write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

946

&crtc_state->infoframes.hdmi);

drivers/gpu/drm/i915/display/intel_hdmi.c

993

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.c

997

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_hdmi.h

27

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

40

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.h

43

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_hdmi.h

45

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

48

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

51

bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

53

bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

59

int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

66

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_hdmi.h

70

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_initial_plane.c

212

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_initial_plane.c

217

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_initial_plane.c

58

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_initial_plane.c

61

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_link_bw.c

112

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_link_bw.c

118

crtc_state = intel_atomic_get_crtc_state(&state->base,

drivers/gpu/drm/i915/display/intel_link_bw.c

120

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_link_bw.c

121

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_link_bw.c

123

if (crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_link_bw.c

124

link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;

drivers/gpu/drm/i915/display/intel_link_bw.c

132

link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp);

drivers/gpu/drm/i915/display/intel_link_bw.c

181

bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_link_bw.c

183

int pipe_bpp = min(crtc_state->pipe_bpp,

drivers/gpu/drm/i915/display/intel_link_bw.c

184

fxp_q4_to_int(crtc_state->max_link_bpp_x16));

drivers/gpu/drm/i915/display/intel_link_bw.c

191

crtc_state->pipe_bpp = pipe_bpp;

drivers/gpu/drm/i915/display/intel_link_bw.c

63

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_link_bw.c

67

if (state->base.duplicated && crtc_state) {

drivers/gpu/drm/i915/display/intel_link_bw.c

68

limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;

drivers/gpu/drm/i915/display/intel_link_bw.c

69

if (intel_dsc_enabled_on_link(crtc_state))

drivers/gpu/drm/i915/display/intel_link_bw.h

30

bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_load_detect.c

144

crtc_state = intel_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_load_detect.c

145

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/i915/display/intel_load_detect.c

146

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_load_detect.c

150

crtc_state->uapi.active = true;

drivers/gpu/drm/i915/display/intel_load_detect.c

152

ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,

drivers/gpu/drm/i915/display/intel_load_detect.c

60

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_lspcon.c

494

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lspcon.c

515

hsw_write_infoframe(encoder, crtc_state, type, frame, len);

drivers/gpu/drm/i915/display/intel_lspcon.c

528

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lspcon.c

534

hsw_read_infoframe(encoder, crtc_state, type,

drivers/gpu/drm/i915/display/intel_lspcon.c

540

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lspcon.c

547

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_lspcon.c

576

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)

drivers/gpu/drm/i915/display/intel_lspcon.c

585

drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&

drivers/gpu/drm/i915/display/intel_lspcon.c

586

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);

drivers/gpu/drm/i915/display/intel_lspcon.c

588

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {

drivers/gpu/drm/i915/display/intel_lspcon.c

592

crtc_state->limited_color_range ?

drivers/gpu/drm/i915/display/intel_lspcon.c

608

dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI,

drivers/gpu/drm/i915/display/intel_lspcon.h

26

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lspcon.h

30

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lspcon.h

35

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1315

intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1318

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1319

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_lt_phy.c

1323

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1332

intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1337

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1744

intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1748

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1754

tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1762

if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1764

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1765

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_lt_phy.c

1769

intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1770

hw_state->ltpll.lane_count = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1775

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1776

hw_state->ltpll.lane_count = crtc_state->lane_count;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1778

crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2118

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_lt_phy.c

2134

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2140

for (ln = 0; ln < crtc_state->lane_count; ln++) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

2141

int level = intel_ddi_level(encoder, crtc_state, ln);

drivers/gpu/drm/i915/display/intel_lt_phy.h

26

intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lt_phy.h

33

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_lvds.c

123

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_lvds.c

129

crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);

drivers/gpu/drm/i915/display/intel_lvds.c

141

crtc_state->hw.adjusted_mode.flags |= flags;

drivers/gpu/drm/i915/display/intel_lvds.c

144

crtc_state->gmch_pfit.lvds_border_bits =

drivers/gpu/drm/i915/display/intel_lvds.c

151

crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;

drivers/gpu/drm/i915/display/intel_lvds.c

154

crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_lvds.c

240

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lvds.c

245

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_lvds.c

246

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_lvds.c

252

assert_dpll_disabled(display, crtc_state->intel_dpll);

drivers/gpu/drm/i915/display/intel_lvds.c

272

temp |= crtc_state->gmch_pfit.lvds_border_bits;

drivers/gpu/drm/i915/display/intel_lvds.c

302

if (crtc_state->dither && crtc_state->pipe_bpp == 18)

drivers/gpu/drm/i915/display/intel_lvds.c

321

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lvds.c

336

intel_backlight_enable(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_lvds.c

417

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_lvds.c

423

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_lvds.c

424

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_lvds.c

435

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/intel_lvds.c

436

if (!intel_link_bw_compute_pipe_bpp(crtc_state))

drivers/gpu/drm/i915/display/intel_lvds.c

446

if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {

drivers/gpu/drm/i915/display/intel_lvds.c

449

crtc_state->pipe_bpp, lvds_bpp);

drivers/gpu/drm/i915/display/intel_lvds.c

450

crtc_state->pipe_bpp = lvds_bpp;

drivers/gpu/drm/i915/display/intel_lvds.c

453

crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_lvds.c

454

crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;

drivers/gpu/drm/i915/display/intel_lvds.c

469

ret = intel_pfit_compute_config(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

100

&crtc_state->intel_dpll->state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

1003

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

1007

intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

162

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

166

__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

167

intel_crtc_free_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

168

intel_crtc_state_reset(crtc_state, crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

220

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

226

if (!is_trans_port_sync_mode(crtc_state)) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

233

if (is_trans_port_sync_master(crtc_state))

drivers/gpu/drm/i915/display/intel_modeset_setup.c

234

master_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

236

master_transcoder = crtc_state->master_transcoder;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

313

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

316

conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

322

static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

324

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

326

if (intel_crtc_is_joiner_secondary(crtc_state))

drivers/gpu/drm/i915/display/intel_modeset_setup.c

329

crtc_state->uapi.enable = crtc_state->hw.enable;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

330

crtc_state->uapi.active = crtc_state->hw.active;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

331

drm_WARN_ON(crtc_state->uapi.crtc->dev,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

332

drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

334

crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

335

crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

336

crtc_state->uapi.sharpness_strength = crtc_state->hw.sharpness_strength;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

337

crtc_state->uapi.background_color =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

338

intel_color_background_color_hw_to_drm(crtc_state->hw.background_color);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

342

drm_property_replace_blob(&crtc_state->hw.degamma_lut,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

343

crtc_state->pre_csc_lut);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

344

drm_property_replace_blob(&crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

345

crtc_state->post_csc_lut);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

355

drm_WARN_ON(display->drm, crtc_state->post_csc_lut &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

356

crtc_state->pre_csc_lut);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

358

drm_property_replace_blob(&crtc_state->hw.degamma_lut,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

360

drm_property_replace_blob(&crtc_state->hw.gamma_lut,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

361

crtc_state->post_csc_lut ?:

drivers/gpu/drm/i915/display/intel_modeset_setup.c

362

crtc_state->pre_csc_lut);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

365

drm_property_replace_blob(&crtc_state->uapi.degamma_lut,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

366

crtc_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

367

drm_property_replace_blob(&crtc_state->uapi.gamma_lut,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

368

crtc_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

369

drm_property_replace_blob(&crtc_state->uapi.ctm,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

370

crtc_state->hw.ctm);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

44

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

447

static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

449

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

450

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

466

!crtc_state->hw.active &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

474

struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

477

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

491

intel_color_commit_noarm(NULL, crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

492

intel_color_commit_arm(NULL, crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

495

if (!crtc_state->hw.active ||

drivers/gpu/drm/i915/display/intel_modeset_setup.c

496

intel_crtc_is_joiner_secondary(crtc_state))

drivers/gpu/drm/i915/display/intel_modeset_setup.c

51

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

551

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

554

intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");

drivers/gpu/drm/i915/display/intel_modeset_setup.c

558

static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

560

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

573

crtc_state->hw.active &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

574

crtc_state->intel_dpll &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

575

crtc_state->port_clock == 0;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

583

struct intel_crtc_state *crtc_state = crtc ?

drivers/gpu/drm/i915/display/intel_modeset_setup.c

593

bool has_active_crtc = crtc_state &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

594

crtc_state->hw.active;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

596

if (crtc_state && has_bogus_dpll_config(crtc_state)) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

619

if (crtc_state) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

633

encoder->disable(NULL, encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

636

encoder->post_disable(NULL, encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

669

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

676

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

678

intel_set_plane_visible(crtc_state, plane_state, visible);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

687

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

690

intel_plane_fixup_bitmasks(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

705

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

708

__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

709

intel_crtc_free_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

710

intel_crtc_state_reset(crtc_state, crtc);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

712

intel_crtc_get_pipe_config(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

714

crtc_state->hw.enable = crtc_state->hw.active;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

716

crtc->base.enabled = crtc_state->hw.enable;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

717

crtc->active = crtc_state->hw.active;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

722

str_enabled_disabled(crtc_state->hw.active));

drivers/gpu/drm/i915/display/intel_modeset_setup.c

728

struct intel_crtc_state *crtc_state = NULL;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

734

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

737

intel_encoder_get_config(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

740

if (crtc_state->joiner_pipes) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

744

WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));

drivers/gpu/drm/i915/display/intel_modeset_setup.c

747

intel_crtc_joiner_secondary_pipes(crtc_state)) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

76

intel_crtc_joiner_secondary_pipes(crtc_state)) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

767

encoder->sync_state(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

780

struct intel_crtc_state *crtc_state = NULL;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

791

crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

793

if (crtc_state && crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

799

crtc_state->uapi.connector_mask |=

drivers/gpu/drm/i915/display/intel_modeset_setup.c

801

crtc_state->uapi.encoder_mask |=

drivers/gpu/drm/i915/display/intel_modeset_setup.c

810

connector->sync_state(connector, crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

820

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

833

crtc_state->inherited = true;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

835

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

836

intel_crtc_update_active_timings(crtc_state,

drivers/gpu/drm/i915/display/intel_modeset_setup.c

837

crtc_state->vrr.enable);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

839

intel_crtc_copy_hw_to_uapi_state(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

851

crtc_state->data_rate[plane->id] =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

852

4 * crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

858

if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

859

crtc_state->plane_min_cdclk[plane->id] =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

860

DIV_ROUND_UP(crtc_state->pixel_rate, 2);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

862

crtc_state->plane_min_cdclk[plane->id] =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

863

crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

868

crtc_state->plane_min_cdclk[plane->id]);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

871

crtc_state->min_cdclk = intel_crtc_min_cdclk(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

874

crtc->base.base.id, crtc->base.name, crtc_state->min_cdclk);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

877

crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

897

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_modeset_setup.c

909

crtc_state = to_intel_crtc_state(encoder->base.crtc->state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

910

encoder->get_power_domains(encoder, crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

967

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

97

if (crtc_state->intel_dpll)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

970

intel_sanitize_fifo_underrun_reporting(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

974

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

975

intel_dmc_enable_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

976

intel_crtc_vblank_on(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

99

crtc_state->intel_dpll,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

28

static void intel_connector_verify_state(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

40

INTEL_DISPLAY_STATE_WARN(display, !crtc_state,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

43

if (!crtc_state)

drivers/gpu/drm/i915/display/intel_modeset_verify.c

46

INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

59

INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

61

INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder,

drivers/gpu/drm/i915/display/intel_modeset_verify.c

77

const struct intel_crtc_state *crtc_state = NULL;

drivers/gpu/drm/i915/display/intel_modeset_verify.c

83

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

85

intel_connector_verify_state(crtc_state, new_conn_state);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

92

static void intel_pipe_config_sanity_check(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_modeset_verify.c

94

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

96

if (crtc_state->has_pch_encoder) {

drivers/gpu/drm/i915/display/intel_modeset_verify.c

97

int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),

drivers/gpu/drm/i915/display/intel_modeset_verify.c

98

&crtc_state->fdi_m_n);

drivers/gpu/drm/i915/display/intel_modeset_verify.c

99

int dotclock = crtc_state->hw.adjusted_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_overlay.c

489

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_overlay.c

493

if (crtc_state->gamma_enable &&

drivers/gpu/drm/i915/display/intel_overlay.c

494

crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

drivers/gpu/drm/i915/display/intel_overlay.c

496

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_overlay.c

644

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_overlay.c

653

if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src))

drivers/gpu/drm/i915/display/intel_panel.c

498

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_panel.c

500

crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_panel.c

502

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_panel.c

505

intel_panel_prepare(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_panel.c

587

void intel_panel_prepare(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_panel.h

57

void intel_panel_prepare(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pch_display.c

222

static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pch_display.c

225

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

226

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_pch_display.c

245

static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_display.c

247

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

248

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

254

assert_dpll_enabled(display, crtc_state->intel_dpll);

drivers/gpu/drm/i915/display/intel_pch_display.c

270

val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

drivers/gpu/drm/i915/display/intel_pch_display.c

281

val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

drivers/gpu/drm/i915/display/intel_pch_display.c

289

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_pch_display.c

298

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))

drivers/gpu/drm/i915/display/intel_pch_display.c

341

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_pch_display.c

349

ilk_fdi_pll_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

364

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_pch_display.c

372

intel_fdi_link_train(crtc, crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

384

if (crtc_state->intel_dpll ==

drivers/gpu/drm/i915/display/intel_pch_display.c

401

intel_dpll_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

405

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

406

intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);

drivers/gpu/drm/i915/display/intel_pch_display.c

407

intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);

drivers/gpu/drm/i915/display/intel_pch_display.c

409

ilk_pch_transcoder_set_timings(crtc_state, pipe);

drivers/gpu/drm/i915/display/intel_pch_display.c

415

intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_pch_display.c

417

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pch_display.c

436

port = intel_get_crtc_new_encoder(state, crtc_state)->port;

drivers/gpu/drm/i915/display/intel_pch_display.c

443

ilk_enable_pch_transcoder(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

478

static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_display.c

480

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

483

i9xx_crtc_clock_get(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

490

crtc_state->hw.adjusted_mode.crtc_clock =

drivers/gpu/drm/i915/display/intel_pch_display.c

491

intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),

drivers/gpu/drm/i915/display/intel_pch_display.c

492

&crtc_state->fdi_m_n);

drivers/gpu/drm/i915/display/intel_pch_display.c

495

void ilk_pch_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_display.c

497

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

498

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

508

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/intel_pch_display.c

511

crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>

drivers/gpu/drm/i915/display/intel_pch_display.c

514

intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,

drivers/gpu/drm/i915/display/intel_pch_display.c

515

&crtc_state->fdi_m_n);

drivers/gpu/drm/i915/display/intel_pch_display.c

531

crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);

drivers/gpu/drm/i915/display/intel_pch_display.c

532

pll = crtc_state->intel_dpll;

drivers/gpu/drm/i915/display/intel_pch_display.c

535

&crtc_state->dpll_hw_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

538

tmp = crtc_state->dpll_hw_state.i9xx.dpll;

drivers/gpu/drm/i915/display/intel_pch_display.c

539

crtc_state->pixel_multiplier =

drivers/gpu/drm/i915/display/intel_pch_display.c

543

ilk_pch_clock_get(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

546

static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_display.c

548

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

549

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_pch_display.c

561

val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

drivers/gpu/drm/i915/display/intel_pch_display.c

595

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_pch_display.c

600

lpt_program_iclkip(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

603

ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);

drivers/gpu/drm/i915/display/intel_pch_display.c

605

lpt_enable_pch_transcoder(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

618

void lpt_pch_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_display.c

620

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.c

621

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

627

crtc_state->has_pch_encoder = true;

drivers/gpu/drm/i915/display/intel_pch_display.c

630

crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>

drivers/gpu/drm/i915/display/intel_pch_display.c

633

intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,

drivers/gpu/drm/i915/display/intel_pch_display.c

634

&crtc_state->fdi_m_n);

drivers/gpu/drm/i915/display/intel_pch_display.c

636

crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);

drivers/gpu/drm/i915/display/intel_pch_display.h

31

void ilk_pch_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.h

37

void lpt_pch_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pch_display.h

71

static inline void ilk_pch_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_display.h

82

static inline void lpt_pch_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

173

int lpt_iclkip(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

177

lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

183

void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

185

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

186

int clock = crtc_state->hw.adjusted_mode.crtc_clock;

drivers/gpu/drm/i915/display/intel_pch_refclk.h

15

void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

18

int lpt_iclkip(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pch_refclk.h

23

static inline void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pch_refclk.h

33

static inline int lpt_iclkip(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

108

static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

110

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

111

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

112

const struct drm_rect *dst = &crtc_state->pch_pfit.dst;

drivers/gpu/drm/i915/display/intel_pfit.c

113

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

114

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

143

static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

145

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

146

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

148

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

161

static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

163

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

164

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

173

if (crtc_state->uapi.encoder_mask &&

drivers/gpu/drm/i915/display/intel_pfit.c

174

!is_power_of_2(crtc_state->uapi.encoder_mask)) {

drivers/gpu/drm/i915/display/intel_pfit.c

185

static int pch_panel_fitting(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pfit.c

188

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

189

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

19

static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

191

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

192

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

193

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

199

crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&

drivers/gpu/drm/i915/display/intel_pfit.c

200

crtc_state->hw.sharpness_strength == 0)

drivers/gpu/drm/i915/display/intel_pfit.c

21

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

22

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

24

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

25

const struct drm_rect *dst = &crtc_state->pch_pfit.dst;

drivers/gpu/drm/i915/display/intel_pfit.c

264

if (crtc_state->hw.sharpness_strength &&

drivers/gpu/drm/i915/display/intel_pfit.c

266

crtc_state->hw.scaling_filter != DRM_SCALING_FILTER_DEFAULT ||

drivers/gpu/drm/i915/display/intel_pfit.c

267

crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)) {

drivers/gpu/drm/i915/display/intel_pfit.c

274

drm_rect_init(&crtc_state->pch_pfit.dst,

drivers/gpu/drm/i915/display/intel_pfit.c

276

crtc_state->pch_pfit.enabled = true;

drivers/gpu/drm/i915/display/intel_pfit.c

285

ret = intel_pch_pfit_check_dst_window(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

289

ret = intel_pch_pfit_check_src_size(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

293

ret = intel_pch_pfit_check_scaling(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

297

ret = intel_pch_pfit_check_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

301

ret = intel_pch_pfit_check_cloning(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

364

static void i965_scale_aspect(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pfit.c

368

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

369

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

370

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

385

static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pfit.c

389

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

390

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

391

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

441

static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

443

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

444

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

446

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

473

static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pfit.c

476

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

477

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

479

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_pfit.c

480

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

481

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

520

i965_scale_aspect(crtc_state, &pfit_control);

drivers/gpu/drm/i915/display/intel_pfit.c

522

i9xx_scale_aspect(crtc_state, &pfit_control,

drivers/gpu/drm/i915/display/intel_pfit.c

559

if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18)

drivers/gpu/drm/i915/display/intel_pfit.c

562

crtc_state->gmch_pfit.control = pfit_control;

drivers/gpu/drm/i915/display/intel_pfit.c

563

crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;

drivers/gpu/drm/i915/display/intel_pfit.c

564

crtc_state->gmch_pfit.lvds_border_bits = border;

drivers/gpu/drm/i915/display/intel_pfit.c

569

return intel_gmch_pfit_check_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

582

int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pfit.c

585

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

588

return gmch_panel_fitting(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_pfit.c

590

return pch_panel_fitting(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_pfit.c

593

void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

595

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

596

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

597

const struct drm_rect *dst = &crtc_state->pch_pfit.dst;

drivers/gpu/drm/i915/display/intel_pfit.c

604

if (!crtc_state->pch_pfit.enabled)

drivers/gpu/drm/i915/display/intel_pfit.c

641

void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

643

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

644

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

657

crtc_state->pch_pfit.enabled = true;

drivers/gpu/drm/i915/display/intel_pfit.c

662

drm_rect_init(&crtc_state->pch_pfit.dst,

drivers/gpu/drm/i915/display/intel_pfit.c

676

void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

678

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

679

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

681

if (!crtc_state->gmch_pfit.control)

drivers/gpu/drm/i915/display/intel_pfit.c

690

assert_transcoder_disabled(display, crtc_state->cpu_transcoder);

drivers/gpu/drm/i915/display/intel_pfit.c

693

crtc_state->gmch_pfit.pgm_ratios);

drivers/gpu/drm/i915/display/intel_pfit.c

695

crtc_state->gmch_pfit.control);

drivers/gpu/drm/i915/display/intel_pfit.c

70

static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

72

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

727

void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pfit.c

729

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.c

73

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

730

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pfit.c

74

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

75

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/intel_pfit.c

750

crtc_state->gmch_pfit.control = tmp;

drivers/gpu/drm/i915/display/intel_pfit.c

751

crtc_state->gmch_pfit.pgm_ratios =

drivers/gpu/drm/i915/display/intel_pfit.h

16

int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pfit.h

18

void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.h

20

void ilk_pfit_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.h

21

void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pfit.h

23

void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_plane.c

1086

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

1095

const struct drm_rect *clip = &crtc_state->pipe_src;

drivers/gpu/drm/i915/display/intel_plane.c

1536

const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/intel_plane.c

1541

if (crtc_state->enable_psr2_sel_fetch) {

drivers/gpu/drm/i915/display/intel_plane.c

1543

intel_psr2_panic_force_full_update(crtc_state);

drivers/gpu/drm/i915/display/intel_plane.c

1666

static void link_nv12_planes(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

1683

crtc_state->enabled_planes |= BIT(y_plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

1684

crtc_state->active_planes |= BIT(y_plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

1685

crtc_state->update_planes |= BIT(y_plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

1687

crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id];

drivers/gpu/drm/i915/display/intel_plane.c

1688

crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id];

drivers/gpu/drm/i915/display/intel_plane.c

1707

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_plane.c

1716

if (!crtc_state->nv12_planes)

drivers/gpu/drm/i915/display/intel_plane.c

1726

if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)

drivers/gpu/drm/i915/display/intel_plane.c

1733

if (crtc_state->active_planes & BIT(y_plane->id))

drivers/gpu/drm/i915/display/intel_plane.c

1747

hweight8(crtc_state->nv12_planes));

drivers/gpu/drm/i915/display/intel_plane.c

1751

link_nv12_planes(crtc_state, plane_state, y_plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1859

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_plane.c

1862

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/intel_plane.c

1865

ret = intel_joiner_add_affected_planes(state, intel_crtc_joined_pipe_mask(crtc_state));

drivers/gpu/drm/i915/display/intel_plane.c

267

unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

284

crtc_state->pixel_rate);

drivers/gpu/drm/i915/display/intel_plane.c

287

unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

296

return intel_plane_pixel_rate(crtc_state, plane_state) *

drivers/gpu/drm/i915/display/intel_plane.c

301

intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

331

skl_plane_relative_data_rate(crtc_state, plane, width, height,

drivers/gpu/drm/i915/display/intel_plane.c

489

static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

507

crtc_state->enabled_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

508

crtc_state->active_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

509

crtc_state->update_planes |= BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

510

crtc_state->data_rate[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

511

crtc_state->rel_data_rate[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

514

void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

519

unlink_nv12_plane(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

521

crtc_state->active_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

522

crtc_state->scaled_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

523

crtc_state->nv12_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

524

crtc_state->c8_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

525

crtc_state->async_flip_planes &= ~BIT(plane->id);

drivers/gpu/drm/i915/display/intel_plane.c

526

crtc_state->data_rate[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

527

crtc_state->data_rate_y[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

528

crtc_state->rel_data_rate[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

529

crtc_state->rel_data_rate_y[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

530

crtc_state->plane_min_cdclk[plane->id] = 0;

drivers/gpu/drm/i915/display/intel_plane.c

892

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_plane.c

908

if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],

drivers/gpu/drm/i915/display/intel_plane.c

910

skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],

drivers/gpu/drm/i915/display/intel_plane.c

915

ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/intel_plane.c

916

ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/intel_plane.c

929

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

932

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

940

plane->update_noarm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

945

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

949

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

952

plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);

drivers/gpu/drm/i915/display/intel_plane.c

957

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.c

960

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

962

if (crtc_state->do_async_flip && plane->async_flip) {

drivers/gpu/drm/i915/display/intel_plane.c

963

intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);

drivers/gpu/drm/i915/display/intel_plane.c

968

plane->update_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

973

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_plane.c

975

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

978

plane->disable_arm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/intel_plane.h

32

unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

35

unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

45

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

50

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

54

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

58

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_plane.h

72

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

76

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_plane.h

80

void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_pmdemand.c

213

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_pmdemand.c

219

crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_pmdemand.c

221

crtc_state = intel_atomic_get_old_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_pmdemand.c

223

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_pps.c

1263

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pps.c

1267

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_pps.c

1309

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_pps.h

54

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_pps.h

56

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

1203

static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

1205

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_psr.c

1209

drm_mode_vrefresh(&crtc_state->hw.adjusted_mode));

drivers/gpu/drm/i915/display/intel_psr.c

1266

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

1270

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_psr.c

1281

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

1284

const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_psr.c

1299

if (crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/intel_psr.c

1305

if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

1317

intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;

drivers/gpu/drm/i915/display/intel_psr.c

1322

crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;

drivers/gpu/drm/i915/display/intel_psr.c

1326

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

1337

return crtc_state->enable_psr2_sel_fetch = true;

drivers/gpu/drm/i915/display/intel_psr.c

1340

static bool psr2_granularity_check(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1345

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_psr.c

1346

const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;

drivers/gpu/drm/i915/display/intel_psr.c

1347

const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_psr.c

1349

u16 sink_y_granularity = crtc_state->has_panel_replay ?

drivers/gpu/drm/i915/display/intel_psr.c

1354

if (crtc_state->has_panel_replay)

drivers/gpu/drm/i915/display/intel_psr.c

1369

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/intel_psr.c

1387

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_psr.c

1391

crtc_state->su_y_granularity = y_granularity;

drivers/gpu/drm/i915/display/intel_psr.c

1395

static bool apply_scanline_indication_wa(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1407

crtc_state->req_psr2_sdp_prior_scanline = false;

drivers/gpu/drm/i915/display/intel_psr.c

1412

crtc_state->req_psr2_sdp_prior_scanline = false;

drivers/gpu/drm/i915/display/intel_psr.c

1420

static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1425

const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;

drivers/gpu/drm/i915/display/intel_psr.c

1432

req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000);

drivers/gpu/drm/i915/display/intel_psr.c

1441

crtc_state->req_psr2_sdp_prior_scanline = true;

drivers/gpu/drm/i915/display/intel_psr.c

1443

return apply_scanline_indication_wa(crtc_state, connector);

drivers/gpu/drm/i915/display/intel_psr.c

1482

int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1486

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

1488

if (!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_psr.c

1492

if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))

drivers/gpu/drm/i915/display/intel_psr.c

1518

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_psr.c

1528

static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1532

if (crtc_state->req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1543

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1549

int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -

drivers/gpu/drm/i915/display/intel_psr.c

1550

crtc_state->hw.adjusted_mode.crtc_vblank_start;

drivers/gpu/drm/i915/display/intel_psr.c

1552

int scl = _intel_psr_min_set_context_latency(crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1558

wake_lines = crtc_state->alpm_state.aux_less_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

1561

psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,

drivers/gpu/drm/i915/display/intel_psr.c

1562

crtc_state->alpm_state.fast_wake_lines) :

drivers/gpu/drm/i915/display/intel_psr.c

1563

crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

1574

return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1578

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1585

if (!intel_alpm_compute_params(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

1591

if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,

drivers/gpu/drm/i915/display/intel_psr.c

1602

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1607

int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;

drivers/gpu/drm/i915/display/intel_psr.c

1608

int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_psr.c

1633

if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {

drivers/gpu/drm/i915/display/intel_psr.c

1636

transcoder_name(crtc_state->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

1645

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_psr.c

1655

max_bpp = crtc_state->pipe_bpp;

drivers/gpu/drm/i915/display/intel_psr.c

1670

if (crtc_state->pipe_bpp > max_bpp) {

drivers/gpu/drm/i915/display/intel_psr.c

1673

crtc_state->pipe_bpp, max_bpp);

drivers/gpu/drm/i915/display/intel_psr.c

1678

if (crtc_state->vrr.enable &&

drivers/gpu/drm/i915/display/intel_psr.c

1685

if (!alpm_config_valid(intel_dp, crtc_state, false, false, true))

drivers/gpu/drm/i915/display/intel_psr.c

1688

if (!crtc_state->enable_psr2_sel_fetch &&

drivers/gpu/drm/i915/display/intel_psr.c

1697

tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

1702

static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1710

!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_psr.c

1723

if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1727

if (!_compute_psr2_sdp_prior_scanline_indication(crtc_state, connector)) {

drivers/gpu/drm/i915/display/intel_psr.c

1733

if (crtc_state->has_panel_replay) {

drivers/gpu/drm/i915/display/intel_psr.c

1740

if (intel_dsc_enabled_on_link(crtc_state) &&

drivers/gpu/drm/i915/display/intel_psr.c

1749

if (crtc_state->crc_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1755

if (!psr2_granularity_check(crtc_state, connector)) {

drivers/gpu/drm/i915/display/intel_psr.c

1761

crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector,

drivers/gpu/drm/i915/display/intel_psr.c

1762

crtc_state->has_panel_replay);

drivers/gpu/drm/i915/display/intel_psr.c

1767

crtc_state->enable_psr2_sel_fetch = false;

drivers/gpu/drm/i915/display/intel_psr.c

1772

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1776

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_psr.c

1785

if (crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_psr.c

1791

crtc_state->entry_setup_frames = entry_setup_frames;

drivers/gpu/drm/i915/display/intel_psr.c

1793

crtc_state->no_psr_reason = "PSR setup timing not met";

drivers/gpu/drm/i915/display/intel_psr.c

1814

static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1834

if (crtc_state->crc_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1840

if (intel_dsc_enabled_on_link(crtc_state) &&

drivers/gpu/drm/i915/display/intel_psr.c

1848

crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1849

crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1856

if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&

drivers/gpu/drm/i915/display/intel_psr.c

1857

to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)

drivers/gpu/drm/i915/display/intel_psr.c

1861

if (intel_dp_is_uhbr(crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

1878

if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))

drivers/gpu/drm/i915/display/intel_psr.c

1885

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

1889

return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&

drivers/gpu/drm/i915/display/intel_psr.c

1890

!crtc_state->has_sel_update);

drivers/gpu/drm/i915/display/intel_psr.c

1895

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

1898

struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);

drivers/gpu/drm/i915/display/intel_psr.c

1907

if (crtc_state->has_panel_replay)

drivers/gpu/drm/i915/display/intel_psr.c

1916

crtc_state->active_non_psr_pipes = active_pipes &

drivers/gpu/drm/i915/display/intel_psr.c

1917

~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);

drivers/gpu/drm/i915/display/intel_psr.c

1921

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1926

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_psr.c

1950

if (crtc_state->joiner_pipes) {

drivers/gpu/drm/i915/display/intel_psr.c

1957

crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;

drivers/gpu/drm/i915/display/intel_psr.c

1958

crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_psr.c

1960

crtc_state->has_psr = crtc_state->has_panel_replay ? true :

drivers/gpu/drm/i915/display/intel_psr.c

1961

_psr_compute_config(intel_dp, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_psr.c

1963

if (!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_psr.c

1966

crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_psr.c

2058

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2065

if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)

drivers/gpu/drm/i915/display/intel_psr.c

2070

crtc_state->hw.adjusted_mode.crtc_vblank_start !=

drivers/gpu/drm/i915/display/intel_psr.c

2071

crtc_state->hw.adjusted_mode.crtc_vdisplay)

drivers/gpu/drm/i915/display/intel_psr.c

2083

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2165

wm_optimization_wa(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2202

intel_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2205

intel_vrr_psr_frame_change_enable(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

223

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2239

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2247

intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;

drivers/gpu/drm/i915/display/intel_psr.c

2248

intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

2250

intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2251

intel_dp->psr.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2253

val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);

drivers/gpu/drm/i915/display/intel_psr.c

2255

intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;

drivers/gpu/drm/i915/display/intel_psr.c

2256

intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;

drivers/gpu/drm/i915/display/intel_psr.c

2257

intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;

drivers/gpu/drm/i915/display/intel_psr.c

2260

crtc_state->req_psr2_sdp_prior_scanline;

drivers/gpu/drm/i915/display/intel_psr.c

2261

intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

2262

intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;

drivers/gpu/drm/i915/display/intel_psr.c

2263

intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2264

intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2265

intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;

drivers/gpu/drm/i915/display/intel_psr.c

2289

intel_psr_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2294

intel_psr_enable_source(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

237

return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&

drivers/gpu/drm/i915/display/intel_psr.c

2553

bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2555

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_psr.c

2556

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2594

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_psr.c

2598

if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

2611

int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2614

return _intel_psr_min_set_context_latency(crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

2615

crtc_state->has_panel_replay,

drivers/gpu/drm/i915/display/intel_psr.c

2616

crtc_state->has_sel_update);

drivers/gpu/drm/i915/display/intel_psr.c

2667

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2669

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2670

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_psr.c

2671

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2674

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/intel_psr.c

2678

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_psr.c

2691

crtc_state->psr2_man_track_ctl);

drivers/gpu/drm/i915/display/intel_psr.c

2693

if (!crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_psr.c

2697

crtc_state->pipe_srcsz_early_tpt);

drivers/gpu/drm/i915/display/intel_psr.c

2699

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_psr.c

2702

intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

2703

drm_rect_height(&crtc_state->psr2_su_area));

drivers/gpu/drm/i915/display/intel_psr.c

2706

static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

2709

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2720

if (crtc_state->psr2_su_area.y1 == -1)

drivers/gpu/drm/i915/display/intel_psr.c

2724

val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1);

drivers/gpu/drm/i915/display/intel_psr.c

2725

val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1);

drivers/gpu/drm/i915/display/intel_psr.c

2727

drm_WARN_ON(crtc_state->uapi.crtc->dev,

drivers/gpu/drm/i915/display/intel_psr.c

2728

crtc_state->psr2_su_area.y1 % 4 ||

drivers/gpu/drm/i915/display/intel_psr.c

2729

crtc_state->psr2_su_area.y2 % 4);

drivers/gpu/drm/i915/display/intel_psr.c

2732

crtc_state->psr2_su_area.y1 / 4 + 1);

drivers/gpu/drm/i915/display/intel_psr.c

2734

crtc_state->psr2_su_area.y2 / 4 + 1);

drivers/gpu/drm/i915/display/intel_psr.c

2737

crtc_state->psr2_man_track_ctl = val;

drivers/gpu/drm/i915/display/intel_psr.c

2740

static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

2745

if (!crtc_state->enable_psr2_su_region_et || full_update)

drivers/gpu/drm/i915/display/intel_psr.c

2748

width = drm_rect_width(&crtc_state->psr2_su_area);

drivers/gpu/drm/i915/display/intel_psr.c

2749

height = drm_rect_height(&crtc_state->psr2_su_area);

drivers/gpu/drm/i915/display/intel_psr.c

2774

static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2776

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2777

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_psr.c

2782

if (crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_psr.c

2786

y_alignment = crtc_state->su_y_granularity;

drivers/gpu/drm/i915/display/intel_psr.c

2788

if (crtc_state->psr2_su_area.y1 % y_alignment) {

drivers/gpu/drm/i915/display/intel_psr.c

2789

crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;

drivers/gpu/drm/i915/display/intel_psr.c

2793

if (crtc_state->psr2_su_area.y2 % y_alignment) {

drivers/gpu/drm/i915/display/intel_psr.c

2794

crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /

drivers/gpu/drm/i915/display/intel_psr.c

2812

struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_psr.c

2817

if (!crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_psr.c

2823

if (new_plane_state->hw.crtc != crtc_state->uapi.crtc)

drivers/gpu/drm/i915/display/intel_psr.c

2832

inter = crtc_state->psr2_su_area;

drivers/gpu/drm/i915/display/intel_psr.c

2836

clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_psr.c

2869

static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2871

if (crtc_state->scaler_state.scaler_id >= 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2872

crtc_state->async_flip_planes)

drivers/gpu/drm/i915/display/intel_psr.c

2879

static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2881

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2885

if (crtc_state->psr2_su_area.y1 != 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2886

crtc_state->psr2_su_area.y2 != 0)

drivers/gpu/drm/i915/display/intel_psr.c

2889

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

drivers/gpu/drm/i915/display/intel_psr.c

2890

hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546;

drivers/gpu/drm/i915/display/intel_psr.c

2892

hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273;

drivers/gpu/drm/i915/display/intel_psr.c

2894

if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit)

drivers/gpu/drm/i915/display/intel_psr.c

2898

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_psr.c

2904

crtc_state->psr2_su_area.y2++;

drivers/gpu/drm/i915/display/intel_psr.c

2911

intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

2913

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2916

if (!crtc_state->has_panel_replay &&

drivers/gpu/drm/i915/display/intel_psr.c

2919

crtc_state->splitter.enable)

drivers/gpu/drm/i915/display/intel_psr.c

2920

crtc_state->psr2_su_area.y1 = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2923

crtc_state->req_psr2_sdp_prior_scanline &&

drivers/gpu/drm/i915/display/intel_psr.c

2924

!crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_psr.c

2925

crtc_state->psr2_su_area.y1 = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2929

intel_psr_apply_pr_link_on_su_wa(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2936

struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/i915/display/intel_psr.c

2942

.x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay,

drivers/gpu/drm/i915/display/intel_psr.c

2943

.y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay,

drivers/gpu/drm/i915/display/intel_psr.c

2948

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/intel_psr.c

2951

if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

2956

crtc_state->psr2_su_area.x1 = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2957

crtc_state->psr2_su_area.y1 = -1;

drivers/gpu/drm/i915/display/intel_psr.c

2958

crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area);

drivers/gpu/drm/i915/display/intel_psr.c

2959

crtc_state->psr2_su_area.y2 = -1;

drivers/gpu/drm/i915/display/intel_psr.c

2972

if (new_plane_state->hw.crtc != crtc_state->uapi.crtc)

drivers/gpu/drm/i915/display/intel_psr.c

2995

clip_area_update(&crtc_state->psr2_su_area, &damaged_area,

drivers/gpu/drm/i915/display/intel_psr.c

3002

clip_area_update(&crtc_state->psr2_su_area, &damaged_area,

drivers/gpu/drm/i915/display/intel_psr.c

3010

clip_area_update(&crtc_state->psr2_su_area, &damaged_area,

drivers/gpu/drm/i915/display/intel_psr.c

3027

clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area);

drivers/gpu/drm/i915/display/intel_psr.c

3036

if (crtc_state->psr2_su_area.y1 == -1) {

drivers/gpu/drm/i915/display/intel_psr.c

3046

intel_psr_apply_su_area_workarounds(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3065

su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3089

if (new_plane_state->hw.crtc != crtc_state->uapi.crtc ||

drivers/gpu/drm/i915/display/intel_psr.c

3093

inter = crtc_state->psr2_su_area;

drivers/gpu/drm/i915/display/intel_psr.c

3103

crtc_state->update_planes |= BIT(plane->id);

drivers/gpu/drm/i915/display/intel_psr.c

3116

crtc_state->update_planes |= BIT(plane->id);

drivers/gpu/drm/i915/display/intel_psr.c

3133

crtc_state->update_planes |= BIT(linked->id);

drivers/gpu/drm/i915/display/intel_psr.c

3139

clip_area_update(&crtc_state->psr2_su_area, &display_area,

drivers/gpu/drm/i915/display/intel_psr.c

3142

psr2_man_trk_ctl_calc(crtc_state, full_update);

drivers/gpu/drm/i915/display/intel_psr.c

3143

crtc_state->pipe_srcsz_early_tpt =

drivers/gpu/drm/i915/display/intel_psr.c

3144

psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);

drivers/gpu/drm/i915/display/intel_psr.c

3148

void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

3150

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3151

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_psr.c

3152

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3162

if (!crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_psr.c

3220

verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

3222

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3224

if (!crtc_state->has_panel_replay)

drivers/gpu/drm/i915/display/intel_psr.c

3228

intel_dsc_enabled_on_link(crtc_state) &&

drivers/gpu/drm/i915/display/intel_psr.c

3229

crtc_state->panel_replay_dsc_support ==

drivers/gpu/drm/i915/display/intel_psr.c

3237

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_psr.c

3241

if (!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_psr.c

3244

verify_panel_replay_dsc_state(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3247

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_psr.c

3255

psr->enabled && !crtc_state->active_planes);

drivers/gpu/drm/i915/display/intel_psr.c

3260

if (!crtc_state->active_planes) {

drivers/gpu/drm/i915/display/intel_psr.c

3266

if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3272

intel_psr_enable_locked(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3273

else if (psr->enabled && !crtc_state->wm_level_disabled)

drivers/gpu/drm/i915/display/intel_psr.c

3275

wm_optimization_wa(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3278

if (crtc_state->crc_enabled && psr->enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3447

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_psr.c

3461

crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/i915/display/intel_psr.c

3462

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

3463

err = PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3468

crtc_state->mode_changed = true;

drivers/gpu/drm/i915/display/intel_psr.c

4016

void intel_psr_lock(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4018

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4021

if (!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_psr.c

4025

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_psr.c

4039

void intel_psr_unlock(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4041

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4044

if (!crtc_state->has_psr)

drivers/gpu/drm/i915/display/intel_psr.c

4048

crtc_state->uapi.encoder_mask) {

drivers/gpu/drm/i915/display/intel_psr.c

4595

bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4601

return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||

drivers/gpu/drm/i915/display/intel_psr.c

4602

crtc_state->has_panel_replay);

drivers/gpu/drm/i915/display/intel_psr.c

4606

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4608

return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

4612

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4615

int vblank = intel_crtc_vblank_length(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4618

if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

4619

wake_lines = crtc_state->alpm_state.aux_less_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

4620

else if (intel_psr_needs_alpm(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

4622

psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,

drivers/gpu/drm/i915/display/intel_psr.c

4623

crtc_state->alpm_state.fast_wake_lines) :

drivers/gpu/drm/i915/display/intel_psr.c

4624

crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

4634

if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) {

drivers/gpu/drm/i915/display/intel_psr.c

4639

if (crtc_state->has_panel_replay) {

drivers/gpu/drm/i915/display/intel_psr.c

4640

crtc_state->has_panel_replay = false;

drivers/gpu/drm/i915/display/intel_psr.c

4647

crtc_state->has_psr = false;

drivers/gpu/drm/i915/display/intel_psr.c

4650

crtc_state->has_sel_update = false;

drivers/gpu/drm/i915/display/intel_psr.c

4651

crtc_state->enable_psr2_su_region_et = false;

drivers/gpu/drm/i915/display/intel_psr.c

4652

crtc_state->enable_psr2_sel_fetch = false;

drivers/gpu/drm/i915/display/intel_psr.c

4656

if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

4657

crtc_state->has_psr = false;

drivers/gpu/drm/i915/display/intel_psr.c

4662

intel_psr_set_non_psr_pipes(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4665

int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4667

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4671

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

drivers/gpu/drm/i915/display/intel_psr.c

4674

if (crtc_state->has_panel_replay)

drivers/gpu/drm/i915/display/intel_psr.c

4675

wake_lines = crtc_state->alpm_state.aux_less_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

4676

else if (crtc_state->has_sel_update)

drivers/gpu/drm/i915/display/intel_psr.c

4678

psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,

drivers/gpu/drm/i915/display/intel_psr.c

4679

crtc_state->alpm_state.fast_wake_lines) :

drivers/gpu/drm/i915/display/intel_psr.c

4680

crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

4684

psr_min_guardband = wake_lines + crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_psr.c

4686

if (crtc_state->req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

4692

bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4694

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

4696

return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;

drivers/gpu/drm/i915/display/intel_psr.c

794

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

805

if (crtc_state->has_sel_update)

drivers/gpu/drm/i915/display/intel_psr.c

808

if (crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_psr.c

811

if (crtc_state->req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

823

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

828

if (crtc_state->has_sel_update) {

drivers/gpu/drm/i915/display/intel_psr.c

838

if (crtc_state->req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

841

if (crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/intel_psr.c

853

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

855

intel_alpm_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

857

crtc_state->has_panel_replay ?

drivers/gpu/drm/i915/display/intel_psr.c

858

_panel_replay_enable_sink(intel_dp, crtc_state) :

drivers/gpu/drm/i915/display/intel_psr.c

859

_psr_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

30

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

48

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_psr.h

61

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

62

void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

65

bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

74

void intel_psr_lock(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

75

void intel_psr_unlock(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

79

int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

82

bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

84

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

86

struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

87

int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

88

bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_sdvo.c

1099

struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sdvo.c

1103

struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;

drivers/gpu/drm/i915/display/intel_sdvo.c

1105

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_sdvo.c

1108

if (!crtc_state->has_hdmi_sink)

drivers/gpu/drm/i915/display/intel_sdvo.c

1111

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_sdvo.c

1123

crtc_state->limited_color_range ?

drivers/gpu/drm/i915/display/intel_sdvo.c

1135

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sdvo.c

1139

const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;

drivers/gpu/drm/i915/display/intel_sdvo.c

1142

if ((crtc_state->infoframes.enable &

drivers/gpu/drm/i915/display/intel_sdvo.c

1160

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sdvo.c

1164

union hdmi_infoframe *frame = &crtc_state->infoframes.avi;

drivers/gpu/drm/i915/display/intel_sdvo.c

1168

if (!crtc_state->has_hdmi_sink)

drivers/gpu/drm/i915/display/intel_sdvo.c

1180

crtc_state->infoframes.enable |=

drivers/gpu/drm/i915/display/intel_sdvo.c

1196

struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sdvo.c

1202

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_sdvo.c

1212

crtc_state->eld, sizeof(crtc_state->eld));

drivers/gpu/drm/i915/display/intel_sdvo.c

1326

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sdvo.c

1334

return intel_hdmi_limited_color_range(crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_sdvo.c

1338

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sdvo.c

1347

if (!crtc_state->has_hdmi_sink)

drivers/gpu/drm/i915/display/intel_sdvo.c

1525

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sdvo.c

1529

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_sdvo.c

1530

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_sdvo.c

1535

const struct drm_display_mode *mode = &crtc_state->hw.mode;

drivers/gpu/drm/i915/display/intel_sdvo.c

1581

if (crtc_state->has_hdmi_sink) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1584

crtc_state->limited_color_range ?

drivers/gpu/drm/i915/display/intel_sdvo.c

1587

intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);

drivers/gpu/drm/i915/display/intel_sdvo.c

1607

switch (crtc_state->pixel_multiplier) {

drivers/gpu/drm/i915/display/intel_sdvo.c

1646

sdvox |= (crtc_state->pixel_multiplier - 1)

drivers/gpu/drm/i915/display/intel_sdvo.c

1816

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sdvo.c

1820

const u8 *eld = crtc_state->eld;

drivers/gpu/drm/i915/display/intel_sdvo.c

1822

if (!crtc_state->has_audio)

drivers/gpu/drm/i915/display/intel_sdvo.c

2449

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_sdvo.c

2452

crtc_state->connectors_changed = true;

drivers/gpu/drm/i915/display/intel_sdvo.c

2534

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_sdvo.c

2538

crtc_state->connectors_changed = true;

drivers/gpu/drm/i915/display/intel_snps_phy.c

1776

intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_snps_phy.c

1779

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {

drivers/gpu/drm/i915/display/intel_snps_phy.c

1781

} else if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_snps_phy.c

1783

} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_snps_phy.c

1791

int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_snps_phy.c

1797

tables = intel_mpllb_tables_get(crtc_state, encoder);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1802

if (crtc_state->port_clock == tables[i]->clock) {

drivers/gpu/drm/i915/display/intel_snps_phy.c

1803

crtc_state->dpll_hw_state.mpllb = *tables[i];

drivers/gpu/drm/i915/display/intel_snps_phy.c

1809

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

drivers/gpu/drm/i915/display/intel_snps_phy.c

1810

intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb,

drivers/gpu/drm/i915/display/intel_snps_phy.c

1811

crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1820

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_snps_phy.c

1823

const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;

drivers/gpu/drm/i915/display/intel_snps_phy.c

68

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_snps_phy.c

75

trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);

drivers/gpu/drm/i915/display/intel_snps_phy.c

80

int level = intel_ddi_level(encoder, crtc_state, ln);

drivers/gpu/drm/i915/display/intel_snps_phy.h

23

int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_snps_phy.h

26

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_snps_phy.h

34

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1000

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_sprite.c

1003

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_sprite.c

1137

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1167

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1177

dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1208

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1271

g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1280

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_sprite.c

1337

g4x_sprite_check(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1355

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1371

ret = g4x_sprite_check_scaling(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1401

vlv_sprite_check(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1410

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

179

vlv_plane_ratio(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

183

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

drivers/gpu/drm/i915/display/intel_sprite.c

237

int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

250

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_sprite.c

252

vlv_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

257

static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sprite.c

261

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_sprite.c

368

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

390

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

401

sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

437

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sprite.c

482

static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

486

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

drivers/gpu/drm/i915/display/intel_sprite.c

519

static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

546

int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

559

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_sprite.c

561

ivb_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

566

static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

579

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_sprite.c

585

ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

587

ivb_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

596

static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

600

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

drivers/gpu/drm/i915/display/intel_sprite.c

629

int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

632

unsigned int pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_sprite.c

635

hsw_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

640

static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sprite.c

644

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/intel_sprite.c

647

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/intel_sprite.c

791

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

822

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

832

sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

867

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sprite.c

913

static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

927

pixel_rate = crtc_state->pixel_rate;

drivers/gpu/drm/i915/display/intel_sprite.c

996

static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_sprite.h

22

int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.h

24

int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.h

26

int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_tc.c

1629

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_tc.c

1639

} else if (crtc_state && crtc_state->hw.active) {

drivers/gpu/drm/i915/display/intel_tc.c

1640

pll_type = intel_ddi_port_pll_type(&dig_port->base, crtc_state);

drivers/gpu/drm/i915/display/intel_tc.c

1665

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_tc.c

1673

if (!tc_port_has_active_streams(tc, crtc_state)) {

drivers/gpu/drm/i915/display/intel_tc.c

1783

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_tc.c

1785

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/intel_tc.c

1786

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/intel_tc.c

1787

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/intel_tc.c

1789

crtc_state->uapi.connectors_changed = true;

drivers/gpu/drm/i915/display/intel_tc.h

100

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

199

int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vblank.c

201

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

233

return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ? 2 : 1;

drivers/gpu/drm/i915/display/intel_vblank.c

524

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vblank.c

527

drm_mode_init(mode, &crtc_state->hw.adjusted_mode);

drivers/gpu/drm/i915/display/intel_vblank.c

533

mode->crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

534

mode->crtc_vblank_end = intel_vrr_vmax_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

535

mode->crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

536

*vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

539

void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vblank.c

542

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

543

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vblank.c

544

u8 mode_flags = crtc_state->mode_flags;

drivers/gpu/drm/i915/display/intel_vblank.c

550

crtc_state, vrr_enable);

drivers/gpu/drm/i915/display/intel_vblank.c

578

crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

654

static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vblank.c

656

bool is_push_sent = intel_vrr_is_push_sent(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

659

if (!crtc_state->vrr.dc_balance.enable) {

drivers/gpu/drm/i915/display/intel_vblank.c

661

return intel_vrr_vmin_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

663

return intel_vrr_vmax_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

667

vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

669

vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

675

vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

677

vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

688

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/intel_vblank.c

699

crtc_state = pre_commit_crtc_state(old_crtc_state, new_crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

701

adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vblank.c

708

evade->vblank_start = vrr_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.c

710

vblank_delay = crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vblank.c

797

int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vblank.c

799

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vblank.c

801

if (crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vblank.c

802

return crtc_state->vrr.guardband;

drivers/gpu/drm/i915/display/intel_vblank.h

43

void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vblank.h

45

int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vblank.h

51

int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1005

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);

drivers/gpu/drm/i915/display/intel_vdsc.c

1011

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);

drivers/gpu/drm/i915/display/intel_vdsc.c

1017

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);

drivers/gpu/drm/i915/display/intel_vdsc.c

1023

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);

drivers/gpu/drm/i915/display/intel_vdsc.c

1031

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);

drivers/gpu/drm/i915/display/intel_vdsc.c

1037

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);

drivers/gpu/drm/i915/display/intel_vdsc.c

1043

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);

drivers/gpu/drm/i915/display/intel_vdsc.c

1048

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);

drivers/gpu/drm/i915/display/intel_vdsc.c

1054

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);

drivers/gpu/drm/i915/display/intel_vdsc.c

1060

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);

drivers/gpu/drm/i915/display/intel_vdsc.c

1065

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);

drivers/gpu/drm/i915/display/intel_vdsc.c

1072

void intel_dsc_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

1074

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1075

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

1076

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vdsc.c

1081

if (!intel_dsc_source_support(crtc_state))

drivers/gpu/drm/i915/display/intel_vdsc.c

1093

crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;

drivers/gpu/drm/i915/display/intel_vdsc.c

1094

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

1099

crtc_state->dsc.slice_config.streams_per_pipe = 3;

drivers/gpu/drm/i915/display/intel_vdsc.c

1101

crtc_state->dsc.slice_config.streams_per_pipe = 2;

drivers/gpu/drm/i915/display/intel_vdsc.c

1103

crtc_state->dsc.slice_config.streams_per_pipe = 1;

drivers/gpu/drm/i915/display/intel_vdsc.c

1105

intel_dsc_get_pps_config(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1111

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

1115

FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),

drivers/gpu/drm/i915/display/intel_vdsc.c

1116

intel_dsc_line_slice_count(&crtc_state->dsc.slice_config),

drivers/gpu/drm/i915/display/intel_vdsc.c

1117

crtc_state->dsc.slice_config.streams_per_pipe);

drivers/gpu/drm/i915/display/intel_vdsc.c

1121

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

1123

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

1126

intel_vdsc_dump_state(p, indent, crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1127

drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);

drivers/gpu/drm/i915/display/intel_vdsc.c

1146

int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

1148

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1149

int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

1150

int htotal = crtc_state->hw.adjusted_mode.crtc_htotal;

drivers/gpu/drm/i915/display/intel_vdsc.c

1151

int dsc_slices = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config);

drivers/gpu/drm/i915/display/intel_vdsc.c

1155

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

1159

crtc_state->pixel_rate,

drivers/gpu/drm/i915/display/intel_vdsc.c

1172

if (crtc_state->joiner_pipes) {

drivers/gpu/drm/i915/display/intel_vdsc.c

1173

int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);

drivers/gpu/drm/i915/display/intel_vdsc.c

1191

int min_cdclk_bj = (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *

drivers/gpu/drm/i915/display/intel_vdsc.c

1200

unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

1202

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

24

bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

26

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

27

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vdsc.c

315

static bool is_dsi_dsc_1_1(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

317

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

321

intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI);

drivers/gpu/drm/i915/display/intel_vdsc.c

428

void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

430

crtc_state->dsc.compression_enabled_on_link = true;

drivers/gpu/drm/i915/display/intel_vdsc.c

431

crtc_state->dsc.compression_enable = true;

drivers/gpu/drm/i915/display/intel_vdsc.c

434

bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

436

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

438

drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&

drivers/gpu/drm/i915/display/intel_vdsc.c

439

!crtc_state->dsc.compression_enabled_on_link);

drivers/gpu/drm/i915/display/intel_vdsc.c

441

return crtc_state->dsc.compression_enabled_on_link;

drivers/gpu/drm/i915/display/intel_vdsc.c

470

static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

472

return crtc_state->dsc.slice_config.streams_per_pipe;

drivers/gpu/drm/i915/display/intel_vdsc.c

475

int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

477

int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

478

int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

485

static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,

drivers/gpu/drm/i915/display/intel_vdsc.c

488

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

489

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vdsc.c

505

static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vdsc.c

508

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

512

vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

517

intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);

drivers/gpu/drm/i915/display/intel_vdsc.c

523

static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

525

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

526

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

527

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

528

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vdsc.c

534

int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

535

int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

557

intel_dsc_pps_write(crtc_state, 0, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

561

intel_dsc_pps_write(crtc_state, 1, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

566

intel_dsc_pps_write(crtc_state, 2, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

571

intel_dsc_pps_write(crtc_state, 3, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

576

intel_dsc_pps_write(crtc_state, 4, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

581

intel_dsc_pps_write(crtc_state, 5, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

588

intel_dsc_pps_write(crtc_state, 6, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

593

intel_dsc_pps_write(crtc_state, 7, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

598

intel_dsc_pps_write(crtc_state, 8, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

603

intel_dsc_pps_write(crtc_state, 9, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

610

intel_dsc_pps_write(crtc_state, 10, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

618

intel_dsc_pps_write(crtc_state, 16, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

623

intel_dsc_pps_write(crtc_state, 17, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

628

intel_dsc_pps_write(crtc_state, 18, pps_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

781

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

783

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

789

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

803

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

806

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

809

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

818

dig_port->write_infoframe(encoder, crtc_state,

drivers/gpu/drm/i915/display/intel_vdsc.c

824

const struct intel_crtc_state *crtc_state, int su_lines)

drivers/gpu/drm/i915/display/intel_vdsc.c

826

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

827

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

828

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

830

int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

858

void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

860

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

861

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

864

if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {

drivers/gpu/drm/i915/display/intel_vdsc.c

865

if (intel_crtc_is_bigjoiner_secondary(crtc_state))

drivers/gpu/drm/i915/display/intel_vdsc.c

870

intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_vdsc.c

875

void intel_dsc_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

877

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

878

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vdsc.c

881

int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

883

if (!crtc_state->dsc.compression_enable)

drivers/gpu/drm/i915/display/intel_vdsc.c

886

intel_dsc_pps_configure(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

899

if (crtc_state->joiner_pipes) {

drivers/gpu/drm/i915/display/intel_vdsc.c

900

if (intel_crtc_ultrajoiner_enable_needed(crtc_state))

drivers/gpu/drm/i915/display/intel_vdsc.c

903

if (intel_crtc_is_ultrajoiner_primary(crtc_state))

drivers/gpu/drm/i915/display/intel_vdsc.c

908

if (intel_crtc_is_bigjoiner_primary(crtc_state))

drivers/gpu/drm/i915/display/intel_vdsc.c

911

intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

912

intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);

drivers/gpu/drm/i915/display/intel_vdsc.c

928

static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,

drivers/gpu/drm/i915/display/intel_vdsc.c

931

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

936

vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

941

intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);

drivers/gpu/drm/i915/display/intel_vdsc.c

957

static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)

drivers/gpu/drm/i915/display/intel_vdsc.c

959

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

963

val = intel_dsc_pps_read(crtc_state, pps, &all_equal);

drivers/gpu/drm/i915/display/intel_vdsc.c

969

static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vdsc.c

971

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

972

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

drivers/gpu/drm/i915/display/intel_vdsc.c

973

int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.c

977

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);

drivers/gpu/drm/i915/display/intel_vdsc.c

989

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);

drivers/gpu/drm/i915/display/intel_vdsc.c

996

crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;

drivers/gpu/drm/i915/display/intel_vdsc.c

999

pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);

drivers/gpu/drm/i915/display/intel_vdsc.h

21

bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

26

void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

27

void intel_dsc_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

28

void intel_dsc_disable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

30

void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

31

bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

32

void intel_dsc_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

36

int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

38

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

40

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

42

const struct intel_crtc_state *crtc_state, int su_lines);

drivers/gpu/drm/i915/display/intel_vdsc.h

44

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

45

int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vdsc.h

46

unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1008

void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1010

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1011

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

1014

trans_vrr_push(crtc_state, false));

drivers/gpu/drm/i915/display/intel_vrr.c

1017

bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1019

return crtc_state->vrr.flipline &&

drivers/gpu/drm/i915/display/intel_vrr.c

1020

crtc_state->vrr.flipline == crtc_state->vrr.vmax &&

drivers/gpu/drm/i915/display/intel_vrr.c

1021

crtc_state->vrr.flipline == crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

1025

void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1028

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1029

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vrr.c

1032

if (!intel_vrr_dc_balance_possible(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

1036

crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0;

drivers/gpu/drm/i915/display/intel_vrr.c

1039

crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0;

drivers/gpu/drm/i915/display/intel_vrr.c

1041

crtc_state->vrr.dc_balance.guardband =

drivers/gpu/drm/i915/display/intel_vrr.c

1043

crtc_state->vrr.dc_balance.max_increase =

drivers/gpu/drm/i915/display/intel_vrr.c

1045

crtc_state->vrr.dc_balance.max_decrease =

drivers/gpu/drm/i915/display/intel_vrr.c

1047

crtc_state->vrr.dc_balance.slope =

drivers/gpu/drm/i915/display/intel_vrr.c

1049

crtc_state->vrr.dc_balance.vblank_target =

drivers/gpu/drm/i915/display/intel_vrr.c

1053

void intel_vrr_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1055

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1056

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

1064

crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);

drivers/gpu/drm/i915/display/intel_vrr.c

1066

if (crtc_state->cmrr.enable) {

drivers/gpu/drm/i915/display/intel_vrr.c

1067

crtc_state->cmrr.cmrr_n =

drivers/gpu/drm/i915/display/intel_vrr.c

1069

crtc_state->cmrr.cmrr_m =

drivers/gpu/drm/i915/display/intel_vrr.c

1074

crtc_state->vrr.guardband =

drivers/gpu/drm/i915/display/intel_vrr.c

1078

crtc_state->vrr.pipeline_full =

drivers/gpu/drm/i915/display/intel_vrr.c

1081

crtc_state->vrr.guardband =

drivers/gpu/drm/i915/display/intel_vrr.c

1082

intel_vrr_pipeline_full_to_guardband(crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

1083

crtc_state->vrr.pipeline_full);

drivers/gpu/drm/i915/display/intel_vrr.c

1088

crtc_state->vrr.flipline = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1090

crtc_state->vrr.vmax = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1092

crtc_state->vrr.vmin = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1097

crtc_state->vrr.flipline += crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vrr.c

1098

crtc_state->vrr.vmax += crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vrr.c

1099

crtc_state->vrr.vmin += crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vrr.c

1101

crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);

drivers/gpu/drm/i915/display/intel_vrr.c

1111

crtc_state->hw.adjusted_mode.crtc_vtotal =

drivers/gpu/drm/i915/display/intel_vrr.c

1112

intel_vrr_vmin_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1118

crtc_state->vrr.vsync_start =

drivers/gpu/drm/i915/display/intel_vrr.c

1120

crtc_state->vrr.vsync_end =

drivers/gpu/drm/i915/display/intel_vrr.c

1128

crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1130

crtc_state->vrr.enable = vrr_enable;

drivers/gpu/drm/i915/display/intel_vrr.c

1132

intel_vrr_get_dc_balance_config(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1139

if (crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

1140

crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

drivers/gpu/drm/i915/display/intel_vrr.c

1151

crtc_state->hw.adjusted_mode.crtc_vblank_start =

drivers/gpu/drm/i915/display/intel_vrr.c

1152

crtc_state->hw.adjusted_mode.crtc_vtotal -

drivers/gpu/drm/i915/display/intel_vrr.c

1153

crtc_state->vrr.guardband;

drivers/gpu/drm/i915/display/intel_vrr.c

1156

int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1158

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1161

return crtc_state->hw.adjusted_mode.crtc_vdisplay -

drivers/gpu/drm/i915/display/intel_vrr.c

1162

crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vrr.c

1164

return crtc_state->hw.adjusted_mode.crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_vrr.c

1168

intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1170

return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?

drivers/gpu/drm/i915/display/intel_vrr.c

1171

intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :

drivers/gpu/drm/i915/display/intel_vrr.c

1172

intel_vrr_dcb_vmin_vblank_start_next(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1175

int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1177

int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?

drivers/gpu/drm/i915/display/intel_vrr.c

1178

intel_vrr_dcb_vmin_vblank_start(crtc_state) :

drivers/gpu/drm/i915/display/intel_vrr.c

1179

intel_vrr_vmin_vblank_start(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1181

return vmin_vblank_start - crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vrr.c

1184

int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1186

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1187

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

1195

return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);

drivers/gpu/drm/i915/display/intel_vrr.c

1198

int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1200

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1201

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

1209

return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);

drivers/gpu/drm/i915/display/intel_vrr.c

1212

int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1214

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1215

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

1220

return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);

drivers/gpu/drm/i915/display/intel_vrr.c

1223

int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

1225

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

1226

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

1231

return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);

drivers/gpu/drm/i915/display/intel_vrr.c

135

static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

139

return guardband - crtc_state->framestart_delay - 1;

drivers/gpu/drm/i915/display/intel_vrr.c

142

static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

146

return pipeline_full + crtc_state->framestart_delay + 1;

drivers/gpu/drm/i915/display/intel_vrr.c

166

int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

169

return crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

172

int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

174

return crtc_state->vrr.vmax;

drivers/gpu/drm/i915/display/intel_vrr.c

177

int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

179

return intel_vrr_vmin_vtotal(crtc_state) - crtc_state->vrr.guardband;

drivers/gpu/drm/i915/display/intel_vrr.c

182

int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

184

return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;

drivers/gpu/drm/i915/display/intel_vrr.c

188

is_cmrr_frac_required(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

190

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

192

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

212

cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)

drivers/gpu/drm/i915/display/intel_vrr.c

216

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

225

crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,

drivers/gpu/drm/i915/display/intel_vrr.c

228

crtc_state->cmrr.cmrr_n);

drivers/gpu/drm/i915/display/intel_vrr.c

230

crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);

drivers/gpu/drm/i915/display/intel_vrr.c

236

void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

244

crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);

drivers/gpu/drm/i915/display/intel_vrr.c

245

crtc_state->vrr.vmin = crtc_state->vrr.vmax;

drivers/gpu/drm/i915/display/intel_vrr.c

246

crtc_state->vrr.flipline = crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

248

crtc_state->cmrr.enable = true;

drivers/gpu/drm/i915/display/intel_vrr.c

249

crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

drivers/gpu/drm/i915/display/intel_vrr.c

253

void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

256

crtc_state->vrr.vmax = vmax;

drivers/gpu/drm/i915/display/intel_vrr.c

257

crtc_state->vrr.vmin = vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

258

crtc_state->vrr.flipline = crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

260

crtc_state->vrr.enable = true;

drivers/gpu/drm/i915/display/intel_vrr.c

261

crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

drivers/gpu/drm/i915/display/intel_vrr.c

265

void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

268

crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;

drivers/gpu/drm/i915/display/intel_vrr.c

269

crtc_state->vrr.vmin = crtc_state->vrr.vmax;

drivers/gpu/drm/i915/display/intel_vrr.c

270

crtc_state->vrr.flipline = crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

273

static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

276

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

285

return value - crtc_state->set_context_latency;

drivers/gpu/drm/i915/display/intel_vrr.c

288

static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

291

return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband;

drivers/gpu/drm/i915/display/intel_vrr.c

299

int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

301

return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);

drivers/gpu/drm/i915/display/intel_vrr.c

305

int intel_vrr_fixed_rr_hw_vmax(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

307

return intel_vrr_fixed_rr_hw_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

311

int intel_vrr_fixed_rr_hw_vmin(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

313

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

315

return intel_vrr_fixed_rr_hw_vtotal(crtc_state) -

drivers/gpu/drm/i915/display/intel_vrr.c

320

int intel_vrr_fixed_rr_hw_flipline(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

322

return intel_vrr_fixed_rr_hw_vtotal(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

325

void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

327

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

328

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

330

if (!intel_vrr_possible(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

334

intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

336

intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

338

intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

342

int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

351

return crtc_state->hw.adjusted_mode.crtc_vtotal;

drivers/gpu/drm/i915/display/intel_vrr.c

368

static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

370

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

371

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vrr.c

384

intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

387

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

389

if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

392

crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;

drivers/gpu/drm/i915/display/intel_vrr.c

393

crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

394

crtc_state->vrr.dc_balance.max_increase =

drivers/gpu/drm/i915/display/intel_vrr.c

395

crtc_state->vrr.vmax - crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

396

crtc_state->vrr.dc_balance.max_decrease =

drivers/gpu/drm/i915/display/intel_vrr.c

397

crtc_state->vrr.vmax - crtc_state->vrr.vmin;

drivers/gpu/drm/i915/display/intel_vrr.c

398

crtc_state->vrr.dc_balance.guardband =

drivers/gpu/drm/i915/display/intel_vrr.c

399

DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *

drivers/gpu/drm/i915/display/intel_vrr.c

403

crtc_state->vrr.dc_balance.guardband);

drivers/gpu/drm/i915/display/intel_vrr.c

410

crtc_state->vrr.dc_balance.slope =

drivers/gpu/drm/i915/display/intel_vrr.c

412

crtc_state->vrr.dc_balance.vblank_target =

drivers/gpu/drm/i915/display/intel_vrr.c

413

DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *

drivers/gpu/drm/i915/display/intel_vrr.c

415

crtc_state->vrr.dc_balance.enable = true;

drivers/gpu/drm/i915/display/intel_vrr.c

419

intel_vrr_compute_config(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

422

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

427

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

436

crtc_state->vrr.in_range =

drivers/gpu/drm/i915/display/intel_vrr.c

447

if (crtc_state->joiner_pipes)

drivers/gpu/drm/i915/display/intel_vrr.c

448

crtc_state->vrr.in_range = false;

drivers/gpu/drm/i915/display/intel_vrr.c

450

vmin = intel_vrr_compute_vmin(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

452

if (crtc_state->vrr.in_range) {

drivers/gpu/drm/i915/display/intel_vrr.c

454

crtc_state->update_lrr = true;

drivers/gpu/drm/i915/display/intel_vrr.c

460

if (crtc_state->uapi.vrr_enabled && vmin < vmax)

drivers/gpu/drm/i915/display/intel_vrr.c

461

intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);

drivers/gpu/drm/i915/display/intel_vrr.c

462

else if (is_cmrr_frac_required(crtc_state) && is_edp)

drivers/gpu/drm/i915/display/intel_vrr.c

463

intel_vrr_compute_cmrr_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

465

intel_vrr_compute_fixed_rr_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

468

crtc_state->vrr.vsync_start =

drivers/gpu/drm/i915/display/intel_vrr.c

469

(crtc_state->hw.adjusted_mode.crtc_vtotal -

drivers/gpu/drm/i915/display/intel_vrr.c

470

crtc_state->hw.adjusted_mode.crtc_vsync_start);

drivers/gpu/drm/i915/display/intel_vrr.c

471

crtc_state->vrr.vsync_end =

drivers/gpu/drm/i915/display/intel_vrr.c

472

(crtc_state->hw.adjusted_mode.crtc_vtotal -

drivers/gpu/drm/i915/display/intel_vrr.c

473

crtc_state->hw.adjusted_mode.crtc_vsync_end);

drivers/gpu/drm/i915/display/intel_vrr.c

476

intel_vrr_dc_balance_compute_config(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

480

intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

482

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

488

return intel_vrr_pipeline_full_to_guardband(crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

493

intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

495

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

496

const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

498

return crtc_state->vrr.vmin -

drivers/gpu/drm/i915/display/intel_vrr.c

500

crtc_state->set_context_latency -

drivers/gpu/drm/i915/display/intel_vrr.c

505

intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

507

return min(intel_vrr_max_hw_guardband(crtc_state),

drivers/gpu/drm/i915/display/intel_vrr.c

508

intel_vrr_max_vblank_guardband(crtc_state));

drivers/gpu/drm/i915/display/intel_vrr.c

512

int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

514

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

519

skl_prefill_init_worst(&prefill_ctx, crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

530

crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

533

if (intel_crtc_has_dp_encoder(crtc_state)) {

drivers/gpu/drm/i915/display/intel_vrr.c

534

guardband = max(guardband, intel_psr_min_guardband(crtc_state));

drivers/gpu/drm/i915/display/intel_vrr.c

535

guardband = max(guardband, intel_dp_sdp_min_guardband(crtc_state, true));

drivers/gpu/drm/i915/display/intel_vrr.c

536

guardband = max(guardband, intel_alpm_lobf_min_guardband(crtc_state));

drivers/gpu/drm/i915/display/intel_vrr.c

542

static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

550

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

drivers/gpu/drm/i915/display/intel_vrr.c

556

void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

558

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

559

struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

560

struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/intel_vrr.c

563

if (!intel_vrr_possible(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

566

if (intel_vrr_use_optimized_guardband(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

567

guardband = intel_vrr_compute_optimized_guardband(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

569

guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;

drivers/gpu/drm/i915/display/intel_vrr.c

571

crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));

drivers/gpu/drm/i915/display/intel_vrr.c

575

adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband;

drivers/gpu/drm/i915/display/intel_vrr.c

585

crtc_state->vrr.pipeline_full =

drivers/gpu/drm/i915/display/intel_vrr.c

586

intel_vrr_guardband_to_pipeline_full(crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

587

crtc_state->vrr.guardband);

drivers/gpu/drm/i915/display/intel_vrr.c

590

static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

592

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

596

XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);

drivers/gpu/drm/i915/display/intel_vrr.c

599

XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);

drivers/gpu/drm/i915/display/intel_vrr.c

602

VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |

drivers/gpu/drm/i915/display/intel_vrr.c

606

void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

608

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

609

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

635

if (!intel_vrr_possible(crtc_state)) {

drivers/gpu/drm/i915/display/intel_vrr.c

641

if (crtc_state->cmrr.enable) {

drivers/gpu/drm/i915/display/intel_vrr.c

643

upper_32_bits(crtc_state->cmrr.cmrr_m));

drivers/gpu/drm/i915/display/intel_vrr.c

645

lower_32_bits(crtc_state->cmrr.cmrr_m));

drivers/gpu/drm/i915/display/intel_vrr.c

647

upper_32_bits(crtc_state->cmrr.cmrr_n));

drivers/gpu/drm/i915/display/intel_vrr.c

649

lower_32_bits(crtc_state->cmrr.cmrr_n));

drivers/gpu/drm/i915/display/intel_vrr.c

652

intel_vrr_set_fixed_rr_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

656

trans_vrr_ctl(crtc_state));

drivers/gpu/drm/i915/display/intel_vrr.c

661

VRR_VSYNC_END(crtc_state->vrr.vsync_end) |

drivers/gpu/drm/i915/display/intel_vrr.c

662

VRR_VSYNC_START(crtc_state->vrr.vsync_start));

drivers/gpu/drm/i915/display/intel_vrr.c

674

EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));

drivers/gpu/drm/i915/display/intel_vrr.c

678

intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

681

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

684

if (!crtc_state->vrr.dc_balance.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

705

static u32 trans_vrr_push(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

708

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

712

crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

725

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

727

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

728

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

730

if (!crtc_state->vrr.enable && !intel_psr_use_trans_push(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

738

trans_vrr_push(crtc_state, true));

drivers/gpu/drm/i915/display/intel_vrr.c

744

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

746

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

747

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vrr.c

748

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

750

if (!crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

771

if (intel_vrr_is_push_sent(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

777

bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

779

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

780

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

782

if (!crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

799

static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

801

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

803

return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin) -

drivers/gpu/drm/i915/display/intel_vrr.c

807

static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

809

return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);

drivers/gpu/drm/i915/display/intel_vrr.c

812

static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

814

return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);

drivers/gpu/drm/i915/display/intel_vrr.c

817

static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

819

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

820

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

823

intel_vrr_hw_vmin(crtc_state) - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

825

intel_vrr_hw_vmax(crtc_state) - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

827

intel_vrr_hw_flipline(crtc_state) - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

831

intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

833

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

834

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

835

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_vrr.c

839

if (!crtc_state->vrr.dc_balance.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

843

VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

845

VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

847

VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

849

VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

851

VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

853

VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

855

VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

857

VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));

drivers/gpu/drm/i915/display/intel_vrr.c

859

crtc_state->vrr.dc_balance.vmin - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

861

crtc_state->vrr.dc_balance.vmax - 1);

drivers/gpu/drm/i915/display/intel_vrr.c

863

crtc_state->vrr.dc_balance.max_increase);

drivers/gpu/drm/i915/display/intel_vrr.c

865

crtc_state->vrr.dc_balance.max_decrease);

drivers/gpu/drm/i915/display/intel_vrr.c

867

crtc_state->vrr.dc_balance.guardband);

drivers/gpu/drm/i915/display/intel_vrr.c

869

crtc_state->vrr.dc_balance.slope);

drivers/gpu/drm/i915/display/intel_vrr.c

871

crtc_state->vrr.dc_balance.vblank_target);

drivers/gpu/drm/i915/display/intel_vrr.c

916

static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.c

919

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

920

enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_vrr.c

924

trans_vrr_push(crtc_state, false));

drivers/gpu/drm/i915/display/intel_vrr.c

926

vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

93

bool intel_vrr_possible(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

95

return crtc_state->vrr.flipline;

drivers/gpu/drm/i915/display/intel_vrr.c

956

void intel_vrr_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

958

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

960

if (!crtc_state->vrr.enable)

drivers/gpu/drm/i915/display/intel_vrr.c

963

intel_vrr_set_vrr_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

964

intel_vrr_enable_dc_balancing(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

967

intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);

drivers/gpu/drm/i915/display/intel_vrr.c

984

void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_vrr.c

986

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

988

intel_vrr_set_transcoder_timings(crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.c

990

if (!intel_vrr_possible(crtc_state))

drivers/gpu/drm/i915/display/intel_vrr.c

994

intel_vrr_tg_enable(crtc_state, false);

drivers/gpu/drm/i915/display/intel_vrr.h

21

bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

23

void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.h

25

void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

26

void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

27

void intel_vrr_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

29

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

31

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

32

void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_vrr.h

34

bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

36

void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

37

void intel_vrr_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

38

int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

39

int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

40

int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

41

int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

42

bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

43

void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

44

void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

45

void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

49

int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

50

int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

52

int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

53

int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

54

int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_vrr.h

55

int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_wm.c

119

bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_wm.c

125

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/intel_wm.h

29

bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.c

101

prefill_init_nocdclk_worst(ctx, crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

103

ctx->adj.cdclk = intel_cdclk_prefill_adjustment_worst(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

109

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.c

111

prefill_init_nocdclk(ctx, crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

113

ctx->adj.cdclk = intel_cdclk_prefill_adjustment(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

119

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.c

122

return ctx->prefill.full + prefill_usecs_to_lines(crtc_state, latency_us);

drivers/gpu/drm/i915/display/skl_prefill.c

126

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.c

129

unsigned int prefill = prefill_lines_with_latency(ctx, crtc_state, latency_us);

drivers/gpu/drm/i915/display/skl_prefill.c

134

static unsigned int prefill_guardband(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.c

136

return intel_crtc_vblank_length(crtc_state) << 16;

drivers/gpu/drm/i915/display/skl_prefill.c

140

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.c

143

unsigned int guardband = prefill_guardband(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

144

unsigned int prefill = prefill_lines_with_latency(ctx, crtc_state, latency_us);

drivers/gpu/drm/i915/display/skl_prefill.c

150

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.c

153

unsigned int prefill_available = prefill_guardband(crtc_state) - ctx->prefill.fixed;

drivers/gpu/drm/i915/display/skl_prefill.c

155

return intel_cdclk_min_cdclk_for_prefill(crtc_state, prefill_unadjusted,

drivers/gpu/drm/i915/display/skl_prefill.c

19

static unsigned int prefill_usecs_to_lines(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.c

22

const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/skl_prefill.c

29

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.c

33

ctx->prefill.fixed = crtc_state->framestart_delay << 16;

drivers/gpu/drm/i915/display/skl_prefill.c

36

ctx->prefill.fixed += prefill_usecs_to_lines(crtc_state, 20);

drivers/gpu/drm/i915/display/skl_prefill.c

38

ctx->prefill.dsc = intel_vdsc_prefill_lines(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

42

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.c

44

prefill_init(ctx, crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

46

ctx->prefill.wm0 = skl_wm0_prefill_lines_worst(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

47

ctx->prefill.scaler_1st = skl_scaler_1st_prefill_lines_worst(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

48

ctx->prefill.scaler_2nd = skl_scaler_2nd_prefill_lines_worst(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

50

ctx->adj.scaler_1st = skl_scaler_1st_prefill_adjustment_worst(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

51

ctx->adj.scaler_2nd = skl_scaler_2nd_prefill_adjustment_worst(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

55

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.c

57

prefill_init(ctx, crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

59

ctx->prefill.wm0 = skl_wm0_prefill_lines(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

60

ctx->prefill.scaler_1st = skl_scaler_1st_prefill_lines(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

61

ctx->prefill.scaler_2nd = skl_scaler_2nd_prefill_lines(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

63

ctx->adj.scaler_1st = skl_scaler_1st_prefill_adjustment(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

64

ctx->adj.scaler_2nd = skl_scaler_2nd_prefill_adjustment(crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.c

99

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_prefill.h

33

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.h

35

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_prefill.h

38

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.h

41

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_prefill.h

44

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1001

if (!crtc_state->pch_pfit.enabled)

drivers/gpu/drm/i915/display/skl_scaler.c

1007

void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1009

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1010

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1012

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

1023

unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1032

unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1041

unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1044

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

1053

unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1056

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

1059

if (num_scalers > 1 && crtc_state->pch_pfit.enabled)

drivers/gpu/drm/i915/display/skl_scaler.c

1065

static unsigned int _skl_scaler_max_scale(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.c

1068

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1077

crtc_state->hw.pipe_mode.crtc_clock));

drivers/gpu/drm/i915/display/skl_scaler.c

1080

unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1082

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1093

return _skl_scaler_max_scale(crtc_state, max_scale);

drivers/gpu/drm/i915/display/skl_scaler.c

1096

unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1098

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1107

return _skl_scaler_max_scale(crtc_state, max_scale);

drivers/gpu/drm/i915/display/skl_scaler.c

1110

unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1112

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1121

return _skl_scaler_max_scale(crtc_state, max_scale);

drivers/gpu/drm/i915/display/skl_scaler.c

1124

unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1126

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1129

return skl_scaler_max_scale(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1134

unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1136

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1139

return skl_scaler_max_scale(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

1144

unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1146

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

1154

unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

1156

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

156

skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,

drivers/gpu/drm/i915/display/skl_scaler.c

162

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

164

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

165

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

167

&crtc_state->hw.adjusted_mode;

drivers/gpu/drm/i915/display/skl_scaler.c

168

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/skl_scaler.c

169

int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/skl_scaler.c

187

if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&

drivers/gpu/drm/i915/display/skl_scaler.c

269

int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

271

const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/skl_scaler.c

275

ret = intel_casf_compute_config(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

279

if (crtc_state->pch_pfit.enabled) {

drivers/gpu/drm/i915/display/skl_scaler.c

280

width = drm_rect_width(&crtc_state->pch_pfit.dst);

drivers/gpu/drm/i915/display/skl_scaler.c

281

height = drm_rect_height(&crtc_state->pch_pfit.dst);

drivers/gpu/drm/i915/display/skl_scaler.c

286

return skl_update_scaler(crtc_state, !crtc_state->hw.active,

drivers/gpu/drm/i915/display/skl_scaler.c

288

&crtc_state->scaler_state.scaler_id,

drivers/gpu/drm/i915/display/skl_scaler.c

289

drm_rect_width(&crtc_state->pipe_src),

drivers/gpu/drm/i915/display/skl_scaler.c

290

drm_rect_height(&crtc_state->pipe_src),

drivers/gpu/drm/i915/display/skl_scaler.c

292

crtc_state->pch_pfit.enabled);

drivers/gpu/drm/i915/display/skl_scaler.c

304

int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.c

318

return skl_update_scaler(crtc_state, force_detach,

drivers/gpu/drm/i915/display/skl_scaler.c

396

static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.c

403

struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

485

if (crtc_state->pch_pfit.enabled) {

drivers/gpu/drm/i915/display/skl_scaler.c

490

drm_rect_width(&crtc_state->pipe_src) << 16,

drivers/gpu/drm/i915/display/skl_scaler.c

491

drm_rect_height(&crtc_state->pipe_src) << 16);

drivers/gpu/drm/i915/display/skl_scaler.c

501

if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {

drivers/gpu/drm/i915/display/skl_scaler.c

506

hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

508

vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

516

drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false);

drivers/gpu/drm/i915/display/skl_scaler.c

536

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_scaler.c

539

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

541

return intel_atomic_setup_scaler(crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.c

545

crtc_state->pch_pfit.casf.enable);

drivers/gpu/drm/i915/display/skl_scaler.c

553

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_scaler.c

556

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

577

return intel_atomic_setup_scaler(crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.c

604

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_scaler.c

607

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

761

static u32 casf_sharpness_ctl(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

763

if (!crtc_state->pch_pfit.casf.enable)

drivers/gpu/drm/i915/display/skl_scaler.c

767

FILTER_STRENGTH(crtc_state->pch_pfit.casf.strength) |

drivers/gpu/drm/i915/display/skl_scaler.c

768

crtc_state->pch_pfit.casf.win_size;

drivers/gpu/drm/i915/display/skl_scaler.c

771

void skl_pfit_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

773

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

774

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

776

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

777

const struct drm_rect *dst = &crtc_state->pch_pfit.dst;

drivers/gpu/drm/i915/display/skl_scaler.c

789

if (!crtc_state->pch_pfit.enabled)

drivers/gpu/drm/i915/display/skl_scaler.c

793

crtc_state->scaler_state.scaler_id < 0))

drivers/gpu/drm/i915/display/skl_scaler.c

797

adl_scaler_ecc_mask(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

800

drm_rect_width(&crtc_state->pipe_src) << 16,

drivers/gpu/drm/i915/display/skl_scaler.c

801

drm_rect_height(&crtc_state->pipe_src) << 16);

drivers/gpu/drm/i915/display/skl_scaler.c

812

skl_scaler_get_filter_select(crtc_state->hw.scaling_filter,

drivers/gpu/drm/i915/display/skl_scaler.c

813

crtc_state->pch_pfit.casf.enable);

drivers/gpu/drm/i915/display/skl_scaler.c

817

if (crtc_state->pch_pfit.casf.enable)

drivers/gpu/drm/i915/display/skl_scaler.c

818

intel_casf_setup(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

821

crtc_state->hw.scaling_filter);

drivers/gpu/drm/i915/display/skl_scaler.c

825

casf_sharpness_ctl(crtc_state));

drivers/gpu/drm/i915/display/skl_scaler.c

839

static int skl_pipe_scaler_get_hw_state(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

841

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

842

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

858

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.c

866

&crtc_state->scaler_state.scalers[scaler_id];

drivers/gpu/drm/i915/display/skl_scaler.c

941

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

943

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

945

&crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

964

void skl_scaler_get_config(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

966

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

967

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_scaler.c

968

struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;

drivers/gpu/drm/i915/display/skl_scaler.c

973

scaler_id = skl_pipe_scaler_get_hw_state(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

978

intel_casf_sharpness_get_config(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.c

980

crtc_state->pch_pfit.enabled = true;

drivers/gpu/drm/i915/display/skl_scaler.c

985

drm_rect_init(&crtc_state->pch_pfit.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

997

void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_scaler.c

999

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

19

int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

21

int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.h

27

void skl_pfit_enable(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

31

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_scaler.h

34

const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

37

void skl_scaler_get_config(struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

45

void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

47

void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

49

unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

50

unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

51

unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

53

unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

54

unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

55

unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

56

unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

58

unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

59

unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

60

unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_scaler.h

61

unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1168

static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1170

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1176

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1179

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1226

static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1228

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1234

if (crtc_state->gamma_enable)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1237

if (crtc_state->csc_enable)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1379

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1406

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1431

skl_write_plane_wm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1437

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1448

skl_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1452

crtc_state->async_flip_planes & BIT(plane->id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

1457

glk_plane_color_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1488

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1503

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1513

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1518

if (crtc_state->enable_psr2_su_region_et)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1519

y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1550

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1568

glk_plane_color_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1617

skl_write_plane_wm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1624

icl_plane_csc_load_black(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1626

icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1631

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1637

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1644

icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1650

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1659

skl_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1669

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1671

icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1710

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1720

plane_ctl |= skl_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1747

static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1824

if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

1846

static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1853

int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2365

static int skl_plane_check(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2375

ret = skl_plane_check_fb(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2385

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2399

ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

266

static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

269

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

290

static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

293

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3060

struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3076

if (crtc_state->joiner_pipes) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

317

static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

320

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

823

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

828

const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;

drivers/gpu/drm/i915/display/skl_universal_plane.c

830

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

832

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

833

const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

835

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

869

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

875

skl_write_plane_wm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

883

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

888

if (!crtc_state->enable_psr2_sel_fetch)

drivers/gpu/drm/i915/display/skl_universal_plane.c

913

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

922

skl_write_plane_wm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

924

icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1263

use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1270

crtc_state->uapi.async_flip &&

drivers/gpu/drm/i915/display/skl_watermark.c

1275

skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1284

if (use_minimal_wm0_only(crtc_state, plane))

drivers/gpu/drm/i915/display/skl_watermark.c

1291

skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

1293

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1294

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

1302

data_rate += crtc_state->rel_data_rate[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1305

data_rate += crtc_state->rel_data_rate_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1436

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

1450

memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

1451

memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));

drivers/gpu/drm/i915/display/skl_watermark.c

1452

memset(crtc_state->wm.skl.plane_min_ddb, 0,

drivers/gpu/drm/i915/display/skl_watermark.c

1453

sizeof(crtc_state->wm.skl.plane_min_ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

1454

memset(crtc_state->wm.skl.plane_interim_ddb, 0,

drivers/gpu/drm/i915/display/skl_watermark.c

1455

sizeof(crtc_state->wm.skl.plane_interim_ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

1457

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/skl_watermark.c

1466

cursor_size = skl_cursor_allocation(crtc_state, num_active);

drivers/gpu/drm/i915/display/skl_watermark.c

1468

skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],

drivers/gpu/drm/i915/display/skl_watermark.c

1471

iter.data_rate = skl_total_relative_data_rate(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1481

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1485

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1525

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1527

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1528

u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1530

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1532

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1538

crtc_state->nv12_planes & BIT(plane_id))

drivers/gpu/drm/i915/display/skl_watermark.c

1540

ddb_y, crtc_state->rel_data_rate_y[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

1541

ddb, crtc_state->rel_data_rate[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.c

1544

ddb, crtc_state->rel_data_rate[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.c

1562

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1564

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1566

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1569

crtc_state->nv12_planes & BIT(plane_id))

drivers/gpu/drm/i915/display/skl_watermark.c

1588

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1590

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1592

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1594

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1597

crtc_state->nv12_planes & BIT(plane_id)) {

drivers/gpu/drm/i915/display/skl_watermark.c

1657

static int skl_wm_linetime_us(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1660

return DIV_ROUND_UP(crtc_state->hw.pipe_mode.crtc_htotal * 1000,

drivers/gpu/drm/i915/display/skl_watermark.c

1665

skl_compute_wm_params(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1671

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1748

wp->linetime_us = skl_wm_linetime_us(crtc_state, plane_pixel_rate);

drivers/gpu/drm/i915/display/skl_watermark.c

1754

skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1768

return skl_compute_wm_params(crtc_state, width,

drivers/gpu/drm/i915/display/skl_watermark.c

1771

intel_plane_pixel_rate(crtc_state, plane_state),

drivers/gpu/drm/i915/display/skl_watermark.c

1800

static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1808

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1814

(use_minimal_wm0_only(crtc_state, plane) && level > 0)) {

drivers/gpu/drm/i915/display/skl_watermark.c

1823

crtc_state->hw.pipe_mode.crtc_htotal,

drivers/gpu/drm/i915/display/skl_watermark.c

1832

if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /

drivers/gpu/drm/i915/display/skl_watermark.c

1944

skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1949

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1957

skl_compute_plane_wm(crtc_state, plane, level, latency,

drivers/gpu/drm/i915/display/skl_watermark.c

1964

static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1969

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

1978

skl_compute_plane_wm(crtc_state, plane, 0, latency,

drivers/gpu/drm/i915/display/skl_watermark.c

2046

static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2050

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2051

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];

drivers/gpu/drm/i915/display/skl_watermark.c

2055

ret = skl_compute_plane_wm_params(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2060

skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);

drivers/gpu/drm/i915/display/skl_watermark.c

2066

tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);

drivers/gpu/drm/i915/display/skl_watermark.c

2075

static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2079

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2080

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];

drivers/gpu/drm/i915/display/skl_watermark.c

2086

ret = skl_compute_plane_wm_params(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2091

skl_compute_wm_levels(crtc_state, plane, &wm_params, uv_wm);

drivers/gpu/drm/i915/display/skl_watermark.c

2103

static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2108

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2114

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2117

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2123

ret = skl_build_plane_wm_uv(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2132

static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2138

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2151

!intel_wm_plane_visible(crtc_state, plane_state));

drivers/gpu/drm/i915/display/skl_watermark.c

2155

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2160

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2164

} else if (intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/skl_watermark.c

2165

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2174

unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2176

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2177

struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->primary);

drivers/gpu/drm/i915/display/skl_watermark.c

2178

const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/skl_watermark.c

2199

pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state),

drivers/gpu/drm/i915/display/skl_watermark.c

2204

width = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_hscale(crtc_state),

drivers/gpu/drm/i915/display/skl_watermark.c

2209

ret = skl_compute_wm_params(crtc_state, width, info,

drivers/gpu/drm/i915/display/skl_watermark.c

2216

skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);

drivers/gpu/drm/i915/display/skl_watermark.c

2225

static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2227

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

2232

const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2241

unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2243

return skl_max_wm0_lines(crtc_state) << 16;

drivers/gpu/drm/i915/display/skl_watermark.c

2251

static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2254

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2255

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

2270

if (!skl_prefill_vblank_too_short(ctx, crtc_state, latency))

drivers/gpu/drm/i915/display/skl_watermark.c

2280

static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2282

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2283

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

2287

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/skl_watermark.c

2290

skl_prefill_init(&ctx, crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2292

level = skl_max_wm_level_for_vblank(crtc_state, &ctx);

drivers/gpu/drm/i915/display/skl_watermark.c

2300

crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;

drivers/gpu/drm/i915/display/skl_watermark.c

2314

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2326

skl_prefill_vblank_too_short(&ctx, crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2332

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2346

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

2362

ret = icl_build_plane_wm(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2364

ret = skl_build_plane_wm(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2369

crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;

drivers/gpu/drm/i915/display/skl_watermark.c

2371

return skl_wm_check_vblank(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2832

const struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2840

for_each_new_intel_crtc_in_state(state, crtc, crtc_state) {

drivers/gpu/drm/i915/display/skl_watermark.c

2841

display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;

drivers/gpu/drm/i915/display/skl_watermark.c

2842

display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);

drivers/gpu/drm/i915/display/skl_watermark.c

3035

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

304

static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

3042

memset(&crtc_state->wm.skl.optimal, 0,

drivers/gpu/drm/i915/display/skl_watermark.c

3043

sizeof(crtc_state->wm.skl.optimal));

drivers/gpu/drm/i915/display/skl_watermark.c

3044

if (crtc_state->hw.active) {

drivers/gpu/drm/i915/display/skl_watermark.c

3045

skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);

drivers/gpu/drm/i915/display/skl_watermark.c

3048

crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;

drivers/gpu/drm/i915/display/skl_watermark.c

3054

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3056

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3058

&crtc_state->wm.skl.plane_min_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

306

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3060

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3062

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/skl_watermark.c

307

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

3073

dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3082

crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;

drivers/gpu/drm/i915/display/skl_watermark.c

3083

crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;

drivers/gpu/drm/i915/display/skl_watermark.c

3087

skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

313

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

335

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

348

static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

350

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

355

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

364

bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

366

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3760

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3763

entries[crtc->pipe] = crtc_state->wm.skl.ddb;

drivers/gpu/drm/i915/display/skl_watermark.c

3767

const struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3776

if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,

drivers/gpu/drm/i915/display/skl_watermark.c

379

if (crtc_state->inherited)

drivers/gpu/drm/i915/display/skl_watermark.c

3808

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3814

drm_WARN_ON(display->drm, crtc_state->active_planes != 0);

drivers/gpu/drm/i915/display/skl_watermark.c

3816

memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

382

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/skl_watermark.c

3829

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3845

memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

385

if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)

drivers/gpu/drm/i915/display/skl_watermark.c

3852

struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3858

skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

3859

skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[plane->id], 0, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

3861

crtc_state->wm.skl.plane_min_ddb[plane->id] = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

3862

crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

3864

memset(&crtc_state->wm.skl.raw.planes[plane->id], 0,

drivers/gpu/drm/i915/display/skl_watermark.c

3865

sizeof(crtc_state->wm.skl.raw.planes[plane->id]));

drivers/gpu/drm/i915/display/skl_watermark.c

3866

memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0,

drivers/gpu/drm/i915/display/skl_watermark.c

3867

sizeof(crtc_state->wm.skl.optimal.planes[plane->id]));

drivers/gpu/drm/i915/display/skl_watermark.c

389

return tgl_crtc_can_enable_sagv(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

391

return skl_crtc_can_enable_sagv(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

467

static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/skl_watermark.c

469

const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

drivers/gpu/drm/i915/display/skl_watermark.c

472

if (!crtc_state->hw.active)

drivers/gpu/drm/i915/display/skl_watermark.c

530

struct intel_crtc_state *crtc_state;

drivers/gpu/drm/i915/display/skl_watermark.c

570

crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

drivers/gpu/drm/i915/display/skl_watermark.c

571

if (IS_ERR(crtc_state))

drivers/gpu/drm/i915/display/skl_watermark.c

572

return PTR_ERR(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

578

crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;

drivers/gpu/drm/i915/display/skl_watermark.c

579

crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;

drivers/gpu/drm/i915/display/skl_watermark.c

592

static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

598

static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

629

skl_cursor_allocation(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.c

632

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.c

633

struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);

drivers/gpu/drm/i915/display/skl_watermark.c

648

ret = skl_compute_wm_params(crtc_state, mode_config->cursor_width,

drivers/gpu/drm/i915/display/skl_watermark.c

650

crtc_state->pixel_rate, &wp, 0, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

656

skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);

drivers/gpu/drm/i915/display/skl_watermark.h

27

bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.h

58

unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/skl_watermark.h

82

unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/skl_watermark.h

83

unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/vlv_dsi.c

1756

int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/vlv_dsi.c

1758

struct intel_display *display = to_intel_display(crtc_state);

drivers/gpu/drm/i915/display/vlv_dsi.c

1760

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

drivers/gpu/drm/i915/display/vlv_dsi.c

611

const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/vlv_dsi.c

614

struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/vlv_dsi.c

820

const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/vlv_dsi.c

823

intel_crtc_vblank_on(crtc_state);

drivers/gpu/drm/i915/display/vlv_dsi.h

16

int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/vlv_dsi.h

22

static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/imx/dc/dc-crtc.c

113

static void dc_crtc_queue_state_event(struct drm_crtc_state *crtc_state)

drivers/gpu/drm/imx/dc/dc-crtc.c

115

struct drm_crtc *crtc = crtc_state->crtc;

drivers/gpu/drm/imx/dc/dc-crtc.c

119

if (crtc_state->event) {

drivers/gpu/drm/imx/dc/dc-crtc.c

122

dc_crtc->event = crtc_state->event;

drivers/gpu/drm/imx/dc/dc-crtc.c

123

crtc_state->event = NULL;

drivers/gpu/drm/imx/dc/dc-plane.c

108

crtc_state =

drivers/gpu/drm/imx/dc/dc-plane.c

110

if (WARN_ON(!crtc_state))

drivers/gpu/drm/imx/dc/dc-plane.c

113

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/imx/dc/dc-plane.c

96

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/imx/dcss/dcss-plane.c

152

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/imx/dcss/dcss-plane.c

163

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/imx/dcss/dcss-plane.c

166

hdisplay = crtc_state->adjusted_mode.hdisplay;

drivers/gpu/drm/imx/dcss/dcss-plane.c

167

vdisplay = crtc_state->adjusted_mode.vdisplay;

drivers/gpu/drm/imx/dcss/dcss-plane.c

179

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/imx/dcss/dcss-plane.c

279

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/imx/dcss/dcss-plane.c

289

crtc_state = new_state->crtc->state;

drivers/gpu/drm/imx/dcss/dcss-plane.c

292

if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state) &&

drivers/gpu/drm/imx/dcss/dcss-plane.c

334

drm_mode_vrefresh(&crtc_state->mode));

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

121

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

124

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

202

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

206

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

310

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/ipuv3/imx-ldb.c

313

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/imx-tve.c

295

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/ipuv3/imx-tve.c

298

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

231

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

235

if (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0)

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

374

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

389

crtc_state =

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

391

if (WARN_ON(!crtc_state))

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

394

ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

402

if (!crtc_state->enable)

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

432

crtc_state->mode_changed = true;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

443

crtc_state->mode_changed = true;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

474

crtc_state->mode_changed = true;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

491

crtc_state->mode_changed = true;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

498

crtc_state->mode_changed = true;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

522

crtc_state->mode_changed = true;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

583

struct drm_crtc_state *crtc_state = new_state->crtc->state;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

656

if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

809

struct drm_crtc_state *old_crtc_state, *crtc_state;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

818

for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {

drivers/gpu/drm/imx/ipuv3/parallel-display.c

139

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/ipuv3/parallel-display.c

142

struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);

drivers/gpu/drm/imx/ipuv3/parallel-display.c

150

next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/imx/ipuv3/parallel-display.c

54

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/ipuv3/parallel-display.c

96

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

191

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

277

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

279

const struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

290

crtc_state->mode_changed =

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

339

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

345

if (crtc_state->gamma_lut &&

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

346

drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) {

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

356

if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) {

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

357

f1_state = drm_atomic_get_plane_state(crtc_state->state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

362

f0_state = drm_atomic_get_plane_state(crtc_state->state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

368

ipu_state = drm_atomic_get_plane_state(crtc_state->state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

409

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

415

drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

432

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

434

struct drm_pending_vblank_event *event = crtc_state->event;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

436

if (drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

437

ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

444

crtc_state->adjusted_mode.crtc_clock * 1000);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

450

crtc_state->event = NULL;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

470

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

480

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

481

if (WARN_ON(!crtc_state))

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

488

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

520

crtc_state->mode_changed = true;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

670

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

679

crtc_state = newstate->crtc->state;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

722

if (drm_atomic_crtc_needs_modeset(crtc_state)) {

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

727

crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

730

if (crtc_state->color_mgmt_changed)

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

731

ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

736

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

740

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

810

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

813

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

848

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

866

crtc_state, conn_state,

drivers/gpu/drm/ingenic/ingenic-ipu.c

577

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/ingenic/ingenic-ipu.c

583

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/ingenic/ingenic-ipu.c

584

if (WARN_ON(!crtc_state))

drivers/gpu/drm/ingenic/ingenic-ipu.c

593

crtc_state->mode_changed = true;

drivers/gpu/drm/ingenic/ingenic-ipu.c

596

!crtc_state->mode.hdisplay || !crtc_state->mode.vdisplay)

drivers/gpu/drm/ingenic/ingenic-ipu.c

601

new_plane_state->crtc_x + new_plane_state->crtc_w > crtc_state->mode.hdisplay ||

drivers/gpu/drm/ingenic/ingenic-ipu.c

602

new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->mode.vdisplay)

drivers/gpu/drm/ingenic/ingenic-ipu.c

616

crtc_state->mode_changed = true;

drivers/gpu/drm/ingenic/ingenic-ipu.c

628

max_w = crtc_state->mode.hdisplay * 102 / 100;

drivers/gpu/drm/ingenic/ingenic-ipu.c

629

max_h = crtc_state->mode.vdisplay * 102 / 100;

drivers/gpu/drm/ingenic/ingenic-ipu.c

698

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/ingenic/ingenic-ipu.c

708

crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);

drivers/gpu/drm/ingenic/ingenic-ipu.c

709

if (WARN_ON(!crtc_state))

drivers/gpu/drm/ingenic/ingenic-ipu.c

712

crtc_state->mode_changed |= mode_changed;

drivers/gpu/drm/kmb/kmb_plane.c

103

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/kmb/kmb_plane.c

132

crtc_state =

drivers/gpu/drm/kmb/kmb_plane.c

135

crtc_state,

drivers/gpu/drm/logicvc/logicvc_layer.c

101

if (WARN_ON(!crtc_state))

drivers/gpu/drm/logicvc/logicvc_layer.c

126

ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,

drivers/gpu/drm/logicvc/logicvc_layer.c

91

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/logicvc/logicvc_layer.c

99

crtc_state = drm_atomic_get_new_crtc_state(new_state->state,

drivers/gpu/drm/loongson/lsdc_crtc.c

798

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/loongson/lsdc_crtc.c

800

if (!crtc_state->enable)

drivers/gpu/drm/loongson/lsdc_crtc.c

803

return lsdc_pixpll_atomic_check(crtc, crtc_state);

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

481

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

489

struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/loongson/lsdc_plane.c

179

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/loongson/lsdc_plane.c

200

crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);

drivers/gpu/drm/loongson/lsdc_plane.c

201

if (!crtc_state->active)

drivers/gpu/drm/loongson/lsdc_plane.c

215

crtc_state,

drivers/gpu/drm/mediatek/mtk_crtc.c

690

struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

693

unsigned int encoder_mask = crtc_state->encoder_mask;

drivers/gpu/drm/mediatek/mtk_crtc.c

695

if (!crtc_state->connectors_changed)

drivers/gpu/drm/mediatek/mtk_crtc.c

705

crtc_state->connectors_changed, encoder_mask, crtc_index);

drivers/gpu/drm/mediatek/mtk_crtc.c

849

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/mediatek/mtk_crtc.c

851

struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);

drivers/gpu/drm/mediatek/mtk_dp.c

2478

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mediatek/mtk_dp.c

2501

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mediatek/mtk_dp.c

2508

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/mediatek/mtk_dp.c

2546

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mediatek/mtk_dp.c

2570

drm_display_mode_to_videomode(&crtc_state->adjusted_mode, &mtk_dp->info.vm);

drivers/gpu/drm/mediatek/mtk_dpi.c

699

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mediatek/mtk_dpi.c

728

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mediatek/mtk_dpi.c

809

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mediatek/mtk_plane.c

104

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/mediatek/mtk_plane.c

107

return drm_atomic_helper_check_plane_state(plane->state, crtc_state,

drivers/gpu/drm/mediatek/mtk_plane.c

236

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/mediatek/mtk_plane.c

250

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/mediatek/mtk_plane.c

252

if (IS_ERR(crtc_state))

drivers/gpu/drm/mediatek/mtk_plane.c

253

return PTR_ERR(crtc_state);

drivers/gpu/drm/mediatek/mtk_plane.c

256

crtc_state,

drivers/gpu/drm/mediatek/mtk_plane.c

87

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/meson/meson_crtc.c

103

writel(crtc_state->mode.hdisplay |

drivers/gpu/drm/meson/meson_crtc.c

104

crtc_state->mode.vdisplay << 16,

drivers/gpu/drm/meson/meson_crtc.c

108

(crtc_state->mode.hdisplay - 1),

drivers/gpu/drm/meson/meson_crtc.c

111

(crtc_state->mode.vdisplay - 1),

drivers/gpu/drm/meson/meson_crtc.c

113

writel_relaxed(crtc_state->mode.hdisplay << 16 |

drivers/gpu/drm/meson/meson_crtc.c

114

crtc_state->mode.vdisplay,

drivers/gpu/drm/meson/meson_crtc.c

124

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/meson/meson_crtc.c

129

if (!crtc_state) {

drivers/gpu/drm/meson/meson_crtc.c

135

writel(crtc_state->mode.hdisplay,

drivers/gpu/drm/meson/meson_crtc.c

88

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/meson/meson_crtc.c

93

if (!crtc_state) {

drivers/gpu/drm/meson/meson_encoder_cvbs.c

132

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/meson/meson_encoder_cvbs.c

135

if (meson_cvbs_get_mode(&crtc_state->mode))

drivers/gpu/drm/meson/meson_encoder_cvbs.c

148

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/meson/meson_encoder_cvbs.c

159

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/meson/meson_encoder_cvbs.c

160

if (WARN_ON(!crtc_state))

drivers/gpu/drm/meson/meson_encoder_cvbs.c

163

meson_mode = meson_cvbs_get_mode(&crtc_state->adjusted_mode);

drivers/gpu/drm/meson/meson_encoder_dsi.c

50

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/meson/meson_encoder_dsi.c

61

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/meson/meson_encoder_dsi.c

62

if (WARN_ON(!crtc_state))

drivers/gpu/drm/meson/meson_encoder_dsi.c

67

meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

199

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/meson/meson_encoder_hdmi.c

212

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/meson/meson_encoder_hdmi.c

213

if (WARN_ON(!crtc_state))

drivers/gpu/drm/meson/meson_encoder_hdmi.c

216

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/meson/meson_encoder_hdmi.c

276

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/meson/meson_encoder_hdmi.c

306

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/meson/meson_encoder_hdmi.c

319

crtc_state->mode_changed = true;

drivers/gpu/drm/meson/meson_overlay.c

174

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/meson/meson_overlay.c

179

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/meson/meson_overlay.c

181

if (IS_ERR(crtc_state))

drivers/gpu/drm/meson/meson_overlay.c

182

return PTR_ERR(crtc_state);

drivers/gpu/drm/meson/meson_overlay.c

185

crtc_state,

drivers/gpu/drm/meson/meson_overlay.c

233

struct drm_crtc_state *crtc_state = priv->crtc->state;

drivers/gpu/drm/meson/meson_overlay.c

251

if (!crtc_state) {

drivers/gpu/drm/meson/meson_overlay.c

256

crtc_height = crtc_state->mode.vdisplay;

drivers/gpu/drm/meson/meson_overlay.c

257

crtc_width = crtc_state->mode.hdisplay;

drivers/gpu/drm/meson/meson_plane.c

80

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/meson/meson_plane.c

85

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/meson/meson_plane.c

87

if (IS_ERR(crtc_state))

drivers/gpu/drm/meson/meson_plane.c

88

return PTR_ERR(crtc_state);

drivers/gpu/drm/meson/meson_plane.c

96

crtc_state,

drivers/gpu/drm/mgag200/mgag200_drv.h

412

void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200.c

145

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200.c

146

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200eh.c

98

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200eh.c

99

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200er.c

126

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200er.c

127

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200er.c

190

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200er.c

191

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/mgag200/mgag200_g200er.c

192

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200er.c

203

if (crtc_state->gamma_lut)

drivers/gpu/drm/mgag200/mgag200_g200er.c

204

mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);

drivers/gpu/drm/mgag200/mgag200_g200ev.c

105

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200ev.c

106

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200ev.c

191

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200ev.c

192

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/mgag200/mgag200_g200ev.c

193

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200ev.c

204

if (crtc_state->gamma_lut)

drivers/gpu/drm/mgag200/mgag200_g200ev.c

205

mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);

drivers/gpu/drm/mgag200/mgag200_g200se.c

183

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200se.c

184

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200se.c

284

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200se.c

285

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200se.c

329

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200se.c

330

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/mgag200/mgag200_g200se.c

331

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_g200se.c

342

if (crtc_state->gamma_lut)

drivers/gpu/drm/mgag200/mgag200_g200se.c

343

mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);

drivers/gpu/drm/mgag200/mgag200_g200wb.c

97

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_g200wb.c

98

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

636

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_mode.c

637

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

641

if (crtc_state->enable && crtc_state->color_mgmt_changed) {

drivers/gpu/drm/mgag200/mgag200_mode.c

644

if (crtc_state->gamma_lut)

drivers/gpu/drm/mgag200/mgag200_mode.c

645

mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);

drivers/gpu/drm/mgag200/mgag200_mode.c

656

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_mode.c

657

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/mgag200/mgag200_mode.c

658

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

667

if (crtc_state->gamma_lut)

drivers/gpu/drm/mgag200/mgag200_mode.c

668

mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);

drivers/gpu/drm/mgag200/mgag200_mode.c

698

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/mgag200/mgag200_mode.c

699

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

702

if (!crtc_state)

drivers/gpu/drm/mgag200/mgag200_mode.c

718

void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)

drivers/gpu/drm/mgag200/mgag200_mode.c

720

struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

105

static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

110

for (i = 0; i < crtc_state->num_mixers; ++i) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

111

m = &crtc_state->mixers[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1324

static int dpu_crtc_assign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1327

struct drm_atomic_commit *state = crtc_state->state;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

133

struct dpu_crtc_state *crtc_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1333

global_state = dpu_kms_get_global_state(crtc_state->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1337

if (!crtc_state->enable)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1344

drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1363

static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1367

global_state = dpu_kms_get_global_state(crtc_state->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1373

return dpu_crtc_assign_planes(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1382

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1384

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1388

drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1389

dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1390

&crtc_state->adjusted_mode);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1392

topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1426

if (crtc_state->ctm || crtc_state->gamma_lut)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1433

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1448

global_state = dpu_kms_get_global_state(crtc_state->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1454

if (!crtc_state->enable)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1457

topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1459

crtc_state->crtc, &topology);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1463

cstate = to_dpu_crtc_state(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1466

crtc_state->crtc,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1470

crtc_state->crtc,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1474

crtc_state->crtc,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

151

crtc_state = to_dpu_crtc_state(crtc->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1525

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1528

struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1535

bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1538

if (crtc_state->mode_changed || crtc_state->connectors_changed ||

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1539

crtc_state->color_mgmt_changed) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

154

current_source = crtc_state->crc_source;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1540

rc = dpu_crtc_assign_resources(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1545

if (crtc_state->planes_changed || crtc_state->zpos_changed) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1547

rc = dpu_crtc_reassign_planes(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1549

rc = dpu_crtc_assign_planes(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1554

if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1556

crtc->base.id, crtc_state->enable,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1557

crtc_state->active);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1565

rc = _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1571

drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1589

rc = dpu_core_perf_crtc_check(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

170

crtc_state->crc_source = source;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

173

crtc_state->crc_frame_skip_count = 0;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

176

dpu_crtc_setup_lm_misr(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

200

struct dpu_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

208

BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

210

for (i = 0; i < crtc_state->num_mixers; ++i) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

212

m = &crtc_state->mixers[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

254

struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

257

if (crtc_state->crc_frame_skip_count < 2) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

258

crtc_state->crc_frame_skip_count++;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

262

if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

263

return dpu_crtc_get_lm_crc(crtc, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

264

else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

375

struct dpu_crtc_state *crtc_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

378

crtc_state = to_dpu_crtc_state(crtc->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

380

for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

381

const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

382

struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

84

struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

92

*values_cnt = crtc_state->num_mixers;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1153

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1181

is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) &&

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1270

phys->cached_mode = crtc_state->adjusted_mode;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1272

phys->ops.atomic_mode_set(phys, crtc_state, conn_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

99

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

151

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

388

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

410

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1053

const struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1071

&crtc_state->adjusted_mode,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1180

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1186

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1189

ret = dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1208

crtc_state->planes_changed = true;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1255

const struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1278

ret = dpu_plane_split(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1309

return dpu_plane_atomic_check_sspp(plane, state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1316

const struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1332

ret = dpu_plane_split(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1348

return dpu_plane_atomic_check_sspp(plane, state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1358

const struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1370

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1376

crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1380

crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

817

const struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

827

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

866

pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

873

const struct drm_crtc_state *crtc_state)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

881

const struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

889

num_lm = dpu_crtc_get_num_lm(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

37

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

55

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

56

if (IS_ERR(crtc_state))

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

57

return PTR_ERR(crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

59

mode = &crtc_state->mode;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

695

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

697

struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

705

const struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

714

drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

752

ret = mdp5_crtc_setup_pipeline(crtc, crtc_state, need_right_mixer);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

765

start = get_start_stage(crtc, crtc_state, &pstates[0].state->base);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

217

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

221

struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

236

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

161

static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

209

ret = drm_atomic_helper_check_plane_state(state, crtc_state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

333

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

339

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

340

if (WARN_ON(!crtc_state))

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

343

return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

371

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

375

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

377

if (WARN_ON(!crtc_state))

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

380

if (!crtc_state->active)

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

400

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/msm/dp/dp_drm.c

74

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/msm/dp/dp_drm.c

84

if (!conn_state->crtc || !crtc_state)

drivers/gpu/drm/msm/dp/dp_drm.c

87

if (crtc_state->self_refresh_active && !dp->psr_supported)

drivers/gpu/drm/msm/hdmi/hdmi_bridge.c

294

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/msm/hdmi/hdmi_bridge.c

300

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/msm/hdmi/hdmi_bridge.c

304

msm_hdmi_set_timings(hdmi, &crtc_state->adjusted_mode);

drivers/gpu/drm/msm/msm_atomic.c

144

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/msm/msm_atomic.c

155

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/msm/msm_atomic.c

156

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/msm/msm_atomic.c

158

if (!crtc_state->active)

drivers/gpu/drm/msm/msm_atomic.c

174

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/msm/msm_atomic.c

178

for_each_new_crtc_in_state(state, crtc, crtc_state, i)

drivers/gpu/drm/mxsfb/lcdif_kms.c

402

static void lcdif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

405

struct lcdif_crtc_state *lcdif_crtc_state = to_lcdif_crtc_state(crtc_state);

drivers/gpu/drm/mxsfb/lcdif_kms.c

406

struct drm_device *drm = crtc_state->crtc->dev;

drivers/gpu/drm/mxsfb/lcdif_kms.c

408

struct drm_display_mode *m = &crtc_state->adjusted_mode;

drivers/gpu/drm/mxsfb/lcdif_kms.c

428

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

430

struct lcdif_crtc_state *lcdif_crtc_state = to_lcdif_crtc_state(crtc_state);

drivers/gpu/drm/mxsfb/lcdif_kms.c

431

bool has_primary = crtc_state->plane_mask &

drivers/gpu/drm/mxsfb/lcdif_kms.c

442

if (crtc_state->active && !has_primary)

drivers/gpu/drm/mxsfb/lcdif_kms.c

672

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/mxsfb/lcdif_kms.c

674

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

677

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

315

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

317

bool has_primary = crtc_state->plane_mask &

drivers/gpu/drm/mxsfb/mxsfb_kms.c

321

if (crtc_state->active && !has_primary)

drivers/gpu/drm/mxsfb/mxsfb_kms.c

528

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/mxsfb/mxsfb_kms.c

530

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

533

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/nouveau/dispnv04/crtc.c

676

struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

687

crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

689

crtc_state->gpio_ext = crtc_saved->gpio_ext;

drivers/gpu/drm/nouveau/dispnv50/crc.c

241

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/nouveau/dispnv50/crc.c

245

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/nouveau/dispnv50/crc.c

247

struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/crc.c

320

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/nouveau/dispnv50/crc.c

324

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/nouveau/dispnv50/crc.c

326

struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/crc.c

553

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/nouveau/dispnv50/crc.c

586

crtc_state = drm_atomic_get_crtc_state(state, &head->base.base);

drivers/gpu/drm/nouveau/dispnv50/crc.c

587

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/nouveau/dispnv50/crc.c

588

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/crc.c

594

asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/disp.c

1959

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/nouveau/dispnv50/disp.c

1962

int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);

drivers/gpu/drm/nouveau/dispnv50/disp.c

1965

crtc_state->adjusted_mode.clock *= 2;

drivers/gpu/drm/nouveau/dispnv50/disp.c

332

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/nouveau/dispnv50/disp.c

336

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/nouveau/dispnv50/disp.c

337

struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/nouveau/dispnv50/disp.c

371

crtc_state->mode_changed = true;

drivers/gpu/drm/nouveau/dispnv50/disp.c

378

nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)

drivers/gpu/drm/nouveau/dispnv50/disp.c

380

struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/disp.c

408

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/nouveau/dispnv50/disp.c

413

struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/disp.c

416

ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,

drivers/gpu/drm/nouveau/dispnv50/disp.c

421

if (crtc_state->mode_changed || crtc_state->connectors_changed)

drivers/gpu/drm/nouveau/dispnv50/disp.c

425

nv50_outp_atomic_fix_depth(encoder, crtc_state);

drivers/gpu/drm/nouveau/dispnv50/disp.c

466

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/nouveau/dispnv50/disp.c

470

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/nouveau/dispnv50/disp.c

471

if (crtc_state->encoder_mask & mask)

drivers/gpu/drm/nouveau/dispnv50/disp.c

964

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/nouveau/dispnv50/disp.c

967

struct drm_atomic_commit *state = crtc_state->state;

drivers/gpu/drm/nouveau/dispnv50/disp.c

972

struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/nouveau/dispnv50/disp.c

976

ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,

drivers/gpu/drm/nouveau/dispnv50/disp.c

981

if (!drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/nouveau/dispnv50/disp.c

990

const int clock = crtc_state->adjusted_mode.clock;

drivers/gpu/drm/nouveau/dispnv50/head.c

337

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/nouveau/dispnv50/head.c

342

struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

350

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/omapdrm/dss/hdmi4.c

365

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/omapdrm/dss/hdmi4.c

366

if (WARN_ON(!crtc_state))

drivers/gpu/drm/omapdrm/dss/hdmi4.c

376

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/omapdrm/dss/hdmi5.c

348

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/omapdrm/dss/hdmi5.c

363

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/omapdrm/dss/hdmi5.c

364

if (WARN_ON(!crtc_state))

drivers/gpu/drm/omapdrm/dss/hdmi5.c

374

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/omapdrm/omap_crtc.c

582

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/omapdrm/omap_crtc.c

586

if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) {

drivers/gpu/drm/omapdrm/omap_crtc.c

587

unsigned int length = crtc_state->degamma_lut->length /

drivers/gpu/drm/omapdrm/omap_crtc.c

598

to_omap_crtc_state(crtc_state);

drivers/gpu/drm/omapdrm/omap_plane.c

211

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/omapdrm/omap_plane.c

233

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/omapdrm/omap_plane.c

235

if (WARN_ON(!crtc_state))

drivers/gpu/drm/omapdrm/omap_plane.c

244

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/omapdrm/omap_plane.c

264

if (new_plane_state->crtc_x + new_plane_state->crtc_w > crtc_state->adjusted_mode.hdisplay)

drivers/gpu/drm/omapdrm/omap_plane.c

267

if (new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->adjusted_mode.vdisplay)

drivers/gpu/drm/panel/panel-novatek-nt35950.c

236

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/panel/panel-novatek-nt35950.c

243

crtc_state = connector->state->crtc->state;

drivers/gpu/drm/panel/panel-novatek-nt35950.c

246

if (drm_mode_match(&crtc_state->mode,

drivers/gpu/drm/qxl/qxl_display.c

388

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/qxl/qxl_display.c

395

event = crtc_state->event;

drivers/gpu/drm/qxl/qxl_display.c

396

crtc_state->event = NULL;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

1105

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

1129

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

1130

if (!IS_ERR(crtc_state)) {

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

1133

rcrtc_state = to_rcar_crtc_state(crtc_state);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

1139

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

694

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

696

struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc_state);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

700

ret = rcar_du_cmm_check(crtc, crtc_state);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

708

crtc_state->encoder_mask) {

drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c

525

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c

535

for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {

drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c

537

to_rcar_crtc_state(crtc_state);

drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c

597

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c

611

crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);

drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c

612

if (IS_ERR(crtc_state))

drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c

613

return PTR_ERR(crtc_state);

drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c

615

ret = drm_atomic_helper_check_plane_state(state, crtc_state,

drivers/gpu/drm/renesas/rcar-du/rcar_du_writeback.c

143

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/renesas/rcar-du/rcar_du_writeback.c

148

const struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c

429

const struct drm_crtc_state *crtc_state =

drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c

432

&crtc_state->adjusted_mode;

drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c

180

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c

194

crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);

drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c

195

if (IS_ERR(crtc_state))

drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c

196

return PTR_ERR(crtc_state);

drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c

198

ret = drm_atomic_helper_check_plane_state(state, crtc_state,

drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c

150

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c

165

crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);

drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c

166

if (IS_ERR(crtc_state))

drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c

167

return PTR_ERR(crtc_state);

drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c

169

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

281

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

284

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/cdn-dp-core.c

663

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/cdn-dp-core.c

666

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

772

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

775

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c

241

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c

244

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/dw_dp-rockchip.c

34

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/dw_dp-rockchip.c

37

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

314

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

317

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

136

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

140

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c

69

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c

72

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

401

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/rockchip/rk3066_hdmi.c

408

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

409

if (WARN_ON(!crtc_state))

drivers/gpu/drm/rockchip/rk3066_hdmi.c

446

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/rk3066_hdmi.c

449

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1084

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1095

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1099

if (!crtc_state)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1100

crtc_state = plane->crtc->state;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1102

return drm_atomic_helper_check_plane_state(plane->state, crtc_state,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1347

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1357

if (crtc_state->color_mgmt_changed &&

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1358

!crtc_state->active_changed)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1520

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1528

if (vop->lut_regs && crtc_state->color_mgmt_changed &&

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1529

crtc_state->gamma_lut) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1532

len = drm_color_lut_size(crtc_state->gamma_lut);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1540

drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1542

drm_atomic_get_plane_state(crtc_state->state, plane);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1558

s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1661

struct rockchip_crtc_state *crtc_state = kzalloc_obj(*crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1666

if (crtc_state)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1667

__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

817

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

830

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

831

if (WARN_ON(!crtc_state))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

834

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1502

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1507

if (!crtc_state->gamma_lut) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1521

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1524

vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1631

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1683

drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1764

drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1808

vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1818

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1823

if (!vp->vop2->lut_regs || !crtc_state->color_mgmt_changed ||

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1824

!crtc_state->gamma_lut)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1827

len = drm_color_lut_size(crtc_state->gamma_lut);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1848

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1851

ret = vop2_crtc_atomic_check_gamma(vp, crtc, state, crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1855

drm_atomic_crtc_state_for_each_plane(plane, crtc_state)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1876

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1881

if (!drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state->color_mgmt_changed)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1882

vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state);

drivers/gpu/drm/rockchip/rockchip_lvds.c

128

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/rockchip_lvds.c

131

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/rockchip/rockchip_rgb.c

36

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/rockchip/rockchip_rgb.c

39

struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);

drivers/gpu/drm/sitronix/st7920.c

349

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/sitronix/st7920.c

355

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/sitronix/st7920.c

357

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/sitronix/st7920.c

395

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sitronix/st7920.c

396

struct st7920_crtc_state *st7920_crtc_state = to_st7920_crtc_state(crtc_state);

drivers/gpu/drm/sitronix/st7920.c

437

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sitronix/st7920.c

444

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sitronix/st7920.c

445

st7920_crtc_state = to_st7920_crtc_state(crtc_state);

drivers/gpu/drm/sitronix/st7920.c

527

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/sitronix/st7920.c

528

struct st7920_crtc_state *st7920_state = to_st7920_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1085

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/solomon/ssd130x.c

1091

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/solomon/ssd130x.c

1093

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1134

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/solomon/ssd130x.c

1140

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/solomon/ssd130x.c

1142

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1179

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/solomon/ssd130x.c

1183

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/solomon/ssd130x.c

1185

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1203

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1204

struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1244

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1245

struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1285

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1286

struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1324

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/solomon/ssd130x.c

1331

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1332

ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1348

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/solomon/ssd130x.c

1355

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1356

ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1372

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/solomon/ssd130x.c

1379

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1380

ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1483

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/solomon/ssd130x.c

1484

struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1504

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/solomon/ssd130x.c

1505

struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/solomon/ssd130x.c

1525

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/solomon/ssd130x.c

1526

struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);

drivers/gpu/drm/sprd/sprd_dpu.c

508

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sprd/sprd_dpu.c

518

crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);

drivers/gpu/drm/sprd/sprd_dpu.c

519

if (IS_ERR(crtc_state))

drivers/gpu/drm/sprd/sprd_dpu.c

520

return PTR_ERR(crtc_state);

drivers/gpu/drm/sprd/sprd_dpu.c

522

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/sti/sti_cursor.c

194

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sti/sti_cursor.c

203

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/sti/sti_cursor.c

204

if (IS_ERR(crtc_state))

drivers/gpu/drm/sti/sti_cursor.c

205

return PTR_ERR(crtc_state);

drivers/gpu/drm/sti/sti_cursor.c

207

mode = &crtc_state->mode;

drivers/gpu/drm/sti/sti_gdp.c

629

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sti/sti_gdp.c

641

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/sti/sti_gdp.c

642

if (IS_ERR(crtc_state))

drivers/gpu/drm/sti/sti_gdp.c

643

return PTR_ERR(crtc_state);

drivers/gpu/drm/sti/sti_gdp.c

645

mode = &crtc_state->mode;

drivers/gpu/drm/sti/sti_hqvdp.c

1031

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sti/sti_hqvdp.c

1040

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/sti/sti_hqvdp.c

1041

if (IS_ERR(crtc_state))

drivers/gpu/drm/sti/sti_hqvdp.c

1042

return PTR_ERR(crtc_state);

drivers/gpu/drm/sti/sti_hqvdp.c

1044

mode = &crtc_state->mode;

drivers/gpu/drm/stm/lvds.c

894

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/stm/lvds.c

912

crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/stm/lvds.c

913

if (IS_ERR(crtc_state))

drivers/gpu/drm/stm/lvds.c

914

return PTR_ERR(crtc_state);

drivers/gpu/drm/stm/lvds.c

916

if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||

drivers/gpu/drm/stm/lvds.c

917

crtc_state->mode.vdisplay != panel_mode->vdisplay)

drivers/gpu/drm/stm/lvds.c

921

drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);

drivers/gpu/drm/sun4i/sun4i_backend.c

471

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/sun4i/sun4i_backend.c

475

struct drm_atomic_commit *state = crtc_state->state;

drivers/gpu/drm/sun4i/sun4i_backend.c

488

if (!crtc_state->planes_changed)

drivers/gpu/drm/sun4i/sun4i_backend.c

491

drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {

drivers/gpu/drm/sun4i/sun4i_crtc.c

51

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/sun4i/sun4i_crtc.c

58

ret = engine->ops->atomic_check(engine, crtc_state);

drivers/gpu/drm/sun4i/sun4i_tv.c

283

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/sun4i/sun4i_tv.c

285

struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/sun4i/sun8i_ui_layer.c

155

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sun4i/sun8i_ui_layer.c

163

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/sun4i/sun8i_ui_layer.c

164

if (WARN_ON(!crtc_state))

drivers/gpu/drm/sun4i/sun8i_ui_layer.c

183

crtc_state,

drivers/gpu/drm/sun4i/sun8i_vi_layer.c

235

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sun4i/sun8i_vi_layer.c

243

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/sun4i/sun8i_vi_layer.c

244

if (WARN_ON(!crtc_state))

drivers/gpu/drm/sun4i/sun8i_vi_layer.c

263

crtc_state,

drivers/gpu/drm/sysfb/drm_sysfb_helper.h

176

void drm_sysfb_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

247

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

261

crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, plane_state->crtc);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

262

if (drm_WARN_ON_ONCE(dev, !crtc_state))

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

264

sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

339

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

340

struct drm_sysfb_crtc_state *sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

539

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

543

if (drm_WARN_ON(dev, !crtc_state))

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

550

sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

559

void drm_sysfb_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

561

drm_sysfb_crtc_state_destroy(to_drm_sysfb_crtc_state(crtc_state));

drivers/gpu/drm/sysfb/ofdrm.c

733

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/sysfb/ofdrm.c

734

struct drm_sysfb_crtc_state *sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);

drivers/gpu/drm/sysfb/ofdrm.c

736

if (crtc_state->enable && crtc_state->color_mgmt_changed) {

drivers/gpu/drm/sysfb/ofdrm.c

739

if (crtc_state->gamma_lut)

drivers/gpu/drm/sysfb/ofdrm.c

740

ofdrm_device_load_gamma(odev, format, crtc_state->gamma_lut->data);

drivers/gpu/drm/sysfb/vesadrm.c

325

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/sysfb/vesadrm.c

326

struct drm_sysfb_crtc_state *sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);

drivers/gpu/drm/sysfb/vesadrm.c

332

if (crtc_state->enable && crtc_state->color_mgmt_changed) {

drivers/gpu/drm/sysfb/vesadrm.c

343

crtc_state->gamma_lut->data);

drivers/gpu/drm/sysfb/vesadrm.c

353

if (crtc_state->gamma_lut)

drivers/gpu/drm/sysfb/vesadrm.c

356

crtc_state->gamma_lut->data);

drivers/gpu/drm/tegra/dc.c

1132

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tegra/dc.c

1136

crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);

drivers/gpu/drm/tegra/dc.c

1137

if (WARN_ON(!crtc_state))

drivers/gpu/drm/tegra/dc.c

1140

if (!crtc_state->active)

drivers/gpu/drm/tegra/dc.c

1155

err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale,

drivers/gpu/drm/tegra/dc.c

1963

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tegra/dc.c

1967

struct tegra_dc_state *state = to_dc_state(crtc_state);

drivers/gpu/drm/tegra/dc.c

2263

struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);

drivers/gpu/drm/tegra/dc.c

2269

tegra_dc_set_clock_rate(dc, crtc_state);

drivers/gpu/drm/tegra/dc.c

2347

value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1;

drivers/gpu/drm/tegra/dc.c

2414

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/tegra/dc.c

2416

struct tegra_dc_state *dc_state = to_dc_state(crtc_state);

drivers/gpu/drm/tegra/dc.h

168

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tegra/dsi.c

1025

err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,

drivers/gpu/drm/tegra/dsi.c

956

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tegra/dsi.c

967

state->pclk = crtc_state->mode.clock * 1000;

drivers/gpu/drm/tegra/dsi.c

979

state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);

drivers/gpu/drm/tegra/hdmi.c

1443

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tegra/hdmi.c

1448

unsigned long pclk = crtc_state->mode.clock * 1000;

drivers/gpu/drm/tegra/hdmi.c

1452

err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,

drivers/gpu/drm/tegra/plane.c

231

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tegra/plane.c

237

crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);

drivers/gpu/drm/tegra/plane.c

238

if (!crtc_state)

drivers/gpu/drm/tegra/plane.c

271

avg_bandwidth *= drm_mode_vrefresh(&crtc_state->adjusted_mode);

drivers/gpu/drm/tegra/plane.c

276

peak_bandwidth = DIV_ROUND_UP(crtc_state->adjusted_mode.clock * bpp, 8);

drivers/gpu/drm/tegra/plane.c

300

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tegra/plane.c

305

crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);

drivers/gpu/drm/tegra/plane.c

306

if (IS_ERR(crtc_state))

drivers/gpu/drm/tegra/plane.c

307

return PTR_ERR(crtc_state);

drivers/gpu/drm/tegra/plane.c

310

err = drm_atomic_helper_check_plane_state(state, crtc_state,

drivers/gpu/drm/tegra/plane.c

319

tegra = to_dc_state(crtc_state);

drivers/gpu/drm/tegra/rgb.c

149

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tegra/rgb.c

154

unsigned long pclk = crtc_state->mode.clock * 1000;

drivers/gpu/drm/tegra/rgb.c

187

err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,

drivers/gpu/drm/tegra/sor.c

1808

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tegra/sor.c

1814

unsigned long pclk = crtc_state->mode.clock * 1000;

drivers/gpu/drm/tegra/sor.c

1833

err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,

drivers/gpu/drm/tests/drm_atomic_commit_test.c

151

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

167

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

168

if (IS_ERR(crtc_state))

drivers/gpu/drm/tests/drm_atomic_commit_test.c

169

return PTR_ERR(crtc_state);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

171

ret = drm_atomic_set_mode_for_crtc(crtc_state, &drm_atomic_test_mode);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

175

crtc_state->enable = true;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

176

crtc_state->active = true;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

184

crtc_state->connector_mask = DRM_TEST_CONN_0;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

257

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

259

crtc_state = kunit_kzalloc(test, sizeof(*crtc_state), GFP_KERNEL);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

260

KUNIT_ASSERT_NOT_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

262

crtc_state->encoder_mask = param->encoder_mask;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

264

ret = drm_crtc_in_clone_mode(crtc_state);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

282

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

304

crtc_state = drm_atomic_get_crtc_state(state, priv->crtc);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

305

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_atomic_commit_test.c

311

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_atomic_commit_test.c

313

crtc_state->encoder_mask = param->encoder_mask;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

316

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_atomic_commit_test.c

43

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1020

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1021

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1022

KUNIT_EXPECT_TRUE(test, crtc_state->mode_changed);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1039

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1100

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1101

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1102

KUNIT_EXPECT_FALSE(test, crtc_state->mode_changed);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1344

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1382

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1383

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1385

crtc_state->connectors_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1708

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1759

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1760

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1766

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

1768

ret = drm_atomic_set_mode_for_crtc(crtc_state, yuv420_only_mode);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2144

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2181

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2182

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2184

crtc_state->active = false;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2185

ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2533

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2574

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2575

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2581

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2583

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2637

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2679

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2680

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2686

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2688

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2741

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2792

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2793

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2799

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2807

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2852

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2906

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2907

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2913

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2930

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

294

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

2989

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3032

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3033

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3039

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3041

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3083

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3084

if (PTR_ERR(crtc_state) == -EDEADLK) {

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3090

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

3092

crtc_state->mode_changed = true;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

350

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

351

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

352

KUNIT_EXPECT_TRUE(test, crtc_state->mode_changed);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

369

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

427

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

428

KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

429

KUNIT_EXPECT_FALSE(test, crtc_state->mode_changed);

drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c

957

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_kunit_helpers.c

302

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tests/drm_kunit_helpers.c

317

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/tests/drm_kunit_helpers.c

318

if (IS_ERR(crtc_state))

drivers/gpu/drm/tests/drm_kunit_helpers.c

319

return PTR_ERR(crtc_state);

drivers/gpu/drm/tests/drm_kunit_helpers.c

321

ret = drm_atomic_set_mode_for_crtc(crtc_state, mode);

drivers/gpu/drm/tests/drm_kunit_helpers.c

325

crtc_state->enable = true;

drivers/gpu/drm/tests/drm_kunit_helpers.c

326

crtc_state->active = true;

drivers/gpu/drm/tests/drm_plane_helper_test.c

118

drm_atomic_helper_check_plane_state(plane_state, &crtc_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

15

static const struct drm_crtc_state crtc_state = {

drivers/gpu/drm/tests/drm_plane_helper_test.c

260

drm_atomic_helper_check_plane_state(plane_state, &crtc_state,

drivers/gpu/drm/tidss/tidss_crtc.c

101

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/tidss/tidss_crtc.c

110

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/tidss/tidss_crtc.c

113

return dispc_vp_bus_check(dispc, hw_videoport, crtc_state);

drivers/gpu/drm/tidss/tidss_crtc.c

88

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/tidss/tidss_crtc.c

98

if (!crtc_state->enable)

drivers/gpu/drm/tidss/tidss_encoder.c

48

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tidss/tidss_encoder.c

53

struct tidss_crtc_state *tcrtc_state = to_tidss_crtc_state(crtc_state);

drivers/gpu/drm/tidss/tidss_encoder.c

58

next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,

drivers/gpu/drm/tidss/tidss_oldi.c

229

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tidss/tidss_oldi.c

244

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/tidss/tidss_oldi.c

245

if (WARN_ON(!crtc_state))

drivers/gpu/drm/tidss/tidss_oldi.c

248

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/tidss/tidss_oldi.c

282

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tidss/tidss_plane.c

40

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tidss/tidss_plane.c

55

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/tidss/tidss_plane.c

57

if (IS_ERR(crtc_state))

drivers/gpu/drm/tidss/tidss_plane.c

58

return PTR_ERR(crtc_state);

drivers/gpu/drm/tidss/tidss_plane.c

60

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

637

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

640

if (!crtc_state->active)

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

643

return drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/tilcdc/tilcdc_plane.c

27

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tilcdc/tilcdc_plane.c

44

crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);

drivers/gpu/drm/tilcdc/tilcdc_plane.c

46

if (WARN_ON(!crtc_state))

drivers/gpu/drm/tilcdc/tilcdc_plane.c

49

if (crtc_state->mode.hdisplay != new_state->crtc_w ||

drivers/gpu/drm/tilcdc/tilcdc_plane.c

50

crtc_state->mode.vdisplay != new_state->crtc_h) {

drivers/gpu/drm/tilcdc/tilcdc_plane.c

53

crtc_state->mode.hdisplay, crtc_state->mode.vdisplay,

drivers/gpu/drm/tilcdc/tilcdc_plane.c

58

pitch = crtc_state->mode.hdisplay *

drivers/gpu/drm/tilcdc/tilcdc_plane.c

70

crtc_state->mode_changed = true;

drivers/gpu/drm/tiny/arcpgu.c

198

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tiny/bochs.c

510

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/tiny/bochs.c

512

bochs_hw_setmode(bochs, &crtc_state->mode);

drivers/gpu/drm/tiny/bochs.c

518

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tiny/bochs.c

520

if (!crtc_state->enable)

drivers/gpu/drm/tiny/bochs.c

523

return drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/tiny/bochs.c

536

struct drm_atomic_commit *crtc_state)

drivers/gpu/drm/tiny/cirrus-qemu.c

379

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tiny/cirrus-qemu.c

382

if (!crtc_state->enable)

drivers/gpu/drm/tiny/cirrus-qemu.c

385

ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/tiny/cirrus-qemu.c

396

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tiny/cirrus-qemu.c

402

cirrus_mode_set(cirrus, &crtc_state->mode);

drivers/gpu/drm/tiny/gm12u320.c

560

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tiny/pixpaper.c

802

struct drm_crtc_state *crtc_state =

drivers/gpu/drm/tiny/pixpaper.c

805

if (!crtc_state->enable)

drivers/gpu/drm/tiny/pixpaper.c

808

return drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/tiny/repaper.c

635

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/tiny/sharp-memory.c

229

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/tiny/sharp-memory.c

232

crtc_state = drm_atomic_get_new_crtc_state(state, &smd->crtc);

drivers/gpu/drm/tiny/sharp-memory.c

234

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/tiny/sharp-memory.c

291

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/tiny/sharp-memory.c

294

if (!crtc_state->enable)

drivers/gpu/drm/tiny/sharp-memory.c

297

ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state);

drivers/gpu/drm/udl/udl_modeset.c

336

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/udl/udl_modeset.c

337

struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/vboxvideo/vbox_mode.c

263

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/vboxvideo/vbox_mode.c

266

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/vboxvideo/vbox_mode.c

268

if (WARN_ON(!crtc_state))

drivers/gpu/drm/vboxvideo/vbox_mode.c

272

return drm_atomic_helper_check_plane_state(new_state, crtc_state,

drivers/gpu/drm/vboxvideo/vbox_mode.c

342

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/vboxvideo/vbox_mode.c

348

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/vboxvideo/vbox_mode.c

350

if (WARN_ON(!crtc_state))

drivers/gpu/drm/vboxvideo/vbox_mode.c

354

ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

108

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

109

if (IS_ERR(crtc_state))

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

110

return PTR_ERR(crtc_state);

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

112

ret = drm_atomic_set_mode_for_crtc(crtc_state, &default_mode);

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

116

crtc_state->active = true;

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

140

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

155

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

156

if (IS_ERR(crtc_state))

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

157

return PTR_ERR(crtc_state);

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

159

crtc_state->active = false;

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

161

ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL);

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

83

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_crtc.c

353

struct drm_crtc_state *crtc_state = crtc->state;

drivers/gpu/drm/vc4/vc4_crtc.c

354

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/vc4/vc4_crtc.c

745

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/vc4/vc4_crtc.c

747

struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);

drivers/gpu/drm/vc4/vc4_crtc.c

757

encoder = vc4_get_crtc_encoder(crtc, crtc_state);

drivers/gpu/drm/vc4/vc4_crtc.c

759

const struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/vc4/vc4_crtc.c

784

crtc_state->zpos_changed = true;

drivers/gpu/drm/vc4/vc4_dsi.c

878

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_dsi.c

912

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/vc4/vc4_dsi.c

913

mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/vc4/vc4_hdmi.c

1706

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/vc4/vc4_hdmi.c

1713

&crtc_state->adjusted_mode);

drivers/gpu/drm/vc4/vc4_hdmi.c

1770

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/vc4/vc4_hdmi.c

1774

struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/vc4/vc4_hdmi.c

282

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_hdmi.c

305

crtc_state = crtc->state;

drivers/gpu/drm/vc4/vc4_hdmi.c

306

if (!crtc_state->active)

drivers/gpu/drm/vc4/vc4_hdmi.c

473

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_hdmi.c

476

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/vc4/vc4_hdmi.c

477

if (IS_ERR(crtc_state))

drivers/gpu/drm/vc4/vc4_hdmi.c

478

return PTR_ERR(crtc_state);

drivers/gpu/drm/vc4/vc4_hdmi.c

496

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_hdmi.c

498

crtc_state = drm_atomic_get_crtc_state(state, crtc);

drivers/gpu/drm/vc4/vc4_hdmi.c

499

if (IS_ERR(crtc_state))

drivers/gpu/drm/vc4/vc4_hdmi.c

500

return PTR_ERR(crtc_state);

drivers/gpu/drm/vc4/vc4_hdmi.c

502

crtc_state->mode_changed = true;

drivers/gpu/drm/vc4/vc4_hvs.c

460

struct drm_crtc_state *crtc_state = vc4_crtc->base.state;

drivers/gpu/drm/vc4/vc4_hvs.c

461

struct drm_color_lut *lut = crtc_state->gamma_lut->data;

drivers/gpu/drm/vc4/vc4_hvs.c

462

u32 length = drm_color_lut_size(crtc_state->gamma_lut);

drivers/gpu/drm/vc4/vc4_hvs.c

792

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

793

struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);

drivers/gpu/drm/vc4/vc4_hvs.c

805

if (hweight32(crtc_state->connector_mask) > 1)

drivers/gpu/drm/vc4/vc4_hvs.c

808

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

drivers/gpu/drm/vc4/vc4_kms.c

224

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_kms.c

230

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/vc4/vc4_kms.c

232

struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);

drivers/gpu/drm/vc4/vc4_kms.c

236

if (!crtc_state->active)

drivers/gpu/drm/vc4/vc4_kms.c

267

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_kms.c

275

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/vc4/vc4_kms.c

276

struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);

drivers/gpu/drm/vc4/vc4_kms.c

343

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_kms.c

349

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/vc4/vc4_kms.c

350

struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);

drivers/gpu/drm/vc4/vc4_kms.c

362

encoder = vc4_get_crtc_encoder(crtc, crtc_state);

drivers/gpu/drm/vc4/vc4_kms.c

513

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_kms.c

522

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/vc4/vc4_kms.c

524

to_vc4_crtc_state(crtc_state);

drivers/gpu/drm/vc4/vc4_kms.c

535

drm_crtc_commit_get(crtc_state->commit);

drivers/gpu/drm/vc4/vc4_plane.c

447

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_plane.c

449

crtc_state = drm_atomic_get_new_crtc_state(pstate->state,

drivers/gpu/drm/vc4/vc4_plane.c

452

vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);

drivers/gpu/drm/vc4/vc4_plane.c

456

if (left + right >= crtc_state->mode.hdisplay ||

drivers/gpu/drm/vc4/vc4_plane.c

457

top + bottom >= crtc_state->mode.vdisplay)

drivers/gpu/drm/vc4/vc4_plane.c

460

adjhdisplay = crtc_state->mode.hdisplay - (left + right);

drivers/gpu/drm/vc4/vc4_plane.c

463

crtc_state->mode.hdisplay);

drivers/gpu/drm/vc4/vc4_plane.c

465

if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - right)

drivers/gpu/drm/vc4/vc4_plane.c

466

vc4_pstate->crtc_x = crtc_state->mode.hdisplay - right;

drivers/gpu/drm/vc4/vc4_plane.c

468

adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);

drivers/gpu/drm/vc4/vc4_plane.c

471

crtc_state->mode.vdisplay);

drivers/gpu/drm/vc4/vc4_plane.c

473

if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - bottom)

drivers/gpu/drm/vc4/vc4_plane.c

474

vc4_pstate->crtc_y = crtc_state->mode.vdisplay - bottom;

drivers/gpu/drm/vc4/vc4_plane.c

478

crtc_state->mode.hdisplay);

drivers/gpu/drm/vc4/vc4_plane.c

481

crtc_state->mode.vdisplay);

drivers/gpu/drm/vc4/vc4_plane.c

494

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_plane.c

499

crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);

drivers/gpu/drm/vc4/vc4_plane.c

500

if (!crtc_state) {

drivers/gpu/drm/vc4/vc4_plane.c

505

ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,

drivers/gpu/drm/vc4/vc4_plane.c

872

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_plane.c

876

crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);

drivers/gpu/drm/vc4/vc4_plane.c

877

vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode);

drivers/gpu/drm/vc4/vc4_txp.c

251

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vc4/vc4_txp.c

259

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/vc4/vc4_txp.c

262

if (fb->width != crtc_state->mode.hdisplay ||

drivers/gpu/drm/vc4/vc4_txp.c

263

fb->height != crtc_state->mode.vdisplay) {

drivers/gpu/drm/vc4/vc4_txp.c

281

vc4_txp_armed(crtc_state);

drivers/gpu/drm/vc4/vc4_txp.c

439

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/vc4/vc4_txp.c

447

crtc_state->no_vblank = true;

drivers/gpu/drm/vc4/vc4_vec.c

664

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/vc4/vc4_vec.c

667

const struct drm_display_mode *mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/verisilicon/vs_bridge.c

117

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/verisilicon/vs_bridge.c

128

crtc_state,

drivers/gpu/drm/verisilicon/vs_bridge.c

136

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/verisilicon/vs_bridge.c

62

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/verisilicon/vs_bridge.c

84

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

49

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

55

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

58

crtc_state,

drivers/gpu/drm/verisilicon/vs_primary_plane.c

31

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/verisilicon/vs_primary_plane.c

35

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/verisilicon/vs_primary_plane.c

38

crtc_state,

drivers/gpu/drm/virtio/virtgpu_display.c

132

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/virtio/virtgpu_display.c

142

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/virtio/virtgpu_display.c

147

event = crtc_state->event;

drivers/gpu/drm/virtio/virtgpu_display.c

148

crtc_state->event = NULL;

drivers/gpu/drm/virtio/virtgpu_plane.c

107

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/virtio/virtgpu_plane.c

121

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/virtio/virtgpu_plane.c

123

if (IS_ERR(crtc_state))

drivers/gpu/drm/virtio/virtgpu_plane.c

124

return PTR_ERR(crtc_state);

drivers/gpu/drm/virtio/virtgpu_plane.c

126

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/vkms/vkms_composer.c

115

static void apply_lut(const struct vkms_crtc_state *crtc_state, struct line_buffer *output_buffer)

drivers/gpu/drm/vkms/vkms_composer.c

117

if (!crtc_state->gamma_lut.base)

drivers/gpu/drm/vkms/vkms_composer.c

120

if (!crtc_state->gamma_lut.lut_length)

drivers/gpu/drm/vkms/vkms_composer.c

126

pixel->r = apply_lut_to_channel_value(&crtc_state->gamma_lut, pixel->r, LUT_RED);

drivers/gpu/drm/vkms/vkms_composer.c

127

pixel->g = apply_lut_to_channel_value(&crtc_state->gamma_lut, pixel->g, LUT_GREEN);

drivers/gpu/drm/vkms/vkms_composer.c

128

pixel->b = apply_lut_to_channel_value(&crtc_state->gamma_lut, pixel->b, LUT_BLUE);

drivers/gpu/drm/vkms/vkms_composer.c

472

struct vkms_crtc_state *crtc_state,

drivers/gpu/drm/vkms/vkms_composer.c

476

struct vkms_plane_state **plane = crtc_state->active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

477

u32 n_active_planes = crtc_state->num_active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

478

u64 bgcolor = crtc_state->base.background_color;

drivers/gpu/drm/vkms/vkms_composer.c

487

int crtc_y_limit = crtc_state->base.mode.vdisplay;

drivers/gpu/drm/vkms/vkms_composer.c

488

int crtc_x_limit = crtc_state->base.mode.hdisplay;

drivers/gpu/drm/vkms/vkms_composer.c

505

apply_lut(crtc_state, output_buffer);

drivers/gpu/drm/vkms/vkms_composer.c

514

static int check_format_funcs(struct vkms_crtc_state *crtc_state,

drivers/gpu/drm/vkms/vkms_composer.c

517

struct vkms_plane_state **planes = crtc_state->active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

518

u32 n_active_planes = crtc_state->num_active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

530

static int check_iosys_map(struct vkms_crtc_state *crtc_state)

drivers/gpu/drm/vkms/vkms_composer.c

532

struct vkms_plane_state **plane_state = crtc_state->active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

533

u32 n_active_planes = crtc_state->num_active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

543

struct vkms_crtc_state *crtc_state,

drivers/gpu/drm/vkms/vkms_composer.c

558

if (WARN_ON(check_iosys_map(crtc_state)))

drivers/gpu/drm/vkms/vkms_composer.c

561

if (WARN_ON(check_format_funcs(crtc_state, active_wb)))

drivers/gpu/drm/vkms/vkms_composer.c

564

line_width = crtc_state->base.mode.hdisplay;

drivers/gpu/drm/vkms/vkms_composer.c

581

blend(active_wb, crtc_state, crc32, &stage_buffer,

drivers/gpu/drm/vkms/vkms_composer.c

602

struct vkms_crtc_state *crtc_state = container_of(work,

drivers/gpu/drm/vkms/vkms_composer.c

605

struct drm_crtc *crtc = crtc_state->base.crtc;

drivers/gpu/drm/vkms/vkms_composer.c

606

struct vkms_writeback_job *active_wb = crtc_state->active_writeback;

drivers/gpu/drm/vkms/vkms_composer.c

614

frame_start = crtc_state->frame_start;

drivers/gpu/drm/vkms/vkms_composer.c

615

frame_end = crtc_state->frame_end;

drivers/gpu/drm/vkms/vkms_composer.c

616

crc_pending = crtc_state->crc_pending;

drivers/gpu/drm/vkms/vkms_composer.c

617

wb_pending = crtc_state->wb_pending;

drivers/gpu/drm/vkms/vkms_composer.c

618

crtc_state->frame_start = 0;

drivers/gpu/drm/vkms/vkms_composer.c

619

crtc_state->frame_end = 0;

drivers/gpu/drm/vkms/vkms_composer.c

620

crtc_state->crc_pending = false;

drivers/gpu/drm/vkms/vkms_composer.c

626

crtc_state->gamma_lut.base = (struct drm_color_lut *)crtc->state->gamma_lut->data;

drivers/gpu/drm/vkms/vkms_composer.c

627

crtc_state->gamma_lut.lut_length =

drivers/gpu/drm/vkms/vkms_composer.c

629

max_lut_index_fp = drm_int2fixp(crtc_state->gamma_lut.lut_length - 1);

drivers/gpu/drm/vkms/vkms_composer.c

630

crtc_state->gamma_lut.channel_value2index_ratio = drm_fixp_div(max_lut_index_fp,

drivers/gpu/drm/vkms/vkms_composer.c

634

crtc_state->gamma_lut.base = NULL;

drivers/gpu/drm/vkms/vkms_composer.c

647

ret = compose_active_planes(active_wb, crtc_state, &crc32);

drivers/gpu/drm/vkms/vkms_composer.c

649

ret = compose_active_planes(NULL, crtc_state, &crc32);

drivers/gpu/drm/vkms/vkms_composer.c

657

crtc_state->wb_pending = false;

drivers/gpu/drm/vkms/vkms_crtc.c

116

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/vkms/vkms_crtc.c

118

struct vkms_crtc_state *vkms_state = to_vkms_crtc_state(crtc_state);

drivers/gpu/drm/vkms/vkms_crtc.c

126

ret = drm_atomic_add_affected_planes(crtc_state->state, crtc);

drivers/gpu/drm/vkms/vkms_crtc.c

130

drm_for_each_plane_mask(plane, crtc->dev, crtc_state->plane_mask) {

drivers/gpu/drm/vkms/vkms_crtc.c

131

plane_state = drm_atomic_get_new_plane_state(crtc_state->state, plane);

drivers/gpu/drm/vkms/vkms_crtc.c

146

drm_for_each_plane_mask(plane, crtc->dev, crtc_state->plane_mask) {

drivers/gpu/drm/vkms/vkms_crtc.c

147

plane_state = drm_atomic_get_new_plane_state(crtc_state->state, plane);

drivers/gpu/drm/vkms/vkms_plane.c

160

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vkms/vkms_plane.c

166

crtc_state = drm_atomic_get_crtc_state(state,

drivers/gpu/drm/vkms/vkms_plane.c

168

if (IS_ERR(crtc_state))

drivers/gpu/drm/vkms/vkms_plane.c

169

return PTR_ERR(crtc_state);

drivers/gpu/drm/vkms/vkms_plane.c

171

ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,

drivers/gpu/drm/vkms/vkms_writeback.c

133

struct vkms_crtc_state *crtc_state = output->composer_state;

drivers/gpu/drm/vkms/vkms_writeback.c

135

u16 crtc_height = crtc_state->base.mode.vdisplay;

drivers/gpu/drm/vkms/vkms_writeback.c

136

u16 crtc_width = crtc_state->base.mode.hdisplay;

drivers/gpu/drm/vkms/vkms_writeback.c

150

crtc_state->active_writeback = active_wb;

drivers/gpu/drm/vkms/vkms_writeback.c

151

crtc_state->wb_pending = true;

drivers/gpu/drm/vkms/vkms_writeback.c

39

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vkms/vkms_writeback.c

50

crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

drivers/gpu/drm/vkms/vkms_writeback.c

51

mode = &crtc_state->mode;

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

699

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

706

crtc_state = drm_atomic_get_new_crtc_state(new_state->state,

drivers/gpu/drm/vmwgfx/vmwgfx_cursor_plane.c

709

ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1041

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1055

for_each_new_crtc_in_state(state, crtc, crtc_state, i) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

1056

if (drm_atomic_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

110

struct drm_crtc_state *crtc_state = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

124

crtc_state = drm_atomic_get_new_crtc_state(state,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

127

ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

869

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

871

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

872

if (crtc_state) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

880

crtc_state = crtc->state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

883

return crtc_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

902

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

911

crtc_state = vmw_crtc_state_and_lock(state, crtc);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

912

if (IS_ERR(crtc_state))

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

913

return PTR_ERR(crtc_state);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

915

if (!crtc_state || !crtc_state->enable)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

958

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

962

crtc_state = vmw_crtc_state_and_lock(state, crtc);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

963

if (IS_ERR(crtc_state)) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

964

ret = PTR_ERR(crtc_state);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

968

if (!crtc_state)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

971

if (crtc_state->enable) {

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

974

rects[i].x2 = du->gui_x + crtc_state->mode.hdisplay;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

975

rects[i].y2 = du->gui_y + crtc_state->mode.vdisplay;

drivers/gpu/drm/xen/xen_drm_front_kms.c

109

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/xen/xen_drm_front_kms.c

229

struct drm_crtc_state *crtc_state)

drivers/gpu/drm/xen/xen_drm_front_kms.c

240

crtc_state->no_vblank = false;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1553

const struct drm_crtc_state *crtc_state;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1575

crtc_state = drm_atomic_get_new_crtc_state(state, crtc);

drivers/gpu/drm/xlnx/zynqmp_dp.c

1576

adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1577

mode = &crtc_state->mode;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1651

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/xlnx/zynqmp_dp.c

1655

struct drm_display_mode *mode = &crtc_state->mode;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1656

struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1752

struct drm_crtc_state *crtc_state,

drivers/gpu/drm/xlnx/zynqmp_kms.c

60

struct drm_crtc_state *crtc_state;

drivers/gpu/drm/xlnx/zynqmp_kms.c

65

crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);

drivers/gpu/drm/xlnx/zynqmp_kms.c

66

if (IS_ERR(crtc_state))

drivers/gpu/drm/xlnx/zynqmp_kms.c

67

return PTR_ERR(crtc_state);

drivers/gpu/drm/xlnx/zynqmp_kms.c

70

crtc_state,

include/drm/bridge/dw_mipi_dsi.h

68

struct drm_crtc_state *crtc_state,

include/drm/bridge/dw_mipi_dsi2.h

78

struct drm_crtc_state *crtc_state,

include/drm/drm_atomic_helper.h

213

#define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \

include/drm/drm_atomic_helper.h

214

drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)

include/drm/drm_atomic_helper.h

231

#define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \

include/drm/drm_atomic_helper.h

232

drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) \

include/drm/drm_atomic_helper.h

234

__drm_atomic_get_current_plane_state((crtc_state)->state, \

include/drm/drm_atomic_helper.h

293

struct drm_crtc_state *crtc_state,

include/drm/drm_atomic_helper.h

55

const struct drm_crtc_state *crtc_state,

include/drm/drm_atomic_helper.h

62

int drm_atomic_helper_check_crtc_primary_plane(struct drm_crtc_state *crtc_state);

include/drm/drm_bridge.h

1554

struct drm_crtc_state *crtc_state,

include/drm/drm_bridge.h

1568

struct drm_crtc_state *crtc_state,

include/drm/drm_bridge.h

431

struct drm_crtc_state *crtc_state,

include/drm/drm_bridge.h

471

struct drm_crtc_state *crtc_state,

include/drm/drm_bridge.h

503

struct drm_crtc_state *crtc_state,

include/drm/drm_crtc.h

1355

bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state);

include/drm/drm_modeset_helper_vtables.h

674

struct drm_crtc_state *crtc_state,

include/drm/drm_modeset_helper_vtables.h

829

struct drm_crtc_state *crtc_state,

include/drm/drm_simple_kms_helper.h

24

struct drm_crtc_state *crtc_state,

include/drm/drm_simple_kms_helper.h

29

struct drm_crtc_state *crtc_state);

include/drm/drm_simple_kms_helper.h

45

struct drm_crtc_state *crtc_state);

include/drm/drm_vblank_helper.h

21

struct drm_atomic_commit *crtc_state);