games/hack/hack.mon.c

548

boolean pool;

games/hack/hack.mon.c

554

pool = (mon->data->mlet == ';');

games/hack/hack.mon.c

565

if((ntyp == POOL) == pool) {

games/hack/hack.mon.c

611

if(!cnt && pool && nowtyp != POOL) {

games/hack/hack.mon.c

612

pool = FALSE;

lib/libc/stdlib/malloc.c

1315

omalloc(struct dir_info *pool, size_t sz, int zero_fill)

lib/libc/stdlib/malloc.c

1327

p = map(pool, psz, zero_fill);

lib/libc/stdlib/malloc.c

1334

caller = pool->caller;

lib/libc/stdlib/malloc.c

1336

if (insert(pool, p, sz, caller)) {

lib/libc/stdlib/malloc.c

1337

unmap(pool, p, psz, 0);

lib/libc/stdlib/malloc.c

1344

wrterror(pool, "mprotect");

lib/libc/stdlib/malloc.c

1345

STATS_ADD(pool->malloc_guarded, mopts.malloc_guard);

lib/libc/stdlib/malloc.c

1350

if (pool->malloc_junk == 2)

lib/libc/stdlib/malloc.c

1355

if (zero_fill && pool->malloc_junk == 2)

lib/libc/stdlib/malloc.c

1358

if (pool->malloc_junk == 2) {

lib/libc/stdlib/malloc.c

1373

p = malloc_bytes(pool, sz);

lib/libc/stdlib/malloc.c

1552

struct dir_info *pool = argpool;

lib/libc/stdlib/malloc.c

1553

struct region_info *r = find(pool, p);

lib/libc/stdlib/malloc.c

1563

pool->active--;

lib/libc/stdlib/malloc.c

1564

_MALLOC_UNLOCK(pool->mutex);

lib/libc/stdlib/malloc.c

1565

pool = mopts.malloc_pool[j];

lib/libc/stdlib/malloc.c

1566

_MALLOC_LOCK(pool->mutex);

lib/libc/stdlib/malloc.c

1567

pool->active++;

lib/libc/stdlib/malloc.c

1568

r = find(pool, p);

lib/libc/stdlib/malloc.c

1570

*saved_function = pool->func;

lib/libc/stdlib/malloc.c

1571

pool->func = argpool->func;

lib/libc/stdlib/malloc.c

1578

*foundpool = pool;

lib/libc/stdlib/malloc.c

1586

struct dir_info *pool;

lib/libc/stdlib/malloc.c

1590

r = findpool(p, *argpool, &pool, &saved_function);

lib/libc/stdlib/malloc.c

1593

if (pool->mmap_flag) {

lib/libc/stdlib/malloc.c

1607

find_chunknum(pool, info, p, 0);

lib/libc/stdlib/malloc.c

1610

wrterror(pool, "recorded size %hu"

lib/libc/stdlib/malloc.c

1616

wrterror(pool, "chunk size %zu < %zu",

lib/libc/stdlib/malloc.c

1620

wrterror(pool, "recorded size %zu < %zu",

lib/libc/stdlib/malloc.c

1627

wrterror(pool, "bogus pointer %p", p);

lib/libc/stdlib/malloc.c

1629

validate_canary(pool, p,

lib/libc/stdlib/malloc.c

1635

wrterror(pool, "bogus moved pointer %p", p);

lib/libc/stdlib/malloc.c

1640

wrterror(pool, "guard size");

lib/libc/stdlib/malloc.c

1645

wrterror(pool, "mprotect");

lib/libc/stdlib/malloc.c

1647

STATS_SUB(pool->malloc_guarded, mopts.malloc_guard);

lib/libc/stdlib/malloc.c

1649

unmap(pool, p, PAGEROUND(sz), clear ? argsz : 0);

lib/libc/stdlib/malloc.c

1650

delete(pool, r);

lib/libc/stdlib/malloc.c

1658

wrterror(pool, "internal struct corrupt");

lib/libc/stdlib/malloc.c

1659

find_chunknum(pool, info, p, mopts.chunk_canaries);

lib/libc/stdlib/malloc.c

1663

tmp = pool->delayed_chunks[i];

lib/libc/stdlib/malloc.c

1665

wrterror(pool,

lib/libc/stdlib/malloc.c

1670

r = find(pool, tmp);

lib/libc/stdlib/malloc.c

1672

wrterror(pool,

lib/libc/stdlib/malloc.c

1676

validate_junk(pool, tmp, tmpsz);

lib/libc/stdlib/malloc.c

1683

junk_free(pool->malloc_junk, p, sz);

lib/libc/stdlib/malloc.c

1685

i = getrbyte(pool) & MALLOC_DELAYED_CHUNK_MASK;

lib/libc/stdlib/malloc.c

1687

p = pool->delayed_chunks[i];

lib/libc/stdlib/malloc.c

1689

wrterror(pool, "double free %p", p);

lib/libc/stdlib/malloc.c

1690

pool->delayed_chunks[i] = tmp;

lib/libc/stdlib/malloc.c

1692

r = find(pool, p);

lib/libc/stdlib/malloc.c

1694

wrterror(pool,

lib/libc/stdlib/malloc.c

1698

validate_junk(pool, p, sz);

lib/libc/stdlib/malloc.c

1700

free_bytes(pool, r, p);

lib/libc/stdlib/malloc.c

1704

if (*argpool != pool) {

lib/libc/stdlib/malloc.c

1705

pool->func = saved_function;

lib/libc/stdlib/malloc.c

1706

*argpool = pool;

lib/libc/stdlib/malloc.c

1778

struct dir_info *pool;

lib/libc/stdlib/malloc.c

1794

r = findpool(p, *argpool, &pool, &saved_function);

lib/libc/stdlib/malloc.c

1800

chunknum = find_chunknum(pool, info, p, 0);

lib/libc/stdlib/malloc.c

1807

wrterror(pool, "guard size");

lib/libc/stdlib/malloc.c

1815

forced = mopts.malloc_realloc || pool->mmap_flag;

lib/libc/stdlib/malloc.c

1836

STATS_INC(pool->cheap_realloc_tries);

lib/libc/stdlib/malloc.c

1838

__MAP_NOREPLACE | pool->mmap_flag);

lib/libc/stdlib/malloc.c

1840

STATS_ADD(pool->malloc_used, needed);

lib/libc/stdlib/malloc.c

1841

if (pool->malloc_junk == 2)

lib/libc/stdlib/malloc.c

1853

STATS_INC(pool->cheap_reallocs);

lib/libc/stdlib/malloc.c

1864

wrterror(pool, "mprotect");

lib/libc/stdlib/malloc.c

1867

wrterror(pool, "munmap %p", (char *)r->p +

lib/libc/stdlib/malloc.c

1869

STATS_SUB(pool->malloc_used, roldsz - rnewsz);

lib/libc/stdlib/malloc.c

1892

if (newsz > oldsz && pool->malloc_junk == 2)

lib/libc/stdlib/malloc.c

1908

if (pool->malloc_junk == 2)

lib/libc/stdlib/malloc.c

1919

q = omalloc(pool, newsz, 0);

lib/libc/stdlib/malloc.c

1926

ofree(&pool, p, 0, 0, 0);

lib/libc/stdlib/malloc.c

1931

wrterror(pool, "realloc internal inconsistency");

lib/libc/stdlib/malloc.c

1937

if (*argpool != pool) {

lib/libc/stdlib/malloc.c

1938

pool->func = saved_function;

lib/libc/stdlib/malloc.c

1939

*argpool = pool;

lib/libc/stdlib/malloc.c

2022

struct dir_info *pool;

lib/libc/stdlib/malloc.c

2033

r = findpool(p, *argpool, &pool, &saved_function);

lib/libc/stdlib/malloc.c

2039

uint32_t chunknum = find_chunknum(pool, info, p, 0);

lib/libc/stdlib/malloc.c

2042

wrterror(pool, "recorded size %hu != %zu",

lib/libc/stdlib/malloc.c

2047

wrterror(pool, "chunk size %zu < %zu",

lib/libc/stdlib/malloc.c

2052

wrterror(pool, "recorded size %zu < %zu",

lib/libc/stdlib/malloc.c

2055

wrterror(pool,

lib/libc/stdlib/malloc.c

2060

newptr = omalloc(pool, newsize, 0);

lib/libc/stdlib/malloc.c

2070

ofree(&pool, p, 1, 0, oldsize);

lib/libc/stdlib/malloc.c

2073

if (*argpool != pool) {

lib/libc/stdlib/malloc.c

2074

pool->func = saved_function;

lib/libc/stdlib/malloc.c

2075

*argpool = pool;

lib/libc/stdlib/malloc.c

2210

omemalign(struct dir_info *pool, size_t alignment, size_t sz, int zero_fill)

lib/libc/stdlib/malloc.c

2233

return omalloc(pool, pof2, zero_fill);

lib/libc/stdlib/malloc.c

2246

p = mapalign(pool, alignment, psz, zero_fill);

lib/libc/stdlib/malloc.c

2254

caller = pool->caller;

lib/libc/stdlib/malloc.c

2256

if (insert(pool, p, sz, caller)) {

lib/libc/stdlib/malloc.c

2257

unmap(pool, p, psz, 0);

lib/libc/stdlib/malloc.c

2265

wrterror(pool, "mprotect");

lib/libc/stdlib/malloc.c

2266

STATS_ADD(pool->malloc_guarded, mopts.malloc_guard);

lib/libc/stdlib/malloc.c

2269

if (pool->malloc_junk == 2) {

lib/libc/stdlib/malloc.c

2387

print_chunk_details(struct dir_info *pool, void *p, size_t sz, size_t index)

lib/libc/stdlib/malloc.c

2398

r = find(pool, p);

lib/libc/stdlib/malloc.c

2400

chunknum = find_chunknum(pool, chunkinfo, p, 0);

lib/libc/stdlib/malloc.c

2415

wrterror(pool,

lib/libc/stdlib/malloc.c

2704

malloc_dump0(int poolno, struct dir_info *pool, struct leaktree *leaks)

lib/libc/stdlib/malloc.c

2710

if (pool == NULL || pool->r == NULL)

lib/libc/stdlib/malloc.c

2713

p = pool->delayed_chunks[i];

lib/libc/stdlib/malloc.c

2716

r = find(pool, p);

lib/libc/stdlib/malloc.c

2718

wrterror(pool, "bogus pointer in malloc_dump %p", p);

lib/libc/stdlib/malloc.c

2719

free_bytes(pool, r, p);

lib/libc/stdlib/malloc.c

2720

pool->delayed_chunks[i] = NULL;

lib/libc/stdlib/malloc.c

2722

malloc_dump1(poolno, pool, leaks);

lib/libc/stdlib/malloc.c

758

validate_junk(struct dir_info *pool, void *p, size_t argsz)

lib/libc/stdlib/malloc.c

763

if (pool->malloc_junk == 0 || argsz == 0)

lib/libc/stdlib/malloc.c

766

if (pool->malloc_junk == 1) {

lib/libc/stdlib/malloc.c

778

print_chunk_details(pool, lp, argsz, i);

lib/libc/stdlib/malloc.c

781

wrterror(pool,

lib/libexpat/lib/xmlparse.c

2068

p = poolCopyString(&parser->m_dtd->pool, p);

lib/libexpat/lib/xmlparse.c

3414

name = poolStoreString(&dtd->pool, enc, s + enc->minBytesPerChar,

lib/libexpat/lib/xmlparse.c

3419

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

3849

const XML_Char *name = poolCopyString(&dtd->pool, tagNamePtr->str);

lib/libexpat/lib/xmlparse.c

398

STRING_POOL pool;

lib/libexpat/lib/xmlparse.c

533

STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

537

const char *ptr, const char *end, STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

5388

= poolStoreString(&dtd->pool, enc, s + enc->minBytesPerChar,

lib/libexpat/lib/xmlparse.c

5394

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5593

s + enc->minBytesPerChar, next - enc->minBytesPerChar, &dtd->pool,

lib/libexpat/lib/xmlparse.c

5597

attVal = poolStart(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5598

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5713

= poolStoreString(&dtd->pool, enc, s + enc->minBytesPerChar,

lib/libexpat/lib/xmlparse.c

5718

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5750

= poolStoreString(&dtd->pool, enc, s, next);

lib/libexpat/lib/xmlparse.c

5753

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5777

const XML_Char *name = poolStoreString(&dtd->pool, enc, s, next);

lib/libexpat/lib/xmlparse.c

5785

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5788

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5800

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5807

const XML_Char *name = poolStoreString(&dtd->pool, enc, s, next);

lib/libexpat/lib/xmlparse.c

5815

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

5818

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

583

static void FASTCALL poolInit(STRING_POOL *pool, XML_Parser parser);

lib/libexpat/lib/xmlparse.c

5830

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

584

static void FASTCALL poolClear(STRING_POOL *pool);

lib/libexpat/lib/xmlparse.c

585

static void FASTCALL poolDestroy(STRING_POOL *pool);

lib/libexpat/lib/xmlparse.c

586

static XML_Char *poolAppend(STRING_POOL *pool, const ENCODING *enc,

lib/libexpat/lib/xmlparse.c

588

static XML_Char *poolStoreString(STRING_POOL *pool, const ENCODING *enc,

lib/libexpat/lib/xmlparse.c

590

static XML_Bool FASTCALL poolGrow(STRING_POOL *pool);

lib/libexpat/lib/xmlparse.c

591

static const XML_Char *FASTCALL poolCopyString(STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

593

static const XML_Char *FASTCALL poolCopyStringNoFinish(STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

595

static const XML_Char *poolCopyStringN(STRING_POOL *pool, const XML_Char *s,

lib/libexpat/lib/xmlparse.c

597

static const XML_Char *FASTCALL poolAppendString(STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

6005

name = poolStoreString(&dtd->pool, enc, s + enc->minBytesPerChar,

lib/libexpat/lib/xmlparse.c

6010

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

645

#define poolStart(pool) ((pool)->start)

lib/libexpat/lib/xmlparse.c

646

#define poolLength(pool) ((pool)->ptr - (pool)->start)

lib/libexpat/lib/xmlparse.c

647

#define poolChop(pool) ((void)--(pool->ptr))

lib/libexpat/lib/xmlparse.c

648

#define poolLastChar(pool) (((pool)->ptr)[-1])

lib/libexpat/lib/xmlparse.c

649

#define poolDiscard(pool) ((pool)->ptr = (pool)->start)

lib/libexpat/lib/xmlparse.c

650

#define poolFinish(pool) ((pool)->start = (pool)->ptr)

lib/libexpat/lib/xmlparse.c

651

#define poolAppendChar(pool, c) \

lib/libexpat/lib/xmlparse.c

6513

const char *ptr, const char *end, STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

652

(((pool)->ptr == (pool)->end && ! poolGrow(pool)) \

lib/libexpat/lib/xmlparse.c

6520

result = appendAttributeValue(parser, enc, isCdata, next, end, pool,

lib/libexpat/lib/xmlparse.c

6537

pool, XML_ACCOUNT_ENTITY_EXPANSION, &nextInEntity);

lib/libexpat/lib/xmlparse.c

654

: ((*((pool)->ptr)++ = c), 1))

lib/libexpat/lib/xmlparse.c

6581

if (! isCdata && poolLength(pool) && poolLastChar(pool) == 0x20)

lib/libexpat/lib/xmlparse.c

6582

poolChop(pool);

lib/libexpat/lib/xmlparse.c

6583

if (! poolAppendChar(pool, XML_T('\0')))

lib/libexpat/lib/xmlparse.c

6590

const char *ptr, const char *end, STRING_POOL *pool,

lib/libexpat/lib/xmlparse.c

6631

&& (poolLength(pool) == 0 || poolLastChar(pool) == 0x20))

lib/libexpat/lib/xmlparse.c

6644

if (! poolAppendChar(pool, buf[i]))

lib/libexpat/lib/xmlparse.c

6649

if (! poolAppend(pool, enc, ptr, next))

lib/libexpat/lib/xmlparse.c

6657

if (! isCdata && (poolLength(pool) == 0 || poolLastChar(pool) == 0x20))

lib/libexpat/lib/xmlparse.c

6659

if (! poolAppendChar(pool, 0x20))

lib/libexpat/lib/xmlparse.c

6677

if (! poolAppendChar(pool, ch))

lib/libexpat/lib/xmlparse.c

6691

if (pool == &dtd->pool) /* are we called from prolog? */

lib/libexpat/lib/xmlparse.c

6787

STRING_POOL *pool = &(dtd->entityValuePool);

lib/libexpat/lib/xmlparse.c

6798

if (! pool->blocks) {

lib/libexpat/lib/xmlparse.c

6799

if (! poolGrow(pool))

lib/libexpat/lib/xmlparse.c

6890

if (! poolAppend(pool, enc, entityTextPtr, next)) {

lib/libexpat/lib/xmlparse.c

6899

if (pool->end == pool->ptr && ! poolGrow(pool)) {

lib/libexpat/lib/xmlparse.c

6903

*(pool->ptr)++ = 0xA;

lib/libexpat/lib/xmlparse.c

6926

if (pool->end == pool->ptr && ! poolGrow(pool)) {

lib/libexpat/lib/xmlparse.c

6930

*(pool->ptr)++ = buf[i];

lib/libexpat/lib/xmlparse.c

7050

STRING_POOL *const pool = &(parser->m_dtd->entityValuePool);

lib/libexpat/lib/xmlparse.c

7051

if (! poolAppendString(pool, entity_start)

lib/libexpat/lib/xmlparse.c

7052

|| ! poolAppendString(pool, entity->name)

lib/libexpat/lib/xmlparse.c

7053

|| ! poolAppendString(pool, entity_end)) {

lib/libexpat/lib/xmlparse.c

7054

poolDiscard(pool);

lib/libexpat/lib/xmlparse.c

7058

entity->textPtr = poolStart(pool);

lib/libexpat/lib/xmlparse.c

7059

entity->textLen = (int)(poolLength(pool));

lib/libexpat/lib/xmlparse.c

7060

poolFinish(pool);

lib/libexpat/lib/xmlparse.c

7252

if (! poolAppendChar(&dtd->pool, *s))

lib/libexpat/lib/xmlparse.c

7255

if (! poolAppendChar(&dtd->pool, XML_T('\0')))

lib/libexpat/lib/xmlparse.c

7257

prefix = (PREFIX *)lookup(parser, &dtd->prefixes, poolStart(&dtd->pool),

lib/libexpat/lib/xmlparse.c

7261

if (prefix->name == poolStart(&dtd->pool))

lib/libexpat/lib/xmlparse.c

7262

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7264

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7278

if (! poolAppendChar(&dtd->pool, XML_T('\0')))

lib/libexpat/lib/xmlparse.c

7280

name = poolStoreString(&dtd->pool, enc, start, end);

lib/libexpat/lib/xmlparse.c

7290

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7292

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7312

if (! poolAppendChar(&dtd->pool, name[j]))

lib/libexpat/lib/xmlparse.c

7315

if (! poolAppendChar(&dtd->pool, XML_T('\0')))

lib/libexpat/lib/xmlparse.c

7318

poolStart(&dtd->pool), sizeof(PREFIX));

lib/libexpat/lib/xmlparse.c

7321

if (id->prefix->name == poolStart(&dtd->pool))

lib/libexpat/lib/xmlparse.c

7322

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7324

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7461

&dtd->pool, poolStart(&parser->m_tempPool));

lib/libexpat/lib/xmlparse.c

7471

poolFinish(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7473

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

7529

poolInit(&(p->pool), parser);

lib/libexpat/lib/xmlparse.c

7575

poolClear(&(p->pool));

lib/libexpat/lib/xmlparse.c

7615

poolDestroy(&(p->pool));

lib/libexpat/lib/xmlparse.c

7640

name = poolCopyString(&(newDtd->pool), oldP->name);

lib/libexpat/lib/xmlparse.c

7659

if (! poolAppendChar(&(newDtd->pool), XML_T('\0')))

lib/libexpat/lib/xmlparse.c

7661

name = poolCopyString(&(newDtd->pool), oldA->name);

lib/libexpat/lib/xmlparse.c

7691

name = poolCopyString(&(newDtd->pool), oldE->name);

lib/libexpat/lib/xmlparse.c

7727

= poolCopyString(&(newDtd->pool), oldE->defaultAtts[i].value);

lib/libexpat/lib/xmlparse.c

7736

if (! copyEntityTable(oldParser, &(newDtd->generalEntities), &(newDtd->pool),

lib/libexpat/lib/xmlparse.c

7741

if (! copyEntityTable(oldParser, &(newDtd->paramEntities), &(newDtd->pool),

lib/libexpat/lib/xmlparse.c

7993

poolInit(STRING_POOL *pool, XML_Parser parser) {

lib/libexpat/lib/xmlparse.c

7994

pool->blocks = NULL;

lib/libexpat/lib/xmlparse.c

7995

pool->freeBlocks = NULL;

lib/libexpat/lib/xmlparse.c

7996

pool->start = NULL;

lib/libexpat/lib/xmlparse.c

7997

pool->ptr = NULL;

lib/libexpat/lib/xmlparse.c

7998

pool->end = NULL;

lib/libexpat/lib/xmlparse.c

7999

pool->parser = parser;

lib/libexpat/lib/xmlparse.c

8003

poolClear(STRING_POOL *pool) {

lib/libexpat/lib/xmlparse.c

8004

if (! pool->freeBlocks)

lib/libexpat/lib/xmlparse.c

8005

pool->freeBlocks = pool->blocks;

lib/libexpat/lib/xmlparse.c

8007

BLOCK *p = pool->blocks;

lib/libexpat/lib/xmlparse.c

8010

p->next = pool->freeBlocks;

lib/libexpat/lib/xmlparse.c

8011

pool->freeBlocks = p;

lib/libexpat/lib/xmlparse.c

8015

pool->blocks = NULL;

lib/libexpat/lib/xmlparse.c

8016

pool->start = NULL;

lib/libexpat/lib/xmlparse.c

8017

pool->ptr = NULL;

lib/libexpat/lib/xmlparse.c

8018

pool->end = NULL;

lib/libexpat/lib/xmlparse.c

8022

poolDestroy(STRING_POOL *pool) {

lib/libexpat/lib/xmlparse.c

8023

BLOCK *p = pool->blocks;

lib/libexpat/lib/xmlparse.c

8026

FREE(pool->parser, p);

lib/libexpat/lib/xmlparse.c

8029

p = pool->freeBlocks;

lib/libexpat/lib/xmlparse.c

8032

FREE(pool->parser, p);

lib/libexpat/lib/xmlparse.c

8038

poolAppend(STRING_POOL *pool, const ENCODING *enc, const char *ptr,

lib/libexpat/lib/xmlparse.c

8040

if (! pool->ptr && ! poolGrow(pool))

lib/libexpat/lib/xmlparse.c

8044

enc, &ptr, end, (ICHAR **)&(pool->ptr), (const ICHAR *)pool->end);

lib/libexpat/lib/xmlparse.c

8048

if (! poolGrow(pool))

lib/libexpat/lib/xmlparse.c

8051

return pool->start;

lib/libexpat/lib/xmlparse.c

8055

poolCopyString(STRING_POOL *pool, const XML_Char *s) {

lib/libexpat/lib/xmlparse.c

8057

if (! poolAppendChar(pool, *s))

lib/libexpat/lib/xmlparse.c

8060

s = pool->start;

lib/libexpat/lib/xmlparse.c

8061

poolFinish(pool);

lib/libexpat/lib/xmlparse.c

8068

poolCopyStringNoFinish(STRING_POOL *pool, const XML_Char *s) {

lib/libexpat/lib/xmlparse.c

8071

if (! poolAppendChar(pool, *s)) {

lib/libexpat/lib/xmlparse.c

8075

pool->ptr -= advancedBy;

lib/libexpat/lib/xmlparse.c

8079

return pool->start;

lib/libexpat/lib/xmlparse.c

8083

poolCopyStringN(STRING_POOL *pool, const XML_Char *s, int n) {

lib/libexpat/lib/xmlparse.c

8084

if (! pool->ptr && ! poolGrow(pool)) {

lib/libexpat/lib/xmlparse.c

8099

if (! poolAppendChar(pool, *s))

lib/libexpat/lib/xmlparse.c

8102

s = pool->start;

lib/libexpat/lib/xmlparse.c

8103

poolFinish(pool);

lib/libexpat/lib/xmlparse.c

8108

poolAppendString(STRING_POOL *pool, const XML_Char *s) {

lib/libexpat/lib/xmlparse.c

8110

if (! poolAppendChar(pool, *s))

lib/libexpat/lib/xmlparse.c

8114

return pool->start;

lib/libexpat/lib/xmlparse.c

8118

poolStoreString(STRING_POOL *pool, const ENCODING *enc, const char *ptr,

lib/libexpat/lib/xmlparse.c

8120

if (! poolAppend(pool, enc, ptr, end))

lib/libexpat/lib/xmlparse.c

8122

if (pool->ptr == pool->end && ! poolGrow(pool))

lib/libexpat/lib/xmlparse.c

8124

*(pool->ptr)++ = 0;

lib/libexpat/lib/xmlparse.c

8125

return pool->start;

lib/libexpat/lib/xmlparse.c

8157

poolGrow(STRING_POOL *pool) {

lib/libexpat/lib/xmlparse.c

8158

if (pool->freeBlocks) {

lib/libexpat/lib/xmlparse.c

8159

if (pool->start == NULL) {

lib/libexpat/lib/xmlparse.c

8160

pool->blocks = pool->freeBlocks;

lib/libexpat/lib/xmlparse.c

8161

pool->freeBlocks = pool->freeBlocks->next;

lib/libexpat/lib/xmlparse.c

8162

pool->blocks->next = NULL;

lib/libexpat/lib/xmlparse.c

8163

pool->start = pool->blocks->s;

lib/libexpat/lib/xmlparse.c

8164

pool->end = pool->start + pool->blocks->size;

lib/libexpat/lib/xmlparse.c

8165

pool->ptr = pool->start;

lib/libexpat/lib/xmlparse.c

8168

if (pool->end - pool->start < pool->freeBlocks->size) {

lib/libexpat/lib/xmlparse.c

8169

BLOCK *tem = pool->freeBlocks->next;

lib/libexpat/lib/xmlparse.c

8170

pool->freeBlocks->next = pool->blocks;

lib/libexpat/lib/xmlparse.c

8171

pool->blocks = pool->freeBlocks;

lib/libexpat/lib/xmlparse.c

8172

pool->freeBlocks = tem;

lib/libexpat/lib/xmlparse.c

8173

memcpy(pool->blocks->s, pool->start,

lib/libexpat/lib/xmlparse.c

8174

(pool->end - pool->start) * sizeof(XML_Char));

lib/libexpat/lib/xmlparse.c

8175

pool->ptr = pool->blocks->s + (pool->ptr - pool->start);

lib/libexpat/lib/xmlparse.c

8176

pool->start = pool->blocks->s;

lib/libexpat/lib/xmlparse.c

8177

pool->end = pool->start + pool->blocks->size;

lib/libexpat/lib/xmlparse.c

8181

if (pool->blocks && pool->start == pool->blocks->s) {

lib/libexpat/lib/xmlparse.c

8183

int blockSize = (int)((unsigned)(pool->end - pool->start) * 2U);

lib/libexpat/lib/xmlparse.c

8188

const ptrdiff_t offsetInsideBlock = pool->ptr - pool->start;

lib/libexpat/lib/xmlparse.c

8204

temp = REALLOC(pool->parser, pool->blocks, bytesToAllocate);

lib/libexpat/lib/xmlparse.c

8207

pool->blocks = temp;

lib/libexpat/lib/xmlparse.c

8208

pool->blocks->size = blockSize;

lib/libexpat/lib/xmlparse.c

8209

pool->ptr = pool->blocks->s + offsetInsideBlock;

lib/libexpat/lib/xmlparse.c

8210

pool->start = pool->blocks->s;

lib/libexpat/lib/xmlparse.c

8211

pool->end = pool->start + blockSize;

lib/libexpat/lib/xmlparse.c

8214

int blockSize = (int)(pool->end - pool->start);

lib/libexpat/lib/xmlparse.c

8244

tem = MALLOC(pool->parser, bytesToAllocate);

lib/libexpat/lib/xmlparse.c

8248

tem->next = pool->blocks;

lib/libexpat/lib/xmlparse.c

8249

pool->blocks = tem;

lib/libexpat/lib/xmlparse.c

8250

if (pool->ptr != pool->start)

lib/libexpat/lib/xmlparse.c

8251

memcpy(tem->s, pool->start, (pool->ptr - pool->start) * sizeof(XML_Char));

lib/libexpat/lib/xmlparse.c

8252

pool->ptr = tem->s + (pool->ptr - pool->start);

lib/libexpat/lib/xmlparse.c

8253

pool->start = tem->s;

lib/libexpat/lib/xmlparse.c

8254

pool->end = tem->s + blockSize;

lib/libexpat/lib/xmlparse.c

8467

const XML_Char *name = poolStoreString(&dtd->pool, enc, ptr, end);

lib/libexpat/lib/xmlparse.c

8477

poolDiscard(&dtd->pool);

lib/libexpat/lib/xmlparse.c

8479

poolFinish(&dtd->pool);

libexec/ld.so/malloc.c

885

validate_junk(struct dir_info *pool, void *p)

libexec/ld.so/malloc.c

892

r = find(pool, p);

regress/usr.sbin/snmpd/agentx.c

2409

struct varbind *pool;

regress/usr.sbin/snmpd/agentx.c

2432

if ((pool = calloc(nvarbind, sizeof(*pool))) == NULL)

regress/usr.sbin/snmpd/agentx.c

2434

memcpy(pool, varbind, nvarbind * sizeof(*pool));

regress/usr.sbin/snmpd/agentx.c

2452

if (oid_cmp(&pool[j].name, &start) == 0)

regress/usr.sbin/snmpd/agentx.c

2459

varbind[i] = pool[j];

regress/usr.sbin/snmpd/agentx.c

2460

pool[j].name.n_subid = 0;

regress/usr.sbin/snmpd/agentx.c

2462

free(pool);

regress/usr.sbin/snmpd/agentx.c

2477

struct varbind *pool;

regress/usr.sbin/snmpd/agentx.c

2500

if ((pool = calloc(nvarbind, sizeof(*pool))) == NULL)

regress/usr.sbin/snmpd/agentx.c

2502

memcpy(pool, varbind, nvarbind * sizeof(*pool));

regress/usr.sbin/snmpd/agentx.c

2520

if (oid_cmp(&pool[j].name, &start) == 0 &&

regress/usr.sbin/snmpd/agentx.c

2521

pool[j].type == TYPE_ENDOFMIBVIEW) {

regress/usr.sbin/snmpd/agentx.c

2523

} else if (oid_cmp(&pool[j].name, &start) < 0 ||

regress/usr.sbin/snmpd/agentx.c

2525

oid_cmp(&pool[j].name, &start) == 0) ||

regress/usr.sbin/snmpd/agentx.c

2526

oid_cmp(&pool[j].name, &end) >= 0)

regress/usr.sbin/snmpd/agentx.c

2531

if (oid_cmp(&pool[j].name,

regress/usr.sbin/snmpd/agentx.c

2532

&pool[match].name) < 0)

regress/usr.sbin/snmpd/agentx.c

2556

varbind[i] = pool[match];

regress/usr.sbin/snmpd/agentx.c

2557

pool[match].name.n_subid = 0;

regress/usr.sbin/snmpd/agentx.c

2559

free(pool);

sbin/pfctl/pfctl_parser.c

461

print_pool(struct pf_pool *pool, u_int16_t p1, u_int16_t p2,

sbin/pfctl/pfctl_parser.c

464

if (pool->ifname[0]) {

sbin/pfctl/pfctl_parser.c

465

if (!PF_AZERO(&pool->addr.v.a.addr, af)) {

sbin/pfctl/pfctl_parser.c

466

print_addr(&pool->addr, af, verbose);

sbin/pfctl/pfctl_parser.c

469

printf("%s", pool->ifname);

sbin/pfctl/pfctl_parser.c

471

print_addr(&pool->addr, af, verbose);

sbin/pfctl/pfctl_parser.c

492

switch (pool->opts & PF_POOL_TYPEMASK) {

sbin/pfctl/pfctl_parser.c

503

pool->key.key32[0], pool->key.key32[1],

sbin/pfctl/pfctl_parser.c

504

pool->key.key32[2], pool->key.key32[3]);

sbin/pfctl/pfctl_parser.c

513

if (pool->opts & PF_POOL_STICKYADDR)

sys/arch/alpha/alpha/pmap.c

247

struct pool pmap_pmap_pool;

sys/arch/alpha/alpha/pmap.c

248

struct pool pmap_l1pt_pool;

sys/arch/alpha/alpha/pmap.c

249

struct pool pmap_pv_pool;

sys/arch/alpha/alpha/pmap.c

2732

pmap_pv_page_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/alpha/alpha/pmap.c

2748

pmap_pv_page_free(struct pool *pp, void *v)

sys/arch/alpha/alpha/pmap.c

3057

pmap_l1pt_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/alpha/alpha/pmap.c

3077

pmap_l1pt_free(struct pool *pp, void *v)

sys/arch/alpha/alpha/pmap.c

408

void *pmap_l1pt_alloc(struct pool *, int, int *);

sys/arch/alpha/alpha/pmap.c

409

void pmap_l1pt_free(struct pool *, void *);

sys/arch/alpha/alpha/pmap.c

423

void *pmap_pv_page_alloc(struct pool *, int, int *);

sys/arch/alpha/alpha/pmap.c

424

void pmap_pv_page_free(struct pool *, void *);

sys/arch/amd64/amd64/aesni.c

73

struct pool aesnipl;

sys/arch/amd64/amd64/pmap.c

278

struct pool pmap_pv_pool;

sys/arch/amd64/amd64/pmap.c

291

struct pool pmap_pmap_pool;

sys/arch/amd64/amd64/pmap.c

303

struct pool pmap_pdp_pool;

sys/arch/arm/arm/pmap7.c

2414

pmap_pv_page_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/arm/arm/pmap7.c

2426

pmap_pv_page_free(struct pool *pp, void *v)

sys/arch/arm/arm/pmap7.c

249

struct pool pmap_pmap_pool;

sys/arch/arm/arm/pmap7.c

254

struct pool pmap_pv_pool;

sys/arch/arm/arm/pmap7.c

255

void *pmap_pv_page_alloc(struct pool *, int, int *);

sys/arch/arm/arm/pmap7.c

256

void pmap_pv_page_free(struct pool *, void *);

sys/arch/arm/arm/pmap7.c

266

struct pool pmap_l2dtable_pool;

sys/arch/arm/arm/pmap7.c

274

struct pool pmap_l2ptp_pool;

sys/arch/arm64/arm64/cryptox.c

65

struct pool cryptoxpl;

sys/arch/arm64/arm64/pmap.c

128

struct pool pmap_pmap_pool;

sys/arch/arm64/arm64/pmap.c

129

struct pool pmap_pted_pool;

sys/arch/arm64/arm64/pmap.c

130

struct pool pmap_vp_pool;

sys/arch/arm64/arm64/pmap.c

511

pmap_vp_page_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/arm64/arm64/pmap.c

523

pmap_vp_page_free(struct pool *pp, void *v)

sys/arch/arm64/arm64/pmap.c

97

void *pmap_vp_page_alloc(struct pool *, int, int *);

sys/arch/arm64/arm64/pmap.c

98

void pmap_vp_page_free(struct pool *, void *);

sys/arch/arm64/dev/smmuvar.h

121

struct pool sc_vp_pool;

sys/arch/arm64/dev/smmuvar.h

122

struct pool sc_vp3_pool;

sys/arch/hppa/gsc/harmony.c

804

harmony_allocm(void *vsc, int dir, size_t size, int pool, int flags)

sys/arch/hppa/gsc/harmony.c

810

d = (struct harmony_dma *)malloc(sizeof(struct harmony_dma), pool, flags);

sys/arch/hppa/gsc/harmony.c

842

free(d, pool, sizeof *d);

sys/arch/hppa/gsc/harmony.c

848

harmony_freem(void *vsc, void *ptr, int pool)

sys/arch/hppa/gsc/harmony.c

860

free(d, pool, sizeof *d);

sys/arch/hppa/hppa/machdep.c

141

struct pool hppa_fppl;

sys/arch/hppa/hppa/pmap.c

94

struct pool pmap_pmap_pool;

sys/arch/hppa/hppa/pmap.c

95

struct pool pmap_pv_pool;

sys/arch/hppa/hppa/vm_machdep.c

49

extern struct pool hppa_fppl;

sys/arch/i386/i386/pmap.c

1155

pmap_pv_page_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/i386/i386/pmap.c

1167

pmap_pv_page_free(struct pool *pp, void *v)

sys/arch/i386/i386/pmap.c

418

struct pool pmap_pv_pool;

sys/arch/i386/i386/pmap.c

445

struct pool pmap_pmap_pool;

sys/arch/i386/i386/pmap.c

467

void *pmap_pv_page_alloc(struct pool *, int, int *);

sys/arch/i386/i386/pmap.c

468

void pmap_pv_page_free(struct pool *, void *);

sys/arch/i386/include/pmap.h

195

extern struct pool pmap_pv_pool;

sys/arch/m88k/m88k/pmap.c

127

struct pool pmappool, pvpool;

sys/arch/macppc/macppc/machdep.c

95

struct pool ppc_vecpl;

sys/arch/mips64/mips64/pmap.c

1922

pmap_pg_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/mips64/mips64/pmap.c

1947

pmap_pg_free(struct pool *pp, void *item)

sys/arch/mips64/mips64/pmap.c

50

struct pool pmap_pmap_pool;

sys/arch/mips64/mips64/pmap.c

51

struct pool pmap_pv_pool;

sys/arch/mips64/mips64/pmap.c

52

struct pool pmap_pg_pool;

sys/arch/mips64/mips64/pmap.c

76

void *pmap_pg_alloc(struct pool *, int, int *);

sys/arch/mips64/mips64/pmap.c

77

void pmap_pg_free(struct pool *, void *);

sys/arch/octeon/dev/cn30xxpkovar.h

117

cn30xxpko_cmd_word1(int i, int back, int pool, int size, paddr_t addr)

sys/arch/octeon/dev/cn30xxpkovar.h

123

| (((uint64_t)pool << 56) & PKO_CMD_WORD1_POOL)

sys/arch/octeon/dev/if_ogx.c

2179

ogx_fpa3_pool_init(struct ogx_node *node, struct fpa3pool *pool,

sys/arch/octeon/dev/if_ogx.c

2187

pool->nodeid = node->node_id;

sys/arch/octeon/dev/if_ogx.c

2188

pool->poolid = poolid;

sys/arch/octeon/dev/if_ogx.c

2191

BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &pool->dmap))

sys/arch/octeon/dev/if_ogx.c

2194

0, &pool->dmaseg, 1, &rsegs,

sys/arch/octeon/dev/if_ogx.c

2197

if (bus_dmamem_map(node->node_dmat, &pool->dmaseg, 1, segsize,

sys/arch/octeon/dev/if_ogx.c

2198

&pool->kva, BUS_DMA_NOWAIT | BUS_DMA_COHERENT))

sys/arch/octeon/dev/if_ogx.c

2200

if (bus_dmamap_load(node->node_dmat, pool->dmap, pool->kva, segsize,

sys/arch/octeon/dev/if_ogx.c

2212

FPA3_WR_8(node, FPA3_POOL_STACK_BASE(poolid), pool->dmaseg.ds_addr);

sys/arch/octeon/dev/if_ogx.c

2213

FPA3_WR_8(node, FPA3_POOL_STACK_ADDR(poolid), pool->dmaseg.ds_addr);

sys/arch/octeon/dev/if_ogx.c

2214

FPA3_WR_8(node, FPA3_POOL_STACK_END(poolid), pool->dmaseg.ds_addr +

sys/arch/octeon/dev/if_ogx.c

2215

pool->dmaseg.ds_len);

sys/arch/octeon/dev/if_ogx.c

2223

uint32_t auraid, struct fpa3pool *pool)

sys/arch/octeon/dev/if_ogx.c

2225

KASSERT(node->node_id == pool->nodeid);

sys/arch/octeon/dev/if_ogx.c

2227

aura->nodeid = pool->nodeid;

sys/arch/octeon/dev/if_ogx.c

2228

aura->poolid = pool->poolid;

sys/arch/octeon/dev/octcrypto.c

200

static struct pool octcryptopl;

sys/arch/powerpc/include/reg.h

74

extern struct pool ppc_vecpl;

sys/arch/powerpc/powerpc/pmap.c

178

struct pool pmap_pmap_pool;

sys/arch/powerpc/powerpc/pmap.c

179

struct pool pmap_vp_pool;

sys/arch/powerpc/powerpc/pmap.c

180

struct pool pmap_pted_pool;

sys/arch/powerpc64/powerpc64/pmap.c

184

struct pool pmap_pmap_pool;

sys/arch/powerpc64/powerpc64/pmap.c

185

struct pool pmap_vp_pool;

sys/arch/powerpc64/powerpc64/pmap.c

186

struct pool pmap_pted_pool;

sys/arch/powerpc64/powerpc64/pmap.c

187

struct pool pmap_slbd_pool;

sys/arch/riscv64/riscv64/pmap.c

191

void *pmap_vp_page_alloc(struct pool *, int, int *);

sys/arch/riscv64/riscv64/pmap.c

192

void pmap_vp_page_free(struct pool *, void *);

sys/arch/riscv64/riscv64/pmap.c

221

struct pool pmap_pmap_pool;

sys/arch/riscv64/riscv64/pmap.c

222

struct pool pmap_pted_pool;

sys/arch/riscv64/riscv64/pmap.c

223

struct pool pmap_vp_pool;

sys/arch/riscv64/riscv64/pmap.c

441

pmap_vp_page_alloc(struct pool *pp, int flags, int *slowdown)

sys/arch/riscv64/riscv64/pmap.c

453

pmap_vp_page_free(struct pool *pp, void *v)

sys/arch/sh/sh/pmap.c

64

STATIC struct pool __pmap_pmap_pool;

sys/arch/sh/sh/pmap.c

77

STATIC void *__pmap_pv_page_alloc(struct pool *, int, int *);

sys/arch/sh/sh/pmap.c

78

STATIC void __pmap_pv_page_free(struct pool *, void *);

sys/arch/sh/sh/pmap.c

79

STATIC struct pool __pmap_pv_pool;

sys/arch/sh/sh/pmap.c

925

__pmap_pv_page_alloc(struct pool *pool, int flags, int *slowdown)

sys/arch/sh/sh/pmap.c

938

__pmap_pv_page_free(struct pool *pool, void *v)

sys/arch/sparc64/dev/ce4231.c

1173

ce4231_alloc(void *addr, int direction, size_t size, int pool, int flags)

sys/arch/sparc64/dev/ce4231.c

1179

p = (struct cs_dma *)malloc(sizeof(struct cs_dma), pool, flags);

sys/arch/sparc64/dev/ce4231.c

1213

free(p, pool, 0);

sys/arch/sparc64/dev/ce4231.c

1218

ce4231_free(void *addr, void *ptr, int pool)

sys/arch/sparc64/dev/ce4231.c

1232

free(p, pool, 0);

sys/arch/sparc64/dev/vnet.c

181

struct pool sc_pool;

sys/arch/sparc64/sparc64/pmap.c

104

static struct pool pv_pool;

sys/arch/sparc64/sparc64/pmap.c

105

static struct pool pmap_pool;

sys/crypto/crypto.c

41

struct pool cryptop_pool; /* [I] set of crypto descriptors */

sys/ddb/db_command.c

386

extern struct pool vnode_pool;

sys/ddb/db_command.c

398

extern struct pool bufpool;

sys/ddb/db_command.c

543

pool_printit((struct pool *)addr, modif, db_printf);

sys/dev/acpi/acpi.c

61

struct pool acpiwqpool;

sys/dev/ata/atascsi.c

301

link->pool = &ahp->ahp_iopool;

sys/dev/cardbus/cardslot.c

73

struct pool cardsloteventpool;

sys/dev/fdt/if_mvpp.c

2170

uint32_t i, nrecv, pool;

sys/dev/fdt/if_mvpp.c

2176

pool = curcpu()->ci_cpuid;

sys/dev/fdt/if_mvpp.c

2177

KASSERT(pool < sc->sc->sc_npools);

sys/dev/fdt/if_mvpp.c

2178

bm = &sc->sc->sc_bm_pools[pool];

sys/dev/fdt/if_mvpp.c

2187

KASSERT(((virt >> 16) & 0xffff) == pool);

sys/dev/fdt/if_mvpp.c

2230

int pool;

sys/dev/fdt/if_mvpp.c

2232

pool = curcpu()->ci_cpuid;

sys/dev/fdt/if_mvpp.c

2233

KASSERT(pool < sc->sc->sc_npools);

sys/dev/fdt/if_mvpp.c

2234

bm = &sc->sc->sc_bm_pools[pool];

sys/dev/fdt/if_mvpp.c

2238

KASSERT(((virt >> 16) & 0xffff) == pool);

sys/dev/fdt/if_mvpp.c

2257

mvpp2_write(sc->sc, MVPP2_BM_PHY_RLS_REG(pool),

sys/dev/fdt/if_mvpp.c

2964

uint32_t i, nrecv, pool;

sys/dev/fdt/if_mvpp.c

2978

pool = (virt >> 16) & 0xffff;

sys/dev/fdt/if_mvpp.c

2979

KASSERT(pool < sc->sc->sc_npools);

sys/dev/fdt/if_mvpp.c

2980

bm = &sc->sc->sc_bm_pools[pool];

sys/dev/fdt/if_mvpp.c

2992

mvpp2_write(sc->sc, MVPP2_BM_PHY_RLS_REG(pool),

sys/dev/fdt/if_mvpp.c

3018

mvpp2_rxq_long_pool_set(struct mvpp2_port *port, int lrxq, int pool)

sys/dev/fdt/if_mvpp.c

3028

val |= ((pool << MVPP2_RXQ_POOL_LONG_OFFS) & MVPP2_RXQ_POOL_LONG_MASK);

sys/dev/fdt/if_mvpp.c

3034

mvpp2_rxq_short_pool_set(struct mvpp2_port *port, int lrxq, int pool)

sys/dev/fdt/if_mvpp.c

3044

val |= ((pool << MVPP2_RXQ_POOL_SHORT_OFFS) & MVPP2_RXQ_POOL_SHORT_MASK);

sys/dev/fdt/if_mvppreg.h

250

#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

252

#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

254

#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

256

#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

258

#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

259

#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

262

#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

274

#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

280

#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

281

#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

288

#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))

sys/dev/fdt/if_mvppreg.h

82

#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))

sys/dev/ic/ncr53c9x.c

142

static struct pool ecb_pool;

sys/dev/ic/wdc.c

86

struct pool wdc_xfer_pool;

sys/dev/isa/ad1848.c

1439

ad1848_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/isa/ad1848.c

1449

return isa_malloc(sc->sc_isa, drq, size, pool, flags);

sys/dev/isa/ad1848.c

1453

ad1848_free(void *addr, void *ptr, int pool)

sys/dev/isa/ad1848.c

1455

isa_free(ptr, pool);

sys/dev/isa/ess.c

2043

ess_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/isa/ess.c

2052

return (isa_malloc(sc->sc_isa, drq, size, pool, flags));

sys/dev/isa/ess.c

2056

ess_free(void *addr, void *ptr, int pool)

sys/dev/isa/ess.c

2058

isa_free(ptr, pool);

sys/dev/isa/gus.c

3036

gus_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/isa/gus.c

3046

return isa_malloc(sc->sc_isa, drq, size, pool, flags);

sys/dev/isa/gus.c

3050

gus_free(void *addr, void *ptr, int pool)

sys/dev/isa/gus.c

3052

isa_free(ptr, pool);

sys/dev/isa/isadma.c

593

isa_malloc(struct device *isadev, int chan, size_t size, int pool, int flags)

sys/dev/isa/isadma.c

608

m = malloc(sizeof(*m), pool, flags);

sys/dev/isa/isadma.c

625

isa_free(void *addr, int pool)

sys/dev/isa/isadma.c

640

free(m, pool, 0);

sys/dev/isa/sbdsp.c

2093

sb_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/isa/sbdsp.c

2104

return isa_malloc(sc->sc_isa, drq, size, pool, flags);

sys/dev/isa/sbdsp.c

2108

sb_free(void *addr, void *ptr, int pool)

sys/dev/isa/sbdsp.c

2110

isa_free(ptr, pool);

sys/dev/kcov.c

130

struct pool kr_pool;

sys/dev/kstat.c

158

struct pool kstat_pool;

sys/dev/pci/auacer.c

580

auacer_allocm(void *v, int direction, size_t size, int pool, int flags)

sys/dev/pci/auacer.c

589

p = malloc(sizeof(*p), pool, flags | M_ZERO);

sys/dev/pci/auacer.c

595

free(p, pool, sizeof(*p));

sys/dev/pci/auacer.c

606

auacer_freem(void *v, void *ptr, int pool)

sys/dev/pci/auacer.c

615

free(p, pool, sizeof(*p));

sys/dev/pci/auglx.c

557

auglx_allocm(void *v, int direction, size_t size, int pool, int flags)

sys/dev/pci/auglx.c

574

p = malloc(sizeof(*p), pool, flags | M_ZERO);

sys/dev/pci/auglx.c

580

free(p, pool, sizeof(*p));

sys/dev/pci/auglx.c

591

auglx_freem(void *v, void *ptr, int pool)

sys/dev/pci/auglx.c

601

free(p, pool, sizeof(*p));

sys/dev/pci/auich.c

855

auich_allocm(void *v, int direction, size_t size, int pool, int flags)

sys/dev/pci/auich.c

869

p = malloc(sizeof(*p), pool, flags | M_ZERO);

sys/dev/pci/auich.c

875

free(p, pool, sizeof(*p));

sys/dev/pci/auich.c

890

auich_freem(void *v, void *ptr, int pool)

sys/dev/pci/auich.c

906

free(p, pool, sizeof(*p));

sys/dev/pci/auixp.c

349

auixp_malloc(void *hdl, int direction, size_t size, int pool, int flags)

sys/dev/pci/auixp.c

359

dma = malloc(sizeof(*dma), pool, flags);

sys/dev/pci/auixp.c

366

free(dma, pool, sizeof(*dma));

sys/dev/pci/auixp.c

386

auixp_free(void *hdl, void *addr, int pool)

sys/dev/pci/auixp.c

399

free(dma, pool, sizeof(*dma));

sys/dev/pci/autri.c

1005

free(p, pool, sizeof(*p));

sys/dev/pci/autri.c

971

autri_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/autri.c

977

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/autri.c

986

free(p, pool, sizeof(*p));

sys/dev/pci/autri.c

996

autri_free(void *addr, void *ptr, int pool)

sys/dev/pci/auvia.c

704

auvia_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/auvia.c

711

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/auvia.c

757

free(p, pool, sizeof(*p));

sys/dev/pci/auvia.c

763

auvia_free(void *addr, void *ptr, int pool)

sys/dev/pci/auvia.c

776

free(p, pool, sizeof(*p));

sys/dev/pci/azalia.c

4119

azalia_allocm(void *v, int dir, size_t size, int pool, int flags)

sys/dev/pci/azalia.c

4136

azalia_freem(void *v, void *addr, int pool)

sys/dev/pci/cs4280.c

1181

cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/cs4280.c

1188

DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags));

sys/dev/pci/cs4280.c

1189

q = malloc(size, pool, flags);

sys/dev/pci/cs4280.c

1192

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/cs4280.c

1194

free(q,pool, 0);

sys/dev/pci/cs4280.c

1203

free(q, pool, 0);

sys/dev/pci/cs4280.c

1204

free(p, pool, 0);

sys/dev/pci/cs4280.c

1216

cs4280_free(void *addr, void *ptr, int pool)

sys/dev/pci/cs4280.c

1225

free(p->dum, pool, 0);

sys/dev/pci/cs4280.c

1226

free(p, pool, 0);

sys/dev/pci/cs4281.c

1134

cs4281_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/cs4281.c

1142

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/cs4281.c

1146

error = cs4281_allocmem(sc, size, pool, flags, p);

sys/dev/pci/cs4281.c

1149

free(p, pool, sizeof(*p));

sys/dev/pci/cs4281.c

1159

cs4281_free(void *addr, void *ptr, int pool)

sys/dev/pci/cs4281.c

1172

free(p, pool, sizeof(*p));

sys/dev/pci/cs4281.c

1264

cs4281_allocmem(struct cs4281_softc *sc, size_t size, int pool, int flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

563

enum amdgpu_ib_pool_type pool,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

41

static struct pool amdgpu_mux_chunk_slab;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

43

static struct pool amdgpu_sync_slab;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1177

struct ttm_pool *pool;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1193

pool = &adev->mman.ttm_pools[gtt->pool_id];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1195

pool = &adev->mman.bdev.pool;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1196

ret = ttm_pool_alloc(pool, ttm, ctx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1219

struct ttm_pool *pool;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1245

pool = &adev->mman.ttm_pools[gtt->pool_id];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1247

pool = &adev->mman.bdev.pool;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1249

return ttm_pool_free(pool, ttm);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2321

enum amdgpu_ib_pool_type pool = direct_submit ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2329

num_dw * 4, pool, job, k_job_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2593

return ttm_pool_debugfs(&adev->mman.bdev.pool, m);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

36

static struct pool amdgpu_userq_fence_slab;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c

45

enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c

59

ndw * 4, pool, &p->job, k_job_id);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2474

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2478

if (pool && res_ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2481

for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2492

if (acquire && pool->funcs->acquire_post_bldn_3dlut)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2493

ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2494

else if (!acquire && pool->funcs->release_post_bldn_3dlut)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2495

ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1716

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1751

int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1763

for (i = pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1823

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1829

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1846

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1852

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1869

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1875

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1893

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1899

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1916

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1922

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2484

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2490

for (i = 0; i < pool->pipe_count && result; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2496

if (pool->funcs->build_pipe_pix_clk_params)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2497

pool->funcs->build_pipe_pix_clk_params(otg_master);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2507

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2513

for (i = 0; i < pool->pipe_count && result; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2523

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2528

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2541

split_pipe->stream_res.tg = pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2542

split_pipe->plane_res.hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2543

split_pipe->plane_res.ipp = pool->ipps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2544

split_pipe->plane_res.dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2545

split_pipe->stream_res.opp = pool->opps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2546

split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2558

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2564

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2565

if (pool->stream_enc[i] == stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2572

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2578

for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2579

if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2599

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2608

i < pool->hpo_dp_link_enc_count) ? i : -1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2636

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2647

enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2653

pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2693

const struct dc_link *link, const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2696

int enc_count = pool->dig_link_enc_count;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2748

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2764

if (pipe_ctx && pipe_ctx->link_res.dio_link_enc == pool->link_encoders[old_encoder])

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2765

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[new_encoder];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2771

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2784

enc_index = find_free_dio_link_enc(res_ctx, stream->link, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2794

int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2797

swap_dio_link_enc_to_muxable_ctx(context, pool, new_enc_index, enc_index);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2808

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[enc_index];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2828

static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2833

for (i = 0; i < pool->pipe_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2840

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2849

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2863

pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2869

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2882

pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2887

pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2890

if (pool->funcs->remove_stream_from_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2891

pool->funcs->remove_stream_from_ctx(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2975

struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2982

if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2989

if (get_num_of_free_pipes(pool, new_ctx) < opp_head_count)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2994

sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2997

pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3021

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3033

cur_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3037

plane_state, new_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3040

pool, plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3048

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3053

for (i = pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3116

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3123

if (!pool->funcs->acquire_free_pipe_as_secondary_opp_head) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3127

new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3128

cur_ctx, new_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3142

new_bottom_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3143

cur_ctx, new_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3195

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3200

if (!pool->funcs->release_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3211

pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3215

pool->funcs->release_pipe(context, last_opp_head, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3255

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3262

if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3266

new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3267

cur_ctx, new_ctx, pool, opp_head);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3317

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3322

if (!pool->funcs->release_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3334

pool->funcs->release_pipe(context, last_dpp_pipe, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3342

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3363

otg_master, new_ctx, cur_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3367

otg_master, new_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3370

otg_master, new_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3377

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3398

dpp_pipes[0], new_ctx, cur_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3402

dpp_pipes[0], new_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3405

dpp_pipes[0]->plane_state, new_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3501

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3506

for (i = 0; i < pool->audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3507

if (pool->audios[i] == audio)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3514

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3519

for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3521

pool->hpo_dp_stream_enc[i]) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3523

return pool->hpo_dp_stream_enc[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3532

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3541

available_audio_count = pool->audio_count;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3548

return pool->audios[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3554

return pool->audios[id];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3559

return pool->audios[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3636

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3653

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3654

if (pool->stream_enc[i]->id == inst) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3655

tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3656

pool->stream_enc[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3662

if (i == pool->stream_enc_count)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3665

if (tg_inst >= pool->timing_generator_count)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3671

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3690

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3691

pipe_ctx->plane_res.mi = pool->mis[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3692

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3693

pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3694

pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3695

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3696

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3698

if (pool->dpps[id_src[i]]) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3699

pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3701

if (pool->mpc->funcs->read_mpcc_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3704

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3707

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3711

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3712

&pool->mpc->mpcc_array[s.bot_mpcc_id];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3720

if (id_src[i] >= pool->timing_generator_count) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3721

id_src[i] = pool->timing_generator_count - 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3723

pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3724

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3783

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3813

&cur_ctx->res_ctx, &new_ctx->res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3820

&cur_ctx->res_ctx, &new_ctx->res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3828

&cur_ctx->res_ctx, &new_ctx->res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3830

pipe_idx = resource_find_any_free_pipe(&new_ctx->res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3835

pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3836

pipe_ctx->plane_res.mi = pool->mis[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3837

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3838

pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3839

pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3840

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3841

pipe_ctx->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3842

if (pool->dpps[pipe_idx])

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3843

pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3845

if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3846

int tg_inst = pool->timing_generator_count - 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3848

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3849

pipe_ctx->stream_res.opp = pool->opps[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3854

pipe_idx = acquire_first_split_pipe(&new_ctx->res_ctx, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3865

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3880

pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3892

context, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3901

&context->res_ctx, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3907

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3927

&context->res_ctx, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3933

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3936

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3942

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3952

&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3960

update_audio_usage(&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3966

if (pool->abm)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3967

pipe_ctx->stream_res.abm = pool->abm;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3969

pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

403

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

407

const struct resource_caps *caps = pool->res_cap;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

415

pool->audio_count = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

424

update_num_audio(&straps, &num_audio, &pool->audio_support);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

436

pool->audios[i] = aud;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

437

pool->audio_count++;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

441

pool->stream_enc_count = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

444

pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

445

if (pool->stream_enc[i] == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

447

pool->stream_enc_count++;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

451

pool->hpo_dp_stream_enc_count = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

454

pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

455

if (pool->hpo_dp_stream_enc[i] == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

457

pool->hpo_dp_stream_enc_count++;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

462

pool->hpo_dp_link_enc_count = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

465

pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

466

if (pool->hpo_dp_link_enc[i] == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

468

pool->hpo_dp_link_enc_count++;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

473

pool->mpc_lut[i] = dc_create_3dlut_func();

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

474

if (pool->mpc_lut[i] == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

476

pool->mpc_shaper[i] = dc_create_transfer_func();

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

477

if (pool->mpc_shaper[i] == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4773

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4777

for (i = 0; i < pool->clk_src_count; ++i) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4779

return pool->clock_sources[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

482

if (pool->audio_count < pool->stream_enc_count) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4839

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4848

pipe_ctx->clock_source = pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

486

pool->stream_enc[pool->stream_enc_count] =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4861

pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4868

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

489

if (pool->stream_enc[pool->stream_enc_count] == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

493

pool->stream_enc_count++;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

501

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

507

for (i = 0; i < pool->clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

508

if (pool->clock_sources[i] == clock_source)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

516

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

519

int i = find_matching_clock_source(pool, clock_source);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5192

const struct resource_pool *const pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5204

enc_index = find_free_dio_link_enc(res_ctx, link, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5207

link_enc = pool->link_encoders[enc_index];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5214

const struct resource_pool *const pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5223

enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5226

hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

524

if (pool->dp_clock_source == clock_source)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

530

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

533

int i = find_matching_clock_source(pool, clock_source);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

538

if (pool->dp_clock_source == clock_source)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

544

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5442

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5460

sec_pipe->plane_res.mi = pool->mis[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5461

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5462

sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5463

sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5464

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5465

sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5469

sec_pipe->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

547

int i = find_matching_clock_source(pool, clock_source);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

552

if (pool->dp_clock_source == clock_source)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

469

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

491

dc->current_state, pool, otg_master_pipe, plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

500

dc->current_state, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

513

dc->current_state, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

539

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

556

state, pool, plane_state);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

29

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

55

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

72

dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

75

return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

79

return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.h

34

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.h

40

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

443

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

456

if (line < pool->res_cap->num_ddc)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

457

dce_i2c_hw = pool->hw_i2cs[line];

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

463

if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw))

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

490

pool->i2c_hw_buffer_in_use = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

629

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

655

pool->i2c_hw_buffer_in_use = false;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

346

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

352

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

467

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

493

release_engine_dce_sw(pool, dce_i2c_sw);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

67

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.h

47

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

113

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

134

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

135

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

191

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

204

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

205

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

213

pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

233

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

249

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

250

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

261

pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

290

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

303

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

304

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

312

pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

330

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

342

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

343

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

385

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

395

for (i = 0; i < pool->mpcc_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

398

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

416

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

427

for (i = 0; i < pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

428

struct timing_generator *tg = pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

493

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

496

for (i = 0; i < pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

497

struct timing_generator *tg = pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

510

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

513

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

514

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1199

for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1261

hsplit_pipe = resource_find_free_secondary_pipe_legacy(&context->res_ctx, pool, pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1263

split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

524

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

536

secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

537

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

538

secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

539

secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

540

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

541

secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

759

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

893

for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2404

struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2411

dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2412

dcn2_1_ip.max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

326

struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

336

dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

337

dcn3_01_ip.max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

34

#define TO_DCN301_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

35

container_of(pool, struct dcn301_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1859

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1887

sec_pipe->plane_res.mi = pool->mis[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1888

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1889

sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1890

sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1891

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1892

sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1913

sec_pipe->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

681

static bool is_pipe_used(const struct dc_plane_pipe_pool *pool, unsigned int pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

685

for (i = 0; i < pool->num_pipes_assigned_to_plane_for_odm_combine; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

686

for (j = 0; j < pool->num_pipes_assigned_to_plane_for_mpcc_combine; j++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

687

if (pool->pipes_assigned_to_plane[i][j] == pipe_idx && pool->pipe_used[i][j])

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

701

const struct dc_plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id, int plane_index)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

711

!is_pipe_used(pool, state->res_ctx.pipe_ctx[i].pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

141

void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

81

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

87

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2085

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2088

int underlay_idx = pool->underlay_pipe_index;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

68

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

297

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

302

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

303

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

337

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

338

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

344

pool->hubps[i]->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

374

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

375

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

380

pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

400

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

401

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

408

pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4103

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4106

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4107

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

432

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

433

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

438

pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

453

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

462

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

463

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

538

for (i = 0; i < pool->mpcc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

541

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

561

for (i = 0; i < pool->mpcc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

564

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

596

for (i = 0; i < pool->mpcc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

599

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

614

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

630

for (i = 0; i < pool->timing_generator_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

631

struct timing_generator *tg = pool->timing_generators[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

644

if (pool->opps[i]->funcs->dpg_is_blanked)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

645

s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

685

for (i = 0; i < pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

686

struct display_stream_compressor *dsc = pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

701

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

702

struct stream_encoder *enc = pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

752

if (pool->hpo_dp_stream_enc_count > 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

754

for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

756

struct hpo_dp_stream_encoder *hpo_dp_stream_enc = pool->hpo_dp_stream_enc[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

782

if (pool->hpo_dp_link_enc_count) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

785

for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

786

struct hpo_dp_link_encoder *hpo_dp_link_enc = pool->hpo_dp_link_enc[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

168

for (i = 0; i < pool->mpcc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

171

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

78

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

88

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

89

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

179

for (i = 0; i < pool->mpcc_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

182

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

183

mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

76

struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

87

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

88

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

142

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

148

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

153

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

174

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

193

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

200

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

74

void (*destroy)(struct resource_pool **pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

127

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

132

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

137

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

154

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

161

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

293

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

302

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

313

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

324

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

345

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

369

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

516

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

528

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

539

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

550

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

558

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

567

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

575

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

596

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

660

const struct resource_pool *const pool,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

99

struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1002

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1010

pool->base.res_cap = &res_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1011

pool->base.funcs = &dce100_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1012

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1017

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1020

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1022

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1024

pool->base.clock_sources[2] =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1026

pool->base.clk_src_count = 3;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1029

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1032

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1034

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1036

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1039

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1045

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1046

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1053

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1057

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1063

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1067

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1076

pool->base.irqs = dal_irq_service_dce110_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1077

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1084

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1085

pool->base.pipe_count = res_cap.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1086

pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1097

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1098

pool->base.timing_generators[i] =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1103

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1109

pool->base.mis[i] = dce100_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1110

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1117

pool->base.ipps[i] = dce100_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1118

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1125

pool->base.transforms[i] = dce100_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1126

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1133

pool->base.opps[i] = dce100_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1134

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1142

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1143

pool->base.engines[i] = dce100_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1144

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1150

pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1151

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1157

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1160

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1165

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1174

dce100_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1183

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1186

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1189

if (dce100_resource_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1190

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1192

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

757

static void dce100_resource_destruct(struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

761

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

762

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

763

dce110_opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

765

if (pool->base.transforms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

766

dce100_transform_destroy(&pool->base.transforms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

768

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

769

dce_ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

771

if (pool->base.mis[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

772

kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

773

pool->base.mis[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

776

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

777

kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

778

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

782

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

783

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

784

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

785

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

786

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

787

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

789

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

790

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

791

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

795

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

796

if (pool->base.stream_enc[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

797

kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

800

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

801

if (pool->base.clock_sources[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

802

dce100_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

805

if (pool->base.dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

806

dce100_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

808

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

809

if (pool->base.audios[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

810

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

813

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

814

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

816

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

817

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

819

if (pool->base.irqs != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

820

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

929

static void dce100_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

931

struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

935

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

949

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

956

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

958

pool->stream_enc[i]) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

963

if (pool->stream_enc[i]->id ==

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

965

return pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

983

return pool->stream_enc[j];

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

60

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1124

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1131

unsigned int underlay_idx = pool->underlay_pipe_index;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1137

pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1138

pipe_ctx->plane_res.mi = pool->mis[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1140

pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1141

pipe_ctx->stream_res.opp = pool->opps[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1191

static void dce110_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1193

struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1197

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1202

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1209

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1211

pool->stream_enc[i]) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1216

if (pool->stream_enc[i]->id ==

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1218

return pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1227

return pool->stream_enc[j];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1245

static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1270

pool->opps[pool->pipe_count] = &dce110_oppv->base;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1271

pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1272

pool->mis[pool->pipe_count] = &dce110_miv->base;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1273

pool->transforms[pool->pipe_count] = &dce110_xfmv->base;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1274

pool->pipe_count++;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1352

struct dce110_resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1361

pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1362

pool->base.funcs = &dce110_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1368

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1369

pool->base.underlay_pipe_index = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1370

pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1387

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1390

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1393

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1397

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1402

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1408

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1409

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1416

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1420

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1426

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1430

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1439

pool->base.irqs = dal_irq_service_dce110_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1440

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1444

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1445

pool->base.timing_generators[i] = dce110_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1447

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1453

pool->base.mis[i] = dce110_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1454

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1461

pool->base.ipps[i] = dce110_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1462

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1469

pool->base.transforms[i] = dce110_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1470

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1477

pool->base.opps[i] = dce110_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1478

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1486

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1487

pool->base.engines[i] = dce110_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1488

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1494

pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1495

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1501

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1507

if (!underlay_create(ctx, &pool->base))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1510

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1517

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1519

for (i = 0; i < pool->base.underlay_pipe_index; ++i)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1522

dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1531

dce110_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1540

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1543

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1546

if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1547

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1549

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

812

static void dce110_resource_destruct(struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

816

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

817

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

818

dce110_opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

820

if (pool->base.transforms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

821

dce110_transform_destroy(&pool->base.transforms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

823

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

824

dce_ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

826

if (pool->base.mis[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

827

kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

828

pool->base.mis[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

831

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

832

kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

833

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

837

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

838

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

839

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

840

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

841

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

842

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

844

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

845

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

846

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

850

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

851

if (pool->base.stream_enc[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

852

kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

855

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

856

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

857

dce110_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

861

if (pool->base.dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

862

dce110_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

864

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

865

if (pool->base.audios[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

866

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

870

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

871

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

873

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

874

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

876

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

877

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.h

34

#define TO_DCE110_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.h

35

container_of(pool, struct dce110_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.h

50

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1042

static void dce112_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1044

struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1048

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1226

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1233

pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1234

pool->base.funcs = &dce112_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1239

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1240

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1241

pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1255

pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1260

pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1265

pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1270

pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1275

pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1280

pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1285

pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1287

pool->base.dp_clock_source = dce112_clock_source_create(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1292

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1293

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1300

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1304

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1310

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1314

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1323

pool->base.irqs = dal_irq_service_dce110_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1324

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1328

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1329

pool->base.timing_generators[i] =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1334

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1340

pool->base.mis[i] = dce112_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1341

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1348

pool->base.ipps[i] = dce112_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1349

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1356

pool->base.transforms[i] = dce112_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1357

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1364

pool->base.opps[i] = dce112_opp_create(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1367

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1375

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1376

pool->base.engines[i] = dce112_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1377

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1383

pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1384

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1390

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1393

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1397

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1412

dce112_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1420

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1423

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1426

if (dce112_resource_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1427

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1429

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

777

static void dce112_resource_destruct(struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

781

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

782

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

783

dce110_opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

785

if (pool->base.transforms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

786

dce112_transform_destroy(&pool->base.transforms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

788

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

789

dce_ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

791

if (pool->base.mis[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

792

kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

793

pool->base.mis[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

796

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

797

kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

798

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

802

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

803

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

804

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

805

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

806

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

807

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

809

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

810

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

811

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

815

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

816

if (pool->base.stream_enc[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

817

kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

820

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

821

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

822

dce112_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

826

if (pool->base.dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

827

dce112_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

829

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

830

if (pool->base.audios[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

831

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

835

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

836

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

838

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

839

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

841

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

842

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

848

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

853

return pool->clock_sources[DCE112_CLK_SRC_PLL0];

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

855

return pool->clock_sources[DCE112_CLK_SRC_PLL1];

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

857

return pool->clock_sources[DCE112_CLK_SRC_PLL2];

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

859

return pool->clock_sources[DCE112_CLK_SRC_PLL3];

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

861

return pool->clock_sources[DCE112_CLK_SRC_PLL4];

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

863

return pool->clock_sources[DCE112_CLK_SRC_PLL5];

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1062

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1075

pool->base.res_cap = &res_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1076

pool->base.funcs = &dce120_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1079

pool->base.pipe_count = res_cap.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1080

pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1081

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1097

pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1101

pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1105

pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1109

pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1113

pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1117

pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1121

pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1123

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1128

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1129

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1136

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1140

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1146

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1150

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1158

pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1159

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1168

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1176

pool->base.timing_generators[j] =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1181

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1187

pool->base.mis[j] = dce120_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1189

if (pool->base.mis[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1196

pool->base.ipps[j] = dce120_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1197

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1204

pool->base.transforms[j] = dce120_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1205

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1212

pool->base.opps[j] = dce120_opp_create(

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1215

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1225

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1226

pool->base.engines[i] = dce120_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1227

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1233

pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1234

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1240

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1244

pool->base.pipe_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1245

pool->base.timing_generator_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1252

if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1259

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1274

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1284

dce120_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1293

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1296

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1299

if (dce120_resource_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1300

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1302

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

597

static void dce120_resource_destruct(struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

601

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

602

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

603

dce110_opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

605

if (pool->base.transforms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

606

dce120_transform_destroy(&pool->base.transforms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

608

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

609

dce_ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

611

if (pool->base.mis[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

612

kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

613

pool->base.mis[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

616

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

617

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

620

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

621

kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

622

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

626

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

627

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

628

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

629

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

630

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

631

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

633

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

634

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

635

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

639

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

640

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

641

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

644

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

645

if (pool->base.stream_enc[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

646

kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

649

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

650

if (pool->base.clock_sources[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

652

&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

655

if (pool->base.dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

656

dce120_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

658

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

659

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

661

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

662

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

664

if (pool->base.oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

665

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

667

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

902

static void dce120_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

904

struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

908

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1000

pool->base.ipps[i] = dce60_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1001

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1007

pool->base.transforms[i] = dce60_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1008

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1014

pool->base.opps[i] = dce60_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1015

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1022

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1023

pool->base.engines[i] = dce60_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1024

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1030

pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1031

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1037

pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1038

if (pool->base.sw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1046

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1053

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1063

dce60_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1071

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1074

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1077

if (dce60_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1078

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1080

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1088

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1096

pool->base.res_cap = &res_cap_61;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1097

pool->base.funcs = &dce60_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1103

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1104

pool->base.pipe_count = res_cap_61.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1105

pool->base.timing_generator_count = res_cap_61.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1118

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1121

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1123

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1125

pool->base.clock_sources[2] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1127

pool->base.clk_src_count = 3;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1130

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1133

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1135

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1137

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1140

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1146

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1147

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1154

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1158

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1164

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1168

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1177

pool->base.irqs = dal_irq_service_dce60_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1178

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1182

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1183

pool->base.timing_generators[i] = dce60_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1185

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1191

pool->base.mis[i] = dce60_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1192

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1198

pool->base.ipps[i] = dce60_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1199

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1205

pool->base.transforms[i] = dce60_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1206

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1212

pool->base.opps[i] = dce60_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1213

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1220

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1221

pool->base.engines[i] = dce60_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1222

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1228

pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1229

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1235

pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1236

if (pool->base.sw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1244

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1251

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1261

dce60_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1269

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1272

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1275

if (dce61_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1276

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1278

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1286

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1294

pool->base.res_cap = &res_cap_64;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1295

pool->base.funcs = &dce60_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1301

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1302

pool->base.pipe_count = res_cap_64.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1303

pool->base.timing_generator_count = res_cap_64.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1316

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1320

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1322

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1324

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1327

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1330

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1332

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1334

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1337

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1343

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1344

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1351

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1355

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1361

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1365

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1374

pool->base.irqs = dal_irq_service_dce60_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1375

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1379

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1380

pool->base.timing_generators[i] = dce60_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1382

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1388

pool->base.mis[i] = dce60_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1389

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1395

pool->base.ipps[i] = dce60_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1396

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1402

pool->base.transforms[i] = dce60_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1403

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1409

pool->base.opps[i] = dce60_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1410

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1417

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1418

pool->base.engines[i] = dce60_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1419

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1425

pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1426

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1432

pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1433

if (pool->base.sw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1441

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1448

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1458

dce60_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1466

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1469

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1472

if (dce64_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1473

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1475

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

798

static void dce60_resource_destruct(struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

802

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

803

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

804

dce110_opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

806

if (pool->base.transforms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

807

dce60_transform_destroy(&pool->base.transforms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

809

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

810

dce_ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

812

if (pool->base.mis[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

813

kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

814

pool->base.mis[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

817

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

818

kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

819

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

823

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

824

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

825

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

826

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

827

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

828

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

830

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

831

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

832

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

836

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

837

if (pool->base.stream_enc[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

838

kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

841

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

842

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

843

dce60_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

847

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

848

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

850

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

851

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

853

if (pool->base.dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

854

dce60_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

856

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

857

if (pool->base.audios[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

858

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

862

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

863

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

867

static void dce60_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

869

struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

873

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

890

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

898

pool->base.res_cap = &res_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

899

pool->base.funcs = &dce60_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

905

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

906

pool->base.pipe_count = res_cap.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

907

pool->base.timing_generator_count = res_cap.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

921

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

925

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

927

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

929

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

932

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

935

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

937

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

939

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

942

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

948

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

949

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

956

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

960

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

966

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

970

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

979

pool->base.irqs = dal_irq_service_dce60_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

980

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

984

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

985

pool->base.timing_generators[i] = dce60_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

987

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

993

pool->base.mis[i] = dce60_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

994

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1003

pool->base.mis[i] = dce80_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1004

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1010

pool->base.ipps[i] = dce80_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1011

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1017

pool->base.transforms[i] = dce80_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1018

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1024

pool->base.opps[i] = dce80_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1025

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1032

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1033

pool->base.engines[i] = dce80_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1034

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1040

pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1041

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1047

pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1048

if (pool->base.sw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1056

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1063

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1073

dce80_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1081

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1084

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1087

if (dce80_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1088

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1090

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1098

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1106

pool->base.res_cap = &res_cap_81;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1107

pool->base.funcs = &dce80_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1113

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1114

pool->base.pipe_count = res_cap_81.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1115

pool->base.timing_generator_count = res_cap_81.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1130

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1133

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1135

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1137

pool->base.clock_sources[2] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1139

pool->base.clk_src_count = 3;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1142

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1145

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1147

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1149

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1152

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1158

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1159

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1166

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1170

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1176

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1180

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1189

pool->base.irqs = dal_irq_service_dce80_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1190

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1194

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1195

pool->base.timing_generators[i] = dce80_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1197

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1203

pool->base.mis[i] = dce80_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1204

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1210

pool->base.ipps[i] = dce80_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1211

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1217

pool->base.transforms[i] = dce80_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1218

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1224

pool->base.opps[i] = dce80_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1225

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1232

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1233

pool->base.engines[i] = dce80_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1234

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1240

pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1241

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1247

pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1248

if (pool->base.sw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1256

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1263

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1273

dce80_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1281

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1284

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1287

if (dce81_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1288

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1290

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1298

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1306

pool->base.res_cap = &res_cap_83;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1307

pool->base.funcs = &dce80_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1313

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1314

pool->base.pipe_count = res_cap_83.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1315

pool->base.timing_generator_count = res_cap_83.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1331

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1334

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1336

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1338

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1341

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1344

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1346

pool->base.clk_src_count = 1;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1349

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1355

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1356

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1363

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1367

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1373

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1377

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1386

pool->base.irqs = dal_irq_service_dce80_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1387

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1391

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1392

pool->base.timing_generators[i] = dce80_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1394

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1400

pool->base.mis[i] = dce80_mem_input_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1401

if (pool->base.mis[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1407

pool->base.ipps[i] = dce80_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1408

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1414

pool->base.transforms[i] = dce80_transform_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1415

if (pool->base.transforms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1421

pool->base.opps[i] = dce80_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1422

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1429

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1430

pool->base.engines[i] = dce80_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1431

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1437

pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1438

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1444

pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1445

if (pool->base.sw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1453

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1460

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1470

dce80_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1478

struct dce110_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1481

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1484

if (dce83_construct(num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1485

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1487

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

804

static void dce80_resource_destruct(struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

808

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

809

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

810

dce110_opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

812

if (pool->base.transforms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

813

dce80_transform_destroy(&pool->base.transforms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

815

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

816

dce_ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

818

if (pool->base.mis[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

819

kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

820

pool->base.mis[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

823

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

824

kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

825

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

829

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

830

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

831

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

832

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

833

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

834

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

836

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

837

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

838

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

842

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

843

if (pool->base.stream_enc[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

844

kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

847

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

848

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

849

dce80_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

853

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

854

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

856

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

857

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

859

if (pool->base.dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

860

dce80_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

862

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

863

if (pool->base.audios[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

864

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

868

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

869

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

873

static void dce80_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

875

struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

879

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

896

struct dce110_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

904

pool->base.res_cap = &res_cap;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

905

pool->base.funcs = &dce80_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

911

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

912

pool->base.pipe_count = res_cap.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

913

pool->base.timing_generator_count = res_cap.num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

930

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

933

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

935

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

937

pool->base.clock_sources[2] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

939

pool->base.clk_src_count = 3;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

942

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

945

pool->base.clock_sources[0] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

947

pool->base.clock_sources[1] =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

949

pool->base.clk_src_count = 2;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

952

if (pool->base.dp_clock_source == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

958

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

959

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

966

pool->base.dmcu = dce_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

970

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

976

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

980

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

989

pool->base.irqs = dal_irq_service_dce80_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

990

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

994

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

995

pool->base.timing_generators[i] = dce80_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

997

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1082

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1087

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1102

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1103

idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1104

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1105

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1120

static void dcn10_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1122

struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1126

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1229

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1236

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1238

pool->stream_enc[i]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1243

if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1246

if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1248

return pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1250

if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && pool->stream_enc[i]->id ==

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1252

return pool->stream_enc[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1261

return pool->stream_enc[j];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1315

struct dcn10_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1328

pool->base.res_cap = &rv2_res_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1330

pool->base.res_cap = &res_cap;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1331

pool->base.funcs = &dcn10_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1341

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1344

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1347

pool->base.pipe_count = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1406

pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1410

pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1414

pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1420

pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1426

pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1429

pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1431

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1437

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1438

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1445

pool->base.dmcu = dcn10_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1449

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1455

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1459

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1491

pool->base.pp_smu = dcn10_pp_smu_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1497

if (pool->base.pp_smu != NULL

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1498

&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1540

dc->res_pool = &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1552

pool->base.irqs = dal_irq_service_dcn10_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1553

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1560

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1567

pool->base.hubps[j] = dcn10_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1568

if (pool->base.hubps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1575

pool->base.ipps[j] = dcn10_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1576

if (pool->base.ipps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1583

pool->base.dpps[j] = dcn10_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1584

if (pool->base.dpps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1591

pool->base.opps[j] = dcn10_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1592

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1599

pool->base.timing_generators[j] = dcn10_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1601

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1610

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1611

pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1612

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1618

pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1619

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1625

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1629

pool->base.pipe_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1630

pool->base.timing_generator_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1631

pool->base.mpcc_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1636

dc->dml.ip.max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1637

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1639

pool->base.mpc = dcn10_mpc_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1640

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1646

pool->base.hubbub = dcn10_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1647

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1653

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1658

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1669

dcn10_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1678

struct dcn10_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1681

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1684

if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1685

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1687

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

900

static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

904

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

905

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

906

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

907

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

911

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

912

kfree(TO_DCN10_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

913

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

916

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

917

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

919

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

920

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

921

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

923

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

924

dcn10_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

926

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

927

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

929

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

930

kfree(TO_DCN10_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

931

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

934

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

935

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

938

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

939

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

940

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

944

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

945

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

946

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

947

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

948

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

949

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

950

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

953

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

954

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

955

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

958

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

959

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

960

dcn10_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

961

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

965

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

966

dcn10_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

967

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

970

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

971

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

973

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

974

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

976

kfree(pool->base.pp_smu);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

32

#define TO_DCN10_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

33

container_of(pool, struct dcn10_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

51

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1082

static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1086

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1087

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1088

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1089

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1093

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1094

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1095

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1098

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1099

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1100

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1102

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1103

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1104

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1106

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1107

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1108

dcn20_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1110

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1111

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1113

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1114

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1115

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1118

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1119

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1123

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1124

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1125

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1126

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1127

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1128

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1130

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1131

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1132

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1136

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1137

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1138

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1141

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1142

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1143

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1144

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1148

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1149

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1150

kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1151

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1153

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1154

kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1155

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1159

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1160

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1161

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1164

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1165

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1166

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1167

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1171

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1172

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1173

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1177

if (pool->base.abm != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1178

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1180

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1181

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1183

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1184

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1186

if (pool->base.pp_smu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1187

dcn20_pp_smu_destroy(&pool->base.pp_smu);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1189

if (pool->base.oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1190

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1192

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1293

struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1295

if (pool->funcs->build_pipe_pix_clk_params) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1296

pool->funcs->build_pipe_pix_clk_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1331

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1338

if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1339

*dsc = pool->dscs[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1352

for (i = 0; i < pool->res_cap->num_dsc; i++)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1354

*dsc = pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1361

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1366

for (i = 0; i < pool->res_cap->num_dsc; i++)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1367

if (pool->dscs[i] == *dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1485

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1490

next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1491

next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1492

next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1493

next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1494

next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1495

next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1520

next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1535

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1546

secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1547

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1548

secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1549

secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1550

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1551

secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1680

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2148

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2153

struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2164

sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2165

sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2166

sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2167

sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2183

static void dcn20_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2185

struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2189

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2212

const struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2215

dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2237

bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2240

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2255

pool->dwbc[i] = &dwbc20->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2260

bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2263

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2282

pool->mcif_wb[i] = &mcif_wb20->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2338

struct dcn20_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2347

if (pool->base.pp_smu) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2355

if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2356

status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2357

(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2362

if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2363

status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2364

(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2383

loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2384

loaded_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2394

struct dcn20_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2408

pool->base.funcs = &dcn20_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2411

pool->base.res_cap = &res_cap_nv14;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2412

pool->base.pipe_count = 5;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2413

pool->base.mpcc_count = 5;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2415

pool->base.res_cap = &res_cap_nv10;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2416

pool->base.pipe_count = 6;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2417

pool->base.mpcc_count = 6;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2422

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2490

pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2494

pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2498

pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2502

pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2506

pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2510

pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2514

pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2516

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2521

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2522

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2529

pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2530

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2536

pool->base.dmcu = dcn20_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2540

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2546

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2550

if (pool->base.abm == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2556

pool->base.pp_smu = dcn20_pp_smu_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2559

if (!init_soc_bounding_box(dc, pool)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2606

if (pool->base.pp_smu && pool->base.pp_smu->nv_funcs.set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2607

pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2611

pool->base.irqs = dal_irq_service_dcn20_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2612

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2616

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2617

pool->base.hubps[i] = dcn20_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2618

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2625

pool->base.ipps[i] = dcn20_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2626

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2633

pool->base.dpps[i] = dcn20_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2634

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2641

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2642

pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2643

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2649

pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2650

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2656

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2659

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2660

pool->base.opps[i] = dcn20_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2661

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2669

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2670

pool->base.timing_generators[i] = dcn20_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2672

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2679

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2681

pool->base.mpc = dcn20_mpc_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2682

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2688

pool->base.hubbub = dcn20_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2689

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2695

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2696

pool->base.dscs[i] = dcn20_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2697

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2704

if (!dcn20_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2709

if (!dcn20_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2715

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2734

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2749

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2751

pool->base.oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2758

dcn20_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2767

struct dcn20_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2770

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2773

if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2774

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2777

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

114

bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

115

bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

133

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

138

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

152

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

32

#define TO_DCN20_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

33

container_of(pool, struct dcn20_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

64

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

68

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1002

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1007

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1021

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1022

idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1023

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1024

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1048

static void dcn201_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1050

struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1054

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1089

struct dcn201_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1096

pool->base.res_cap = &res_cap_dnc201;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1097

pool->base.funcs = &dcn201_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1102

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1104

pool->base.pipe_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1105

pool->base.mpcc_count = 5;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1164

pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1168

pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1173

pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1176

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1181

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1182

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1188

pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1189

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1194

dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1195

dcn201_ip.max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1200

pool->base.irqs = dal_irq_service_dcn201_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1201

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1206

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1207

pool->base.hubps[i] = dcn201_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1208

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1214

pool->base.ipps[i] = dcn201_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1215

if (pool->base.ipps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1221

pool->base.dpps[i] = dcn201_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1222

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1229

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1230

pool->base.opps[i] = dcn201_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1231

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1238

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1239

pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1240

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1245

pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1246

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1251

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1254

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1255

pool->base.timing_generators[i] = dcn201_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1257

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1263

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1265

pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1266

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1271

pool->base.hubbub = dcn201_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1272

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1277

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1283

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1296

dcn201_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1305

struct dcn201_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1308

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1311

if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1312

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1314

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

910

static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

914

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

915

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

916

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

917

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

922

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

923

kfree(TO_DCN201_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

924

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

927

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

928

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

929

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

932

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

933

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

934

dcn201_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

936

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

937

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

939

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

940

kfree(TO_DCN10_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

941

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

944

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

945

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

949

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

950

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

951

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

954

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

955

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

956

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

957

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

960

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

961

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

962

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

965

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

966

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

967

dcn201_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

968

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

972

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

973

dcn201_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

974

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

977

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

978

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

36

#define TO_DCN201_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

37

container_of(pool, struct dcn201_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1387

struct dcn21_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1397

pool->base.res_cap = &res_cap_rn;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1399

pool->base.funcs = &dcn21_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1404

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1407

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1473

pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1477

pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1481

pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1485

pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1489

pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1494

pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1497

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1502

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1503

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1510

pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1511

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1518

pool->base.dmcu = dcn21_dmcu_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1522

if (pool->base.dmcu == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1532

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1534

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1542

pool->base.abm = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1547

pool->base.abm = dce_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1552

pool->base.pp_smu = dcn21_pp_smu_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1565

pool->base.irqs = dal_irq_service_dcn21_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1566

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1571

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1578

pool->base.hubps[j] = dcn21_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1579

if (pool->base.hubps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1586

pool->base.ipps[j] = dcn21_ipp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1587

if (pool->base.ipps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1594

pool->base.dpps[j] = dcn21_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1595

if (pool->base.dpps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1602

pool->base.opps[j] = dcn21_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1603

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1610

pool->base.timing_generators[j] = dcn21_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1612

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1620

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1621

pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1622

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1628

pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1629

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1635

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1638

pool->base.timing_generator_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1639

pool->base.pipe_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1640

pool->base.mpcc_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1642

pool->base.mpc = dcn21_mpc_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1643

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1649

pool->base.hubbub = dcn21_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1650

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1656

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1657

pool->base.dscs[i] = dcn21_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1658

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1665

if (!dcn20_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1670

if (!dcn20_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1676

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1682

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1695

dcn21_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1704

struct dcn21_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1707

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1710

if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1711

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1714

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

653

static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

657

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

658

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

659

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

660

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

664

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

665

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

666

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

669

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

670

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

671

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

673

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

674

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

675

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

677

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

678

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

679

dcn20_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

681

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

682

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

684

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

685

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

686

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

689

if (pool->base.irqs != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

690

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

693

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

694

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

695

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

696

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

697

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

698

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

700

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

701

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

702

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

706

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

707

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

708

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

711

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

712

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

713

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

714

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

718

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

719

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

720

kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

721

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

723

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

724

kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

725

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

729

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

730

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

731

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

734

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

735

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

736

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

737

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

741

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

742

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

743

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

746

if (pool->base.abm != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

747

if (pool->base.abm->ctx->dc->config.disable_dmcu)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

748

dmub_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

750

dce_abm_destroy(&pool->base.abm);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

753

if (pool->base.dmcu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

754

dce_dmcu_destroy(&pool->base.dmcu);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

756

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

757

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

759

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

760

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

762

if (pool->base.pp_smu != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

763

dcn21_pp_smu_destroy(&pool->base.pp_smu);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

944

static void dcn21_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

946

struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

950

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

31

#define TO_DCN21_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

32

container_of(pool, struct dcn21_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1065

static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1069

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1070

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1071

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1072

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1073

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1075

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1076

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1077

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1079

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1080

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1084

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1085

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1086

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1089

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1090

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1091

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1093

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1094

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1095

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1097

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1098

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1099

dcn30_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1101

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1102

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1104

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1105

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1106

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1109

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1110

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1114

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1115

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1116

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1117

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1118

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1119

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1121

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1122

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1123

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1127

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1128

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1129

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1132

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1133

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1134

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1135

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1139

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1140

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1141

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1142

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1144

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1145

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1146

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1150

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1151

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1152

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1155

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1156

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1157

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1158

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1162

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1163

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1164

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1165

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1167

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1168

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1169

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1173

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1174

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1175

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1178

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1179

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1180

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1183

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1184

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1186

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1187

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1189

if (pool->base.oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1190

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1192

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1215

static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1218

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1235

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1240

static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1243

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1260

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1286

static void dcn30_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1288

struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1292

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1430

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1443

for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1445

*lut = pool->mpc_lut[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1446

*shaper = pool->mpc_shaper[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1447

state = &pool->mpc_lut[i]->state;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1466

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1473

for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1474

if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1476

pool->mpc_lut[i]->state.raw = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1497

struct dcn30_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1509

loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1510

loaded_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1528

const struct resource_pool *pool = dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1533

sec_pipe->plane_res.mi = pool->mis[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1534

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1535

sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1536

sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1537

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1538

sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1558

sec_pipe->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2271

struct dcn30_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2291

pool->base.res_cap = &res_cap_dcn3;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2293

pool->base.funcs = &dcn30_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2298

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2299

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2300

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2345

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2390

pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2394

pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2398

pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2402

pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2406

pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2410

pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2415

pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2418

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2423

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2424

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2432

pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2433

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2440

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2455

pool->base.irqs = dal_irq_service_dcn30_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2456

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2460

pool->base.hubbub = dcn30_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2461

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2468

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2469

pool->base.hubps[i] = dcn30_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2470

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2477

pool->base.dpps[i] = dcn30_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2478

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2486

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2487

pool->base.opps[i] = dcn30_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2488

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2496

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2497

pool->base.timing_generators[i] = dcn30_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2499

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2505

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2507

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2509

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2516

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2517

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2521

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2528

pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2529

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2535

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2536

pool->base.dscs[i] = dcn30_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2537

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2545

if (!dcn30_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2551

if (!dcn30_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2558

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2559

pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2560

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2566

pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2567

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2573

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2577

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2584

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2599

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2601

pool->base.oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2611

dcn30_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2620

struct dcn30_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2623

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2626

if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2627

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2630

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

31

#define TO_DCN30_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

32

container_of(pool, struct dcn30_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

85

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

92

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1036

static void dcn301_destruct(struct dcn301_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1040

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1041

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1042

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1043

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1044

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1046

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1047

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1048

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1050

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1051

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1055

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1056

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1057

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1060

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1061

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1062

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1064

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1065

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1066

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1068

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1069

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1070

dcn301_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1072

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1073

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1075

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1076

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1077

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1080

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1081

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1085

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1086

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1087

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1088

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1089

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1090

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1092

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1093

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1094

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1098

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1099

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1100

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1103

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1104

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1105

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1106

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1110

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1111

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1112

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1113

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1115

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1116

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1117

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1121

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1122

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1123

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1126

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1127

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1128

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1129

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1133

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1134

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1135

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1136

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1138

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1139

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1140

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1144

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1145

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1146

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1149

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1150

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1151

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1154

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1155

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1175

static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1178

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1195

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1200

static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1203

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1220

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1241

static void dcn301_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1243

struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1247

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1290

struct dcn301_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1302

loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1303

loaded_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1410

struct dcn301_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1424

pool->base.res_cap = &res_cap_dcn301;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1426

pool->base.funcs = &dcn301_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1431

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1432

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1433

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1474

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1514

pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1518

pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1522

pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1526

pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1531

pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1534

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1539

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1540

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1548

pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1549

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1555

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1557

if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1558

set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1573

pool->base.irqs = dal_irq_service_dcn30_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1574

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1578

pool->base.hubbub = dcn301_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1579

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1587

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1597

pool->base.hubps[j] = dcn301_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1598

if (pool->base.hubps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1605

pool->base.dpps[j] = dcn301_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1606

if (pool->base.dpps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1613

pool->base.opps[j] = dcn301_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1614

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1621

pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1622

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1629

pool->base.timing_generator_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1630

pool->base.pipe_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1631

pool->base.mpcc_count = j;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1635

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1636

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1640

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1648

pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1649

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1655

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1656

pool->base.dscs[i] = dcn301_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1657

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1665

if (!dcn301_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1671

if (!dcn301_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1678

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1679

pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1680

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1686

pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1687

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1693

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1697

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1704

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1717

dcn301_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1726

struct dcn301_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1729

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1732

if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1733

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1736

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

92

#define TO_DCN301_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

93

container_of(pool, struct dcn301_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1000

pool->stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1002

kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1003

pool->stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1007

for (i = 0; i < pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1008

if (pool->dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1009

dcn20_dsc_destroy(&pool->dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1012

if (pool->mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1013

kfree(TO_DCN20_MPC(pool->mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1014

pool->mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1017

if (pool->hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1018

kfree(pool->hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1019

pool->hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1022

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1023

if (pool->dpps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1024

kfree(TO_DCN20_DPP(pool->dpps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1025

pool->dpps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1028

if (pool->hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1029

kfree(TO_DCN20_HUBP(pool->hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1030

pool->hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1033

if (pool->irqs != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1034

dal_irq_service_destroy(&pool->irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1037

for (i = 0; i < pool->res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1038

if (pool->engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1039

dce110_engine_destroy(&pool->engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1040

if (pool->hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1041

kfree(pool->hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1042

pool->hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1044

if (pool->sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1045

kfree(pool->sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1046

pool->sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1050

for (i = 0; i < pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1051

if (pool->opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1052

pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1055

for (i = 0; i < pool->res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1056

if (pool->timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1057

kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1058

pool->timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1062

for (i = 0; i < pool->res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1063

if (pool->dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1064

kfree(TO_DCN30_DWBC(pool->dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1065

pool->dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1067

if (pool->mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1068

kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1069

pool->mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1073

for (i = 0; i < pool->audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1074

if (pool->audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1075

dce_aud_destroy(&pool->audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1078

for (i = 0; i < pool->clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1079

if (pool->clock_sources[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1080

dcn20_clock_source_destroy(&pool->clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1083

if (pool->dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1084

dcn20_clock_source_destroy(&pool->dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1086

for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1087

if (pool->mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1088

dc_3dlut_func_release(pool->mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1089

pool->mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1091

if (pool->mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1092

dc_transfer_func_release(pool->mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1093

pool->mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1097

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1098

if (pool->multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1099

dce_abm_destroy(&pool->multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1102

if (pool->psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1103

dmub_psr_destroy(&pool->psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1105

if (pool->dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1106

dcn_dccg_destroy(&pool->dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1108

if (pool->oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1109

struct dc *dc = pool->oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1111

dc->link_srv->destroy_ddc_service(&pool->oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1115

static void dcn302_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1117

dcn302_resource_destruct(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1118

kfree(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1119

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1201

struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1210

pool->res_cap = &res_cap_dcn302;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1212

pool->funcs = &dcn302_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1217

pool->underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1218

pool->pipe_count = pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1219

pool->mpcc_count = pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1265

dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1306

pool->clock_sources[DCN302_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1310

pool->clock_sources[DCN302_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1314

pool->clock_sources[DCN302_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1318

pool->clock_sources[DCN302_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1322

pool->clock_sources[DCN302_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1327

pool->clk_src_count = DCN302_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1330

pool->dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1335

for (i = 0; i < pool->clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1336

if (pool->clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1344

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1345

if (pool->dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1352

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1359

pool->irqs = dal_irq_service_dcn302_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1360

if (!pool->irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1364

pool->hubbub = dcn302_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1365

if (pool->hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1372

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1373

pool->hubps[i] = dcn302_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1374

if (pool->hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1380

pool->dpps[i] = dcn302_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1381

if (pool->dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1388

for (i = 0; i < pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1389

pool->opps[i] = dcn302_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1390

if (pool->opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1397

for (i = 0; i < pool->res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1398

pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1399

if (pool->timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1405

pool->timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1408

pool->psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1409

if (pool->psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1416

for (i = 0; i < pool->res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1417

pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1418

if (pool->multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1426

pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1427

if (pool->mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1433

for (i = 0; i < pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1434

pool->dscs[i] = dcn302_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1435

if (pool->dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1443

if (!dcn302_dwbc_create(ctx, pool)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1449

if (!dcn302_mmhubbub_create(ctx, pool)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1456

for (i = 0; i < pool->res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1457

pool->engines[i] = dcn302_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1458

if (pool->engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1463

pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1464

if (pool->hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1469

pool->sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1473

if (!resource_construct(num_virtual_links, dc, pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1480

dc->caps.max_planes = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1495

pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1497

pool->oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1504

dcn302_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1511

struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1513

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1516

if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1517

return pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1520

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

708

static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

711

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

723

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

743

static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

746

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

758

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

954

static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

966

loaded_ip->max_num_otg = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

967

loaded_ip->max_num_dpp = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

988

static void dcn302_resource_destruct(struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

992

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

993

if (pool->stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

994

if (pool->stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

995

kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

996

pool->stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

998

if (pool->stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

999

kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1000

if (pool->timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1001

kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1002

pool->timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1006

for (i = 0; i < pool->res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1007

if (pool->dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1008

kfree(TO_DCN30_DWBC(pool->dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1009

pool->dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1011

if (pool->mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1012

kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1013

pool->mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1017

for (i = 0; i < pool->audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1018

if (pool->audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1019

dce_aud_destroy(&pool->audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1022

for (i = 0; i < pool->clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1023

if (pool->clock_sources[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1024

dcn20_clock_source_destroy(&pool->clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1027

if (pool->dp_clock_source != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1028

dcn20_clock_source_destroy(&pool->dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1030

for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1031

if (pool->mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1032

dc_3dlut_func_release(pool->mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1033

pool->mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1035

if (pool->mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1036

dc_transfer_func_release(pool->mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1037

pool->mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1041

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1042

if (pool->multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1043

dce_abm_destroy(&pool->multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1046

if (pool->psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1047

dmub_psr_destroy(&pool->psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1049

if (pool->dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1050

dcn_dccg_destroy(&pool->dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1052

if (pool->oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1053

struct dc *dc = pool->oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1055

dc->link_srv->destroy_ddc_service(&pool->oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1059

static void dcn303_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1061

dcn303_resource_destruct(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1062

kfree(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1063

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1142

struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1151

pool->res_cap = &res_cap_dcn303;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1153

pool->funcs = &dcn303_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1158

pool->underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1159

pool->pipe_count = pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1160

pool->mpcc_count = pool->res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1209

dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1250

pool->clock_sources[DCN303_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1254

pool->clock_sources[DCN303_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1259

pool->clk_src_count = DCN303_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1262

pool->dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1267

for (i = 0; i < pool->clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1268

if (pool->clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1276

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1277

if (pool->dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1284

init_soc_bounding_box(dc, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1291

pool->irqs = dal_irq_service_dcn303_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1292

if (!pool->irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1296

pool->hubbub = dcn303_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1297

if (pool->hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1304

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1305

pool->hubps[i] = dcn303_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1306

if (pool->hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1312

pool->dpps[i] = dcn303_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1313

if (pool->dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1320

for (i = 0; i < pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1321

pool->opps[i] = dcn303_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1322

if (pool->opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1329

for (i = 0; i < pool->res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1330

pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1331

if (pool->timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1337

pool->timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1340

pool->psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1341

if (pool->psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1348

for (i = 0; i < pool->res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1349

pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1350

if (pool->multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1358

pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1359

if (pool->mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1365

for (i = 0; i < pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1366

pool->dscs[i] = dcn303_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1367

if (pool->dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1375

if (!dcn303_dwbc_create(ctx, pool)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1381

if (!dcn303_mmhubbub_create(ctx, pool)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1388

for (i = 0; i < pool->res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1389

pool->engines[i] = dcn303_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1390

if (pool->engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1395

pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1396

if (pool->hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1401

pool->sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1405

if (!resource_construct(num_virtual_links, dc, pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1412

dc->caps.max_planes = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1427

pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1429

pool->oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1436

dcn303_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1443

struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1445

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1448

if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1449

return pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1452

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

669

static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

672

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

684

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

704

static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

707

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

719

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

899

static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

911

loaded_ip->max_num_otg = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

912

loaded_ip->max_num_dpp = pool->pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

932

static void dcn303_resource_destruct(struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

936

for (i = 0; i < pool->stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

937

if (pool->stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

938

if (pool->stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

939

kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

940

pool->stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

942

if (pool->stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

943

kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

944

pool->stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

946

kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

947

pool->stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

951

for (i = 0; i < pool->res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

952

if (pool->dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

953

dcn20_dsc_destroy(&pool->dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

956

if (pool->mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

957

kfree(TO_DCN20_MPC(pool->mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

958

pool->mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

961

if (pool->hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

962

kfree(pool->hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

963

pool->hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

966

for (i = 0; i < pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

967

if (pool->dpps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

968

kfree(TO_DCN20_DPP(pool->dpps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

969

pool->dpps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

972

if (pool->hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

973

kfree(TO_DCN20_HUBP(pool->hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

974

pool->hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

977

if (pool->irqs != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

978

dal_irq_service_destroy(&pool->irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

981

for (i = 0; i < pool->res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

982

if (pool->engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

983

dce110_engine_destroy(&pool->engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

984

if (pool->hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

985

kfree(pool->hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

986

pool->hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

988

if (pool->sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

989

kfree(pool->sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

990

pool->sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

994

for (i = 0; i < pool->res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

995

if (pool->opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

996

pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

999

for (i = 0; i < pool->res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1344

static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1348

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1349

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1350

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1351

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1352

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1354

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1355

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1356

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1358

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1359

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1363

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1364

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1365

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1366

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1367

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1369

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1370

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1371

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1373

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1374

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1378

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1379

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1380

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1381

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1385

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1386

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1387

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1390

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1391

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1392

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1394

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1395

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1396

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1398

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1399

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1400

dcn31_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1402

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1403

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1405

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1406

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1407

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1410

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1411

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1415

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1416

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1417

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1418

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1419

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1420

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1422

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1423

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1424

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1428

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1429

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1430

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1433

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1434

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1435

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1436

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1440

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1441

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1442

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1443

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1445

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1446

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1447

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1451

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1452

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1453

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1456

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1457

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1458

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1459

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1463

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1464

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1465

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1466

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1468

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1469

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1470

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1474

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1475

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1476

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1479

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1480

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1481

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1484

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1485

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1487

if (pool->base.replay != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1488

dmub_replay_destroy(&pool->base.replay);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1490

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1491

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1513

static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1516

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1533

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1538

static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1541

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1558

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1578

static void dcn31_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1580

struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1584

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1885

struct dcn31_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1893

pool->base.res_cap = &res_cap_dcn31;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1895

pool->base.funcs = &dcn31_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1900

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1901

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1902

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1950

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1994

pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1998

pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2004

pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2008

pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2013

pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2017

pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2023

pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2028

pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2031

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2036

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2037

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2045

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2046

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2054

pool->base.irqs = dal_irq_service_dcn31_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2055

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2059

pool->base.hubbub = dcn31_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2060

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2067

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2068

pool->base.hubps[i] = dcn31_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2069

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2076

pool->base.dpps[i] = dcn31_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2077

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2085

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2086

pool->base.opps[i] = dcn31_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2087

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2095

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2096

pool->base.timing_generators[i] = dcn31_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2098

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2104

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2107

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2108

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2115

pool->base.replay = dmub_replay_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2116

if (pool->base.replay == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2123

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2124

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2128

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2136

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2137

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2143

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2144

pool->base.dscs[i] = dcn31_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2145

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2153

if (!dcn31_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2159

if (!dcn31_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2166

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2167

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2168

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2174

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2175

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2181

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2188

pool->base.usb4_dpia_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2192

pool->base.usb4_dpia_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2195

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2202

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2216

dcn31_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2225

struct dcn31_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2228

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2231

if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2232

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2235

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

31

#define TO_DCN31_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

32

container_of(pool, struct dcn31_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1403

static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1407

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1408

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1409

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1410

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1411

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1413

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1414

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1415

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1417

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1418

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1422

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1423

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1424

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1425

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1426

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1428

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1429

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1430

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1432

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1433

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1437

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1438

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1439

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1440

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1444

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1445

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1446

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1449

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1450

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1451

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1453

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1454

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1455

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1457

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1458

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1459

dcn31_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1461

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1462

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1464

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1465

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1466

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1469

if (pool->base.irqs != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1470

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1473

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1474

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1475

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1476

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1477

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1478

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1480

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1481

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1482

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1486

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1487

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1488

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1491

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1492

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1493

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1494

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1498

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1499

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1500

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1501

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1503

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1504

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1505

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1509

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1510

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1511

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1514

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1515

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1516

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1517

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1521

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1522

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1523

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1524

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1526

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1527

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1528

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1532

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1533

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1534

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1537

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1538

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1539

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1542

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1543

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1545

if (pool->base.replay != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1546

dmub_replay_destroy(&pool->base.replay);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1548

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1549

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1571

static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1574

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1591

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1596

static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1599

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1616

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1636

static void dcn314_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1638

struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1642

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1816

struct dcn314_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1824

pool->base.res_cap = &res_cap_dcn314;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1825

pool->base.funcs = &dcn314_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1830

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1831

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1832

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1881

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1933

pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1937

pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1941

pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1945

pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1949

pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1954

pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1957

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1962

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1963

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1970

pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1971

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1978

pool->base.irqs = dal_irq_service_dcn314_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1979

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1983

pool->base.hubbub = dcn31_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1984

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1991

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1992

pool->base.hubps[i] = dcn31_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1993

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2000

pool->base.dpps[i] = dcn31_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2001

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2009

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2010

pool->base.opps[i] = dcn31_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2011

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2019

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2020

pool->base.timing_generators[i] = dcn31_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2022

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2028

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2031

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2032

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2039

pool->base.replay = dmub_replay_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2040

if (pool->base.replay == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2047

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2048

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2052

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2060

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2061

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2067

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2068

pool->base.dscs[i] = dcn314_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2069

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2077

if (!dcn31_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2083

if (!dcn31_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2090

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2091

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2092

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2098

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2099

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2105

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2109

pool->base.usb4_dpia_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2112

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2119

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2134

dcn314_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2143

struct dcn314_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2146

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2149

if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2150

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2153

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

35

#define TO_DCN314_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

36

container_of(pool, struct dcn314_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1344

static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1348

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1349

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1350

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1351

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1352

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1354

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1355

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1356

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1358

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1359

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1363

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1364

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1365

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1366

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1367

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1369

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1370

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1371

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1373

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1374

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1378

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1379

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1380

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1381

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1385

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1386

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1387

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1390

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1391

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1392

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1394

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1395

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1396

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1398

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1399

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1400

dcn31_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1402

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1403

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1405

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1406

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1407

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1410

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1411

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1415

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1416

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1417

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1418

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1419

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1420

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1422

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1423

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1424

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1428

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1429

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1430

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1433

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1434

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1435

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1436

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1440

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1441

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1442

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1443

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1445

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1446

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1447

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1451

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1452

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1453

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1456

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1457

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1458

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1459

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1463

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1464

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1465

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1466

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1468

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1469

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1470

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1474

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1475

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1476

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1479

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1480

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1481

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1484

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1485

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1487

if (pool->base.replay != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1488

dmub_replay_destroy(&pool->base.replay);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1490

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1491

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1513

static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1516

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1533

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1538

static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1541

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1558

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1578

static void dcn315_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1580

struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1584

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1855

struct dcn315_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1863

pool->base.res_cap = &res_cap_dcn31;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1865

pool->base.funcs = &dcn315_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1870

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1871

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1872

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1918

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1955

pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1959

pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1963

pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1967

pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1971

pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1976

pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1979

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1984

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1985

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1993

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1994

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2002

pool->base.irqs = dal_irq_service_dcn315_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2003

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2007

pool->base.hubbub = dcn31_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2008

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2015

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2016

pool->base.hubps[i] = dcn31_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2017

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2024

pool->base.dpps[i] = dcn31_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2025

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2033

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2034

pool->base.opps[i] = dcn31_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2035

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2043

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2044

pool->base.timing_generators[i] = dcn31_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2046

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2052

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2055

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2056

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2063

pool->base.replay = dmub_replay_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2064

if (pool->base.replay == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2071

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2072

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2076

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2084

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2085

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2091

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2092

pool->base.dscs[i] = dcn31_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2093

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2101

if (!dcn31_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2107

if (!dcn31_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2114

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2115

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2116

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2122

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2123

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2129

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2133

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2140

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2155

dcn315_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2164

struct dcn315_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2167

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2170

if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2171

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2174

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.h

31

#define TO_DCN315_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.h

32

container_of(pool, struct dcn315_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1340

static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1344

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1345

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1346

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1347

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1348

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1350

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1351

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1352

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1354

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1355

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1359

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1360

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1361

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1362

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1363

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1365

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1366

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1367

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1369

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1370

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1374

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1375

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1376

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1377

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1381

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1382

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1383

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1386

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1387

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1388

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1390

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1391

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1392

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1394

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1395

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1396

dcn31_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1398

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1399

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1401

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1402

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1403

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1406

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1407

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1411

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1412

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1413

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1414

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1415

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1416

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1418

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1419

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1420

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1424

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1425

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1426

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1429

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1430

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1431

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1432

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1436

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1437

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1438

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1439

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1441

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1442

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1443

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1447

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1448

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1449

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1452

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1453

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1454

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1455

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1459

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1460

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1461

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1462

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1464

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1465

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1466

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1470

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1471

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1472

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1475

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1476

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1477

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1480

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1481

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1483

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1484

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1506

static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1509

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1526

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1531

static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1534

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1551

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1571

static void dcn316_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1573

struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1577

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1731

struct dcn316_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1739

pool->base.res_cap = &res_cap_dcn31;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1741

pool->base.funcs = &dcn316_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1746

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1747

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1748

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1794

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1831

pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1835

pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1839

pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1843

pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1847

pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1852

pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1855

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1860

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1861

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1869

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1870

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1878

pool->base.irqs = dal_irq_service_dcn31_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1879

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1883

pool->base.hubbub = dcn31_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1884

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1891

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1892

pool->base.hubps[i] = dcn31_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1893

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1900

pool->base.dpps[i] = dcn31_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1901

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1909

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1910

pool->base.opps[i] = dcn31_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1911

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1919

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1920

pool->base.timing_generators[i] = dcn31_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1922

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1928

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1931

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1932

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1939

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1940

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1944

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1952

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1953

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1959

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1960

pool->base.dscs[i] = dcn31_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1961

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1969

if (!dcn31_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1975

if (!dcn31_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1982

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1983

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1984

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1990

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1991

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1997

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2001

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2008

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2023

dcn316_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2032

struct dcn316_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2035

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2038

if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2039

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2042

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.h

31

#define TO_DCN316_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.h

32

container_of(pool, struct dcn316_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1350

static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1354

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1355

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1356

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1357

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1358

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1360

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1361

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1362

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1364

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1365

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1369

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1370

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1371

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1372

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1373

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1375

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1376

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1377

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1379

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1380

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1384

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1385

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1386

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1387

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1391

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1392

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1393

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1396

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1397

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1398

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1400

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1401

kfree(TO_DCN20_HUBBUB(pool->base.hubbub));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1402

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1404

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1405

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1406

dcn32_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1408

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1409

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1411

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1412

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1413

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1416

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1417

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1421

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1422

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1423

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1424

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1425

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1426

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1428

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1429

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1430

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1434

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1435

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1436

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1439

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1440

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1441

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1442

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1446

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1447

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1448

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1449

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1451

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1452

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1453

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1457

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1458

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1459

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1462

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1463

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1464

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1465

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1469

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1470

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1471

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1472

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1474

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1475

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1476

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1480

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1481

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1482

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1485

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1486

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1487

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1490

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1491

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1493

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1494

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1496

if (pool->base.oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1497

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1499

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1504

static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1507

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1528

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1533

static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1536

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1557

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1587

static void dcn32_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1589

struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1593

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1598

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1610

*lut = pool->mpc_lut[mpcc_id];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1611

*shaper = pool->mpc_shaper[mpcc_id];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1620

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1627

for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1628

if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1630

pool->mpc_lut[i]->state.raw = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2134

struct dcn32_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2168

pool->base.res_cap = &res_cap_dcn32;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2170

num_pipes = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2173

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2189

pool->base.funcs = &dcn32_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2194

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2195

pool->base.timing_generator_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2196

pool->base.pipe_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2197

pool->base.mpcc_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2269

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2313

pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2317

pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2321

pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2325

pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2329

pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2334

pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2337

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2342

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2343

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2351

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2352

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2363

pool->base.irqs = dal_irq_service_dcn32_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2364

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2368

pool->base.hubbub = dcn32_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2369

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2376

for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2385

pool->base.hubps[j] = dcn32_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2386

if (pool->base.hubps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2394

pool->base.dpps[j] = dcn32_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2395

if (pool->base.dpps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2403

pool->base.opps[j] = dcn32_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2404

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2412

pool->base.timing_generators[j] = dcn32_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2414

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2421

pool->base.multiple_abms[j] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2425

if (pool->base.multiple_abms[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2436

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2437

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2444

pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2445

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2452

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2453

pool->base.dscs[i] = dcn32_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2454

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2462

if (!dcn32_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2469

if (!dcn32_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2476

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2477

pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2478

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2484

pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2485

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2491

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2495

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2502

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2517

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2519

pool->base.oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2522

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2529

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2562

dcn32_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2571

struct dcn32_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2574

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2577

if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2578

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2581

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2630

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2646

cur_res_ctx, new_res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2656

cur_res_ctx, new_res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2659

free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2666

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2701

preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2714

for (i = pool->pipe_count - 1; i >= 0; i--) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2728

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2754

idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2763

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2764

idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2765

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2766

idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2774

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2790

cur_res_ctx, new_res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2793

free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2801

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2810

new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2814

pool, opp_head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2822

free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2823

free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2824

free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2826

pool->dpps[free_pipe->pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2838

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2843

pool, otg_master);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2852

free_pipe->stream_res.opp = pool->opps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2853

free_pipe->plane_res.mi = pool->mis[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2854

free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2855

free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2856

free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2857

free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2858

free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

143

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

149

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

155

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

160

const struct resource_pool *pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

47

#define TO_DCN32_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

48

container_of(pool, struct dcn32_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

84

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

91

const struct resource_pool *pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1331

static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1335

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1336

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1337

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1338

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1339

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1341

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1342

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1343

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1345

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1346

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1350

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1351

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1352

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1353

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1354

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1356

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1357

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1358

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1360

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1361

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1365

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1366

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1367

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1368

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1372

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1373

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1374

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1377

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1378

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1379

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1381

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1382

kfree(TO_DCN20_HUBBUB(pool->base.hubbub));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1383

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1385

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1386

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1387

dcn321_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1389

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1390

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1392

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1393

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1394

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1397

if (pool->base.irqs != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1398

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1401

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1402

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1403

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1404

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1405

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1406

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1408

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1409

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1410

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1414

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1415

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1416

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1419

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1420

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1421

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1422

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1426

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1427

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1428

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1429

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1431

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1432

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1433

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1437

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1438

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1439

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1442

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1443

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1444

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1445

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1449

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1450

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1451

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1452

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1454

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1455

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1456

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1460

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1461

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1462

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1465

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1466

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1467

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1470

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1471

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1473

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1474

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1476

if (pool->base.oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1477

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1479

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1484

static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1487

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1508

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1513

static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1516

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1537

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1567

static void dcn321_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1569

struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1573

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1637

struct dcn321_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1672

pool->base.res_cap = &res_cap_dcn321;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1674

num_pipes = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1677

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1693

pool->base.funcs = &dcn321_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1698

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1699

pool->base.timing_generator_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1700

pool->base.pipe_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1701

pool->base.mpcc_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1769

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1813

pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1817

pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1821

pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1825

pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1829

pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1834

pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1837

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1842

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1843

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1851

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1852

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1863

pool->base.irqs = dal_irq_service_dcn32_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1864

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1868

pool->base.hubbub = dcn321_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1869

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1876

for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1884

pool->base.hubps[j] = dcn321_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1885

if (pool->base.hubps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1892

pool->base.dpps[j] = dcn321_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1893

if (pool->base.dpps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1900

pool->base.opps[j] = dcn321_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1901

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1908

pool->base.timing_generators[j] = dcn321_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1910

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1916

pool->base.multiple_abms[j] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1920

if (pool->base.multiple_abms[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1931

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1932

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1939

pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1940

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1947

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1948

pool->base.dscs[i] = dcn321_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1949

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1957

if (!dcn321_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1964

if (!dcn321_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1971

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1972

pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1973

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1979

pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1980

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1986

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1990

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1997

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2012

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2014

pool->base.oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2017

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2024

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2053

dcn321_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2062

struct dcn321_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2065

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2068

if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2069

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2072

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.h

31

#define TO_DCN321_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.h

32

container_of(pool, struct dcn321_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1413

static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1417

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1418

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1419

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1420

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1421

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1423

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1424

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1425

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1427

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1428

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1432

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1433

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1434

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1435

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1436

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1438

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1439

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1440

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1442

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1443

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1447

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1448

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1449

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1450

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1454

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1455

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1456

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1459

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1460

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1461

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1463

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1464

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1465

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1467

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1468

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1469

dcn35_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1471

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1472

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1474

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1475

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1476

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1479

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1480

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1484

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1485

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1486

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1487

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1488

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1489

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1491

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1492

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1493

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1497

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1498

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1499

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1502

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1503

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1504

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1505

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1509

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1510

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1511

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1512

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1514

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1515

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1516

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1520

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1521

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1522

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1525

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1526

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1527

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1528

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1532

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1533

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1534

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1535

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1537

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1538

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1539

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1543

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1544

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1545

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1548

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1549

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1550

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1553

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1554

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1556

if (pool->base.replay != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1557

dmub_replay_destroy(&pool->base.replay);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1559

if (pool->base.pg_cntl != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1560

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1562

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1563

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1598

static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1601

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1622

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1637

static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1640

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1663

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1692

static void dcn35_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1694

struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1698

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1811

struct dcn35_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1842

pool->base.res_cap = &res_cap_dcn35;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1844

pool->base.funcs = &dcn35_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1849

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1850

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1851

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1904

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1963

pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1967

pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1971

pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1975

pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1979

pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1984

pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1987

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1992

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1993

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2003

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2004

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2014

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2015

if (pool->base.pg_cntl == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2023

pool->base.irqs = dal_irq_service_dcn35_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2024

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2028

pool->base.hubbub = dcn35_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2029

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2036

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2037

pool->base.hubps[i] = dcn35_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2038

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2045

pool->base.dpps[i] = dcn35_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2046

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2054

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2055

pool->base.opps[i] = dcn35_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2056

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2064

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2065

pool->base.timing_generators[i] = dcn35_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2067

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2073

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2076

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2077

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2084

pool->base.replay = dmub_replay_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2085

if (pool->base.replay == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2092

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2093

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2097

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2105

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2106

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2112

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2113

pool->base.dscs[i] = dcn35_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2114

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2122

if (!dcn35_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2128

if (!dcn35_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2135

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2136

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2137

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2143

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2144

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2150

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2154

pool->base.usb4_dpia_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2156

pool->base.usb4_dpia_count = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2159

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2166

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2175

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2177

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2198

dcn35_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2207

struct dcn35_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2210

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2213

if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2214

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2217

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

33

#define TO_DCN35_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

34

container_of(pool, struct dcn35_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1393

static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1397

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1398

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1399

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1400

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1401

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1403

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1404

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1405

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1407

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1408

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1412

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1413

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1414

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1415

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1416

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1418

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1419

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1420

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1422

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1423

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1427

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1428

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1429

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1430

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1434

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1435

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1436

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1439

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1440

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1441

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1443

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1444

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1445

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1447

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1448

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1449

dcn35_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1451

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1452

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1454

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1455

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1456

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1459

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1460

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1464

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1465

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1466

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1467

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1468

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1469

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1471

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1472

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1473

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1477

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1478

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1479

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1482

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1483

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1484

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1485

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1489

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1490

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1491

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1492

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1494

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1495

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1496

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1500

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1501

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1502

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1505

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1506

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1507

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1508

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1512

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1513

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1514

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1515

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1517

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1518

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1519

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1523

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1524

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1525

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1528

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1529

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1530

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1533

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1534

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1536

if (pool->base.replay != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1537

dmub_replay_destroy(&pool->base.replay);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1539

if (pool->base.pg_cntl != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1540

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1542

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1543

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1578

static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1581

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1602

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1617

static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1620

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1643

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1672

static void dcn351_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1674

struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1678

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1784

struct dcn351_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1815

pool->base.res_cap = &res_cap_dcn351;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1817

pool->base.funcs = &dcn351_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1822

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1823

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1824

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1877

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1935

pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1939

pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1943

pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1947

pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1951

pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1956

pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1959

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1964

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1965

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1975

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1976

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1986

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1987

if (pool->base.pg_cntl == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1995

pool->base.irqs = dal_irq_service_dcn351_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1996

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2000

pool->base.hubbub = dcn35_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2001

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2008

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2009

pool->base.hubps[i] = dcn35_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2010

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2017

pool->base.dpps[i] = dcn35_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2018

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2026

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2027

pool->base.opps[i] = dcn35_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2028

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2036

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2037

pool->base.timing_generators[i] = dcn35_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2039

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2045

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2048

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2049

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2056

pool->base.replay = dmub_replay_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2057

if (pool->base.replay == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2064

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2065

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2069

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2077

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2078

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2084

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2085

pool->base.dscs[i] = dcn35_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2086

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2094

if (!dcn35_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2100

if (!dcn35_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2107

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2108

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2109

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2115

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2116

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2122

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2126

pool->base.usb4_dpia_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2128

pool->base.usb4_dpia_count = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2131

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2138

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2148

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2150

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2171

dcn351_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2180

struct dcn351_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2183

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2186

if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2187

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2190

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.h

12

#define TO_DCN351_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.h

13

container_of(pool, struct dcn351_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1394

static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1398

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1399

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1400

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1401

kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1402

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1404

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1405

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1406

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1408

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1409

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1413

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1414

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1415

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1416

kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1417

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1419

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1420

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1421

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1423

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1424

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1428

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1429

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1430

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1431

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1435

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1436

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1437

dcn20_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1440

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1441

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1442

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1444

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1445

kfree(pool->base.hubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1446

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1448

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1449

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1450

dcn35_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1452

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1453

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1455

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1456

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1457

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1460

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1461

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1465

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1466

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1467

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1468

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1469

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1470

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1472

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1473

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1474

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1478

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1479

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1480

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1483

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1484

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1485

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1486

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1490

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1491

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1492

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1493

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1495

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1496

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1497

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1501

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1502

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1503

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1506

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1507

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1508

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1509

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1513

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1514

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1515

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1516

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1518

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1519

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1520

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1524

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1525

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1526

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1529

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1530

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1531

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1534

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1535

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1537

if (pool->base.replay != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1538

dmub_replay_destroy(&pool->base.replay);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1540

if (pool->base.pg_cntl != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1541

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1543

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1544

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1579

static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1582

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1603

pool->dwbc[i] = &dwbc30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1618

static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1621

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1644

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1673

static void dcn36_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1675

struct dcn36_resource_pool *dcn36_pool = TO_DCN36_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1679

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1784

struct dcn36_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1815

pool->base.res_cap = &res_cap_dcn36;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1817

pool->base.funcs = &dcn36_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1822

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1823

pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1824

pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1877

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1936

pool->base.clock_sources[DCN36_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1940

pool->base.clock_sources[DCN36_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1944

pool->base.clock_sources[DCN36_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1948

pool->base.clock_sources[DCN36_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1952

pool->base.clock_sources[DCN36_CLK_SRC_PLL4] =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1957

pool->base.clk_src_count = DCN36_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1960

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1965

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1966

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1976

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1977

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1987

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1988

if (pool->base.pg_cntl == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1996

pool->base.irqs = dal_irq_service_dcn36_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1997

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2001

pool->base.hubbub = dcn35_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2002

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2009

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2010

pool->base.hubps[i] = dcn35_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2011

if (pool->base.hubps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2018

pool->base.dpps[i] = dcn35_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2019

if (pool->base.dpps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2027

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2028

pool->base.opps[i] = dcn35_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2029

if (pool->base.opps[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2037

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2038

pool->base.timing_generators[i] = dcn35_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2040

if (pool->base.timing_generators[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2046

pool->base.timing_generator_count = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2049

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2050

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2057

pool->base.replay = dmub_replay_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2058

if (pool->base.replay == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2065

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2066

pool->base.multiple_abms[i] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2070

if (pool->base.multiple_abms[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2078

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2079

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2085

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2086

pool->base.dscs[i] = dcn35_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2087

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2095

if (!dcn35_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2101

if (!dcn35_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2108

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2109

pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2110

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2116

pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2117

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2123

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2127

pool->base.usb4_dpia_count = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2129

pool->base.usb4_dpia_count = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2132

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2139

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2148

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2150

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2171

dcn36_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2180

struct dcn36_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2183

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2186

if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2187

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2190

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h

12

#define TO_DCN36_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.h

13

container_of(pool, struct dcn36_resource_pool, base)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1353

static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1357

for (i = 0; i < pool->base.stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1358

if (pool->base.stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1359

if (pool->base.stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1360

kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1361

pool->base.stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1363

if (pool->base.stream_enc[i]->afmt != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1364

kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1365

pool->base.stream_enc[i]->afmt = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1367

kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1368

pool->base.stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1372

for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1373

if (pool->base.hpo_dp_stream_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1374

if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1375

kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1376

pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1378

if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1379

kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1380

pool->base.hpo_dp_stream_enc[i]->apg = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1382

kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1383

pool->base.hpo_dp_stream_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1387

for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1388

if (pool->base.hpo_dp_link_enc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1389

kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1390

pool->base.hpo_dp_link_enc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1394

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1395

if (pool->base.dscs[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1396

dcn401_dsc_destroy(&pool->base.dscs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1399

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1400

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1401

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1403

if (pool->base.hubbub != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1404

kfree(TO_DCN20_HUBBUB(pool->base.hubbub));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1405

pool->base.hubbub = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1407

for (i = 0; i < pool->base.pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1408

if (pool->base.dpps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1409

dcn401_dpp_destroy(&pool->base.dpps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1411

if (pool->base.ipps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1412

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1414

if (pool->base.hubps[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1415

kfree(TO_DCN20_HUBP(pool->base.hubps[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1416

pool->base.hubps[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1419

if (pool->base.irqs != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1420

dal_irq_service_destroy(&pool->base.irqs);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1424

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1425

if (pool->base.engines[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1426

dce110_engine_destroy(&pool->base.engines[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1427

if (pool->base.hw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1428

kfree(pool->base.hw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1429

pool->base.hw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1431

if (pool->base.sw_i2cs[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1432

kfree(pool->base.sw_i2cs[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1433

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1437

for (i = 0; i < pool->base.res_cap->num_opp; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1438

if (pool->base.opps[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1439

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1442

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1443

if (pool->base.timing_generators[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1444

kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1445

pool->base.timing_generators[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1449

for (i = 0; i < pool->base.res_cap->num_dwb; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1450

if (pool->base.dwbc[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1451

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1452

pool->base.dwbc[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1454

if (pool->base.mcif_wb[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1455

kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1456

pool->base.mcif_wb[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1460

for (i = 0; i < pool->base.audio_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1461

if (pool->base.audios[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1462

dce_aud_destroy(&pool->base.audios[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1465

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1466

if (pool->base.clock_sources[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1467

dcn20_clock_source_destroy(&pool->base.clock_sources[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1468

pool->base.clock_sources[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1472

for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1473

if (pool->base.mpc_lut[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1474

dc_3dlut_func_release(pool->base.mpc_lut[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1475

pool->base.mpc_lut[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1477

if (pool->base.mpc_shaper[i] != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1478

dc_transfer_func_release(pool->base.mpc_shaper[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1479

pool->base.mpc_shaper[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1483

if (pool->base.dp_clock_source != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1484

dcn20_clock_source_destroy(&pool->base.dp_clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1485

pool->base.dp_clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1488

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1489

if (pool->base.multiple_abms[i] != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1490

dce_abm_destroy(&pool->base.multiple_abms[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1493

if (pool->base.psr != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1494

dmub_psr_destroy(&pool->base.psr);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1496

if (pool->base.dccg != NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1497

dcn_dccg_destroy(&pool->base.dccg);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1499

if (pool->base.oem_device != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1500

struct dc *dc = pool->base.oem_device->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1502

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1507

static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1510

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1532

pool->dwbc[i] = &dwbc401->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1538

static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1541

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1562

pool->mcif_wb[i] = &mcif_wb30->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1595

static void dcn401_destroy_resource_pool(struct resource_pool **pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1597

struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1601

*pool = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1820

struct dcn401_resource_pool *pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1853

pool->base.res_cap = &res_cap_dcn4_01;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1856

num_pipes = pool->base.res_cap->num_timing_generator;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1859

for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1869

pool->base.funcs = &dcn401_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1874

pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1875

pool->base.timing_generator_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1876

pool->base.pipe_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1877

pool->base.mpcc_count = num_pipes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1947

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2011

pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2015

pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2019

pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2023

pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2032

pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2035

pool->base.dp_clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2040

for (i = 0; i < pool->base.clk_src_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2041

if (pool->base.clock_sources[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2049

pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2050

if (pool->base.dccg == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2058

pool->base.irqs = dal_irq_service_dcn401_create(&init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2059

if (!pool->base.irqs)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2063

pool->base.hubbub = dcn401_hubbub_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2064

if (pool->base.hubbub == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2071

for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2079

pool->base.hubps[j] = dcn401_hubp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2080

if (pool->base.hubps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2087

pool->base.dpps[j] = dcn401_dpp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2088

if (pool->base.dpps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2095

pool->base.opps[j] = dcn401_opp_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2096

if (pool->base.opps[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2103

pool->base.timing_generators[j] = dcn401_timing_generator_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2105

if (pool->base.timing_generators[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2111

pool->base.multiple_abms[j] = dmub_abm_create(ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2115

if (pool->base.multiple_abms[j] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2126

pool->base.psr = dmub_psr_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2127

if (pool->base.psr == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2134

pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2135

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2142

for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2143

pool->base.dscs[i] = dcn401_dsc_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2144

if (pool->base.dscs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2152

if (!dcn401_dwbc_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2159

if (!dcn401_mmhubbub_create(ctx, &pool->base)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2166

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2167

pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2168

if (pool->base.engines[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2174

pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2175

if (pool->base.hw_i2cs[i] == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2181

pool->base.sw_i2cs[i] = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2185

if (!resource_construct(num_virtual_links, dc, &pool->base,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2192

dc->caps.max_planes = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2207

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2209

pool->base.oem_device = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2216

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2225

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2257

dcn401_resource_destruct(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2266

struct dcn401_resource_pool *pool =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2269

if (!pool)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2272

if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2273

return &pool->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2276

kfree(pool);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

12

#define TO_DCN401_RES_POOL(pool)\

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

13

container_of(pool, struct dcn401_resource_pool, base)

sys/dev/pci/drm/apple/apldcp.c

124

struct pool task_pool;

sys/dev/pci/drm/drm_buddy.c

23

static struct pool slab_blocks;

sys/dev/pci/drm/drm_linux.c

1044

struct pool xa_pool;

sys/dev/pci/drm/drm_linux.c

806

struct pool idr_pool;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

91

static struct pool slab_luts;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2265

struct intel_gt_buffer_pool_node *pool = eb->batch_pool;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2298

if (!pool) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2299

pool = intel_gt_get_buffer_pool(eb->gt, len,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2301

if (IS_ERR(pool))

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2302

return PTR_ERR(pool);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2303

eb->batch_pool = pool;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2306

err = i915_gem_object_lock(pool->obj, &eb->ww);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2310

shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2314

intel_gt_buffer_pool_mark_used(pool);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2316

shadow->private = pool;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2322

shadow = shadow_batch_pin(eb, pool->obj,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2328

shadow->private = pool;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

46

static struct pool slab_objects;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

331

return ttm_pool_alloc(&bdev->pool, ttm, ctx);

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

348

ttm_pool_free(&bdev->pool, ttm);

sys/dev/pci/drm/i915/gt/intel_context.c

18

static struct pool slab_ce;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

103

struct intel_gt_buffer_pool *pool = node->pool;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

104

struct intel_gt *gt = container_of(pool, struct intel_gt, buffer_pool);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

105

struct list_head *list = bucket_for_size(pool, node->obj->base.size);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

117

spin_lock_irqsave(&pool->lock, flags);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

120

spin_unlock_irqrestore(&pool->lock, flags);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

122

queue_delayed_work(gt->i915->unordered_wq, &pool->work,

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

140

node_create(struct intel_gt_buffer_pool *pool, size_t sz,

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

143

struct intel_gt *gt = container_of(pool, struct intel_gt, buffer_pool);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

15

bucket_for_size(struct intel_gt_buffer_pool *pool, size_t sz)

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

153

node->pool = pool;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

175

struct intel_gt_buffer_pool *pool = &gt->buffer_pool;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

181

list = bucket_for_size(pool, size);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

198

spin_lock_irq(&pool->lock);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

200

spin_unlock_irq(&pool->lock);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

207

node = node_create(pool, size, type);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

223

struct intel_gt_buffer_pool *pool = &gt->buffer_pool;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

226

mtx_init(&pool->lock, IPL_TTY);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

227

for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

228

INIT_LIST_HEAD(&pool->cache_list[n]);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

229

INIT_DELAYED_WORK(&pool->work, pool_free_work);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

234

struct intel_gt_buffer_pool *pool = &gt->buffer_pool;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

237

while (pool_free_older_than(pool, 0))

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

239

} while (cancel_delayed_work_sync(&pool->work));

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

244

struct intel_gt_buffer_pool *pool = &gt->buffer_pool;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

247

for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

248

GEM_BUG_ON(!list_empty(&pool->cache_list[n]));

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

25

if (n >= ARRAY_SIZE(pool->cache_list))

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

26

n = ARRAY_SIZE(pool->cache_list) - 1;

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

28

return &pool->cache_list[n];

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

38

static bool pool_free_older_than(struct intel_gt_buffer_pool *pool, long keep)

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

45

for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

46

struct list_head *list = &pool->cache_list[n];

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

51

if (spin_trylock_irq(&pool->lock)) {

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

74

spin_unlock_irq(&pool->lock);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

90

struct intel_gt_buffer_pool *pool =

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

91

container_of(wrk, typeof(*pool), work.work);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

92

struct intel_gt *gt = container_of(pool, struct intel_gt, buffer_pool);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

94

if (pool_free_older_than(pool, HZ))

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

95

queue_delayed_work(gt->i915->unordered_wq, &pool->work,

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool_types.h

27

struct intel_gt_buffer_pool *pool;

sys/dev/pci/drm/i915/i915_active.c

24

static struct pool slab_cache;

sys/dev/pci/drm/i915/i915_gpu_error.c

1304

pool_free(&compress->pool, page_address(page));

sys/dev/pci/drm/i915/i915_gpu_error.c

1815

pool_refill(&compress->pool, ALLOW_FAIL);

sys/dev/pci/drm/i915/i915_gpu_error.c

273

struct folio_batch pool;

sys/dev/pci/drm/i915/i915_gpu_error.c

282

if (intel_pool_init(&c->pool, ALLOW_FAIL))

sys/dev/pci/drm/i915/i915_gpu_error.c

289

pool_fini(&c->pool);

sys/dev/pci/drm/i915/i915_gpu_error.c

295

c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);

sys/dev/pci/drm/i915/i915_gpu_error.c

317

page_addr = pool_alloc(&c->pool, ALLOW_FAIL);

sys/dev/pci/drm/i915/i915_gpu_error.c

398

pool_free(&c->pool, c->tmp);

sys/dev/pci/drm/i915/i915_gpu_error.c

399

pool_fini(&c->pool);

sys/dev/pci/drm/i915/i915_gpu_error.c

410

struct folio_batch pool;

sys/dev/pci/drm/i915/i915_gpu_error.c

415

return intel_pool_init(&c->pool, ALLOW_FAIL) == 0;

sys/dev/pci/drm/i915/i915_gpu_error.c

433

ptr = pool_alloc(&c->pool, ALLOW_FAIL);

sys/dev/pci/drm/i915/i915_gpu_error.c

458

pool_fini(&c->pool);

sys/dev/pci/drm/i915/i915_request.c

113

struct pool *i915_request_slab_cache(void)

sys/dev/pci/drm/i915/i915_request.c

57

static struct pool slab_requests;

sys/dev/pci/drm/i915/i915_request.c

58

static struct pool slab_execute_cbs;

sys/dev/pci/drm/i915/i915_request.h

375

struct pool *i915_request_slab_cache(void);

sys/dev/pci/drm/i915/i915_scheduler.c

13

static struct pool slab_dependencies;

sys/dev/pci/drm/i915/i915_scheduler.c

14

static struct pool slab_priorities;

sys/dev/pci/drm/i915/i915_vma.c

59

static struct pool slab_vmas;

sys/dev/pci/drm/i915/i915_vma_resource.c

16

static struct pool slab_vma_resources;

sys/dev/pci/drm/include/drm/drm_device.h

366

struct pool objpl;

sys/dev/pci/drm/include/drm/ttm/ttm_device.h

251

struct ttm_pool pool;

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

102

long ttm_pool_backup(struct ttm_pool *pool, struct ttm_tt *ttm,

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

104

int ttm_pool_restore_and_alloc(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

58

struct ttm_pool *pool;

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

90

int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

92

void ttm_pool_free(struct ttm_pool *pool, struct ttm_tt *tt);

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

94

void ttm_pool_init(struct ttm_pool *pool, struct device *dev,

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

96

void ttm_pool_fini(struct ttm_pool *pool);

sys/dev/pci/drm/include/drm/ttm/ttm_pool.h

98

int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m);

sys/dev/pci/drm/radeon/radeon_ttm.c

565

return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx);

sys/dev/pci/drm/radeon/radeon_ttm.c

585

return ttm_pool_free(&rdev->mman.bdev.pool, ttm);

sys/dev/pci/drm/radeon/radeon_ttm.c

819

return ttm_pool_debugfs(&rdev->mman.bdev.pool, m);

sys/dev/pci/drm/scheduler/sched_fence.c

36

static struct pool sched_fence_slab;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

541

ttm_pool_alloc(&priv->ttm_dev->pool, old_tt, &ctx);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

158

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

170

pool = &ttm_dev->pool;

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

171

KUNIT_ASSERT_NOT_NULL(test, pool);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

172

KUNIT_EXPECT_PTR_EQ(test, pool->dev, priv->dev);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

173

KUNIT_EXPECT_EQ(test, pool->use_dma_alloc, params->use_dma_alloc);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

174

KUNIT_EXPECT_EQ(test, pool->use_dma32, params->use_dma32);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

179

pt = pool->caching[i].orders[j];

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

180

KUNIT_EXPECT_PTR_EQ(test, pt.pool, pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

140

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

150

pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

151

KUNIT_ASSERT_NOT_NULL(test, pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

153

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, params->use_dma_alloc,

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

156

KUNIT_ASSERT_PTR_EQ(test, pool->dev, devs->dev);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

157

KUNIT_ASSERT_EQ(test, pool->nid, NUMA_NO_NODE);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

158

KUNIT_ASSERT_EQ(test, pool->use_dma_alloc, params->use_dma_alloc);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

160

err = ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

190

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

192

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

201

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

218

pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

219

KUNIT_ASSERT_NOT_NULL(test, pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

221

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

223

err = ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

233

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

235

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

241

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

248

pool = ttm_pool_pre_populated(test, size, caching);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

250

pt = &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

256

err = ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

261

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

263

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

269

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

277

pool = ttm_pool_pre_populated(test, size, pool_caching);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

279

pt_pool = &pool->caching[pool_caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

280

pt_tt = &pool->caching[tt_caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

288

err = ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

291

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

297

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

303

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

311

pool = ttm_pool_pre_populated(test, fst_size, caching);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

313

pt_pool = &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

314

pt_tt = &pool->caching[caching].orders[0];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

322

err = ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

325

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

331

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

339

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

348

pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

349

KUNIT_ASSERT_NOT_NULL(test, pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

351

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

352

ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

354

pt = &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

357

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

362

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

370

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

379

pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

380

KUNIT_ASSERT_NOT_NULL(test, pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

382

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, false, false);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

383

ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

385

pt = &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

388

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

393

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

398

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

404

pool = ttm_pool_pre_populated(test, size, caching);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

405

pt = &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

409

ttm_pool_fini(pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

79

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

86

pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

87

KUNIT_ASSERT_NOT_NULL(test, pool);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

89

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

91

err = ttm_pool_alloc(pool, tt, &simple_ctx);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

94

ttm_pool_free(pool, tt);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

97

return pool;

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

364

err = ttm_pool_alloc(&devs->ttm_dev->pool, tt, &ctx);

sys/dev/pci/drm/ttm/ttm_bo.c

309

queue_work_node(bdev->pool.nid, bdev->wq, &bo->delayed_delete);

sys/dev/pci/drm/ttm/ttm_device.c

238

ttm_pool_init(&bdev->pool, dev, nid, use_dma_alloc, use_dma32);

sys/dev/pci/drm/ttm/ttm_device.c

274

ttm_pool_fini(&bdev->pool);

sys/dev/pci/drm/ttm/ttm_pool.c

1015

tt->restore->pool = pool;

sys/dev/pci/drm/ttm/ttm_pool.c

1031

return __ttm_pool_alloc(pool, tt, ctx, &alloc, tt->restore);

sys/dev/pci/drm/ttm/ttm_pool.c

1042

void ttm_pool_free(struct ttm_pool *pool, struct ttm_tt *tt)

sys/dev/pci/drm/ttm/ttm_pool.c

1044

ttm_pool_free_range(pool, tt, tt->caching, 0, tt->num_pages);

sys/dev/pci/drm/ttm/ttm_pool.c

1075

ttm_pool_unmap_and_free(restore->pool, restore->alloced_page,

sys/dev/pci/drm/ttm/ttm_pool.c

1090

ttm_pool_free_range(restore->pool, tt, tt->caching,

sys/dev/pci/drm/ttm/ttm_pool.c

1093

ttm_pool_free_range(restore->pool, tt, ttm_cached,

sys/dev/pci/drm/ttm/ttm_pool.c

110

struct ttm_pool *pool;

sys/dev/pci/drm/ttm/ttm_pool.c

1123

long ttm_pool_backup(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/ttm/ttm_pool.c

1139

pool->use_dma_alloc || ttm_tt_is_backed_up(tt))

sys/dev/pci/drm/ttm/ttm_pool.c

1159

order = ttm_pool_page_order(pool, page);

sys/dev/pci/drm/ttm/ttm_pool.c

1165

ttm_pool_unmap(pool, tt->dma_address[i],

sys/dev/pci/drm/ttm/ttm_pool.c

1182

if (pool->use_dma32)

sys/dev/pci/drm/ttm/ttm_pool.c

1202

ttm_pool_split_for_swap(pool, page);

sys/dev/pci/drm/ttm/ttm_pool.c

1235

void ttm_pool_init(struct ttm_pool *pool, struct device *dev,

sys/dev/pci/drm/ttm/ttm_pool.c

1242

pool->dev = dev;

sys/dev/pci/drm/ttm/ttm_pool.c

1243

pool->nid = nid;

sys/dev/pci/drm/ttm/ttm_pool.c

1244

pool->use_dma_alloc = use_dma_alloc;

sys/dev/pci/drm/ttm/ttm_pool.c

1245

pool->use_dma32 = use_dma32;

sys/dev/pci/drm/ttm/ttm_pool.c

1252

pt = ttm_pool_select_type(pool, i, j);

sys/dev/pci/drm/ttm/ttm_pool.c

1253

if (pt != &pool->caching[i].orders[j])

sys/dev/pci/drm/ttm/ttm_pool.c

1256

ttm_pool_type_init(pt, pool, i, j);

sys/dev/pci/drm/ttm/ttm_pool.c

1282

void ttm_pool_fini(struct ttm_pool *pool)

sys/dev/pci/drm/ttm/ttm_pool.c

1290

pt = ttm_pool_select_type(pool, i, j);

sys/dev/pci/drm/ttm/ttm_pool.c

1291

if (pt != &pool->caching[i].orders[j])

sys/dev/pci/drm/ttm/ttm_pool.c

141

static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags,

sys/dev/pci/drm/ttm/ttm_pool.c

1414

int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m)

sys/dev/pci/drm/ttm/ttm_pool.c

1418

if (!pool->use_dma_alloc && pool->nid == NUMA_NO_NODE) {

sys/dev/pci/drm/ttm/ttm_pool.c

1427

if (!ttm_pool_select_type(pool, i, 0))

sys/dev/pci/drm/ttm/ttm_pool.c

1429

if (pool->use_dma_alloc)

sys/dev/pci/drm/ttm/ttm_pool.c

1432

seq_printf(m, "N%d ", pool->nid);

sys/dev/pci/drm/ttm/ttm_pool.c

1444

ttm_pool_debugfs_orders(pool->caching[i].orders, m);

sys/dev/pci/drm/ttm/ttm_pool.c

157

if (!pool->use_dma_alloc) {

sys/dev/pci/drm/ttm/ttm_pool.c

158

p = alloc_pages_node(pool->nid, gfp_flags, order);

sys/dev/pci/drm/ttm/ttm_pool.c

171

vaddr = dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE,

sys/dev/pci/drm/ttm/ttm_pool.c

194

static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching,

sys/dev/pci/drm/ttm/ttm_pool.c

209

if (!pool || !pool->use_dma_alloc) {

sys/dev/pci/drm/ttm/ttm_pool.c

219

dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr,

sys/dev/pci/drm/ttm/ttm_pool.c

226

static struct vm_page *ttm_pool_alloc_page(struct ttm_pool *pool,

sys/dev/pci/drm/ttm/ttm_pool.c

237

if (pool->use_dma32) {

sys/dev/pci/drm/ttm/ttm_pool.c

286

static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching,

sys/dev/pci/drm/ttm/ttm_pool.c

333

static int ttm_pool_map(struct ttm_pool *pool, unsigned int order,

sys/dev/pci/drm/ttm/ttm_pool.c

338

if (pool->use_dma_alloc) {

sys/dev/pci/drm/ttm/ttm_pool.c

345

addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL);

sys/dev/pci/drm/ttm/ttm_pool.c

346

if (dma_mapping_error(pool->dev, addr))

sys/dev/pci/drm/ttm/ttm_pool.c

356

static void ttm_pool_unmap(struct ttm_pool *pool, dma_addr_t dma_addr,

sys/dev/pci/drm/ttm/ttm_pool.c

360

if (pool->use_dma_alloc)

sys/dev/pci/drm/ttm/ttm_pool.c

363

dma_unmap_page(pool->dev, dma_addr, (long)num_pages << PAGE_SHIFT,

sys/dev/pci/drm/ttm/ttm_pool.c

369

static int ttm_pool_map(struct ttm_pool *pool, unsigned int order,

sys/dev/pci/drm/ttm/ttm_pool.c

384

static void ttm_pool_unmap(struct ttm_pool *pool, dma_addr_t dma_addr,

sys/dev/pci/drm/ttm/ttm_pool.c

434

static void ttm_pool_type_init(struct ttm_pool_type *pt, struct ttm_pool *pool,

sys/dev/pci/drm/ttm/ttm_pool.c

437

pt->pool = pool;

sys/dev/pci/drm/ttm/ttm_pool.c

460

ttm_pool_free_page(pt->pool, pt->caching, pt->order, p);

sys/dev/pci/drm/ttm/ttm_pool.c

470

static struct ttm_pool_type *ttm_pool_select_type(struct ttm_pool *pool,

sys/dev/pci/drm/ttm/ttm_pool.c

474

if (pool->use_dma_alloc)

sys/dev/pci/drm/ttm/ttm_pool.c

475

return &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/ttm_pool.c

480

if (pool->nid != NUMA_NO_NODE)

sys/dev/pci/drm/ttm/ttm_pool.c

481

return &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/ttm_pool.c

483

if (pool->use_dma32)

sys/dev/pci/drm/ttm/ttm_pool.c

488

if (pool->nid != NUMA_NO_NODE)

sys/dev/pci/drm/ttm/ttm_pool.c

489

return &pool->caching[caching].orders[order];

sys/dev/pci/drm/ttm/ttm_pool.c

491

if (pool->use_dma32)

sys/dev/pci/drm/ttm/ttm_pool.c

518

ttm_pool_free_page(pt->pool, pt->caching, pt->order, p);

sys/dev/pci/drm/ttm/ttm_pool.c

531

static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct vm_page *p)

sys/dev/pci/drm/ttm/ttm_pool.c

533

if (pool->use_dma_alloc) {

sys/dev/pci/drm/ttm/ttm_pool.c

549

static void ttm_pool_split_for_swap(struct ttm_pool *pool, struct vm_page *p)

sys/dev/pci/drm/ttm/ttm_pool.c

553

unsigned int order = ttm_pool_page_order(pool, p);

sys/dev/pci/drm/ttm/ttm_pool.c

595

static pgoff_t ttm_pool_unmap_and_free(struct ttm_pool *pool, struct vm_page *page,

sys/dev/pci/drm/ttm/ttm_pool.c

603

if (pool) {

sys/dev/pci/drm/ttm/ttm_pool.c

605

order = ttm_pool_page_order(pool, page);

sys/dev/pci/drm/ttm/ttm_pool.c

611

ttm_pool_unmap(pool, *dma_addr, nr);

sys/dev/pci/drm/ttm/ttm_pool.c

613

pt = ttm_pool_select_type(pool, caching, order);

sys/dev/pci/drm/ttm/ttm_pool.c

626

ttm_pool_free_page(pool, caching, order, page);

sys/dev/pci/drm/ttm/ttm_pool.c

704

ttm_pool_split_for_swap(restore->pool, p);

sys/dev/pci/drm/ttm/ttm_pool.c

717

ttm_pool_unmap_and_free(restore->pool, restore->alloced_page,

sys/dev/pci/drm/ttm/ttm_pool.c

737

ttm_pool_page_allocated_restore(struct ttm_pool *pool, unsigned int order,

sys/dev/pci/drm/ttm/ttm_pool.c

744

restore->pool = pool;

sys/dev/pci/drm/ttm/ttm_pool.c

760

static int ttm_pool_page_allocated(struct ttm_pool *pool, unsigned int order,

sys/dev/pci/drm/ttm/ttm_pool.c

778

r = ttm_pool_map(pool, order, p, &first_dma);

sys/dev/pci/drm/ttm/ttm_pool.c

784

ttm_pool_page_allocated_restore(pool, order, p, page_caching,

sys/dev/pci/drm/ttm/ttm_pool.c

809

static void ttm_pool_free_range(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/ttm/ttm_pool.c

830

nr = ttm_pool_unmap_and_free(pool, p, dma_addr, caching, tt->orders[i]);

sys/dev/pci/drm/ttm/ttm_pool.c

856

static int __ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/ttm/ttm_pool.c

872

WARN_ON(alloc->dma_addr && !pool->dev);

sys/dev/pci/drm/ttm/ttm_pool.c

881

if (pool->use_dma32)

sys/dev/pci/drm/ttm/ttm_pool.c

895

pt = ttm_pool_select_type(pool, page_caching, order);

sys/dev/pci/drm/ttm/ttm_pool.c

907

p = ttm_pool_alloc_page(pool, gfp_flags, order, tt->dmat);

sys/dev/pci/drm/ttm/ttm_pool.c

920

r = ttm_pool_page_allocated(pool, order, p, page_caching, alloc,

sys/dev/pci/drm/ttm/ttm_pool.c

942

ttm_pool_free_page(pool, page_caching, order, p);

sys/dev/pci/drm/ttm/ttm_pool.c

949

ttm_pool_free_range(pool, tt, tt->caching, 0, caching_divide);

sys/dev/pci/drm/ttm/ttm_pool.c

950

ttm_pool_free_range(pool, tt, ttm_cached, caching_divide,

sys/dev/pci/drm/ttm/ttm_pool.c

968

int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/ttm/ttm_pool.c

978

return __ttm_pool_alloc(pool, tt, ctx, &alloc, NULL);

sys/dev/pci/drm/ttm/ttm_pool.c

995

int ttm_pool_restore_and_alloc(struct ttm_pool *pool, struct ttm_tt *tt,

sys/dev/pci/drm/ttm/ttm_resource.c

382

struct dmem_cgroup_pool_state *pool = NULL;

sys/dev/pci/drm/ttm/ttm_resource.c

386

ret = dmem_cgroup_try_charge(man->cg, bo->base.size, &pool, ret_limit_pool);

sys/dev/pci/drm/ttm/ttm_resource.c

393

if (pool)

sys/dev/pci/drm/ttm/ttm_resource.c

394

dmem_cgroup_uncharge(pool, bo->base.size);

sys/dev/pci/drm/ttm/ttm_resource.c

398

(*res_ptr)->css = pool;

sys/dev/pci/drm/ttm/ttm_resource.c

410

struct dmem_cgroup_pool_state *pool;

sys/dev/pci/drm/ttm/ttm_resource.c

419

pool = (*res)->css;

sys/dev/pci/drm/ttm/ttm_resource.c

424

dmem_cgroup_uncharge(pool, bo->base.size);

sys/dev/pci/drm/ttm/ttm_tt.c

245

if (bo->bdev->pool.use_dma32 == false)

sys/dev/pci/drm/ttm/ttm_tt.c

331

ret = ttm_pool_backup(&bdev->pool, tt, &flags);

sys/dev/pci/drm/ttm/ttm_tt.c

343

int ret = ttm_pool_restore_and_alloc(&bdev->pool, tt, ctx);

sys/dev/pci/drm/ttm/ttm_tt.c

436

if (bdev->pool.use_dma32)

sys/dev/pci/drm/ttm/ttm_tt.c

455

ret = ttm_pool_alloc(&bdev->pool, ttm, ctx);

sys/dev/pci/drm/ttm/ttm_tt.c

474

if (bdev->pool.use_dma32)

sys/dev/pci/drm/ttm/ttm_tt.c

493

ttm_pool_free(&bdev->pool, ttm);

sys/dev/pci/drm/ttm/ttm_tt.c

497

if (bdev->pool.use_dma32)

sys/dev/pci/drm/ttm/ttm_tt.c

96

if (bdev->pool.use_dma_alloc && cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {

sys/dev/pci/eap.c

1443

eap_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/eap.c

1449

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/eap.c

1454

free(p, pool, sizeof(*p));

sys/dev/pci/eap.c

1463

eap_free(void *addr, void *ptr, int pool)

sys/dev/pci/eap.c

1472

free(p, pool, sizeof(*p));

sys/dev/pci/fms.c

542

fms_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/fms.c

549

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/fms.c

595

free(p, pool, sizeof(*p));

sys/dev/pci/fms.c

600

fms_free(void *addr, void *ptr, int pool)

sys/dev/pci/fms.c

613

free(p, pool, sizeof(*p));

sys/dev/pci/if_myx.c

82

struct pool *myx_mcl_pool;

sys/dev/pci/if_nep.c

415

struct pool *nep_block_pool;

sys/dev/pci/if_oce.c

491

struct pool *oce_pkt_pool;

sys/dev/pci/if_oce.c

579

oce_pkt_pool = malloc(sizeof(struct pool), M_DEVBUF, M_NOWAIT);

sys/dev/pci/ixgbe_x550.c

1038

unsigned int pool)

sys/dev/pci/ixgbe_x550.c

1043

if (pool > 63)

sys/dev/pci/ixgbe_x550.c

1050

pfflp |= (1ULL << pool);

sys/dev/pci/ixgbe_x550.c

1052

pfflp &= ~(1ULL << pool);

sys/dev/pci/ixgbe_x550.c

75

unsigned int pool);

sys/dev/pci/maestro.c

1660

struct salloc_pool *pool;

sys/dev/pci/maestro.c

1664

pool = malloc(sizeof *pool + nzones * sizeof pool->zones[0],

sys/dev/pci/maestro.c

1666

if (pool == NULL)

sys/dev/pci/maestro.c

1668

SLIST_INIT(&pool->free);

sys/dev/pci/maestro.c

1669

SLIST_INIT(&pool->used);

sys/dev/pci/maestro.c

1670

SLIST_INIT(&pool->spare);

sys/dev/pci/maestro.c

1672

pool->zones = (struct salloc_zone *)(pool + 1);

sys/dev/pci/maestro.c

1674

SLIST_INSERT_HEAD(&pool->spare, &pool->zones[i], link);

sys/dev/pci/maestro.c

1675

space = &pool->zones[0];

sys/dev/pci/maestro.c

1678

SLIST_INSERT_HEAD(&pool->free, space, link);

sys/dev/pci/maestro.c

1679

return pool;

sys/dev/pci/maestro.c

1683

salloc_destroy(salloc_t pool)

sys/dev/pci/maestro.c

1685

free(pool, M_TEMP, 0);

sys/dev/pci/maestro.c

1689

salloc_insert(salloc_t pool, struct salloc_head *head, struct salloc_zone *zone,

sys/dev/pci/maestro.c

1707

SLIST_INSERT_HEAD(&pool->spare, zone, link);

sys/dev/pci/maestro.c

1716

SLIST_INSERT_HEAD(&pool->spare, next, link);

sys/dev/pci/maestro.c

1721

salloc_alloc(salloc_t pool, size_t size)

sys/dev/pci/maestro.c

1725

SLIST_FOREACH(zone, &pool->free, link)

sys/dev/pci/maestro.c

1731

SLIST_REMOVE(&pool->free, zone, salloc_zone, link);

sys/dev/pci/maestro.c

1734

uzone = SLIST_FIRST(&pool->spare);

sys/dev/pci/maestro.c

1737

SLIST_REMOVE_HEAD(&pool->spare, link);

sys/dev/pci/maestro.c

1743

salloc_insert(pool, &pool->used, uzone, 0);

sys/dev/pci/maestro.c

1748

salloc_free(salloc_t pool, caddr_t addr)

sys/dev/pci/maestro.c

1752

SLIST_FOREACH(zone, &pool->used, link)

sys/dev/pci/maestro.c

1759

SLIST_REMOVE(&pool->used, zone, salloc_zone, link);

sys/dev/pci/maestro.c

1760

salloc_insert(pool, &pool->free, zone, 1);

sys/dev/pci/maestro.c

824

maestro_malloc(void *arg, int dir, size_t size, int pool, int flags)

sys/dev/pci/maestro.c

832

maestro_free(void *self, void *ptr, int pool)

sys/dev/pci/neo.c

893

neo_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/neo.c

913

neo_free(void *addr, void *ptr, int pool)

sys/dev/pci/sv.c

1267

sv_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/sv.c

1273

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/sv.c

1278

free(p, pool, sizeof(*p));

sys/dev/pci/sv.c

1287

sv_free(void *addr, void *ptr, int pool)

sys/dev/pci/sv.c

1296

free(*p, pool, sizeof(**p));

sys/dev/pci/yds.c

1509

yds_malloc(void *addr, int direction, size_t size, int pool, int flags)

sys/dev/pci/yds.c

1515

p = malloc(sizeof(*p), pool, flags);

sys/dev/pci/yds.c

1520

free(p, pool, sizeof *p);

sys/dev/pci/yds.c

1529

yds_free(void *addr, void *ptr, int pool)

sys/dev/pci/yds.c

1538

free(p, pool, sizeof *p);

sys/dev/pv/hypervic.c

1132

int next, pool, error = 0;

sys/dev/pv/hypervic.c

1136

pool = kvp_poolname(&key);

sys/dev/pv/hypervic.c

1137

if (pool == -1)

sys/dev/pv/hypervic.c

1140

kvpl = &kvp->kvp_pool[pool];

sys/dev/pv/hypervic.c

1158

if (pool == HV_KVP_POOL_AUTO)

sys/dev/pv/hypervic.c

1161

else if (pool == HV_KVP_POOL_GUEST)

sys/dev/pv/hypervic.c

87

struct pool kvp_entry_pool;

sys/dev/sbus/cs4231.c

1290

cs4231_alloc(void *vsc, int direction, size_t size, int pool, int flags)

sys/dev/sbus/cs4231.c

1296

p = (struct cs_dma *)malloc(sizeof(struct cs_dma), pool, flags);

sys/dev/sbus/cs4231.c

1330

free(p, pool, 0);

sys/dev/sbus/cs4231.c

1335

cs4231_free(void *vsc, void *ptr, int pool)

sys/dev/sbus/cs4231.c

1349

free(p, pool, 0);

sys/dev/softraid.c

2439

link->pool = &sd->sd_iopool;

sys/dev/usb/dwc2/dwc2var.h

100

struct pool sc_xferpool;

sys/dev/usb/dwc2/dwc2var.h

101

struct pool sc_qhpool;

sys/dev/usb/dwc2/dwc2var.h

102

struct pool sc_qtdpool;

sys/dev/usb/ehci.c

333

ehcixfer = malloc(sizeof(struct pool), M_USBHC, M_NOWAIT);

sys/dev/usb/ehci.c

93

struct pool *ehcixfer;

sys/dev/usb/ohci.c

68

struct pool *ohcixfer;

sys/dev/usb/ohci.c

723

ohcixfer = malloc(sizeof(struct pool), M_USBHC, M_NOWAIT);

sys/dev/usb/uhci.c

366

uhcixfer = malloc(sizeof(struct pool), M_USBHC, M_NOWAIT);

sys/dev/usb/uhci.c

73

struct pool *uhcixfer;

sys/dev/usb/xhci.c

320

xhcixfer = malloc(sizeof(struct pool), M_USBHC, M_NOWAIT);

sys/dev/usb/xhci.c

57

struct pool *xhcixfer;

sys/dev/vmm/vmm.c

36

struct pool vm_pool;

sys/dev/vmm/vmm.c

37

struct pool vcpu_pool;

sys/dev/vmm/vmm.h

242

extern struct pool vm_pool;

sys/dev/vmm/vmm.h

243

extern struct pool vcpu_pool;

sys/dev/vscsi.c

67

struct pool sc_ccb_pool;

sys/isofs/udf/udf_extern.h

62

extern struct pool udf_trans_pool;

sys/isofs/udf/udf_extern.h

63

extern struct pool unode_pool;

sys/isofs/udf/udf_extern.h

64

extern struct pool udf_ds_pool;

sys/isofs/udf/udf_vfsops.c

74

struct pool udf_trans_pool;

sys/isofs/udf/udf_vfsops.c

75

struct pool unode_pool;

sys/isofs/udf/udf_vfsops.c

76

struct pool udf_ds_pool;

sys/kern/dma_alloc.c

31

struct pool dmapools[DMA_PAGE_SHIFT - DMA_BUCKET_OFFSET + 1];

sys/kern/kern_descrip.c

85

struct pool file_pool;

sys/kern/kern_descrip.c

86

struct pool fdesc_pool;

sys/kern/kern_event.c

205

struct pool knote_pool;

sys/kern/kern_event.c

206

struct pool kqueue_pool;

sys/kern/kern_proc.c

70

struct pool proc_pool;

sys/kern/kern_proc.c

71

struct pool process_pool;

sys/kern/kern_proc.c

72

struct pool rusage_pool;

sys/kern/kern_proc.c

73

struct pool ucred_pool;

sys/kern/kern_proc.c

74

struct pool pgrp_pool;

sys/kern/kern_proc.c

75

struct pool session_pool;

sys/kern/kern_resource.c

635

struct pool plimit_pool;

sys/kern/kern_rwlock.c

688

struct pool rwlock_obj_pool;

sys/kern/kern_sig.c

138

struct pool sigacts_pool; /* memory pool for sigacts structures */

sys/kern/kern_srp.c

97

struct pool srp_gc_ctx_pool;

sys/kern/subr_extent.c

131

struct pool ex_region_pl;

sys/kern/subr_percpu.c

248

cpumem_get(struct pool *pp)

sys/kern/subr_percpu.c

254

cpumem_put(struct pool *pp, struct cpumem *cm)

sys/kern/subr_percpu.c

27

struct pool cpumem_pl;

sys/kern/subr_percpu.c

37

cpumem_get(struct pool *pp)

sys/kern/subr_percpu.c

51

cpumem_put(struct pool *pp, struct cpumem *cm)

sys/kern/subr_pool.c

102

pl_enter(struct pool *pp, union pool_lock *pl)

sys/kern/subr_pool.c

1023

pool_p_insert(struct pool *pp, struct pool_page_header *ph)

sys/kern/subr_pool.c

1044

pool_p_remove(struct pool *pp, struct pool_page_header *ph)

sys/kern/subr_pool.c

1061

pool_update_curpage(struct pool *pp)

sys/kern/subr_pool.c

107

pl_enter_try(struct pool *pp, union pool_lock *pl)

sys/kern/subr_pool.c

1070

pool_setlowat(struct pool *pp, int n)

sys/kern/subr_pool.c

1089

pool_sethiwat(struct pool *pp, int n)

sys/kern/subr_pool.c

1097

pool_sethardlimit(struct pool *pp, u_int n)

sys/kern/subr_pool.c

1116

pool_set_constraints(struct pool *pp, const struct kmem_pa_mode *mode)

sys/kern/subr_pool.c

112

pl_leave(struct pool *pp, union pool_lock *pl)

sys/kern/subr_pool.c

1127

pool_reclaim(struct pool *pp)

sys/kern/subr_pool.c

117

pl_assert_locked(struct pool *pp, union pool_lock *pl)

sys/kern/subr_pool.c

1171

struct pool *pp;

sys/kern/subr_pool.c

1187

pool_printit(struct pool *pp, const char *modif,

sys/kern/subr_pool.c

1213

pool_print1(struct pool *pp, const char *modif,

sys/kern/subr_pool.c

122

pl_assert_unlocked(struct pool *pp, union pool_lock *pl)

sys/kern/subr_pool.c

1261

struct pool *pp;

sys/kern/subr_pool.c

127

pl_sleep(struct pool *pp, void *ident, union pool_lock *lock, int priority,

sys/kern/subr_pool.c

1335

pool_chk_page(struct pool *pp, struct pool_page_header *ph, int expected)

sys/kern/subr_pool.c

1406

pool_chk(struct pool *pp)

sys/kern/subr_pool.c

1424

pool_walk(struct pool *pp, int full,

sys/kern/subr_pool.c

1475

struct pool *pp;

sys/kern/subr_pool.c

1563

struct pool *pp;

sys/kern/subr_pool.c

1604

pool_allocator_alloc(struct pool *pp, int flags, int *slowdown)

sys/kern/subr_pool.c

1624

pool_allocator_free(struct pool *pp, void *v)

sys/kern/subr_pool.c

1632

pool_page_alloc(struct pool *pp, int flags, int *slowdown)

sys/kern/subr_pool.c

1643

pool_page_free(struct pool *pp, void *v)

sys/kern/subr_pool.c

1649

pool_multi_alloc(struct pool *pp, int flags, int *slowdown)

sys/kern/subr_pool.c

1670

pool_multi_free(struct pool *pp, void *v)

sys/kern/subr_pool.c

1684

pool_multi_alloc_ni(struct pool *pp, int flags, int *slowdown)

sys/kern/subr_pool.c

1704

pool_multi_free_ni(struct pool *pp, void *v)

sys/kern/subr_pool.c

1718

struct pool pool_caches; /* per cpu cache entries */

sys/kern/subr_pool.c

1721

pool_cache_init(struct pool *pp)

sys/kern/subr_pool.c

1767

pool_cache_item_magic(struct pool *pp, struct pool_cache_item *ci)

sys/kern/subr_pool.c

1776

pool_cache_item_magic_check(struct pool *pp, struct pool_cache_item *ci)

sys/kern/subr_pool.c

1800

pool_list_enter(struct pool *pp)

sys/kern/subr_pool.c

1809

pool_list_leave(struct pool *pp)

sys/kern/subr_pool.c

1815

pool_cache_list_alloc(struct pool *pp, struct pool_cache *pc)

sys/kern/subr_pool.c

1840

pool_cache_list_free(struct pool *pp, struct pool_cache *pc,

sys/kern/subr_pool.c

1859

pool_cache_enter(struct pool *pp, int *s)

sys/kern/subr_pool.c

1871

pool_cache_leave(struct pool *pp, struct pool_cache *pc, int s)

sys/kern/subr_pool.c

1879

pool_cache_get(struct pool *pp)

sys/kern/subr_pool.c

1928

pool_cache_put(struct pool *pp, void *v)

sys/kern/subr_pool.c

194

void *pool_cache_get(struct pool *);

sys/kern/subr_pool.c

195

void pool_cache_put(struct pool *, void *);

sys/kern/subr_pool.c

196

void pool_cache_destroy(struct pool *);

sys/kern/subr_pool.c

197

void pool_cache_gc(struct pool *);

sys/kern/subr_pool.c

1972

pool_cache_list_put(struct pool *pp, struct pool_cache_item *pl)

sys/kern/subr_pool.c

199

void pool_cache_pool_info(struct pool *, struct kinfo_pool *);

sys/kern/subr_pool.c

1993

pool_cache_destroy(struct pool *pp)

sys/kern/subr_pool.c

200

int pool_cache_info(struct pool *, void *, size_t *);

sys/kern/subr_pool.c

201

int pool_cache_cpus_info(struct pool *, void *, size_t *);

sys/kern/subr_pool.c

2018

pool_cache_gc(struct pool *pp)

sys/kern/subr_pool.c

2061

pool_cache_pool_info(struct pool *pp, struct kinfo_pool *pi)

sys/kern/subr_pool.c

2097

pool_cache_info(struct pool *pp, void *oldp, size_t *oldlenp)

sys/kern/subr_pool.c

2117

pool_cache_cpus_info(struct pool *pp, void *oldp, size_t *oldlenp)

sys/kern/subr_pool.c

212

pool_p_alloc(struct pool *, int, int *);

sys/kern/subr_pool.c

213

void pool_p_insert(struct pool *, struct pool_page_header *);

sys/kern/subr_pool.c

214

void pool_p_remove(struct pool *, struct pool_page_header *);

sys/kern/subr_pool.c

215

void pool_p_free(struct pool *, struct pool_page_header *);

sys/kern/subr_pool.c

217

void pool_update_curpage(struct pool *);

sys/kern/subr_pool.c

2172

pool_cache_init(struct pool *pp)

sys/kern/subr_pool.c

2178

pool_cache_pool_info(struct pool *pp, struct kinfo_pool *pi)

sys/kern/subr_pool.c

218

void *pool_do_get(struct pool *, int, int *);

sys/kern/subr_pool.c

2184

pool_cache_info(struct pool *pp, void *oldp, size_t *oldlenp)

sys/kern/subr_pool.c

219

void pool_do_put(struct pool *, void *);

sys/kern/subr_pool.c

2190

pool_cache_cpus_info(struct pool *pp, void *oldp, size_t *oldlenp)

sys/kern/subr_pool.c

2198

pool_lock_mtx_init(struct pool *pp, union pool_lock *lock,

sys/kern/subr_pool.c

220

int pool_chk_page(struct pool *, struct pool_page_header *, int);

sys/kern/subr_pool.c

221

int pool_chk(struct pool *);

sys/kern/subr_pool.c

222

void pool_get_done(struct pool *, void *, void *);

sys/kern/subr_pool.c

223

void pool_runqueue(struct pool *, int);

sys/kern/subr_pool.c

225

void *pool_allocator_alloc(struct pool *, int, int *);

sys/kern/subr_pool.c

2252

pool_lock_rw_init(struct pool *pp, union pool_lock *lock,

sys/kern/subr_pool.c

226

void pool_allocator_free(struct pool *, void *);

sys/kern/subr_pool.c

231

void *pool_page_alloc(struct pool *, int, int *);

sys/kern/subr_pool.c

232

void pool_page_free(struct pool *, void *);

sys/kern/subr_pool.c

243

void *pool_multi_alloc(struct pool *, int, int *);

sys/kern/subr_pool.c

244

void pool_multi_free(struct pool *, void *);

sys/kern/subr_pool.c

252

void *pool_multi_alloc_ni(struct pool *, int, int *);

sys/kern/subr_pool.c

253

void pool_multi_free_ni(struct pool *, void *);

sys/kern/subr_pool.c

264

void pool_print1(struct pool *, const char *, int (*)(const char *, ...)

sys/kern/subr_pool.c

301

pr_find_pagehead(struct pool *pp, void *v)

sys/kern/subr_pool.c

332

pool_init(struct pool *pp, size_t size, u_int align, int ipl, int flags,

sys/kern/subr_pool.c

339

struct pool *iter;

sys/kern/subr_pool.c

490

pool_destroy(struct pool *pp)

sys/kern/subr_pool.c

493

struct pool *prev, *iter;

sys/kern/subr_pool.c

539

void (*handler)(struct pool *, void *, void *), void *cookie)

sys/kern/subr_pool.c

547

pool_request(struct pool *pp, struct pool_request *pr)

sys/kern/subr_pool.c

564

pool_get(struct pool *pp, int flags)

sys/kern/subr_pool.c

63

SIMPLEQ_HEAD(,pool) pool_head = SIMPLEQ_HEAD_INITIALIZER(pool_head);

sys/kern/subr_pool.c

635

pool_get_done(struct pool *pp, void *xmem, void *v)

sys/kern/subr_pool.c

647

pool_runqueue(struct pool *pp, int flags)

sys/kern/subr_pool.c

696

pool_do_get(struct pool *pp, int flags, int *slowdown)

sys/kern/subr_pool.c

76

struct pool phpool;

sys/kern/subr_pool.c

783

pool_put(struct pool *pp, void *v)

sys/kern/subr_pool.c

79

void (*pl_init)(struct pool *, union pool_lock *,

sys/kern/subr_pool.c

825

pool_wakeup(struct pool *pp)

sys/kern/subr_pool.c

835

pool_do_put(struct pool *pp, void *v)

sys/kern/subr_pool.c

889

pool_prime(struct pool *pp, int n)

sys/kern/subr_pool.c

918

pool_p_alloc(struct pool *pp, int flags, int *slowdown)

sys/kern/subr_pool.c

985

pool_p_free(struct pool *pp, struct pool_page_header *ph)

sys/kern/sys_pipe.c

124

struct pool pipe_pair_pool;

sys/kern/sysv_msg.c

62

struct pool sysvmsgpl;

sys/kern/sysv_sem.c

54

struct pool sema_pool; /* pool for struct semid_ds */

sys/kern/sysv_sem.c

55

struct pool semu_pool; /* pool for struct sem_undo (SEMUSZ) */

sys/kern/sysv_shm.c

71

struct pool shm_pool;

sys/kern/uipc_mbuf.c

103

struct pool mbpool;

sys/kern/uipc_mbuf.c

104

struct pool mtagpool;

sys/kern/uipc_mbuf.c

118

struct pool mclpools[MCLPOOLS];

sys/kern/uipc_mbuf.c

120

struct pool *m_clpool(u_int);

sys/kern/uipc_mbuf.c

134

void *m_pool_alloc(struct pool *, int, int *);

sys/kern/uipc_mbuf.c

135

void m_pool_free(struct pool *, void *);

sys/kern/uipc_mbuf.c

1450

m_pool_alloc(struct pool *pp, int flags, int *slowdown)

sys/kern/uipc_mbuf.c

1469

m_pool_free(struct pool *pp, void *v)

sys/kern/uipc_mbuf.c

1477

m_pool_init(struct pool *pp, u_int size, u_int align, const char *wmesg)

sys/kern/uipc_mbuf.c

351

struct pool *

sys/kern/uipc_mbuf.c

354

struct pool *pp;

sys/kern/uipc_mbuf.c

370

struct pool *pp;

sys/kern/uipc_mbuf2.c

72

extern struct pool mtagpool;

sys/kern/uipc_socket.c

119

struct pool socket_pool;

sys/kern/uipc_socket.c

121

struct pool sosplice_pool;

sys/kern/uipc_socket2.c

52

extern struct pool mclpools[];

sys/kern/uipc_socket2.c

53

extern struct pool mbpool;

sys/kern/uipc_usrreq.c

103

struct pool unpcb_pool;

sys/kern/vfs_bio.c

74

struct pool bufpool;

sys/kern/vfs_cache.c

69

struct pool nch_pool;

sys/kern/vfs_init.c

47

struct pool namei_pool;

sys/kern/vfs_lockf.c

77

struct pool lockf_state_pool;

sys/kern/vfs_lockf.c

78

struct pool lockf_pool;

sys/kern/vfs_subr.c

130

struct pool vnode_pool;

sys/miscfs/fuse/fuse_vfsops.c

69

struct pool fusefs_fbuf_pool;

sys/miscfs/fuse/fusefs.h

64

extern struct pool fusefs_fbuf_pool;

sys/net/art.c

103

static struct pool an_pool, at_pool, at_heap_4_pool, at_heap_8_pool;

sys/net/bfd.c

142

struct pool bfd_pool, bfd_pool_neigh, bfd_pool_time;

sys/net/hfsc.c

253

struct pool hfsc_class_pl, hfsc_internal_sc_pl;

sys/net/if_bpe.c

129

static struct pool bpe_endpoint_pool;

sys/net/if_etherbridge.c

45

static struct pool eb_entry_pool;

sys/net/if_gre.c

477

struct pool nvgre_endpoint_pool;

sys/net/if_pfsync.c

114

static struct pool pfsync_deferrals_pool;

sys/net/if_ppp.c

1570

extern struct pool ppp_pkts;

sys/net/if_pppx.c

130

struct pool pppx_if_pl;

sys/net/if_veb.c

392

static struct pool veb_rule_pool;

sys/net/if_vxlan.c

211

static struct pool vxlan_endpoint_pool;

sys/net/if_wg.c

386

struct pool wg_aip_pool;

sys/net/if_wg.c

387

struct pool wg_peer_pool;

sys/net/if_wg.c

388

struct pool wg_ratelimit_pool;

sys/net/pf.c

148

struct pool pf_src_tree_pl, pf_rule_pl, pf_queue_pl;

sys/net/pf.c

149

struct pool pf_state_pl, pf_state_key_pl, pf_state_item_pl;

sys/net/pf.c

150

struct pool pf_rule_item_pl, pf_sn_item_pl, pf_pktdelay_pl;

sys/net/pf.c

151

struct pool pf_statelim_pl, pf_sourcelim_pl, pf_source_pl;

sys/net/pf.c

152

struct pool pf_state_link_pl;

sys/net/pf.c

268

extern struct pool pfr_ktable_pl;

sys/net/pf.c

269

extern struct pool pfr_kentry_pl;

sys/net/pf_if.c

67

struct pool pfi_addr_pl;

sys/net/pf_ioctl.c

3080

if (((struct pool *)pf_pool_limits[pl->index].pp)->pr_nout >

sys/net/pf_ioctl.c

85

struct pool pf_tag_pl;

sys/net/pf_ioctl.c

86

extern struct pool pf_statelim_pl, pf_sourcelim_pl, pf_source_pl;

sys/net/pf_ioctl.c

87

extern struct pool pf_state_link_pl;

sys/net/pf_norm.c

143

struct pool pf_frent_pl, pf_frag_pl, pf_frnode_pl;

sys/net/pf_norm.c

144

struct pool pf_state_scrub_pl;

sys/net/pf_osfp.c

47

typedef struct pool pool_t;

sys/net/pf_osfp.c

59

#define pool_get(pool, flags) malloc(*(pool))

sys/net/pf_osfp.c

60

#define pool_put(pool, item) free(item)

sys/net/pf_osfp.c

61

#define pool_init(pool, size, a, ao, f, m, p) (*(pool)) = (size)

sys/net/pf_ruleset.c

56

struct pool pf_anchor_pl;

sys/net/pf_table.c

142

struct pool pfr_ktable_pl;

sys/net/pf_table.c

143

struct pool pfr_kentry_pl[PFRKE_MAX];

sys/net/pf_table.c

144

struct pool pfr_kcounters_pl;

sys/net/pfkeyv2.c

124

struct pool pkpcb_pool;

sys/net/pfkeyv2.h

469

extern struct pool ipsec_policy_pool;

sys/net/pfkeyv2.h

470

extern struct pool ipsec_acquire_pool;

sys/net/pfvar.h

1739

extern struct pool pf_src_tree_pl, pf_sn_item_pl, pf_rule_pl;

sys/net/pfvar.h

1740

extern struct pool pf_state_pl, pf_state_key_pl, pf_state_item_pl,

sys/net/pfvar.h

1743

extern struct pool pf_state_scrub_pl;

sys/net/pfvar.h

1939

extern struct pool pf_frent_pl, pf_frag_pl;

sys/net/pipex.c

80

struct pool pipex_session_pool;

sys/net/pipex.c

81

struct pool mppe_key_pool;

sys/net/pipex_local.h

321

extern struct pool pipex_session_pool;

sys/net/ppp_tty.c

135

struct pool ppp_pkts;

sys/net/radix.c

63

struct pool rtmask_pool; /* pool for radix_mask structures */

sys/net/route.c

157

struct pool rtentry_pool; /* pool for rtentry structures */

sys/net/route.c

158

struct pool rttimer_pool; /* pool for rttimer structures */

sys/net/rtsock.c

171

struct pool rtpcb_pool;

sys/net/wg_cookie.c

290

ratelimit_init(struct ratelimit *rl, struct pool *pool)

sys/net/wg_cookie.c

296

rl->rl_pool = pool;

sys/net/wg_cookie.c

40

static int ratelimit_init(struct ratelimit *, struct pool *);

sys/net/wg_cookie.c

470

struct pool rl_pool;

sys/net/wg_cookie.c

539

struct pool rl_pool;

sys/net/wg_cookie.c

56

cookie_checker_init(struct cookie_checker *cc, struct pool *pool)

sys/net/wg_cookie.c

571

struct pool rl_pool;

sys/net/wg_cookie.c

64

if ((res = ratelimit_init(&cc->cc_ratelimit_v4, pool)) != 0)

sys/net/wg_cookie.c

67

if ((res = ratelimit_init(&cc->cc_ratelimit_v6, pool)) != 0) {

sys/net/wg_cookie.h

114

int cookie_checker_init(struct cookie_checker *, struct pool *);

sys/net/wg_cookie.h

78

struct pool *rl_pool;

sys/netinet/if_ether.c

116

struct pool arp_pool; /* [I] pool for llinfo_arp structures */

sys/netinet/in_pcb.c

121

struct pool inpcb_pool;

sys/netinet/ip_input.c

136

struct pool ipqent_pool;

sys/netinet/ip_input.c

137

struct pool ipq_pool;

sys/netinet/ip_ipsp.c

109

struct pool tdb_pool;

sys/netinet/ip_ipsp.h

544

extern struct pool tdb_pool;

sys/netinet/ip_spd.c

48

struct pool ipsec_policy_pool;

sys/netinet/ip_spd.c

49

struct pool ipsec_acquire_pool;

sys/netinet/ip_var.h

237

extern struct pool ipqent_pool;

sys/netinet/tcp_input.c

3117

struct pool syn_cache_pool;

sys/netinet/tcp_subr.c

129

struct pool tcpcb_pool;

sys/netinet/tcp_subr.c

130

struct pool tcpqe_pool;

sys/netinet/tcp_subr.c

131

struct pool sackhl_pool;

sys/netinet/tcp_usrreq.c

1466

struct pool *pool;

sys/netinet/tcp_usrreq.c

1470

pool = &tcpqe_pool;

sys/netinet/tcp_usrreq.c

1473

pool = &sackhl_pool;

sys/netinet/tcp_usrreq.c

1487

error = pool_sethardlimit(pool, nval);

sys/netinet/tcp_var.h

684

extern struct pool tcpcb_pool;

sys/netinet/tcp_var.h

692

extern struct pool sackhl_pool;

sys/netinet/tcp_var.h

698

extern struct pool tcpqe_pool;

sys/netinet6/frag6.c

64

struct pool ip6af_pool;

sys/netinet6/frag6.c

65

struct pool ip6q_pool;

sys/netinet6/nd6.c

92

struct pool nd6_pool; /* [I] pool for llinfo_nd6 structures */

sys/nfs/nfs.h

310

extern struct pool nfsreqpl;

sys/nfs/nfs.h

311

extern struct pool nfs_node_pool;

sys/nfs/nfs_node.c

55

struct pool nfs_node_pool;

sys/nfs/nfs_socket.c

78

extern struct pool nfsrv_descript_pl;

sys/nfs/nfs_subs.c

507

struct pool nfsreqpl;

sys/nfs/nfs_subs.c

908

extern struct pool nfs_node_pool;

sys/nfs/nfs_syscalls.c

73

struct pool nfsrv_descript_pl;

sys/scsi/scsi_base.c

324

ioh->pool = iopl;

sys/scsi/scsi_base.c

332

struct scsi_iopool *iopl = ioh->pool;

sys/scsi/scsi_base.c

360

struct scsi_iopool *iopl = ioh->pool;

sys/scsi/scsi_base.c

511

scsi_ioh_set(&xsh->ioh, link->pool, scsi_xsh_ioh, xsh);

sys/scsi/scsi_base.c

526

mtx_enter(&link->pool->mtx);

sys/scsi/scsi_base.c

532

mtx_leave(&link->pool->mtx);

sys/scsi/scsi_base.c

546

mtx_enter(&link->pool->mtx);

sys/scsi/scsi_base.c

555

TAILQ_REMOVE(&link->pool->queue, &xsh->ioh, q_entry);

sys/scsi/scsi_base.c

564

mtx_leave(&link->pool->mtx);

sys/scsi/scsi_base.c

579

if (!scsi_pending_start(&link->pool->mtx, &link->running))

sys/scsi/scsi_base.c

584

mtx_enter(&link->pool->mtx);

sys/scsi/scsi_base.c

591

TAILQ_INSERT_TAIL(&link->pool->queue, ioh, q_entry);

sys/scsi/scsi_base.c

596

mtx_leave(&link->pool->mtx);

sys/scsi/scsi_base.c

599

scsi_iopool_run(link->pool);

sys/scsi/scsi_base.c

600

} while (!scsi_pending_finish(&link->pool->mtx, &link->running));

sys/scsi/scsi_base.c

635

struct scsi_iopool *iopl = link->pool;

sys/scsi/scsi_base.c

64

struct pool scsi_xfer_pool;

sys/scsi/scsi_base.c

65

struct pool scsi_plug_pool;

sys/scsi/scsi_base.c

682

struct scsi_iopool *iopl = link->pool;

sys/scsi/scsi_base.c

736

mtx_enter(&link->pool->mtx);

sys/scsi/scsi_base.c

741

mtx_leave(&link->pool->mtx);

sys/scsi/scsi_base.c

749

mtx_enter(&link->pool->mtx);

sys/scsi/scsi_base.c

753

mtx_leave(&link->pool->mtx);

sys/scsi/scsi_base.c

766

scsi_io_put(link->pool, io);

sys/scsi/scsi_base.c

787

scsi_io_put(link->pool, io);

sys/scsi/scsiconf.c

511

link->pool = sb->sb_pool;

sys/scsi/scsiconf.c

530

if (link->pool == NULL) {

sys/scsi/scsiconf.c

531

link->pool = malloc(sizeof(*link->pool), M_DEVBUF, M_NOWAIT);

sys/scsi/scsiconf.c

532

if (link->pool == NULL) {

sys/scsi/scsiconf.c

537

scsi_iopool_init(link->pool, link, scsi_default_get,

sys/scsi/scsiconf.c

795

if (link->pool != NULL)

sys/scsi/scsiconf.c

806

if (link->pool != NULL && ISSET(link->flags, SDEV_OWN_IOPL)) {

sys/scsi/scsiconf.c

807

scsi_iopool_destroy(link->pool);

sys/scsi/scsiconf.c

808

free(link->pool, M_DEVBUF, sizeof(*link->pool));

sys/scsi/scsiconf.h

241

struct scsi_iopool *pool;

sys/scsi/scsiconf.h

323

struct scsi_iopool *pool;

sys/sys/buf.h

239

extern struct pool bufpool;

sys/sys/mbuf.h

411

struct pool;

sys/sys/mbuf.h

443

void m_pool_init(struct pool *, u_int, u_int, const char *);

sys/sys/namei.h

213

extern struct pool namei_pool;

sys/sys/percpu.h

51

struct pool;

sys/sys/percpu.h

53

struct cpumem *cpumem_get(struct pool *);

sys/sys/percpu.h

54

void cpumem_put(struct pool *, struct cpumem *);

sys/sys/pool.h

103

struct pool;

sys/sys/pool.h

109

void *(*pa_alloc)(struct pool *, int, int *);

sys/sys/pool.h

110

void (*pa_free)(struct pool *, void *);

sys/sys/pool.h

156

SIMPLEQ_ENTRY(pool)

sys/sys/pool.h

246

void (*pr_handler)(struct pool *, void *, void *);

sys/sys/pool.h

251

void pool_init(struct pool *, size_t, u_int, int, int,

sys/sys/pool.h

253

void pool_cache_init(struct pool *);

sys/sys/pool.h

254

void pool_destroy(struct pool *);

sys/sys/pool.h

255

void pool_setlowat(struct pool *, int);

sys/sys/pool.h

256

void pool_sethiwat(struct pool *, int);

sys/sys/pool.h

257

int pool_sethardlimit(struct pool *, u_int);

sys/sys/pool.h

258

void pool_set_constraints(struct pool *,

sys/sys/pool.h

261

void *pool_get(struct pool *, int) __malloc;

sys/sys/pool.h

263

void (*)(struct pool *, void *, void *), void *);

sys/sys/pool.h

264

void pool_request(struct pool *, struct pool_request *);

sys/sys/pool.h

265

void pool_put(struct pool *, void *);

sys/sys/pool.h

266

void pool_wakeup(struct pool *);

sys/sys/pool.h

267

int pool_reclaim(struct pool *);

sys/sys/pool.h

269

int pool_prime(struct pool *, int);

sys/sys/pool.h

275

void pool_printit(struct pool *, const char *,

sys/sys/pool.h

277

void pool_walk(struct pool *, int, int (*)(const char *, ...),

sys/sys/proc.h

560

extern struct pool process_pool; /* memory pool for processes */

sys/sys/proc.h

561

extern struct pool proc_pool; /* memory pool for procs */

sys/sys/proc.h

562

extern struct pool rusage_pool; /* memory pool for zombies */

sys/sys/proc.h

563

extern struct pool ucred_pool; /* memory pool for ucreds */

sys/sys/proc.h

564

extern struct pool session_pool; /* memory pool for sessions */

sys/sys/proc.h

565

extern struct pool pgrp_pool; /* memory pool for pgrps */

sys/sys/socketvar.h

315

extern struct pool socket_pool;

sys/tmpfs/tmpfs_mem.c

46

extern struct pool tmpfs_dirent_pool;

sys/tmpfs/tmpfs_mem.c

47

extern struct pool tmpfs_node_pool;

sys/tmpfs/tmpfs_vfsops.c

59

struct pool tmpfs_dirent_pool;

sys/tmpfs/tmpfs_vfsops.c

60

struct pool tmpfs_node_pool;

sys/ufs/ext2fs/ext2fs_extern.h

54

extern struct pool ext2fs_inode_pool; /* memory pool for inodes */

sys/ufs/ext2fs/ext2fs_extern.h

55

extern struct pool ext2fs_dinode_pool; /* memory pool for dinodes */

sys/ufs/ext2fs/ext2fs_vfsops.c

85

struct pool ext2fs_inode_pool;

sys/ufs/ext2fs/ext2fs_vfsops.c

86

struct pool ext2fs_dinode_pool;

sys/ufs/ffs/ffs_extern.h

166

extern struct pool ffs_ino_pool; /* memory pool for inodes */

sys/ufs/ffs/ffs_extern.h

167

extern struct pool ffs_dinode1_pool; /* memory pool for UFS1 dinodes */

sys/ufs/ffs/ffs_extern.h

169

extern struct pool ffs_dinode2_pool; /* memory pool for UFS2 dinodes */

sys/ufs/ffs/ffs_vfsops.c

148

struct pool ffs_ino_pool;

sys/ufs/ffs/ffs_vfsops.c

149

struct pool ffs_dinode1_pool;

sys/ufs/ffs/ffs_vfsops.c

151

struct pool ffs_dinode2_pool;

sys/ufs/ufs/ufs_dirhash.c

70

struct pool ufsdirhash_pool;

sys/uvm/uvm_addr.c

47

struct pool uaddr_pool;

sys/uvm/uvm_addr.c

48

struct pool uaddr_bestfit_pool;

sys/uvm/uvm_addr.c

49

struct pool uaddr_pivot_pool;

sys/uvm/uvm_addr.c

50

struct pool uaddr_rnd_pool;

sys/uvm/uvm_amap.c

53

struct pool uvm_amap_pool;

sys/uvm/uvm_amap.c

54

struct pool uvm_small_amap_pool[UVM_AMAP_CHUNK];

sys/uvm/uvm_amap.c

55

struct pool uvm_amap_chunk_pool;

sys/uvm/uvm_anon.c

43

struct pool uvm_anon_pool;

sys/uvm/uvm_aobj.c

115

struct pool uao_swhash_elt_pool;

sys/uvm/uvm_aobj.c

142

struct pool uvm_aobj_pool;

sys/uvm/uvm_map.c

265

struct pool uvm_vmspace_pool;

sys/uvm/uvm_map.c

270

struct pool uvm_map_entry_pool;

sys/uvm/uvm_map.c

271

struct pool uvm_map_entry_kmem_pool;

sys/uvm/uvm_swap.c

204

struct pool vndxfer_pool;

sys/uvm/uvm_swap.c

205

struct pool vndbuf_pool;

sys/uvm/uvm_vnode.c

71

struct pool uvm_vnode_pool;

usr.bin/ctfconv/dw.c

33

struct pool dcu_pool, die_pool, dav_pool, dab_pool, dat_pool;

usr.bin/ctfconv/parse.c

46

struct pool it_pool, im_pool, ir_pool;

usr.bin/ctfconv/pool.c

38

SIMPLEQ_HEAD(, pool) pool_head = SIMPLEQ_HEAD_INITIALIZER(pool_head);

usr.bin/ctfconv/pool.c

41

pool_init(struct pool *pp, const char *name, size_t nmemb, size_t size)

usr.bin/ctfconv/pool.c

56

pool_get(struct pool *pp)

usr.bin/ctfconv/pool.c

82

pool_put(struct pool *pp, void *p)

usr.bin/ctfconv/pool.c

98

struct pool *pp;

usr.bin/ctfconv/pool.h

25

SIMPLEQ_ENTRY(pool) pr_list; /* list of all pools */

usr.bin/ctfconv/pool.h

34

void pool_init(struct pool *, const char *, size_t, size_t);

usr.bin/ctfconv/pool.h

35

void *pool_get(struct pool *);

usr.bin/ctfconv/pool.h

36

void pool_put(struct pool *, void *);

usr.bin/ctfconv/pool.h

40

pmalloc(struct pool *pp, size_t sz)

usr.bin/ctfconv/pool.h

46

pzalloc(struct pool *pp, size_t sz)

usr.bin/ctfconv/pool.h

57

pfree(struct pool *pp, void *p)

usr.bin/less/linenum.c

68

static struct linenum_info pool[NPOOL]; /* The pool itself */

usr.bin/less/linenum.c

87

for (p = pool; p < &pool[NPOOL-2]; p++)

usr.bin/less/linenum.c

89

pool[NPOOL-2].next = NULL;

usr.bin/less/linenum.c

90

freelist = pool;

usr.bin/less/linenum.c

92

spare = &pool[NPOOL-1];

usr.bin/netstat/mbuf.c

141

size = sizeof(pool);

usr.bin/netstat/mbuf.c

142

if (sysctl(mib, 4, &pool, &size, NULL, 0) == -1) {

usr.bin/netstat/mbuf.c

159

bcopy(&pool, &mbpool, sizeof(pool));

usr.bin/netstat/mbuf.c

162

bcopy(&pool, &mclpools[mclp++],

usr.bin/netstat/mbuf.c

163

sizeof(pool));

usr.bin/netstat/mbuf.c

92

struct kinfo_pool pool;

usr.bin/systat/mbufs.c

110

struct kinfo_pool pool;

usr.bin/systat/mbufs.c

171

size = sizeof(pool);

usr.bin/systat/mbufs.c

173

if (sysctl(mib, 4, &pool, &size, NULL, 0) == -1) {

usr.bin/systat/mbufs.c

180

ifr[mclpool_count].ifr_size = pool.pr_size;

usr.bin/systat/mbufs.c

208

struct kinfo_pool pool;

usr.bin/systat/mbufs.c

321

size = sizeof(pool);

usr.bin/systat/mbufs.c

323

if (sysctl(mib, 4, &pool, &size, NULL, 0) == -1) {

usr.bin/systat/mbufs.c

328

ifr->ifr_info.rxr_alive = pool.pr_nget - pool.pr_nput;

usr.bin/systat/mbufs.c

329

ifr->ifr_info.rxr_hwm = pool.pr_hiwat;

usr.bin/systat/pool.c

234

if (p1->pool.pr_nget < p2->pool.pr_nget)

usr.bin/systat/pool.c

236

if (p1->pool.pr_nget > p2->pool.pr_nget)

usr.bin/systat/pool.c

249

if (p1->pool.pr_npages < p2->pool.pr_npages)

usr.bin/systat/pool.c

251

if (p1->pool.pr_npages > p2->pool.pr_npages)

usr.bin/systat/pool.c

265

if (p1->pool.pr_size < p2->pool.pr_size)

usr.bin/systat/pool.c

267

if (p1->pool.pr_size > p2->pool.pr_size)

usr.bin/systat/pool.c

341

size = sizeof(pools[i].pool);

usr.bin/systat/pool.c

342

if (sysctl(mib, nitems(mib), &p->pool, &size, NULL, 0) == -1) {

usr.bin/systat/pool.c

371

(p->pool.pr_nget == 0 && p->pool.pr_npagealloc == 0))

usr.bin/systat/pool.c

410

print_fld_uint(FLD_POOL_SIZE, p->pool.pr_size);

usr.bin/systat/pool.c

412

print_fld_size(FLD_POOL_REQS, p->pool.pr_nget);

usr.bin/systat/pool.c

413

print_fld_size(FLD_POOL_FAIL, p->pool.pr_nfail);

usr.bin/systat/pool.c

414

print_fld_ssize(FLD_POOL_INUSE, p->pool.pr_nget - p->pool.pr_nput);

usr.bin/systat/pool.c

415

print_fld_size(FLD_POOL_PGREQ, p->pool.pr_npagealloc);

usr.bin/systat/pool.c

416

print_fld_size(FLD_POOL_PGREL, p->pool.pr_npagefree);

usr.bin/systat/pool.c

418

print_fld_size(FLD_POOL_NPAGE, p->pool.pr_npages);

usr.bin/systat/pool.c

419

print_fld_size(FLD_POOL_HIWAT, p->pool.pr_hiwat);

usr.bin/systat/pool.c

420

print_fld_size(FLD_POOL_MINPG, p->pool.pr_minpages);

usr.bin/systat/pool.c

422

if (p->pool.pr_maxpages == UINT_MAX)

usr.bin/systat/pool.c

425

print_fld_size(FLD_POOL_MAXPG, p->pool.pr_maxpages);

usr.bin/systat/pool.c

427

print_fld_size(FLD_POOL_IDLE, p->pool.pr_nidle);

usr.bin/systat/pool.c

57

struct kinfo_pool pool;

usr.bin/systat/pool.c

774

pool_get_cache(int pool, struct kinfo_pool_cache *kpc)

usr.bin/systat/pool.c

776

int mib[] = { CTL_KERN, KERN_POOL, KERN_POOL_CACHE, pool };

usr.bin/systat/pool.c

783

pool_get_cache_cpus(int pool, struct kinfo_pool_cache_cpu *kpcc,

usr.bin/systat/pool.c

786

int mib[] = { CTL_KERN, KERN_POOL, KERN_POOL_CACHE_CPUS, pool };

usr.bin/systat/pool.c

793

pool_get_name(int pool, char *name, size_t len)

usr.bin/systat/pool.c

795

int mib[] = { CTL_KERN, KERN_POOL, KERN_POOL_NAME, pool };

usr.bin/vmstat/vmstat.c

1003

print_pool(&pool, name);

usr.bin/vmstat/vmstat.c

1005

inuse += (pool.pr_nget - pool.pr_nput) * pool.pr_size;

usr.bin/vmstat/vmstat.c

1006

total += pool.pr_npages * pool.pr_pgsize;

usr.bin/vmstat/vmstat.c

1018

SIMPLEQ_HEAD(,pool) pool_head;

usr.bin/vmstat/vmstat.c

1019

struct pool pool, *pp = &pool;

usr.bin/vmstat/vmstat.c

970

struct kinfo_pool pool;

usr.bin/vmstat/vmstat.c

989

size = sizeof(pool);

usr.bin/vmstat/vmstat.c

990

if (sysctl(mib, 4, &pool, &size, NULL, 0) == -1) {

usr.sbin/npppd/npppd/npppd.c

1531

npppd_pool *pool;

usr.sbin/npppd/npppd/npppd.c

1544

pool = NULL;

usr.sbin/npppd/npppd/npppd.c

1563

pool = ppp_pool(ppp);

usr.sbin/npppd/npppd/npppd.c

1564

rval = npppd_pool_get_assignability(pool, req_ip4, ip4mask,

usr.sbin/npppd/npppd/npppd.c

1608

ppp->assigned_pool = pool;

usr.sbin/npppd/npppd/npppd.c

1615

pool = ppp_pool(ppp);

usr.sbin/npppd/npppd/npppd.c

1616

ip4 = npppd_pool_get_dynamic(pool, ppp);

usr.sbin/npppd/npppd/npppd.c

1622

ppp->assigned_pool = pool;

usr.sbin/npppd/npppd/npppd.c

1911

for (j = 0; j < countof(_this->pool); j++) {

usr.sbin/npppd/npppd/npppd.c

1912

if (_this->pool[j].initialized == 0)

usr.sbin/npppd/npppd/npppd.c

1915

_this->pool[j].ipcp_name) == 0) {

usr.sbin/npppd/npppd/npppd.c

1917

_this->iface_pool[i] = &_this->pool[j];

usr.sbin/npppd/npppd/npppd.c

507

for (i = countof(_this->pool) - 1; i >= 0; i--) {

usr.sbin/npppd/npppd/npppd.c

508

if (_this->pool[i].initialized != 0)

usr.sbin/npppd/npppd/npppd.c

509

npppd_pool_uninit(&_this->pool[i]);

usr.sbin/npppd/npppd/npppd_config.c

166

if (n >= countof(_this->pool)) {

usr.sbin/npppd/npppd/npppd_config.c

168

"limit=%d",(int)countof(_this->pool));

usr.sbin/npppd/npppd/npppd_config.c

187

for (i = 0; i < countof(_this->pool); i++) {

usr.sbin/npppd/npppd/npppd_config.c

188

if (_this->pool[i].initialized != 0)

usr.sbin/npppd/npppd/npppd_config.c

189

npppd_pool_uninit(&_this->pool[i]);

usr.sbin/npppd/npppd/npppd_config.c

192

_this->pool[i] = pool0[i];

usr.sbin/npppd/npppd/npppd_config.c

194

for (j = 0; j < _this->pool[i].addrs_size; j++) {

usr.sbin/npppd/npppd/npppd_config.c

195

if (_this->pool[i].initialized == 0)

usr.sbin/npppd/npppd/npppd_config.c

197

_this->pool[i].addrs[j].snp_data_ptr = &_this->pool[i];

usr.sbin/npppd/npppd/npppd_local.h

121

npppd_pool pool[NPPPD_MAX_POOL];

usr.sbin/npppd/npppd/npppd_pool.c

124

struct in_addr_range *pool, *dyna_pool, *range;

usr.sbin/npppd/npppd/npppd_pool.c

129

pool = NULL;

usr.sbin/npppd/npppd/npppd_pool.c

136

pool = ipcp->static_pool;

usr.sbin/npppd/npppd/npppd_pool.c

143

for (range = pool; range != NULL; range = range->next)

usr.sbin/npppd/npppd/npppd_pool.c

172

for (i = 0, range = pool; range != NULL; range = range->next, i++) {

usr.sbin/ntpd/constraint.c

775

if (cstr->addr_head.pool) {

usr.sbin/ntpd/constraint.c

780

if (cstr->addr_head.pool == n->addr_head.pool)

usr.sbin/ntpd/constraint.c

796

if (ncstr == NULL || cstr->addr_head.pool) {

usr.sbin/ntpd/constraint.c

805

ncstr->addr_head.pool = cstr->addr_head.pool;

usr.sbin/ntpd/control.c

347

const char *pool = "", *addr_head_name = "";

usr.sbin/ntpd/control.c

359

if (p->addr_head.pool)

usr.sbin/ntpd/control.c

360

pool = "from pool ";

usr.sbin/ntpd/control.c

362

if (0 != strcmp(a, p->addr_head.name) || p->addr_head.pool)

usr.sbin/ntpd/control.c

366

"%s %s%s%s", a, pool, addr_head_name, auth);

usr.sbin/ntpd/ntp.c

580

if (peer->addr_head.pool) {

usr.sbin/ntpd/ntp.c

586

if (npeer->addr_head.pool !=

usr.sbin/ntpd/ntp.c

587

peer->addr_head.pool)

usr.sbin/ntpd/ntp.c

621

if (peer->addr_head.pool) {

usr.sbin/ntpd/ntp.c

642

npeer->addr_head.pool =

usr.sbin/ntpd/ntp.c

643

peer->addr_head.pool;

usr.sbin/ntpd/ntp.c

657

if (peer->addr_head.pool)

usr.sbin/ntpd/ntpd.h

126

u_int8_t pool;

usr.sbin/ntpd/parse.y

191

p->addr_head.pool = ++poolseqnum;

usr.sbin/ntpd/parse.y

232

p->addr_head.pool = 0;

usr.sbin/ntpd/parse.y

267

p->addr_head.pool = ++poolseqnum;

usr.sbin/ntpd/parse.y

305

p->addr_head.pool = 0;