bin/ed/buf.c

103

len = s - cs;

bin/ed/buf.c

116

if (fwrite(cs, sizeof(char), len, sfp) != len) {

bin/ed/buf.c

84

put_sbuf_line(char *cs)

bin/ed/buf.c

96

for (s = cs; *s != '\n'; s++)

bin/ed/buf.c

98

if (s - cs >= LINECHARS) {

bin/ksh/c_sh.c

261

XString cs, xs;

bin/ksh/c_sh.c

326

Xinit(cs, cp, 128, ATEMP);

bin/ksh/c_sh.c

328

for (cp = Xstring(cs, cp); ; ) {

bin/ksh/c_sh.c

355

Xcheck(cs, cp);

bin/ksh/c_sh.c

368

Xput(cs, cp, c);

bin/ksh/c_sh.c

378

if (Xlength(cs, cp) == 0 && ctype(c, C_IFSWS))

bin/ksh/c_sh.c

383

Xput(cs, cp, c);

bin/ksh/c_sh.c

387

while (Xlength(cs, cp) && ctype(cp[-1], C_IFS) &&

bin/ksh/c_sh.c

390

Xput(cs, cp, '\0');

bin/ksh/c_sh.c

400

if (!setstr(vp, Xstring(cs, cp), KSH_RETURN_ERROR)) {

lib/libc/regex/engine.c

491

cset *cs;

lib/libc/regex/engine.c

510

cs = &m->g->sets[OPND(s)];

lib/libc/regex/engine.c

511

if (sp == stop || !CHIN(cs, *sp++))

lib/libc/regex/engine.c

855

cset *cs;

lib/libc/regex/engine.c

895

cs = &g->sets[OPND(s)];

lib/libc/regex/engine.c

896

if (!NONCHAR(ch) && CHIN(cs, ch))

lib/libc/regex/regcomp.c

1015

cset *cs;

lib/libc/regex/regcomp.c

1046

cs = &p->g->sets[no];

lib/libc/regex/regcomp.c

1047

cs->ptr = p->g->setbits + css*((no)/CHAR_BIT);

lib/libc/regex/regcomp.c

1048

cs->mask = 1 << ((no) % CHAR_BIT);

lib/libc/regex/regcomp.c

1049

cs->hash = 0;

lib/libc/regex/regcomp.c

1051

return(cs);

lib/libc/regex/regcomp.c

1067

freeset(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

1074

CHsub(cs, i);

lib/libc/regex/regcomp.c

1075

if (cs == top-1) /* recover only the easy case */

lib/libc/regex/regcomp.c

1089

freezeset(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

1091

uch h = cs->hash;

lib/libc/regex/regcomp.c

1099

if (cs2->hash == h && cs2 != cs) {

lib/libc/regex/regcomp.c

1102

if (CHIN(cs2, i) != CHIN(cs, i))

lib/libc/regex/regcomp.c

1109

freeset(p, cs);

lib/libc/regex/regcomp.c

1110

cs = cs2;

lib/libc/regex/regcomp.c

1113

return((int)(cs - p->g->sets));

lib/libc/regex/regcomp.c

1120

firstch(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

1126

if (CHIN(cs, i))

lib/libc/regex/regcomp.c

1136

nch(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

1143

if (CHIN(cs, i))

lib/libc/regex/regcomp.c

612

cset *cs;

lib/libc/regex/regcomp.c

629

if ((cs = allocset(p)) == NULL) {

lib/libc/regex/regcomp.c

637

CHadd(cs, ']');

lib/libc/regex/regcomp.c

639

CHadd(cs, '-');

lib/libc/regex/regcomp.c

641

p_b_term(p, cs);

lib/libc/regex/regcomp.c

643

CHadd(cs, '-');

lib/libc/regex/regcomp.c

647

freeset(p, cs);

lib/libc/regex/regcomp.c

656

if (CHIN(cs, i) && isalpha(i)) {

lib/libc/regex/regcomp.c

659

CHadd(cs, ci);

lib/libc/regex/regcomp.c

666

if (CHIN(cs, i))

lib/libc/regex/regcomp.c

667

CHsub(cs, i);

lib/libc/regex/regcomp.c

669

CHadd(cs, i);

lib/libc/regex/regcomp.c

671

CHsub(cs, '\n');

lib/libc/regex/regcomp.c

674

if (nch(p, cs) == 1) { /* optimize singleton sets */

lib/libc/regex/regcomp.c

675

ordinary(p, firstch(p, cs));

lib/libc/regex/regcomp.c

676

freeset(p, cs);

lib/libc/regex/regcomp.c

678

EMIT(OANYOF, freezeset(p, cs));

lib/libc/regex/regcomp.c

685

p_b_term(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

711

p_b_cclass(p, cs);

lib/libc/regex/regcomp.c

720

p_b_eclass(p, cs);

lib/libc/regex/regcomp.c

739

CHadd(cs, i);

lib/libc/regex/regcomp.c

748

p_b_cclass(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

770

CHadd(cs, c);

lib/libc/regex/regcomp.c

779

p_b_eclass(struct parse *p, cset *cs)

lib/libc/regex/regcomp.c

784

CHadd(cs, c);

lib/libc/regex/regex2.h

112

CHadd(cset *cs, char c)

lib/libc/regex/regex2.h

114

cs->ptr[(uch)c] |= cs->mask;

lib/libc/regex/regex2.h

115

cs->hash += c;

lib/libc/regex/regex2.h

119

CHsub(cset *cs, char c)

lib/libc/regex/regex2.h

121

cs->ptr[(uch)c] &= ~cs->mask;

lib/libc/regex/regex2.h

122

cs->hash -= c;

lib/libc/regex/regex2.h

126

CHIN(const cset *cs, char c)

lib/libc/regex/regex2.h

128

return (cs->ptr[(uch)c] & cs->mask) != 0;

lib/libcrypto/ocsp/ocsp.h

187

#define OCSP_CERTSTATUS_dup(cs) \

lib/libcrypto/ocsp/ocsp.h

188

ASN1_item_dup(&OCSP_CERTSTATUS_it, cs)

lib/libcrypto/ocsp/ocsp_srv.c

154

OCSP_CERTSTATUS *cs;

lib/libcrypto/ocsp/ocsp_srv.c

175

cs = single->certStatus;

lib/libcrypto/ocsp/ocsp_srv.c

176

switch (cs->type = status) {

lib/libcrypto/ocsp/ocsp_srv.c

182

if (!(cs->value.revoked = ri = OCSP_REVOKEDINFO_new()))

lib/libcrypto/ocsp/ocsp_srv.c

196

cs->value.good = ASN1_NULL_new();

lib/libcrypto/ocsp/ocsp_srv.c

200

cs->value.unknown = ASN1_NULL_new();

lib/libm/src/k_sincos.h

31

__kernel_sincos(double x, double y, int iy, double *sn, double *cs)

lib/libm/src/k_sincos.h

48

*cs = w + (((1 - w) - hz) + (z * r - x * y));

lib/libm/src/k_sincosf.h

29

__kernel_sincosdf(double x, float *sn, float *cs)

lib/libm/src/k_sincosf.h

39

*cs = ((1 + z * C0) + w * C1) + (w * z) * r;

lib/libm/src/ld128/k_sincosl.h

44

long double *cs)

lib/libm/src/ld128/k_sincosl.h

60

*cs = x - ((z * (y / 2 - v * r) - y) - v * S1);

lib/libm/src/ld128/k_sincosl.h

67

*cs = w + (((1 - w) - hz) + (z * r - x * y));

lib/libm/src/ld80/k_sincosl.h

47

long double *cs)

lib/libm/src/ld80/k_sincosl.h

68

*cs = w + (((1 - w) - hz) + (z * r - x * y));

lib/libm/src/s_sincos.c

22

sincos(double x, double *sn, double *cs)

lib/libm/src/s_sincos.c

36

*cs = 1;

lib/libm/src/s_sincos.c

40

__kernel_sincos(x, 0, 0, sn, cs);

lib/libm/src/s_sincos.c

47

*cs = x - x;

lib/libm/src/s_sincos.c

56

__kernel_sincos(y[0], y[1], 1, sn, cs);

lib/libm/src/s_sincos.c

59

__kernel_sincos(y[0], y[1], 1, cs, sn);

lib/libm/src/s_sincos.c

60

*cs = -*cs;

lib/libm/src/s_sincos.c

63

__kernel_sincos(y[0], y[1], 1, sn, cs);

lib/libm/src/s_sincos.c

65

*cs = -*cs;

lib/libm/src/s_sincos.c

68

__kernel_sincos(y[0], y[1], 1, cs, sn);

lib/libm/src/s_sincosf.c

106

*cs = c;

lib/libm/src/s_sincosf.c

110

*cs = -s;

lib/libm/src/s_sincosf.c

114

*cs = -c;

lib/libm/src/s_sincosf.c

118

*cs = s;

lib/libm/src/s_sincosf.c

32

sincosf(float x, float *sn, float *cs)

lib/libm/src/s_sincosf.c

45

*cs = 1;

lib/libm/src/s_sincosf.c

49

__kernel_sincosdf(x, sn, cs);

lib/libm/src/s_sincosf.c

56

__kernel_sincosdf(x - p1pio2, cs, sn);

lib/libm/src/s_sincosf.c

57

*cs = -*cs;

lib/libm/src/s_sincosf.c

59

__kernel_sincosdf(x + p1pio2, cs, sn);

lib/libm/src/s_sincosf.c

64

__kernel_sincosdf(x - p2pio2, sn, cs);

lib/libm/src/s_sincosf.c

66

__kernel_sincosdf(x + p2pio2, sn, cs);

lib/libm/src/s_sincosf.c

68

*cs = -*cs;

lib/libm/src/s_sincosf.c

76

__kernel_sincosdf(x - p3pio2, cs, sn);

lib/libm/src/s_sincosf.c

79

__kernel_sincosdf(x + p3pio2, cs, sn);

lib/libm/src/s_sincosf.c

80

*cs = -*cs;

lib/libm/src/s_sincosf.c

84

__kernel_sincosdf(x - p4pio2, sn, cs);

lib/libm/src/s_sincosf.c

86

__kernel_sincosdf(x + p4pio2, sn, cs);

lib/libm/src/s_sincosf.c

94

*cs = x - x;

lib/libm/src/s_sincosl.c

108

__kernel_sincosl(hi, lo, 1, sn, cs);

lib/libm/src/s_sincosl.c

111

__kernel_sincosl(hi, lo, 1, cs, sn);

lib/libm/src/s_sincosl.c

112

*cs = -*cs;

lib/libm/src/s_sincosl.c

115

__kernel_sincosl(hi, lo, 1, sn, cs);

lib/libm/src/s_sincosl.c

117

*cs = -*cs;

lib/libm/src/s_sincosl.c

120

__kernel_sincosl(hi, lo, 1, cs, sn);

lib/libm/src/s_sincosl.c

51

sincosl(long double x, long double *sn, long double *cs)

lib/libm/src/s_sincosl.c

72

*cs = 1;

lib/libm/src/s_sincosl.c

74

__kernel_sincosl(x, 0, 0, sn, cs);

lib/libm/src/s_sincosl.c

81

*cs = x - x;

lib/libssl/ssl_lib.c

2359

const SSL_CIPHER *cs = s->s3->hs.cipher;

lib/libssl/ssl_lib.c

2362

alg_a = cs->algorithm_auth;

lib/libtls/tls_config.c

575

char *cs = NULL;

lib/libtls/tls_config.c

587

if ((cs = strdup(curves)) == NULL) {

lib/libtls/tls_config.c

593

q = cs;

lib/libtls/tls_config.c

627

free(cs);

libexec/ftpd/ftpcmd.y

1098

char *cs;

libexec/ftpd/ftpcmd.y

1100

cs = s;

libexec/ftpd/ftpcmd.y

1103

*cs++ = tmpline[c];

libexec/ftpd/ftpcmd.y

1105

*cs++ = '\0';

libexec/ftpd/ftpcmd.y

1139

*cs++ = c;

libexec/ftpd/ftpcmd.y

1154

if (c == EOF && cs == s)

libexec/ftpd/ftpcmd.y

1156

*cs++ = '\0';

libexec/getty/main.c

365

unsigned char cs;

libexec/getty/main.c

388

r = read(STDIN_FILENO, &cs, 1);

libexec/getty/main.c

397

if (cs == CTRL('L') || cs == CTRL('K'))

libexec/getty/main.c

399

if (cs == '\t')

libexec/getty/main.c

400

cs = ' ';

libexec/getty/main.c

401

if ((c = cs&0177) == 0)

libexec/getty/main.c

444

putchr(cs);

libexec/ld.so/aarch64/SYS.h

52

cneg x0, x0, cs /* r0 = -errno */ ;\

regress/lib/libc/regex/debug.c

114

cs = &g->sets[opnd];

regress/lib/libc/regex/debug.c

117

if (CHIN(cs, i) && i < g->csetsize) {

regress/lib/libc/regex/debug.c

62

register cset *cs;

regress/lib/libcrypto/des/destest.c

310

DES_LONG cs;

regress/lib/libcrypto/des/destest.c

675

cs=DES_cbc_cksum(cbc_data,&cret,strlen((char *)cbc_data),&ks,&cbc_iv);

regress/lib/libcrypto/des/destest.c

676

if (cs != cbc_cksum_ret)

regress/lib/libcrypto/des/destest.c

679

(unsigned long)cs,(unsigned long)cbc_cksum_ret);

regress/lib/libcrypto/des/destest.c

689

cs=DES_quad_cksum(cbc_data,(DES_cblock *)lqret,

regress/lib/libcrypto/des/destest.c

691

if (cs != 0x70d7a63aL)

regress/lib/libcrypto/des/destest.c

694

(unsigned long)cs);

regress/lib/libssl/dtls/dtlstest.c

329

int cs = -1, ss = -1;

regress/lib/libssl/dtls/dtlstest.c

344

if ((cs = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) == -1)

regress/lib/libssl/dtls/dtlstest.c

346

if (connect(cs, (struct sockaddr *)&sin, sizeof(sin)) == -1)

regress/lib/libssl/dtls/dtlstest.c

349

*client_sock = cs;

regress/lib/libssl/interop/botan/client.cpp

127

std::vector<Botan::Certificate_Store*> cs { &m_ca };

regress/lib/libssl/interop/botan/client.cpp

128

return cs;

regress/sys/kern/sosplice/perf/relay.c

236

int optval, error, save_errno, cs;

regress/sys/kern/sosplice/perf/relay.c

243

cs = -1;

regress/sys/kern/sosplice/perf/relay.c

245

cs = socket(res->ai_family, res->ai_socktype,

regress/sys/kern/sosplice/perf/relay.c

247

if (cs == -1) {

regress/sys/kern/sosplice/perf/relay.c

252

if (setsockopt(cs, SOL_SOCKET, SO_SNDBUF,

regress/sys/kern/sosplice/perf/relay.c

255

if (connect(cs, res->ai_addr, res->ai_addrlen) == -1) {

regress/sys/kern/sosplice/perf/relay.c

258

close(cs);

regress/sys/kern/sosplice/perf/relay.c

260

cs = -1;

regress/sys/kern/sosplice/perf/relay.c

265

if (cs == -1)

regress/sys/kern/sosplice/perf/relay.c

268

if (getpeername(cs, (struct sockaddr *)&sa, &salen) == -1)

regress/sys/kern/sosplice/perf/relay.c

278

return cs;

regress/sys/kern/sosplice/perf/relay.c

285

int ch, ls[FD_SETSIZE], nls, as, cs, optval;

regress/sys/kern/sosplice/perf/relay.c

348

cs = socket_connect(&hints, hostname, port);

regress/sys/kern/sosplice/perf/relay.c

350

if (setsockopt(cs, IPPROTO_TCP, TCP_NODELAY,

regress/sys/kern/sosplice/perf/relay.c

354

cs = socket_connect(&hints, hostname, port);

regress/sys/kern/sosplice/perf/relay.c

358

relayfunc(as, cs);

regress/sys/kern/sosplice/perf/relay.c

360

if (close(cs) == -1)

sbin/dumpfs/dumpfs.c

309

struct csum *cs = &afs.fs_cs(&afs, cg);

sbin/dumpfs/dumpfs.c

313

cs->cs_nbfree, cs->cs_ndir, cs->cs_nifree, cs->cs_nffree);

sbin/fsck_ffs/pass5.c

320

cs = &fs->fs_cs(fs, c);

sbin/fsck_ffs/pass5.c

321

if (memcmp(&newcg->cg_cs, cs, sizeof *cs) != 0 &&

sbin/fsck_ffs/pass5.c

323

memcpy(cs, &newcg->cg_cs, sizeof *cs);

sbin/fsck_ffs/pass5.c

72

struct csum *cs;

sbin/growfs/growfs.c

1002

*cs = acg.cg_cs;

sbin/growfs/growfs.c

1017

cs = fscs + ncscg;

sbin/growfs/growfs.c

1090

*cs = acg.cg_cs;

sbin/growfs/growfs.c

1364

*cs = acg.cg_cs;

sbin/growfs/growfs.c

328

struct csum *cs;

sbin/growfs/growfs.c

354

cs = &fscs[cg];

sbin/growfs/growfs.c

478

*cs = acg.cg_cs;

sbin/growfs/growfs.c

627

struct csum *cs;

sbin/growfs/growfs.c

671

cs = fscs + cg;

sbin/growfs/growfs.c

815

*cs = acg.cg_cs;

sbin/growfs/growfs.c

843

struct csum *cs;

sbin/growfs/growfs.c

862

cs = fscs + ocscg;

sbin/growfs/growfs.c

889

if (/*((int)sblock.fs_time & 0x3) > 0 || */ cs->cs_nbfree < blocks) {

sbin/iked/control.c

101

if (unlink(cs->cs_name) == -1)

sbin/iked/control.c

103

log_warn("%s: unlink %s", __func__, cs->cs_name);

sbin/iked/control.c

108

if (cs->cs_restricted) {

sbin/iked/control.c

117

log_warn("%s: bind: %s", __func__, cs->cs_name);

sbin/iked/control.c

124

if (chmod(cs->cs_name, mode) == -1) {

sbin/iked/control.c

127

(void)unlink(cs->cs_name);

sbin/iked/control.c

131

cs->cs_fd = fd;

sbin/iked/control.c

132

cs->cs_env = env;

sbin/iked/control.c

138

control_listen(struct control_sock *cs)

sbin/iked/control.c

140

if (cs->cs_name == NULL)

sbin/iked/control.c

143

if (listen(cs->cs_fd, CONTROL_BACKLOG) == -1) {

sbin/iked/control.c

148

event_set(&cs->cs_ev, cs->cs_fd, EV_READ,

sbin/iked/control.c

149

control_accept, cs);

sbin/iked/control.c

150

event_add(&cs->cs_ev, NULL);

sbin/iked/control.c

151

evtimer_set(&cs->cs_evt, control_accept, cs);

sbin/iked/control.c

159

struct control_sock *cs = arg;

sbin/iked/control.c

166

event_add(&cs->cs_ev, NULL);

sbin/iked/control.c

180

event_del(&cs->cs_ev);

sbin/iked/control.c

181

evtimer_add(&cs->cs_evt, &evtpause);

sbin/iked/control.c

202

c->iev.data = cs;

sbin/iked/control.c

230

control_close(int fd, struct control_sock *cs)

sbin/iked/control.c

246

if (evtimer_pending(&cs->cs_evt, NULL)) {

sbin/iked/control.c

247

evtimer_del(&cs->cs_evt);

sbin/iked/control.c

248

event_add(&cs->cs_ev, NULL);

sbin/iked/control.c

257

struct control_sock *cs = arg;

sbin/iked/control.c

258

struct iked *env = cs->cs_env;

sbin/iked/control.c

270

control_close(fd, cs);

sbin/iked/control.c

276

control_close(fd, cs);

sbin/iked/control.c

283

control_close(fd, cs);

sbin/iked/control.c

78

control_init(struct privsep *ps, struct control_sock *cs)

sbin/iked/control.c

85

if (cs->cs_name == NULL)

sbin/iked/control.c

94

if (strlcpy(s_un.sun_path, cs->cs_name,

sbin/iked/control.c

96

log_warn("%s: %s name too long", __func__, cs->cs_name);

sbin/newfs/mkfs.c

628

struct csum *cs;

sbin/newfs/mkfs.c

646

cs = &fscs[cg];

sbin/newfs/mkfs.c

728

*cs = acg.cg_cs;

sbin/unwind/libunbound/services/cache/infra.c

1124

char ts[12], cs[12], ip[128];

sbin/unwind/libunbound/services/cache/infra.c

1128

sldns_wire2str_class_buf(qinfo->qclass, cs, sizeof(cs));

sbin/unwind/libunbound/services/cache/infra.c

1133

verbose(VERB_OPS, "ratelimit exceeded %s %d query %s %s %s from %s", buf, lim, qnm, cs, ts, ip);

sbin/unwind/libunbound/services/cache/infra.c

1135

verbose(VERB_OPS, "ratelimit exceeded %s %d query %s %s %s", buf, lim, qnm, cs, ts);

sbin/unwind/libunbound/util/net_help.c

558

const char *ts, *cs;

sbin/unwind/libunbound/util/net_help.c

576

cs = sldns_lookup_by_id(sldns_rr_classes, (int)dclass)->name;

sbin/unwind/libunbound/util/net_help.c

579

cs = c;

sbin/unwind/libunbound/util/net_help.c

581

log_info("%s %s %s %s", str, buf, ts, cs);

sbin/unwind/libunbound/util/net_help.c

589

const char *ts, *cs;

sbin/unwind/libunbound/util/net_help.c

605

cs = sldns_lookup_by_id(sldns_rr_classes, (int)dclass)->name;

sbin/unwind/libunbound/util/net_help.c

608

cs = c;

sbin/unwind/libunbound/util/net_help.c

611

log_query("%s %s %s %s", str, buf, ts, cs);

sbin/unwind/libunbound/util/net_help.c

612

else log_info("%s %s %s %s", str, buf, ts, cs);

sys/arch/amd64/include/frameasm.h

121

movl %cs,%r11d ; \

sys/arch/amd64/stand/rdboot/cmd.c

184

const struct cmd_table *ct = cmd_table, *cs;

sys/arch/amd64/stand/rdboot/cmd.c

199

cs = NULL;

sys/arch/amd64/stand/rdboot/cmd.c

206

cs = cmd_set;

sys/arch/amd64/stand/rdboot/cmd.c

209

cs = MACHINE_CMD;

sys/arch/amd64/stand/rdboot/cmd.c

213

if (cs != NULL) {

sys/arch/amd64/stand/rdboot/cmd.c

214

p = whatcmd(&cs, p);

sys/arch/amd64/stand/rdboot/cmd.c

215

if (cs == NULL) {

sys/arch/amd64/stand/rdboot/cmd.c

219

ct = cs;

sys/arch/arm64/dev/aplspi.c

175

int cs;

sys/arch/arm64/dev/aplspi.c

177

cs = conf->sc_cs;

sys/arch/arm64/dev/aplspi.c

178

if (cs > 4) {

sys/arch/arm64/dev/aplspi.c

179

printf("%s: invalid chip-select (%d)\n", DEVNAME(sc), cs);

sys/arch/arm64/dev/aplspi.c

182

sc->sc_cs = cs;

sys/arch/arm64/dev/aplspi.c

211

aplspi_set_cs(struct aplspi_softc *sc, int cs, int on)

sys/arch/arm64/dev/aplspi.c

213

if (cs == 0) {

sys/arch/armv7/marvell/mvahci.c

87

struct mbus_dram_window *win = &mvmbus_dram_info->cs[i];

sys/arch/armv7/marvell/mvmbus.c

380

int i, cs = 0;

sys/arch/armv7/marvell/mvmbus.c

396

struct mbus_dram_window *win = &sc->sc_dram_info.cs[cs++];

sys/arch/armv7/marvell/mvmbus.c

403

sc->sc_dram_info.numcs = cs;

sys/arch/armv7/marvell/mvmbusvar.h

28

} cs[4];

sys/arch/armv7/marvell/mvpcie.c

471

struct mbus_dram_window *win = &mvmbus_dram_info->cs[i];

sys/arch/armv7/marvell/mvpcie.c

487

HWRITE4(po, PCIE_BAR_LO(1), mvmbus_dram_info->cs[0].base);

sys/arch/armv7/marvell/mvpxa.c

89

struct mbus_dram_window *win = &mvmbus_dram_info->cs[i];

sys/arch/armv7/marvell/mvxhci.c

87

struct mbus_dram_window *win = &mvmbus_dram_info->cs[i];

sys/arch/i386/i386/machdep.c

2975

initcodesegment(struct segment_descriptor *cs)

sys/arch/i386/i386/machdep.c

2982

setsegment(cs, 0, atop(VM_MAXUSER_ADDRESS - 1),

sys/arch/i386/i386/machdep.c

2993

setsegment(cs, 0, atop(I386_MAX_EXE_ADDR - 1),

sys/arch/macppc/dev/zs.c

194

struct zs_chanstate *cs;

sys/arch/macppc/dev/zs.c

241

cs = &xcs->xzs_cs;

sys/arch/macppc/dev/zs.c

242

zsc->zsc_cs[channel] = cs;

sys/arch/macppc/dev/zs.c

244

cs->cs_channel = channel;

sys/arch/macppc/dev/zs.c

245

cs->cs_private = NULL;

sys/arch/macppc/dev/zs.c

246

cs->cs_ops = &zsops_null;

sys/arch/macppc/dev/zs.c

250

cs->cs_reg_csr = &zc->zc_csr;

sys/arch/macppc/dev/zs.c

251

cs->cs_reg_data = &zc->zc_data;

sys/arch/macppc/dev/zs.c

253

memcpy(cs->cs_creg, zs_init_reg, 16);

sys/arch/macppc/dev/zs.c

254

memcpy(cs->cs_preg, zs_init_reg, 16);

sys/arch/macppc/dev/zs.c

258

cs->cs_brg_clk = PCLK / 16;

sys/arch/macppc/dev/zs.c

260

cs->cs_defspeed = zs_get_speed(cs);

sys/arch/macppc/dev/zs.c

262

cs->cs_defspeed =

sys/arch/macppc/dev/zs.c

264

cs->cs_defcflag = zs_def_cflag;

sys/arch/macppc/dev/zs.c

267

cs->cs_rr0_dcd = ZSRR0_DCD;

sys/arch/macppc/dev/zs.c

268

cs->cs_rr0_cts = 0;

sys/arch/macppc/dev/zs.c

269

cs->cs_wr5_dtr = ZSWR5_DTR;

sys/arch/macppc/dev/zs.c

270

cs->cs_wr5_rts = 0;

sys/arch/macppc/dev/zs.c

273

cs->cs_slave_type = ZS_SLAVE_NONE;

sys/arch/macppc/dev/zs.c

331

zs_write_reg(cs, 9, reset);

sys/arch/macppc/dev/zs.c

355

cs = zsc->zsc_cs[0];

sys/arch/macppc/dev/zs.c

358

zs_write_reg(cs, 2, zs_init_reg[2]);

sys/arch/macppc/dev/zs.c

360

zs_write_reg(cs, 9, zs_init_reg[9]);

sys/arch/macppc/dev/zs.c

364

cs->enable = zs_enable;

sys/arch/macppc/dev/zs.c

365

cs->disable = zs_disable;

sys/arch/macppc/dev/zs.c

383

zsmdioctl(struct zs_chanstate *cs, u_long cmd, caddr_t data)

sys/arch/macppc/dev/zs.c

393

zsmd_setclock(struct zs_chanstate *cs)

sys/arch/macppc/dev/zs.c

396

struct xzs_chanstate *xcs = (void *)cs;

sys/arch/macppc/dev/zs.c

398

if (cs->cs_channel != 0)

sys/arch/macppc/dev/zs.c

473

struct zs_chanstate *cs;

sys/arch/macppc/dev/zs.c

481

cs = zsc->zsc_cs[ch];

sys/arch/macppc/dev/zs.c

482

zstty_txdma_int(cs);

sys/arch/macppc/dev/zs.c

484

if (cs->cs_softreq) {

sys/arch/macppc/dev/zs.c

494

zs_dma_setup(struct zs_chanstate *cs, caddr_t pa, int len)

sys/arch/macppc/dev/zs.c

498

int ch = cs->cs_channel;

sys/arch/macppc/dev/zs.c

520

zs_get_speed(struct zs_chanstate *cs)

sys/arch/macppc/dev/zs.c

524

tconst = zs_read_reg(cs, 12);

sys/arch/macppc/dev/zs.c

525

tconst |= zs_read_reg(cs, 13) << 8;

sys/arch/macppc/dev/zs.c

526

return TCONST_TO_BPS(cs->cs_brg_clk, tconst);

sys/arch/macppc/dev/zs.c

547

zs_set_speed(struct zs_chanstate *cs, int bps)

sys/arch/macppc/dev/zs.c

549

struct xzs_chanstate *xcs = (void *)cs;

sys/arch/macppc/dev/zs.c

637

cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;

sys/arch/macppc/dev/zs.c

639

cs->cs_brg_clk = PCLK / 16;

sys/arch/macppc/dev/zs.c

649

cs->cs_preg[4] = ZSWR4_CLK_X16;

sys/arch/macppc/dev/zs.c

650

cs->cs_preg[11]= ZSWR11_RXCLK_BAUD | ZSWR11_TXCLK_BAUD;

sys/arch/macppc/dev/zs.c

652

cs->cs_preg[14] = ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK;

sys/arch/macppc/dev/zs.c

654

cs->cs_preg[14] = ZSWR14_BAUD_ENA;

sys/arch/macppc/dev/zs.c

658

cs->cs_preg[4] = tc0;

sys/arch/macppc/dev/zs.c

660

cs->cs_preg[11] = ZSWR11_RXCLK_RTXC | ZSWR11_TXCLK_RTXC;

sys/arch/macppc/dev/zs.c

662

cs->cs_preg[11] = ZSWR11_RXCLK_TRXC | ZSWR11_TXCLK_TRXC;

sys/arch/macppc/dev/zs.c

664

cs->cs_preg[14]= 0;

sys/arch/macppc/dev/zs.c

668

cs->cs_preg[12] = tc;

sys/arch/macppc/dev/zs.c

669

cs->cs_preg[13] = tc >> 8;

sys/arch/macppc/dev/zs.c

676

cs->cs_preg[4], cs->cs_preg[11], cs->cs_preg[14]);

sys/arch/macppc/dev/zs.c

679

cs->cs_preg[5] |= ZSWR5_RTS; /* Make sure the drivers are on! */

sys/arch/macppc/dev/zs.c

686

zs_set_modes(struct zs_chanstate *cs, int cflag)

sys/arch/macppc/dev/zs.c

688

struct xzs_chanstate *xcs = (void*)cs;

sys/arch/macppc/dev/zs.c

722

cs->cs_rr0_dcd = 0;

sys/arch/macppc/dev/zs.c

724

cs->cs_rr0_dcd = ZSRR0_DCD;

sys/arch/macppc/dev/zs.c

739

cs->cs_wr5_dtr = ZSWR5_DTR;

sys/arch/macppc/dev/zs.c

740

cs->cs_wr5_rts = 0;

sys/arch/macppc/dev/zs.c

741

cs->cs_rr0_cts = ZSRR0_CTS;

sys/arch/macppc/dev/zs.c

744

cs->cs_wr5_dtr = 0;

sys/arch/macppc/dev/zs.c

745

cs->cs_wr5_rts = ZSWR5_DTR;

sys/arch/macppc/dev/zs.c

746

cs->cs_rr0_cts = ZSRR0_CTS;

sys/arch/macppc/dev/zs.c

749

cs->cs_wr5_dtr = 0;

sys/arch/macppc/dev/zs.c

750

cs->cs_wr5_rts = ZSWR5_DTR;

sys/arch/macppc/dev/zs.c

751

cs->cs_rr0_cts = ZSRR0_DCD;

sys/arch/macppc/dev/zs.c

753

cs->cs_wr5_dtr = ZSWR5_DTR;

sys/arch/macppc/dev/zs.c

754

cs->cs_wr5_rts = 0;

sys/arch/macppc/dev/zs.c

755

cs->cs_rr0_cts = 0;

sys/arch/macppc/dev/zs.c

773

zs_read_reg(struct zs_chanstate *cs, u_char reg)

sys/arch/macppc/dev/zs.c

777

out8(cs->cs_reg_csr, reg);

sys/arch/macppc/dev/zs.c

779

val = in8(cs->cs_reg_csr);

sys/arch/macppc/dev/zs.c

785

zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)

sys/arch/macppc/dev/zs.c

787

out8(cs->cs_reg_csr, reg);

sys/arch/macppc/dev/zs.c

789

out8(cs->cs_reg_csr, val);

sys/arch/macppc/dev/zs.c

794

zs_read_csr(struct zs_chanstate *cs)

sys/arch/macppc/dev/zs.c

798

val = in8(cs->cs_reg_csr);

sys/arch/macppc/dev/zs.c

806

zs_write_csr(struct zs_chanstate *cs, u_char val)

sys/arch/macppc/dev/zs.c

809

out8(cs->cs_reg_csr, val);

sys/arch/macppc/dev/zs.c

814

zs_read_data(struct zs_chanstate *cs)

sys/arch/macppc/dev/zs.c

818

val = in8(cs->cs_reg_data);

sys/arch/macppc/dev/zs.c

824

zs_write_data(struct zs_chanstate *cs, u_char val)

sys/arch/macppc/dev/zs.c

826

out8(cs->cs_reg_data, val);

sys/arch/macppc/dev/zs.c

838

zs_enable(struct zs_chanstate *cs)

sys/arch/macppc/dev/zs.c

841

cs->enabled = 1;

sys/arch/macppc/dev/zs.c

846

zs_disable(struct zs_chanstate *cs)

sys/arch/macppc/dev/zs.c

849

cs->enabled = 0;

sys/arch/macppc/include/z8530var.h

117

u_char zs_read_reg(struct zs_chanstate *cs, u_char reg);

sys/arch/macppc/include/z8530var.h

118

u_char zs_read_csr(struct zs_chanstate *cs);

sys/arch/macppc/include/z8530var.h

119

u_char zs_read_data(struct zs_chanstate *cs);

sys/arch/macppc/include/z8530var.h

121

void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);

sys/arch/macppc/include/z8530var.h

122

void zs_write_csr(struct zs_chanstate *cs, u_char val);

sys/arch/macppc/include/z8530var.h

123

void zs_write_data(struct zs_chanstate *cs, u_char val);

sys/arch/macppc/include/z8530var.h

129

int zsmdioctl(struct zs_chanstate *cs, u_long cmd, caddr_t data);

sys/arch/macppc/include/z8530var.h

136

void zsmd_setclock(struct zs_chanstate *cs);

sys/arch/macppc/include/z8530var.h

137

#define ZS_MD_SETCLK(cs) zsmd_setclock(cs)

sys/arch/octeon/stand/rdboot/cmd.c

180

const struct cmd_table *ct = cmd_table, *cs;

sys/arch/octeon/stand/rdboot/cmd.c

195

cs = NULL;

sys/arch/octeon/stand/rdboot/cmd.c

202

cs = cmd_set;

sys/arch/octeon/stand/rdboot/cmd.c

205

cs = MACHINE_CMD;

sys/arch/octeon/stand/rdboot/cmd.c

209

if (cs != NULL) {

sys/arch/octeon/stand/rdboot/cmd.c

210

p = whatcmd(&cs, p);

sys/arch/octeon/stand/rdboot/cmd.c

211

if (cs == NULL) {

sys/arch/octeon/stand/rdboot/cmd.c

215

ct = cs;

sys/arch/powerpc64/stand/rdboot/cmd.c

178

const struct cmd_table *ct = cmd_table, *cs;

sys/arch/powerpc64/stand/rdboot/cmd.c

193

cs = NULL;

sys/arch/powerpc64/stand/rdboot/cmd.c

200

cs = cmd_set;

sys/arch/powerpc64/stand/rdboot/cmd.c

203

cs = MACHINE_CMD;

sys/arch/powerpc64/stand/rdboot/cmd.c

207

if (cs != NULL) {

sys/arch/powerpc64/stand/rdboot/cmd.c

208

p = whatcmd(&cs, p);

sys/arch/powerpc64/stand/rdboot/cmd.c

209

if (cs == NULL) {

sys/arch/powerpc64/stand/rdboot/cmd.c

213

ct = cs;

sys/arch/sparc64/dev/z8530kbd.c

1001

struct zskbd_softc *zst = cs->cs_private;

sys/arch/sparc64/dev/z8530kbd.c

274

struct zs_chanstate *cs;

sys/arch/sparc64/dev/z8530kbd.c

288

cs = zsc->zsc_cs[channel];

sys/arch/sparc64/dev/z8530kbd.c

289

cs->cs_private = zst;

sys/arch/sparc64/dev/z8530kbd.c

290

cs->cs_ops = &zsops_kbd;

sys/arch/sparc64/dev/z8530kbd.c

292

zst->zst_cs = cs;

sys/arch/sparc64/dev/z8530kbd.c

325

if (!cs->enable)

sys/arch/sparc64/dev/z8530kbd.c

326

cs->enabled = 1;

sys/arch/sparc64/dev/z8530kbd.c

342

zs_write_reg(cs, 9, reset);

sys/arch/sparc64/dev/z8530kbd.c

354

SET(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_SIE);

sys/arch/sparc64/dev/z8530kbd.c

355

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/arch/sparc64/dev/z8530kbd.c

405

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

410

if (zs_set_speed(cs, 1200)) { /* set 1200bps */

sys/arch/sparc64/dev/z8530kbd.c

414

if (zs_set_modes(cs, CS8 | CLOCAL)) {

sys/arch/sparc64/dev/z8530kbd.c

423

v3 = cs->cs_preg[3]; /* set 8 bit chars */

sys/arch/sparc64/dev/z8530kbd.c

424

v5 = cs->cs_preg[5];

sys/arch/sparc64/dev/z8530kbd.c

429

cs->cs_preg[3] = v3;

sys/arch/sparc64/dev/z8530kbd.c

430

cs->cs_preg[5] = v5;

sys/arch/sparc64/dev/z8530kbd.c

432

v4 = cs->cs_preg[4]; /* no parity 1 stop */

sys/arch/sparc64/dev/z8530kbd.c

435

cs->cs_preg[4] = v4;

sys/arch/sparc64/dev/z8530kbd.c

437

if (!cs->cs_heldchange) {

sys/arch/sparc64/dev/z8530kbd.c

441

cs->cs_heldchange = 1;

sys/arch/sparc64/dev/z8530kbd.c

443

zs_loadchannelregs(cs);

sys/arch/sparc64/dev/z8530kbd.c

456

cs->cs_softreq = 1;

sys/arch/sparc64/dev/z8530kbd.c

467

zskbd_stint(cs, 1);

sys/arch/sparc64/dev/z8530kbd.c

480

zskbd_softint(cs);

sys/arch/sparc64/dev/z8530kbd.c

497

rr0 = *cs->cs_reg_csr;

sys/arch/sparc64/dev/z8530kbd.c

499

sunkbd_raw(ss, *cs->cs_reg_data);

sys/arch/sparc64/dev/z8530kbd.c

511

rr0 = *cs->cs_reg_csr;

sys/arch/sparc64/dev/z8530kbd.c

513

sunkbd_raw(ss, *cs->cs_reg_data);

sys/arch/sparc64/dev/z8530kbd.c

530

rr0 = *cs->cs_reg_csr;

sys/arch/sparc64/dev/z8530kbd.c

532

sunkbd_raw(ss, *cs->cs_reg_data);

sys/arch/sparc64/dev/z8530kbd.c

592

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

606

if (!ISSET(cs->cs_preg[1], ZSWR1_TIE)) {

sys/arch/sparc64/dev/z8530kbd.c

607

SET(cs->cs_preg[1], ZSWR1_TIE);

sys/arch/sparc64/dev/z8530kbd.c

608

cs->cs_creg[1] = cs->cs_preg[1];

sys/arch/sparc64/dev/z8530kbd.c

609

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/arch/sparc64/dev/z8530kbd.c

612

zs_write_data(cs, *zst->zst_tba);

sys/arch/sparc64/dev/z8530kbd.c

632

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

635

cs->cs_rr0_mask = cs->cs_rr0_cts | cs->cs_rr0_dcd;

sys/arch/sparc64/dev/z8530kbd.c

637

cs->cs_rr0_mask |= cs->cs_rr0_pps;

sys/arch/sparc64/dev/z8530kbd.c

638

tmp15 = cs->cs_preg[15];

sys/arch/sparc64/dev/z8530kbd.c

639

if (ISSET(cs->cs_rr0_mask, ZSRR0_DCD))

sys/arch/sparc64/dev/z8530kbd.c

643

if (ISSET(cs->cs_rr0_mask, ZSRR0_CTS))

sys/arch/sparc64/dev/z8530kbd.c

647

cs->cs_preg[15] = tmp15;

sys/arch/sparc64/dev/z8530kbd.c

658

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

660

if (cs->cs_wr5_dtr == 0)

sys/arch/sparc64/dev/z8530kbd.c

664

SET(cs->cs_preg[5], cs->cs_wr5_dtr);

sys/arch/sparc64/dev/z8530kbd.c

666

CLR(cs->cs_preg[5], cs->cs_wr5_dtr);

sys/arch/sparc64/dev/z8530kbd.c

668

if (!cs->cs_heldchange) {

sys/arch/sparc64/dev/z8530kbd.c

672

cs->cs_heldchange = 1;

sys/arch/sparc64/dev/z8530kbd.c

674

zs_loadchannelregs(cs);

sys/arch/sparc64/dev/z8530kbd.c

685

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

687

if (cs->cs_wr5_rts == 0)

sys/arch/sparc64/dev/z8530kbd.c

691

CLR(cs->cs_preg[5], cs->cs_wr5_rts);

sys/arch/sparc64/dev/z8530kbd.c

692

CLR(cs->cs_creg[5], cs->cs_wr5_rts);

sys/arch/sparc64/dev/z8530kbd.c

694

SET(cs->cs_preg[5], cs->cs_wr5_rts);

sys/arch/sparc64/dev/z8530kbd.c

695

SET(cs->cs_creg[5], cs->cs_wr5_rts);

sys/arch/sparc64/dev/z8530kbd.c

697

zs_write_reg(cs, 5, cs->cs_creg[5]);

sys/arch/sparc64/dev/z8530kbd.c

714

zskbd_rxint(struct zs_chanstate *cs)

sys/arch/sparc64/dev/z8530kbd.c

716

struct zskbd_softc *zst = cs->cs_private;

sys/arch/sparc64/dev/z8530kbd.c

730

rr1 = zs_read_reg(cs, 1);

sys/arch/sparc64/dev/z8530kbd.c

731

c = zs_read_data(cs);

sys/arch/sparc64/dev/z8530kbd.c

735

zs_write_csr(cs, ZSWR0_RESET_ERRORS);

sys/arch/sparc64/dev/z8530kbd.c

745

rr0 = zs_read_csr(cs);

sys/arch/sparc64/dev/z8530kbd.c

760

cs->cs_softreq = 1;

sys/arch/sparc64/dev/z8530kbd.c

779

CLR(cs->cs_preg[1], ZSWR1_RIE);

sys/arch/sparc64/dev/z8530kbd.c

780

cs->cs_creg[1] = cs->cs_preg[1];

sys/arch/sparc64/dev/z8530kbd.c

781

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/arch/sparc64/dev/z8530kbd.c

789

zskbd_txint(struct zs_chanstate *cs)

sys/arch/sparc64/dev/z8530kbd.c

791

struct zskbd_softc *zst = cs->cs_private;

sys/arch/sparc64/dev/z8530kbd.c

797

if (cs->cs_heldchange) {

sys/arch/sparc64/dev/z8530kbd.c

798

zs_loadchannelregs(cs);

sys/arch/sparc64/dev/z8530kbd.c

799

cs->cs_heldchange = 0;

sys/arch/sparc64/dev/z8530kbd.c

806

zs_write_data(cs, *zst->zst_tba);

sys/arch/sparc64/dev/z8530kbd.c

812

if (ISSET(cs->cs_preg[1], ZSWR1_TIE)) {

sys/arch/sparc64/dev/z8530kbd.c

813

CLR(cs->cs_preg[1], ZSWR1_TIE);

sys/arch/sparc64/dev/z8530kbd.c

814

cs->cs_creg[1] = cs->cs_preg[1];

sys/arch/sparc64/dev/z8530kbd.c

815

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/arch/sparc64/dev/z8530kbd.c

820

cs->cs_softreq = 1;

sys/arch/sparc64/dev/z8530kbd.c

829

zskbd_stint(struct zs_chanstate *cs, int force)

sys/arch/sparc64/dev/z8530kbd.c

831

struct zskbd_softc *zst = cs->cs_private;

sys/arch/sparc64/dev/z8530kbd.c

834

rr0 = zs_read_csr(cs);

sys/arch/sparc64/dev/z8530kbd.c

835

zs_write_csr(cs, ZSWR0_RESET_STATUS);

sys/arch/sparc64/dev/z8530kbd.c

842

delta = rr0 ^ cs->cs_rr0;

sys/arch/sparc64/dev/z8530kbd.c

844

delta = cs->cs_rr0_mask;

sys/arch/sparc64/dev/z8530kbd.c

845

cs->cs_rr0 = rr0;

sys/arch/sparc64/dev/z8530kbd.c

847

if (ISSET(delta, cs->cs_rr0_mask)) {

sys/arch/sparc64/dev/z8530kbd.c

848

SET(cs->cs_rr0_delta, delta);

sys/arch/sparc64/dev/z8530kbd.c

854

if (ISSET(~rr0, cs->cs_rr0_mask)) {

sys/arch/sparc64/dev/z8530kbd.c

860

cs->cs_softreq = 1;

sys/arch/sparc64/dev/z8530kbd.c

890

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

946

SET(cs->cs_preg[1], ZSWR1_RIE);

sys/arch/sparc64/dev/z8530kbd.c

947

cs->cs_creg[1] = cs->cs_preg[1];

sys/arch/sparc64/dev/z8530kbd.c

948

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/arch/sparc64/dev/z8530kbd.c

967

struct zs_chanstate *cs = zst->zst_cs;

sys/arch/sparc64/dev/z8530kbd.c

972

rr0 = cs->cs_rr0;

sys/arch/sparc64/dev/z8530kbd.c

973

delta = cs->cs_rr0_delta;

sys/arch/sparc64/dev/z8530kbd.c

974

cs->cs_rr0_delta = 0;

sys/arch/sparc64/dev/z8530kbd.c

977

if (ISSET(delta, cs->cs_rr0_cts)) {

sys/arch/sparc64/dev/z8530kbd.c

979

if (ISSET(rr0, cs->cs_rr0_cts))

sys/arch/sparc64/dev/z8530kbd.c

999

zskbd_softint(struct zs_chanstate *cs)

sys/arch/sparc64/dev/zs.c

295

struct zs_chanstate *cs;

sys/arch/sparc64/dev/zs.c

316

cs = &zsc->zsc_cs_store[channel];

sys/arch/sparc64/dev/zs.c

317

zsc->zsc_cs[channel] = cs;

sys/arch/sparc64/dev/zs.c

319

cs->cs_channel = channel;

sys/arch/sparc64/dev/zs.c

320

cs->cs_private = NULL;

sys/arch/sparc64/dev/zs.c

321

cs->cs_ops = &zsops_null;

sys/arch/sparc64/dev/zs.c

322

cs->cs_brg_clk = PCLK / 16;

sys/arch/sparc64/dev/zs.c

349

cs->cs_reg_csr = &zc->zc_csr;

sys/arch/sparc64/dev/zs.c

350

cs->cs_reg_data = &zc->zc_data;

sys/arch/sparc64/dev/zs.c

352

bcopy(zs_init_reg, cs->cs_creg, 16);

sys/arch/sparc64/dev/zs.c

353

bcopy(zs_init_reg, cs->cs_preg, 16);

sys/arch/sparc64/dev/zs.c

356

cs->cs_defspeed = zs_get_speed(cs);

sys/arch/sparc64/dev/zs.c

357

cs->cs_defcflag = zs_def_cflag;

sys/arch/sparc64/dev/zs.c

360

cs->cs_rr0_dcd = ZSRR0_DCD;

sys/arch/sparc64/dev/zs.c

361

cs->cs_rr0_cts = 0;

sys/arch/sparc64/dev/zs.c

362

cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;

sys/arch/sparc64/dev/zs.c

363

cs->cs_wr5_rts = 0;

sys/arch/sparc64/dev/zs.c

371

zs_write_reg(cs, 9, 0);

sys/arch/sparc64/dev/zs.c

384

zs_write_reg(cs, 9, reset);

sys/arch/sparc64/dev/zs.c

402

cs = zsc->zsc_cs[0];

sys/arch/sparc64/dev/zs.c

405

zs_write_reg(cs, 2, zs_init_reg[2]);

sys/arch/sparc64/dev/zs.c

407

zs_write_reg(cs, 9, zs_init_reg[9]);

sys/arch/sparc64/dev/zs.c

472

zs_get_speed(struct zs_chanstate *cs)

sys/arch/sparc64/dev/zs.c

476

tconst = zs_read_reg(cs, 12);

sys/arch/sparc64/dev/zs.c

477

tconst |= zs_read_reg(cs, 13) << 8;

sys/arch/sparc64/dev/zs.c

478

return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));

sys/arch/sparc64/dev/zs.c

485

zs_set_speed(struct zs_chanstate *cs, int bps)

sys/arch/sparc64/dev/zs.c

493

if (cs->cs_brg_clk == 0)

sys/arch/sparc64/dev/zs.c

497

tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);

sys/arch/sparc64/dev/zs.c

502

real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);

sys/arch/sparc64/dev/zs.c

508

cs->cs_preg[12] = tconst;

sys/arch/sparc64/dev/zs.c

509

cs->cs_preg[13] = tconst >> 8;

sys/arch/sparc64/dev/zs.c

516

zs_set_modes(struct zs_chanstate *cs, int cflag)

sys/arch/sparc64/dev/zs.c

528

cs->cs_rr0_pps = 0;

sys/arch/sparc64/dev/zs.c

530

cs->cs_rr0_dcd = 0;

sys/arch/sparc64/dev/zs.c

532

cs->cs_rr0_pps = ZSRR0_DCD;

sys/arch/sparc64/dev/zs.c

534

cs->cs_rr0_dcd = ZSRR0_DCD;

sys/arch/sparc64/dev/zs.c

536

cs->cs_wr5_dtr = ZSWR5_DTR;

sys/arch/sparc64/dev/zs.c

537

cs->cs_wr5_rts = ZSWR5_RTS;

sys/arch/sparc64/dev/zs.c

538

cs->cs_rr0_cts = ZSRR0_CTS;

sys/arch/sparc64/dev/zs.c

541

cs->cs_wr5_dtr = 0;

sys/arch/sparc64/dev/zs.c

542

cs->cs_wr5_rts = ZSWR5_DTR;

sys/arch/sparc64/dev/zs.c

543

cs->cs_rr0_cts = ZSRR0_CTS;

sys/arch/sparc64/dev/zs.c

546

cs->cs_wr5_dtr = 0;

sys/arch/sparc64/dev/zs.c

547

cs->cs_wr5_rts = ZSWR5_DTR;

sys/arch/sparc64/dev/zs.c

548

cs->cs_rr0_cts = ZSRR0_DCD;

sys/arch/sparc64/dev/zs.c

550

cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;

sys/arch/sparc64/dev/zs.c

551

cs->cs_wr5_rts = 0;

sys/arch/sparc64/dev/zs.c

552

cs->cs_rr0_cts = 0;

sys/arch/sparc64/dev/zs.c

566

zs_read_reg(struct zs_chanstate *cs, u_char reg)

sys/arch/sparc64/dev/zs.c

570

*cs->cs_reg_csr = reg;

sys/arch/sparc64/dev/zs.c

572

val = *cs->cs_reg_csr;

sys/arch/sparc64/dev/zs.c

578

zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)

sys/arch/sparc64/dev/zs.c

580

*cs->cs_reg_csr = reg;

sys/arch/sparc64/dev/zs.c

582

*cs->cs_reg_csr = val;

sys/arch/sparc64/dev/zs.c

587

zs_read_csr(struct zs_chanstate *cs)

sys/arch/sparc64/dev/zs.c

591

val = *cs->cs_reg_csr;

sys/arch/sparc64/dev/zs.c

597

zs_write_csr(struct zs_chanstate *cs, u_char val)

sys/arch/sparc64/dev/zs.c

599

*cs->cs_reg_csr = val;

sys/arch/sparc64/dev/zs.c

604

zs_read_data(struct zs_chanstate *cs)

sys/arch/sparc64/dev/zs.c

608

val = *cs->cs_reg_data;

sys/arch/sparc64/dev/zs.c

614

zs_write_data(struct zs_chanstate *cs, u_char val)

sys/arch/sparc64/dev/zs.c

616

*cs->cs_reg_data = val;

sys/arch/sparc64/dev/zs.c

631

zs_abort(struct zs_chanstate *cs)

sys/arch/sparc64/include/z8530var.h

66

u_char zs_read_reg(struct zs_chanstate *cs, u_char reg);

sys/arch/sparc64/include/z8530var.h

67

u_char zs_read_csr(struct zs_chanstate *cs);

sys/arch/sparc64/include/z8530var.h

68

u_char zs_read_data(struct zs_chanstate *cs);

sys/arch/sparc64/include/z8530var.h

70

void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);

sys/arch/sparc64/include/z8530var.h

71

void zs_write_csr(struct zs_chanstate *cs, u_char val);

sys/arch/sparc64/include/z8530var.h

72

void zs_write_data(struct zs_chanstate *cs, u_char val);

sys/dev/fdt/bcm2835_dmac.c

204

uint32_t cs, ce;

sys/dev/fdt/bcm2835_dmac.c

206

cs = bcmdmac_read(sc, DMAC_CS(ch->ch_index));

sys/dev/fdt/bcm2835_dmac.c

207

bcmdmac_write(sc, DMAC_CS(ch->ch_index), cs);

sys/dev/fdt/bcm2835_dmac.c

208

cs &= DMAC_CS_INT | DMAC_CS_END | DMAC_CS_ERROR;

sys/dev/fdt/bcm2835_dmac.c

216

ch->ch_callback(cs, ce, ch->ch_callbackarg);

sys/dev/fdt/if_mvneta.c

351

struct mbus_dram_window *win = &mvmbus_dram_info->cs[i];

sys/dev/fdt/imxspi.c

230

int cs;

sys/dev/fdt/imxspi.c

232

cs = conf->sc_cs;

sys/dev/fdt/imxspi.c

233

if (cs > 4) {

sys/dev/fdt/imxspi.c

234

printf("%s: invalid chip-select (%d)\n", DEVNAME(sc), cs);

sys/dev/fdt/imxspi.c

237

sc->sc_cs = cs;

sys/dev/fdt/imxspi.c

243

conreg |= SPI_CONREG_CHANNEL_SELECT(cs);

sys/dev/fdt/imxspi.c

247

configreg &= ~SPI_CONFIGREG_SCLK_PHA(cs);

sys/dev/fdt/imxspi.c

249

configreg |= SPI_CONFIGREG_SCLK_PHA(cs);

sys/dev/fdt/imxspi.c

250

configreg &= ~SPI_CONFIGREG_SCLK_POL(cs);

sys/dev/fdt/imxspi.c

251

configreg &= ~SPI_CONFIGREG_SCLK_CTL(cs);

sys/dev/fdt/imxspi.c

253

configreg |= SPI_CONFIGREG_SCLK_POL(cs);

sys/dev/fdt/imxspi.c

254

configreg |= SPI_CONFIGREG_SCLK_CTL(cs);

sys/dev/fdt/imxspi.c

256

configreg |= SPI_CONFIGREG_SS_CTL(cs);

sys/dev/fdt/imxspi.c

257

configreg &= ~SPI_CONFIGREG_SS_POL(cs);

sys/dev/fdt/imxspi.c

259

configreg |= SPI_CONFIGREG_SS_POL(cs);

sys/dev/fdt/imxspi.c

307

imxspi_find_cs_gpio(struct imxspi_softc *sc, int cs)

sys/dev/fdt/imxspi.c

316

if (cs == 0)

sys/dev/fdt/imxspi.c

319

cs--;

sys/dev/fdt/mvspi.c

173

int cs;

sys/dev/fdt/mvspi.c

175

cs = conf->sc_cs;

sys/dev/fdt/mvspi.c

176

if (cs > 4) {

sys/dev/fdt/mvspi.c

177

printf("%s: invalid chip-select (%d)\n", DEVNAME(sc), cs);

sys/dev/fdt/mvspi.c

180

sc->sc_cs = cs;

sys/dev/fdt/mvspi.c

225

mvspi_set_cs(struct mvspi_softc *sc, int cs, int on)

sys/dev/fdt/mvspi.c

228

HSET4(sc, SPI_CTRL, SPI_CTRL_CS(cs));

sys/dev/fdt/mvspi.c

230

HCLR4(sc, SPI_CTRL, SPI_CTRL_CS(cs));

sys/dev/fdt/rkspi.c

207

int cs;

sys/dev/fdt/rkspi.c

216

cs = conf->sc_cs;

sys/dev/fdt/rkspi.c

217

if (cs >= 2) {

sys/dev/fdt/rkspi.c

218

printf("%s: invalid chip-select (%d)\n", DEVNAME(sc), cs);

sys/dev/fdt/rkspi.c

221

sc->sc_cs = cs;

sys/dev/ic/aic79xx.c

2595

struct cs *cs;

sys/dev/ic/aic79xx.c

2602

cs = ahd->critical_sections;

sys/dev/ic/aic79xx.c

2603

for (i = 0; i < ahd->num_critical_sections; i++, cs++) {

sys/dev/ic/aic79xx.c

2605

if (cs->begin < seqaddr && cs->end >= seqaddr)

sys/dev/ic/aic79xx.c

8288

struct cs cs_table[NUM_CRITICAL_SECTIONS];

sys/dev/ic/aic79xx.c

8430

sizeof(struct cs), M_DEVBUF, M_NOWAIT);

sys/dev/ic/aic79xx.c

8433

cs_count *= sizeof(struct cs);

sys/dev/ic/aic79xx.h

1159

struct cs *critical_sections;

sys/dev/ic/aic7xxx.c

1467

struct cs *cs;

sys/dev/ic/aic7xxx.c

1479

cs = ahc->critical_sections;

sys/dev/ic/aic7xxx.c

1480

for (i = 0; i < ahc->num_critical_sections; i++, cs++) {

sys/dev/ic/aic7xxx.c

1482

if (cs->begin < seqaddr && cs->end >= seqaddr)

sys/dev/ic/aic7xxx.c

6100

struct cs cs_table[NUM_CRITICAL_SECTIONS];

sys/dev/ic/aic7xxx.c

6191

sizeof(struct cs), M_DEVBUF, M_NOWAIT);

sys/dev/ic/aic7xxx.c

6194

cs_count *= sizeof(struct cs);

sys/dev/ic/aic7xxxvar.h

1035

struct cs *critical_sections;

sys/dev/ic/i82365.c

381

const char *cs;

sys/dev/ic/i82365.c

385

cs = "0,0";

sys/dev/ic/i82365.c

388

cs = "0,1";

sys/dev/ic/i82365.c

391

cs = "1,0";

sys/dev/ic/i82365.c

394

cs = "1,1";

sys/dev/ic/i82365.c

400

snprintf(name, sizeof name, "%s,%s", h->ph_parent->dv_xname, cs);

sys/dev/ic/tcic2.c

436

const char *cs;

sys/dev/ic/tcic2.c

440

cs = "0";

sys/dev/ic/tcic2.c

443

cs = "1";

sys/dev/ic/tcic2.c

449

snprintf(name, sizeof name, "%s,%s", h->sc->dev.dv_xname, cs);

sys/dev/ic/z8530sc.c

109

zs_break(struct zs_chanstate *cs, int set)

sys/dev/ic/z8530sc.c

113

cs->cs_preg[5] |= ZSWR5_BREAK;

sys/dev/ic/z8530sc.c

114

cs->cs_creg[5] |= ZSWR5_BREAK;

sys/dev/ic/z8530sc.c

116

cs->cs_preg[5] &= ~ZSWR5_BREAK;

sys/dev/ic/z8530sc.c

117

cs->cs_creg[5] &= ~ZSWR5_BREAK;

sys/dev/ic/z8530sc.c

119

zs_write_reg(cs, 5, cs->cs_creg[5]);

sys/dev/ic/z8530sc.c

127

zs_iflush(struct zs_chanstate *cs)

sys/dev/ic/z8530sc.c

138

rr0 = zs_read_csr(cs);

sys/dev/ic/z8530sc.c

146

rr1 = zs_read_reg(cs, 1);

sys/dev/ic/z8530sc.c

147

c = zs_read_data(cs);

sys/dev/ic/z8530sc.c

151

zs_write_csr(cs, ZSWR0_RESET_ERRORS);

sys/dev/ic/z8530sc.c

164

zs_loadchannelregs(struct zs_chanstate *cs)

sys/dev/ic/z8530sc.c

168

zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */

sys/dev/ic/z8530sc.c

175

zs_iflush(cs); /* XXX */

sys/dev/ic/z8530sc.c

178

if (cs->cs_ctl_chan != NULL)

sys/dev/ic/z8530sc.c

179

v = ((cs->cs_ctl_chan->cs_creg[5] & (ZSWR5_RTS | ZSWR5_DTR)) !=

sys/dev/ic/z8530sc.c

180

(cs->cs_ctl_chan->cs_preg[5] & (ZSWR5_RTS | ZSWR5_DTR)));

sys/dev/ic/z8530sc.c

184

if (memcmp((void *)cs->cs_preg, (void *)cs->cs_creg, 16) == 0 && !v)

sys/dev/ic/z8530sc.c

188

memcpy((void *)cs->cs_creg, (void *)cs->cs_preg, 16);

sys/dev/ic/z8530sc.c

189

reg = cs->cs_creg; /* current regs */

sys/dev/ic/z8530sc.c

192

zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK);

sys/dev/ic/z8530sc.c

195

zs_write_reg(cs, 4, reg[4]);

sys/dev/ic/z8530sc.c

198

zs_write_reg(cs, 10, reg[10]);

sys/dev/ic/z8530sc.c

201

zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);

sys/dev/ic/z8530sc.c

202

zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);

sys/dev/ic/z8530sc.c

205

zs_write_reg(cs, 6, reg[6]);

sys/dev/ic/z8530sc.c

207

zs_write_reg(cs, 15, 0);

sys/dev/ic/z8530sc.c

208

zs_write_reg(cs, 7, reg[7]);

sys/dev/ic/z8530sc.c

219

zs_write_reg(cs, 2, reg[2]);

sys/dev/ic/z8530sc.c

221

zs_write_reg(cs, 9, reg[9]);

sys/dev/ic/z8530sc.c

225

zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA);

sys/dev/ic/z8530sc.c

229

ZS_MD_SETCLK(cs);

sys/dev/ic/z8530sc.c

233

zs_write_reg(cs, 11, reg[11]);

sys/dev/ic/z8530sc.c

236

zs_write_reg(cs, 12, reg[12]);

sys/dev/ic/z8530sc.c

237

zs_write_reg(cs, 13, reg[13]);

sys/dev/ic/z8530sc.c

240

zs_write_reg(cs, 14, reg[14]);

sys/dev/ic/z8530sc.c

243

zs_write_reg(cs, 15, reg[15]);

sys/dev/ic/z8530sc.c

251

zs_write_csr(cs, ZSM_RESET_STINT);

sys/dev/ic/z8530sc.c

252

zs_write_csr(cs, ZSM_RESET_STINT);

sys/dev/ic/z8530sc.c

255

zs_write_reg(cs, 3, reg[3]);

sys/dev/ic/z8530sc.c

256

zs_write_reg(cs, 5, reg[5]);

sys/dev/ic/z8530sc.c

259

if (cs->cs_ctl_chan != NULL) {

sys/dev/ic/z8530sc.c

260

v = cs->cs_ctl_chan->cs_preg[5];

sys/dev/ic/z8530sc.c

261

cs->cs_ctl_chan->cs_creg[5] = v;

sys/dev/ic/z8530sc.c

262

zs_write_reg(cs->cs_ctl_chan, 5, v);

sys/dev/ic/z8530sc.c

267

zs_write_reg(cs, 7, reg[16]);

sys/dev/ic/z8530sc.c

270

zs_write_reg(cs, 1, reg[1]);

sys/dev/ic/z8530sc.c

347

struct zs_chanstate *cs;

sys/dev/ic/z8530sc.c

352

cs = zsc->zsc_cs[chan];

sys/dev/ic/z8530sc.c

359

if (cs->cs_softreq) {

sys/dev/ic/z8530sc.c

360

cs->cs_softreq = 0;

sys/dev/ic/z8530sc.c

361

(*cs->cs_ops->zsop_softint)(cs);

sys/dev/ic/z8530sc.c

378

zsnull_rxint(struct zs_chanstate *cs)

sys/dev/ic/z8530sc.c

382

cs->cs_softreq = 1;

sys/dev/ic/z8530sc.c

386

zsnull_stint(struct zs_chanstate *cs, int force)

sys/dev/ic/z8530sc.c

390

cs->cs_softreq = 1;

sys/dev/ic/z8530sc.c

394

zsnull_txint(struct zs_chanstate *cs)

sys/dev/ic/z8530sc.c

398

cs->cs_softreq = 1;

sys/dev/ic/z8530sc.c

402

zsnull_softint(struct zs_chanstate *cs)

sys/dev/ic/z8530sc.c

405

zs_write_reg(cs, 1, 0);

sys/dev/ic/z8530sc.c

406

zs_write_reg(cs, 15, 0);

sys/dev/ic/z8530tty.c

1007

if (!cs->cs_heldchange) {

sys/dev/ic/z8530tty.c

1011

cs->cs_heldchange = 1;

sys/dev/ic/z8530tty.c

1013

zs_loadchannelregs(cs);

sys/dev/ic/z8530tty.c

1027

cs->cs_softreq = 1;

sys/dev/ic/z8530tty.c

1042

zstty_stint(cs, 1);

sys/dev/ic/z8530tty.c

1057

zstty_softint(cs);

sys/dev/ic/z8530tty.c

1070

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

1073

cs->cs_rr0_mask = cs->cs_rr0_cts | cs->cs_rr0_dcd;

sys/dev/ic/z8530tty.c

1075

cs->cs_rr0_mask |= cs->cs_rr0_pps;

sys/dev/ic/z8530tty.c

1076

tmp15 = cs->cs_preg[15];

sys/dev/ic/z8530tty.c

1077

if (ISSET(cs->cs_rr0_mask, ZSRR0_DCD))

sys/dev/ic/z8530tty.c

1081

if (ISSET(cs->cs_rr0_mask, ZSRR0_CTS))

sys/dev/ic/z8530tty.c

1085

cs->cs_preg[15] = tmp15;

sys/dev/ic/z8530tty.c

1097

struct zs_chanstate *cs = zst->zst_cs, *ccs;

sys/dev/ic/z8530tty.c

1099

if (cs->cs_wr5_dtr == 0)

sys/dev/ic/z8530tty.c

1102

ccs = (cs->cs_ctl_chan != NULL ? cs->cs_ctl_chan : cs);

sys/dev/ic/z8530tty.c

1105

SET(ccs->cs_preg[5], cs->cs_wr5_dtr);

sys/dev/ic/z8530tty.c

1107

CLR(ccs->cs_preg[5], cs->cs_wr5_dtr);

sys/dev/ic/z8530tty.c

1109

if (!cs->cs_heldchange) {

sys/dev/ic/z8530tty.c

1113

cs->cs_heldchange = 1;

sys/dev/ic/z8530tty.c

1115

zs_loadchannelregs(cs);

sys/dev/ic/z8530tty.c

1126

struct zs_chanstate *cs = zst->zst_cs, *ccs;

sys/dev/ic/z8530tty.c

1129

ccs = (cs->cs_ctl_chan != NULL ? cs->cs_ctl_chan : cs);

sys/dev/ic/z8530tty.c

1152

if (!cs->cs_heldchange) {

sys/dev/ic/z8530tty.c

1156

cs->cs_heldchange = 1;

sys/dev/ic/z8530tty.c

1158

zs_loadchannelregs(cs);

sys/dev/ic/z8530tty.c

1169

struct zs_chanstate *cs = zst->zst_cs, *ccs;

sys/dev/ic/z8530tty.c

1173

ccs = (cs->cs_ctl_chan != NULL ? cs->cs_ctl_chan : cs);

sys/dev/ic/z8530tty.c

1181

zsbits = cs->cs_rr0;

sys/dev/ic/z8530tty.c

1200

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

1203

if (cs->cs_wr5_rts == 0)

sys/dev/ic/z8530tty.c

1216

cs->cs_softreq = 1;

sys/dev/ic/z8530tty.c

1234

struct zs_chanstate *cs = zst->zst_cs, *ccs;

sys/dev/ic/z8530tty.c

1236

if (cs->cs_wr5_rts == 0)

sys/dev/ic/z8530tty.c

1239

ccs = (cs->cs_ctl_chan != NULL ? cs->cs_ctl_chan : cs);

sys/dev/ic/z8530tty.c

1242

CLR(ccs->cs_preg[5], cs->cs_wr5_rts);

sys/dev/ic/z8530tty.c

1243

CLR(ccs->cs_creg[5], cs->cs_wr5_rts);

sys/dev/ic/z8530tty.c

1245

SET(ccs->cs_preg[5], cs->cs_wr5_rts);

sys/dev/ic/z8530tty.c

1246

SET(ccs->cs_creg[5], cs->cs_wr5_rts);

sys/dev/ic/z8530tty.c

1266

zstty_rxint(struct zs_chanstate *cs)

sys/dev/ic/z8530tty.c

1268

struct zstty_softc *zst = cs->cs_private;

sys/dev/ic/z8530tty.c

1282

rr1 = zs_read_reg(cs, 1);

sys/dev/ic/z8530tty.c

1283

c = zs_read_data(cs);

sys/dev/ic/z8530tty.c

1287

zs_write_csr(cs, ZSWR0_RESET_ERRORS);

sys/dev/ic/z8530tty.c

1297

rr0 = zs_read_csr(cs);

sys/dev/ic/z8530tty.c

1312

cs->cs_softreq = 1;

sys/dev/ic/z8530tty.c

1331

CLR(cs->cs_preg[1], ZSWR1_RIE);

sys/dev/ic/z8530tty.c

1332

cs->cs_creg[1] = cs->cs_preg[1];

sys/dev/ic/z8530tty.c

1333

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/dev/ic/z8530tty.c

1342

zstty_txint(struct zs_chanstate *cs)

sys/dev/ic/z8530tty.c

1344

struct zstty_softc *zst = cs->cs_private;

sys/dev/ic/z8530tty.c

1347

zs_write_csr(cs, ZSWR0_RESET_TXINT);

sys/dev/ic/z8530tty.c

1353

if (cs->cs_heldchange) {

sys/dev/ic/z8530tty.c

1354

zs_loadchannelregs(cs);

sys/dev/ic/z8530tty.c

1355

cs->cs_heldchange = 0;

sys/dev/ic/z8530tty.c

1361

rr0 = zs_read_csr(cs);

sys/dev/ic/z8530tty.c

1365

zs_write_data(cs, *zst->zst_tba);

sys/dev/ic/z8530tty.c

1374

cs->cs_softreq = 1;

sys/dev/ic/z8530tty.c

1391

zstty_stint(struct zs_chanstate *cs, int force)

sys/dev/ic/z8530tty.c

1393

struct zstty_softc *zst = cs->cs_private;

sys/dev/ic/z8530tty.c

1397

rr0 = zs_read_csr(cs);

sys/dev/ic/z8530tty.c

1398

zs_write_csr(cs, ZSWR0_RESET_STATUS);

sys/dev/ic/z8530tty.c

1406

zs_abort(cs);

sys/dev/ic/z8530tty.c

1409

delta = rr0 ^ cs->cs_rr0;

sys/dev/ic/z8530tty.c

1411

delta = cs->cs_rr0_mask;

sys/dev/ic/z8530tty.c

1413

ttytstamp(tp, cs->cs_rr0 & ZSRR0_CTS, rr0 & ZSRR0_CTS,

sys/dev/ic/z8530tty.c

1414

cs->cs_rr0 & ZSRR0_DCD, rr0 & ZSRR0_DCD);

sys/dev/ic/z8530tty.c

1416

cs->cs_rr0 = rr0;

sys/dev/ic/z8530tty.c

1418

if (ISSET(delta, cs->cs_rr0_mask)) {

sys/dev/ic/z8530tty.c

1419

SET(cs->cs_rr0_delta, delta);

sys/dev/ic/z8530tty.c

1425

if (ISSET(~rr0, cs->cs_rr0_mask)) {

sys/dev/ic/z8530tty.c

1431

cs->cs_softreq = 1;

sys/dev/ic/z8530tty.c

1459

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

1540

SET(cs->cs_preg[1], ZSWR1_RIE);

sys/dev/ic/z8530tty.c

1541

cs->cs_creg[1] = cs->cs_preg[1];

sys/dev/ic/z8530tty.c

1542

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/dev/ic/z8530tty.c

1572

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

1577

rr0 = cs->cs_rr0;

sys/dev/ic/z8530tty.c

1578

delta = cs->cs_rr0_delta;

sys/dev/ic/z8530tty.c

1579

cs->cs_rr0_delta = 0;

sys/dev/ic/z8530tty.c

1582

if (ISSET(delta, cs->cs_rr0_dcd)) {

sys/dev/ic/z8530tty.c

1589

if (ISSET(delta, cs->cs_rr0_cts)) {

sys/dev/ic/z8530tty.c

1591

if (ISSET(rr0, cs->cs_rr0_cts)) {

sys/dev/ic/z8530tty.c

1613

zstty_softint(struct zs_chanstate *cs)

sys/dev/ic/z8530tty.c

1615

struct zstty_softc *zst = cs->cs_private;

sys/dev/ic/z8530tty.c

265

struct zs_chanstate *cs;

sys/dev/ic/z8530tty.c

277

cs = zsc->zsc_cs[channel];

sys/dev/ic/z8530tty.c

278

cs->cs_private = zst;

sys/dev/ic/z8530tty.c

279

cs->cs_ops = &zsops_tty;

sys/dev/ic/z8530tty.c

281

zst->zst_cs = cs;

sys/dev/ic/z8530tty.c

343

if (!cs->enable)

sys/dev/ic/z8530tty.c

344

cs->enabled = 1;

sys/dev/ic/z8530tty.c

360

t.c_ospeed = cs->cs_defspeed;

sys/dev/ic/z8530tty.c

361

t.c_cflag = cs->cs_defcflag;

sys/dev/ic/z8530tty.c

371

SET(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE);

sys/dev/ic/z8530tty.c

388

zs_write_reg(cs, 9, resetbit);

sys/dev/ic/z8530tty.c

409

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

420

zs_break(cs, 0);

sys/dev/ic/z8530tty.c

432

tsleep_nsec(cs, TTIPRI, ttclos, SEC_TO_NSEC(1));

sys/dev/ic/z8530tty.c

437

CLR(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE);

sys/dev/ic/z8530tty.c

438

cs->cs_creg[1] = cs->cs_preg[1];

sys/dev/ic/z8530tty.c

439

zs_write_reg(cs, 1, cs->cs_creg[1]);

sys/dev/ic/z8530tty.c

443

if (cs->disable) {

sys/dev/ic/z8530tty.c

445

if (!cs->enabled)

sys/dev/ic/z8530tty.c

448

(*cs->disable)(zst->zst_cs);

sys/dev/ic/z8530tty.c

461

struct zs_chanstate *cs;

sys/dev/ic/z8530tty.c

474

cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

496

if (cs->enable) {

sys/dev/ic/z8530tty.c

497

if ((*cs->enable)(cs)) {

sys/dev/ic/z8530tty.c

510

t.c_ospeed = cs->cs_defspeed;

sys/dev/ic/z8530tty.c

511

t.c_cflag = cs->cs_defcflag;

sys/dev/ic/z8530tty.c

529

SET(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE);

sys/dev/ic/z8530tty.c

571

zs_iflush(cs);

sys/dev/ic/z8530tty.c

586

cs->cs_cua = 1;

sys/dev/ic/z8530tty.c

592

if (!ZSDIALOUT(dev) && cs->cs_cua) {

sys/dev/ic/z8530tty.c

597

while (cs->cs_cua ||

sys/dev/ic/z8530tty.c

604

if (!ZSDIALOUT(dev) && !cs->cs_cua) {

sys/dev/ic/z8530tty.c

617

rr0 = zs_read_csr(cs);

sys/dev/ic/z8530tty.c

629

ISSET(tp->t_state, TS_CARR_ON)) && !cs->cs_cua)

sys/dev/ic/z8530tty.c

635

if (!ZSDIALOUT(dev) && cs->cs_cua && error == EINTR) {

sys/dev/ic/z8530tty.c

653

cs->cs_cua = 0;

sys/dev/ic/z8530tty.c

657

if (!ZSDIALOUT(dev) && cs->cs_cua)

sys/dev/ic/z8530tty.c

689

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

700

cs->cs_cua = 0;

sys/dev/ic/z8530tty.c

741

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

766

zs_break(cs, 1);

sys/dev/ic/z8530tty.c

770

zs_break(cs, 0);

sys/dev/ic/z8530tty.c

821

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

850

rr0 = zs_read_csr(cs);

sys/dev/ic/z8530tty.c

854

zs_write_data(cs, *zst->zst_tba);

sys/dev/ic/z8530tty.c

893

struct zs_chanstate *cs = zst->zst_cs;

sys/dev/ic/z8530tty.c

932

error = zs_set_speed(cs, ospeed);

sys/dev/ic/z8530tty.c

935

error = zs_set_modes(cs, cflag);

sys/dev/ic/z8530tty.c

956

tmp3 = cs->cs_preg[3];

sys/dev/ic/z8530tty.c

957

tmp5 = cs->cs_preg[5];

sys/dev/ic/z8530tty.c

978

cs->cs_preg[3] = tmp3;

sys/dev/ic/z8530tty.c

979

cs->cs_preg[5] = tmp5;

sys/dev/ic/z8530tty.c

986

tmp4 = cs->cs_preg[4];

sys/dev/ic/z8530tty.c

996

cs->cs_preg[4] = tmp4;

sys/dev/isa/uguru.c

109

} cs;

sys/dev/isa/uguru.c

870

if (sc->cs.reading == 0x00) {

sys/dev/isa/uguru.c

876

sensor->value = sc->cs.reading * 1000000 + 273150000;

sys/dev/isa/uguru.c

881

if (sc->cs.reading >= sc->cs.lower)

sys/dev/isa/uguru.c

883

if (sc->cs.reading >= sc->cs.upper)

sys/dev/isa/uguru.c

897

if (sc->cs.reading <= sc->cs.lower ||

sys/dev/isa/uguru.c

898

sc->cs.reading >= sc->cs.upper)

sys/dev/isa/uguru.c

902

sc->cs.reading * sc->uguru_sensors[n].rfact;

sys/dev/isa/uguru.c

913

if (sc->cs.reading == 0x00) {

sys/dev/isa/uguru.c

919

sensor->value = sc->cs.reading * 60;

sys/dev/isa/uguru.c

924

if (sc->cs.reading <= sc->cs.lower)

sys/dev/isa/uguru.c

960

sc->cs.reading = val;

sys/dev/isa/uguru.c

962

sc->cs.lower = data[1];

sys/dev/isa/uguru.c

963

sc->cs.upper = data[2];

sys/dev/isa/uguru.c

982

sc->cs.reading = val;

sys/dev/microcode/aic7xxx/aicasm.c

352

critical_section_t *cs;

sys/dev/microcode/aic7xxx/aicasm.c

442

for (cs = TAILQ_FIRST(&cs_tailq);

sys/dev/microcode/aic7xxx/aicasm.c

443

cs != NULL;

sys/dev/microcode/aic7xxx/aicasm.c

444

cs = TAILQ_NEXT(cs, links)) {

sys/dev/microcode/aic7xxx/aicasm.c

446

cs == TAILQ_FIRST(&cs_tailq) ? "" : ",\n",

sys/dev/microcode/aic7xxx/aicasm.c

447

cs->begin_addr, cs->end_addr);

sys/dev/microcode/aic7xxx/aicasm_gram.y

976

critical_section_t *cs;

sys/dev/microcode/aic7xxx/aicasm_gram.y

983

cs = cs_alloc();

sys/dev/microcode/aic7xxx/aicasm_gram.y

984

cs->begin_addr = instruction_ptr;

sys/dev/microcode/aic7xxx/aicasm_gram.y

992

critical_section_t *cs;

sys/dev/microcode/aic7xxx/aicasm_gram.y

998

cs = TAILQ_LAST(&cs_tailq, cs_tailq);

sys/dev/microcode/aic7xxx/aicasm_gram.y

999

cs->end_addr = instruction_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1283

union drm_amdgpu_cs *cs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1367

cs->out.handle = seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

177

union drm_amdgpu_cs *cs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

188

chunk_array = memdup_array_user(u64_to_user_ptr(cs->in.chunks),

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

189

cs->in.num_chunks,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

194

p->nchunks = cs->in.num_chunks;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

48

union drm_amdgpu_cs *cs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

52

if (cs->in.num_chunks == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

59

p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

856

union drm_amdgpu_cs *cs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

868

if (cs->in.bo_list_handle) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

872

r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1366

struct clock_source *cs,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1371

struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

569

struct clock_source *cs,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

573

struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

586

if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

587

cs->id == CLOCK_SOURCE_ID_EXTERNAL) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

602

struct clock_source *cs,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

606

struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

618

if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

619

cs->id == CLOCK_SOURCE_ID_EXTERNAL) {

sys/dev/pci/drm/amd/display/modules/inc/mod_info_packet.h

38

enum dc_color_space cs,

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

135

enum dc_color_space cs,

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

364

if ((cs == COLOR_SPACE_SRGB) ||

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

365

(cs == COLOR_SPACE_SRGB_LIMITED))

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

367

else if (cs == COLOR_SPACE_ADOBERGB)

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

369

else if ((cs == COLOR_SPACE_2020_RGB_FULLRANGE) ||

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

370

(cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE))

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

380

if (cs == COLOR_SPACE_YCBCR601)

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

382

else if (cs == COLOR_SPACE_YCBCR709)

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

384

else if (cs == COLOR_SPACE_ADOBERGB)

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

386

else if (cs == COLOR_SPACE_2020_YCBCR_LIMITED)

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

389

if (cs == COLOR_SPACE_2020_YCBCR_LIMITED && tf == TRANSFER_FUNC_GAMMA_22)

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

427

if ((cs == COLOR_SPACE_SRGB_LIMITED) ||

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

428

(cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE) ||

sys/dev/pci/drm/i915/display/intel_overlay.c

261

u32 *cs;

sys/dev/pci/drm/i915/display/intel_overlay.c

269

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/display/intel_overlay.c

270

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/display/intel_overlay.c

272

return PTR_ERR(cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

280

*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;

sys/dev/pci/drm/i915/display/intel_overlay.c

281

*cs++ = overlay->flip_addr | OFC_UPDATE;

sys/dev/pci/drm/i915/display/intel_overlay.c

282

*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;

sys/dev/pci/drm/i915/display/intel_overlay.c

283

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/display/intel_overlay.c

284

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

327

u32 tmp, *cs;

sys/dev/pci/drm/i915/display/intel_overlay.c

343

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/display/intel_overlay.c

344

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/display/intel_overlay.c

346

return PTR_ERR(cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

349

*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;

sys/dev/pci/drm/i915/display/intel_overlay.c

350

*cs++ = flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

351

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

408

u32 *cs, flip_addr = overlay->flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

424

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/display/intel_overlay.c

425

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/display/intel_overlay.c

427

return PTR_ERR(cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

431

*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;

sys/dev/pci/drm/i915/display/intel_overlay.c

432

*cs++ = flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

433

*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;

sys/dev/pci/drm/i915/display/intel_overlay.c

436

*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;

sys/dev/pci/drm/i915/display/intel_overlay.c

437

*cs++ = flip_addr;

sys/dev/pci/drm/i915/display/intel_overlay.c

438

*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;

sys/dev/pci/drm/i915/display/intel_overlay.c

440

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

466

u32 *cs;

sys/dev/pci/drm/i915/display/intel_overlay.c

484

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/display/intel_overlay.c

485

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/display/intel_overlay.c

487

return PTR_ERR(cs);

sys/dev/pci/drm/i915/display/intel_overlay.c

490

*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;

sys/dev/pci/drm/i915/display/intel_overlay.c

491

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/display/intel_overlay.c

492

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2207

u32 *cs;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2215

cs = intel_ring_begin(rq, 4 * 2 + 2);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2216

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2217

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2219

*cs++ = MI_LOAD_REGISTER_IMM(4);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2221

*cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2222

*cs++ = 0;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2224

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2225

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

149

u32 cmd, *cs;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

151

cs = i915_gem_object_pin_map_unlocked(batch, I915_MAP_WC);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

152

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

153

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

163

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

164

*cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

165

*cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

190

*cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

192

*cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

193

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

194

*cs++ = t->height << 16 | t->width;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

195

*cs++ = lower_32_bits(i915_vma_offset(dst->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

196

*cs++ = upper_32_bits(i915_vma_offset(dst->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

197

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

198

*cs++ = src_pitch;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

199

*cs++ = lower_32_bits(i915_vma_offset(src->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

200

*cs++ = upper_32_bits(i915_vma_offset(src->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

203

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

204

*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

210

*cs++ = cmd;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

215

*cs++ = cmd;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

216

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

217

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

218

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

237

*cs++ = cmd;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

238

*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

239

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

240

*cs++ = t->height << 16 | t->width;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

241

*cs++ = lower_32_bits(i915_vma_offset(dst->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

243

*cs++ = upper_32_bits(i915_vma_offset(dst->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

244

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

245

*cs++ = src_pitch;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

246

*cs++ = lower_32_bits(i915_vma_offset(src->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

248

*cs++ = upper_32_bits(i915_vma_offset(src->vma));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

251

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

198

u32 *cs;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

216

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

217

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

218

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

223

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

224

*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

225

*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

226

*cs++ = v;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

228

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

229

*cs++ = 0;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

230

*cs++ = i915_ggtt_offset(vma) + offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

231

*cs++ = v;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

233

*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

234

*cs++ = i915_ggtt_offset(vma) + offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

235

*cs++ = v;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

236

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

238

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

104

*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

105

*cs++ = intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

108

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

109

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

112

*cs++ = MI_FLUSH;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

114

*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

115

*cs++ = intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

118

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

119

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

122

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

124

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

131

u32 *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

133

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

134

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

135

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

137

*cs++ = MI_FLUSH;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

138

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

139

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

144

static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

150

*cs++ = MI_FLUSH;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

153

*cs++ = MI_STORE_DWORD_INDEX;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

154

*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

155

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

159

*cs++ = MI_STORE_DWORD_INDEX;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

160

*cs++ = I915_GEM_HWS_SEQNO_ADDR;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

161

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

164

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

166

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

169

return cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

172

u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

174

return __gen2_emit_breadcrumb(rq, cs, 16, 8);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

177

u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

179

return __gen2_emit_breadcrumb(rq, cs, 8, 8);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

19

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

190

u32 *cs, cs_offset =

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

196

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

197

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

198

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

201

*cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

202

*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

203

*cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

204

*cs++ = cs_offset;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

205

*cs++ = 0xdeadbeef;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

206

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

207

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

213

cs = intel_ring_begin(rq, 6 + 2);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

214

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

215

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

222

*cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

223

*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

224

*cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

225

*cs++ = cs_offset;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

226

*cs++ = 4096;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

227

*cs++ = offset;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

229

*cs++ = MI_FLUSH;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

230

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

231

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

240

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

241

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

242

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

244

*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

245

*cs++ = offset;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

246

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

25

cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

255

u32 *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

26

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

260

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

261

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

262

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

264

*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

265

*cs++ = offset;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

266

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

27

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

276

u32 *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

282

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

283

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

284

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

286

*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

287

*cs++ = offset;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

288

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

29

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

31

*cs++ = MI_STORE_DWORD_INDEX;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

32

*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

33

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

34

*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

36

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

38

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

45

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

87

cs = intel_ring_begin(rq, i);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

88

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

89

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

91

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

18

u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

19

u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

130

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

131

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

132

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

134

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

135

*cs++ = flags;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

136

*cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

137

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

138

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

143

u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

146

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

147

*cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

148

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

149

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

151

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

152

*cs++ = PIPE_CONTROL_QW_WRITE;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

153

*cs++ = intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

156

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

159

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

160

*cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

165

*cs++ = i915_request_active_seqno(rq) |

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

167

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

169

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

170

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

172

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

175

return cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

180

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

182

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

183

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

184

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

204

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

205

*cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

206

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

207

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

209

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

234

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

240

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

241

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

242

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

244

cs = __gen6_emit_bb_start(cs, offset, security);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

245

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

256

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

262

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

263

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

264

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

266

cs = __gen6_emit_bb_start(cs, offset, security);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

267

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

274

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

276

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

277

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

278

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

280

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

281

*cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

282

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

283

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

284

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

294

u32 *cs, flags = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

340

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

341

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

342

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

344

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

345

*cs++ = flags;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

346

*cs++ = scratch_addr;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

347

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

348

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

353

u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

355

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

356

*cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

363

*cs++ = i915_request_active_seqno(rq);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

364

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

366

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

367

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

369

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

372

return cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

375

u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

380

*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

381

*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

382

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

384

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

386

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

389

return cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

393

u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

400

*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

402

*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

403

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

406

*cs++ = MI_STORE_DWORD_INDEX;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

407

*cs++ = I915_GEM_HWS_SEQNO_ADDR;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

408

*cs++ = rq->fence.seqno;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

411

*cs++ = MI_FLUSH_DW;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

412

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

413

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

415

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

416

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

418

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

421

return cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

60

u32 *cs;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

62

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

63

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

64

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

66

*cs++ = GFX_OP_PIPE_CONTROL(5);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

67

*cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

68

*cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

69

*cs++ = 0; /* low dword */

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

70

*cs++ = 0; /* high dword */

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

71

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

72

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

74

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

75

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

76

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

78

*cs++ = GFX_OP_PIPE_CONTROL(5);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

79

*cs++ = PIPE_CONTROL_QW_WRITE;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

80

*cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

81

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

82

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

83

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

84

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

94

u32 *cs, flags = 0;

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

19

u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

20

u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

23

u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

24

u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

102

static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

104

return (cs - bc->start) * sizeof(*bc->start) + bc->offset;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

148

u32 *cs = batch_alloc_items(state, 32, 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

149

u32 offset = batch_offset(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

155

*cs++ = SURFACE_2D << 29 |

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

159

*cs++ = batch_addr(state) + dst_offset;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

161

*cs++ = ((surface_h / 4 - 1) << 16) | (surface_w / 4 - 1);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

162

*cs++ = surface_w;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

163

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

164

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

165

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

168

*cs++ = SHADER_CHANNELS(4, 5, 6, 7);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

169

batch_advance(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

180

u32 *cs = batch_alloc_items(state, 32, 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

181

u32 offset = batch_offset(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

183

*cs++ = surface_start - state->offset;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

184

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

185

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

186

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

187

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

188

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

189

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

190

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

191

batch_advance(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

215

u32 *cs = batch_alloc_items(state, 32, 8 * count);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

216

u32 offset = batch_offset(state, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

218

*cs++ = kernel_offset;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

219

*cs++ = (1 << 7) | (1 << 13);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

220

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

221

*cs++ = (binding_table - state->offset) | 1;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

222

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

223

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

224

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

225

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

228

memset32(cs, 0x00, (count - 1) * 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

229

batch_advance(state, cs + (count - 1) * 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

238

u32 *cs = batch_alloc_items(batch, 0, 10);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

240

*cs++ = STATE_BASE_ADDRESS | (10 - 2);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

242

*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

244

*cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

246

*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

248

*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

250

*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

253

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

254

*cs++ = BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

255

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

256

*cs++ = BASE_ADDRESS_MODIFY;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

257

batch_advance(batch, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

267

u32 *cs = batch_alloc_items(batch, 32, 8);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

269

*cs++ = MEDIA_VFE_STATE | (8 - 2);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

272

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

275

*cs++ = threads << 16 | 1 << 8 | mode << 2;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

277

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

280

*cs++ = urb_size << 16 | curbe_size;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

283

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

284

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

285

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

286

batch_advance(batch, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

294

u32 *cs = batch_alloc_items(batch, 8, 4);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

296

*cs++ = MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

297

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

298

*cs++ = count * 8 * sizeof(*cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

304

*cs++ = interface_descriptor;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

305

batch_advance(batch, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

315

u32 *cs;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

317

cs = batch_alloc_items(batch, 8, pkt);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

319

*cs++ = MEDIA_OBJECT | (pkt - 2);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

322

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

325

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

326

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

329

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

330

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

333

*cs++ = y_offset << 16 | x_offset;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

334

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

335

*cs++ = GT3_INLINE_DATA_DELAYS;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

337

batch_advance(batch, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

342

u32 *cs = batch_alloc_items(batch, 0, 4);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

344

*cs++ = GFX_OP_PIPE_CONTROL(4);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

345

*cs++ = PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

349

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

350

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

352

batch_advance(batch, cs);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

357

u32 *cs = batch_alloc_items(batch, 0, 10);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

360

*cs++ = GFX_OP_PIPE_CONTROL(5);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

361

*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

363

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

364

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

365

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

367

*cs++ = GFX_OP_PIPE_CONTROL(5);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

368

*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

369

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

370

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

371

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

373

batch_advance(batch, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

103

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

104

*cs++ = LRC_PPHWSP_SCRATCH_ADDR;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

105

*cs++ = 0; /* upper addr */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

106

*cs++ = 0; /* value */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

107

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

115

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

128

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

129

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

130

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

132

cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

133

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

137

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

152

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

153

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

154

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

156

cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

157

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

16

u32 *cs, flags = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

199

u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

205

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

207

*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

208

*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

209

*cs++ = AUX_INV;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

211

*cs++ = MI_SEMAPHORE_WAIT_TOKEN |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

215

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

216

*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

217

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

218

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

220

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

228

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

231

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

232

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

233

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

234

cs = gen12_emit_pipe_control(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

238

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

256

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

300

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

301

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

302

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

304

cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

306

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

311

u32 *cs, count;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

340

cs = intel_ring_begin(rq, count);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

341

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

342

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

349

*cs++ = preparser_disable(true);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

351

cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

353

cs = gen12_emit_aux_table_inv(engine, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

355

*cs++ = preparser_disable(false);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

356

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

365

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

374

cs = intel_ring_begin(rq, cmd);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

375

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

376

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

379

*cs++ = preparser_disable(true);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

401

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

402

*cs++ = LRC_PPHWSP_SCRATCH_ADDR;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

403

*cs++ = 0; /* upper addr */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

404

*cs++ = 0; /* value */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

406

cs = gen12_emit_aux_table_inv(rq->engine, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

409

*cs++ = preparser_disable(false);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

411

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

436

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

442

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

443

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

444

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

446

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

447

*cs++ = hwsp_offset(rq);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

448

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

449

*cs++ = rq->fence.seqno - 1;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

468

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

469

*cs++ = MI_ARB_CHECK;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

471

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

474

rq->infix = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

488

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

492

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

493

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

494

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

496

*cs++ = MI_ARB_ON_OFF | arb;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

498

*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

501

*cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0));

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

502

*cs++ = wa_offset + DG2_PREDICATE_RESULT_WA;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

503

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

505

*cs++ = MI_BATCH_BUFFER_START_GEN8 |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

507

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

508

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

511

*cs++ = MI_BATCH_BUFFER_START_GEN8;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

512

*cs++ = wa_offset + DG2_PREDICATE_RESULT_BB;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

513

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

515

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

517

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

540

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

542

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

543

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

544

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

559

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

562

*cs++ = MI_BATCH_BUFFER_START_GEN8 |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

564

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

565

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

567

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

576

u32 *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

58

cs = intel_ring_begin(rq, len);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

581

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

582

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

583

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

585

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

587

*cs++ = MI_BATCH_BUFFER_START_GEN8 |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

589

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

59

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

590

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

592

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

593

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

595

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

60

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

613

static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

616

*cs++ = MI_ARB_CHECK;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

617

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

618

rq->wa_tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

623

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

626

static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

628

*cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

629

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

63

cs = gen8_emit_pipe_control(cs, 0, 0);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

633

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

634

*cs++ = preempt_address(rq->engine);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

635

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

636

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

638

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

642

gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

644

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

646

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

649

cs = emit_preempt_busywait(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

651

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

654

return gen8_emit_wa_tail(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

657

static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

659

return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

66

cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

662

u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

664

return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

667

u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

669

cs = gen8_emit_pipe_control(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

678

cs = gen8_emit_ggtt_write_rcs(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

684

return gen8_emit_fini_breadcrumb_tail(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

687

u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

689

cs = gen8_emit_pipe_control(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

69

cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

699

cs = gen8_emit_ggtt_write_rcs(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

705

return gen8_emit_fini_breadcrumb_tail(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

72

cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

727

static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

729

*cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

730

*cs++ = MI_SEMAPHORE_WAIT_TOKEN |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

734

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

735

*cs++ = preempt_address(rq->engine);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

736

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

737

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

739

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

74

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

755

static u32 *hold_switchout_emit_wa_busywait(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

759

*cs++ = MI_ATOMIC_INLINE | MI_ATOMIC_GLOBAL_GTT | MI_ATOMIC_CS_STALL |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

761

*cs++ = hold_switchout_semaphore_offset(rq);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

762

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

763

*cs++ = 1;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

770

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

772

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

776

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

777

*cs++ = hold_switchout_semaphore_offset(rq);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

778

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

780

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

784

gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

786

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

788

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

791

cs = gen12_emit_preempt_busywait(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

797

cs = hold_switchout_emit_wa_busywait(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

799

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

802

return gen8_emit_wa_tail(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

805

u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

808

cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

809

return gen12_emit_fini_breadcrumb_tail(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

81

u32 cmd, *cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

812

u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

83

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

830

cs = gen12_emit_pipe_control(cs, 0,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

84

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

842

cs = gen12_emit_pipe_control(cs, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

845

cs = gen12_emit_ggtt_write_rcs(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

85

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

852

return gen12_emit_fini_breadcrumb_tail(rq, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

105

gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

110

return __gen8_emit_write_rcs(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

118

__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

120

*cs++ = (MI_FLUSH_DW + 1) | flags;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

121

*cs++ = gtt_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

122

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

123

*cs++ = value;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

125

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

129

gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

136

return __gen8_emit_flush_dw(cs,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

43

u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

44

u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

46

u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

47

u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

48

u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

50

u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

79

__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

81

*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

82

*cs++ = flags1 | PIPE_CONTROL_QW_WRITE;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

83

*cs++ = offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

84

*cs++ = 0;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

85

*cs++ = value;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

86

*cs++ = 0; /* We're thrashing one extra dword. */

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

88

return cs;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

92

gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

97

return __gen8_emit_write_rcs(cs,

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

21

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

23

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

24

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

25

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

30

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

31

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

32

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

33

*cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

35

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1309

u32 cs[2048];

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1330

frame->ring.vaddr = frame->cs;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1331

frame->ring.size = sizeof(frame->cs);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1341

dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

548

u32 *cs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2719

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2730

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2731

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2732

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2734

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2735

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2736

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2748

cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2749

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2750

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2753

*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2758

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2759

*cs++ = upper_32_bits(pd_daddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2760

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2761

*cs++ = lower_32_bits(pd_daddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2763

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2764

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2766

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

380

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

413

cs = intel_ring_begin(rq, 2 * n_ptes + 2);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

414

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/intel_ggtt.c

416

i915_request_set_error_once(rq, PTR_ERR(cs));

sys/dev/pci/drm/i915/gt/intel_ggtt.c

421

*cs++ = MI_UPDATE_GTT | (2 * n_ptes);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

422

*cs++ = offset << 12;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

428

*cs++ = lower_32_bits(pte | addr);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

429

*cs++ = upper_32_bits(pte | addr);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

434

memset64((u64 *)cs, scratch_pte,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

436

cs += (n_ptes - count) * 2;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

439

memset64((u64 *)cs, pte, n_ptes);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

440

cs += n_ptes * 2;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

443

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

467

static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

469

*cs++ = MI_BATCH_BUFFER_START | flags;

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

470

*cs++ = addr;

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

472

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1051

static u32 *setup_predicate_disable_wa(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1054

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1055

*cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1056

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1057

*cs++ = 0; /* No predication */

sys/dev/pci/drm/i915/gt/intel_lrc.c

1060

*cs++ = MI_BATCH_BUFFER_END | BIT(15);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1061

*cs++ = MI_SET_PREDICATE | MI_SET_PREDICATE_DISABLE;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1064

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1065

*cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1066

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1067

*cs++ = 1; /* enable predication before the next BB */

sys/dev/pci/drm/i915/gt/intel_lrc.c

1069

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1070

GEM_BUG_ON(offset_in_page(cs) > DG2_PREDICATE_RESULT_WA);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1072

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1264

gen12_emit_timestamp_wa(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1266

*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |

sys/dev/pci/drm/i915/gt/intel_lrc.c

1269

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1270

*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +

sys/dev/pci/drm/i915/gt/intel_lrc.c

1272

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1274

*cs++ = MI_LOAD_REGISTER_REG |

sys/dev/pci/drm/i915/gt/intel_lrc.c

1277

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1278

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1280

*cs++ = MI_LOAD_REGISTER_REG |

sys/dev/pci/drm/i915/gt/intel_lrc.c

1283

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1284

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1286

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1290

gen12_emit_restore_scratch(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1294

*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |

sys/dev/pci/drm/i915/gt/intel_lrc.c

1297

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1298

*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +

sys/dev/pci/drm/i915/gt/intel_lrc.c

1300

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1302

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1306

gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1310

*cs++ = MI_LOAD_REGISTER_MEM_GEN8 |

sys/dev/pci/drm/i915/gt/intel_lrc.c

1313

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1314

*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +

sys/dev/pci/drm/i915/gt/intel_lrc.c

1316

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1318

*cs++ = MI_LOAD_REGISTER_REG |

sys/dev/pci/drm/i915/gt/intel_lrc.c

1321

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1322

*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1324

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1335

dg2_emit_draw_watermark_setting(u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1337

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1338

*cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1339

*cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1341

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1345

gen12_invalidate_state_cache(u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1347

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1348

*cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1349

*cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1350

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1354

gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1356

cs = gen12_emit_timestamp_wa(ce, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1357

cs = gen12_emit_cmd_buf_wa(ce, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1358

cs = gen12_emit_restore_scratch(ce, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1362

cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1364

cs = gen12_emit_aux_table_inv(ce->engine, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1368

cs = gen12_invalidate_state_cache(cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1374

cs = dg2_emit_draw_watermark_setting(cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1376

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1380

gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1382

cs = gen12_emit_timestamp_wa(ce, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1383

cs = gen12_emit_restore_scratch(ce, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1388

cs = gen8_emit_pipe_control(cs,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1392

return gen12_emit_aux_table_inv(ce->engine, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1395

static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1419

*cs++ = XY_FAST_COLOR_BLT_CMD | (16 - 2);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1420

*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1421

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1422

*cs++ = 4 << 16 | 1;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1423

*cs++ = lower_32_bits(i915_vma_offset(ce->vm->rsvd.vma));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1424

*cs++ = upper_32_bits(i915_vma_offset(ce->vm->rsvd.vma));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1425

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1426

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1427

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1428

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1429

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1430

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1431

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1432

*cs++ = 0x20004004;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1433

*cs++ = 0x10;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1434

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1436

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1440

xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1444

cs = xehp_emit_fastcolor_blt_wabb(ce, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1446

return cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1456

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1458

cs = emit(ce, start);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1461

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1463

GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1474

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1476

cs = emit(ce, start);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1477

GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1478

while ((unsigned long)cs % CACHELINE_BYTES)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1479

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1481

GEM_BUG_ON(cs - start > DG2_PREDICATE_RESULT_BB / sizeof(*start));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1486

(cs - start) * sizeof(*cs));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1563

u32 *(*fn)(const struct intel_context *ce, u32 *cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

336

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

338

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/intel_migrate.c

339

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_migrate.c

340

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

343

*cs++ = MI_ARB_ON_OFF;

sys/dev/pci/drm/i915/gt/intel_migrate.c

344

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_migrate.c

345

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

376

u32 *hdr, *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

403

cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS);

sys/dev/pci/drm/i915/gt/intel_migrate.c

404

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_migrate.c

405

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

410

hdr = cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

411

*cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */

sys/dev/pci/drm/i915/gt/intel_migrate.c

412

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_migrate.c

413

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_migrate.c

416

if (cs - hdr >= pkt) {

sys/dev/pci/drm/i915/gt/intel_migrate.c

419

*hdr += cs - hdr - 2;

sys/dev/pci/drm/i915/gt/intel_migrate.c

420

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_migrate.c

422

ring->emit = (void *)cs - ring->vaddr;

sys/dev/pci/drm/i915/gt/intel_migrate.c

423

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

426

cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS);

sys/dev/pci/drm/i915/gt/intel_migrate.c

427

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_migrate.c

428

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

443

hdr = cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

444

*cs++ = MI_STORE_DATA_IMM | REG_BIT(21);

sys/dev/pci/drm/i915/gt/intel_migrate.c

445

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_migrate.c

446

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/intel_migrate.c

451

*cs++ = lower_32_bits(encode | it->dma);

sys/dev/pci/drm/i915/gt/intel_migrate.c

452

*cs++ = upper_32_bits(encode | it->dma);

sys/dev/pci/drm/i915/gt/intel_migrate.c

468

*hdr += cs - hdr - 2;

sys/dev/pci/drm/i915/gt/intel_migrate.c

469

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_migrate.c

471

ring->emit = (void *)cs - ring->vaddr;

sys/dev/pci/drm/i915/gt/intel_migrate.c

472

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

537

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

539

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/gt/intel_migrate.c

540

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_migrate.c

541

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

546

cs = i915_flush_dw(cs, MI_FLUSH_DW_LLC | MI_FLUSH_DW_CCS);

sys/dev/pci/drm/i915/gt/intel_migrate.c

562

*cs++ = XY_CTRL_SURF_COPY_BLT |

sys/dev/pci/drm/i915/gt/intel_migrate.c

566

*cs++ = src_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

567

*cs++ = rq->engine->instance |

sys/dev/pci/drm/i915/gt/intel_migrate.c

569

*cs++ = dst_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

570

*cs++ = rq->engine->instance |

sys/dev/pci/drm/i915/gt/intel_migrate.c

573

cs = i915_flush_dw(cs, MI_FLUSH_DW_LLC | MI_FLUSH_DW_CCS);

sys/dev/pci/drm/i915/gt/intel_migrate.c

574

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_migrate.c

576

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

586

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

588

cs = intel_ring_begin(rq, ver >= 8 ? 10 : 6);

sys/dev/pci/drm/i915/gt/intel_migrate.c

589

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_migrate.c

590

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

593

*cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);

sys/dev/pci/drm/i915/gt/intel_migrate.c

594

*cs++ = BLT_DEPTH_32 | PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

595

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

596

*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

sys/dev/pci/drm/i915/gt/intel_migrate.c

597

*cs++ = dst_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

598

*cs++ = instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

599

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

600

*cs++ = PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

601

*cs++ = src_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

602

*cs++ = instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

604

*cs++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 - 2);

sys/dev/pci/drm/i915/gt/intel_migrate.c

605

*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

606

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

607

*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

sys/dev/pci/drm/i915/gt/intel_migrate.c

608

*cs++ = dst_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

609

*cs++ = instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

610

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

611

*cs++ = PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

612

*cs++ = src_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

613

*cs++ = instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

616

*cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);

sys/dev/pci/drm/i915/gt/intel_migrate.c

617

*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

618

*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

619

*cs++ = dst_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

620

*cs++ = PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

621

*cs++ = src_offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

624

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

924

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_migrate.c

935

cs = intel_ring_begin(rq, ring_sz);

sys/dev/pci/drm/i915/gt/intel_migrate.c

936

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_migrate.c

937

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_migrate.c

940

*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |

sys/dev/pci/drm/i915/gt/intel_migrate.c

942

*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |

sys/dev/pci/drm/i915/gt/intel_migrate.c

944

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

945

*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

sys/dev/pci/drm/i915/gt/intel_migrate.c

946

*cs++ = offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

947

*cs++ = rq->engine->instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

948

*cs++ = !is_lmem << XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT;

sys/dev/pci/drm/i915/gt/intel_migrate.c

950

*cs++ = value;

sys/dev/pci/drm/i915/gt/intel_migrate.c

951

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

952

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

953

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

955

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

956

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

958

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

959

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

960

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

962

*cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);

sys/dev/pci/drm/i915/gt/intel_migrate.c

963

*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

964

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

965

*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

sys/dev/pci/drm/i915/gt/intel_migrate.c

966

*cs++ = offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

967

*cs++ = rq->engine->instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

968

*cs++ = value;

sys/dev/pci/drm/i915/gt/intel_migrate.c

969

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_migrate.c

971

*cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);

sys/dev/pci/drm/i915/gt/intel_migrate.c

972

*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;

sys/dev/pci/drm/i915/gt/intel_migrate.c

973

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

974

*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;

sys/dev/pci/drm/i915/gt/intel_migrate.c

975

*cs++ = offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

976

*cs++ = value;

sys/dev/pci/drm/i915/gt/intel_migrate.c

979

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_ring.c

237

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ring.c

302

cs = ring->vaddr + ring->emit;

sys/dev/pci/drm/i915/gt/intel_ring.c

304

memset32(cs, POISON_INUSE, bytes / sizeof(*cs));

sys/dev/pci/drm/i915/gt/intel_ring.c

308

return cs;

sys/dev/pci/drm/i915/gt/intel_ring.h

40

static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)

sys/dev/pci/drm/i915/gt/intel_ring.h

50

GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

702

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

704

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

705

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

706

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

708

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

709

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

710

*cs++ = valid;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

712

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

713

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

714

*cs++ = pp_dir(vm);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

717

*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

718

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

719

*cs++ = intel_gt_scratch_offset(engine->gt,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

722

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

723

*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

724

*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

726

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

742

u32 *cs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

756

cs = intel_ring_begin(rq, len);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

757

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

758

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

762

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

766

*cs++ = MI_LOAD_REGISTER_IMM(num_engines);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

771

*cs++ = i915_mmio_reg_offset(

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

773

*cs++ = _MASKED_BIT_ENABLE(

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

784

*cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

800

*cs++ = MI_SET_CONTEXT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

801

*cs++ = i915_ggtt_offset(engine->kernel_context->state) |

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

806

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

807

*cs++ = MI_SET_CONTEXT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

808

*cs++ = i915_ggtt_offset(ce->state) | flags;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

813

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

820

*cs++ = MI_LOAD_REGISTER_IMM(num_engines);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

826

*cs++ = i915_mmio_reg_offset(last_reg);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

827

*cs++ = _MASKED_BIT_DISABLE(

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

832

*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

833

*cs++ = i915_mmio_reg_offset(last_reg);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

834

*cs++ = intel_gt_scratch_offset(engine->gt,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

836

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

838

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

840

*cs++ = MI_SUSPEND_FLUSH;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

843

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

851

u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

857

cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

858

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

859

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

866

*cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

868

*cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

869

*cs++ = remap_info[i];

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

871

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

872

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1010

cs = intel_ring_begin(rq, (wal->count * 2 + 6));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1012

cs = intel_ring_begin(rq, (wal->count * 2 + 2));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1014

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1015

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1023

*cs++ = MI_LOAD_REGISTER_IMM(wal->count);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1038

*cs++ = i915_mmio_reg_offset(wa->reg);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1039

*cs++ = val;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1041

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1046

*cs++ = CMD_3DSTATE_MESH_CONTROL;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1047

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1048

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1049

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1056

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2996

u32 srm, *cs;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3007

cs = intel_ring_begin(rq, 4 * count);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3008

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3009

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3017

*cs++ = srm;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3018

*cs++ = offset;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3019

*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3020

*cs++ = 0;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3022

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

998

u32 *cs;

sys/dev/pci/drm/i915/gt/mock_engine.c

231

static u32 *mock_emit_breadcrumb(struct i915_request *request, u32 *cs)

sys/dev/pci/drm/i915/gt/mock_engine.c

233

return cs;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

91

int (*fn)(struct intel_engine_cs *cs))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1057

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1070

cs = intel_ring_begin(rq, 14);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1071

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1072

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1076

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1077

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1079

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1083

*cs++ = idx;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1084

*cs++ = offset;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1085

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1087

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1088

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1089

*cs++ = offset + idx * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1090

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1092

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1093

*cs++ = offset;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1094

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1095

*cs++ = idx + 1;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1097

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1584

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1612

cs = intel_ring_begin(lo, 8);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1613

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1614

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1619

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1620

*cs++ = i915_ggtt_offset(vma);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1621

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1622

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1626

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1630

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1631

*cs++ = i915_ggtt_offset(vma);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1632

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1634

intel_ring_advance(lo, cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1661

cs = intel_ring_begin(hi, 4);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1662

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1663

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1669

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1670

*cs++ = i915_ggtt_offset(vma);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1671

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1672

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1674

intel_ring_advance(hi, cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2708

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2731

cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2732

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2733

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2738

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2740

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2743

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2744

*cs++ = lower_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2745

*cs++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2751

*cs++ = MI_STORE_DWORD_IMM_GEN4;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2752

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2753

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2754

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2757

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2980

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3008

cs = i915_gem_object_pin_map_unlocked(rq->batch->obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3009

if (!IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3010

*cs = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3013

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3053

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3073

cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3074

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3076

return ERR_CAST(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3080

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3081

*cs++ = CS_GPR(engine, 0);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3082

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3094

*cs++ = MI_MATH(4);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3095

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(i));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3096

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(0));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3097

*cs++ = MI_MATH_ADD;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3098

*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3100

addr = i915_vma_offset(result) + offset + i * sizeof(*cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3101

*cs++ = MI_STORE_REGISTER_MEM_GEN8;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3102

*cs++ = CS_GPR(engine, 2 * i);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3103

*cs++ = lower_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3104

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3106

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3109

*cs++ = i;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3110

*cs++ = lower_32_bits(i915_vma_offset(result));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3111

*cs++ = upper_32_bits(i915_vma_offset(result));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3114

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3216

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3222

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3223

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3225

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3228

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3229

*cs++ = i915_ggtt_offset(global);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3230

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3231

*cs++ = id;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3233

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3645

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3661

cs = i915_gem_object_pin_map_unlocked(smoke.batch, I915_MAP_WB);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3662

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3663

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3666

for (n = 0; n < PAGE_SIZE / sizeof(*cs) - 1; n++)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3667

cs[n] = MI_ARB_CHECK;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3668

cs[n] = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4198

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4237

cs = intel_ring_begin(rq, 8);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4238

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4240

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4244

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4245

*cs++ = CS_GPR(engine, n);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4246

*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4247

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4249

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4250

*cs++ = CS_GPR(engine, (n + 1) % NUM_GPR_DW);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4251

*cs++ = n + 1;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4253

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4254

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4266

cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4267

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4268

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4273

if (cs[n] != n) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4275

cs[n], n);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

714

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

743

cs = intel_ring_begin(rq, 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

744

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

746

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

751

*cs++ = 0xdeadbeef;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

752

*cs++ = 0xdeadbeef;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

754

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

755

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

822

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

824

cs = intel_ring_begin(rq, 10);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

825

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

826

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

828

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

830

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_execlists.c

834

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

835

*cs++ = i915_ggtt_offset(vma) + 4 * idx;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

836

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

839

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

840

*cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

841

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

842

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

844

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

845

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

846

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

847

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

850

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

852

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

896

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

902

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

903

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

905

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

908

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

909

*cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

910

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

911

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

913

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

100

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

102

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1038

*cs++ = MI_STORE_REGISTER_MEM_GEN8;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1039

*cs++ = hw[dw];

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1040

*cs++ = lower_32_bits(i915_vma_offset(scratch) + x);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1041

*cs++ = upper_32_bits(i915_vma_offset(scratch) + x);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1049

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1067

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1100

cs = intel_ring_begin(rq, 14);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1101

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1102

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1106

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1107

*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1108

*cs++ = lower_32_bits(i915_vma_offset(b_before));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1109

*cs++ = upper_32_bits(i915_vma_offset(b_before));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1111

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1112

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1116

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1117

*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1119

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1120

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1122

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1123

*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1124

*cs++ = lower_32_bits(i915_vma_offset(b_after));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1125

*cs++ = upper_32_bits(i915_vma_offset(b_after));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1127

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1147

u32 dw, *cs, *hw;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1154

cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1155

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1157

return ERR_CAST(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1196

*cs++ = MI_LOAD_REGISTER_IMM(len);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1198

*cs++ = hw[dw];

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1199

*cs++ = safe_poison(hw[dw] & get_lri_mask(ce->engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1207

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1221

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1238

cs = intel_ring_begin(rq, 8);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1239

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1240

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1244

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1245

*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1246

*cs++ = lower_32_bits(i915_vma_offset(batch));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1247

*cs++ = upper_32_bits(i915_vma_offset(batch));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1249

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1250

*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1252

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1253

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1255

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1592

u32 *cs, bool per_ctx)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1594

*cs++ = MI_STORE_REGISTER_MEM_GEN8 |

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1597

*cs++ = i915_mmio_reg_offset(RING_START(0));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1598

*cs++ = i915_ggtt_offset(ce->state) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1602

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1604

return cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1608

emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1610

return emit_wabb_ctx_canary(ce, cs, false);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1614

emit_per_ctx_bb_canary(const struct intel_context *ce, u32 *cs)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1616

return emit_wabb_ctx_canary(ce, cs, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1622

u32 *cs = context_wabb(ce, per_ctx);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1624

cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

415

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

437

cs = intel_ring_begin(rq, 4 * MAX_IDX);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

438

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

439

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

444

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

445

*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

446

*cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

447

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

451

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

452

*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

453

*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

454

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

471

cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

472

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

473

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

478

if (cs[n] != expected[n]) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

480

engine->name, n, cs[n], expected[n]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

536

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

543

cs = intel_ring_begin(rq, 2 * NUM_GPR_DW + 2);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

544

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

546

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

549

*cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

551

*cs++ = CS_GPR(ce->engine, n);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

552

*cs++ = STACK_MAGIC;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

554

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

556

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

571

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

579

cs = intel_ring_begin(rq, 6 + 4 * NUM_GPR_DW);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

580

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

582

return ERR_CAST(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

585

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

586

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

588

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_lrc.c

592

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

593

*cs++ = offset;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

594

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

597

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

598

*cs++ = CS_GPR(ce->engine, n);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

599

*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

600

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

622

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

669

cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

670

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

671

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

676

if (cs[n]) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

680

cs[n]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

744

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

751

cs = intel_ring_begin(rq, 10);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

752

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

753

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

757

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

758

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

760

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/selftest_lrc.c

764

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

765

*cs++ = offset;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

766

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

768

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

769

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

770

*cs++ = offset + idx * sizeof(u32);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

771

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

773

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

85

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

91

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

92

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

94

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

97

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

976

u32 dw, x, *cs, *hw;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

98

*cs++ = offset;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

983

cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

984

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

986

return ERR_CAST(cs);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

99

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

557

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

626

cs = intel_ring_begin(rq, sz);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

627

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_migrate.c

628

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

632

memset32(cs, MI_NOOP, sz);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

633

cs += sz;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

634

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

107

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

111

cs = intel_ring_begin(rq, 4 * count);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

112

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/selftest_mocs.c

113

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

116

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

117

*cs++ = addr;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

118

*cs++ = *offset;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

119

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

125

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

161

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

167

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

168

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_rc6.c

170

return cs;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

177

*cs++ = cmd;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

178

*cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

179

*cs++ = ce->timeline->hwsp_offset + 8;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

180

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

181

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

13

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

38

cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

39

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

41

return ERR_CAST(cs);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

45

*cs++ = MI_STORE_DWORD_IMM_GEN4;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

46

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

48

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

49

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

51

*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

53

*cs++ = i915_vma_offset(vma) + 4000;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

54

*cs++ = STACK_MAGIC;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

56

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_rps.c

101

*cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2);

sys/dev/pci/drm/i915/gt/selftest_rps.c

103

*cs++ = i915_mmio_reg_offset(CS_GPR(i));

sys/dev/pci/drm/i915/gt/selftest_rps.c

104

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_rps.c

105

*cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4;

sys/dev/pci/drm/i915/gt/selftest_rps.c

106

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_rps.c

109

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/selftest_rps.c

110

*cs++ = i915_mmio_reg_offset(CS_GPR(INC));

sys/dev/pci/drm/i915/gt/selftest_rps.c

111

*cs++ = 1;

sys/dev/pci/drm/i915/gt/selftest_rps.c

113

loop = cs - base;

sys/dev/pci/drm/i915/gt/selftest_rps.c

117

*cs++ = MI_MATH(4);

sys/dev/pci/drm/i915/gt/selftest_rps.c

118

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(COUNT));

sys/dev/pci/drm/i915/gt/selftest_rps.c

119

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(INC));

sys/dev/pci/drm/i915/gt/selftest_rps.c

120

*cs++ = MI_MATH_ADD;

sys/dev/pci/drm/i915/gt/selftest_rps.c

121

*cs++ = MI_MATH_STORE(MI_MATH_REG(COUNT), MI_MATH_REG_ACCU);

sys/dev/pci/drm/i915/gt/selftest_rps.c

124

*cs++ = MI_STORE_REGISTER_MEM_GEN8;

sys/dev/pci/drm/i915/gt/selftest_rps.c

125

*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));

sys/dev/pci/drm/i915/gt/selftest_rps.c

126

*cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));

sys/dev/pci/drm/i915/gt/selftest_rps.c

127

*cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));

sys/dev/pci/drm/i915/gt/selftest_rps.c

131

*cs++ = MI_BATCH_BUFFER_START_GEN8;

sys/dev/pci/drm/i915/gt/selftest_rps.c

132

*cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));

sys/dev/pci/drm/i915/gt/selftest_rps.c

133

*cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));

sys/dev/pci/drm/i915/gt/selftest_rps.c

134

GEM_BUG_ON(cs - base > end);

sys/dev/pci/drm/i915/gt/selftest_rps.c

72

u32 *base, *cs;

sys/dev/pci/drm/i915/gt/selftest_rps.c

99

cs = base;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

456

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

458

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

459

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

460

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

463

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

464

*cs++ = addr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

465

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

466

*cs++ = value;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

468

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

469

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

470

*cs++ = addr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

471

*cs++ = value;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

473

*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

474

*cs++ = addr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

475

*cs++ = value;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

476

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

479

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

783

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

785

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

786

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

787

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

789

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

790

*cs++ = *addr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

791

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

792

*cs++ = seqno;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

795

*cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

796

*cs++ = gpr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

797

*cs++ = hwsp;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

798

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

800

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

801

*cs++ = gpr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

802

*cs++ = *addr;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

803

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

806

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

100

cs = i915_gem_object_pin_map_unlocked(batch, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

101

*cs++ = MI_NOOP; /* for later termination */

sys/dev/pci/drm/i915/gt/selftest_tlb.c

110

*cs++ = MI_CONDITIONAL_BATCH_BUFFER_END | MI_DO_COMPARE | 2;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

111

*cs++ = 0; /* break if *addr == 0 */

sys/dev/pci/drm/i915/gt/selftest_tlb.c

112

*cs++ = lower_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

113

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

118

*cs++ = MI_BATCH_BUFFER_START | BIT(8) | 1;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

119

*cs++ = lower_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_tlb.c

120

*cs++ = upper_32_bits(i915_vma_offset(vma));

sys/dev/pci/drm/i915/gt/selftest_tlb.c

184

cs = page_mask_bits(batch->mm.mapping);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

185

*cs = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

48

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

106

u32 srm, *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

116

cs = i915_gem_object_pin_map_unlocked(result, I915_MAP_WB);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

117

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

118

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

121

memset(cs, 0xc5, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

149

cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

150

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

151

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

156

*cs++ = srm;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

157

*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

158

*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

159

*cs++ = 0;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

161

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

506

u32 *cs, *results;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

539

cs = NULL;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

548

cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

549

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

550

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

572

*cs++ = srm;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

573

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

574

*cs++ = lower_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

575

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

580

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

581

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

582

*cs++ = values[v];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

585

*cs++ = srm;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

586

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

587

*cs++ = lower_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

588

*cs++ = upper_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

593

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

594

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

595

*cs++ = ~values[v];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

598

*cs++ = srm;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

599

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

600

*cs++ = lower_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

601

*cs++ = upper_32_bits(addr + sizeof(u32) * idx);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

607

*cs++ = lrm;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

608

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

609

*cs++ = lower_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

610

*cs++ = upper_32_bits(addr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

612

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

617

cs = NULL;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

732

if (cs)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

848

u32 srm, *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

862

cs = intel_ring_begin(rq, 4 * engine->whitelist.count);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

863

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

864

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

875

*cs++ = srm;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

876

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

877

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

878

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

880

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

892

u32 *cs;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

898

cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

899

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

900

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

904

*cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

914

*cs++ = reg;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

915

*cs++ = 0xffffffff;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

917

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

266

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

268

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

269

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

270

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

272

*cs++ = GSC_FW_LOAD;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

273

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

274

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

275

*cs++ = (gsc->local->size / SZ_4K) | HECI1_FW_LIMIT_VALID;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

277

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

24

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

26

cs = intel_ring_begin(rq, 8);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

27

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

28

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

30

*cs++ = GSC_HECI_CMD_PKT;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

31

*cs++ = lower_32_bits(pkt->addr_in);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

32

*cs++ = upper_32_bits(pkt->addr_in);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

33

*cs++ = pkt->size_in;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

34

*cs++ = lower_32_bits(pkt->addr_out);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

35

*cs++ = upper_32_bits(pkt->addr_out);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

36

*cs++ = pkt->size_out;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

37

*cs++ = 0;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

39

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

92

u32 *cs, int timeout_ms);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4211

u32 *cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4214

u32 *cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5643

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5648

cs = intel_ring_begin(rq, 10 + 4 * ce->parallel.number_children);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5649

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5650

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5654

*cs++ = (MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5658

*cs++ = PARENT_GO_BB;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5659

*cs++ = get_children_join_addr(ce, i);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5660

*cs++ = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5664

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5665

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5668

cs = gen8_emit_ggtt_write(cs,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5674

*cs++ = MI_BATCH_BUFFER_START_GEN8 |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5676

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5677

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5678

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5680

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5691

u32 *cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5695

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5696

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5697

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5700

cs = gen8_emit_ggtt_write(cs,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5707

*cs++ = (MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5711

*cs++ = CHILD_GO_BB;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5712

*cs++ = get_children_go_addr(parent);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5713

*cs++ = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5716

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5719

*cs++ = MI_BATCH_BUFFER_START_GEN8 |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5721

*cs++ = lower_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5722

*cs++ = upper_32_bits(offset);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5724

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5731

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5740

*cs++ = (MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5744

*cs++ = PARENT_GO_FINI_BREADCRUMB;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5745

*cs++ = get_children_join_addr(ce, i);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5746

*cs++ = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5750

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5751

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5754

cs = gen8_emit_ggtt_write(cs,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5759

return cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5781

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5785

__maybe_unused u32 *start_fini_breadcrumb_cs = cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5794

memset(cs, 0, sizeof(u32) *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5796

cs += ce->engine->emit_fini_breadcrumb_dw - NON_SKIP_LEN;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5798

cs = __emit_fini_breadcrumb_parent_no_preempt_mid_batch(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5802

before_fini_breadcrumb_user_interrupt_cs = cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5803

cs = gen8_emit_ggtt_write(cs,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5809

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5810

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5814

cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5816

ce->engine->emit_fini_breadcrumb_dw != cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5818

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5820

return cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5825

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5833

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5834

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5837

cs = gen8_emit_ggtt_write(cs,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5844

*cs++ = (MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5848

*cs++ = CHILD_GO_FINI_BREADCRUMB;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5849

*cs++ = get_children_go_addr(parent);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5850

*cs++ = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5852

return cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5857

u32 *cs)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5861

__maybe_unused u32 *start_fini_breadcrumb_cs = cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5870

memset(cs, 0, sizeof(u32) *

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5872

cs += ce->engine->emit_fini_breadcrumb_dw - NON_SKIP_LEN;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5874

cs = __emit_fini_breadcrumb_child_no_preempt_mid_batch(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5878

before_fini_breadcrumb_user_interrupt_cs = cs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5879

cs = gen8_emit_ggtt_write(cs,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5885

*cs++ = MI_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5886

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5890

cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5892

ce->engine->emit_fini_breadcrumb_dw != cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5894

rq->tail = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5896

return cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

214

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

228

cs = intel_ring_begin(req, count * 2 + 2);

sys/dev/pci/drm/i915/gvt/mmio_context.c

229

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gvt/mmio_context.c

230

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

232

*cs++ = MI_LOAD_REGISTER_IMM(count);

sys/dev/pci/drm/i915/gvt/mmio_context.c

238

*cs++ = i915_mmio_reg_offset(mmio->reg);

sys/dev/pci/drm/i915/gvt/mmio_context.c

239

*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);

sys/dev/pci/drm/i915/gvt/mmio_context.c

241

*(cs-2), *(cs-1), vgpu->id, ring_id);

sys/dev/pci/drm/i915/gvt/mmio_context.c

244

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gvt/mmio_context.c

245

intel_ring_advance(req, cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

259

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

261

cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);

sys/dev/pci/drm/i915/gvt/mmio_context.c

262

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gvt/mmio_context.c

263

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

265

*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);

sys/dev/pci/drm/i915/gvt/mmio_context.c

268

*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));

sys/dev/pci/drm/i915/gvt/mmio_context.c

269

*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));

sys/dev/pci/drm/i915/gvt/mmio_context.c

271

*(cs-2), *(cs-1), vgpu->id, req->engine->id);

sys/dev/pci/drm/i915/gvt/mmio_context.c

275

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gvt/mmio_context.c

276

intel_ring_advance(req, cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

286

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

288

cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);

sys/dev/pci/drm/i915/gvt/mmio_context.c

289

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gvt/mmio_context.c

290

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

292

*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);

sys/dev/pci/drm/i915/gvt/mmio_context.c

295

*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));

sys/dev/pci/drm/i915/gvt/mmio_context.c

296

*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));

sys/dev/pci/drm/i915/gvt/mmio_context.c

298

*(cs-2), *(cs-1), vgpu->id, req->engine->id);

sys/dev/pci/drm/i915/gvt/mmio_context.c

302

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gvt/mmio_context.c

303

intel_ring_advance(req, cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

317

u32 *cs;

sys/dev/pci/drm/i915/gvt/mmio_context.c

319

cs = intel_ring_begin(req, 2);

sys/dev/pci/drm/i915/gvt/mmio_context.c

320

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gvt/mmio_context.c

321

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

323

*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;

sys/dev/pci/drm/i915/gvt/mmio_context.c

324

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gvt/mmio_context.c

325

intel_ring_advance(req, cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

344

cs = intel_ring_begin(req, 2);

sys/dev/pci/drm/i915/gvt/mmio_context.c

345

if (IS_ERR(cs))

sys/dev/pci/drm/i915/gvt/mmio_context.c

346

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gvt/mmio_context.c

348

*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

sys/dev/pci/drm/i915/gvt/mmio_context.c

349

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/gvt/mmio_context.c

350

intel_ring_advance(req, cs);

sys/dev/pci/drm/i915/gvt/scheduler.c

366

u32 *cs;

sys/dev/pci/drm/i915/gvt/scheduler.c

391

cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));

sys/dev/pci/drm/i915/gvt/scheduler.c

392

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/gvt/scheduler.c

395

return PTR_ERR(cs);

sys/dev/pci/drm/i915/gvt/scheduler.c

401

workload->shadow_ring_buffer_va = cs;

sys/dev/pci/drm/i915/gvt/scheduler.c

403

memcpy(cs, shadow_ring_buffer_va,

sys/dev/pci/drm/i915/gvt/scheduler.c

406

cs += workload->rb_len / sizeof(u32);

sys/dev/pci/drm/i915/gvt/scheduler.c

407

intel_ring_advance(workload->req, cs);

sys/dev/pci/drm/i915/i915_gpu_error.c

2095

struct intel_engine_coredump *cs;

sys/dev/pci/drm/i915/i915_gpu_error.c

2097

for (cs = gt->engine; cs; cs = cs->next) {

sys/dev/pci/drm/i915/i915_gpu_error.c

2098

if (cs->hung) {

sys/dev/pci/drm/i915/i915_gpu_error.c

2099

hung_classes |= BIT(cs->engine->uabi_class);

sys/dev/pci/drm/i915/i915_gpu_error.c

2101

first = cs;

sys/dev/pci/drm/i915/i915_perf.c

1337

u32 *cs, cmd;

sys/dev/pci/drm/i915/i915_perf.c

1343

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/i915_perf.c

1344

if (IS_ERR(cs))

sys/dev/pci/drm/i915/i915_perf.c

1345

return PTR_ERR(cs);

sys/dev/pci/drm/i915/i915_perf.c

1347

*cs++ = cmd;

sys/dev/pci/drm/i915/i915_perf.c

1348

*cs++ = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/i915_perf.c

1349

*cs++ = ggtt_offset;

sys/dev/pci/drm/i915/i915_perf.c

1350

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

1352

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/i915_perf.c

1933

static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,

sys/dev/pci/drm/i915/i915_perf.c

1946

*cs++ = cmd;

sys/dev/pci/drm/i915/i915_perf.c

1947

*cs++ = i915_mmio_reg_offset(reg) + 4 * d;

sys/dev/pci/drm/i915/i915_perf.c

1948

*cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;

sys/dev/pci/drm/i915/i915_perf.c

1949

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

1952

return cs;

sys/dev/pci/drm/i915/i915_perf.c

1966

u32 *batch, *ts0, *cs, *jump;

sys/dev/pci/drm/i915/i915_perf.c

2015

batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);

sys/dev/pci/drm/i915/i915_perf.c

2028

cs = save_restore_register(

sys/dev/pci/drm/i915/i915_perf.c

2029

stream, cs, true /* save */, CS_GPR(i),

sys/dev/pci/drm/i915/i915_perf.c

2031

cs = save_restore_register(

sys/dev/pci/drm/i915/i915_perf.c

2032

stream, cs, true /* save */, mi_predicate_result,

sys/dev/pci/drm/i915/i915_perf.c

2036

ts0 = cs;

sys/dev/pci/drm/i915/i915_perf.c

2043

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/i915_perf.c

2044

*cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;

sys/dev/pci/drm/i915/i915_perf.c

2045

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

2046

*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);

sys/dev/pci/drm/i915/i915_perf.c

2047

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));

sys/dev/pci/drm/i915/i915_perf.c

2048

*cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));

sys/dev/pci/drm/i915/i915_perf.c

2054

jump = cs;

sys/dev/pci/drm/i915/i915_perf.c

2061

*cs++ = MI_LOAD_REGISTER_IMM(1);

sys/dev/pci/drm/i915/i915_perf.c

2062

*cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;

sys/dev/pci/drm/i915/i915_perf.c

2063

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

2064

*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);

sys/dev/pci/drm/i915/i915_perf.c

2065

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));

sys/dev/pci/drm/i915/i915_perf.c

2066

*cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));

sys/dev/pci/drm/i915/i915_perf.c

2072

*cs++ = MI_MATH(5);

sys/dev/pci/drm/i915/i915_perf.c

2073

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));

sys/dev/pci/drm/i915/i915_perf.c

2074

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));

sys/dev/pci/drm/i915/i915_perf.c

2075

*cs++ = MI_MATH_SUB;

sys/dev/pci/drm/i915/i915_perf.c

2076

*cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);

sys/dev/pci/drm/i915/i915_perf.c

2077

*cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);

sys/dev/pci/drm/i915/i915_perf.c

2084

*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);

sys/dev/pci/drm/i915/i915_perf.c

2085

*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

sys/dev/pci/drm/i915/i915_perf.c

2086

*cs++ = i915_mmio_reg_offset(mi_predicate_result);

sys/dev/pci/drm/i915/i915_perf.c

2089

*cs++ = MI_SET_PREDICATE | 1;

sys/dev/pci/drm/i915/i915_perf.c

2092

*cs++ = (GRAPHICS_VER(i915) < 8 ?

sys/dev/pci/drm/i915/i915_perf.c

2096

*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;

sys/dev/pci/drm/i915/i915_perf.c

2097

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

2100

*cs++ = MI_SET_PREDICATE;

sys/dev/pci/drm/i915/i915_perf.c

2109

*cs++ = MI_LOAD_REGISTER_IMM(2);

sys/dev/pci/drm/i915/i915_perf.c

2110

*cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));

sys/dev/pci/drm/i915/i915_perf.c

2111

*cs++ = lower_32_bits(delay_ticks);

sys/dev/pci/drm/i915/i915_perf.c

2112

*cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;

sys/dev/pci/drm/i915/i915_perf.c

2113

*cs++ = upper_32_bits(delay_ticks);

sys/dev/pci/drm/i915/i915_perf.c

2115

*cs++ = MI_MATH(4);

sys/dev/pci/drm/i915/i915_perf.c

2116

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));

sys/dev/pci/drm/i915/i915_perf.c

2117

*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));

sys/dev/pci/drm/i915/i915_perf.c

2118

*cs++ = MI_MATH_ADD;

sys/dev/pci/drm/i915/i915_perf.c

2119

*cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);

sys/dev/pci/drm/i915/i915_perf.c

2121

*cs++ = MI_ARB_CHECK;

sys/dev/pci/drm/i915/i915_perf.c

2127

*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);

sys/dev/pci/drm/i915/i915_perf.c

2128

*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

sys/dev/pci/drm/i915/i915_perf.c

2129

*cs++ = i915_mmio_reg_offset(mi_predicate_result);

sys/dev/pci/drm/i915/i915_perf.c

2132

*cs++ = MI_SET_PREDICATE | 1;

sys/dev/pci/drm/i915/i915_perf.c

2135

*cs++ = (GRAPHICS_VER(i915) < 8 ?

sys/dev/pci/drm/i915/i915_perf.c

2139

*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;

sys/dev/pci/drm/i915/i915_perf.c

2140

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

2143

*cs++ = MI_SET_PREDICATE;

sys/dev/pci/drm/i915/i915_perf.c

2147

cs = save_restore_register(

sys/dev/pci/drm/i915/i915_perf.c

2148

stream, cs, false /* restore */, CS_GPR(i),

sys/dev/pci/drm/i915/i915_perf.c

2150

cs = save_restore_register(

sys/dev/pci/drm/i915/i915_perf.c

2151

stream, cs, false /* restore */, mi_predicate_result,

sys/dev/pci/drm/i915/i915_perf.c

2155

*cs++ = MI_BATCH_BUFFER_END;

sys/dev/pci/drm/i915/i915_perf.c

2157

GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));

sys/dev/pci/drm/i915/i915_perf.c

2180

static u32 *write_cs_mi_lri(u32 *cs,

sys/dev/pci/drm/i915/i915_perf.c

2192

*cs++ = MI_LOAD_REGISTER_IMM(n_lri);

sys/dev/pci/drm/i915/i915_perf.c

2194

*cs++ = i915_mmio_reg_offset(reg_data[i].addr);

sys/dev/pci/drm/i915/i915_perf.c

2195

*cs++ = reg_data[i].value;

sys/dev/pci/drm/i915/i915_perf.c

2198

return cs;

sys/dev/pci/drm/i915/i915_perf.c

2221

u32 *cs;

sys/dev/pci/drm/i915/i915_perf.c

2246

cs = i915_gem_object_pin_map(obj, I915_MAP_WB);

sys/dev/pci/drm/i915/i915_perf.c

2247

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/i915_perf.c

2248

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/i915_perf.c

2252

cs = write_cs_mi_lri(cs,

sys/dev/pci/drm/i915/i915_perf.c

2255

cs = write_cs_mi_lri(cs,

sys/dev/pci/drm/i915/i915_perf.c

2258

cs = write_cs_mi_lri(cs,

sys/dev/pci/drm/i915/i915_perf.c

2263

*cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?

sys/dev/pci/drm/i915/i915_perf.c

2266

*cs++ = i915_ggtt_offset(stream->noa_wait);

sys/dev/pci/drm/i915/i915_perf.c

2267

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

2509

u32 *cs;

sys/dev/pci/drm/i915/i915_perf.c

2511

cs = intel_ring_begin(rq, 4 * count);

sys/dev/pci/drm/i915/i915_perf.c

2512

if (IS_ERR(cs))

sys/dev/pci/drm/i915/i915_perf.c

2513

return PTR_ERR(cs);

sys/dev/pci/drm/i915/i915_perf.c

2517

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/i915_perf.c

2518

*cs++ = offset + flex->offset * sizeof(u32);

sys/dev/pci/drm/i915/i915_perf.c

2519

*cs++ = 0;

sys/dev/pci/drm/i915/i915_perf.c

2520

*cs++ = flex->value;

sys/dev/pci/drm/i915/i915_perf.c

2523

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/i915_perf.c

2533

u32 *cs;

sys/dev/pci/drm/i915/i915_perf.c

2537

cs = intel_ring_begin(rq, 2 * count + 2);

sys/dev/pci/drm/i915/i915_perf.c

2538

if (IS_ERR(cs))

sys/dev/pci/drm/i915/i915_perf.c

2539

return PTR_ERR(cs);

sys/dev/pci/drm/i915/i915_perf.c

2541

*cs++ = MI_LOAD_REGISTER_IMM(count);

sys/dev/pci/drm/i915/i915_perf.c

2543

*cs++ = i915_mmio_reg_offset(flex->reg);

sys/dev/pci/drm/i915/i915_perf.c

2544

*cs++ = flex->value;

sys/dev/pci/drm/i915/i915_perf.c

2546

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/i915_perf.c

2548

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/i915_request.c

1234

u32 *cs;

sys/dev/pci/drm/i915/i915_request.c

1248

cs = intel_ring_begin(to, len);

sys/dev/pci/drm/i915/i915_request.c

1249

if (IS_ERR(cs))

sys/dev/pci/drm/i915/i915_request.c

1250

return PTR_ERR(cs);

sys/dev/pci/drm/i915/i915_request.c

1260

*cs++ = (MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/i915_request.c

1265

*cs++ = seqno;

sys/dev/pci/drm/i915/i915_request.c

1266

*cs++ = hwsp_offset;

sys/dev/pci/drm/i915/i915_request.c

1267

*cs++ = 0;

sys/dev/pci/drm/i915/i915_request.c

1269

*cs++ = 0;

sys/dev/pci/drm/i915/i915_request.c

1270

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/i915_request.c

1273

intel_ring_advance(to, cs);

sys/dev/pci/drm/i915/i915_request.c

1874

u32 *cs;

sys/dev/pci/drm/i915/i915_request.c

1893

cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);

sys/dev/pci/drm/i915/i915_request.c

1894

GEM_BUG_ON(IS_ERR(cs));

sys/dev/pci/drm/i915/i915_request.c

1895

rq->postfix = intel_ring_offset(rq, cs);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

101

u32 *cs;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

117

cs = intel_ring_begin(rq, SESSION_TERMINATION_LEN(1) + WAIT_LEN);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

118

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

119

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

123

cs = pxp_emit_session_termination(cs, id);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

124

cs = pxp_emit_wait(cs);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

126

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

23

static u32 *pxp_emit_session_selection(u32 *cs, u32 idx)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

25

*cs++ = MFX_WAIT_PXP;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

28

*cs++ = MI_FLUSH_DW;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

29

*cs++ = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

30

*cs++ = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

33

*cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

35

*cs++ = MFX_WAIT_PXP;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

38

*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN |

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

40

*cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

41

*cs++ = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

43

*cs++ = MFX_WAIT_PXP;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

45

return cs;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

48

static u32 *pxp_emit_inline_termination(u32 *cs)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

51

*cs++ = CRYPTO_KEY_EXCHANGE;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

52

*cs++ = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

54

return cs;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

57

static u32 *pxp_emit_session_termination(u32 *cs, u32 idx)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

59

cs = pxp_emit_session_selection(cs, idx);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

60

cs = pxp_emit_inline_termination(cs);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

62

return cs;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

65

static u32 *pxp_emit_wait(u32 *cs)

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

68

*cs++ = MFX_WAIT_PXP;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

69

*cs++ = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

71

return cs;

sys/dev/pci/drm/i915/selftests/i915_perf.c

163

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_perf.c

166

cs = intel_ring_begin(rq, 6);

sys/dev/pci/drm/i915/selftests/i915_perf.c

167

if (IS_ERR(cs))

sys/dev/pci/drm/i915/selftests/i915_perf.c

168

return PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_perf.c

174

*cs++ = GFX_OP_PIPE_CONTROL(len);

sys/dev/pci/drm/i915/selftests/i915_perf.c

175

*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB |

sys/dev/pci/drm/i915/selftests/i915_perf.c

178

*cs++ = slot * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

179

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_perf.c

180

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_perf.c

181

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_perf.c

183

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_perf.c

295

u32 *cs, *store;

sys/dev/pci/drm/i915/selftests/i915_perf.c

335

cs = intel_ring_begin(rq, 2 * 32 + 2);

sys/dev/pci/drm/i915/selftests/i915_perf.c

336

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_perf.c

337

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_perf.c

342

*cs++ = MI_LOAD_REGISTER_IMM(32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

344

*cs++ = gpr0 + i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

345

*cs++ = STACK_MAGIC;

sys/dev/pci/drm/i915/selftests/i915_perf.c

347

*cs++ = MI_NOOP;

sys/dev/pci/drm/i915/selftests/i915_perf.c

348

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_perf.c

364

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/selftests/i915_perf.c

365

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_perf.c

366

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_perf.c

376

*cs++ = cmd;

sys/dev/pci/drm/i915/selftests/i915_perf.c

377

*cs++ = gpr0 + i * sizeof(u32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

378

*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +

sys/dev/pci/drm/i915/selftests/i915_perf.c

381

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_perf.c

382

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

1959

static u32 *emit_timestamp_store(u32 *cs, struct intel_context *ce, u32 offset)

sys/dev/pci/drm/i915/selftests/i915_request.c

1961

*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;

sys/dev/pci/drm/i915/selftests/i915_request.c

1962

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));

sys/dev/pci/drm/i915/selftests/i915_request.c

1963

*cs++ = offset;

sys/dev/pci/drm/i915/selftests/i915_request.c

1964

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_request.c

1966

return cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

1969

static u32 *emit_store_dw(u32 *cs, u32 offset, u32 value)

sys/dev/pci/drm/i915/selftests/i915_request.c

1971

*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

sys/dev/pci/drm/i915/selftests/i915_request.c

1972

*cs++ = offset;

sys/dev/pci/drm/i915/selftests/i915_request.c

1973

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_request.c

1974

*cs++ = value;

sys/dev/pci/drm/i915/selftests/i915_request.c

1976

return cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

1979

static u32 *emit_semaphore_poll(u32 *cs, u32 mode, u32 value, u32 offset)

sys/dev/pci/drm/i915/selftests/i915_request.c

1981

*cs++ = MI_SEMAPHORE_WAIT |

sys/dev/pci/drm/i915/selftests/i915_request.c

1985

*cs++ = value;

sys/dev/pci/drm/i915/selftests/i915_request.c

1986

*cs++ = offset;

sys/dev/pci/drm/i915/selftests/i915_request.c

1987

*cs++ = 0;

sys/dev/pci/drm/i915/selftests/i915_request.c

1989

return cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

1992

static u32 *emit_semaphore_poll_until(u32 *cs, u32 offset, u32 value)

sys/dev/pci/drm/i915/selftests/i915_request.c

1994

return emit_semaphore_poll(cs, MI_SEMAPHORE_SAD_EQ_SDD, value, offset);

sys/dev/pci/drm/i915/selftests/i915_request.c

2020

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2041

cs = intel_ring_begin(rq, 4 + 12 * ARRAY_SIZE(elapsed));

sys/dev/pci/drm/i915/selftests/i915_request.c

2042

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2044

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2048

cs = emit_store_dw(cs, offset, 0);

sys/dev/pci/drm/i915/selftests/i915_request.c

2050

cs = emit_semaphore_poll_until(cs, offset, i);

sys/dev/pci/drm/i915/selftests/i915_request.c

2051

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2052

cs = emit_store_dw(cs, offset, 0);

sys/dev/pci/drm/i915/selftests/i915_request.c

2055

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2094

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2122

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/selftests/i915_request.c

2123

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2125

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2129

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2131

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2165

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2190

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/selftests/i915_request.c

2191

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2193

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2197

cs = emit_store_dw(cs, offset + i * sizeof(u32), -1);

sys/dev/pci/drm/i915/selftests/i915_request.c

2198

cs = emit_semaphore_poll_until(cs, offset, i);

sys/dev/pci/drm/i915/selftests/i915_request.c

2199

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2201

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2243

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2249

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/selftests/i915_request.c

2250

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2252

return PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2255

cs = emit_semaphore_poll(cs, mode, value, offset);

sys/dev/pci/drm/i915/selftests/i915_request.c

2257

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2298

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2314

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/selftests/i915_request.c

2315

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2317

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2321

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2323

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2361

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2404

cs = intel_ring_begin(rq, 4);

sys/dev/pci/drm/i915/selftests/i915_request.c

2405

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2407

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2411

cs = emit_timestamp_store(cs, ce, addr);

sys/dev/pci/drm/i915/selftests/i915_request.c

2414

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2453

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2486

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/selftests/i915_request.c

2487

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2489

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2493

cs = emit_store_dw(cs, addr, -1);

sys/dev/pci/drm/i915/selftests/i915_request.c

2494

cs = emit_semaphore_poll_until(cs, offset, i);

sys/dev/pci/drm/i915/selftests/i915_request.c

2495

cs = emit_timestamp_store(cs, ce, addr + sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2497

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2511

cs = intel_ring_begin(rq, 8);

sys/dev/pci/drm/i915/selftests/i915_request.c

2512

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2514

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2518

cs = emit_timestamp_store(cs, ce, addr);

sys/dev/pci/drm/i915/selftests/i915_request.c

2519

cs = emit_store_dw(cs, offset, i);

sys/dev/pci/drm/i915/selftests/i915_request.c

2521

intel_ring_advance(rq, cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2573

u32 *cs;

sys/dev/pci/drm/i915/selftests/i915_request.c

2598

cs = intel_ring_begin(rq, 12);

sys/dev/pci/drm/i915/selftests/i915_request.c

2599

if (IS_ERR(cs)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2601

err = PTR_ERR(cs);

sys/dev/pci/drm/i915/selftests/i915_request.c

2605

cs = emit_store_dw(cs, offset + i * sizeof(u32), -1);

sys/dev/pci/drm/i915/selftests/i915_request.c

2606

cs = emit_semaphore_poll_until(cs, offset, i);

sys/dev/pci/drm/i915/selftests/i915_request.c

2607

cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));

sys/dev/pci/drm/i915/selftests/i915_request.c

2609

intel_ring_advance(rq, cs);

sys/dev/pci/drm/include/drm/drm_writeback.h

41

drm_writeback_set_fb(struct drm_connector_state *cs, struct drm_framebuffer *fb)

sys/dev/pci/drm/radeon/radeon_cs.c

271

struct drm_radeon_cs *cs = data;

sys/dev/pci/drm/radeon/radeon_cs.c

281

if (!cs->num_chunks) {

sys/dev/pci/drm/radeon/radeon_cs.c

293

p->chunks_array = kvmalloc_array(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);

sys/dev/pci/drm/radeon/radeon_cs.c

297

chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);

sys/dev/pci/drm/radeon/radeon_cs.c

299

sizeof(uint64_t)*cs->num_chunks)) {

sys/dev/pci/drm/radeon/radeon_cs.c

303

p->nchunks = cs->num_chunks;

sys/dev/pci/envy.c

372

int clk, dout, csmask, cs;

sys/dev/pci/envy.c

381

cs = dev ? 0x40 : 0x80;

sys/dev/pci/envy.c

386

cs = dev << 4;

sys/dev/pci/envy.c

391

reg |= cs;

sys/dev/pci/if_iwm.c

605

dlen < sizeof(l->size) + l->size * sizeof(*l->cs))

sys/dev/pci/if_iwmreg.h

1022

struct iwm_fw_cipher_scheme cs[];

sys/dev/pci/if_iwx.c

580

dlen < sizeof(l->size) + l->size * sizeof(*l->cs))

sys/dev/pci/if_iwxreg.h

1544

struct iwx_fw_cipher_scheme cs[];

sys/dev/sun/z8530ms.c

201

struct zs_chanstate *cs;

sys/dev/sun/z8530ms.c

206

cs = zsc->zsc_cs[channel];

sys/dev/sun/z8530ms.c

207

cs->cs_private = sc;

sys/dev/sun/z8530ms.c

208

cs->cs_ops = &zsops_ms;

sys/dev/sun/z8530ms.c

209

sc->sc_cs = cs;

sys/dev/sun/z8530ms.c

213

zs_write_reg(cs, 9, channel == 0 ? ZSWR9_A_RESET : ZSWR9_B_RESET);

sys/dev/sun/z8530ms.c

215

CLR(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_SIE | ZSWR1_TIE);

sys/dev/sun/z8530ms.c

218

CLR(cs->cs_preg[4], ZSWR4_SBMASK | ZSWR4_PARMASK);

sys/dev/sun/z8530ms.c

219

SET(cs->cs_preg[4], ZSWR4_TWOSB);

sys/dev/sun/z8530ms.c

220

(void)zs_set_speed(cs, INIT_SPEED);

sys/dev/sun/z8530ms.c

221

zs_loadchannelregs(cs);

sys/dev/sun/z8530ms.c

237

struct zs_chanstate *cs = sc->sc_cs;

sys/dev/sun/z8530ms.c

242

CLR(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_SIE);

sys/dev/sun/z8530ms.c

243

zs_loadchannelregs(cs);

sys/dev/sun/z8530ms.c

251

struct zs_chanstate *cs = sc->sc_cs;

sys/dev/sun/z8530ms.c

256

SET(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_SIE);

sys/dev/sun/z8530ms.c

257

zs_loadchannelregs(cs);

sys/dev/sun/z8530ms.c

268

zsms_rxint(struct zs_chanstate *cs)

sys/dev/sun/z8530ms.c

270

struct zsms_softc *sc = cs->cs_private;

sys/dev/sun/z8530ms.c

281

rr1 = zs_read_reg(cs, 1);

sys/dev/sun/z8530ms.c

282

c = zs_read_data(cs);

sys/dev/sun/z8530ms.c

290

zs_write_csr(cs, ZSWR0_RESET_ERRORS);

sys/dev/sun/z8530ms.c

307

rr0 = zs_read_csr(cs);

sys/dev/sun/z8530ms.c

315

cs->cs_softreq = 1;

sys/dev/sun/z8530ms.c

319

zsms_txint(struct zs_chanstate *cs)

sys/dev/sun/z8530ms.c

326

zs_write_csr(cs, ZSWR0_RESET_TXINT);

sys/dev/sun/z8530ms.c

329

CLR(cs->cs_preg[1], ZSWR1_TIE);

sys/dev/sun/z8530ms.c

330

zs_loadchannelregs(cs);

sys/dev/sun/z8530ms.c

334

zsms_stint(struct zs_chanstate *cs, int force)

sys/dev/sun/z8530ms.c

336

struct zsms_softc *sc = cs->cs_private;

sys/dev/sun/z8530ms.c

339

rr0 = zs_read_csr(cs);

sys/dev/sun/z8530ms.c

340

zs_write_csr(cs, ZSWR0_RESET_STATUS);

sys/dev/sun/z8530ms.c

354

cs->cs_softreq = 1;

sys/dev/sun/z8530ms.c

363

delta = rr0 ^ cs->cs_rr0;

sys/dev/sun/z8530ms.c

365

delta = cs->cs_rr0_mask;

sys/dev/sun/z8530ms.c

366

cs->cs_rr0 = rr0;

sys/dev/sun/z8530ms.c

368

if (ISSET(delta, cs->cs_rr0_mask)) {

sys/dev/sun/z8530ms.c

369

SET(cs->cs_rr0_delta, delta);

sys/dev/sun/z8530ms.c

372

cs->cs_softreq = 1;

sys/dev/sun/z8530ms.c

377

zsms_softint(struct zs_chanstate *cs)

sys/dev/sun/z8530ms.c

384

sc = cs->cs_private;

sys/dev/sun/z8530ms.c

429

cs->cs_rr0_delta = 0;

sys/dev/sun/z8530ms.c

442

struct zs_chanstate *cs = sc->sc_cs;

sys/dev/sun/z8530ms.c

452

rr0 = zs_read_csr(cs);

sys/dev/sun/z8530ms.c

455

(void)zs_read_data(cs);

sys/dev/sun/z8530ms.c

458

(void)zs_set_speed(cs, sc->sc_base.sc_bps);

sys/dev/sun/z8530ms.c

459

zs_loadchannelregs(cs);

sys/dev/sun/z8530ms.c

460

zsms_stint(cs, 1);

sys/dev/tc/zs_ioasic.c

228

struct zs_chanstate *cs;

sys/dev/tc/zs_ioasic.c

245

cs = &zs_ioasic_conschanstate_store;

sys/dev/tc/zs_ioasic.c

248

cs = malloc(sizeof(struct zs_chanstate),

sys/dev/tc/zs_ioasic.c

251

cs->cs_reg_csr = (volatile void *)&zc->zc_csr;

sys/dev/tc/zs_ioasic.c

253

memcpy(cs->cs_creg, zs_ioasic_init_reg, 16);

sys/dev/tc/zs_ioasic.c

254

memcpy(cs->cs_preg, zs_ioasic_init_reg, 16);

sys/dev/tc/zs_ioasic.c

256

cs->cs_defcflag = zs_def_cflag;

sys/dev/tc/zs_ioasic.c

257

cs->cs_defspeed = 9600; /* XXX */

sys/dev/tc/zs_ioasic.c

258

(void)zs_set_modes(cs, cs->cs_defcflag);

sys/dev/tc/zs_ioasic.c

261

zs->zsc_cs[channel] = cs;

sys/dev/tc/zs_ioasic.c

263

cs->cs_channel = channel;

sys/dev/tc/zs_ioasic.c

264

cs->cs_ops = &zsops_null;

sys/dev/tc/zs_ioasic.c

265

cs->cs_brg_clk = PCLK / 16;

sys/dev/tc/zs_ioasic.c

274

cs->cs_creg[15] |= ZSWR15_DCD_IE;

sys/dev/tc/zs_ioasic.c

275

cs->cs_preg[15] |= ZSWR15_DCD_IE;

sys/dev/tc/zs_ioasic.c

281

cs->cs_private = (void *)zflg;

sys/dev/tc/zs_ioasic.c

289

zs_write_reg(cs, 9, 0);

sys/dev/tc/zs_ioasic.c

298

cs->cs_ctl_chan = zs->zsc_cs[0];

sys/dev/tc/zs_ioasic.c

300

cs->cs_ctl_chan = NULL;

sys/dev/tc/zs_ioasic.c

330

zs_write_reg(cs, 9, reset);

sys/dev/tc/zs_ioasic.c

436

zs_set_speed(struct zs_chanstate *cs, int bps)

sys/dev/tc/zs_ioasic.c

444

if (cs->cs_brg_clk == 0)

sys/dev/tc/zs_ioasic.c

448

tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);

sys/dev/tc/zs_ioasic.c

453

real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);

sys/dev/tc/zs_ioasic.c

461

cs->cs_preg[12] = tconst;

sys/dev/tc/zs_ioasic.c

462

cs->cs_preg[13] = tconst >> 8;

sys/dev/tc/zs_ioasic.c

469

zs_set_modes(struct zs_chanstate *cs, int cflag)

sys/dev/tc/zs_ioasic.c

471

u_long privflags = (u_long)cs->cs_private;

sys/dev/tc/zs_ioasic.c

482

cs->cs_rr0_pps = 0;

sys/dev/tc/zs_ioasic.c

484

cs->cs_rr0_dcd = 0;

sys/dev/tc/zs_ioasic.c

486

cs->cs_rr0_pps = ZSRR0_DCD;

sys/dev/tc/zs_ioasic.c

488

cs->cs_rr0_dcd = ZSRR0_DCD;

sys/dev/tc/zs_ioasic.c

490

cs->cs_wr5_dtr = ZSWR5_DTR;

sys/dev/tc/zs_ioasic.c

491

cs->cs_wr5_rts = ZSWR5_RTS;

sys/dev/tc/zs_ioasic.c

492

cs->cs_rr0_cts = ZSRR0_CTS;

sys/dev/tc/zs_ioasic.c

495

cs->cs_wr5_dtr = 0;

sys/dev/tc/zs_ioasic.c

496

cs->cs_wr5_rts = ZSWR5_DTR;

sys/dev/tc/zs_ioasic.c

497

cs->cs_rr0_cts = ZSRR0_CTS;

sys/dev/tc/zs_ioasic.c

500

cs->cs_wr5_dtr = 0;

sys/dev/tc/zs_ioasic.c

501

cs->cs_wr5_rts = ZSWR5_DTR;

sys/dev/tc/zs_ioasic.c

502

cs->cs_rr0_cts = ZSRR0_DCD;

sys/dev/tc/zs_ioasic.c

504

cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;

sys/dev/tc/zs_ioasic.c

505

cs->cs_wr5_rts = 0;

sys/dev/tc/zs_ioasic.c

506

cs->cs_rr0_cts = 0;

sys/dev/tc/zs_ioasic.c

510

cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD);

sys/dev/tc/zs_ioasic.c

511

cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD);

sys/dev/tc/zs_ioasic.c

514

cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR);

sys/dev/tc/zs_ioasic.c

515

cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR);

sys/dev/tc/zs_ioasic.c

532

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/dev/tc/zs_ioasic.c

534

volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;

sys/dev/tc/zs_ioasic.c

547

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/dev/tc/zs_ioasic.c

549

volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;

sys/dev/tc/zs_ioasic.c

560

zs_read_csr(struct zs_chanstate *cs)

sys/dev/tc/zs_ioasic.c

562

volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;

sys/dev/tc/zs_ioasic.c

572

zs_write_csr(struct zs_chanstate *cs, uint8_t val)

sys/dev/tc/zs_ioasic.c

574

volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;

sys/dev/tc/zs_ioasic.c

582

zs_read_data(struct zs_chanstate *cs)

sys/dev/tc/zs_ioasic.c

584

volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;

sys/dev/tc/zs_ioasic.c

594

zs_write_data(struct zs_chanstate *cs, uint8_t val)

sys/dev/tc/zs_ioasic.c

596

volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;

sys/dev/tc/zs_ioasic.c

611

zs_abort(struct zs_chanstate *cs)

sys/dev/tc/zs_ioasic.c

618

rr0 = zs_read_csr(cs);

sys/dev/tc/zs_ioasic.c

632

zs_getc(struct zs_chanstate *cs)

sys/dev/tc/zs_ioasic.c

640

rr0 = zs_read_csr(cs);

sys/dev/tc/zs_ioasic.c

643

c = zs_read_data(cs);

sys/dev/tc/zs_ioasic.c

657

zs_putc(struct zs_chanstate *cs, int c)

sys/dev/tc/zs_ioasic.c

665

rr0 = zs_read_csr(cs);

sys/dev/tc/zs_ioasic.c

668

zs_write_data(cs, c);

sys/dev/tc/zs_ioasic.c

672

rr0 = zs_read_csr(cs);

sys/dev/tc/zs_ioasic.c

687

struct zs_chanstate *cs;

sys/dev/tc/zs_ioasic.c

702

cs = &zs_ioasic_conschanstate_store;

sys/dev/tc/zs_ioasic.c

714

cs->cs_reg_csr = (volatile void *)&zc->zc_csr;

sys/dev/tc/zs_ioasic.c

716

cs->cs_channel = channel;

sys/dev/tc/zs_ioasic.c

717

cs->cs_ops = &zsops_null;

sys/dev/tc/zs_ioasic.c

718

cs->cs_brg_clk = PCLK / 16;

sys/dev/tc/zs_ioasic.c

721

memcpy(cs->cs_preg, zs_ioasic_init_reg, 16);

sys/dev/tc/zs_ioasic.c

736

cs->cs_private = (void *)zflg;

sys/dev/tc/zs_ioasic.c

739

zs_write_reg(cs, 9, 0);

sys/dev/tc/zs_ioasic.c

742

zs_write_reg(cs, 9, ZSWR9_HARD_RESET);

sys/dev/tc/zs_ioasic.c

745

zs_loadchannelregs(cs);

sys/dev/tc/zs_ioasic.c

755

struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;

sys/dev/tc/zs_ioasic.c

758

cs->cs_defspeed = 9600;

sys/dev/tc/zs_ioasic.c

759

cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;

sys/dev/tc/zs_ioasic.c

777

struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;

sys/dev/tc/zs_ioasic.c

780

cs->cs_defspeed = 4800;

sys/dev/tc/zs_ioasic.c

781

cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;

sys/dev/tc/zs_ioasic.c

782

return (zskbd_cnattach(cs));

sys/dev/usb/uticom.c

840

uint8_t cs = 0, *buffer;

sys/dev/usb/uticom.c

865

cs = (uint8_t)(cs + buffer[pos]);

sys/dev/usb/uticom.c

870

header->checkSum = cs;

sys/dev/wscons/wsmouse.c

1259

int *cs = mc + m; /* the column set */

sys/dev/wscons/wsmouse.c

1260

int *c2r = cs + n; /* column-to-row assignments in cs */

sys/dev/wscons/wsmouse.c

1280

for (p = mc; p < cs; *p++ = col) {}

sys/dev/wscons/wsmouse.c

1282

cs[k++] = j;

sys/dev/wscons/wsmouse.c

1303

cd[cs[i]] += delta;

sys/dev/wscons/wsmouse.c

1304

red[c2r[cs[i]]] -= delta;

sys/dev/x86emu/x86emu.c

3798

uint16_t cs, ip;

sys/dev/x86emu/x86emu.c

3801

cs = fetch_word_imm(emu);

sys/dev/x86emu/x86emu.c

3803

emu->x86.R_CS = cs;

sys/kern/kern_sched.c

763

cpuset_add(struct cpuset *cs, struct cpu_info *ci)

sys/kern/kern_sched.c

766

atomic_setbits_int(&cs->cs_set[num/32], (1U << (num % 32)));

sys/kern/kern_sched.c

770

cpuset_del(struct cpuset *cs, struct cpu_info *ci)

sys/kern/kern_sched.c

773

atomic_clearbits_int(&cs->cs_set[num/32], (1U << (num % 32)));

sys/kern/kern_sched.c

777

cpuset_isset(struct cpuset *cs, struct cpu_info *ci)

sys/kern/kern_sched.c

780

return (cs->cs_set[num/32] & (1U << (num % 32)));

sys/kern/kern_sched.c

790

cpuset_first(struct cpuset *cs)

sys/kern/kern_sched.c

795

if (cs->cs_set[i])

sys/kern/kern_sched.c

796

return (cpuset_infos[i * 32 + ffs(cs->cs_set[i]) - 1]);

sys/kern/kern_sched.c

820

cpuset_cardinality(struct cpuset *cs)

sys/kern/kern_sched.c

827

for (n = cs->cs_set[i]; n != 0; n &= n - 1)

sys/kern/kern_sysctl.c

2868

struct cpustats cs;

sys/kern/kern_sysctl.c

2884

memset(&cs, 0, sizeof cs);

sys/kern/kern_sysctl.c

2885

sysctl_ci_cp_time(ci, cs.cs_time);

sys/kern/kern_sysctl.c

2886

cs.cs_flags = 0;

sys/kern/kern_sysctl.c

2888

cs.cs_flags |= CPUSTATS_ONLINE;

sys/kern/kern_sysctl.c

2890

return (sysctl_rdstruct(oldp, oldlenp, newp, &cs, sizeof(cs)));

sys/kern/tty_endrun.c

252

char *fld[NUMFLDS], *cs;

sys/kern/tty_endrun.c

257

for (cs = NULL, n = 0; n < np->pos && cs == NULL; n++) {

sys/kern/tty_endrun.c

261

cs = &np->cbuf[n + 1];

sys/kern/tty_msts.c

211

char *fld[MAXFLDS], *cs;

sys/kern/tty_msts.c

215

for (cs = NULL, n = 0; n < np->pos && cs == NULL; n++) {

sys/kern/tty_msts.c

219

cs = &np->cbuf[n + 1];

sys/kern/tty_nmea.c

259

char *fld[MAXFLDS], *cs;

sys/kern/tty_nmea.c

263

for (cs = NULL, n = 0; n < np->pos && cs == NULL; n++) {

sys/kern/tty_nmea.c

267

cs = &np->cbuf[n + 1];

sys/kern/tty_nmea.c

307

if (cs != NULL) {

sys/kern/tty_nmea.c

309

while (*cs) {

sys/kern/tty_nmea.c

310

if ((*cs >= '0' && *cs <= '9') ||

sys/kern/tty_nmea.c

311

(*cs >= 'A' && *cs <= 'F')) {

sys/kern/tty_nmea.c

314

if (*cs >= '0' && *cs<= '9')

sys/kern/tty_nmea.c

315

msgcksum += *cs - '0';

sys/kern/tty_nmea.c

316

else if (*cs >= 'A' && *cs <= 'F')

sys/kern/tty_nmea.c

317

msgcksum += 10 + *cs - 'A';

sys/kern/tty_nmea.c

318

cs++;

sys/kern/tty_nmea.c

320

DPRINTF(("bad char %c in checksum\n", *cs));

sys/net/slcompress.c

169

struct cstate *cs = comp->last_cs->cs_next;

sys/net/slcompress.c

198

if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr ||

sys/net/slcompress.c

199

ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr ||

sys/net/slcompress.c

200

*(int32_t *)th != ((int32_t *)&cs->cs_ip)[cs->cs_ip.ip_hl]) {

sys/net/slcompress.c

217

lcs = cs; cs = cs->cs_next;

sys/net/slcompress.c

219

if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr

sys/net/slcompress.c

220

&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr

sys/net/slcompress.c

222

((int32_t *)&cs->cs_ip)[cs->cs_ip.ip_hl])

sys/net/slcompress.c

224

} while (cs != lastcs);

sys/net/slcompress.c

244

if (cs == lastcs)

sys/net/slcompress.c

247

lcs->cs_next = cs->cs_next;

sys/net/slcompress.c

248

cs->cs_next = lastcs->cs_next;

sys/net/slcompress.c

249

lastcs->cs_next = cs;

sys/net/slcompress.c

264

oth = (struct tcphdr *)&((int32_t *)&cs->cs_ip)[hlen];

sys/net/slcompress.c

269

if (((u_int16_t *)ip)[0] != ((u_int16_t *)&cs->cs_ip)[0] ||

sys/net/slcompress.c

270

((u_int16_t *)ip)[3] != ((u_int16_t *)&cs->cs_ip)[3] ||

sys/net/slcompress.c

271

((u_int16_t *)ip)[4] != ((u_int16_t *)&cs->cs_ip)[4] ||

sys/net/slcompress.c

274

BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) ||

sys/net/slcompress.c

329

if (ip->ip_len != cs->cs_ip.ip_len &&

sys/net/slcompress.c

330

ntohs(cs->cs_ip.ip_len) == hlen)

sys/net/slcompress.c

345

deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {

sys/net/slcompress.c

353

if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {

sys/net/slcompress.c

361

deltaS = ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id);

sys/net/slcompress.c

373

BCOPY(ip, &cs->cs_ip, hlen);

sys/net/slcompress.c

386

if (compress_cid == 0 || comp->last_xmit != cs->cs_id) {

sys/net/slcompress.c

387

comp->last_xmit = cs->cs_id;

sys/net/slcompress.c

391

*cp++ = cs->cs_id;

sys/net/slcompress.c

411

BCOPY(ip, &cs->cs_ip, hlen);

sys/net/slcompress.c

412

ip->ip_p = cs->cs_id;

sys/net/slcompress.c

413

comp->last_xmit = cs->cs_id;

sys/net/slcompress.c

469

struct cstate *cs;

sys/net/slcompress.c

480

cs = &comp->rstate[comp->last_recv = ip->ip_p];

sys/net/slcompress.c

493

BCOPY(ip, &cs->cs_ip, hlen);

sys/net/slcompress.c

494

cs->cs_hlen = hlen;

sys/net/slcompress.c

496

*hdrp = (u_char *) &cs->cs_ip;

sys/net/slcompress.c

527

cs = &comp->rstate[comp->last_recv];

sys/net/slcompress.c

528

hlen = cs->cs_ip.ip_hl << 2;

sys/net/slcompress.c

529

th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];

sys/net/slcompress.c

540

u_int i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;

sys/net/slcompress.c

547

th->th_seq = htonl(ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len)

sys/net/slcompress.c

548

- cs->cs_hlen);

sys/net/slcompress.c

566

DECODES(cs->cs_ip.ip_id)

sys/net/slcompress.c

568

cs->cs_ip.ip_id = htons(ntohs(cs->cs_ip.ip_id) + 1);

sys/net/slcompress.c

582

total_len += cs->cs_hlen - vjlen;

sys/net/slcompress.c

583

cs->cs_ip.ip_len = htons(total_len);

sys/net/slcompress.c

586

bp = (u_int16_t *) &cs->cs_ip;

sys/net/slcompress.c

587

cs->cs_ip.ip_sum = 0;

sys/net/slcompress.c

592

cs->cs_ip.ip_sum = ~ changes;

sys/net/slcompress.c

594

*hdrp = (u_char *) &cs->cs_ip;

sys/net/slcompress.c

595

*hlenp = cs->cs_hlen;

sys/stand/boot/cmd.c

175

const struct cmd_table *ct = cmd_table, *cs;

sys/stand/boot/cmd.c

190

cs = NULL;

sys/stand/boot/cmd.c

197

cs = cmd_set;

sys/stand/boot/cmd.c

200

cs = MACHINE_CMD;

sys/stand/boot/cmd.c

204

if (cs != NULL) {

sys/stand/boot/cmd.c

205

p = whatcmd(&cs, p);

sys/stand/boot/cmd.c

206

if (cs == NULL) {

sys/stand/boot/cmd.c

210

ct = cs;

usr.bin/bc/bc.y

202

$$ = cs("");

usr.bin/bc/bc.y

214

$$ = cs("");

usr.bin/bc/bc.y

232

$$ = cs("");

usr.bin/bc/bc.y

239

$$ = node($1, cs("ps."), END_NODE);

usr.bin/bc/bc.y

244

$$ = node($3, cs($2), $1.store,

usr.bin/bc/bc.y

247

$$ = node($1.load, $3, cs($2), $1.store,

usr.bin/bc/bc.y

252

$$ = node(cs("["), as($1),

usr.bin/bc/bc.y

253

cs("]P"), END_NODE);

usr.bin/bc/bc.y

264

cs("Q"), END_NODE);

usr.bin/bc/bc.y

276

cs("J"), END_NODE);

usr.bin/bc/bc.y

306

n = node($10, cs("M"), $8, cs("s."),

usr.bin/bc/bc.y

309

n = node($10, $8, cs("s."), $6, $3,

usr.bin/bc/bc.y

313

$$ = node($4, cs("s."), $6, $3, cs(" "),

usr.bin/bc/bc.y

320

$$ = node($5, $3, cs(" "), END_NODE);

usr.bin/bc/bc.y

327

$$ = node($5, $3, cs("e"), $9, cs(" "),

usr.bin/bc/bc.y

336

n = node($6, cs("M"), $4, $3, END_NODE);

usr.bin/bc/bc.y

340

$$ = node($4, $3, cs(" "), END_NODE);

usr.bin/bc/bc.y

354

$$ = cs(str_table[macro_char]);

usr.bin/bc/bc.y

383

cs("0"), numnode(nesting),

usr.bin/bc/bc.y

384

cs("Q"), END_NODE);

usr.bin/bc/bc.y

396

prologue = cs("");

usr.bin/bc/bc.y

397

epilogue = cs("");

usr.bin/bc/bc.y

471

$$ = cs("");

usr.bin/bc/bc.y

484

$$ = node($1, cs("l"), array_node($3),

usr.bin/bc/bc.y

493

$$ = cs(" 0 0=");

usr.bin/bc/bc.y

501

$$ = node($1, $3, cs("="), END_NODE);

usr.bin/bc/bc.y

505

$$ = node($1, $3, cs("!="), END_NODE);

usr.bin/bc/bc.y

509

$$ = node($1, $3, cs(">"), END_NODE);

usr.bin/bc/bc.y

513

$$ = node($1, $3, cs("!<"), END_NODE);

usr.bin/bc/bc.y

517

$$ = node($1, $3, cs("<"), END_NODE);

usr.bin/bc/bc.y

521

$$ = node($1, $3, cs("!>"), END_NODE);

usr.bin/bc/bc.y

525

$$ = node($1, cs(" 0!="), END_NODE);

usr.bin/bc/bc.y

533

$$ = node(cs("0"), epilogue,

usr.bin/bc/bc.y

534

numnode(nesting), cs("Q"), END_NODE);

usr.bin/bc/bc.y

539

numnode(nesting), cs("Q"), END_NODE);

usr.bin/bc/bc.y

543

$$ = node(cs("0"), epilogue,

usr.bin/bc/bc.y

544

numnode(nesting), cs("Q"), END_NODE);

usr.bin/bc/bc.y

551

$$ = cs(" 0");

usr.bin/bc/bc.y

561

$$ = node(cs("l."), END_NODE);

usr.bin/bc/bc.y

565

$$ = node(cs(" "), as($1), END_NODE);

usr.bin/bc/bc.y

573

$$ = node($3, cs("l"),

usr.bin/bc/bc.y

574

function_node($1), cs("x"),

usr.bin/bc/bc.y

580

$$ = node(cs(" 0"), $2, cs("-"),

usr.bin/bc/bc.y

585

$$ = node($1, $3, cs("+"), END_NODE);

usr.bin/bc/bc.y

589

$$ = node($1, $3, cs("-"), END_NODE);

usr.bin/bc/bc.y

593

$$ = node($1, $3, cs("*"), END_NODE);

usr.bin/bc/bc.y

597

$$ = node($1, $3, cs("/"), END_NODE);

usr.bin/bc/bc.y

601

$$ = node($1, $3, cs("%"), END_NODE);

usr.bin/bc/bc.y

605

$$ = node($1, $3, cs("^"), END_NODE);

usr.bin/bc/bc.y

609

$$ = node($2.load, cs("1+d"), $2.store,

usr.bin/bc/bc.y

614

$$ = node($2.load, cs("1-d"),

usr.bin/bc/bc.y

619

$$ = node($1.load, cs("d1+"),

usr.bin/bc/bc.y

624

$$ = node($1.load, cs("d1-"),

usr.bin/bc/bc.y

630

$$ = node($3, cs($2), cs("d"), $1.store,

usr.bin/bc/bc.y

633

$$ = node($1.load, $3, cs($2), cs("d"),

usr.bin/bc/bc.y

638

$$ = node($3, cs("Z"), END_NODE);

usr.bin/bc/bc.y

642

$$ = node($3, cs("v"), END_NODE);

usr.bin/bc/bc.y

646

$$ = node($3, cs("X"), END_NODE);

usr.bin/bc/bc.y

650

$$ = node($2, cs("N"), END_NODE);

usr.bin/bc/bc.y

654

ssize_t n = node(cs("R"), $5, END_NODE);

usr.bin/bc/bc.y

656

$$ = node($1, cs("d0!="), $3, END_NODE);

usr.bin/bc/bc.y

660

ssize_t n = node(cs("R"), $5, END_NODE);

usr.bin/bc/bc.y

662

$$ = node($1, cs("d0="), $3, END_NODE);

usr.bin/bc/bc.y

666

$$ = node($1, $3, cs("G"), END_NODE);

usr.bin/bc/bc.y

670

$$ = node($1, $3, cs("GN"), END_NODE);

usr.bin/bc/bc.y

674

$$ = node($3, $1, cs("("), END_NODE);

usr.bin/bc/bc.y

678

$$ = node($3, $1, cs("{"), END_NODE);

usr.bin/bc/bc.y

682

$$ = node($1, $3, cs("("), END_NODE);

usr.bin/bc/bc.y

686

$$ = node($1, $3, cs("{"), END_NODE);

usr.bin/bc/bc.y

693

$$.load = node(cs("l"), letter_node($1),

usr.bin/bc/bc.y

695

$$.store = node(cs("s"), letter_node($1),

usr.bin/bc/bc.y

701

$$.load = node($3, cs(";"),

usr.bin/bc/bc.y

703

$$.store = node($3, cs(":"),

usr.bin/bc/bc.y

709

$$.load = cs("K");

usr.bin/bc/bc.y

710

$$.store = cs("k");

usr.bin/bc/bc.y

714

$$.load = cs("I");

usr.bin/bc/bc.y

715

$$.store = cs("i");

usr.bin/bc/bc.y

719

$$.load = cs("O");

usr.bin/bc/bc.y

72

static ssize_t cs(const char *);

usr.bin/bc/bc.y

720

$$.store = cs("o");

usr.bin/bc/bc.y

734

$$ = node($1, cs("ds.n"), END_NODE);

usr.bin/bc/bc.y

739

$$ = node(cs("["), as(p), cs("]n"), END_NODE);

usr.bin/bc/bc.y

851

return node(cs(" "), cs(p), END_NODE);

usr.bin/bc/bc.y

889

return cs(found->data);

usr.bin/bc/bc.y

899

return cs(str_table[(int)str[0]]);

usr.bin/bc/bc.y

911

return cs(str_table[(int)str[0] - 'a' + ARRAY_CHAR]);

usr.bin/bc/bc.y

923

return cs(str_table[(int)str[0] - 'a' + FUNC_CHAR]);

usr.bin/bc/bc.y

931

prologue = node(cs("S"), n, prologue, END_NODE);

usr.bin/bc/bc.y

932

epilogue = node(epilogue, cs("L"), n, cs("s."), END_NODE);

usr.bin/bc/bc.y

938

prologue = node(cs("0S"), n, prologue, END_NODE);

usr.bin/bc/bc.y

939

epilogue = node(epilogue, cs("L"), n, cs("s."), END_NODE);

usr.bin/hexdump/parse.c

214

char savech, *fmtp, cs[4];

usr.bin/hexdump/parse.c

264

cs[0] = *p1; /* Set conversion string. */

usr.bin/hexdump/parse.c

265

cs[1] = '\0';

usr.bin/hexdump/parse.c

272

switch(cs[0]) {

usr.bin/hexdump/parse.c

286

if (cs[0] == 'd' || cs[0] == 'i')

usr.bin/hexdump/parse.c

291

cs[3] = '\0';

usr.bin/hexdump/parse.c

292

cs[2] = cs[0];

usr.bin/hexdump/parse.c

293

cs[1] = 'l';

usr.bin/hexdump/parse.c

294

cs[0] = 'l';

usr.bin/hexdump/parse.c

352

cs[0] = 'l';

usr.bin/hexdump/parse.c

353

cs[1] = 'l';

usr.bin/hexdump/parse.c

354

cs[2] = p1[2];

usr.bin/hexdump/parse.c

355

cs[3] = '\0';

usr.bin/hexdump/parse.c

371

cs[0] = 'c';

usr.bin/hexdump/parse.c

393

if (cs[0])

usr.bin/hexdump/parse.c

404

if (asprintf(&pr->fmt, "%s%s", fmtp, cs) == -1)

usr.bin/less/cmdbuf.c

405

cmd_ichar(char *cs, int clen)

usr.bin/less/cmdbuf.c

424

*s = *cs++;

usr.bin/less/line.c

493

char cs;

usr.bin/less/line.c

544

cs = (char)ch;

usr.bin/less/line.c

545

rep = &cs;

usr.bin/mandoc/mansearch.c

722

int cs, i, irc;

usr.bin/mandoc/mansearch.c

736

cs = 0;

usr.bin/mandoc/mansearch.c

739

cs = 1;

usr.bin/mandoc/mansearch.c

763

cs = 0;

usr.bin/mandoc/mansearch.c

768

cs = 0;

usr.bin/mandoc/mansearch.c

779

cs = 0;

usr.bin/mandoc/mansearch.c

787

REG_EXTENDED | REG_NOSUB | (cs ? 0 : REG_ICASE));

usr.bin/rpcgen/rpc_cout.c

342

declaration *cs;

usr.bin/rpcgen/rpc_cout.c

354

cs = &cl->case_decl;

usr.bin/rpcgen/rpc_cout.c

355

if (!streq(cs->type, "void")) {

usr.bin/rpcgen/rpc_cout.c

357

strlen(cs->name) + 1;

usr.bin/rpcgen/rpc_cout.c

364

if (isvectordef(cs->type, cs->rel)) {

usr.bin/rpcgen/rpc_cout.c

366

cs->name);

usr.bin/rpcgen/rpc_cout.c

369

cs->name);

usr.bin/rpcgen/rpc_cout.c

371

print_ifstat(2, cs->prefix, cs->type, cs->rel, cs->array_max,

usr.bin/rpcgen/rpc_cout.c

372

object, cs->name);

usr.bin/systat/vmstat.c

599

struct cpustats cs;

usr.bin/systat/vmstat.c

619

size = sizeof(cs);

usr.bin/systat/vmstat.c

620

if (sysctl(cpustats_mib, 3, &cs, &size, NULL, 0) == -1) {

usr.bin/systat/vmstat.c

624

if ((cs.cs_flags & CPUSTATS_ONLINE) == 0)

usr.bin/systat/vmstat.c

626

for (j = 0; j < nitems(cs.cs_time); j++)

usr.bin/systat/vmstat.c

627

si->cpustats.cs_time[j] += cs.cs_time[j];

usr.bin/tmux/control-notify.c

110

struct session *cs;

usr.bin/tmux/control-notify.c

115

cs = c->session;

usr.bin/tmux/control-notify.c

117

if (winlink_find_by_window_id(&cs->windows, w->id) != NULL)

usr.bin/tmux/control-notify.c

128

struct session *cs;

usr.bin/tmux/control-notify.c

133

cs = c->session;

usr.bin/tmux/control-notify.c

135

if (winlink_find_by_window_id(&cs->windows, w->id) != NULL) {

usr.bin/tmux/control-notify.c

92

struct session *cs;

usr.bin/tmux/control-notify.c

97

cs = c->session;

usr.bin/tmux/control-notify.c

99

if (winlink_find_by_window_id(&cs->windows, w->id) != NULL)

usr.bin/tmux/control.c

1036

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

1047

evtimer_add(&cs->subs_timer, &tv);

usr.bin/tmux/control.c

1053

RB_FOREACH(csub, control_subs, &cs->subs) {

usr.bin/tmux/control.c

1072

RB_FOREACH_SAFE(csub, control_subs, &cs->subs, csub1) {

usr.bin/tmux/control.c

1080

RB_FOREACH_SAFE(csub, control_subs, &cs->subs, csub1) {

usr.bin/tmux/control.c

1100

RB_FOREACH_SAFE(csub, control_subs, &cs->subs,

usr.bin/tmux/control.c

1116

RB_FOREACH_SAFE(csub, control_subs, &cs->subs,

usr.bin/tmux/control.c

1133

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

1138

if ((csub = RB_FIND(control_subs, &cs->subs, &find)) != NULL)

usr.bin/tmux/control.c

1139

control_free_sub(cs, csub);

usr.bin/tmux/control.c

1146

RB_INSERT(control_subs, &cs->subs, csub);

usr.bin/tmux/control.c

1151

if (!evtimer_initialized(&cs->subs_timer))

usr.bin/tmux/control.c

1152

evtimer_set(&cs->subs_timer, control_check_subs_timer, c);

usr.bin/tmux/control.c

1153

if (!evtimer_pending(&cs->subs_timer, NULL))

usr.bin/tmux/control.c

1154

evtimer_add(&cs->subs_timer, &tv);

usr.bin/tmux/control.c

1161

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

1165

if ((csub = RB_FIND(control_subs, &cs->subs, &find)) != NULL)

usr.bin/tmux/control.c

1166

control_free_sub(cs, csub);

usr.bin/tmux/control.c

1167

if (RB_EMPTY(&cs->subs))

usr.bin/tmux/control.c

1168

evtimer_del(&cs->subs_timer);

usr.bin/tmux/control.c

204

control_free_sub(struct control_state *cs, struct control_sub *csub)

usr.bin/tmux/control.c

219

RB_REMOVE(control_subs, &cs->subs, csub);

usr.bin/tmux/control.c

227

control_free_block(struct control_state *cs, struct control_block *cb)

usr.bin/tmux/control.c

230

TAILQ_REMOVE(&cs->all_blocks, cb, all_entry);

usr.bin/tmux/control.c

238

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

241

return (RB_FIND(control_panes, &cs->panes, &cp));

usr.bin/tmux/control.c

248

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

257

RB_INSERT(control_panes, &cs->panes, cp);

usr.bin/tmux/control.c

270

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

275

control_free_block(cs, cb);

usr.bin/tmux/control.c

298

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

301

RB_FOREACH_SAFE(cp, control_panes, &cs->panes, cp1) {

usr.bin/tmux/control.c

302

RB_REMOVE(control_panes, &cs->panes, cp);

usr.bin/tmux/control.c

306

TAILQ_INIT(&cs->pending_list);

usr.bin/tmux/control.c

307

cs->pending_count = 0;

usr.bin/tmux/control.c

314

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

331

*off = (EVBUFFER_LENGTH(cs->write_event->output) >= CONTROL_BUFFER_LOW);

usr.bin/tmux/control.c

392

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

398

bufferevent_write(cs->write_event, s, strlen(s));

usr.bin/tmux/control.c

399

bufferevent_write(cs->write_event, "\n", 1);

usr.bin/tmux/control.c

401

bufferevent_enable(cs->write_event, EV_WRITE);

usr.bin/tmux/control.c

409

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

415

if (TAILQ_EMPTY(&cs->all_blocks)) {

usr.bin/tmux/control.c

423

TAILQ_INSERT_TAIL(&cs->all_blocks, cb, all_entry);

usr.bin/tmux/control.c

427

bufferevent_enable(cs->write_event, EV_WRITE);

usr.bin/tmux/control.c

471

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

498

TAILQ_INSERT_TAIL(&cs->all_blocks, cb, all_entry);

usr.bin/tmux/control.c

508

TAILQ_INSERT_TAIL(&cs->pending_list, cp, pending_entry);

usr.bin/tmux/control.c

510

cs->pending_count++;

usr.bin/tmux/control.c

512

bufferevent_enable(cs->write_event, EV_WRITE);

usr.bin/tmux/control.c

551

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

552

struct evbuffer *buffer = cs->read_event->input;

usr.bin/tmux/control.c

582

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

584

if (!TAILQ_EMPTY(&cs->all_blocks))

usr.bin/tmux/control.c

586

return (EVBUFFER_LENGTH(cs->write_event->output) == 0);

usr.bin/tmux/control.c

593

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

596

TAILQ_FOREACH_SAFE(cb, &cs->all_blocks, all_entry, cb1) {

usr.bin/tmux/control.c

602

bufferevent_write(cs->write_event, cb->line, strlen(cb->line));

usr.bin/tmux/control.c

603

bufferevent_write(cs->write_event, "\n", 1);

usr.bin/tmux/control.c

604

control_free_block(cs, cb);

usr.bin/tmux/control.c

652

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

658

bufferevent_write_buffer(cs->write_event, message);

usr.bin/tmux/control.c

666

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

677

control_free_block(cs, cb);

usr.bin/tmux/control.c

710

control_free_block(cs, cb);

usr.bin/tmux/control.c

712

cb = TAILQ_FIRST(&cs->all_blocks);

usr.bin/tmux/control.c

732

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

734

struct evbuffer *evb = cs->write_event->output;

usr.bin/tmux/control.c

740

if (cs->pending_count == 0)

usr.bin/tmux/control.c

744

c->name, space, cs->pending_count);

usr.bin/tmux/control.c

746

limit = (space / cs->pending_count / 3); /* 3 bytes for \xxx */

usr.bin/tmux/control.c

750

TAILQ_FOREACH_SAFE(cp, &cs->pending_list, pending_entry, cp1) {

usr.bin/tmux/control.c

755

TAILQ_REMOVE(&cs->pending_list, cp, pending_entry);

usr.bin/tmux/control.c

757

cs->pending_count--;

usr.bin/tmux/control.c

761

bufferevent_disable(cs->write_event, EV_WRITE);

usr.bin/tmux/control.c

768

struct control_state *cs;

usr.bin/tmux/control.c

777

cs = c->control_state = xcalloc(1, sizeof *cs);

usr.bin/tmux/control.c

778

RB_INIT(&cs->panes);

usr.bin/tmux/control.c

779

TAILQ_INIT(&cs->pending_list);

usr.bin/tmux/control.c

780

TAILQ_INIT(&cs->all_blocks);

usr.bin/tmux/control.c

781

RB_INIT(&cs->subs);

usr.bin/tmux/control.c

783

cs->read_event = bufferevent_new(c->fd, control_read_callback,

usr.bin/tmux/control.c

785

if (cs->read_event == NULL)

usr.bin/tmux/control.c

789

cs->write_event = cs->read_event;

usr.bin/tmux/control.c

791

cs->write_event = bufferevent_new(c->out_fd, NULL,

usr.bin/tmux/control.c

793

if (cs->write_event == NULL)

usr.bin/tmux/control.c

796

bufferevent_setwatermark(cs->write_event, EV_WRITE, CONTROL_BUFFER_LOW,

usr.bin/tmux/control.c

800

bufferevent_write(cs->write_event, "\033P1000p", 7);

usr.bin/tmux/control.c

801

bufferevent_enable(cs->write_event, EV_WRITE);

usr.bin/tmux/control.c

816

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

819

RB_FOREACH(cp, control_panes, &cs->panes)

usr.bin/tmux/control.c

821

bufferevent_disable(cs->read_event, EV_READ);

usr.bin/tmux/control.c

828

struct control_state *cs = c->control_state;

usr.bin/tmux/control.c

833

bufferevent_free(cs->write_event);

usr.bin/tmux/control.c

834

bufferevent_free(cs->read_event);

usr.bin/tmux/control.c

836

RB_FOREACH_SAFE(csub, control_subs, &cs->subs, csub1)

usr.bin/tmux/control.c

837

control_free_sub(cs, csub);

usr.bin/tmux/control.c

838

if (evtimer_initialized(&cs->subs_timer))

usr.bin/tmux/control.c

839

evtimer_del(&cs->subs_timer);

usr.bin/tmux/control.c

841

TAILQ_FOREACH_SAFE(cb, &cs->all_blocks, all_entry, cb1)

usr.bin/tmux/control.c

842

control_free_block(cs, cb);

usr.bin/tmux/control.c

845

free(cs);

usr.bin/tmux/window-copy.c

1063

window_copy_expand_search_string(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1065

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1067

const char *ss = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

1073

if (args_has(cs->args, 'F')) {

usr.bin/tmux/window-copy.c

1089

window_copy_cmd_append_selection(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1091

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1092

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

1101

window_copy_cmd_append_selection_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1103

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1104

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

1113

window_copy_cmd_back_to_indentation(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1115

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1122

window_copy_cmd_begin_selection(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1124

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1125

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

1126

struct mouse_event *m = cs->m;

usr.bin/tmux/window-copy.c

1141

window_copy_cmd_stop_selection(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1143

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1153

window_copy_cmd_bottom_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1155

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1166

window_copy_cmd_cancel(__unused struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1172

window_copy_cmd_clear_selection(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1174

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1181

window_copy_do_copy_end_of_line(struct window_copy_cmd_state *cs, int pipe,

usr.bin/tmux/window-copy.c

1184

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1185

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

1186

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

1187

struct winlink *wl = cs->wl;

usr.bin/tmux/window-copy.c

1189

u_int count = args_count(cs->wargs);

usr.bin/tmux/window-copy.c

1193

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

1194

const char *arg1 = args_string(cs->wargs, 1);

usr.bin/tmux/window-copy.c

1195

int set_paste = !args_has(cs->wargs, 'P');

usr.bin/tmux/window-copy.c

1196

int set_clip = !args_has(cs->wargs, 'C');

usr.bin/tmux/window-copy.c

1243

window_copy_cmd_copy_end_of_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1245

return (window_copy_do_copy_end_of_line(cs, 0, 0));

usr.bin/tmux/window-copy.c

1249

window_copy_cmd_copy_end_of_line_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1251

return (window_copy_do_copy_end_of_line(cs, 0, 1));

usr.bin/tmux/window-copy.c

1255

window_copy_cmd_copy_pipe_end_of_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1257

return (window_copy_do_copy_end_of_line(cs, 1, 0));

usr.bin/tmux/window-copy.c

1262

struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1264

return (window_copy_do_copy_end_of_line(cs, 1, 1));

usr.bin/tmux/window-copy.c

1268

window_copy_do_copy_line(struct window_copy_cmd_state *cs, int pipe, int cancel)

usr.bin/tmux/window-copy.c

1270

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1271

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

1272

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

1273

struct winlink *wl = cs->wl;

usr.bin/tmux/window-copy.c

1276

u_int count = args_count(cs->wargs);

usr.bin/tmux/window-copy.c

1279

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

1280

const char *arg1 = args_string(cs->wargs, 1);

usr.bin/tmux/window-copy.c

1281

int set_paste = !args_has(cs->wargs, 'P');

usr.bin/tmux/window-copy.c

1282

int set_clip = !args_has(cs->wargs, 'C');

usr.bin/tmux/window-copy.c

1331

window_copy_cmd_copy_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1333

return (window_copy_do_copy_line(cs, 0, 0));

usr.bin/tmux/window-copy.c

1337

window_copy_cmd_copy_line_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1339

return (window_copy_do_copy_line(cs, 0, 1));

usr.bin/tmux/window-copy.c

1343

window_copy_cmd_copy_pipe_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1345

return (window_copy_do_copy_line(cs, 1, 0));

usr.bin/tmux/window-copy.c

1349

window_copy_cmd_copy_pipe_line_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1351

return (window_copy_do_copy_line(cs, 1, 1));

usr.bin/tmux/window-copy.c

1355

window_copy_cmd_copy_selection_no_clear(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1357

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1358

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

1359

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

1360

struct winlink *wl = cs->wl;

usr.bin/tmux/window-copy.c

1363

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

1364

int set_paste = !args_has(cs->wargs, 'P');

usr.bin/tmux/window-copy.c

1365

int set_clip = !args_has(cs->wargs, 'C');

usr.bin/tmux/window-copy.c

1378

window_copy_cmd_copy_selection(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1380

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1382

window_copy_cmd_copy_selection_no_clear(cs);

usr.bin/tmux/window-copy.c

1388

window_copy_cmd_copy_selection_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1390

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1392

window_copy_cmd_copy_selection_no_clear(cs);

usr.bin/tmux/window-copy.c

1398

window_copy_cmd_cursor_down(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1400

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1409

window_copy_cmd_cursor_down_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1411

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1424

window_copy_cmd_cursor_left(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1426

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1435

window_copy_cmd_cursor_right(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1437

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1450

window_copy_cmd_scroll_to(struct window_copy_cmd_state *cs, u_int to)

usr.bin/tmux/window-copy.c

1452

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1479

window_copy_cmd_scroll_bottom(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1481

struct window_copy_mode_data *data = cs->wme->data;

usr.bin/tmux/window-copy.c

1485

return (window_copy_cmd_scroll_to(cs, bottom));

usr.bin/tmux/window-copy.c

1490

window_copy_cmd_scroll_middle(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1492

struct window_copy_mode_data *data = cs->wme->data;

usr.bin/tmux/window-copy.c

1496

return (window_copy_cmd_scroll_to(cs, mid_value));

usr.bin/tmux/window-copy.c

1501

window_copy_cmd_scroll_to_mouse(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1503

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1505

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

1506

struct mouse_event *m = cs->m;

usr.bin/tmux/window-copy.c

1507

int scroll_exit = args_has(cs->wargs, 'e');

usr.bin/tmux/window-copy.c

1515

window_copy_cmd_scroll_top(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1517

return (window_copy_cmd_scroll_to(cs, 0));

usr.bin/tmux/window-copy.c

1521

window_copy_cmd_cursor_up(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1523

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1532

window_copy_cmd_centre_vertical(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1534

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1543

window_copy_cmd_centre_horizontal(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1545

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1554

window_copy_cmd_end_of_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1556

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1563

window_copy_cmd_halfpage_down(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1565

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1577

window_copy_cmd_halfpage_down_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1580

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1591

window_copy_cmd_halfpage_up(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1593

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1602

window_copy_cmd_toggle_position(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1604

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1612

window_copy_cmd_history_bottom(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1614

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1634

window_copy_cmd_history_top(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1636

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1655

window_copy_cmd_jump_again(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1657

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1683

window_copy_cmd_jump_reverse(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1685

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1711

window_copy_cmd_middle_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1713

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1724

window_copy_cmd_previous_matching_bracket(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1726

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1810

window_copy_cmd_next_matching_bracket(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1812

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1855

window_copy_cmd_previous_matching_bracket(cs);

usr.bin/tmux/window-copy.c

1931

window_copy_cmd_next_paragraph(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1933

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1942

window_copy_cmd_next_space(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1944

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1953

window_copy_cmd_next_space_end(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1955

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1964

window_copy_cmd_next_word(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1966

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1970

separators = options_get_string(cs->s->options, "word-separators");

usr.bin/tmux/window-copy.c

1978

window_copy_cmd_next_word_end(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1980

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

1984

separators = options_get_string(cs->s->options, "word-separators");

usr.bin/tmux/window-copy.c

1992

window_copy_cmd_other_end(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

1994

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2005

window_copy_cmd_selection_mode(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2007

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2008

struct options *so = cs->s->options;

usr.bin/tmux/window-copy.c

2010

const char *s = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2023

window_copy_cmd_page_down(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2025

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2037

window_copy_cmd_page_down_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2039

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2050

window_copy_cmd_page_up(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2052

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2061

window_copy_cmd_previous_paragraph(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2063

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2072

window_copy_cmd_previous_space(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2074

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2083

window_copy_cmd_previous_word(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2085

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2089

separators = options_get_string(cs->s->options, "word-separators");

usr.bin/tmux/window-copy.c

2097

window_copy_cmd_rectangle_on(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2099

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2109

window_copy_cmd_rectangle_off(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2111

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2121

window_copy_cmd_rectangle_toggle(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2123

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2133

window_copy_cmd_scroll_exit_on(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2135

struct window_copy_mode_data *data = cs->wme->data;

usr.bin/tmux/window-copy.c

2143

window_copy_cmd_scroll_exit_off(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2145

struct window_copy_mode_data *data = cs->wme->data;

usr.bin/tmux/window-copy.c

2153

window_copy_cmd_scroll_exit_toggle(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2155

struct window_copy_mode_data *data = cs->wme->data;

usr.bin/tmux/window-copy.c

2163

window_copy_cmd_scroll_down(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2165

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2177

window_copy_cmd_scroll_down_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2179

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2191

window_copy_cmd_scroll_up(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2193

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2202

window_copy_cmd_search_again(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2204

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2219

window_copy_cmd_search_reverse(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2221

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2236

window_copy_cmd_select_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2238

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2265

window_copy_cmd_select_word(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2267

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2268

struct options *so = cs->s->options;

usr.bin/tmux/window-copy.c

2314

window_copy_cmd_set_mark(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2316

struct window_copy_mode_data *data = cs->wme->data;

usr.bin/tmux/window-copy.c

2325

window_copy_cmd_start_of_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2327

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2334

window_copy_cmd_top_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2336

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2347

window_copy_cmd_copy_pipe_no_clear(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2349

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2350

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

2351

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

2352

struct winlink *wl = cs->wl;

usr.bin/tmux/window-copy.c

2355

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2356

const char *arg1 = args_string(cs->wargs, 1);

usr.bin/tmux/window-copy.c

2357

int set_paste = !args_has(cs->wargs, 'P');

usr.bin/tmux/window-copy.c

2358

int set_clip = !args_has(cs->wargs, 'C');

usr.bin/tmux/window-copy.c

2374

window_copy_cmd_copy_pipe(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2376

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2378

window_copy_cmd_copy_pipe_no_clear(cs);

usr.bin/tmux/window-copy.c

2384

window_copy_cmd_copy_pipe_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2386

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2388

window_copy_cmd_copy_pipe_no_clear(cs);

usr.bin/tmux/window-copy.c

2394

window_copy_cmd_pipe_no_clear(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2396

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2397

struct client *c = cs->c;

usr.bin/tmux/window-copy.c

2398

struct session *s = cs->s;

usr.bin/tmux/window-copy.c

2399

struct winlink *wl = cs->wl;

usr.bin/tmux/window-copy.c

2402

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2413

window_copy_cmd_pipe(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2415

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2417

window_copy_cmd_pipe_no_clear(cs);

usr.bin/tmux/window-copy.c

2423

window_copy_cmd_pipe_and_cancel(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2425

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2427

window_copy_cmd_pipe_no_clear(cs);

usr.bin/tmux/window-copy.c

2433

window_copy_cmd_goto_line(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2435

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2436

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2444

window_copy_cmd_jump_backward(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2446

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2449

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2462

window_copy_cmd_jump_forward(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2464

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2467

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2480

window_copy_cmd_jump_to_backward(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2482

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2485

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2498

window_copy_cmd_jump_to_forward(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2500

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2503

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2516

window_copy_cmd_jump_to_mark(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2518

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2525

window_copy_cmd_next_prompt(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2527

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2529

window_copy_cursor_prompt(wme, 1, args_has(cs->wargs, 'o'));

usr.bin/tmux/window-copy.c

2534

window_copy_cmd_previous_prompt(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2536

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2538

window_copy_cursor_prompt(wme, 0, args_has(cs->wargs, 'o'));

usr.bin/tmux/window-copy.c

2543

window_copy_cmd_search_backward(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2545

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2549

if (!window_copy_expand_search_string(cs))

usr.bin/tmux/window-copy.c

2563

window_copy_cmd_search_backward_text(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2565

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2569

if (!window_copy_expand_search_string(cs))

usr.bin/tmux/window-copy.c

2583

window_copy_cmd_search_forward(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2585

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2589

if (!window_copy_expand_search_string(cs))

usr.bin/tmux/window-copy.c

2603

window_copy_cmd_search_forward_text(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2605

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2609

if (!window_copy_expand_search_string(cs))

usr.bin/tmux/window-copy.c

2623

window_copy_cmd_search_backward_incremental(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2625

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2627

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2678

window_copy_cmd_search_forward_incremental(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2680

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

2682

const char *arg0 = args_string(cs->wargs, 0);

usr.bin/tmux/window-copy.c

2732

window_copy_cmd_refresh_from_pane(struct window_copy_cmd_state *cs)

usr.bin/tmux/window-copy.c

2734

struct window_mode_entry *wme = cs->wme;

usr.bin/tmux/window-copy.c

3331

struct window_copy_cmd_state cs;

usr.bin/tmux/window-copy.c

3346

cs.wme = wme;

usr.bin/tmux/window-copy.c

3347

cs.args = args;

usr.bin/tmux/window-copy.c

3348

cs.wargs = NULL;

usr.bin/tmux/window-copy.c

3349

cs.m = m;

usr.bin/tmux/window-copy.c

3351

cs.c = c;

usr.bin/tmux/window-copy.c

3352

cs.s = s;

usr.bin/tmux/window-copy.c

3353

cs.wl = wl;

usr.bin/tmux/window-copy.c

3367

cs.wargs = args_parse(&window_copy_cmd_table[i].args,

usr.bin/tmux/window-copy.c

3374

if (cs.wargs == NULL)

usr.bin/tmux/window-copy.c

3378

action = window_copy_cmd_table[i].f(&cs);

usr.bin/tmux/window-copy.c

3379

args_free(cs.wargs);

usr.bin/tmux/window-copy.c

3380

cs.wargs = NULL;

usr.bin/vi/vi/v_match.c

100

cs.cs_cno = off;

usr.bin/vi/vi/v_match.c

101

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_match.c

104

if (gc(sp, &cs))

usr.bin/vi/vi/v_match.c

106

if (cs.cs_flags != 0) {

usr.bin/vi/vi/v_match.c

107

if (cs.cs_flags == CS_EOF || cs.cs_flags == CS_SOF)

usr.bin/vi/vi/v_match.c

111

if (cs.cs_ch == startc)

usr.bin/vi/vi/v_match.c

113

else if (cs.cs_ch == matchc && --cnt == 0)

usr.bin/vi/vi/v_match.c

121

vp->m_stop.lno = cs.cs_lno;

usr.bin/vi/vi/v_match.c

122

vp->m_stop.cno = cs.cs_cno;

usr.bin/vi/vi/v_match.c

36

VCS cs;

usr.bin/vi/vi/v_match.c

99

cs.cs_lno = vp->m_start.lno;

usr.bin/vi/vi/v_sentence.c

101

if (cs.cs_flags == CS_EMP) { /* An EMP is two sentences. */

usr.bin/vi/vi/v_sentence.c

104

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_sentence.c

111

switch (cs.cs_ch) {

usr.bin/vi/vi/v_sentence.c

134

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_sentence.c

146

if (vp->m_start.lno == cs.cs_lno && vp->m_start.cno == cs.cs_cno) {

usr.bin/vi/vi/v_sentence.c

151

okret: vp->m_stop.lno = cs.cs_lno;

usr.bin/vi/vi/v_sentence.c

152

vp->m_stop.cno = cs.cs_cno;

usr.bin/vi/vi/v_sentence.c

169

(cs.cs_flags != 0 || vp->m_stop.cno == 0)) {

usr.bin/vi/vi/v_sentence.c

194

VCS cs;

usr.bin/vi/vi/v_sentence.c

207

cs.cs_lno = vp->m_start.lno;

usr.bin/vi/vi/v_sentence.c

208

cs.cs_cno = vp->m_start.cno;

usr.bin/vi/vi/v_sentence.c

209

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_sentence.c

225

if (cs.cs_flags == CS_EMP) {

usr.bin/vi/vi/v_sentence.c

226

if (cs_bblank(sp, &cs))

usr.bin/vi/vi/v_sentence.c

229

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_sentence.c

231

if (cs.cs_flags != CS_EOL)

usr.bin/vi/vi/v_sentence.c

234

} else if (cs.cs_flags == 0 && !isblank(cs.cs_ch))

usr.bin/vi/vi/v_sentence.c

236

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_sentence.c

238

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_sentence.c

243

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_sentence.c

245

if (cs.cs_flags == CS_SOF) /* SOF is a movement sink. */

usr.bin/vi/vi/v_sentence.c

247

if (cs.cs_flags == CS_EOL) {

usr.bin/vi/vi/v_sentence.c

251

if (cs.cs_flags == CS_EMP) {

usr.bin/vi/vi/v_sentence.c

254

if (cs_bblank(sp, &cs))

usr.bin/vi/vi/v_sentence.c

259

switch (cs.cs_ch) {

usr.bin/vi/vi/v_sentence.c

268

ret: slno = cs.cs_lno;

usr.bin/vi/vi/v_sentence.c

269

scno = cs.cs_cno;

usr.bin/vi/vi/v_sentence.c

276

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_sentence.c

278

} while (!cs.cs_flags &&

usr.bin/vi/vi/v_sentence.c

279

(cs.cs_ch == ')' || cs.cs_ch == ']' ||

usr.bin/vi/vi/v_sentence.c

280

cs.cs_ch == '"' || cs.cs_ch == '\''));

usr.bin/vi/vi/v_sentence.c

281

if ((cs.cs_flags || isblank(cs.cs_ch)) &&

usr.bin/vi/vi/v_sentence.c

282

cs_fblank(sp, &cs))

usr.bin/vi/vi/v_sentence.c

291

if (vp->m_start.lno != cs.cs_lno ||

usr.bin/vi/vi/v_sentence.c

292

vp->m_start.cno != cs.cs_cno)

usr.bin/vi/vi/v_sentence.c

300

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_sentence.c

302

if (cs.cs_flags == CS_EOL)

usr.bin/vi/vi/v_sentence.c

304

if (cs.cs_flags == 0 && isblank(cs.cs_ch))

usr.bin/vi/vi/v_sentence.c

308

if (cs.cs_flags == CS_EMP)

usr.bin/vi/vi/v_sentence.c

313

cs.cs_lno = slno;

usr.bin/vi/vi/v_sentence.c

314

cs.cs_cno = scno;

usr.bin/vi/vi/v_sentence.c

322

cs.cs_flags == CS_EOL || isblank(cs.cs_ch) ||

usr.bin/vi/vi/v_sentence.c

323

cs.cs_ch == ')' || cs.cs_ch == ']' ||

usr.bin/vi/vi/v_sentence.c

324

cs.cs_ch == '"' || cs.cs_ch == '\'' ? 1 : 0;

usr.bin/vi/vi/v_sentence.c

328

okret: vp->m_stop.lno = cs.cs_lno;

usr.bin/vi/vi/v_sentence.c

329

vp->m_stop.cno = cs.cs_cno;

usr.bin/vi/vi/v_sentence.c

343

(cs.cs_flags != 0 || vp->m_stop.cno == 0)) {

usr.bin/vi/vi/v_sentence.c

56

VCS cs;

usr.bin/vi/vi/v_sentence.c

60

cs.cs_lno = vp->m_start.lno;

usr.bin/vi/vi/v_sentence.c

61

cs.cs_cno = vp->m_start.cno;

usr.bin/vi/vi/v_sentence.c

62

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_sentence.c

73

if (cs.cs_flags == CS_EMP || (cs.cs_flags == 0 && isblank(cs.cs_ch))) {

usr.bin/vi/vi/v_sentence.c

74

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_sentence.c

77

if (vp->m_start.lno != cs.cs_lno ||

usr.bin/vi/vi/v_sentence.c

78

vp->m_start.cno != cs.cs_cno)

usr.bin/vi/vi/v_sentence.c

85

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_sentence.c

87

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_sentence.c

89

if (cs.cs_flags == CS_EOL) {

usr.bin/vi/vi/v_sentence.c

91

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_sentence.c

93

if (cs.cs_flags == 0 &&

usr.bin/vi/vi/v_sentence.c

94

isblank(cs.cs_ch) && cs_fblank(sp, &cs))

usr.bin/vi/vi/v_txt.c

2676

VCS cs;

usr.bin/vi/vi/v_txt.c

2696

cs.cs_lno = tp->lno;

usr.bin/vi/vi/v_txt.c

2697

cs.cs_cno = tp->cno - 1;

usr.bin/vi/vi/v_txt.c

2698

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_txt.c

2700

startc = (endc = cs.cs_ch) == ')' ? '(' : '{';

usr.bin/vi/vi/v_txt.c

2704

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_txt.c

2706

if (cs.cs_flags != 0) {

usr.bin/vi/vi/v_txt.c

2707

if (cs.cs_flags == CS_EOF || cs.cs_flags == CS_SOF) {

usr.bin/vi/vi/v_txt.c

2714

if (cs.cs_ch == endc)

usr.bin/vi/vi/v_txt.c

2716

else if (cs.cs_ch == startc && --cnt == 0)

usr.bin/vi/vi/v_txt.c

2721

if (cs.cs_lno < m.lno || (cs.cs_lno == m.lno && cs.cs_cno < m.cno))

usr.bin/vi/vi/v_txt.c

2723

sp->lno = cs.cs_lno;

usr.bin/vi/vi/v_txt.c

2724

sp->cno = cs.cs_cno;

usr.bin/vi/vi/v_word.c

103

VCS cs;

usr.bin/vi/vi/v_word.c

107

cs.cs_lno = vp->m_start.lno;

usr.bin/vi/vi/v_word.c

108

cs.cs_cno = vp->m_start.cno;

usr.bin/vi/vi/v_word.c

109

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_word.c

119

if (cs.cs_flags == CS_EMP || (cs.cs_flags == 0 && isblank(cs.cs_ch))) {

usr.bin/vi/vi/v_word.c

120

if (ISMOTION(vp) && cs.cs_flags != CS_EMP && cnt == 1) {

usr.bin/vi/vi/v_word.c

124

if (cs_fspace(sp, &cs))

usr.bin/vi/vi/v_word.c

129

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_word.c

143

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

145

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

147

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

159

cs_fspace(sp, &cs))

usr.bin/vi/vi/v_word.c

165

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_word.c

167

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

172

state = cs.cs_flags == 0 &&

usr.bin/vi/vi/v_word.c

173

inword(cs.cs_ch) ? INWORD : NOTWORD;

usr.bin/vi/vi/v_word.c

175

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

177

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

179

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

182

if (!inword(cs.cs_ch))

usr.bin/vi/vi/v_word.c

185

if (inword(cs.cs_ch))

usr.bin/vi/vi/v_word.c

192

cs_fspace(sp, &cs))

usr.bin/vi/vi/v_word.c

198

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

199

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_word.c

201

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

212

cs.cs_lno == vp->m_start.lno && cs.cs_cno == vp->m_start.cno) {

usr.bin/vi/vi/v_word.c

218

vp->m_stop.lno = cs.cs_lno;

usr.bin/vi/vi/v_word.c

219

vp->m_stop.cno = cs.cs_cno;

usr.bin/vi/vi/v_word.c

220

if (ISMOTION(vp) && cs.cs_flags == 0)

usr.bin/vi/vi/v_word.c

263

VCS cs;

usr.bin/vi/vi/v_word.c

267

cs.cs_lno = vp->m_start.lno;

usr.bin/vi/vi/v_word.c

268

cs.cs_cno = vp->m_start.cno;

usr.bin/vi/vi/v_word.c

269

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_word.c

278

if (cs.cs_flags == 0 && !isblank(cs.cs_ch)) {

usr.bin/vi/vi/v_word.c

279

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

281

if (cs.cs_flags == 0 && !isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

284

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_word.c

296

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

298

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

300

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

309

if (cs.cs_flags == 0 && cs_prev(sp, &cs))

usr.bin/vi/vi/v_word.c

315

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_word.c

317

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

322

state = cs.cs_flags == 0 &&

usr.bin/vi/vi/v_word.c

323

inword(cs.cs_ch) ? INWORD : NOTWORD;

usr.bin/vi/vi/v_word.c

325

if (cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

327

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

329

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

332

if (!inword(cs.cs_ch))

usr.bin/vi/vi/v_word.c

335

if (inword(cs.cs_ch))

usr.bin/vi/vi/v_word.c

340

if (cs.cs_flags == 0 && cs_prev(sp, &cs))

usr.bin/vi/vi/v_word.c

346

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

347

if (cs_fblank(sp, &cs))

usr.bin/vi/vi/v_word.c

349

if (cs.cs_flags == CS_EOF)

usr.bin/vi/vi/v_word.c

360

cs.cs_lno == vp->m_start.lno && cs.cs_cno == vp->m_start.cno) {

usr.bin/vi/vi/v_word.c

366

vp->m_stop.lno = cs.cs_lno;

usr.bin/vi/vi/v_word.c

367

vp->m_stop.cno = cs.cs_cno;

usr.bin/vi/vi/v_word.c

409

VCS cs;

usr.bin/vi/vi/v_word.c

413

cs.cs_lno = vp->m_start.lno;

usr.bin/vi/vi/v_word.c

414

cs.cs_cno = vp->m_start.cno;

usr.bin/vi/vi/v_word.c

415

if (cs_init(sp, &cs))

usr.bin/vi/vi/v_word.c

425

if (cs.cs_flags == 0 && !isblank(cs.cs_ch)) {

usr.bin/vi/vi/v_word.c

426

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_word.c

428

if (cs.cs_flags == 0 && !isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

431

if (cs_bblank(sp, &cs))

usr.bin/vi/vi/v_word.c

443

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_word.c

445

if (cs.cs_flags == CS_SOF)

usr.bin/vi/vi/v_word.c

447

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

456

if (cs.cs_flags == 0 && cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

462

if (cs_bblank(sp, &cs))

usr.bin/vi/vi/v_word.c

464

if (cs.cs_flags == CS_SOF)

usr.bin/vi/vi/v_word.c

469

state = cs.cs_flags == 0 &&

usr.bin/vi/vi/v_word.c

470

inword(cs.cs_ch) ? INWORD : NOTWORD;

usr.bin/vi/vi/v_word.c

472

if (cs_prev(sp, &cs))

usr.bin/vi/vi/v_word.c

474

if (cs.cs_flags == CS_SOF)

usr.bin/vi/vi/v_word.c

476

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

479

if (!inword(cs.cs_ch))

usr.bin/vi/vi/v_word.c

482

if (inword(cs.cs_ch))

usr.bin/vi/vi/v_word.c

487

if (cs.cs_flags == 0 && cs_next(sp, &cs))

usr.bin/vi/vi/v_word.c

493

if (cs.cs_flags != 0 || isblank(cs.cs_ch))

usr.bin/vi/vi/v_word.c

494

if (cs_bblank(sp, &cs))

usr.bin/vi/vi/v_word.c

496

if (cs.cs_flags == CS_SOF)

usr.bin/vi/vi/v_word.c

501

ret: if (cs.cs_lno == vp->m_start.lno && cs.cs_cno == vp->m_start.cno) {

usr.bin/vi/vi/v_word.c

507

vp->m_stop.lno = cs.cs_lno;

usr.bin/vi/vi/v_word.c

508

vp->m_stop.cno = cs.cs_cno;

usr.sbin/eigrpctl/eigrpctl.c

823

struct ctl_stats *cs;

usr.sbin/eigrpctl/eigrpctl.c

829

cs = imsg->data;

usr.sbin/eigrpctl/eigrpctl.c

831

if (res->family != AF_UNSPEC && res->family != cs->af)

usr.sbin/eigrpctl/eigrpctl.c

833

if (res->as != 0 && res->as != cs->as)

usr.sbin/eigrpctl/eigrpctl.c

837

af_name(cs->af), cs->as);

usr.sbin/eigrpctl/eigrpctl.c

839

cs->stats.hellos_sent, cs->stats.hellos_recv);

usr.sbin/eigrpctl/eigrpctl.c

841

cs->stats.updates_sent, cs->stats.updates_recv);

usr.sbin/eigrpctl/eigrpctl.c

843

cs->stats.queries_sent, cs->stats.queries_recv);

usr.sbin/eigrpctl/eigrpctl.c

845

cs->stats.replies_sent, cs->stats.replies_recv);

usr.sbin/eigrpctl/eigrpctl.c

847

cs->stats.acks_sent, cs->stats.acks_recv);

usr.sbin/eigrpctl/eigrpctl.c

849

cs->stats.squeries_sent, cs->stats.squeries_recv);

usr.sbin/eigrpctl/eigrpctl.c

851

cs->stats.sreplies_sent, cs->stats.sreplies_recv);

usr.sbin/httpd/control.c

104

control_listen(struct control_sock *cs)

usr.sbin/httpd/control.c

106

if (cs->cs_name == NULL)

usr.sbin/httpd/control.c

109

if (listen(cs->cs_fd, CONTROL_BACKLOG) == -1) {

usr.sbin/httpd/control.c

114

event_set(&cs->cs_ev, cs->cs_fd, EV_READ,

usr.sbin/httpd/control.c

115

control_accept, cs);

usr.sbin/httpd/control.c

116

event_add(&cs->cs_ev, NULL);

usr.sbin/httpd/control.c

117

evtimer_set(&cs->cs_evt, control_accept, cs);

usr.sbin/httpd/control.c

123

control_cleanup(struct control_sock *cs)

usr.sbin/httpd/control.c

125

if (cs->cs_name == NULL)

usr.sbin/httpd/control.c

127

event_del(&cs->cs_ev);

usr.sbin/httpd/control.c

128

event_del(&cs->cs_evt);

usr.sbin/httpd/control.c

138

struct control_sock *cs = arg;

usr.sbin/httpd/control.c

140

event_add(&cs->cs_ev, NULL);

usr.sbin/httpd/control.c

154

event_del(&cs->cs_ev);

usr.sbin/httpd/control.c

155

evtimer_add(&cs->cs_evt, &evtpause);

usr.sbin/httpd/control.c

176

c->iev.data = cs; /* proc.c cheats (reuses the handler) */

usr.sbin/httpd/control.c

178

c->iev.handler, cs);

usr.sbin/httpd/control.c

198

control_close(int fd, struct control_sock *cs)

usr.sbin/httpd/control.c

214

if (evtimer_pending(&cs->cs_evt, NULL)) {

usr.sbin/httpd/control.c

215

evtimer_del(&cs->cs_evt);

usr.sbin/httpd/control.c

216

event_add(&cs->cs_ev, NULL);

usr.sbin/httpd/control.c

225

struct control_sock *cs = arg;

usr.sbin/httpd/control.c

230

struct httpd *env = cs->cs_env;

usr.sbin/httpd/control.c

239

control_close(fd, cs);

usr.sbin/httpd/control.c

246

control_close(fd, cs);

usr.sbin/httpd/control.c

253

control_close(fd, cs);

usr.sbin/httpd/control.c

264

control_close(fd, cs);

usr.sbin/httpd/control.c

44

control_init(struct privsep *ps, struct control_sock *cs)

usr.sbin/httpd/control.c

51

if (cs->cs_name == NULL)

usr.sbin/httpd/control.c

60

if (strlcpy(sun.sun_path, cs->cs_name,

usr.sbin/httpd/control.c

62

log_warn("%s: %s name too long", __func__, cs->cs_name);

usr.sbin/httpd/control.c

67

if (unlink(cs->cs_name) == -1)

usr.sbin/httpd/control.c

69

log_warn("%s: unlink %s", __func__, cs->cs_name);

usr.sbin/httpd/control.c

74

if (cs->cs_restricted) {

usr.sbin/httpd/control.c

83

log_warn("%s: bind: %s", __func__, cs->cs_name);

usr.sbin/httpd/control.c

90

if (chmod(cs->cs_name, mode) == -1) {

usr.sbin/httpd/control.c

93

(void)unlink(cs->cs_name);

usr.sbin/httpd/control.c

97

cs->cs_fd = fd;

usr.sbin/httpd/control.c

98

cs->cs_env = env;

usr.sbin/ldapd/btree.c

1315

char *cs, size_t *cn)

usr.sbin/ldapd/btree.c

1319

bcopy(s2, cs, n2);

usr.sbin/ldapd/btree.c

1320

bcopy(s1, cs + n2, n1);

usr.sbin/ldapd/btree.c

1322

bcopy(s1, cs, n1);

usr.sbin/ldapd/btree.c

1323

bcopy(s2, cs + n1, n2);

usr.sbin/ldapd/btree.c

298

char *s2, size_t n2, char *cs, size_t *cn);

usr.sbin/ldapd/control.c

102

if (listen(cs->cs_fd, CONTROL_BACKLOG) == -1)

usr.sbin/ldapd/control.c

105

event_set(&cs->cs_ev, cs->cs_fd, EV_READ,

usr.sbin/ldapd/control.c

106

control_accept, cs);

usr.sbin/ldapd/control.c

107

event_add(&cs->cs_ev, NULL);

usr.sbin/ldapd/control.c

108

evtimer_set(&cs->cs_evt, control_accept, cs);

usr.sbin/ldapd/control.c

112

control_cleanup(struct control_sock *cs)

usr.sbin/ldapd/control.c

114

if (cs->cs_name == NULL)

usr.sbin/ldapd/control.c

116

event_del(&cs->cs_ev);

usr.sbin/ldapd/control.c

117

event_del(&cs->cs_evt);

usr.sbin/ldapd/control.c

123

struct control_sock *cs = arg;

usr.sbin/ldapd/control.c

129

event_add(&cs->cs_ev, NULL);

usr.sbin/ldapd/control.c

143

event_del(&cs->cs_ev);

usr.sbin/ldapd/control.c

144

evtimer_add(&cs->cs_evt, &evtpause);

usr.sbin/ldapd/control.c

158

imsgev_init(&c->iev, connfd, cs, control_imsgev, control_needfd);

usr.sbin/ldapd/control.c

175

control_close(int fd, struct control_sock *cs)

usr.sbin/ldapd/control.c

189

if (evtimer_pending(&cs->cs_evt, NULL)) {

usr.sbin/ldapd/control.c

190

evtimer_del(&cs->cs_evt);

usr.sbin/ldapd/control.c

191

event_add(&cs->cs_ev, NULL);

usr.sbin/ldapd/control.c

230

struct control_sock *cs;

usr.sbin/ldapd/control.c

234

cs = iev->data;

usr.sbin/ldapd/control.c

243

control_close(fd, cs);

usr.sbin/ldapd/control.c

252

control_close(fd, cs);

usr.sbin/ldapd/control.c

278

control_close_any(struct control_sock *cs)

usr.sbin/ldapd/control.c

285

control_close(c->iev.ibuf.fd, cs);

usr.sbin/ldapd/control.c

50

control_init(struct control_sock *cs)

usr.sbin/ldapd/control.c

56

if (cs->cs_name == NULL)

usr.sbin/ldapd/control.c

64

if (strlcpy(sun.sun_path, cs->cs_name,

usr.sbin/ldapd/control.c

71

if (unlink(cs->cs_name) == -1 && errno != ENOENT)

usr.sbin/ldapd/control.c

74

if (cs->cs_restricted) {

usr.sbin/ldapd/control.c

88

if (chmod(cs->cs_name, mode) == -1) {

usr.sbin/ldapd/control.c

89

(void)unlink(cs->cs_name);

usr.sbin/ldapd/control.c

93

cs->cs_fd = fd;

usr.sbin/ldapd/control.c

97

control_listen(struct control_sock *cs)

usr.sbin/ldapd/control.c

99

if (cs->cs_name == NULL)

usr.sbin/npppd/npppd/control.c

102

(void)unlink(cs->cs_name);

usr.sbin/npppd/npppd/control.c

107

cs->cs_fd = fd;

usr.sbin/npppd/npppd/control.c

113

control_listen(struct control_sock *cs)

usr.sbin/npppd/npppd/control.c

115

if (cs->cs_name == NULL)

usr.sbin/npppd/npppd/control.c

118

if (listen(cs->cs_fd, CONTROL_BACKLOG) == -1) {

usr.sbin/npppd/npppd/control.c

123

event_set(&cs->cs_ev, cs->cs_fd, EV_READ,

usr.sbin/npppd/npppd/control.c

124

control_accept, cs);

usr.sbin/npppd/npppd/control.c

125

event_add(&cs->cs_ev, NULL);

usr.sbin/npppd/npppd/control.c

126

evtimer_set(&cs->cs_evt, control_accept, cs);

usr.sbin/npppd/npppd/control.c

132

control_cleanup(struct control_sock *cs)

usr.sbin/npppd/npppd/control.c

136

if (cs->cs_name == NULL)

usr.sbin/npppd/npppd/control.c

140

control_close(c->iev.ibuf.fd, cs);

usr.sbin/npppd/npppd/control.c

142

event_del(&cs->cs_ev);

usr.sbin/npppd/npppd/control.c

143

event_del(&cs->cs_evt);

usr.sbin/npppd/npppd/control.c

144

(void)unlink(cs->cs_name);

usr.sbin/npppd/npppd/control.c

151

struct control_sock *cs = (struct control_sock *)arg;

usr.sbin/npppd/npppd/control.c

157

event_add(&cs->cs_ev, NULL);

usr.sbin/npppd/npppd/control.c

171

event_del(&cs->cs_ev);

usr.sbin/npppd/npppd/control.c

172

evtimer_add(&cs->cs_evt, &evtpause);

usr.sbin/npppd/npppd/control.c

183

if ((c->ctx = npppd_ctl_create(cs->cs_ctx)) == NULL) {

usr.sbin/npppd/npppd/control.c

200

c->iev.data = cs;

usr.sbin/npppd/npppd/control.c

202

c->iev.handler, cs);

usr.sbin/npppd/npppd/control.c

222

control_close(int fd, struct control_sock *cs)

usr.sbin/npppd/npppd/control.c

238

if (evtimer_pending(&cs->cs_evt, NULL)) {

usr.sbin/npppd/npppd/control.c

239

evtimer_del(&cs->cs_evt);

usr.sbin/npppd/npppd/control.c

240

event_add(&cs->cs_ev, NULL);

usr.sbin/npppd/npppd/control.c

250

struct control_sock *cs = (struct control_sock *)arg;

usr.sbin/npppd/npppd/control.c

263

control_close(fd, cs);

usr.sbin/npppd/npppd/control.c

274

control_close(fd, cs);

usr.sbin/npppd/npppd/control.c

281

control_close(fd, cs);

usr.sbin/npppd/npppd/control.c

288

if (cs->cs_restricted || (c->flags & CTL_CONN_LOCKED)) {

usr.sbin/npppd/npppd/control.c

294

control_close(fd, cs);

usr.sbin/npppd/npppd/control.c

54

control_init(struct control_sock *cs)

usr.sbin/npppd/npppd/control.c

60

if (cs->cs_name == NULL)

usr.sbin/npppd/npppd/control.c

69

if (strlcpy(sun.sun_path, cs->cs_name,

usr.sbin/npppd/npppd/control.c

71

log_warn("control_init: %s name too long", cs->cs_name);

usr.sbin/npppd/npppd/control.c

76

if (unlink(cs->cs_name) == -1)

usr.sbin/npppd/npppd/control.c

78

log_warn("control_init: unlink %s", cs->cs_name);

usr.sbin/npppd/npppd/control.c

83

if (cs->cs_restricted) {

usr.sbin/npppd/npppd/control.c

92

log_warn("control_init: bind: %s", cs->cs_name);

usr.sbin/npppd/npppd/control.c

99

if (chmod(cs->cs_name, mode) == -1) {

usr.sbin/nsd/remote.c

2542

struct cookie_secret const* cs = &nsd->cookie_secrets[i];

usr.sbin/nsd/remote.c

2543

ssize_t const len = hex_ntop(cs->cookie_secret, NSD_COOKIE_SECRET_SIZE,

usr.sbin/nsd/remote.c

2692

struct cookie_secret const* cs = &nsd->cookie_secrets[i];

usr.sbin/nsd/remote.c

2693

ssize_t const len = hex_ntop(cs->cookie_secret, NSD_COOKIE_SECRET_SIZE,

usr.sbin/ntpd/control.c

315

build_show_status(struct ctl_show_status *cs)

usr.sbin/ntpd/control.c

320

cs->peercnt = cs->valid_peers = 0;

usr.sbin/ntpd/control.c

321

cs->sensorcnt = cs->valid_sensors = 0;

usr.sbin/ntpd/control.c

324

cs->peercnt++;

usr.sbin/ntpd/control.c

326

cs->valid_peers++;

usr.sbin/ntpd/control.c

329

cs->sensorcnt++;

usr.sbin/ntpd/control.c

331

cs->valid_sensors++;

usr.sbin/ntpd/control.c

334

cs->synced = conf->status.synced;

usr.sbin/ntpd/control.c

335

cs->stratum = conf->status.stratum;

usr.sbin/ntpd/control.c

336

cs->clock_offset = getoffset() * 1000.0;

usr.sbin/ntpd/control.c

337

cs->constraints = !TAILQ_EMPTY(&conf->constraints);

usr.sbin/ntpd/control.c

338

cs->constraint_median = conf->constraint_median;

usr.sbin/ntpd/control.c

339

cs->constraint_last = conf->constraint_last;

usr.sbin/ntpd/control.c

340

cs->constraint_errors = conf->constraint_errors;

usr.sbin/ntpd/control.c

425

build_show_sensor(struct ctl_show_sensor *cs, struct ntp_sensor *s)

usr.sbin/ntpd/control.c

436

snprintf(cs->sensor_desc, sizeof(cs->sensor_desc),

usr.sbin/ntpd/control.c

446

cs->syncedto = 1;

usr.sbin/ntpd/control.c

448

cs->syncedto = 0;

usr.sbin/ntpd/control.c

450

cs->weight = s->weight;

usr.sbin/ntpd/control.c

451

cs->good = s->update.good;

usr.sbin/ntpd/control.c

452

cs->stratum = s->offsets[shift].status.stratum;

usr.sbin/ntpd/control.c

453

cs->next = s->next - now < 0 ? 0 : s->next - now;

usr.sbin/ntpd/control.c

454

cs->poll = SENSOR_QUERY_INTERVAL;

usr.sbin/ntpd/control.c

455

cs->offset = s->offsets[shift].offset * 1000.0;

usr.sbin/ntpd/control.c

456

cs->correction = (double)s->correction / 1000.0;

usr.sbin/ntpd/sensors.c

115

struct ntp_conf_sensor *cs;

usr.sbin/ntpd/sensors.c

123

for (cs = TAILQ_FIRST(&conf->ntp_conf_sensors); cs != NULL &&

usr.sbin/ntpd/sensors.c

124

strcmp(cs->device, dxname) && strcmp(cs->device, "*");

usr.sbin/ntpd/sensors.c

125

cs = TAILQ_NEXT(cs, entry))

usr.sbin/ntpd/sensors.c

127

if (cs == NULL)

usr.sbin/ntpd/sensors.c

134

s->weight = cs->weight;

usr.sbin/ntpd/sensors.c

135

s->correction = cs->correction;

usr.sbin/ntpd/sensors.c

136

s->stratum = cs->stratum - 1;

usr.sbin/ntpd/sensors.c

137

s->trusted = cs->trusted;

usr.sbin/ntpd/sensors.c

142

if (cs->refstr == NULL)

usr.sbin/ntpd/sensors.c

146

strncpy((char *)&s->refid, cs->refstr, sizeof(s->refid));

usr.sbin/relayctl/relayctl.c

293

struct ctl_status cs;

usr.sbin/relayctl/relayctl.c

295

memcpy(&cs, imsg->data, sizeof(cs));

usr.sbin/relayctl/relayctl.c

296

printf("\tid: %u\n", cs.id);

usr.sbin/relayctl/relayctl.c

298

switch (cs.up) {

usr.sbin/relayd/control.c

104

control_listen(struct control_sock *cs)

usr.sbin/relayd/control.c

106

if (cs->cs_name == NULL)

usr.sbin/relayd/control.c

109

if (listen(cs->cs_fd, CONTROL_BACKLOG) == -1) {

usr.sbin/relayd/control.c

114

event_set(&cs->cs_ev, cs->cs_fd, EV_READ,

usr.sbin/relayd/control.c

115

control_accept, cs);

usr.sbin/relayd/control.c

116

event_add(&cs->cs_ev, NULL);

usr.sbin/relayd/control.c

117

evtimer_set(&cs->cs_evt, control_accept, cs);

usr.sbin/relayd/control.c

123

control_cleanup(struct control_sock *cs)

usr.sbin/relayd/control.c

125

if (cs->cs_name == NULL)

usr.sbin/relayd/control.c

127

event_del(&cs->cs_ev);

usr.sbin/relayd/control.c

128

event_del(&cs->cs_evt);

usr.sbin/relayd/control.c

138

struct control_sock *cs = arg;

usr.sbin/relayd/control.c

140

event_add(&cs->cs_ev, NULL);

usr.sbin/relayd/control.c

154

event_del(&cs->cs_ev);

usr.sbin/relayd/control.c

155

evtimer_add(&cs->cs_evt, &evtpause);

usr.sbin/relayd/control.c

177

c->iev.data = cs; /* proc.c cheats (reuses the handler) */

usr.sbin/relayd/control.c

179

c->iev.handler, cs);

usr.sbin/relayd/control.c

199

control_close(int fd, struct control_sock *cs)

usr.sbin/relayd/control.c

215

if (evtimer_pending(&cs->cs_evt, NULL)) {

usr.sbin/relayd/control.c

216

evtimer_del(&cs->cs_evt);

usr.sbin/relayd/control.c

217

event_add(&cs->cs_ev, NULL);

usr.sbin/relayd/control.c

226

struct control_sock *cs = arg;

usr.sbin/relayd/control.c

232

struct relayd *env = cs->cs_env;

usr.sbin/relayd/control.c

242

control_close(fd, cs);

usr.sbin/relayd/control.c

249

control_close(fd, cs);

usr.sbin/relayd/control.c

256

control_close(fd, cs);

usr.sbin/relayd/control.c

267

control_close(fd, cs);

usr.sbin/relayd/control.c

44

control_init(struct privsep *ps, struct control_sock *cs)

usr.sbin/relayd/control.c

51

if (cs->cs_name == NULL)

usr.sbin/relayd/control.c

60

if (strlcpy(sun.sun_path, cs->cs_name,

usr.sbin/relayd/control.c

62

log_warn("%s: %s name too long", __func__, cs->cs_name);

usr.sbin/relayd/control.c

67

if (unlink(cs->cs_name) == -1)

usr.sbin/relayd/control.c

69

log_warn("%s: unlink %s", __func__, cs->cs_name);

usr.sbin/relayd/control.c

74

if (cs->cs_restricted) {

usr.sbin/relayd/control.c

83

log_warn("%s: bind: %s", __func__, cs->cs_name);

usr.sbin/relayd/control.c

90

if (chmod(cs->cs_name, mode) == -1) {

usr.sbin/relayd/control.c

93

(void)unlink(cs->cs_name);

usr.sbin/relayd/control.c

97

cs->cs_fd = fd;

usr.sbin/relayd/control.c

98

cs->cs_env = env;

usr.sbin/unbound/daemon/remote.c

3689

struct cookie_secret const* cs = &cookie_secrets->

usr.sbin/unbound/daemon/remote.c

3691

ssize_t const len = hex_ntop(cs->cookie_secret,

usr.sbin/unbound/daemon/remote.c

3845

struct cookie_secret const* cs = &cookie_secrets->

usr.sbin/unbound/daemon/remote.c

3847

ssize_t const len = hex_ntop(cs->cookie_secret,

usr.sbin/unbound/services/cache/infra.c

1124

char ts[12], cs[12], ip[128];

usr.sbin/unbound/services/cache/infra.c

1128

sldns_wire2str_class_buf(qinfo->qclass, cs, sizeof(cs));

usr.sbin/unbound/services/cache/infra.c

1133

verbose(VERB_OPS, "ratelimit exceeded %s %d query %s %s %s from %s", buf, lim, qnm, cs, ts, ip);

usr.sbin/unbound/services/cache/infra.c

1135

verbose(VERB_OPS, "ratelimit exceeded %s %d query %s %s %s", buf, lim, qnm, cs, ts);

usr.sbin/unbound/util/net_help.c

558

const char *ts, *cs;

usr.sbin/unbound/util/net_help.c

576

cs = sldns_lookup_by_id(sldns_rr_classes, (int)dclass)->name;

usr.sbin/unbound/util/net_help.c

579

cs = c;

usr.sbin/unbound/util/net_help.c

581

log_info("%s %s %s %s", str, buf, ts, cs);

usr.sbin/unbound/util/net_help.c

589

const char *ts, *cs;

usr.sbin/unbound/util/net_help.c

605

cs = sldns_lookup_by_id(sldns_rr_classes, (int)dclass)->name;

usr.sbin/unbound/util/net_help.c

608

cs = c;

usr.sbin/unbound/util/net_help.c

611

log_query("%s %s %s %s", str, buf, ts, cs);

usr.sbin/unbound/util/net_help.c

612

else log_info("%s %s %s %s", str, buf, ts, cs);

usr.sbin/vmd/control.c

178

control_init(struct privsep *ps, struct control_sock *cs)

usr.sbin/vmd/control.c

184

if (cs->cs_name == NULL)

usr.sbin/vmd/control.c

193

if (strlcpy(sun.sun_path, cs->cs_name,

usr.sbin/vmd/control.c

195

log_warn("%s: %s name too long", __func__, cs->cs_name);

usr.sbin/vmd/control.c

200

if (unlink(cs->cs_name) == -1)

usr.sbin/vmd/control.c

202

log_warn("%s: unlink %s", __func__, cs->cs_name);

usr.sbin/vmd/control.c

207

if (cs->cs_restricted) {

usr.sbin/vmd/control.c

216

log_warn("%s: bind: %s", __func__, cs->cs_name);

usr.sbin/vmd/control.c

223

if (chmod(cs->cs_name, mode) == -1) {

usr.sbin/vmd/control.c

226

(void)unlink(cs->cs_name);

usr.sbin/vmd/control.c

230

cs->cs_fd = fd;

usr.sbin/vmd/control.c

231

cs->cs_env = ps;

usr.sbin/vmd/control.c

237

control_reset(struct control_sock *cs)

usr.sbin/vmd/control.c

240

if (chown(cs->cs_name, cs->cs_uid, cs->cs_gid) == -1)

usr.sbin/vmd/control.c

247

control_listen(struct control_sock *cs)

usr.sbin/vmd/control.c

249

if (cs->cs_name == NULL)

usr.sbin/vmd/control.c

252

if (listen(cs->cs_fd, CONTROL_BACKLOG) == -1) {

usr.sbin/vmd/control.c

257

event_set(&cs->cs_ev, cs->cs_fd, EV_READ, control_accept, cs);

usr.sbin/vmd/control.c

258

event_add(&cs->cs_ev, NULL);

usr.sbin/vmd/control.c

259

evtimer_set(&cs->cs_evt, control_accept, cs);

usr.sbin/vmd/control.c

267

struct control_sock *cs = arg;

usr.sbin/vmd/control.c

273

event_add(&cs->cs_ev, NULL);

usr.sbin/vmd/control.c

287

event_del(&cs->cs_ev);

usr.sbin/vmd/control.c

288

evtimer_add(&cs->cs_evt, &evtpause);

usr.sbin/vmd/control.c

318

c->iev.data = cs;

usr.sbin/vmd/control.c

340

control_close(int fd, struct control_sock *cs)

usr.sbin/vmd/control.c

365

if (evtimer_pending(&cs->cs_evt, NULL)) {

usr.sbin/vmd/control.c

366

evtimer_del(&cs->cs_evt);

usr.sbin/vmd/control.c

367

event_add(&cs->cs_ev, NULL);

usr.sbin/vmd/control.c

376

struct control_sock *cs = arg;

usr.sbin/vmd/control.c

377

struct privsep *ps = cs->cs_env;

usr.sbin/vmd/control.c

393

control_close(fd, cs);

usr.sbin/vmd/control.c

399

control_close(fd, cs);

usr.sbin/vmd/control.c

406

control_close(fd, cs);

usr.sbin/vmd/control.c

456

control_close(fd, cs);

usr.sbin/vmd/control.c

483

control_close(fd, cs);

usr.sbin/vmd/control.c

490

control_close(fd, cs);

usr.sbin/vmd/control.c

507

control_close(fd, cs);

usr.sbin/vmd/control.c

521

control_close(fd, cs);

usr.sbin/vmd/x86_mmio.c

368

uint64_t cr0, cr4, cs, efer, rflags;

usr.sbin/vmd/x86_mmio.c

376

cs = vrs->vrs_sregs[VCPU_REGS_CS].vsi_ar;

usr.sbin/vmd/x86_mmio.c

382

if (cs & CS_L) {

usr.sbin/vmd/x86_mmio.c

384

if (!(cs & CS_D))

usr.sbin/vmd/x86_mmio.c

390

if (cs & CS_D) /* XXX Add Compat32 mode */

usr.sbin/vmd/x86_mmio.c

397

if (cs & CS_D)