MIPS_INT_MASK_1
if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
|MIPS_INT_MASK_0|MIPS_INT_MASK_1
| MIPS_INT_MASK_1
| MIPS_INT_MASK_1
| MIPS_INT_MASK_1
(*platform->set_intr)(MIPS_INT_MASK_1, jazzio_intr, ARC_INTPRI_JAZZ);
return MIPS_INT_MASK_1;
if (pending & MIPS_INT_MASK_1) {
#define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
#define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
MIPS_INT_MASK_1 |
MIPS_INT_MASK_1 |
if (ipending & MIPS_INT_MASK_1) {
MIPS_INT_MASK_1 |
MIPS_INT_MASK_1 |
MIPS_INT_MASK_1 |
if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) {
if (ipending & MIPS_INT_MASK_1)
| MIPS_INT_MASK_0 | MIPS_INT_MASK_1
| MIPS_INT_MASK_0 | MIPS_INT_MASK_1
| MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
| MIPS_INT_MASK_1 | MIPS_INT_MASK_4
if (ipending & MIPS_INT_MASK_1)
if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
if (ipending & MIPS_INT_MASK_1) {
| MIPS_INT_MASK_1,
if (ipending & MIPS_INT_MASK_1) {
MIPS_INT_MASK_1 |
| MIPS_INT_MASK_1 | MIPS_INT_MASK_2
| MIPS_INT_MASK_1 | MIPS_INT_MASK_2,
MIPS_INT_MASK_1, /* USB */
MIPS_INT_MASK_1 | /* USB */
MIPS_INT_MASK_1 | /* USB */
MIPS_INT_MASK_1 | /* USB */
} else if (ipending & MIPS_INT_MASK_1) {
| MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
| MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
KASSERT(pending == MIPS_INT_MASK_1);
HANDLE_INTR(SYS_INTR_SCSI, MIPS_INT_MASK_1);
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
if (ipending & MIPS_INT_MASK_1) {
| MIPS_INT_MASK_1,
| MIPS_INT_MASK_1
if (ipending & MIPS_INT_MASK_1) {
| MIPS_INT_MASK_1,
| MIPS_INT_MASK_1
if (ipending & MIPS_INT_MASK_1) {
| MIPS_INT_MASK_1,
| MIPS_INT_MASK_1
if (ipending & MIPS_INT_MASK_1) {
#define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK)
#define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
CALLINTR(SYS_DEV_LANCE, MIPS_INT_MASK_1);
mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK), MIPS_INT_MASK_1);
if (ipending & MIPS_INT_MASK_1) {
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
if (ipending & MIPS_INT_MASK_1) {
if ((ipending & MIPS_INT_MASK_1) && old_buscycle > (tick+49) * 25) {
mask = MIPS_INT_MASK_1;
if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) {
if (ipending & MIPS_INT_MASK_1) {
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
if (ipending & MIPS_INT_MASK_1) {
if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
| MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
| MIPS_INT_MASK_1 | MIPS_INT_MASK_4
if (pending & MIPS_INT_MASK_1) {
[IPL_VM] = MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0|
MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_INT_MASK_1|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,