syscon_read_4
return syscon_read_4(sc->sc_syscon, reg);
syscon_read_4((reg)->syscon, (off))
syscon_read_4((sc)->sc_syscon, (reg))
syscon_read_4(syscon, (reg))
status = syscon_read_4(rm, RK3399_GRF_SOC_STATUS1);
status = syscon_read_4(rm, RK3399_GRF_SOC_STATUS1);
status = syscon_read_4(rm, RK3399_GRF_SOC_STATUS1);
val = syscon_read_4(sc->sc_grf, mux->reg);
if (syscon_read_4(sc->sc_grf,
syscon_read_4((sc)->sc_syscon, (sc)->sc_regbase + (reg))
reg = syscon_read_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id));
reg = syscon_read_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id));
val = syscon_read_4(sc->sc_pmureg, USBDRD_PHY_CTRL(phy->phy_index));
val = syscon_read_4(sc->sc_sysreg, USB20PHY_CFG);
val = syscon_read_4(sc->sc_pmureg, USBHOST_PHY_CTRL);
reg = syscon_read_4(sc->syscon, EMAC_CLK_REG);
uint32_t cfgchip_reg3 = syscon_read_4(syscon, AM18XX_ACLK_CFGCHIP3);
val = syscon_read_4(sc->sc_syscon, AM18XX_CFGCHIP2);
val = syscon_read_4(sc->sc_syscon, AM18XX_CFGCHIP2);
uint32_t val = syscon_read_4(sc->sc_syscon, AM18XX_CFGCHIP2);
while ((syscon_read_4(sc->sc_syscon, AM18XX_CFGCHIP2) &
uint32_t val = syscon_read_4(sc->sc_syscon, AM18XX_CFGCHIP2);
rev = __BIT(__SHIFTOUT(syscon_read_4(ti_opp_syscon, AM33XX_REV_OFFSET), AM33XX_REV_MASK));
efuse = __SHIFTOUT(syscon_read_4(ti_opp_syscon, AM33XX_EFUSE_OFFSET), AM33XX_EFUSE_MASK);
val = syscon_read_4(sc->sc_syscon, reg);
val = syscon_read_4(sc->sc_syscon, reg);
val = syscon_read_4(sc->sc_syscon, CLK_621_TRUE);
val = syscon_read_4(sc->sc_syscon, CLK_621_TRUE);
val = syscon_read_4(sc->sc_syscon, ARM_CLK_CTRL);
val = syscon_read_4(sc->sc_syscon, reg);
#define SCRD4(sc, off) syscon_read_4((sc), (off))
uint32_t val = syscon_read_4(jh_sc->sc_syscon, reg);
const uint32_t old = syscon_read_4(sc->sc_syscon, off);