Symbol: ctl
sbin/mount_portal/activate.c
112
void *ctl = NULL;
sbin/mount_portal/activate.c
138
ctl = malloc(cmsgsize);
sbin/mount_portal/activate.c
139
if (ctl == NULL) {
sbin/mount_portal/activate.c
143
memset(ctl, 0, cmsgsize);
sbin/mount_portal/activate.c
145
cmsg = (struct cmsghdr *) ctl;
sbin/mount_portal/activate.c
153
msg.msg_control = ctl;
sbin/mount_portal/activate.c
176
if (ctl != NULL)
sbin/mount_portal/activate.c
177
free(ctl);
sys/arch/alpha/pci/dwlpx.c
184
uint32_t ctl;
sys/arch/alpha/pci/dwlpx.c
199
sizeof (ctl)) != 0) {
sys/arch/alpha/pci/dwlpx.c
225
ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
234
} else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
sys/arch/alpha/pci/dwlpx.c
266
ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
sys/arch/alpha/pci/dwlpx.c
267
ctl &= 0x0fffffff;
sys/arch/alpha/pci/dwlpx.c
268
ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
sys/arch/alpha/pci/dwlpx.c
273
ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
sys/arch/alpha/pci/dwlpx.c
278
ctl |= PCIA_CTL_3UP;
sys/arch/alpha/pci/dwlpx.c
280
ctl |= PCIA_CTL_CUTENA;
sys/arch/alpha/pci/dwlpx.c
286
ctl |= PCIA_CTL_SG32K;
sys/arch/alpha/pci/dwlpx.c
288
ctl |= PCIA_CTL_SG128K;
sys/arch/alpha/pci/dwlpx.c
290
ctl |= PCIA_CTL_SG32K;
sys/arch/alpha/pci/dwlpx.c
292
REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
sys/arch/alpha/pci/dwlpx.c
80
uint32_t ctl;
sys/arch/alpha/pci/dwlpx.c
91
if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
sys/arch/alpha/pci/mcpcia.c
132
uint32_t ctl;
sys/arch/alpha/pci/mcpcia.c
163
ctl = REGVAL(MCPCIA_PCI_REV(ccp));
sys/arch/alpha/pci/mcpcia.c
166
" CAP Revision %d\n", HORSE_REV(ctl),
sys/arch/alpha/pci/mcpcia.c
167
(SADDLE_TYPE(ctl) & 1)? "Right": "Left", SADDLE_REV(ctl),
sys/arch/alpha/pci/mcpcia.c
168
CAP_REV(ctl));
sys/arch/alpha/pci/mcpcia.c
244
uint32_t ctl;
sys/arch/alpha/pci/mcpcia.c
272
ctl = REGVAL(MCPCIA_WHOAMI(ccp));
sys/arch/alpha/pci/mcpcia.c
273
mcbus_primary.mcbus_cpu_mid = MCBUS_CPU_MID(ctl);
sys/arch/alpha/pci/mcpcia.c
274
if ((MCBUS_CPU_INFO(ctl) & CPU_Fill_Err) == 0 &&
sys/arch/alpha/pci/mcpcia.c
277
MCBUS_CPU_INFO(ctl) & CPU_BCacheMask;
sys/arch/alpha/pci/mcpcia.c
300
volatile uint32_t ctl;
sys/arch/alpha/pci/mcpcia.c
317
ctl = REGVAL(MCPCIA_INT_MASK0(ccp));
sys/arch/alpha/pci/mcpcia.c
318
ctl |= MCPCIA_GEN_IENABL;
sys/arch/alpha/pci/mcpcia.c
319
REGVAL(MCPCIA_INT_MASK0(ccp)) = ctl;
sys/arch/alpha/pci/mcpcia.c
323
ctl = REGVAL(MCPCIA_INT_MASK0(ccp));
sys/arch/amiga/amiga/custom.h
170
unsigned short ctl;
sys/arch/arc/dev/pccons.c
1778
capchar[0] = scan_codes[dt].ctl[0];
sys/arch/arc/dev/pccons.c
1806
more_chars = scan_codes[dt].ctl;
sys/arch/arc/dev/pccons.c
778
map[i].ctl[KB_CODE_SIZE-1] ||
sys/arch/arc/include/pccons.h
34
char ctl[KB_CODE_SIZE];
sys/arch/arm/apple/apple_pcie.c
470
pcireg_t ctl;
sys/arch/arm/apple/apple_pcie.c
476
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/apple/apple_pcie.c
477
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/apple/apple_pcie.c
478
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/apple/apple_pcie.c
480
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/apple/apple_pcie.c
481
ctl &= ~PCI_MSI_CTL_MME_MASK;
sys/arch/arm/apple/apple_pcie.c
482
ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
sys/arch/arm/apple/apple_pcie.c
483
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/apple/apple_pcie.c
488
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/apple/apple_pcie.c
489
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
sys/arch/arm/apple/apple_pcie.c
500
ctl |= PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/apple/apple_pcie.c
501
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/apple/apple_pcie.c
510
pcireg_t ctl;
sys/arch/arm/apple/apple_pcie.c
516
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/apple/apple_pcie.c
517
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/apple/apple_pcie.c
518
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/apple/apple_pcie.c
528
pcireg_t ctl;
sys/arch/arm/apple/apple_pcie.c
535
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/apple/apple_pcie.c
536
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/arch/arm/apple/apple_pcie.c
537
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/apple/apple_pcie.c
554
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/apple/apple_pcie.c
555
ctl |= PCI_MSIX_CTL_ENABLE;
sys/arch/arm/apple/apple_pcie.c
556
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/apple/apple_pcie.c
565
pcireg_t ctl;
sys/arch/arm/apple/apple_pcie.c
571
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/apple/apple_pcie.c
572
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/arch/arm/apple/apple_pcie.c
573
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/at91/at91emac.c
211
uint32_t imr, isr, ctl;
sys/arch/arm/at91/at91emac.c
232
ctl = EMAC_READ(ETH_CTL); // get current control register value
sys/arch/arm/at91/at91emac.c
233
EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
sys/arch/arm/at91/at91emac.c
235
EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
sys/arch/arm/at91/at91emac.c
759
uint32_t ctl = EMAC_READ(ETH_CTL);
sys/arch/arm/at91/at91emac.c
763
EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
sys/arch/arm/at91/at91emac.c
863
EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
sys/arch/arm/broadcom/bcm2835_cm.c
137
bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div)
sys/arch/arm/broadcom/bcm2835_cm.c
174
ctl &= ~CM_CTL_PASSWD;
sys/arch/arm/broadcom/bcm2835_cm.c
175
ctl |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);
sys/arch/arm/broadcom/bcm2835_cm.c
195
CM_WRITE(sc, ctlreg, ctl & ~CM_CTL_ENAB);
sys/arch/arm/broadcom/bcm2835_cm.c
198
if (ctl & CM_CTL_ENAB) {
sys/arch/arm/broadcom/bcm2835_cm.c
199
CM_WRITE(sc, ctlreg, ctl);
sys/arch/arm/broadcom/bcm2835_pwm.c
228
bcm_pwm_control(struct bcm_pwm_channel *pwm, uint32_t ctl, uint32_t rng)
sys/arch/arm/broadcom/bcm2835_pwm.c
239
ctl = (w & ~pwm->ctlmask) | __SHIFTIN(ctl, pwm->ctlmask);
sys/arch/arm/broadcom/bcm2835_pwm.c
243
(ctl & (PWM_CTL_USEF1|PWM_CTL_USEF2)) != 0)
sys/arch/arm/broadcom/bcm2835_pwm.c
244
ctl |= PWM_CTL_CLRF1;
sys/arch/arm/broadcom/bcm2835_pwm.c
247
PWM_WRITE(sc, PWM_CTL, ctl & ~PWM_CTL_WRITEZERO);
sys/arch/arm/cortex/a9tmr.c
194
uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL);
sys/arch/arm/cortex/a9tmr.c
195
if (ctl & TMR_GBL_CTL_CMP_ENABLE) {
sys/arch/arm/cortex/a9tmr.c
197
ctl & ~TMR_GBL_CTL_CMP_ENABLE);
sys/arch/arm/cortex/a9tmr.c
211
ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE |
sys/arch/arm/cortex/a9tmr.c
213
a9tmr_global_write(sc, TMR_GBL_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
127
pcireg_t ctl;
sys/arch/arm/cortex/gic_v2m.c
133
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gic_v2m.c
134
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/cortex/gic_v2m.c
135
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
137
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gic_v2m.c
138
ctl &= ~PCI_MSI_CTL_MME_MASK;
sys/arch/arm/cortex/gic_v2m.c
139
ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
sys/arch/arm/cortex/gic_v2m.c
140
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
145
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gic_v2m.c
146
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
sys/arch/arm/cortex/gic_v2m.c
157
ctl |= PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/cortex/gic_v2m.c
158
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
167
pcireg_t ctl;
sys/arch/arm/cortex/gic_v2m.c
173
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gic_v2m.c
174
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/cortex/gic_v2m.c
175
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
185
pcireg_t ctl;
sys/arch/arm/cortex/gic_v2m.c
192
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/cortex/gic_v2m.c
193
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/arch/arm/cortex/gic_v2m.c
194
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
206
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/cortex/gic_v2m.c
207
ctl |= PCI_MSIX_CTL_ENABLE;
sys/arch/arm/cortex/gic_v2m.c
208
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/cortex/gic_v2m.c
217
pcireg_t ctl;
sys/arch/arm/cortex/gic_v2m.c
223
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/cortex/gic_v2m.c
224
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/arch/arm/cortex/gic_v2m.c
225
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/cortex/gicv3_its.c
551
pcireg_t ctl;
sys/arch/arm/cortex/gicv3_its.c
557
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gicv3_its.c
558
ctl &= ~PCI_MSI_CTL_MME_MASK;
sys/arch/arm/cortex/gicv3_its.c
559
ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
sys/arch/arm/cortex/gicv3_its.c
560
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gicv3_its.c
563
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gicv3_its.c
564
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
sys/arch/arm/cortex/gicv3_its.c
576
ctl |= PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/cortex/gicv3_its.c
577
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gicv3_its.c
586
pcireg_t ctl;
sys/arch/arm/cortex/gicv3_its.c
592
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/arm/cortex/gicv3_its.c
593
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
sys/arch/arm/cortex/gicv3_its.c
594
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/arm/cortex/gicv3_its.c
604
pcireg_t ctl;
sys/arch/arm/cortex/gicv3_its.c
623
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/cortex/gicv3_its.c
624
ctl |= PCI_MSIX_CTL_ENABLE;
sys/arch/arm/cortex/gicv3_its.c
625
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/cortex/gicv3_its.c
634
pcireg_t ctl;
sys/arch/arm/cortex/gicv3_its.c
640
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/arm/cortex/gicv3_its.c
641
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/arch/arm/cortex/gicv3_its.c
642
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/arm/cortex/gtmr.c
254
uint64_t ctl;
sys/arch/arm/cortex/gtmr.c
286
ctl = gtmr_read_ctl(sc);
sys/arch/arm/cortex/gtmr.c
287
ctl &= ~CNTCTL_IMASK;
sys/arch/arm/cortex/gtmr.c
288
ctl |= CNTCTL_ENABLE;
sys/arch/arm/cortex/gtmr.c
289
gtmr_write_ctl(sc, ctl);
sys/arch/arm/cortex/gtmr.c
353
const uint32_t ctl = gtmr_read_ctl(sc);
sys/arch/arm/cortex/gtmr.c
354
if ((ctl & (CNTCTL_ENABLE|CNTCTL_ISTATUS)) != (CNTCTL_ENABLE|CNTCTL_ISTATUS)) {
sys/arch/arm/cortex/gtmr.c
355
aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl);
sys/arch/arm/sunxi/sun4i_spi.c
162
uint32_t ctl, cctl;
sys/arch/arm/sunxi/sun4i_spi.c
174
ctl = SPI_CTL_SDM | SPI_CTL_TP_EN | SPI_CTL_SSPOL | SPI_CTL_MODE | SPI_CTL_EN;
sys/arch/arm/sunxi/sun4i_spi.c
178
ctl |= 0;
sys/arch/arm/sunxi/sun4i_spi.c
181
ctl |= SPI_CTL_PHA;
sys/arch/arm/sunxi/sun4i_spi.c
184
ctl |= SPI_CTL_POL;
sys/arch/arm/sunxi/sun4i_spi.c
187
ctl |= SPI_CTL_PHA | SPI_CTL_POL;
sys/arch/arm/sunxi/sun4i_spi.c
207
ctl, cctl, sc->sc_modclkrate,
sys/arch/arm/sunxi/sun4i_spi.c
213
sc->sc_CTL = ctl;
sys/arch/arm/sunxi/sun4i_spi.c
214
SPIREG_WRITE(sc, SPI_CTL, (ctl | SPI_CTL_RF_RST | SPI_CTL_TF_RST) & ~SPI_CTL_EN);
sys/arch/arm/sunxi/sun4i_spi.c
216
SPIREG_WRITE(sc, SPI_CTL, ctl);
sys/arch/arm/sunxi/sun4i_spi.c
338
uint32_t ctl;
sys/arch/arm/sunxi/sun4i_spi.c
363
ctl = sc->sc_CTL | __SHIFTIN(st->st_slave, SPI_CTL_SS) | SPI_CTL_XCH;
sys/arch/arm/sunxi/sun4i_spi.c
364
SPIREG_WRITE(sc, SPI_CTL, ctl);
sys/arch/arm/sunxi/sunxi_i2s.c
695
uint32_t ctl, fat0, chsel;
sys/arch/arm/sunxi/sunxi_i2s.c
702
ctl = I2S_READ(sc, DA_CTL);
sys/arch/arm/sunxi/sunxi_i2s.c
720
ctl &= ~DA_CTL_PCM;
sys/arch/arm/sunxi/sunxi_i2s.c
722
ctl &= ~DA_CTL_MODE_SEL;
sys/arch/arm/sunxi/sunxi_i2s.c
725
ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL);
sys/arch/arm/sunxi/sunxi_i2s.c
729
ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL);
sys/arch/arm/sunxi/sunxi_i2s.c
733
ctl |= __SHIFTIN(DA_CTL_MODE_SEL_RJ, DA_CTL_MODE_SEL);
sys/arch/arm/sunxi/sunxi_i2s.c
737
ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL);
sys/arch/arm/sunxi/sunxi_i2s.c
741
ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL);
sys/arch/arm/sunxi/sunxi_i2s.c
778
ctl |= DA_CTL_MS; /* codec is master */
sys/arch/arm/sunxi/sunxi_i2s.c
780
ctl &= ~DA_CTL_BCLK_OUT;
sys/arch/arm/sunxi/sunxi_i2s.c
781
ctl &= ~DA_CLK_LRCK_OUT;
sys/arch/arm/sunxi/sunxi_i2s.c
786
ctl &= ~DA_CTL_MS; /* codec is slave */
sys/arch/arm/sunxi/sunxi_i2s.c
788
ctl |= DA_CTL_BCLK_OUT;
sys/arch/arm/sunxi/sunxi_i2s.c
789
ctl |= DA_CLK_LRCK_OUT;
sys/arch/arm/sunxi/sunxi_i2s.c
796
I2S_WRITE(sc, DA_CTL, ctl);
sys/arch/arm/sunxi/sunxi_nand.c
370
uint32_t ctl;
sys/arch/arm/sunxi/sunxi_nand.c
372
ctl = NAND_READ(sc, NDFC_CTL);
sys/arch/arm/sunxi/sunxi_nand.c
374
ctl &= ~NDFC_CTL_CE_SEL;
sys/arch/arm/sunxi/sunxi_nand.c
375
ctl |= __SHIFTIN(chip->chip_cs, NDFC_CTL_CE_SEL);
sys/arch/arm/sunxi/sunxi_nand.c
376
ctl &= ~NDFC_CTL_RB_SEL;
sys/arch/arm/sunxi/sunxi_nand.c
377
ctl |= __SHIFTIN(chip->chip_rb, NDFC_CTL_RB_SEL);
sys/arch/arm/sunxi/sunxi_nand.c
378
ctl &= ~NDFC_CTL_PAGE_SIZE;
sys/arch/arm/sunxi/sunxi_nand.c
379
ctl &= ~NDFC_CTL_BUS_WIDTH;
sys/arch/arm/sunxi/sunxi_nand.c
380
ctl |= NDFC_CTL_EN;
sys/arch/arm/sunxi/sunxi_nand.c
383
ctl |= __SHIFTIN(__builtin_ffs(nc->nc_page_size) - 11,
sys/arch/arm/sunxi/sunxi_nand.c
386
ctl |= NDFC_CTL_BUS_WIDTH;
sys/arch/arm/sunxi/sunxi_nand.c
391
NAND_WRITE(sc, NDFC_CTL, ctl);
sys/arch/bebox/stand/boot/kbd.c
140
chr = ctl[dt];
sys/arch/cobalt/stand/boot/tlp.c
457
uint32_t ctl, sts;
sys/arch/cobalt/stand/boot/tlp.c
460
ctl = tlp_mii_read(l, phy, MII_BMCR);
sys/arch/cobalt/stand/boot/tlp.c
462
if (ctl != 0xffff && sts != 0xffff)
sys/arch/cobalt/stand/boot/tlp.c
468
ctl = tlp_mii_read(l, phy, MII_BMCR);
sys/arch/cobalt/stand/boot/tlp.c
469
tlp_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/cobalt/stand/boot/tlp.c
473
ctl = tlp_mii_read(l, phy, MII_BMCR);
sys/arch/cobalt/stand/boot/tlp.c
474
if (ctl == 0xffff) {
sys/arch/cobalt/stand/boot/tlp.c
478
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/cobalt/stand/boot/tlp.c
482
ctl &= ~BMCR_ISO;
sys/arch/cobalt/stand/boot/tlp.c
483
tlp_mii_write(l, phy, MII_BMCR, ctl);
sys/arch/emips/ebus/if_le_ebus.c
518
uint32_t ctl;
sys/arch/emips/ebus/if_le_ebus.c
534
ctl = sc->sc_regs->Control | EC_INTEN;
sys/arch/emips/ebus/if_le_ebus.c
535
ctl &= ~EC_RXDIS;
sys/arch/emips/ebus/if_le_ebus.c
536
sc->sc_regs->Control = ctl;
sys/arch/emips/ebus/if_le_ebus.c
538
printf("enic_init <- %x\n", ctl);
sys/arch/evbmips/loongson/dev/stvii.c
406
int ctl;
sys/arch/evbmips/loongson/dev/stvii.c
410
ctl = stvii_readreg(sc, ST7_CONTROL);
sys/arch/evbmips/loongson/dev/stvii.c
411
if (ctl == -1)
sys/arch/evbmips/loongson/dev/stvii.c
413
stvii_writereg(sc, ST7_CONTROL, ctl & ~(STC_MAIN_POWER | STC_DDR_POWER));
sys/arch/evbppc/walnut/dev/ds1743.c
211
u_char octl, ctl;
sys/arch/evbppc/walnut/dev/ds1743.c
214
ctl = octl | (mode & DS_CTL_RW);
sys/arch/evbppc/walnut/dev/ds1743.c
215
ds1743_write(sc, DS_CENTURY, ctl); /* Lock RTC for both reading and writing */
sys/arch/evbppc/walnut/dev/ds1743.c
222
int ctl;
sys/arch/evbppc/walnut/dev/ds1743.c
224
ctl = ds1743_read(sc, DS_CENTURY);
sys/arch/evbppc/walnut/dev/ds1743.c
225
ctl = (ctl & 0x3f) | (key & DS_CTL_RW);
sys/arch/evbppc/walnut/dev/ds1743.c
226
ds1743_write(sc, DS_CENTURY, ctl); /* Enable updates */
sys/arch/luna68k/dev/if_le.c
220
volatile struct { uint32_t ctl; } *ds1220;
sys/arch/luna68k/dev/if_le.c
243
ds1220->ctl = (loc) << 16;
sys/arch/luna68k/dev/if_le.c
244
u = 0xf0 & (ds1220->ctl >> 12);
sys/arch/luna68k/dev/if_le.c
245
ds1220->ctl = (loc + 1) << 16;
sys/arch/luna68k/dev/if_le.c
246
l = 0x0f & (ds1220->ctl >> 16);
sys/arch/luna68k/dev/if_le.c
249
ds1220->ctl = (loc + 2) << 16;
sys/arch/luna68k/dev/if_le.c
250
u = 0xf0 & (ds1220->ctl >> 12);
sys/arch/luna68k/dev/if_le.c
251
ds1220->ctl = (loc + 3) << 16;
sys/arch/luna68k/dev/if_le.c
252
l = 0x0f & (ds1220->ctl >> 16);
sys/arch/luna68k/stand/boot/if_le.c
239
volatile struct { uint32_t ctl; } *ds1220;
sys/arch/luna68k/stand/boot/if_le.c
262
ds1220->ctl = (loc) << 16;
sys/arch/luna68k/stand/boot/if_le.c
263
u = 0xf0 & (ds1220->ctl >> 12);
sys/arch/luna68k/stand/boot/if_le.c
264
ds1220->ctl = (loc + 1) << 16;
sys/arch/luna68k/stand/boot/if_le.c
265
l = 0x0f & (ds1220->ctl >> 16);
sys/arch/luna68k/stand/boot/if_le.c
268
ds1220->ctl = (loc + 2) << 16;
sys/arch/luna68k/stand/boot/if_le.c
269
u = 0xf0 & (ds1220->ctl >> 12);
sys/arch/luna68k/stand/boot/if_le.c
270
ds1220->ctl = (loc + 3) << 16;
sys/arch/luna68k/stand/boot/if_le.c
271
l = 0x0f & (ds1220->ctl >> 16);
sys/arch/mips/alchemy/au_timer.c
109
if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
sys/arch/mips/alchemy/au_timer.c
110
SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl);
sys/arch/mips/alchemy/au_timer.c
75
uint32_t ctl, ctr, octr;
sys/arch/mips/alchemy/au_timer.c
79
ctl = bus_space_read_4(st, sh, PC_COUNTER_CONTROL);
sys/arch/mips/alchemy/au_timer.c
80
if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1))
sys/arch/mips/alchemy/au_timer.c
81
SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl | CC_EO | CC_EN1);
sys/arch/mips/atheros/dev/arspi.c
284
uint32_t ctl, cnt;
sys/arch/mips/atheros/dev/arspi.c
301
ctl = GETREG(sc, ARSPI_REG_CTL);
sys/arch/mips/atheros/dev/arspi.c
302
} while (ctl & ARSPI_CTL_BUSY);
sys/arch/mips/atheros/dev/arspi.c
304
ctl &= ~(ARSPI_CTL_TXCNT_MASK | ARSPI_CTL_RXCNT_MASK);
sys/arch/mips/atheros/dev/arspi.c
309
ctl |= (1 << ARSPI_CTL_TXCNT_SHIFT);
sys/arch/mips/atheros/dev/arspi.c
311
ctl |= (1 << ARSPI_CTL_RXCNT_SHIFT);
sys/arch/mips/atheros/dev/arspi.c
315
ctl |= (1 << ARSPI_CTL_TXCNT_SHIFT);
sys/arch/mips/atheros/dev/arspi.c
328
ctl |= (cnt << ARSPI_CTL_TXCNT_SHIFT);
sys/arch/mips/atheros/dev/arspi.c
332
ctl |= (cnt << ARSPI_CTL_RXCNT_SHIFT);
sys/arch/mips/atheros/dev/arspi.c
336
ctl |= ARSPI_CTL_START;
sys/arch/mips/atheros/dev/arspi.c
338
PUTREG(sc, ARSPI_REG_CTL, ctl);
sys/arch/mips/cavium/dev/octeon_gmx.c
577
uint64_t ctl = 0;
sys/arch/mips/cavium/dev/octeon_gmx.c
585
SET(ctl, RXN_ADR_CTL_BCST);
sys/arch/mips/cavium/dev/octeon_gmx.c
589
CLR(ctl, RXN_ADR_CTL_CAM_MODE);
sys/arch/mips/cavium/dev/octeon_gmx.c
592
SET(ctl, RXN_ADR_CTL_CAM_MODE);
sys/arch/mips/cavium/dev/octeon_gmx.c
661
ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_ACCEPT, RXN_ADR_CTL_MCST);
sys/arch/mips/cavium/dev/octeon_gmx.c
666
ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_AFCAM, RXN_ADR_CTL_MCST);
sys/arch/mips/cavium/dev/octeon_gmx.c
671
ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_REJECT, RXN_ADR_CTL_MCST);
sys/arch/mips/cavium/dev/octeon_gmx.c
684
dprintf("ctl = %#lx, cam_en = %#lx\n", ctl, cam_en);
sys/arch/mips/cavium/dev/octeon_gmx.c
685
_GMX_PORT_WR8(sc, GMX0_RX0_ADR_CTL, ctl);
sys/arch/mips/cavium/dev/octeon_rnm.c
320
uint64_t ctl = 0;
sys/arch/mips/cavium/dev/octeon_rnm.c
322
ctl |= RNM_CTL_STATUS_RNG_EN; /* enable FIFO */
sys/arch/mips/cavium/dev/octeon_rnm.c
323
ctl |= RNM_CTL_STATUS_ENT_EN; /* enable entropy source */
sys/arch/mips/cavium/dev/octeon_rnm.c
324
ctl |= RNM_CTL_STATUS_EXP_ENT; /* expose entropy without LFSR/SHA-1 */
sys/arch/mips/cavium/dev/octeon_rnm.c
325
ctl |= __SHIFTIN(rogroup, RNM_CTL_STATUS_ENT_SEL_MASK);
sys/arch/mips/cavium/dev/octeon_rnm.c
328
ctl);
sys/arch/mips/include/netbsd32_machdep.h
81
int ctl;
sys/arch/mips/include/sysarch.h
46
int ctl;
sys/arch/mips/mips/netbsd32_machdep.c
191
error = mips_user_cachectl(p, ccua.va, ccua.nbytes, ccua.ctl);
sys/arch/mips/mips/sys_machdep.c
86
error = mips_user_cachectl(p, ccua.va, ccua.nbytes, ccua.ctl);
sys/arch/mips/sibyte/dev/sbmac.c
1337
uint64_t ctl;
sys/arch/mips/sibyte/dev/sbmac.c
1355
ctl = SBMAC_READCSR(sc->sbm_macenable);
sys/arch/mips/sibyte/dev/sbmac.c
1356
ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0);
sys/arch/mips/sibyte/dev/sbmac.c
1357
SBMAC_WRITECSR(sc->sbm_macenable, ctl);
sys/arch/mvme68k/stand/sboot/console.c
109
zs->ctl = 0;
sys/arch/mvme68k/stand/sboot/console.c
110
while ((zs->ctl & 0x1) == 0) {
sys/arch/mvme68k/stand/sboot/console.c
111
zs->ctl = 0;
sys/arch/mvme68k/stand/sboot/console.c
113
zs->ctl = 8;
sys/arch/mvme68k/stand/sboot/console.c
114
return zs->ctl;
sys/arch/mvme68k/stand/sboot/console.c
38
volatile u_char ctl;
sys/arch/mvme68k/stand/sboot/console.c
55
zs->ctl = 1; rr1 = zs->ctl;
sys/arch/mvme68k/stand/sboot/console.c
56
zs->ctl = 0;
sys/arch/mvme68k/stand/sboot/console.c
57
if ((rr1 & 0x1) == 1 && (zs->ctl & 0x4) == 4)
sys/arch/mvme68k/stand/sboot/console.c
60
zs->ctl = 9;
sys/arch/mvme68k/stand/sboot/console.c
61
zs->ctl = 0x00; /* clear interrupt */
sys/arch/mvme68k/stand/sboot/console.c
62
zs->ctl = 4;
sys/arch/mvme68k/stand/sboot/console.c
63
zs->ctl = 0x44; /* 16x clk, 1 stop bit */
sys/arch/mvme68k/stand/sboot/console.c
64
zs->ctl = 5;
sys/arch/mvme68k/stand/sboot/console.c
65
zs->ctl = 0xea; /* DTR on, 8 bit xmit, xmit on, RTS on */
sys/arch/mvme68k/stand/sboot/console.c
66
zs->ctl = 3;
sys/arch/mvme68k/stand/sboot/console.c
67
zs->ctl = 0xc1; /* 8 bit recv, auto cd_cts, recv on */
sys/arch/mvme68k/stand/sboot/console.c
68
zs->ctl = 1;
sys/arch/mvme68k/stand/sboot/console.c
69
zs->ctl = 0x00; /* no intrs */
sys/arch/mvme68k/stand/sboot/console.c
70
zs->ctl = 2;
sys/arch/mvme68k/stand/sboot/console.c
71
zs->ctl = 0x00; /* no vector */
sys/arch/mvme68k/stand/sboot/console.c
72
zs->ctl = 10;
sys/arch/mvme68k/stand/sboot/console.c
73
zs->ctl = 0x00; /* */
sys/arch/mvme68k/stand/sboot/console.c
74
zs->ctl = 11;
sys/arch/mvme68k/stand/sboot/console.c
75
zs->ctl = 0x50; /* clocking options */
sys/arch/mvme68k/stand/sboot/console.c
76
zs->ctl = 12;
sys/arch/mvme68k/stand/sboot/console.c
77
zs->ctl = 0x0e; /* 9600 baud, part 1 */
sys/arch/mvme68k/stand/sboot/console.c
78
zs->ctl = 13;
sys/arch/mvme68k/stand/sboot/console.c
79
zs->ctl = 0x00; /* 9600 baud, part 2 */
sys/arch/mvme68k/stand/sboot/console.c
80
zs->ctl = 14;
sys/arch/mvme68k/stand/sboot/console.c
81
zs->ctl = 0x03; /* more clocking options */
sys/arch/mvme68k/stand/sboot/console.c
82
zs->ctl = 15;
sys/arch/mvme68k/stand/sboot/console.c
83
zs->ctl = 0x00; /* clear intrs */
sys/arch/mvme68k/stand/sboot/console.c
94
zs->ctl = 0;
sys/arch/mvme68k/stand/sboot/console.c
95
while ((zs->ctl & 0x04) == 0) {
sys/arch/mvme68k/stand/sboot/console.c
96
zs->ctl = 0;
sys/arch/mvme68k/stand/sboot/console.c
98
zs->ctl = 8;
sys/arch/mvme68k/stand/sboot/console.c
99
zs->ctl = (char)c;
sys/arch/news68k/dev/dmac_0266.h
30
volatile uint32_t ctl; /* Control Register */
sys/arch/news68k/dev/si.c
221
sc->sc_regs->ctl = DC_CTL_RST;
sys/arch/news68k/dev/si.c
285
dmac->ctl = DC_CTL_RST;
sys/arch/news68k/dev/si.c
286
dmac->ctl = 0;
sys/arch/news68k/dev/si.c
322
dmac->ctl = 0;
sys/arch/news68k/dev/si.c
326
dmac->ctl = DC_CTL_ENB;
sys/arch/news68k/dev/si.c
334
dmac->ctl = DC_CTL_MOD;
sys/arch/news68k/dev/si.c
338
dmac->ctl = DC_CTL_MOD | DC_CTL_ENB;
sys/arch/news68k/dev/si.c
403
dmac->ctl &= ~DC_CTL_ENB;
sys/arch/news68k/dev/si.c
431
dmac->ctl = DC_CTL_RST;
sys/arch/news68k/dev/si.c
432
dmac->ctl = 0;
sys/arch/newsmips/apbus/apbus_subr.c
74
struct apbus_ctl *ctl;
sys/arch/newsmips/apbus/apbus_subr.c
79
ctl = apbus_dev->apbd_ctl;
sys/arch/newsmips/apbus/apbus_subr.c
80
if (ctl == NULL)
sys/arch/newsmips/apbus/apbus_subr.c
83
return (void *)ctl->apbc_hwbase;
sys/arch/next68k/dev/esp.c
1650
NCR_WRITE_REG(sc, ESP_DCTL, ctl);
sys/arch/pmax/tc/dt.c
284
sc->sc_msg.ctl = DT_CTL(1, 0, 0);
sys/arch/pmax/tc/dt.c
342
if (DT_CTL_P(msg->ctl) != 0) {
sys/arch/pmax/tc/dt.c
358
if (DT_CTL_LEN(msg->ctl) >= 6 &&
sys/arch/pmax/tc/dt.c
362
} else if (DT_CTL_LEN(msg->ctl) < 6 && msg->body[0] != 0 &&
sys/arch/pmax/tc/dt.c
442
msg->ctl = c;
sys/arch/pmax/tc/dt.c
444
dt_state.ds_len = DT_CTL_LEN(msg->ctl) + 1;
sys/arch/pmax/tc/dt.c
466
l = DT_CTL_LEN(msg->ctl);
sys/arch/pmax/tc/dt.c
469
msg->dst, msg->src, DT_CTL_P(msg->ctl), DT_CTL_SUBADDR(msg->ctl),
sys/arch/pmax/tc/dtkbd.c
167
!DT_CTL_P(msg.ctl))
sys/arch/pmax/tc/dtkbd.c
231
len = DT_CTL_LEN(msg->ctl);
sys/arch/pmax/tc/dtvar.h
41
uint8_t ctl;
sys/arch/powerpc/booke/dev/pq3gpio.c
108
pq3gpio_null_pin_ctl(void *v, int num, int ctl)
sys/arch/powerpc/booke/dev/pq3gpio.c
118
pq3gpio_pin_ctl(void *v, int num, int ctl)
sys/arch/powerpc/booke/dev/pq3gpio.c
128
switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
sys/arch/powerpc/booke/dev/pq3gpio.c
154
if (ctl & GPIO_PIN_OPENDRAIN) {
sys/arch/powerpc/booke/dev/pq3gpio.c
170
pq3gpio_pin_ctl(void *v, int num, int ctl)
sys/arch/powerpc/booke/dev/pq3gpio.c
177
switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
sys/arch/powerpc/booke/dev/pq3gpio.c
191
if (ctl & GPIO_PIN_OPENDRAIN) {
sys/arch/powerpc/ibm4xx/dev/dwcsata.c
377
uint32_t ctl, serror;
sys/arch/powerpc/ibm4xx/dev/dwcsata.c
439
ctl = DWCDMAC_CTL_TTFC(DWCDMAC_TTFC_P2M_DMAC) |
sys/arch/powerpc/ibm4xx/dev/dwcsata.c
447
ctl = DWCDMAC_CTL_TTFC(DWCDMAC_TTFC_M2P_PER) |
sys/arch/powerpc/ibm4xx/dev/dwcsata.c
454
ctl |= DWCDMAC_CTL_SRC_TRWID(2) | DWCDMAC_CTL_DST_TRWID(2) |
sys/arch/powerpc/ibm4xx/dev/dwcsata.c
497
lli->ctl_lo = htole32(ctl);
sys/arch/prep/stand/boot/kbd.c
140
chr = ctl[dt];
sys/arch/sandpoint/stand/altboot/dsk.c
184
CSR_WRITE_1(chan->ctl, ATA_DREQ);
sys/arch/sandpoint/stand/altboot/dsk.c
186
CSR_WRITE_1(chan->ctl, ATA_SRST|ATA_DREQ);
sys/arch/sandpoint/stand/altboot/dsk.c
188
CSR_WRITE_1(chan->ctl, ATA_DREQ);
sys/arch/sandpoint/stand/altboot/globals.h
230
uint32_t cmd, ctl, alt, dma;
sys/arch/sandpoint/stand/altboot/pciide.c
111
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
sys/arch/sandpoint/stand/altboot/pciide.c
114
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
sys/arch/sandpoint/stand/altboot/pciide.c
124
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
sys/arch/sandpoint/stand/altboot/pciide.c
127
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
sys/arch/sandpoint/stand/altboot/pcn.c
348
int phy, ctl, sts, bound;
sys/arch/sandpoint/stand/altboot/pcn.c
351
ctl = pcn_mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/pcn.c
353
if (ctl != 0xffff && sts != 0xffff)
sys/arch/sandpoint/stand/altboot/pcn.c
359
ctl = pcn_mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/pcn.c
360
pcn_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/sandpoint/stand/altboot/pcn.c
364
ctl = pcn_mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/pcn.c
365
if (ctl == 0xffff) {
sys/arch/sandpoint/stand/altboot/pcn.c
369
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/sandpoint/stand/altboot/pcn.c
373
ctl &= ~BMCR_ISO;
sys/arch/sandpoint/stand/altboot/pcn.c
374
pcn_mii_write(l, phy, MII_BMCR, ctl);
sys/arch/sandpoint/stand/altboot/rge.c
369
int bound, ctl, phy, sts;
sys/arch/sandpoint/stand/altboot/rge.c
372
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/rge.c
373
mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/sandpoint/stand/altboot/rge.c
377
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/rge.c
378
if (ctl == 0xffff) {
sys/arch/sandpoint/stand/altboot/rge.c
382
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/sandpoint/stand/altboot/rge.c
386
ctl &= ~BMCR_ISO;
sys/arch/sandpoint/stand/altboot/rge.c
387
mii_write(l, phy, MII_BMCR, ctl);
sys/arch/sandpoint/stand/altboot/siisata.c
100
l->chan[1].ctl = l->chan[1].alt = (l->bar[5] + 0x0c8) | 02;
sys/arch/sandpoint/stand/altboot/siisata.c
102
l->chan[2].ctl = l->chan[2].alt = (l->bar[5] + 0x288) | 02;
sys/arch/sandpoint/stand/altboot/siisata.c
104
l->chan[3].ctl = l->chan[3].alt = (l->bar[5] + 0x2c8) | 02;
sys/arch/sandpoint/stand/altboot/siisata.c
88
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
sys/arch/sandpoint/stand/altboot/siisata.c
91
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
sys/arch/sandpoint/stand/altboot/siisata.c
98
l->chan[0].ctl = l->chan[0].alt = (l->bar[5] + 0x088) | 02;
sys/arch/sandpoint/stand/altboot/sip.c
376
int phy, ctl, sts, bound;
sys/arch/sandpoint/stand/altboot/sip.c
379
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/sip.c
381
if (ctl != 0xffff && sts != 0xffff)
sys/arch/sandpoint/stand/altboot/sip.c
387
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/sip.c
388
mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/sandpoint/stand/altboot/sip.c
392
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/sip.c
393
if (ctl == 0xffff) {
sys/arch/sandpoint/stand/altboot/sip.c
397
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/sandpoint/stand/altboot/sip.c
401
ctl &= ~BMCR_ISO;
sys/arch/sandpoint/stand/altboot/sip.c
402
mii_write(l, phy, MII_BMCR, ctl);
sys/arch/sandpoint/stand/altboot/skg.c
360
unsigned bound, ctl, rxstat, len;
sys/arch/sandpoint/stand/altboot/skg.c
371
ctl = le32toh(rxd->xd0);
sys/arch/sandpoint/stand/altboot/skg.c
372
if ((ctl & CTL_OWN) == 0)
sys/arch/sandpoint/stand/altboot/skg.c
386
len = ctl & FRAMEMASK;
sys/arch/sandpoint/stand/altboot/sme.c
278
uint32_t ctl;
sys/arch/sandpoint/stand/altboot/sme.c
281
ctl = CSR_READ(l, MIIADDR);
sys/arch/sandpoint/stand/altboot/sme.c
282
} while (ctl & 01);
sys/arch/sandpoint/stand/altboot/sme.c
283
ctl = (phy << 11) | (reg << 6) | (0 << 1); /* READ op */
sys/arch/sandpoint/stand/altboot/sme.c
284
CSR_WRITE(l, MIIADDR, ctl);
sys/arch/sandpoint/stand/altboot/sme.c
286
ctl = CSR_READ(l, MIIADDR);
sys/arch/sandpoint/stand/altboot/sme.c
287
} while (ctl & 01);
sys/arch/sandpoint/stand/altboot/sme.c
294
uint32_t ctl;
sys/arch/sandpoint/stand/altboot/sme.c
297
ctl = CSR_READ(l, MIIADDR);
sys/arch/sandpoint/stand/altboot/sme.c
298
} while (ctl & 01);
sys/arch/sandpoint/stand/altboot/sme.c
299
ctl = (phy << 11) | (reg << 6) | (1 << 1); /* WRITE op */
sys/arch/sandpoint/stand/altboot/stg.c
443
int phy, ctl, sts, bound;
sys/arch/sandpoint/stand/altboot/stg.c
449
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/stg.c
451
if (ctl != 0xffff && sts != 0xffff && sts != 0)
sys/arch/sandpoint/stand/altboot/stg.c
458
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/stg.c
459
mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/sandpoint/stand/altboot/stg.c
464
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/stg.c
465
if (ctl == 0xffff) {
sys/arch/sandpoint/stand/altboot/stg.c
469
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/sandpoint/stand/altboot/stg.c
473
ctl &= ~BMCR_ISO;
sys/arch/sandpoint/stand/altboot/stg.c
474
mii_write(l, phy, MII_BMCR, ctl);
sys/arch/sandpoint/stand/altboot/tlp.c
374
int phy, ctl, sts, bound;
sys/arch/sandpoint/stand/altboot/tlp.c
377
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/tlp.c
379
if (ctl != 0xffff && sts != 0xffff)
sys/arch/sandpoint/stand/altboot/tlp.c
385
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/tlp.c
386
mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/sandpoint/stand/altboot/tlp.c
390
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/tlp.c
391
if (ctl == 0xffff) {
sys/arch/sandpoint/stand/altboot/tlp.c
395
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/sandpoint/stand/altboot/tlp.c
399
ctl &= ~BMCR_ISO;
sys/arch/sandpoint/stand/altboot/tlp.c
400
mii_write(l, phy, MII_BMCR, ctl);
sys/arch/sandpoint/stand/altboot/wm.c
111
unsigned ctl, tctl, rctl;
sys/arch/sandpoint/stand/altboot/wm.c
405
int phy, ctl, sts, bound;
sys/arch/sandpoint/stand/altboot/wm.c
408
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/wm.c
410
if (ctl != 0xffff && sts != 0xffff)
sys/arch/sandpoint/stand/altboot/wm.c
416
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/wm.c
417
mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
sys/arch/sandpoint/stand/altboot/wm.c
421
ctl = mii_read(l, phy, MII_BMCR);
sys/arch/sandpoint/stand/altboot/wm.c
422
if (ctl == 0xffff) {
sys/arch/sandpoint/stand/altboot/wm.c
426
} while (bound-- > 0 && (ctl & BMCR_RESET));
sys/arch/sandpoint/stand/altboot/wm.c
430
ctl &= ~BMCR_ISO;
sys/arch/sandpoint/stand/altboot/wm.c
431
mii_write(l, phy, MII_BMCR, ctl);
sys/arch/sgimips/dev/ctl.c
68
CFATTACH_DECL_NEW(ctl, sizeof(struct ctl_softc),
sys/arch/sgimips/hpc/haltwo.c
132
haltwo_write(sc, ctl, HAL2_REG_CTL_IDR0, low);
sys/arch/sgimips/hpc/haltwo.c
133
haltwo_write(sc, ctl, HAL2_REG_CTL_IDR1, high);
sys/arch/sgimips/hpc/haltwo.c
134
haltwo_write(sc, ctl, HAL2_REG_CTL_IDR2, 0);
sys/arch/sgimips/hpc/haltwo.c
135
haltwo_write(sc, ctl, HAL2_REG_CTL_IDR3, 0);
sys/arch/sgimips/hpc/haltwo.c
136
haltwo_write(sc, ctl, HAL2_REG_CTL_IAR, ireg);
sys/arch/sgimips/hpc/haltwo.c
138
while (haltwo_read(sc, ctl, HAL2_REG_CTL_ISR) & HAL2_ISR_TSTATUS)
sys/arch/sgimips/hpc/haltwo.c
147
haltwo_write(sc, ctl, HAL2_REG_CTL_IAR,
sys/arch/sgimips/hpc/haltwo.c
150
while (haltwo_read(sc, ctl, HAL2_REG_CTL_ISR) & HAL2_ISR_TSTATUS)
sys/arch/sgimips/hpc/haltwo.c
154
*low = haltwo_read(sc, ctl, HAL2_REG_CTL_IDR0);
sys/arch/sgimips/hpc/haltwo.c
157
*high = haltwo_read(sc, ctl, HAL2_REG_CTL_IDR1);
sys/arch/sgimips/hpc/haltwo.c
322
haltwo_write(sc, ctl, HAL2_REG_CTL_ISR, 0);
sys/arch/sgimips/hpc/haltwo.c
323
haltwo_write(sc, ctl, HAL2_REG_CTL_ISR,
sys/arch/sgimips/hpc/haltwo.c
327
rev = haltwo_read(sc, ctl, HAL2_REG_CTL_REV);
sys/arch/sgimips/hpc/haltwo.c
770
haltwo_write(sc, ctl, HAL2_REG_CTL_ISR, 0);
sys/arch/sgimips/hpc/haltwo.c
771
haltwo_write(sc, ctl, HAL2_REG_CTL_ISR,
sys/arch/sparc/dev/tctrl.c
1039
int ctl = (minor(dev)&0x0f);
sys/arch/sparc/dev/tctrl.c
1048
switch (ctl) {
sys/arch/sparc/dev/tctrl.c
1069
int ctl = (minor(dev)&0x0f);
sys/arch/sparc/dev/tctrl.c
1076
switch (ctl) {
sys/arch/sparc/dev/ts102.c
405
int ctl, status;
sys/arch/sparc/dev/ts102.c
426
ctl = TSLOT_READ(td, TS102_REG_CARD_A_CTL);
sys/arch/sparc/dev/ts102.c
429
ctl &= ~(TS102_CARD_CTL_AA_MASK | TS102_CARD_CTL_IA_MASK);
sys/arch/sparc/dev/ts102.c
432
ctl |= TS102_CARD_CTL_SBLE; /* this is not what it looks like! */
sys/arch/sparc/dev/ts102.c
433
ctl &= ~TS102_CARD_CTL_PCMBE; /* default */
sys/arch/sparc/dev/ts102.c
436
ctl &= ~TS102_CARD_CTL_RAHD;
sys/arch/sparc/dev/ts102.c
437
ctl |= TS102_CARD_CTL_INCDIS;
sys/arch/sparc/dev/ts102.c
440
ctl &= ~TS102_CARD_CTL_PWRD;
sys/arch/sparc/dev/ts102.c
441
TSLOT_WRITE(td, TS102_REG_CARD_A_CTL, ctl);
sys/arch/sparc/dev/ts102.c
442
TSPRINTF("ctl: %x\n", ctl);
sys/arch/sun3/dev/xd.c
423
struct xd_iopb_ctrl *ctl;
sys/arch/sun3/dev/xd.c
485
ctl = (struct xd_iopb_ctrl *)&xdc->iopbase[rqno];
sys/arch/sun3/dev/xd.c
486
if (ctl->ctype != XDCT_753) {
sys/arch/sun3/dev/xd.c
495
ctl->eprom_partno, ctl->eprom_lvl, ctl->eprom_rev);
sys/arch/x68k/usr.bin/tvctrl/tvctrl.c
19
unsigned char ctl;
sys/arch/x68k/usr.bin/tvctrl/tvctrl.c
31
ctl = num;
sys/arch/x68k/usr.bin/tvctrl/tvctrl.c
32
if (ioctl(0, ITETVCTRL, &ctl))
sys/arch/x86/pci/msipic.c
340
pcireg_t ctl;
sys/arch/x86/pci/msipic.c
353
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/x86/pci/msipic.c
355
ctl |= PCI_MSI_CTL_MSI_ENABLE;
sys/arch/x86/pci/msipic.c
357
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
sys/arch/x86/pci/msipic.c
360
pci_conf_write16(pc, tag, off + PCI_MSI_CTL + 2, ctl >> 16);
sys/arch/x86/pci/msipic.c
362
pci_conf_write(pc, tag, off, ctl);
sys/arch/x86/pci/msipic.c
394
pcireg_t ctl;
sys/arch/x86/pci/msipic.c
403
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/x86/pci/msipic.c
428
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
sys/arch/x86/pci/msipic.c
437
ctl |= PCI_MSI_CTL_MSI_ENABLE;
sys/arch/x86/pci/msipic.c
439
pci_conf_write16(pc, tag, off + PCI_MSI_CTL + 2, ctl >> 16);
sys/arch/x86/pci/msipic.c
441
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/x86/pci/msipic.c
573
pcireg_t ctl;
sys/arch/x86/pci/msipic.c
590
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/x86/pci/msipic.c
591
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/arch/x86/pci/msipic.c
592
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/x86/pci/msipic.c
621
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/arch/x86/pci/msipic.c
622
if (ctl & PCI_MSIX_CTL_FUNCMASK) {
sys/arch/x86/pci/msipic.c
623
ctl &= ~PCI_MSIX_CTL_FUNCMASK;
sys/arch/x86/pci/msipic.c
625
ctl |= PCI_MSIX_CTL_ENABLE;
sys/arch/x86/pci/msipic.c
627
pci_conf_write16(pc, tag, off + PCI_MSIX_CTL + 2, ctl >> 16);
sys/arch/x86/pci/msipic.c
629
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/arch/x86/pci/msipic.c
816
pcireg_t ctl;
sys/arch/x86/pci/msipic.c
824
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
sys/arch/x86/pci/msipic.c
825
ctl &= ~PCI_MSI_CTL_MME_MASK;
sys/arch/x86/pci/msipic.c
826
ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
sys/arch/x86/pci/msipic.c
827
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
sys/arch/x86/x86/powernow.c
525
uint64_t status, ctl;
sys/arch/x86/x86/powernow.c
555
ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;
sys/arch/x86/x86/powernow.c
557
ctl |= PN7_CTR_FID(fid);
sys/arch/x86/x86/powernow.c
558
ctl |= PN7_CTR_VID(vid);
sys/arch/x86/x86/powernow.c
559
ctl |= PN7_CTR_SGTC(sc->sc_state->sgtc);
sys/arch/x86/x86/powernow.c
566
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
sys/arch/x86/x86/powernow.c
569
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC);
sys/arch/x86/x86/powernow.c
573
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_VIDC);
sys/arch/x86/x86/powernow.c
576
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
sys/compat/common/uipc_syscalls_43.c
307
struct mbuf *ctl;
sys/compat/common/uipc_syscalls_43.c
321
ctl = m_get(M_WAIT, MT_CONTROL);
sys/compat/common/uipc_syscalls_43.c
322
ctl->m_len = clen;
sys/compat/common/uipc_syscalls_43.c
323
cmsg = mtod(ctl, struct cmsghdr *);
sys/compat/common/uipc_syscalls_43.c
330
m_free(ctl);
sys/compat/common/uipc_syscalls_43.c
334
msg->msg_control = ctl;
sys/compat/sunos/sunos_ioctl.c
412
int (*ctl)(struct file *, u_long, void *);
sys/compat/sunos/sunos_ioctl.c
426
ctl = fp->f_ops->fo_ioctl;
sys/compat/sunos/sunos_ioctl.c
449
error = (*ctl)(fp, TIOCSETD, &disc);
sys/compat/sunos/sunos_ioctl.c
469
error = (*ctl)(fp, TIOCCONS, &on);
sys/compat/sunos/sunos_ioctl.c
477
if ((error = (*ctl)(fp, TIOCGWINSZ, &ws)) != 0)
sys/compat/sunos/sunos_ioctl.c
486
error = (*ctl)(fp, TIOCSWINSZ, &ws);
sys/compat/sunos/sunos_ioctl.c
494
if ((error = (*ctl)(fp, TIOCGWINSZ, &ws)) != 0)
sys/compat/sunos/sunos_ioctl.c
508
error = (*ctl)(fp, TIOCGPGRP, &pgrp);
sys/compat/sunos/sunos_ioctl.c
529
error = (*ctl)(fp, TIOCGPGRP, &pgrp);
sys/compat/sunos/sunos_ioctl.c
553
if ((error = (*ctl)(fp, TIOCGETA, &bts)) != 0)
sys/compat/sunos/sunos_ioctl.c
578
if ((error = (*ctl)(fp, TIOCGETA, &bts)) != 0)
sys/compat/sunos/sunos_ioctl.c
589
error = (*ctl)(fp, SCARG(uap, com) - SUNOS_TCSETA + TIOCSETA,
sys/compat/sunos/sunos_ioctl.c
604
error = (*ctl)(fp, SCARG(uap, com) - SUNOS_TCSETS + TIOCSETA,
sys/compat/sunos/sunos_ioctl.c
617
error = (*ctl)(fp, TIOCUCNTL, &on);
sys/compat/sunos/sunos_ioctl.c
626
error = (*ctl)(fp, TIOCSIG, &sig);
sys/compat/sunos/sunos_ioctl.c
638
error = (*ctl)(fp, a, &ifreq); \
sys/compat/sunos/sunos_ioctl.c
646
if ((error = (*ctl)(fp, a, &ifreq)) != 0) \
sys/compat/sunos/sunos_ioctl.c
719
error = (*ctl)(fp, OOSIOCGIFCONF, &ifc);
sys/compat/sunos/sunos_ioctl.c
735
error = (*ctl)(fp, AUDIO_GETINFO, &aui);
sys/compat/sunos/sunos_ioctl.c
800
error = (*ctl)(fp, AUDIO_SETINFO, &aui);
sys/compat/sunos/sunos_ioctl.c
807
error = (*ctl)(fp, AUDIO_DRAIN, NULL);
sys/compat/sunos/sunos_ioctl.c
837
error = (*ctl)(fp, TIOCFLUSH, &tmp);
sys/compat/sunos/sunos_ioctl.c
848
error = (*ctl)(fp, FIOASYNC, &on);
sys/compat/sunos/sunos_ioctl.c
860
error = (*ctl)(fp, DIOCGDINFO, &dl);
sys/compat/sunos/sunos_ioctl.c
889
error = (*ctl)(fp, DIOCGDINFO, &label);
sys/compat/sunos/sunos_ioctl.c
892
error = (*ctl)(fp, DIOCGPARTINFO, &pi);
sys/dev/apm/apm.c
678
int ctl = APM(dev);
sys/dev/apm/apm.c
693
switch (ctl) {
sys/dev/apm/apm.c
726
int ctl = APM(dev);
sys/dev/apm/apm.c
732
switch (ctl) {
sys/dev/cadence/if_cemac.c
1090
uint32_t ctl = CEMAC_READ(ETH_CTL);
sys/dev/cadence/if_cemac.c
1096
CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
sys/dev/cadence/if_cemac.c
1200
CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
sys/dev/cadence/if_cemac.c
250
uint32_t imr, isr, ctl;
sys/dev/cadence/if_cemac.c
291
ctl = CEMAC_READ(ETH_CTL);
sys/dev/cadence/if_cemac.c
293
CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
sys/dev/cadence/if_cemac.c
297
CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
sys/dev/cadence/if_cemac.c
954
uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX;
sys/dev/cadence/if_cemac.c
955
CEMAC_WRITE(ETH_CTL, ctl);
sys/dev/gpio/gpio.c
1030
struct gpio_pin_ctl *ctl;
sys/dev/gpio/gpio.c
1112
ctl = data;
sys/dev/gpio/gpio.c
1118
pin = ctl->gp_pin;
sys/dev/gpio/gpio.c
1124
flags = ctl->gp_flags;
sys/dev/gpio/gpio.c
1130
ctl->gp_caps = sc->sc_pins[pin].pin_caps;
sys/dev/gpio/gpio.c
1132
ctl->gp_flags = sc->sc_pins[pin].pin_flags;
sys/dev/hdaudio/hdafg.c
1235
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
1270
ctl = kmem_zalloc(sc->sc_nctls * sizeof(*ctl), KM_SLEEP);
sys/dev/hdaudio/hdafg.c
1286
ctl[cnt].ctl_enable = true;
sys/dev/hdaudio/hdafg.c
1287
ctl[cnt].ctl_widget = w;
sys/dev/hdaudio/hdafg.c
1288
ctl[cnt].ctl_mute = mute;
sys/dev/hdaudio/hdafg.c
1289
ctl[cnt].ctl_step = step;
sys/dev/hdaudio/hdafg.c
1290
ctl[cnt].ctl_size = size;
sys/dev/hdaudio/hdafg.c
1291
ctl[cnt].ctl_offset = offset;
sys/dev/hdaudio/hdafg.c
1292
ctl[cnt].ctl_left = offset;
sys/dev/hdaudio/hdafg.c
1293
ctl[cnt].ctl_right = offset;
sys/dev/hdaudio/hdafg.c
1296
ctl[cnt].ctl_ndir = HDAUDIO_PINDIR_IN;
sys/dev/hdaudio/hdafg.c
1298
ctl[cnt].ctl_ndir = HDAUDIO_PINDIR_OUT;
sys/dev/hdaudio/hdafg.c
1299
ctl[cnt++].ctl_dir = HDAUDIO_PINDIR_OUT;
sys/dev/hdaudio/hdafg.c
1319
ctl[cnt].ctl_enable = true;
sys/dev/hdaudio/hdafg.c
1320
ctl[cnt].ctl_widget = w;
sys/dev/hdaudio/hdafg.c
1321
ctl[cnt].ctl_childwidget = cw;
sys/dev/hdaudio/hdafg.c
1322
ctl[cnt].ctl_index = j;
sys/dev/hdaudio/hdafg.c
1323
ctl[cnt].ctl_mute = mute;
sys/dev/hdaudio/hdafg.c
1324
ctl[cnt].ctl_step = step;
sys/dev/hdaudio/hdafg.c
1325
ctl[cnt].ctl_size = size;
sys/dev/hdaudio/hdafg.c
1326
ctl[cnt].ctl_offset = offset;
sys/dev/hdaudio/hdafg.c
1327
ctl[cnt].ctl_left = offset;
sys/dev/hdaudio/hdafg.c
1328
ctl[cnt].ctl_right = offset;
sys/dev/hdaudio/hdafg.c
1329
ctl[cnt].ctl_ndir = HDAUDIO_PINDIR_IN;
sys/dev/hdaudio/hdafg.c
1330
ctl[cnt++].ctl_dir = HDAUDIO_PINDIR_IN;
sys/dev/hdaudio/hdafg.c
1338
ctl[cnt].ctl_enable = true;
sys/dev/hdaudio/hdafg.c
1339
ctl[cnt].ctl_widget = w;
sys/dev/hdaudio/hdafg.c
1340
ctl[cnt].ctl_mute = mute;
sys/dev/hdaudio/hdafg.c
1341
ctl[cnt].ctl_step = step;
sys/dev/hdaudio/hdafg.c
1342
ctl[cnt].ctl_size = size;
sys/dev/hdaudio/hdafg.c
1343
ctl[cnt].ctl_offset = offset;
sys/dev/hdaudio/hdafg.c
1344
ctl[cnt].ctl_left = offset;
sys/dev/hdaudio/hdafg.c
1345
ctl[cnt].ctl_right = offset;
sys/dev/hdaudio/hdafg.c
1347
ctl[cnt].ctl_ndir = HDAUDIO_PINDIR_OUT;
sys/dev/hdaudio/hdafg.c
1349
ctl[cnt].ctl_ndir = HDAUDIO_PINDIR_IN;
sys/dev/hdaudio/hdafg.c
1350
ctl[cnt++].ctl_dir = HDAUDIO_PINDIR_IN;
sys/dev/hdaudio/hdafg.c
1356
sc->sc_ctls = ctl;
sys/dev/hdaudio/hdafg.c
1447
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
1476
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
1477
if (ctl->ctl_enable == false)
sys/dev/hdaudio/hdafg.c
1479
if (ctl->ctl_widget->w_enable == false ||
sys/dev/hdaudio/hdafg.c
1480
(ctl->ctl_childwidget != NULL &&
sys/dev/hdaudio/hdafg.c
1481
ctl->ctl_childwidget->w_enable == false)) {
sys/dev/hdaudio/hdafg.c
1482
ctl->ctl_forcemute = 1;
sys/dev/hdaudio/hdafg.c
1483
ctl->ctl_muted = HDAUDIO_AMP_MUTE_ALL;
sys/dev/hdaudio/hdafg.c
1484
ctl->ctl_left = ctl->ctl_right = 0;
sys/dev/hdaudio/hdafg.c
1485
ctl->ctl_enable = false;
sys/dev/hdaudio/hdafg.c
1486
if (ctl->ctl_ndir == HDAUDIO_PINDIR_IN)
sys/dev/hdaudio/hdafg.c
1487
ctl->ctl_widget->w_connsenable[
sys/dev/hdaudio/hdafg.c
1488
ctl->ctl_index] = false;
sys/dev/hdaudio/hdafg.c
1490
hda_trace(ctl->ctl_widget->w_afg,
sys/dev/hdaudio/hdafg.c
1492
i, ctl->ctl_widget->w_nid,
sys/dev/hdaudio/hdafg.c
1493
ctl->ctl_childwidget ?
sys/dev/hdaudio/hdafg.c
1494
ctl->ctl_childwidget->w_nid : 0xff);
sys/dev/hdaudio/hdafg.c
2058
hdafg_dump_ctl(const struct hdafg_softc *sc, const struct hdaudio_control *ctl)
sys/dev/hdaudio/hdafg.c
2060
int type = ctl->ctl_widget ? ctl->ctl_widget->w_type : -1;
sys/dev/hdaudio/hdafg.c
2061
int i = (int)(ctl - sc->sc_ctls);
sys/dev/hdaudio/hdafg.c
2064
i, (ctl->ctl_widget ? ctl->ctl_widget->w_nid : -1), type,
sys/dev/hdaudio/hdafg.c
2065
ctl->ctl_ndir == HDAUDIO_PINDIR_IN ? "in " : "out",
sys/dev/hdaudio/hdafg.c
2066
ctl->ctl_dir == HDAUDIO_PINDIR_IN ? "in " : "out",
sys/dev/hdaudio/hdafg.c
2067
ctl->ctl_index);
sys/dev/hdaudio/hdafg.c
2069
if (ctl->ctl_childwidget)
sys/dev/hdaudio/hdafg.c
2070
hda_print1(sc, " cnid %02X", ctl->ctl_childwidget->w_nid);
sys/dev/hdaudio/hdafg.c
2075
ctl->ctl_mute, ctl->ctl_step, ctl->ctl_size,
sys/dev/hdaudio/hdafg.c
2076
ctl->ctl_offset, ctl->ctl_enable == false ? " [DISABLED]" : "");
sys/dev/hdaudio/hdafg.c
2108
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2137
ctl = hdafg_control_lookup(sc, w->w_nid,
sys/dev/hdaudio/hdafg.c
2139
if (ctl && ctl->ctl_enable == true) {
sys/dev/hdaudio/hdafg.c
2140
ctl->ctl_forcemute = 1;
sys/dev/hdaudio/hdafg.c
2141
ctl->ctl_muted = HDAUDIO_AMP_MUTE_ALL;
sys/dev/hdaudio/hdafg.c
2142
ctl->ctl_left = ctl->ctl_right = 0;
sys/dev/hdaudio/hdafg.c
2143
ctl->ctl_enable = false;
sys/dev/hdaudio/hdafg.c
2146
ctl = hdafg_control_lookup(sc, w->w_nid,
sys/dev/hdaudio/hdafg.c
2148
if (ctl && ctl->ctl_enable == true) {
sys/dev/hdaudio/hdafg.c
2149
ctl->ctl_forcemute = 1;
sys/dev/hdaudio/hdafg.c
2150
ctl->ctl_muted = HDAUDIO_AMP_MUTE_ALL;
sys/dev/hdaudio/hdafg.c
2151
ctl->ctl_left = ctl->ctl_right = 0;
sys/dev/hdaudio/hdafg.c
2152
ctl->ctl_enable = false;
sys/dev/hdaudio/hdafg.c
2171
ctl = hdafg_control_lookup(sc,
sys/dev/hdaudio/hdafg.c
2173
if (ctl && ctl->ctl_enable == true) {
sys/dev/hdaudio/hdafg.c
2174
ctl->ctl_forcemute = 1;
sys/dev/hdaudio/hdafg.c
2175
ctl->ctl_muted =
sys/dev/hdaudio/hdafg.c
2177
ctl->ctl_left =
sys/dev/hdaudio/hdafg.c
2178
ctl->ctl_right = 0;
sys/dev/hdaudio/hdafg.c
2179
ctl->ctl_enable = false;
sys/dev/hdaudio/hdafg.c
2222
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2256
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
2257
if (ctl->ctl_enable == false || ctl->ctl_childwidget == NULL)
sys/dev/hdaudio/hdafg.c
2259
if (ctl->ctl_widget->w_bindas == -2 ||
sys/dev/hdaudio/hdafg.c
2260
ctl->ctl_childwidget->w_bindas == -2)
sys/dev/hdaudio/hdafg.c
2262
if (ctl->ctl_widget->w_bindas !=
sys/dev/hdaudio/hdafg.c
2263
ctl->ctl_childwidget->w_bindas ||
sys/dev/hdaudio/hdafg.c
2264
(ctl->ctl_widget->w_bindseqmask &
sys/dev/hdaudio/hdafg.c
2265
ctl->ctl_childwidget->w_bindseqmask) == 0) {
sys/dev/hdaudio/hdafg.c
2266
ctl->ctl_forcemute = 1;
sys/dev/hdaudio/hdafg.c
2267
ctl->ctl_muted = HDAUDIO_AMP_MUTE_ALL;
sys/dev/hdaudio/hdafg.c
2268
ctl->ctl_left = ctl->ctl_right = 0;
sys/dev/hdaudio/hdafg.c
2269
ctl->ctl_enable = false;
sys/dev/hdaudio/hdafg.c
2270
if (ctl->ctl_ndir == HDAUDIO_PINDIR_IN) {
sys/dev/hdaudio/hdafg.c
2273
i, ctl->ctl_widget->w_nid,
sys/dev/hdaudio/hdafg.c
2274
ctl->ctl_widget->w_conns[ctl->ctl_index]);
sys/dev/hdaudio/hdafg.c
2275
ctl->ctl_widget->w_connsenable[
sys/dev/hdaudio/hdafg.c
2276
ctl->ctl_index] = false;
sys/dev/hdaudio/hdafg.c
2286
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2290
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
2291
if (ctl->ctl_enable == false)
sys/dev/hdaudio/hdafg.c
2293
if (ctl->ctl_widget->w_nid != nid)
sys/dev/hdaudio/hdafg.c
2295
if (dir && ctl->ctl_ndir != dir)
sys/dev/hdaudio/hdafg.c
2297
if (index >= 0 && ctl->ctl_ndir == HDAUDIO_PINDIR_IN &&
sys/dev/hdaudio/hdafg.c
2298
ctl->ctl_dir == ctl->ctl_ndir &&
sys/dev/hdaudio/hdafg.c
2299
ctl->ctl_index != index)
sys/dev/hdaudio/hdafg.c
2303
return ctl;
sys/dev/hdaudio/hdafg.c
2310
hdafg_control_amp_set1(struct hdaudio_control *ctl, int lmute, int rmute,
sys/dev/hdaudio/hdafg.c
2313
struct hdafg_softc *sc = ctl->ctl_widget->w_afg;
sys/dev/hdaudio/hdafg.c
2314
int index = ctl->ctl_index;
sys/dev/hdaudio/hdafg.c
2320
hdaudio_command(sc->sc_codec, ctl->ctl_widget->w_nid,
sys/dev/hdaudio/hdafg.c
2327
hdaudio_command(sc->sc_codec, ctl->ctl_widget->w_nid,
sys/dev/hdaudio/hdafg.c
2332
hdafg_control_amp_set(struct hdaudio_control *ctl, uint32_t mute,
sys/dev/hdaudio/hdafg.c
2339
ctl->ctl_muted = mute;
sys/dev/hdaudio/hdafg.c
2341
ctl->ctl_left = left;
sys/dev/hdaudio/hdafg.c
2343
ctl->ctl_right = right;
sys/dev/hdaudio/hdafg.c
2346
if (ctl->ctl_forcemute) {
sys/dev/hdaudio/hdafg.c
2350
lmute = HDAUDIO_AMP_LEFT_MUTED(ctl->ctl_muted);
sys/dev/hdaudio/hdafg.c
2351
rmute = HDAUDIO_AMP_RIGHT_MUTED(ctl->ctl_muted);
sys/dev/hdaudio/hdafg.c
2352
left = ctl->ctl_left;
sys/dev/hdaudio/hdafg.c
2353
right = ctl->ctl_right;
sys/dev/hdaudio/hdafg.c
2357
if (ctl->ctl_dir & HDAUDIO_PINDIR_OUT)
sys/dev/hdaudio/hdafg.c
2358
hdafg_control_amp_set1(ctl, lmute, rmute, left, right, 0);
sys/dev/hdaudio/hdafg.c
2359
if (ctl->ctl_dir & HDAUDIO_PINDIR_IN)
sys/dev/hdaudio/hdafg.c
2360
hdafg_control_amp_set1(ctl, lmute, rmute, left, right, 1);
sys/dev/hdaudio/hdafg.c
2369
const struct hdaudio_control *ctl)
sys/dev/hdaudio/hdafg.c
2374
switch (ctl->ctl_widget->w_type) {
sys/dev/hdaudio/hdafg.c
2379
w = ctl->ctl_childwidget;
sys/dev/hdaudio/hdafg.c
2407
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2411
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
2413
if (ctl->ctl_enable == false)
sys/dev/hdaudio/hdafg.c
2416
z = ctl->ctl_offset;
sys/dev/hdaudio/hdafg.c
2417
if (z > ctl->ctl_step)
sys/dev/hdaudio/hdafg.c
2418
z = ctl->ctl_step;
sys/dev/hdaudio/hdafg.c
2420
if (hdafg_mixer_child_is_input(sc, ctl))
sys/dev/hdaudio/hdafg.c
2421
hdafg_control_amp_set(ctl, HDAUDIO_AMP_MUTE_ALL, z, z);
sys/dev/hdaudio/hdafg.c
2423
hdafg_control_amp_set(ctl, HDAUDIO_AMP_MUTE_NONE, z, z);
sys/dev/hdaudio/hdafg.c
2592
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2616
ctl = hdafg_control_amp_get(sc, w->w_nid,
sys/dev/hdaudio/hdafg.c
2618
if (ctl) {
sys/dev/hdaudio/hdafg.c
2619
if (HDAUDIO_CONTROL_GIVE(ctl) & need)
sys/dev/hdaudio/hdafg.c
2620
ctl->ctl_audiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2622
ctl->ctl_paudiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2623
need &= ~HDAUDIO_CONTROL_GIVE(ctl);
sys/dev/hdaudio/hdafg.c
2648
ctl = hdafg_control_amp_get(sc, w->w_nid,
sys/dev/hdaudio/hdafg.c
2650
if (ctl) {
sys/dev/hdaudio/hdafg.c
2651
if (HDAUDIO_CONTROL_GIVE(ctl) & need)
sys/dev/hdaudio/hdafg.c
2652
ctl->ctl_audiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2654
ctl->ctl_paudiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2655
need &= ~HDAUDIO_CONTROL_GIVE(ctl);
sys/dev/hdaudio/hdafg.c
266
#define HDAUDIO_CONTROL_GIVE(ctl) ((ctl)->ctl_step ? 1 : 0)
sys/dev/hdaudio/hdafg.c
2683
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2722
ctl = hdafg_control_amp_get(sc, w->w_nid,
sys/dev/hdaudio/hdafg.c
2724
if (ctl) {
sys/dev/hdaudio/hdafg.c
2725
if (HDAUDIO_CONTROL_GIVE(ctl) & need)
sys/dev/hdaudio/hdafg.c
2726
ctl->ctl_audiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2728
ctl->ctl_paudiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2729
need &= ~HDAUDIO_CONTROL_GIVE(ctl);
sys/dev/hdaudio/hdafg.c
2741
ctl = hdafg_control_amp_get(sc, w->w_nid,
sys/dev/hdaudio/hdafg.c
2743
if (ctl) {
sys/dev/hdaudio/hdafg.c
2744
if (HDAUDIO_CONTROL_GIVE(ctl) & tneed)
sys/dev/hdaudio/hdafg.c
2745
ctl->ctl_audiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2747
ctl->ctl_paudiomask |= (1 << audiodev);
sys/dev/hdaudio/hdafg.c
2748
tneed &= ~HDAUDIO_CONTROL_GIVE(ctl);
sys/dev/hdaudio/hdafg.c
2759
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
2797
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
2798
if (ctl->ctl_audiomask == 0)
sys/dev/hdaudio/hdafg.c
2799
ctl->ctl_audiomask = ctl->ctl_paudiomask;
sys/dev/hdaudio/hdafg.c
2807
struct hdaudio_control *ctl, *masterctl = NULL;
sys/dev/hdaudio/hdafg.c
2818
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
2819
if (ctl->ctl_enable == false ||
sys/dev/hdaudio/hdafg.c
2820
ctl->ctl_audiomask == 0)
sys/dev/hdaudio/hdafg.c
2822
audiomask |= ctl->ctl_audiomask;
sys/dev/hdaudio/hdafg.c
2823
if (ctl->ctl_step > 0)
sys/dev/hdaudio/hdafg.c
2825
if (ctl->ctl_mute)
sys/dev/hdaudio/hdafg.c
2937
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
2938
if (ctl->ctl_enable == false ||
sys/dev/hdaudio/hdafg.c
2939
ctl->ctl_audiomask == 0)
sys/dev/hdaudio/hdafg.c
2941
audiodev = ffs(ctl->ctl_audiomask) - 1;
sys/dev/hdaudio/hdafg.c
2964
if (ctl->ctl_step > 0) {
sys/dev/hdaudio/hdafg.c
2975
mx[index].mx_ctl = ctl;
sys/dev/hdaudio/hdafg.c
2980
mx[index].mx_di.un.v.delta = 256 / ctl->ctl_step;
sys/dev/hdaudio/hdafg.c
2987
if (ctl->ctl_mute) {
sys/dev/hdaudio/hdafg.c
2988
if (ctl->ctl_step > 0) {
sys/dev/hdaudio/hdafg.c
3009
mx[index].mx_ctl = ctl;
sys/dev/hdaudio/hdafg.c
3891
struct hdaudio_control *ctl = sc->sc_ctls;
sys/dev/hdaudio/hdafg.c
3923
if (ctl)
sys/dev/hdaudio/hdafg.c
3924
kmem_free(ctl, sc->sc_nctls * sizeof(*ctl));
sys/dev/hdaudio/hdafg.c
4156
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
4162
ctl = mx->mx_ctl;
sys/dev/hdaudio/hdafg.c
4163
if (ctl == NULL) {
sys/dev/hdaudio/hdafg.c
4189
divisor = 255 / ctl->ctl_step;
sys/dev/hdaudio/hdafg.c
4190
hdafg_control_amp_set(ctl, HDAUDIO_AMP_MUTE_NONE,
sys/dev/hdaudio/hdafg.c
4195
hdafg_control_amp_set(ctl,
sys/dev/hdaudio/hdafg.c
4197
ctl->ctl_left, ctl->ctl_right);
sys/dev/hdaudio/hdafg.c
4212
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
4219
ctl = mx->mx_ctl;
sys/dev/hdaudio/hdafg.c
4220
if (ctl == NULL) {
sys/dev/hdaudio/hdafg.c
4246
factor = 255 / ctl->ctl_step;
sys/dev/hdaudio/hdafg.c
4247
mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = ctl->ctl_left * factor;
sys/dev/hdaudio/hdafg.c
4248
mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = ctl->ctl_right * factor;
sys/dev/hdaudio/hdafg.c
4251
mc->un.ord = (ctl->ctl_muted || ctl->ctl_forcemute) ? 1 : 0;
sys/dev/hdaudio/hdafg.c
446
struct hdaudio_control *ctl;
sys/dev/hdaudio/hdafg.c
452
ctl = &sc->sc_ctls[i];
sys/dev/hdaudio/hdafg.c
453
if (ctl->ctl_enable == false)
sys/dev/hdaudio/hdafg.c
455
if (ctl->ctl_widget->w_nid != nid)
sys/dev/hdaudio/hdafg.c
457
if (dir && ctl->ctl_ndir != dir)
sys/dev/hdaudio/hdafg.c
459
if (index >= 0 && ctl->ctl_ndir == HDAUDIO_PINDIR_IN &&
sys/dev/hdaudio/hdafg.c
460
ctl->ctl_dir == ctl->ctl_ndir && ctl->ctl_index != index)
sys/dev/hdaudio/hdafg.c
464
return ctl;
sys/dev/hpc/apm/apmdev.c
734
int ctl = APM(dev);
sys/dev/hpc/apm/apmdev.c
749
switch (ctl) {
sys/dev/hpc/apm/apmdev.c
782
int ctl = APM(dev);
sys/dev/hpc/apm/apmdev.c
788
switch (ctl) {
sys/dev/i2c/em3027.c
152
} ctl;
sys/dev/i2c/em3027.c
167
error = em3027rtc_read(sc, EM3027_CONTROL_BASE, &ctl, sizeof(ctl));
sys/dev/i2c/em3027.c
176
aprint_debug_dev(sc->sc_dev, "status=0x%02x\n", ctl.status);
sys/dev/i2c/em3027.c
179
if (ctl.status & EM3027_STATUS_VLOW2) {
sys/dev/i2c/em3027.c
183
else if (ctl.status & EM3027_STATUS_VLOW1) {
sys/dev/i2c/em3027.c
188
ctl.status = EM3027_STATUS_POWER_ON;
sys/dev/i2c/em3027.c
192
aprint_debug_dev(sc->sc_dev, "on/off=0x%02x\n", ctl.onoff);
sys/dev/i2c/em3027.c
194
if ((ctl.onoff & EM3027_ONOFF_SR) == 0) {
sys/dev/i2c/em3027.c
196
ctl.onoff |= EM3027_ONOFF_SR;
sys/dev/i2c/em3027.c
199
if ((ctl.onoff & EM3027_ONOFF_EEREF) == 0) {
sys/dev/i2c/em3027.c
201
ctl.onoff |= EM3027_ONOFF_EEREF;
sys/dev/i2c/em3027.c
204
ctl.onoff &= ~EM3027_ONOFF_TR;
sys/dev/i2c/em3027.c
206
if (ctl.onoff & EM3027_ONOFF_TI) {
sys/dev/i2c/em3027.c
208
ctl.onoff &= ~EM3027_ONOFF_TI;
sys/dev/i2c/em3027.c
211
if ((ctl.onoff & EM3027_ONOFF_WA) == 0) {
sys/dev/i2c/em3027.c
213
ctl.onoff |= EM3027_ONOFF_WA;
sys/dev/i2c/em3027.c
218
if (ctl.irq_ctl != 0)
sys/dev/i2c/em3027.c
220
"irq=0x%02x - disabling all\n", ctl.irq_ctl);
sys/dev/i2c/em3027.c
221
ctl.irq_ctl = 0;
sys/dev/i2c/em3027.c
222
ctl.irq_flags = 0;
sys/dev/i2c/em3027.c
226
error = em3027rtc_write(sc, EM3027_CONTROL_BASE, &ctl, sizeof(ctl));
sys/dev/ic/ac97.c
1241
mixer_ctrl_t ctl;
sys/dev/ic/ac97.c
1568
memset(&ctl, 0, sizeof(ctl));
sys/dev/ic/ac97.c
1587
ctl.type = AUDIO_MIXER_ENUM;
sys/dev/ic/ac97.c
1588
ctl.un.ord = 0;
sys/dev/ic/ac97.c
1590
ctl.dev = ac97_get_portnum_by_name(&as->codec_if,
sys/dev/ic/ac97.c
1592
ac97_mixer_set_port(&as->codec_if, &ctl);
sys/dev/ic/ac97.c
1594
ctl.type = AUDIO_MIXER_ENUM;
sys/dev/ic/ac97.c
1595
ctl.un.ord = 0;
sys/dev/ic/ac97.c
1596
ctl.dev = ac97_get_portnum_by_name(&as->codec_if, AudioCrecord,
sys/dev/ic/ac97.c
1598
ac97_mixer_set_port(&as->codec_if, &ctl);
sys/dev/ic/ac97.c
1601
ctl.type = AUDIO_MIXER_VALUE;
sys/dev/ic/ac97.c
1602
ctl.un.value.num_channels = 2;
sys/dev/ic/ac97.c
1603
ctl.un.value.level[AUDIO_MIXER_LEVEL_LEFT] = \
sys/dev/ic/ac97.c
1604
ctl.un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 127;
sys/dev/ic/ac97.c
1605
ctl.dev = ac97_get_portnum_by_name(&as->codec_if, AudioCoutputs,
sys/dev/ic/ac97.c
1607
ac97_mixer_set_port(&as->codec_if, &ctl);
sys/dev/ic/ac97.c
1608
ctl.dev = ac97_get_portnum_by_name(&as->codec_if, AudioCoutputs,
sys/dev/ic/ac97.c
1610
ac97_mixer_set_port(&as->codec_if, &ctl);
sys/dev/ic/ac97.c
1611
ctl.un.value.num_channels = 1;
sys/dev/ic/ac97.c
1612
ctl.dev = ac97_get_portnum_by_name(&as->codec_if, AudioCoutputs,
sys/dev/ic/ac97.c
1614
ac97_mixer_set_port(&as->codec_if, &ctl);
sys/dev/ic/ac97.c
1615
ctl.dev = ac97_get_portnum_by_name(&as->codec_if, AudioCoutputs,
sys/dev/ic/ac97.c
1617
ac97_mixer_set_port(&as->codec_if, &ctl);
sys/dev/ic/arn5008.c
2633
uint8_t ctl, const struct ar_cal_target_power_leg *tgt, int nchans,
sys/dev/ic/arn5008.c
2665
uint8_t ctl, const struct ar_cal_target_power_ht *tgt, int nchans,
sys/dev/ic/arn9003.c
3304
uint8_t ctl, const uint8_t *fbins,
sys/dev/ic/arn9003.c
3336
uint8_t ctl, const uint8_t *fbins,
sys/dev/ic/atw.c
3518
int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg;
sys/dev/ic/atw.c
3792
ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK));
sys/dev/ic/atw.c
3796
ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));
sys/dev/ic/atw.c
3811
txd->at_ctl = ctl |
sys/dev/ic/bwi.c
7826
bwi_tx_frame_data_pio(struct bwi_softc *sc, u_int idx, uint32_t *ctl,
sys/dev/ic/bwi.c
7831
*ctl |= BWI_PIO_TXCTL_VALID_BYTES(4);
sys/dev/ic/bwi.c
7832
CSR_WRITE_4(sc, BWI_PIO_TXCTL(idx), *ctl);
sys/dev/ic/bwi.c
7841
*ctl &= ~BWI_PIO_TXCTL_VALID;
sys/dev/ic/bwi.c
7842
*ctl |= BWI_PIO_TXCTL_VALID_BYTES(buflen);
sys/dev/ic/bwi.c
7843
CSR_WRITE_4(sc, BWI_PIO_TXCTL(idx), *ctl);
sys/dev/ic/bwi.c
7855
uint32_t ctl;
sys/dev/ic/bwi.c
7861
ctl = CSR_READ_4(sc, BWI_PIO_TXCTL(idx));
sys/dev/ic/bwi.c
7862
ctl |= BWI_PIO_TXCTL_FREADY;
sys/dev/ic/bwi.c
7863
ctl &= ~BWI_PIO_TXCTL_EOF;
sys/dev/ic/bwi.c
7865
bwi_tx_frame_data_pio(sc, idx, &ctl, txbuf, pktlen);
sys/dev/ic/bwi.c
7867
ctl |= BWI_PIO_TXCTL_EOF;
sys/dev/ic/bwi.c
7868
CSR_WRITE_4(sc, BWI_PIO_TXCTL(idx), ctl);
sys/dev/ic/ds1286reg.h
148
u_int ctl; \
sys/dev/ic/ds1286reg.h
151
ctl = ds1286_read(sc, DS1286_CONTROL); \
sys/dev/ic/ds1286reg.h
152
ds1286_write(sc, DS1286_CONTROL, ctl | DS1286_TE); \
sys/dev/ic/ds1286reg.h
159
ds1286_write(sc, DS1286_CONTROL, ctl); \
sys/dev/ic/ds1286reg.h
169
u_int ctl; \
sys/dev/ic/ds1286reg.h
172
ctl = ds1286_read(sc, DS1286_CONTROL); \
sys/dev/ic/ds1286reg.h
173
ds1286_write(sc, DS1286_CONTROL, ctl | DS1286_TE); \
sys/dev/ic/ds1286reg.h
180
ds1286_write(sc, DS1286_CONTROL, ctl); \
sys/dev/ic/ds1687reg.h
218
u_int ctl; \
sys/dev/ic/ds1687reg.h
221
ctl = ds1687_read(sc, DS1687_CONTROLB); \
sys/dev/ic/ds1687reg.h
222
ds1687_write(sc, DS1687_CONTROLB, ctl | DS1687_SET); \
sys/dev/ic/ds1687reg.h
234
ds1687_write(sc, DS1687_CONTROLB, ctl); \
sys/dev/ic/ds1687reg.h
244
u_int ctl; \
sys/dev/ic/ds1687reg.h
247
ctl = ds1687_read(sc, DS1687_CONTROLB); \
sys/dev/ic/ds1687reg.h
248
ds1687_write(sc, DS1687_CONTROLB, ctl | DS1687_SET); \
sys/dev/ic/ds1687reg.h
260
ds1687_write(sc, DS1687_CONTROLB, ctl); \
sys/dev/ic/isp.c
4466
isp_control(ispsoftc_t *isp, ispctl_t ctl, ...)
sys/dev/ic/isp.c
4474
switch (ctl) {
sys/dev/ic/isp.c
4486
va_start(ap, ctl);
sys/dev/ic/isp.c
4506
va_start(ap, ctl);
sys/dev/ic/isp.c
4600
va_start(ap, ctl);
sys/dev/ic/isp.c
4703
va_start(ap, ctl);
sys/dev/ic/isp.c
4713
va_start(ap, ctl);
sys/dev/ic/isp.c
4727
va_start(ap, ctl);
sys/dev/ic/isp.c
4737
va_start(ap, ctl);
sys/dev/ic/isp.c
4747
va_start(ap, ctl);
sys/dev/ic/isp.c
4771
va_start(ap, ctl);
sys/dev/ic/isp.c
4783
va_start(ap, ctl);
sys/dev/ic/isp.c
4808
va_start(ap, ctl);
sys/dev/ic/isp.c
4819
va_start(ap, ctl);
sys/dev/ic/isp.c
4838
isp_prt(isp, ISP_LOGERR, "Unknown Control Opcode 0x%x", ctl);
sys/dev/ic/opl.c
694
setting = midictl_read(&ms->ctl, chan, MIDI_CTRL_PAN_MSB, 8192);
sys/dev/ic/rng200.c
53
uint32_t ctl, rng, rbg;
sys/dev/ic/rng200.c
56
ctl = READ4(sc, RNG200_CONTROL);
sys/dev/ic/rng200.c
57
ctl &= ~RNG200_RBG_MASK;
sys/dev/ic/rng200.c
58
WRITE4(sc, RNG200_CONTROL, ctl);
sys/dev/ic/rng200.c
72
WRITE4(sc, RNG200_CONTROL, ctl | RNG200_RBG_ENABLE);
sys/dev/ic/rtw.c
1353
uint32_t ctl, octl, obuf;
sys/dev/ic/rtw.c
1363
ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
sys/dev/ic/rtw.c
1367
ctl |= RTW_RXCTL_EOR;
sys/dev/ic/rtw.c
1370
rd->rd_ctl = htole32(ctl);
sys/dev/ic/rtw.c
1391
rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick)
sys/dev/ic/rtw.c
1397
rs = &ctl[i];
sys/dev/marvell/gt.c
605
uint32_t ctl;
sys/dev/marvell/gt.c
607
ctl = gt_read(gt, GT_ECC_Ctl);
sys/dev/marvell/gt.c
608
ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */
sys/dev/marvell/gt.c
609
gt_write(gt, GT_ECC_Ctl, ctl);
sys/dev/marvell/mvspi.c
107
int ctl;
sys/dev/marvell/mvspi.c
126
ctl = GETREG(sc, MVSPI_INTCONF_REG);
sys/dev/marvell/mvspi.c
128
ctl &= MVSPI_DIRHS_MASK;
sys/dev/marvell/mvspi.c
129
ctl &= MVSPI_1BYTE_MASK;
sys/dev/marvell/mvspi.c
131
PUTREG(sc, MVSPI_INTCONF_REG, ctl);
sys/dev/marvell/mvspi.c
156
uint32_t ctl = 0, spr, sppr;
sys/dev/marvell/mvspi.c
168
ctl &= ~(MVSPI_CPOL_MASK);
sys/dev/marvell/mvspi.c
170
ctl &= MVSPI_CPHA_MASK;
sys/dev/marvell/mvspi.c
173
ctl |= MVSPI_CPOL_MASK;
sys/dev/marvell/mvspi.c
174
ctl &= MVSPI_CPHA_MASK;
sys/dev/marvell/mvspi.c
177
ctl &= ~(MVSPI_CPOL_MASK);
sys/dev/marvell/mvspi.c
178
ctl |= ~(MVSPI_CPHA_MASK);
sys/dev/marvell/mvspi.c
181
ctl |= MVSPI_CPOL_MASK;
sys/dev/marvell/mvspi.c
182
ctl |= ~(MVSPI_CPHA_MASK);
sys/dev/marvell/mvspi.c
226
ctl &= ~(MVSPI_SPR_MASK);
sys/dev/marvell/mvspi.c
227
ctl &= ~(MVSPI_SPPR_MASK);
sys/dev/marvell/mvspi.c
228
ctl |= best_spr;
sys/dev/marvell/mvspi.c
233
ctl |= best_spprhi;
sys/dev/marvell/mvspi.c
238
ctl |= best_sppr0;
sys/dev/marvell/mvspi.c
240
PUTREG(sc, MVSPI_INTCONF_REG, ctl);
sys/dev/marvell/mvspi.c
263
int ctl;
sys/dev/marvell/mvspi.c
273
ctl = GETREG(sc, MVSPI_CTRL_REG);
sys/dev/marvell/mvspi.c
274
ctl |= MVSPI_CSNACT_MASK;
sys/dev/marvell/mvspi.c
275
PUTREG(sc, MVSPI_CTRL_REG, ctl);
sys/dev/marvell/mvspi.c
281
int ctl = GETREG(sc, MVSPI_CTRL_REG);
sys/dev/marvell/mvspi.c
282
ctl &= ~(MVSPI_CSNACT_MASK);
sys/dev/marvell/mvspi.c
283
PUTREG(sc, MVSPI_CTRL_REG, ctl);
sys/dev/marvell/mvspi.c
291
int i, j, ctl;
sys/dev/marvell/mvspi.c
312
ctl = GETREG(sc, MVSPI_CTRL_REG);
sys/dev/marvell/mvspi.c
313
ctl &= ~(MVSPI_CR_SMEMRDY);
sys/dev/marvell/mvspi.c
314
PUTREG(sc, MVSPI_CTRL_REG, ctl);
sys/dev/midisyn.c
141
ms->ctl.lock = ms->lock;
sys/dev/midisyn.c
142
error = midictl_open(&ms->ctl);
sys/dev/midisyn.c
183
midictl_close(&ms->ctl);
sys/dev/midisyn.c
270
ms->ctl = (midictl) {
sys/dev/midisyn.c
402
midictl_change(&ms->ctl, chan, buf+1);
sys/dev/midisyn.c
510
midictl_read(&ms->ctl, chan, key, 100<<7));
sys/dev/midisyn.c
520
midictl_read(&ms->ctl, chan, key, 16383));
sys/dev/midisyn.c
535
w = midictl_rpn_read(&ms->ctl, chan, key, 2<<7);
sys/dev/midisyn.c
558
mp = midictl_rpn_read(&ms->ctl, chan, key, 8192);
sys/dev/midisyn.c
579
mp = midictl_rpn_read(&ms->ctl, chan, key, 64<<7) >> 7;
sys/dev/midisynvar.h
176
midictl ctl;
sys/dev/nvmm/nvmm.c
1001
ctl.nram = 0;
sys/dev/nvmm/nvmm.c
1005
ctl.nram += mach->hmap[i].size;
sys/dev/nvmm/nvmm.c
1008
ctl.pid = mach->owner->pid;
sys/dev/nvmm/nvmm.c
1009
ctl.time = mach->time;
sys/dev/nvmm/nvmm.c
1013
error = copyout(&ctl, args->data, sizeof(ctl));
sys/dev/nvmm/nvmm.c
984
struct nvmm_ctl_mach_info ctl;
sys/dev/nvmm/nvmm.c
989
if (args->size != sizeof(ctl))
sys/dev/nvmm/nvmm.c
991
error = copyin(args->data, &ctl, sizeof(ctl));
sys/dev/nvmm/nvmm.c
995
error = nvmm_machine_get(owner, ctl.machid, &mach, true);
sys/dev/nvmm/nvmm.c
999
ctl.nvcpus = mach->ncpus;
sys/dev/pci/alipm.c
227
u_int8_t ctl, st;
sys/dev/pci/alipm.c
292
ctl = ALIPM_SMB_HC_CMD_QUICK;
sys/dev/pci/alipm.c
294
ctl = ALIPM_SMB_HC_CMD_BYTE;
sys/dev/pci/alipm.c
296
ctl = ALIPM_SMB_HC_CMD_BDATA;
sys/dev/pci/alipm.c
298
ctl = ALIPM_SMB_HC_CMD_WDATA;
sys/dev/pci/alipm.c
299
bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HC, ctl);
sys/dev/pci/cxgb/cxgb_offload.c
1371
if (dev->ctl(dev, GET_TX_MAX_CHUNK, &t->tx_max_chunk) < 0 ||
sys/dev/pci/cxgb/cxgb_offload.c
1372
dev->ctl(dev, GET_MAX_OUTSTANDING_WR, &t->max_wrs) < 0 ||
sys/dev/pci/cxgb/cxgb_offload.c
1373
dev->ctl(dev, GET_L2T_CAPACITY, &l2t_capacity) < 0 ||
sys/dev/pci/cxgb/cxgb_offload.c
1374
dev->ctl(dev, GET_MTUS, &mtutab) < 0 ||
sys/dev/pci/cxgb/cxgb_offload.c
1375
dev->ctl(dev, GET_TID_RANGE, &tid_range) < 0 ||
sys/dev/pci/cxgb/cxgb_offload.c
1376
dev->ctl(dev, GET_STID_RANGE, &stid_range) < 0)
sys/dev/pci/cxgb/cxgb_offload.c
1471
tdev->ctl = cxgb_offload_ctl;
sys/dev/pci/cxgb/cxgb_t3_hw.c
345
unsigned int ctl;
sys/dev/pci/cxgb/cxgb_t3_hw.c
352
err = mdio_read(phy, mmd, MII_BMCR, &ctl);
sys/dev/pci/cxgb/cxgb_t3_hw.c
355
ctl &= BMCR_RESET;
sys/dev/pci/cxgb/cxgb_t3_hw.c
356
if (ctl)
sys/dev/pci/cxgb/cxgb_t3_hw.c
358
} while (ctl && --wait);
sys/dev/pci/cxgb/cxgb_t3_hw.c
360
return ctl ? -1 : 0;
sys/dev/pci/cxgb/cxgb_t3_hw.c
418
unsigned int ctl;
sys/dev/pci/cxgb/cxgb_t3_hw.c
420
err = mdio_read(phy, 0, MII_BMCR, &ctl);
sys/dev/pci/cxgb/cxgb_t3_hw.c
425
ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
sys/dev/pci/cxgb/cxgb_t3_hw.c
427
ctl |= BMCR_SPEED100;
sys/dev/pci/cxgb/cxgb_t3_hw.c
429
ctl |= BMCR_SPEED1000;
sys/dev/pci/cxgb/cxgb_t3_hw.c
432
ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
sys/dev/pci/cxgb/cxgb_t3_hw.c
434
ctl |= BMCR_FULLDPLX;
sys/dev/pci/cxgb/cxgb_t3_hw.c
436
if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
sys/dev/pci/cxgb/cxgb_t3_hw.c
437
ctl |= BMCR_ANENABLE;
sys/dev/pci/cxgb/cxgb_t3_hw.c
438
return mdio_write(phy, 0, MII_BMCR, ctl);
sys/dev/pci/cxgb/cxgb_toedev.h
105
int (*ctl)(struct toedev *dev, unsigned int req, void *data);
sys/dev/pci/eap.c
534
mixer_ctrl_t ctl;
sys/dev/pci/eap.c
641
ctl.dev = EAP_INPUT_SOURCE;
sys/dev/pci/eap.c
642
ctl.type = AUDIO_MIXER_SET;
sys/dev/pci/eap.c
643
ctl.un.mask = 1 << EAP_VOICE_VOL | 1 << EAP_FM_VOL |
sys/dev/pci/eap.c
646
eap_hw_if->set_port(&sc->sc_ei[EAP_I1], &ctl);
sys/dev/pci/eap.c
648
ctl.type = AUDIO_MIXER_VALUE;
sys/dev/pci/eap.c
649
ctl.un.value.num_channels = 1;
sys/dev/pci/eap.c
650
for (ctl.dev = EAP_MASTER_VOL; ctl.dev < EAP_MIC_VOL;
sys/dev/pci/eap.c
651
ctl.dev++) {
sys/dev/pci/eap.c
652
ctl.un.value.level[AUDIO_MIXER_LEVEL_MONO] = VOL_0DB;
sys/dev/pci/eap.c
653
eap_hw_if->set_port(&sc->sc_ei[EAP_I1], &ctl);
sys/dev/pci/eap.c
655
ctl.un.value.level[AUDIO_MIXER_LEVEL_MONO] = 0;
sys/dev/pci/eap.c
656
eap_hw_if->set_port(&sc->sc_ei[EAP_I1], &ctl);
sys/dev/pci/eap.c
657
ctl.dev = EAP_MIC_PREAMP;
sys/dev/pci/eap.c
658
ctl.type = AUDIO_MIXER_ENUM;
sys/dev/pci/eap.c
659
ctl.un.ord = 0;
sys/dev/pci/eap.c
660
eap_hw_if->set_port(&sc->sc_ei[EAP_I1], &ctl);
sys/dev/pci/eap.c
661
ctl.dev = EAP_RECORD_SOURCE;
sys/dev/pci/eap.c
662
ctl.type = AUDIO_MIXER_SET;
sys/dev/pci/eap.c
663
ctl.un.mask = 1 << EAP_MIC_VOL;
sys/dev/pci/eap.c
664
eap_hw_if->set_port(&sc->sc_ei[EAP_I1], &ctl);
sys/dev/pci/ichsmb.c
527
uint8_t ctl = 0, st;
sys/dev/pci/ichsmb.c
603
ctl = SMB_HC_CMD_QUICK;
sys/dev/pci/ichsmb.c
605
ctl = SMB_HC_CMD_BYTE;
sys/dev/pci/ichsmb.c
607
ctl = SMB_HC_CMD_BDATA;
sys/dev/pci/ichsmb.c
609
ctl = SMB_HC_CMD_WDATA;
sys/dev/pci/ichsmb.c
612
ctl |= SMB_HC_INTREN;
sys/dev/pci/ichsmb.c
615
ctl |= SMB_HC_START;
sys/dev/pci/ichsmb.c
616
bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HC, ctl);
sys/dev/pci/if_alc.c
1184
uint32_t cap, ctl, val;
sys/dev/pci/if_alc.c
1211
ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_alc.c
1213
if ((ctl & 0x08) != 0)
sys/dev/pci/if_alc.c
1219
state = ctl & 0x03;
sys/dev/pci/if_iwi.c
2081
uint32_t sentinel, ctl, sum;
sys/dev/pci/if_iwi.c
2144
ctl = IWI_CB_DEFAULT_CTL | mlen;
sys/dev/pci/if_iwi.c
2145
sum = ctl ^ cs ^ cd;
sys/dev/pci/if_iwi.c
2148
CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, ctl);
sys/dev/pci/if_iwm.c
5049
uint16_t ctl;
sys/dev/pci/if_iwm.c
5053
ctl = barfrm[1] << 8 | barfrm[0];
sys/dev/pci/if_iwm.c
5054
tid = (ctl & IEEE80211_BA_TID_INFO_MASK) >>
sys/dev/pci/if_iwnreg.h
695
uint16_t ctl;
sys/dev/pci/if_nfe.c
583
uint32_t ctl;
sys/dev/pci/if_nfe.c
594
ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
sys/dev/pci/if_nfe.c
595
NFE_WRITE(sc, NFE_PHY_CTL, ctl);
sys/dev/pci/nside.c
133
ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1);
sys/dev/pci/nside.c
135
ctl &= ~NATSEMI_CTRL1_INTAMASK;
sys/dev/pci/nside.c
137
ctl |= NATSEMI_CTRL1_INTAMASK;
sys/dev/pci/nside.c
138
pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl);
sys/dev/pci/nside.c
95
pcireg_t interface, ctl;
sys/dev/pci/pci_subr.c
1313
uint32_t ctl, mmc, mme;
sys/dev/pci/pci_subr.c
1316
ctl = *regs++;
sys/dev/pci/pci_subr.c
1317
mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
sys/dev/pci/pci_subr.c
1318
mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
sys/dev/pci/pci_subr.c
1322
printf(" Message Control register: 0x%04x\n", ctl >> 16);
sys/dev/pci/pci_subr.c
1323
onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
sys/dev/pci/pci_subr.c
1328
onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
sys/dev/pci/pci_subr.c
1329
onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
sys/dev/pci/pci_subr.c
1330
onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP);
sys/dev/pci/pci_subr.c
1331
onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN);
sys/dev/pci/pci_subr.c
1333
ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
sys/dev/pci/pci_subr.c
1334
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
sys/dev/pci/pci_subr.c
1339
if (ctl & PCI_MSI_CTL_EXTMDATA_CAP)
sys/dev/pci/pci_subr.c
1344
if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
sys/dev/pci/pci_subr.c
3387
pcireg_t reg, cap, ctl;
sys/dev/pci/pci_subr.c
3394
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
3407
printf(" ACS Control register: 0x%08x\n", ctl);
sys/dev/pci/pci_subr.c
3408
onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V);
sys/dev/pci/pci_subr.c
3409
onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B);
sys/dev/pci/pci_subr.c
3410
onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R);
sys/dev/pci/pci_subr.c
3411
onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C);
sys/dev/pci/pci_subr.c
3412
onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U);
sys/dev/pci/pci_subr.c
3413
onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E);
sys/dev/pci/pci_subr.c
3414
onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T);
sys/dev/pci/pci_subr.c
3430
pcireg_t reg, cap, ctl;
sys/dev/pci/pci_subr.c
3436
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
3442
printf(" Control register: 0x%08x\n", ctl);
sys/dev/pci/pci_subr.c
3452
pcireg_t reg, cap, ctl;
sys/dev/pci/pci_subr.c
3459
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
3469
printf(" Control register: 0x%04x\n", ctl);
sys/dev/pci/pci_subr.c
3603
pcireg_t reg, cap, ctl;
sys/dev/pci/pci_subr.c
3612
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
3624
printf(" Control Register: 0x%04x\n", ctl);
sys/dev/pci/pci_subr.c
3671
pcireg_t reg, ctl, sta;
sys/dev/pci/pci_subr.c
3676
ctl = reg & 0xffff;
sys/dev/pci/pci_subr.c
3678
printf(" Control Register: 0x%04x\n", ctl);
sys/dev/pci/pci_subr.c
3702
pcireg_t cap, ctl;
sys/dev/pci/pci_subr.c
3709
ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))];
sys/dev/pci/pci_subr.c
3710
bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR);
sys/dev/pci/pci_subr.c
3739
ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))];
sys/dev/pci/pci_subr.c
3740
printf(" Control register(%u): 0x%08x\n", n, ctl);
sys/dev/pci/pci_subr.c
3742
PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX));
sys/dev/pci/pci_subr.c
3745
<< PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ),
sys/dev/pci/pci_subr.c
3982
pcireg_t reg, cap, ctl;
sys/dev/pci/pci_subr.c
3989
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
3996
printf(" PASID Control Register: 0x%04x\n", ctl);
sys/dev/pci/pci_subr.c
4005
pcireg_t reg, cap, ctl;
sys/dev/pci/pci_subr.c
4012
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
4019
printf(" LNR Control register: 0x%04x\n", ctl);
sys/dev/pci/pci_subr.c
4043
pcireg_t reg, cap, ctl, stat, errsrc;
sys/dev/pci/pci_subr.c
4051
ctl = reg >> 16;
sys/dev/pci/pci_subr.c
4064
printf(" DPC Control register: 0x%04x\n", ctl);
sys/dev/pci/piixpm.c
633
uint8_t ctl = 0, st;
sys/dev/pci/piixpm.c
675
ctl = PIIX_SMB_HC_CMD_QUICK;
sys/dev/pci/piixpm.c
677
ctl = PIIX_SMB_HC_CMD_BYTE;
sys/dev/pci/piixpm.c
679
ctl = PIIX_SMB_HC_CMD_BDATA;
sys/dev/pci/piixpm.c
681
ctl = PIIX_SMB_HC_CMD_WDATA;
sys/dev/pci/piixpm.c
721
ctl |= PIIX_SMB_HC_INTREN;
sys/dev/pci/piixpm.c
724
ctl |= PIIX_SMB_HC_START;
sys/dev/pci/piixpm.c
725
bus_space_write_1(sc->sc_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl);
sys/dev/pci/universe_pci.c
172
u_int32_t ctl = 0x80000000;
sys/dev/pci/universe_pci.c
176
ctl |= 0x00020000;
sys/dev/pci/universe_pci.c
179
ctl |= 0x00010000;
sys/dev/pci/universe_pci.c
187
ctl |= 0x00001000;
sys/dev/pci/universe_pci.c
189
ctl |= 0x00004000;
sys/dev/pci/universe_pci.c
191
ctl |= 0x00800000;
sys/dev/pci/universe_pci.c
193
ctl |= 0x00400000;
sys/dev/pci/universe_pci.c
199
d->devname, wnd, vmebase, vmebase + len, pcibase, ctl);
sys/dev/pci/universe_pci.c
205
write_pcislv(d, wnd, lsi_ctl, ctl);
sys/dev/pci/universe_pci.c
222
u_int32_t ctl = 0x80000000;
sys/dev/pci/universe_pci.c
226
ctl |= 0x00020000;
sys/dev/pci/universe_pci.c
229
ctl |= 0x00010000;
sys/dev/pci/universe_pci.c
237
ctl |= 0x00200000;
sys/dev/pci/universe_pci.c
239
ctl |= 0x00300000; /* both */
sys/dev/pci/universe_pci.c
241
ctl |= 0x00800000;
sys/dev/pci/universe_pci.c
243
ctl |= 0x00c00000; /* both */
sys/dev/pci/universe_pci.c
247
d->devname, wnd, pcibase, pcibase + len, vmebase, ctl);
sys/dev/pci/universe_pci.c
253
write_vmeslv(d, wnd, vsi_ctl, ctl);
sys/dev/pci/virtio_pci.c
1148
pcireg_t ctl;
sys/dev/pci/virtio_pci.c
1217
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
sys/dev/pci/virtio_pci.c
1218
ctl &= ~PCI_MSIX_CTL_ENABLE;
sys/dev/pci/virtio_pci.c
1219
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
sys/dev/pci/xmm7360.c
426
struct control ctl;
sys/dev/pci/xmm7360.c
648
xmm->cp->ctl.status = xmm->cp_phys + offsetof(struct control_page, status);
sys/dev/pci/xmm7360.c
649
xmm->cp->ctl.s_wptr = xmm->cp_phys + offsetof(struct control_page, s_wptr);
sys/dev/pci/xmm7360.c
650
xmm->cp->ctl.s_rptr = xmm->cp_phys + offsetof(struct control_page, s_rptr);
sys/dev/pci/xmm7360.c
651
xmm->cp->ctl.c_wptr = xmm->cp_phys + offsetof(struct control_page, c_wptr);
sys/dev/pci/xmm7360.c
652
xmm->cp->ctl.c_rptr = xmm->cp_phys + offsetof(struct control_page, c_rptr);
sys/dev/pci/xmm7360.c
653
xmm->cp->ctl.c_ring = xmm->cp_phys + offsetof(struct control_page, c_ring);
sys/dev/pci/xmm7360.c
654
xmm->cp->ctl.c_ring_size = CMD_RING_SIZE;
sys/dev/scsipi/atapi_tape.h
71
u_int16_t ctl; /* continuous transfer limit */
sys/dev/usb/if_axen.c
366
uint16_t ctl, temp;
sys/dev/usb/if_axen.c
413
ctl = le16toh(wval);
sys/dev/usb/if_axen.c
414
ctl |= AXEN_PHYPWR_RSTCTL_AUTODETACH;
sys/dev/usb/if_axen.c
415
wval = htole16(ctl);
sys/dev/usb/if_axen.c
419
ctl);
sys/dev/usb/if_axen.c
469
ctl = AXEN_RXCTL_IPE | AXEN_RXCTL_DROPCRCERR | AXEN_RXCTL_AUTOB;
sys/dev/usb/if_axen.c
470
wval = htole16(ctl);
sys/dev/usb/if_axen.c
480
ctl = AXEN_MEDIUM_GIGA | AXEN_MEDIUM_FDX | AXEN_MEDIUM_EN_125MHZ |
sys/dev/usb/if_axen.c
483
wval = htole16(ctl);
sys/dev/usb/if_axen.c
484
DPRINTF(("axen: set to medium mode: 0x%04x\n", ctl));
sys/dev/usb/if_cue.c
613
int i, ctl;
sys/dev/usb/if_cue.c
636
ctl = CUE_ETHCTL_RX_ON | CUE_ETHCTL_MCAST_ON;
sys/dev/usb/if_cue.c
638
ctl |= CUE_ETHCTL_PROMISC;
sys/dev/usb/if_cue.c
639
cue_csr_write_1(un, CUE_ETHCTL, ctl);
sys/dev/usb/if_mos.c
520
u_int8_t ctl;
sys/dev/usb/if_mos.c
525
ctl = mos_reg_read_1(un, MOS_CTL);
sys/dev/usb/if_mos.c
526
ctl &= ~(MOS_CTL_RX_PROMISC | MOS_CTL_ALLMULTI | MOS_CTL_TX_ENB |
sys/dev/usb/if_mos.c
529
mos_reg_write_1(un, MOS_CTL, ctl);
sys/dev/usb/ohci.c
1027
ctl = OREAD4(sc, OHCI_CONTROL);
sys/dev/usb/ohci.c
1028
ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
sys/dev/usb/ohci.c
1029
ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
sys/dev/usb/ohci.c
1033
OWRITE4(sc, OHCI_CONTROL, ctl);
sys/dev/usb/ohci.c
1179
uint32_t ctl;
sys/dev/usb/ohci.c
1191
ctl = sc->sc_control;
sys/dev/usb/ohci.c
1193
ctl = OREAD4(sc, OHCI_CONTROL);
sys/dev/usb/ohci.c
1194
ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME);
sys/dev/usb/ohci.c
1195
OWRITE4(sc, OHCI_CONTROL, ctl);
sys/dev/usb/ohci.c
1197
ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL);
sys/dev/usb/ohci.c
1198
OWRITE4(sc, OHCI_CONTROL, ctl);
sys/dev/usb/ohci.c
1209
uint32_t ctl;
sys/dev/usb/ohci.c
1211
ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
sys/dev/usb/ohci.c
1217
sc->sc_control = ctl;
sys/dev/usb/ohci.c
1221
ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND);
sys/dev/usb/ohci.c
1222
OWRITE4(sc, OHCI_CONTROL, ctl);
sys/dev/usb/ohci.c
811
uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
sys/dev/usb/ohci.c
942
ctl = OREAD4(sc, OHCI_CONTROL);
sys/dev/usb/ohci.c
943
rwc = ctl & OHCI_RWC;
sys/dev/usb/ohci.c
949
if (ctl & OHCI_IR) {
sys/dev/usb/ohci.c
957
for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
sys/dev/usb/ohci.c
959
ctl = OREAD4(sc, OHCI_CONTROL);
sys/dev/usb/ohci.c
962
if ((ctl & OHCI_IR) == 0) {
sys/dev/usb/ohci.c
974
} else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) {
sys/dev/usb/ohci.c
977
if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) {
sys/dev/usb/uaudio.c
1426
int unit, int ctl, struct mixerctl *mc)
sys/dev/usb/uaudio.c
1434
switch (ctl) {
sys/dev/usb/uaudio.c
1534
int chan, ctl, i, unit;
sys/dev/usb/uaudio.c
1569
for (ctl = MUTE_CONTROL; ctl <= LOUDNESS_CONTROL; ctl++) {
sys/dev/usb/uaudio.c
1570
fumask = FU_MASK(ctl);
sys/dev/usb/uaudio.c
1572
ctl, fumask);
sys/dev/usb/uaudio.c
1575
mix.wValue[0] = MAKE(ctl, 0);
sys/dev/usb/uaudio.c
1580
mix.wValue[i-1] = MAKE(ctl, i);
sys/dev/usb/uaudio.c
1588
uaudio_add_feature_mixer(sc, &iot[id], unit, ctl, &mix);
sys/dev/usb/uaudio.c
1622
for (ctl = MUTE_CONTROL; ctl <= OVERFLOW_CONTROL; ctl++) {
sys/dev/usb/uaudio.c
1623
fumask = V2_FU_MASK(ctl);
sys/dev/usb/uaudio.c
1625
ctl, fumask);
sys/dev/usb/uaudio.c
1629
mix.wValue[0] = MAKE(ctl, 0);
sys/dev/usb/uaudio.c
1634
mix.wValue[i-1] = MAKE(ctl, i);
sys/dev/usb/uaudio.c
1642
uaudio_add_feature_mixer(sc, &iot[id], unit, ctl, &mix);
sys/dev/usb/uftdi.c
585
int ctl;
sys/dev/usb/uftdi.c
595
ctl = onoff ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW;
sys/dev/usb/uftdi.c
598
ctl = onoff ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW;
sys/dev/usb/uftdi.c
608
USETW(req.wValue, ctl);
sys/dev/vme/xd.c
500
struct xd_iopb_ctrl *ctl;
sys/dev/vme/xd.c
641
ctl = (struct xd_iopb_ctrl *) &xdc->iopbase[rqno];
sys/dev/vme/xd.c
642
if (ctl->ctype != XDCT_753) {
sys/dev/vme/xd.c
650
ctl->eprom_partno, ctl->eprom_lvl, ctl->eprom_rev);
sys/kern/subr_blist.c
1130
panic(const char *ctl, ...)
sys/kern/subr_blist.c
1134
va_start(va, ctl);
sys/kern/subr_blist.c
1135
vfprintf(stderr, ctl, va);
sys/kern/subr_blist.c
121
void panic(const char *ctl, ...) __printflike(1, 2);
sys/modules/examples/executor/executor.c
54
static once_t ctl;
sys/modules/examples/executor/executor.c
55
static ONCE_DECL(ctl);
sys/modules/examples/executor/executor.c
77
RUN_ONCE(&ctl, runonce_example);
sys/netbt/hci_socket.c
799
struct mbuf *m0, *ctlmsg, **ctl;
sys/netbt/hci_socket.c
875
ctl = &ctlmsg;
sys/netbt/hci_socket.c
879
*ctl = sbcreatecontrol(&dir, sizeof(dir),
sys/netbt/hci_socket.c
882
if (*ctl != NULL)
sys/netbt/hci_socket.c
883
ctl = &((*ctl)->m_next);
sys/netbt/hci_socket.c
889
*ctl = sbcreatecontrol(&tv, sizeof(tv),
sys/netbt/hci_socket.c
892
if (*ctl != NULL)
sys/netbt/hci_socket.c
893
ctl = &((*ctl)->m_next);
sys/netinet/tcp_input.c
1116
vtw_del(vp->ctl, vp->vtw);
sys/netinet/tcp_vtw.c
1004
fp = fatp_next(ctl->fat, fp);
sys/netinet/tcp_vtw.c
1027
vtw_ctl_t *ctl = it->ctl;
sys/netinet/tcp_vtw.c
1038
it->fp = ctl->fat->port[tag & ctl->fat->mask];
sys/netinet/tcp_vtw.c
1063
vtw = vtw_from_index(ctl, idx);
sys/netinet/tcp_vtw.c
1074
&& vtw->port_key == fatp_key(ctl->fat, fp, i)
sys/netinet/tcp_vtw.c
1109
, idx_decode(ctl, idx)
sys/netinet/tcp_vtw.c
1115
it->fp = fp = fatp_next(ctl->fat, fp);
sys/netinet/tcp_vtw.c
1141
vtw_ctl_t *ctl = it->ctl;
sys/netinet/tcp_vtw.c
1152
it->fp = ctl->fat->port[tag & ctl->fat->mask];
sys/netinet/tcp_vtw.c
1177
vtw = vtw_from_index(ctl, idx);
sys/netinet/tcp_vtw.c
1190
, i, idx_decode(ctl, idx)
sys/netinet/tcp_vtw.c
1194
&& vtw->port_key == fatp_key(ctl->fat, fp, i)
sys/netinet/tcp_vtw.c
1202
, idx_decode(ctl, idx), vtw->key));
sys/netinet/tcp_vtw.c
1237
, lport, idx_decode(ctl, idx)
sys/netinet/tcp_vtw.c
1243
it->fp = fp = fatp_next(ctl->fat, fp);
sys/netinet/tcp_vtw.c
1280
vtw_init(fatp_ctl_t *fat, vtw_ctl_t *ctl, const uint32_t n, vtw_t *ctl_base_v)
sys/netinet/tcp_vtw.c
1285
ctl->base.v = ctl_base_v;
sys/netinet/tcp_vtw.c
1287
if (ctl->is_v4) {
sys/netinet/tcp_vtw.c
1288
ctl->lim.v4 = ctl->base.v4 + n - 1;
sys/netinet/tcp_vtw.c
1289
ctl->alloc.v4 = ctl->base.v4;
sys/netinet/tcp_vtw.c
1291
ctl->lim.v6 = ctl->base.v6 + n - 1;
sys/netinet/tcp_vtw.c
1292
ctl->alloc.v6 = ctl->base.v6;
sys/netinet/tcp_vtw.c
1295
ctl->nfree = n;
sys/netinet/tcp_vtw.c
1296
ctl->ctl = ctl;
sys/netinet/tcp_vtw.c
1298
ctl->idx_bits = 32;
sys/netinet/tcp_vtw.c
1299
for (ctl->idx_mask = ~0; (ctl->idx_mask & (n-1)) == n-1; ) {
sys/netinet/tcp_vtw.c
1300
ctl->idx_mask >>= 1;
sys/netinet/tcp_vtw.c
1301
ctl->idx_bits -= 1;
sys/netinet/tcp_vtw.c
1304
ctl->idx_mask <<= 1;
sys/netinet/tcp_vtw.c
1305
ctl->idx_mask |= 1;
sys/netinet/tcp_vtw.c
1306
ctl->idx_bits += 1;
sys/netinet/tcp_vtw.c
1308
ctl->fat = fat;
sys/netinet/tcp_vtw.c
1309
fat->vtw = ctl;
sys/netinet/tcp_vtw.c
1317
base = ctl->base.v;
sys/netinet/tcp_vtw.c
1322
ctl[i] = ctl[0];
sys/netinet/tcp_vtw.c
1323
ctl[i].clidx = i;
sys/netinet/tcp_vtw.c
1325
ctl[i].base.v = base;
sys/netinet/tcp_vtw.c
1326
ctl[i].alloc = ctl[i].base;
sys/netinet/tcp_vtw.c
1331
base = vtw_next(ctl, base);
sys/netinet/tcp_vtw.c
1334
ctl[i].lim.v = base;
sys/netinet/tcp_vtw.c
1335
base = vtw_next(ctl, base);
sys/netinet/tcp_vtw.c
1336
ctl[i].nfree = class_n;
sys/netinet/tcp_vtw.c
1376
vtw_alloc(vtw_ctl_t *ctl)
sys/netinet/tcp_vtw.c
1380
int avail = ctl ? (ctl->nalloc + ctl->nfree) : 0;
sys/netinet/tcp_vtw.c
1387
if (!ctl || !ctl->base.v4 || avail <= 0)
sys/netinet/tcp_vtw.c
1392
while (!ctl->nfree) {
sys/netinet/tcp_vtw.c
1393
vtw_age(ctl, 0);
sys/netinet/tcp_vtw.c
1408
, (ctl, "vtw:!none free in class %x %x/%x"
sys/netinet/tcp_vtw.c
1409
, ctl->clidx
sys/netinet/tcp_vtw.c
1410
, ctl->nalloc, ctl->nfree));
sys/netinet/tcp_vtw.c
1416
vtw = ctl->alloc.v;
sys/netinet/tcp_vtw.c
1418
if (vtw->msl_class != ctl->clidx) {
sys/netinet/tcp_vtw.c
1422
KASSERT(!vtw->msl_class || !ctl->clidx);
sys/netinet/tcp_vtw.c
1432
, (ctl, "vtw:!%p class %x!=%x %x:%x%s"
sys/netinet/tcp_vtw.c
1433
, vtw, vtw->msl_class, ctl->clidx
sys/netinet/tcp_vtw.c
1442
, (ctl, "vtw:!%p usurped from %x to %x"
sys/netinet/tcp_vtw.c
1443
, vtw, vtw->msl_class, ctl->clidx));
sys/netinet/tcp_vtw.c
1445
vtw->msl_class = ctl->clidx;
sys/netinet/tcp_vtw.c
1455
ctl->alloc.v = vtw_next(ctl, vtw);
sys/netinet/tcp_vtw.c
1457
--ctl->nfree;
sys/netinet/tcp_vtw.c
1458
++ctl->nalloc;
sys/netinet/tcp_vtw.c
1460
msl = (2 * class_to_msl(ctl->clidx) * 1000) / PR_SLOWHZ; // msec
sys/netinet/tcp_vtw.c
1476
if (!ctl->oldest.v)
sys/netinet/tcp_vtw.c
1477
ctl->oldest.v = vtw;
sys/netinet/tcp_vtw.c
1485
vtw_age(vtw_ctl_t *ctl, struct timeval *_when)
sys/netinet/tcp_vtw.c
1491
if (!ctl->oldest.v) {
sys/netinet/tcp_vtw.c
1492
KASSERT(!ctl->nalloc);
sys/netinet/tcp_vtw.c
1496
for (vtw = ctl->oldest.v; vtw && ctl->nalloc; ) {
sys/netinet/tcp_vtw.c
1497
if (++maxtries > ctl->nalloc)
sys/netinet/tcp_vtw.c
1500
if (vtw->msl_class != ctl->clidx) {
sys/netinet/tcp_vtw.c
1503
, vtw->msl_class, ctl->clidx));
sys/netinet/tcp_vtw.c
1508
ctl->oldest.v = vtw = vtw_next(ctl, vtw);
sys/netinet/tcp_vtw.c
1523
, ctl->clidx
sys/netinet/tcp_vtw.c
1526
, ctl->nalloc
sys/netinet/tcp_vtw.c
1527
, ctl->nfree));
sys/netinet/tcp_vtw.c
1532
vtw_del(ctl, vtw);
sys/netinet/tcp_vtw.c
1533
vtw = ctl->oldest.v;
sys/netinet/tcp_vtw.c
1536
return ctl->nalloc; // # remaining allocated
sys/netinet/tcp_vtw.c
154
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1591
it->ctl = &vtw_tcpv4[0];
sys/netinet/tcp_vtw.c
1602
vtw_export_v4(vtw_ctl_t *ctl, vtw_t *vtw, vestigial_inpcb_t *res)
sys/netinet/tcp_vtw.c
1608
if (ctl && vtw) {
sys/netinet/tcp_vtw.c
1609
if (!ctl->clidx && vtw->msl_class)
sys/netinet/tcp_vtw.c
1610
ctl += vtw->msl_class;
sys/netinet/tcp_vtw.c
1612
KASSERT(ctl->clidx == vtw->msl_class);
sys/netinet/tcp_vtw.c
1622
res->ctl = ctl;
sys/netinet/tcp_vtw.c
1642
if (it->ctl)
sys/netinet/tcp_vtw.c
1646
it->ctl = 0;
sys/netinet/tcp_vtw.c
1648
return vtw_export_v4(it->ctl, vtw, res);
sys/netinet/tcp_vtw.c
1657
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1665
vtw = vtw_lookup_hash_v4((ctl = &vtw_tcpv4[0])
sys/netinet/tcp_vtw.c
1669
return vtw_export_v4(ctl, vtw, res);
sys/netinet/tcp_vtw.c
1690
it->ctl = &vtw_tcpv6[0];
sys/netinet/tcp_vtw.c
1701
vtw_export_v6(vtw_ctl_t *ctl, vtw_t *vtw, vestigial_inpcb_t *res)
sys/netinet/tcp_vtw.c
1707
if (ctl && vtw) {
sys/netinet/tcp_vtw.c
1708
if (!ctl->clidx && vtw->msl_class)
sys/netinet/tcp_vtw.c
1709
ctl += vtw->msl_class;
sys/netinet/tcp_vtw.c
1711
KASSERT(ctl->clidx == vtw->msl_class);
sys/netinet/tcp_vtw.c
1721
res->ctl = ctl;
sys/netinet/tcp_vtw.c
1742
if (it->ctl)
sys/netinet/tcp_vtw.c
1746
it->ctl = 0;
sys/netinet/tcp_vtw.c
1748
return vtw_export_v6(it->ctl, vtw, res);
sys/netinet/tcp_vtw.c
1756
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1764
vtw = vtw_lookup_hash_v6((ctl = &vtw_tcpv6[0])
sys/netinet/tcp_vtw.c
1768
return vtw_export_v6(ctl, vtw, res);
sys/netinet/tcp_vtw.c
1784
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1789
ctl = &vtw_tcpv4[0];
sys/netinet/tcp_vtw.c
1793
ctl = &vtw_tcpv6[0];
sys/netinet/tcp_vtw.c
1801
*ctlp = ctl;
sys/netinet/tcp_vtw.c
1811
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1820
if (!vtw_select(af, &fat, &ctl))
sys/netinet/tcp_vtw.c
1824
KASSERT(fat->base != NULL && ctl->base.v != NULL);
sys/netinet/tcp_vtw.c
1835
sz = (ctl->is_v4 ? sizeof(vtw_v4_t) : sizeof(vtw_v6_t));
sys/netinet/tcp_vtw.c
1841
vtw_init(fat, ctl, tcp_vtw_entries, ctl_base_v);
sys/netinet/tcp_vtw.c
1852
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1855
if (!vtw_select(af, &fat, &ctl))
sys/netinet/tcp_vtw.c
1858
if (!fat->base || !ctl->base.v)
sys/netinet/tcp_vtw.c
1871
return ctl + msl_class;
sys/netinet/tcp_vtw.c
1882
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
1887
ctl = vtw_control(af, tp->t_msl);
sys/netinet/tcp_vtw.c
1888
if (!ctl)
sys/netinet/tcp_vtw.c
1895
vtw = vtw_alloc(ctl);
sys/netinet/tcp_vtw.c
1918
vtw_inshash_v4(ctl, vtw);
sys/netinet/tcp_vtw.c
1927
(ctl
sys/netinet/tcp_vtw.c
1933
(ctl
sys/netinet/tcp_vtw.c
1991
vtw_inshash_v6(ctl, vtw);
sys/netinet/tcp_vtw.c
1997
KASSERT(vtw_lookup_hash_v6(ctl
sys/netinet/tcp_vtw.c
2003
(ctl
sys/netinet/tcp_vtw.c
2062
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
2073
ctl = vtw_control(AF_INET, class_to_msl(cp->msl_class));
sys/netinet/tcp_vtw.c
2074
vtw = vtw_alloc(ctl);
sys/netinet/tcp_vtw.c
2081
vtw_del(vp->ctl, vp->vtw);
sys/netinet/tcp_vtw.c
2096
vtw_inshash_v4(ctl, vtw);
sys/netinet/tcp_vtw.c
2110
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
2123
ctl = vtw_control(AF_INET6, class_to_msl(cp->msl_class));
sys/netinet/tcp_vtw.c
2124
vtw = vtw_alloc(ctl);
sys/netinet/tcp_vtw.c
2131
vtw_del(vp->ctl, vp->vtw);
sys/netinet/tcp_vtw.c
2146
vtw_inshash_v6(ctl, vtw);
sys/netinet/tcp_vtw.c
2229
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
2232
ctl = vtw_control(af, msl ? msl : class_to_msl(msl_class));
sys/netinet/tcp_vtw.c
2233
if (!ctl)
sys/netinet/tcp_vtw.c
2236
vtw = vtw_alloc(ctl);
sys/netinet/tcp_vtw.c
2256
vtw_inshash_v4(ctl, vtw);
sys/netinet/tcp_vtw.c
2274
vtw_inshash_v6(ctl, vtw);
sys/netinet/tcp_vtw.c
2375
vtw_ctl_t *ctl;
sys/netinet/tcp_vtw.c
2381
ctl = &vtw_tcpv4[i];
sys/netinet/tcp_vtw.c
2383
if (!ctl->base.v || ctl->nalloc)
sys/netinet/tcp_vtw.c
2386
for (n = 0, vtw = ctl->base.v; ; ) {
sys/netinet/tcp_vtw.c
2388
vtw = vtw_next(ctl, vtw);
sys/netinet/tcp_vtw.c
2389
if (vtw == ctl->base.v)
sys/netinet/tcp_vtw.c
2393
, (ctl, "sanity: class %x n %x nfree %x"
sys/netinet/tcp_vtw.c
2394
, i, n, ctl->nfree));
sys/netinet/tcp_vtw.c
2396
KASSERT(n == ctl->nfree);
sys/netinet/tcp_vtw.c
2400
ctl = &vtw_tcpv6[i];
sys/netinet/tcp_vtw.c
2402
if (!ctl->base.v || ctl->nalloc)
sys/netinet/tcp_vtw.c
2405
for (n = 0, vtw = ctl->base.v; ; ) {
sys/netinet/tcp_vtw.c
2407
vtw = vtw_next(ctl, vtw);
sys/netinet/tcp_vtw.c
2408
if (vtw == ctl->base.v)
sys/netinet/tcp_vtw.c
2412
, (ctl, "sanity: class %x n %x nfree %x"
sys/netinet/tcp_vtw.c
2413
, i, n, ctl->nfree));
sys/netinet/tcp_vtw.c
2414
KASSERT(n == ctl->nfree);
sys/netinet/tcp_vtw.c
325
idx_encode(vtw_ctl_t *ctl, uint32_t idx)
sys/netinet/tcp_vtw.c
327
return (idx << ctl->idx_bits) | idx;
sys/netinet/tcp_vtw.c
331
idx_decode(vtw_ctl_t *ctl, uint32_t bits)
sys/netinet/tcp_vtw.c
333
uint32_t idx = bits & ctl->idx_mask;
sys/netinet/tcp_vtw.c
335
if (idx_encode(ctl, idx) == bits)
sys/netinet/tcp_vtw.c
418
vtw_index_v4(vtw_ctl_t *ctl, vtw_v4_t *v4)
sys/netinet/tcp_vtw.c
420
if (ctl->base.v4 <= v4 && v4 <= ctl->lim.v4)
sys/netinet/tcp_vtw.c
421
return v4 - ctl->base.v4;
sys/netinet/tcp_vtw.c
429
vtw_index_v6(vtw_ctl_t *ctl, vtw_v6_t *v6)
sys/netinet/tcp_vtw.c
431
if (ctl->base.v6 <= v6 && v6 <= ctl->lim.v6)
sys/netinet/tcp_vtw.c
432
return v6 - ctl->base.v6;
sys/netinet/tcp_vtw.c
440
vtw_index(vtw_ctl_t *ctl, vtw_t *vtw)
sys/netinet/tcp_vtw.c
442
if (ctl->clidx)
sys/netinet/tcp_vtw.c
443
ctl = ctl->ctl;
sys/netinet/tcp_vtw.c
445
if (ctl->is_v4)
sys/netinet/tcp_vtw.c
446
return vtw_index_v4(ctl, (vtw_v4_t *)vtw);
sys/netinet/tcp_vtw.c
448
if (ctl->is_v6)
sys/netinet/tcp_vtw.c
449
return vtw_index_v6(ctl, (vtw_v6_t *)vtw);
sys/netinet/tcp_vtw.c
457
vtw_from_index(vtw_ctl_t *ctl, uint32_t idx)
sys/netinet/tcp_vtw.c
459
if (ctl->clidx)
sys/netinet/tcp_vtw.c
460
ctl = ctl->ctl;
sys/netinet/tcp_vtw.c
465
idx = idx_decode(ctl, idx);
sys/netinet/tcp_vtw.c
469
} else if (ctl->is_v4) {
sys/netinet/tcp_vtw.c
470
vtw_v4_t *vtw = ctl->base.v4 + idx;
sys/netinet/tcp_vtw.c
472
return (ctl->base.v4 <= vtw && vtw <= ctl->lim.v4)
sys/netinet/tcp_vtw.c
474
} else if (ctl->is_v6) {
sys/netinet/tcp_vtw.c
475
vtw_v6_t *vtw = ctl->base.v6 + idx;
sys/netinet/tcp_vtw.c
477
return (ctl->base.v6 <= vtw && vtw <= ctl->lim.v6)
sys/netinet/tcp_vtw.c
493
vtw_next(vtw_ctl_t *ctl, vtw_t *vtw)
sys/netinet/tcp_vtw.c
495
if (ctl->is_v4) {
sys/netinet/tcp_vtw.c
505
if (vtw > ctl->lim.v)
sys/netinet/tcp_vtw.c
506
vtw = ctl->base.v;
sys/netinet/tcp_vtw.c
514
vtw_unhash(vtw_ctl_t *ctl, vtw_t *vtw)
sys/netinet/tcp_vtw.c
516
fatp_ctl_t *fat = ctl->fat;
sys/netinet/tcp_vtw.c
541
idx = vtw_index(ctl, vtw);
sys/netinet/tcp_vtw.c
548
KASSERT(fp->tag[slot] == (tag ^ idx_encode(ctl, idx)
sys/netinet/tcp_vtw.c
552
&& fp->tag[slot] == (tag ^ idx_encode(ctl, idx)
sys/netinet/tcp_vtw.c
620
idx = vtw_index(ctl, vtw);
sys/netinet/tcp_vtw.c
628
KASSERT(fp->tag[slot] == (tag ^ idx_encode(ctl, idx)
sys/netinet/tcp_vtw.c
632
&& fp->tag[slot] == (tag ^ idx_encode(ctl, idx)
sys/netinet/tcp_vtw.c
676
vtw_del(vtw_ctl_t *ctl, vtw_t *vtw)
sys/netinet/tcp_vtw.c
682
vtw_unhash(ctl, vtw);
sys/netinet/tcp_vtw.c
687
if (vtw != ctl->oldest.v)
sys/netinet/tcp_vtw.c
690
--ctl->nalloc;
sys/netinet/tcp_vtw.c
691
++ctl->nfree;
sys/netinet/tcp_vtw.c
696
if (!ctl->nalloc)
sys/netinet/tcp_vtw.c
697
ctl->oldest.v = 0;
sys/netinet/tcp_vtw.c
699
ctl->oldest.v = vtw_next(ctl, vtw);
sys/netinet/tcp_vtw.c
705
vtw_inshash_v4(vtw_ctl_t *ctl, vtw_t *vtw)
sys/netinet/tcp_vtw.c
707
uint32_t idx = vtw_index(ctl, vtw);
sys/netinet/tcp_vtw.c
713
KASSERT(ctl->clidx == vtw->msl_class);
sys/netinet/tcp_vtw.c
720
vtw->key = fatp_vtw_inshash(ctl->fat, idx, tag, 0, vtw);
sys/netinet/tcp_vtw.c
722
db_trace(KTR_VTW, (ctl
sys/netinet/tcp_vtw.c
731
vtw->port_key = fatp_vtw_inshash(ctl->fat, idx, tag, 1, vtw);
sys/netinet/tcp_vtw.c
733
db_trace(KTR_VTW, (ctl, "vtw: ins %P - %4.4x tag %8.8x key %8.8x"
sys/netinet/tcp_vtw.c
744
vtw_inshash_v6(vtw_ctl_t *ctl, vtw_t *vtw)
sys/netinet/tcp_vtw.c
746
uint32_t idx = vtw_index(ctl, vtw);
sys/netinet/tcp_vtw.c
752
KASSERT(ctl->clidx == vtw->msl_class);
sys/netinet/tcp_vtw.c
759
vtw->key = fatp_vtw_inshash(ctl->fat, idx, tag, 0, vtw);
sys/netinet/tcp_vtw.c
762
vtw->port_key = fatp_vtw_inshash(ctl->fat, idx, tag, 1, vtw);
sys/netinet/tcp_vtw.c
764
db_trace(KTR_VTW, (ctl, "vtw: ins %P - %4.4x tag %8.8x key %8.8x"
sys/netinet/tcp_vtw.c
773
vtw_lookup_hash_v4(vtw_ctl_t *ctl, uint32_t faddr, uint16_t fport
sys/netinet/tcp_vtw.c
784
if (!ctl || !ctl->fat)
sys/netinet/tcp_vtw.c
791
fp = ctl->fat->port[tag & ctl->fat->mask];
sys/netinet/tcp_vtw.c
794
fp = ctl->fat->hash[tag & ctl->fat->mask];
sys/netinet/tcp_vtw.c
814
vtw = vtw_from_index(ctl, idx);
sys/netinet/tcp_vtw.c
835
== fatp_key(ctl->fat, fp, i))
sys/netinet/tcp_vtw.c
847
, idx_decode(ctl, idx), vtw->key));
sys/netinet/tcp_vtw.c
862
, fatp_key(ctl->fat, fp, i)
sys/netinet/tcp_vtw.c
874
if (vtw->key == fatp_key(ctl->fat, fp, i)) {
sys/netinet/tcp_vtw.c
891
, fatp_key(ctl->fat, fp, i)
sys/netinet/tcp_vtw.c
892
, idx_decode(ctl, idx)
sys/netinet/tcp_vtw.c
901
, idx_decode(ctl, idx)
sys/netinet/tcp_vtw.c
907
fp = fatp_next(ctl->fat, fp);
sys/netinet/tcp_vtw.c
926
vtw_lookup_hash_v6(vtw_ctl_t *ctl, const struct in6_addr *faddr, uint16_t fport
sys/netinet/tcp_vtw.c
939
if (!ctl || !ctl->fat)
sys/netinet/tcp_vtw.c
944
fp = ctl->fat->port[tag & ctl->fat->mask];
sys/netinet/tcp_vtw.c
947
fp = ctl->fat->hash[tag & ctl->fat->mask];
sys/netinet/tcp_vtw.c
967
vtw = vtw_from_index(ctl, idx);
sys/netinet/tcp_vtw.c
974
, idx_decode(ctl, idx)));
sys/netinet/tcp_vtw.c
986
== fatp_key(ctl->fat, fp, i))
sys/netinet/tcp_vtw.h
250
vtw_ctl_t *ctl; /* <! controller's controller */
sys/netinet/tcp_vtw.h
390
struct vtw_ctl *ctl;
sys/rump/librump/rumpkern/lwproc.c
186
struct rump_spctl *ctl = (struct rump_spctl *)p->p_vmspace;
sys/rump/librump/rumpkern/lwproc.c
188
kmem_free(ctl, sizeof(*ctl));
tests/dev/audio/audiotest.c
6839
int ctl;
tests/dev/audio/audiotest.c
6856
ctl = OPEN(devaudioctl, cmode);
tests/dev/audio/audiotest.c
6857
XP_SYS_OK(ctl);
tests/dev/audio/audiotest.c
6859
r = CLOSE(ctl);
tests/dev/audio/audiotest.c
6882
int ctl;
tests/dev/audio/audiotest.c
6896
ctl = OPEN(devaudioctl, cmode);
tests/dev/audio/audiotest.c
6897
REQUIRED_SYS_OK(ctl);
tests/dev/audio/audiotest.c
6905
r = CLOSE(ctl);
usr.bin/cdplay/cdplay.c
126
#define IOCTL_SIMPLE(fd, ctl) \
usr.bin/cdplay/cdplay.c
128
if (ioctl((fd), (ctl)) >= 0) { \
usr.bin/cdplay/cdplay.c
132
warn("ioctl(" #ctl ")");\
usr.bin/netstat/vtw.c
205
process_vtw(const vtw_ctl_t * ctl, void (*print)(const vtw_t *))
usr.bin/netstat/vtw.c
209
for (vp = ctl->base.v; vp && vp <= ctl->lim.v;) {
usr.bin/netstat/vtw.c
213
if (ctl->is_v4) {
usr.bin/netstat/vtw.c
217
} else if (ctl->is_v6) {
usr.sbin/bthcid/client.c
101
ctl = socket(PF_LOCAL, SOCK_STREAM, 0);
usr.sbin/bthcid/client.c
102
if (ctl < 0)
usr.sbin/bthcid/client.c
109
if (bind(ctl, (struct sockaddr *)&un, sizeof(un)) < 0) {
usr.sbin/bthcid/client.c
110
close(ctl);
usr.sbin/bthcid/client.c
115
close(ctl);
usr.sbin/bthcid/client.c
120
if (listen(ctl, 10) < 0) {
usr.sbin/bthcid/client.c
121
close(ctl);
usr.sbin/bthcid/client.c
126
event_set(&control_ev, ctl, EV_READ | EV_PERSIST, process_control, NULL);
usr.sbin/bthcid/client.c
128
close(ctl);
usr.sbin/bthcid/client.c
90
int ctl;