sys/arch/arm/amlogic/meson_clk.c

180

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/amlogic/meson_clk_div.c

97

return clk_set_rate(clkp_parent, new_rate);

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

76

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/amlogic/meson_clk_pll.c

116

return clk_set_rate(clkp_parent, new_rate);

sys/arch/arm/nvidia/tegra124_cpu.c

277

error = clk_set_rate(tegra124_clk_pllx, r->rate * 1000000);

sys/arch/arm/nvidia/tegra210_car.c

847

error = clk_set_rate(clk, tegra210_init_parents[n].rate);

sys/arch/arm/nvidia/tegra_ahcisata.c

373

error = clk_set_rate(sc->sc_clk_sata_oob, 204000000);

sys/arch/arm/nvidia/tegra_ahcisata.c

381

error = clk_set_rate(sc->sc_clk_sata, 102000000);

sys/arch/arm/nvidia/tegra_drm_mode.c

806

error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000);

sys/arch/arm/nvidia/tegra_drm_mode.c

881

error = clk_set_rate(sc->sc_clk_hdmi, rate);

sys/arch/arm/nvidia/tegra_hdaudio.c

200

error = clk_set_rate(sc->sc_clk_hda, 48000000);

sys/arch/arm/nvidia/tegra_hdaudio.c

222

error = clk_set_rate(sc->sc_clk_hda2codec_2x, 48000000);

sys/arch/arm/nvidia/tegra_i2c.c

161

error = clk_set_rate(sc->sc_clk, 20400000);

sys/arch/arm/nvidia/tegra_nouveau.c

175

error = clk_set_rate(sc->sc_clk_pwr, 204000000);

sys/arch/arm/nvidia/tegra_sdhc.c

202

error = clk_set_rate(sc->sc_clk, 100000000);

sys/arch/arm/nvidia/tegra_sdhc.c

204

error = clk_set_rate(sc->sc_clk, 204000000);

sys/arch/arm/nvidia/tegra_soctherm.c

237

error = clk_set_rate(sc->sc_clk_soctherm, 51000000);

sys/arch/arm/nvidia/tegra_soctherm.c

244

error = clk_set_rate(sc->sc_clk_tsensor, 400000);

sys/arch/arm/nvidia/tegra_xusb.c

321

error = clk_set_rate(clk, 102000000);

sys/arch/arm/nvidia/tegra_xusb.c

332

error = clk_set_rate(clk, 204000000);

sys/arch/arm/nvidia/tegra_xusb.c

358

error = clk_set_rate(psc->sc_clk_ss_src, 2000000);

sys/arch/arm/nvidia/tegra_xusb.c

367

error = clk_set_rate(psc->sc_clk_ss_src, 120000000);

sys/arch/arm/nvidia/tegra_xusb.c

558

error = clk_set_rate(psc->sc_clk_ss_src, data * 1000);

sys/arch/arm/nxp/imx_ccm.c

117

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/nxp/imx_ccm_composite.c

107

return clk_set_rate(clk_parent, rate);

sys/arch/arm/nxp/imx_ccm_div.c

83

return clk_set_rate(clkp, rate);

sys/arch/arm/nxp/imx_ccm_extclk.c

80

return clk_set_rate(extclk, rate);

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

76

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/rockchip/rk3399_cru.c

1132

clk_set_rate(&clk->base, clk_get_rate(&clk->base));

sys/arch/arm/rockchip/rk_cru.c

169

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/rockchip/rk_cru_arm.c

153

error = clk_set_rate(&main_parent->base, rate);

sys/arch/arm/rockchip/rk_cru_arm.c

98

error = clk_set_rate(&main_parent->base, parent_rate);

sys/arch/arm/rockchip/rk_cru_composite.c

153

return clk_set_rate(clk_parent, rate);

sys/arch/arm/rockchip/rk_dwhdmi.c

206

error = clk_set_rate(sc->sc_clk_vpll, adjusted_mode->clock * 1000);

sys/arch/arm/rockchip/rk_i2s.c

424

error = clk_set_rate(sc->sc_clk, rate);

sys/arch/arm/rockchip/rk_vop.c

477

error = clk_set_rate(sc->sc_dclk, adjusted_mode->clock * 1000);

sys/arch/arm/samsung/exynos_dwcmmc.c

204

error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

753

error = clk_set_rate(clkp, rate);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

755

error = clk_set_rate(clkp, rate / 2);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

835

error = clk_set_rate(pllclk, 3000000 * n);

sys/arch/arm/sunxi/sun4i_spi.c

114

|| clk_set_rate(modclk, clk_get_rate(clk)) != 0

sys/arch/arm/sunxi/sun50i_a64_ccu.c

641

clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000);

sys/arch/arm/sunxi/sun50i_a64_ccu.c

644

clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000);

sys/arch/arm/sunxi/sun50i_a64_ccu.c

645

clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000);

sys/arch/arm/sunxi/sun6i_spi.c

125

|| clk_set_rate(modclk, 200000000) != 0

sys/arch/arm/sunxi/sun8i_crypto.c

442

if (clk_set_rate(clk, mod_rate) != 0) {

sys/arch/arm/sunxi/sunxi_ccu.c

179

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/sunxi/sunxi_ccu_display.c

135

error = clk_set_rate(pllclkp, best_parent_rate);

sys/arch/arm/sunxi/sunxi_ccu_display.c

63

error = clk_set_rate(clkp, new_rate / 2);

sys/arch/arm/sunxi/sunxi_ccu_display.c

68

error = clk_set_rate(clkp, new_rate);

sys/arch/arm/sunxi/sunxi_ccu_div.c

152

return clk_set_rate(clkp_parent, new_rate);

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

76

return clk_set_rate(clkp_parent, rate);

sys/arch/arm/sunxi/sunxi_codec.c

537

error = clk_set_rate(clk, 24576000);

sys/arch/arm/sunxi/sunxi_debe.c

239

error = clk_set_rate(sc->sc_clk_mod, 300000000);

sys/arch/arm/sunxi/sunxi_dwhdmi.c

194

error = clk_set_rate(sc->sc_clk, adjusted_mode->clock * 1000);

sys/arch/arm/sunxi/sunxi_gmac.c

177

if (clk_set_rate(clk_gmac_tx, GMAC_TX_RATE_MII) != 0) {

sys/arch/arm/sunxi/sunxi_gmac.c

182

if (clk_set_rate(clk_gmac_tx, GMAC_TX_RATE_RGMII) != 0) {

sys/arch/arm/sunxi/sunxi_hdmi.c

596

error = clk_set_rate(clk, 270000000);

sys/arch/arm/sunxi/sunxi_hdmi.c

600

error = clk_set_rate(clk, 270000000);

sys/arch/arm/sunxi/sunxi_i2s.c

640

error = clk_set_rate(sc->sc_clk, SUNXI_I2S_CLK_RATE);

sys/arch/arm/sunxi/sunxi_lcdc.c

246

error = clk_set_rate(sc->sc_clk_ch[0], mode->crtc_clock * 1000);

sys/arch/arm/sunxi/sunxi_lcdc.c

294

error = clk_set_rate(sc->sc_clk_ch[1], mode->crtc_clock * 1000);

sys/arch/arm/sunxi/sunxi_mixer.c

650

clk_set_rate(clk_mod, SUNXI_MIXER_FREQ) != 0 ||

sys/arch/arm/sunxi/sunxi_mmc.c

534

error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << dbl);

sys/arch/arm/sunxi/sunxi_mmc.c

544

error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase);

sys/arch/arm/sunxi/sunxi_mmc.c

549

error = clk_set_rate(sc->sc_clk_output, delays->output_phase);

sys/arch/arm/sunxi/sunxi_tcon.c

500

error = clk_set_rate(sc->sc_clk_ch0, best_clk_freq);

sys/arch/arm/sunxi/sunxi_tcon.c

806

error = clk_set_rate(sc->sc_clk_ch1, mode->dot_clock * 1000);

sys/arch/arm/sunxi/sunxi_thermal.c

540

error = clk_set_rate(clk, sc->conf->clk_rate);

sys/arch/arm/ti/ti_prcm.c

96

return clk_set_rate(clkp_parent, rate);

sys/arch/riscv/starfive/jh7100_gmac.c

83

int error = clk_set_rate(jheth_sc->sc_clk_tx, rate);

sys/arch/riscv/starfive/jh71x0_clkc.c

103

return clk_set_rate(clk_parent, rate);

sys/arch/riscv/starfive/jh71x0_clkc.c

550

return clk_set_rate(clk_parent, rate);

sys/dev/clk/clk.c

235

return clk_set_rate(clk_get_parent(clk), rate);

sys/dev/clk/clk.h

38

int clk_set_rate(struct clk *, u_int);

sys/dev/fdt/cpufreq_dt.c

130

error = clk_set_rate(sc->sc_clk, new_rate);

sys/dev/fdt/dwcmmc_fdt.c

243

error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div);

sys/dev/fdt/fdt_clock.c

261

error = clk_set_rate(clk, rate);

sys/dev/i2c/es8316ac.c

495

error = clk_set_rate(sc->sc_clk, rate);