Symbol: WR4
sys/arch/arm/amlogic/meson_i2c.c
166
WR4(sc, reg, data);
sys/arch/arm/nvidia/tegra210_xusbpad.c
878
WR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_3_REG(port->index), 0xc0077f1f);
sys/arch/arm/nvidia/tegra210_xusbpad.c
882
WR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_6_REG(port->index), 0xfcf01368);
sys/arch/arm/rockchip/rk3288_iomux.c
190
WR4(reg, reg->pull_reg, val);
sys/arch/arm/rockchip/rk3288_iomux.c
224
WR4(reg, reg->drv_reg, val);
sys/arch/arm/rockchip/rk3288_iomux.c
243
WR4(reg, reg->mux_reg, val);
sys/arch/arm/rockchip/rk3328_iomux.c
166
WR4(sc, GRF_GPIO_P_REG(bank, idx),
sys/arch/arm/rockchip/rk3328_iomux.c
174
WR4(sc, GRF_GPIO_E_REG(bank, idx),
sys/arch/arm/rockchip/rk3328_iomux.c
187
WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));
sys/arch/arm/rockchip/rk3399_iomux.c
250
WR4(syscon, reg, bias_val | bias_mask);
sys/arch/arm/rockchip/rk3399_iomux.c
342
WR4(syscon, reg, write_val | write_mask);
sys/arch/arm/rockchip/rk3399_iomux.c
376
WR4(syscon, reg, (mask << 16) | __SHIFTIN(mux, mask));
sys/arch/arm/rockchip/rk3399_iomux.c
475
WR4(syscon, GRF_GPIO4B_IOMUX, val);
sys/arch/arm/rockchip/rk3399_iomux.c
478
WR4(syscon, GRF_SOC_CON7, val);
sys/arch/arm/rockchip/rk_emmcphy.c
146
WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
sys/arch/arm/rockchip/rk_emmcphy.c
151
WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val);
sys/arch/arm/rockchip/rk_emmcphy.c
157
WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
sys/arch/arm/rockchip/rk_emmcphy.c
184
WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
sys/arch/arm/rockchip/rk_emmcphy.c
198
WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val);
sys/arch/arm/rockchip/rk_emmcphy.c
203
WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
sys/arch/arm/rockchip/rk_gpio.c
234
WR4(sc, GPIO_SWPORTA_DR_REG, data);
sys/arch/arm/rockchip/rk_gpio.c
252
WR4(sc, GPIO_SWPORTA_DDR_REG, ddr);
sys/arch/arm/rockchip/rk_gpio.c
286
WR4(sc, GPIOV2_SWPORT_DR_REG(pin), write_mask | data);
sys/arch/arm/rockchip/rk_gpio.c
299
WR4(sc, GPIOV2_SWPORT_DDR_REG(pin), GPIOV2_WRITE_MASK(pin) | ddr);
sys/arch/arm/rockchip/rk_gpio.c
314
WR4(sc, GPIO_PORTA_EOI_REG, status);
sys/arch/arm/rockchip/rk_gpio.c
356
WR4(sc, GPIO_INTTYPE_LEVEL_REG, val);
sys/arch/arm/rockchip/rk_gpio.c
363
WR4(sc, GPIO_INT_POLARITY_REG, val);
sys/arch/arm/rockchip/rk_gpio.c
367
WR4(sc, GPIO_INTEN_REG, val);
sys/arch/arm/rockchip/rk_gpio.c
400
WR4(sc, GPIO_INTEN_REG, val);
sys/arch/arm/rockchip/rk_gpio.c
401
WR4(sc, GPIO_INT_STATUS_REG, __BIT(eint->eint_num));
sys/arch/arm/rockchip/rk_gpio.c
562
WR4(sc, GPIO_INTEN_REG, val);
sys/arch/arm/rockchip/rk_gpio.c
574
WR4(sc, GPIO_INTEN_REG, val);
sys/arch/arm/rockchip/rk_gpio.c
670
WR4(sc, GPIO_INTEN_REG, 0);
sys/arch/arm/rockchip/rk_i2c.c
154
WR4(sc, RKI2C_CLKDIV,
sys/arch/arm/rockchip/rk_i2c.c
161
WR4(sc, RKI2C_CON, 0);
sys/arch/arm/rockchip/rk_i2c.c
162
WR4(sc, RKI2C_IEN, 0);
sys/arch/arm/rockchip/rk_i2c.c
163
WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD));
sys/arch/arm/rockchip/rk_i2c.c
180
WR4(sc, RKI2C_IPD, val & ipdmask);
sys/arch/arm/rockchip/rk_i2c.c
199
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
205
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
219
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
225
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
249
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
264
WR4(sc, RKI2C_MTXCNT, __SHIFTIN(len + 1, RKI2C_MTXCNT_MTXCNT));
sys/arch/arm/rockchip/rk_i2c.c
289
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
297
WR4(sc, RKI2C_MRXADDR, mrxaddr);
sys/arch/arm/rockchip/rk_i2c.c
302
WR4(sc, RKI2C_MRXRADDR, mrxraddr);
sys/arch/arm/rockchip/rk_i2c.c
308
WR4(sc, RKI2C_CON, con);
sys/arch/arm/rockchip/rk_i2c.c
311
WR4(sc, RKI2C_MRXCNT, __SHIFTIN(buflen, RKI2C_MRXCNT_MRXCNT));
sys/arch/arm/rockchip/rk_i2c.c
362
WR4(sc, RKI2C_CON, 0);
sys/arch/arm/rockchip/rk_i2c.c
363
WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD));
sys/arch/arm/rockchip/rk_i2s.c
202
WR4(sc, I2S_CKR, ckr);
sys/arch/arm/rockchip/rk_i2s.c
212
WR4(sc, I2S_TXCR, txcr);
sys/arch/arm/rockchip/rk_i2s.c
223
WR4(sc, I2S_RXCR, rxcr);
sys/arch/arm/rockchip/rk_i2s.c
260
WR4(sc, I2S_XFER, val);
sys/arch/arm/rockchip/rk_i2s.c
269
WR4(sc, I2S_INTCR, val);
sys/arch/arm/rockchip/rk_i2s.c
299
WR4(sc, I2S_XFER, val);
sys/arch/arm/rockchip/rk_i2s.c
304
WR4(sc, I2S_INTCR, val);
sys/arch/arm/rockchip/rk_i2s.c
308
WR4(sc, I2S_CLR, val);
sys/arch/arm/rockchip/rk_i2s.c
330
WR4(sc, I2S_XFER, val);
sys/arch/arm/rockchip/rk_i2s.c
335
WR4(sc, I2S_INTCR, val);
sys/arch/arm/rockchip/rk_i2s.c
400
WR4(sc, I2S_TXDR, *pch->ch_cur);
sys/arch/arm/rockchip/rk_i2s.c
479
WR4(sc, I2S_TXCR, txcr);
sys/arch/arm/rockchip/rk_i2s.c
480
WR4(sc, I2S_RXCR, rxcr);
sys/arch/arm/rockchip/rk_i2s.c
504
WR4(sc, I2S_CKR, ckr);
sys/arch/arm/rockchip/rk_vop.c
194
WR4(sc, reg, ((uint32_t)mask << 16) | val);
sys/arch/arm/rockchip/rk_vop.c
248
WR4(sc, VOP_DSP_CTRL1, val);
sys/arch/arm/rockchip/rk_vop.c
258
WR4(sc, VOP_SYS_CTRL, val);
sys/arch/arm/rockchip/rk_vop.c
325
WR4(sc, VOP_WIN0_ACT_INFO, val);
sys/arch/arm/rockchip/rk_vop.c
331
WR4(sc, VOP_WIN0_DSP_INFO, val);
sys/arch/arm/rockchip/rk_vop.c
339
WR4(sc, VOP_WIN0_DSP_ST, val);
sys/arch/arm/rockchip/rk_vop.c
341
WR4(sc, VOP_WIN0_COLOR_KEY, 0);
sys/arch/arm/rockchip/rk_vop.c
354
WR4(sc, VOP_WIN0_CTRL, val);
sys/arch/arm/rockchip/rk_vop.c
374
WR4(sc, VOP_WIN0_VIR, val);
sys/arch/arm/rockchip/rk_vop.c
377
WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr);
sys/arch/arm/rockchip/rk_vop.c
387
WR4(sc, VOP_WIN0_CTRL, 0); /* clear WIN0_EN */
sys/arch/arm/rockchip/rk_vop.c
437
WR4(sc, VOP_SYS_CTRL, val);
sys/arch/arm/rockchip/rk_vop.c
440
WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
sys/arch/arm/rockchip/rk_vop.c
519
WR4(sc, VOP_SYS_CTRL, val);
sys/arch/arm/rockchip/rk_vop.c
524
WR4(sc, VOP_DSP_CTRL0, val);
sys/arch/arm/rockchip/rk_vop.c
528
WR4(sc, VOP_POST_DSP_HACT_INFO, val);
sys/arch/arm/rockchip/rk_vop.c
532
WR4(sc, VOP_DSP_HACT_ST_END, val);
sys/arch/arm/rockchip/rk_vop.c
536
WR4(sc, VOP_DSP_HTOTAL_HS_END, val);
sys/arch/arm/rockchip/rk_vop.c
540
WR4(sc, VOP_POST_DSP_VACT_INFO, val);
sys/arch/arm/rockchip/rk_vop.c
544
WR4(sc, VOP_DSP_VACT_ST_END, val);
sys/arch/arm/rockchip/rk_vop.c
548
WR4(sc, VOP_DSP_VTOTAL_VS_END, val);
sys/arch/arm/rockchip/rk_vop.c
564
WR4(sc, VOP_SYS_CTRL, val);
sys/arch/arm/rockchip/rk_vop.c
583
WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
sys/arch/arm/samsung/exynos_uart.c
277
WR4(sc, SSCOM_UFCON,
sys/arch/arm/samsung/exynos_uart.c
286
WR4(sc, SSCOM_UCON, ucon);
sys/arch/arm/samsung/exynos_uart.c
290
WR4(sc, SSCOM_UCON, ucon | __SHIFTIN(3, UCON_RXTO));
sys/arch/arm/samsung/exynos_uart.c
292
WR4(sc, SSCOM_UINTM, ~0u);
sys/arch/arm/samsung/exynos_uart.c
337
WR4(sc, SSCOM_UTXH, c & 0xff);
sys/arch/arm/samsung/exynos_uart.c
400
WR4(sc, SSCOM_UINTM, ~0u & ~(UINT_RXD|UINT_ERROR));
sys/arch/arm/samsung/exynos_uart.c
405
WR4(sc, SSCOM_UCON, ucon);
sys/arch/arm/samsung/exynos_uart.c
430
WR4(sc, SSCOM_UINTM, ~0u);
sys/arch/arm/samsung/exynos_uart.c
435
WR4(sc, SSCOM_UCON, ucon);
sys/arch/arm/samsung/exynos_uart.c
524
WR4(sc, SSCOM_UTXH, *p);
sys/arch/arm/samsung/exynos_uart.c
571
WR4(sc, SSCOM_ULCON, ulcon);
sys/arch/arm/samsung/exynos_uart.c
576
WR4(sc, SSCOM_UBRDIV, ubrdiv);
sys/arch/arm/samsung/exynos_uart.c
627
WR4(sc, SSCOM_UTRSTAT, ack);
sys/arch/arm/samsung/exynos_uart.c
629
WR4(sc, SSCOM_UINTP, ack);
sys/arch/arm/sunxi/sun4i_a10_codec.c
113
WR4((sc), (reg), RD4((sc), (reg)) | (mask))
sys/arch/arm/sunxi/sun4i_a10_codec.c
115
WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
sys/arch/arm/sunxi/sun4i_a10_codec.c
165
WR4(sc, mix->reg, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
168
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
172
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
177
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
193
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
198
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
203
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
207
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun50i_a64_acodec.c
211
WR4(sc, A64_PR_CFG, val);
sys/arch/arm/sunxi/sun6i_a31_codec.c
156
WR4((sc), (reg), RD4((sc), (reg)) | (mask))
sys/arch/arm/sunxi/sun6i_a31_codec.c
158
WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
sys/arch/arm/sunxi/sun6i_a31_codec.c
226
WR4(sc, mix->reg, val);
sys/arch/arm/sunxi/sun8i_codec.c
263
WR4(sc, AIF1CLK_CTRL, val);
sys/arch/arm/sunxi/sun8i_codec.c
295
WR4(sc, HMIC_CTRL1, val);
sys/arch/arm/sunxi/sun8i_codec.c
349
WR4(sc, HMIC_STS, val);
sys/arch/arm/sunxi/sun8i_codec.c
427
WR4(sc, SYSCLK_CTL, val);
sys/arch/arm/sunxi/sun8i_codec.c
428
WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC);
sys/arch/arm/sunxi/sun8i_codec.c
429
WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC);
sys/arch/arm/sunxi/sun8i_codec.c
432
WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA);
sys/arch/arm/sunxi/sun8i_codec.c
433
WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD);
sys/arch/arm/sunxi/sun8i_codec.c
439
WR4(sc, SYS_SR_CTRL, val);
sys/arch/arm/sunxi/sun8i_codec.c
445
WR4(sc, AIF1CLK_CTRL, val);
sys/arch/arm/sunxi/sun8i_codec.c
451
WR4(sc, AIF1_DACDAT_CTRL, val);
sys/arch/arm/sunxi/sun8i_codec.c
459
WR4(sc, DAC_MXR_SRC, val);
sys/arch/arm/sunxi/sun8i_codec.c
469
WR4(sc, HMIC_CTRL1, val);
sys/arch/arm/sunxi/sun8i_codec.c
474
WR4(sc, HMIC_CTRL2, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
157
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
161
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
166
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
182
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
187
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
192
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
196
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_h3_codec.c
200
WR4(csc, H3_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
144
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
148
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
153
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
169
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
174
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
179
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
183
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sun8i_v3s_codec.c
187
WR4(csc, V3S_PR_CFG, val);
sys/arch/arm/sunxi/sunxi_emac.c
211
WR4(sc, EMAC_MII_CMD,
sys/arch/arm/sunxi/sunxi_emac.c
239
WR4(sc, EMAC_MII_DATA, val);
sys/arch/arm/sunxi/sunxi_emac.c
240
WR4(sc, EMAC_MII_CMD,
sys/arch/arm/sunxi/sunxi_emac.c
280
WR4(sc, EMAC_BASIC_CTL_0, val);
sys/arch/arm/sunxi/sunxi_emac.c
286
WR4(sc, EMAC_RX_CTL_0, val);
sys/arch/arm/sunxi/sunxi_emac.c
294
WR4(sc, EMAC_TX_FLOW_CTL, val);
sys/arch/arm/sunxi/sunxi_emac.c
488
WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
sys/arch/arm/sunxi/sunxi_emac.c
574
WR4(sc, EMAC_ADDR_HIGH(0), machi);
sys/arch/arm/sunxi/sunxi_emac.c
575
WR4(sc, EMAC_ADDR_LOW(0), maclo);
sys/arch/arm/sunxi/sunxi_emac.c
578
WR4(sc, EMAC_RX_HASH_0, hash[1]);
sys/arch/arm/sunxi/sunxi_emac.c
579
WR4(sc, EMAC_RX_HASH_1, hash[0]);
sys/arch/arm/sunxi/sunxi_emac.c
582
WR4(sc, EMAC_RX_FRM_FLT, val);
sys/arch/arm/sunxi/sunxi_emac.c
589
WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
sys/arch/arm/sunxi/sunxi_emac.c
596
WR4(sc, EMAC_INT_EN, 0);
sys/arch/arm/sunxi/sunxi_emac.c
646
WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
sys/arch/arm/sunxi/sunxi_emac.c
681
WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
sys/arch/arm/sunxi/sunxi_emac.c
682
WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
sys/arch/arm/sunxi/sunxi_emac.c
690
WR4(sc, EMAC_BASIC_CTL_1, val);
sys/arch/arm/sunxi/sunxi_emac.c
697
WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
sys/arch/arm/sunxi/sunxi_emac.c
701
WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
sys/arch/arm/sunxi/sunxi_emac.c
705
WR4(sc, EMAC_TX_CTL_0, val | TX_EN);
sys/arch/arm/sunxi/sunxi_emac.c
709
WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC);
sys/arch/arm/sunxi/sunxi_emac.c
748
WR4(sc, EMAC_TX_CTL_1, val);
sys/arch/arm/sunxi/sunxi_emac.c
752
WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN);
sys/arch/arm/sunxi/sunxi_emac.c
756
WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN);
sys/arch/arm/sunxi/sunxi_emac.c
763
WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
sys/arch/arm/sunxi/sunxi_emac.c
767
WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
sys/arch/arm/sunxi/sunxi_emac.c
901
WR4(sc, EMAC_INT_STA, val);
sys/arch/arm/sunxi/sunxi_gmacclk.c
192
WR4(sc, 0, val);
sys/arch/arm/sunxi/sunxi_thermal.c
360
WR4(sc, THS_CALIB0, calib[0]);
sys/arch/arm/sunxi/sunxi_thermal.c
362
WR4(sc, THS_CALIB1, calib[1]);
sys/arch/arm/sunxi/sunxi_thermal.c
366
WR4(sc, THS_CTRL1, ADC_CALI_EN);
sys/arch/arm/sunxi/sunxi_thermal.c
367
WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time);
sys/arch/arm/sunxi/sunxi_thermal.c
368
WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT);
sys/arch/arm/sunxi/sunxi_thermal.c
371
WR4(sc, THS_FILTER, sc->conf->filter);
sys/arch/arm/sunxi/sunxi_thermal.c
374
WR4(sc, THS_INTS, RD4(sc, THS_INTS));
sys/arch/arm/sunxi/sunxi_thermal.c
375
WR4(sc, THS_INTC, sc->conf->intc | SHUT_INT_ALL | ALARM_INT_ALL);
sys/arch/arm/sunxi/sunxi_thermal.c
378
WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);
sys/arch/arm/sunxi/sunxi_thermal.c
412
WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val);
sys/arch/arm/sunxi/sunxi_thermal.c
445
WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val);
sys/arch/arm/sunxi/sunxi_thermal.c
490
WR4(sc, THS_INTS, ints);
sys/arch/arm/ti/ti_dpll_clock.c
299
WR4(sc, REG_CONTROL, control);
sys/arch/arm/ti/ti_dpll_clock.c
306
WR4(sc, REG_MULT_DIV1, mult_div1);
sys/arch/arm/ti/ti_dpll_clock.c
310
WR4(sc, REG_CONTROL, control);
sys/arch/arm/ti/ti_dpll_clock.c
339
WR4(sc, REG_CONTROL, control);
sys/arch/arm/ti/ti_dpll_clock.c
345
WR4(sc, REG_MULT_DIV1, mult_div1);
sys/arch/arm/ti/ti_dpll_clock.c
349
WR4(sc, REG_CONTROL, control);
sys/arch/arm/ti/ti_gate_clock.c
174
WR4(sc, 0, val);
sys/arch/arm/ti/ti_gate_clock.c
188
WR4(sc, 0, val);
sys/arch/arm/ti/ti_gpio.c
162
WR4(sc, GPIO_OE, oe);
sys/arch/arm/ti/ti_gpio.c
254
WR4(sc, data_reg, data_mask);
sys/arch/arm/ti/ti_gpio.c
274
WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask);
sys/arch/arm/ti/ti_gpio.c
276
WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask);
sys/arch/arm/ti/ti_gpio.c
327
WR4(sc, GPIO_LEVELDETECT0, val);
sys/arch/arm/ti/ti_gpio.c
334
WR4(sc, GPIO_LEVELDETECT1, val);
sys/arch/arm/ti/ti_gpio.c
341
WR4(sc, GPIO_RISINGDETECT, val);
sys/arch/arm/ti/ti_gpio.c
348
WR4(sc, GPIO_FALLINGDETECT, val);
sys/arch/arm/ti/ti_gpio.c
353
WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
sys/arch/arm/ti/ti_gpio.c
355
WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
sys/arch/arm/ti/ti_gpio.c
419
WR4(sc, data_reg, data_mask);
sys/arch/arm/ti/ti_gpio.c
475
WR4(sc, GPIO_LEVELDETECT0, val);
sys/arch/arm/ti/ti_gpio.c
482
WR4(sc, GPIO_LEVELDETECT1, val);
sys/arch/arm/ti/ti_gpio.c
490
WR4(sc, GPIO_RISINGDETECT, val);
sys/arch/arm/ti/ti_gpio.c
498
WR4(sc, GPIO_FALLINGDETECT, val);
sys/arch/arm/ti/ti_gpio.c
503
WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
sys/arch/arm/ti/ti_gpio.c
505
WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
sys/arch/arm/ti/ti_gpio.c
575
WR4(sc, GPIO_IRQSTATUS1, status);
sys/arch/arm/ti/ti_lcdc.c
113
WR4(sc, LCD_LCDDMA_FB0_BASE, paddr);
sys/arch/arm/ti/ti_lcdc.c
114
WR4(sc, LCD_LCDDMA_FB0_CEILING, paddr + psize - 1);
sys/arch/arm/ti/ti_lcdc.c
190
WR4(sc, LCD_CTRL, val);
sys/arch/arm/ti/ti_lcdc.c
196
WR4(sc, LCD_RASTER_TIMING_0, val);
sys/arch/arm/ti/ti_lcdc.c
202
WR4(sc, LCD_RASTER_TIMING_1, val);
sys/arch/arm/ti/ti_lcdc.c
214
WR4(sc, LCD_RASTER_TIMING_2, val);
sys/arch/arm/ti/ti_lcdc.c
219
WR4(sc, LCD_LCDDMA_CTRL, val);
sys/arch/arm/ti/ti_lcdc.c
227
WR4(sc, LCD_RASTER_CTRL, val);
sys/arch/arm/ti/ti_lcdc.c
269
WR4(sc, LCD_CLKC_ENABLE, CLKC_ENABLE_DMA | CLKC_ENABLE_CORE);
sys/arch/arm/ti/ti_lcdc.c
270
WR4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN);
sys/arch/arm/ti/ti_lcdc.c
272
WR4(sc, LCD_CLKC_RESET, 0);
sys/arch/arm/ti/ti_lcdc.c
275
WR4(sc, LCD_RASTER_CTRL, val | RASTER_CTRL_LCDEN);
sys/arch/arm/ti/ti_lcdc.c
345
WR4(sc, LCD_SYSCONFIG, SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART);
sys/arch/arm/ti/ti_mux_clock.c
213
WR4(sc, 0, val);
sys/arch/arm/ti/ti_omapmusb.c
132
WR4(sc, OTG_SYSCONFIG, OTG_SYSCONFIG_SOFTRESET);
sys/arch/arm/ti/ti_omapmusb.c
153
WR4(sc, OTG_SYSCONFIG, val);
sys/arch/arm/ti/ti_omaptimer.c
128
WR4(sc, TIMER_TISR, OVF_IT_FLAG);
sys/arch/arm/ti/ti_omaptimer.c
152
WR4(sc, TIMER_TIER, OVF_EN_FLAG);
sys/arch/arm/ti/ti_omaptimer.c
167
WR4(sc, TIMER_TLDR, value);
sys/arch/arm/ti/ti_omaptimer.c
168
WR4(sc, TIMER_TCRR, value);
sys/arch/arm/ti/ti_omaptimer.c
169
WR4(sc, TIMER_TIER, 0);
sys/arch/arm/ti/ti_omaptimer.c
170
WR4(sc, TIMER_TCLR, TCLR_ST | TCLR_AR);
sys/arch/arm/ti/ti_rng.c
104
WR4(sc, TRNG_CONFIG_REG,
sys/arch/arm/ti/ti_rng.c
107
WR4(sc, TRNG_CONTROL_REG,
sys/arch/arm/ti/ti_rng.c
137
WR4(sc, TRNG_INTACK_REG, TRNG_INTACK_READY);
sys/arch/arm/ti/ti_usb.c
201
WR4(sc, UHH_SYSCONFIG, val);
sys/arch/arm/ti/ti_usb.c
219
WR4(sc, UHH_HOSTCONFIG, val);
sys/arch/arm/ti/ti_usbtll.c
122
WR4(sc, USBTLL_CHANNEL_CONF(port), val);
sys/arch/arm/ti/ti_usbtll.c
131
WR4(sc, USBTLL_SYSCONFIG, USBTLL_SYSCONFIG_SOFTRESET);
sys/arch/arm/ti/ti_usbtll.c
153
WR4(sc, USBTLL_SYSCONFIG, val);
sys/arch/arm/ti/ti_usbtll.c
159
WR4(sc, USBTLL_SHARED_CONF, val);
sys/arch/arm/ti/ti_wdt.c
123
WR4(sc, WDT_WDSC, val);
sys/arch/arm/ti/ti_wdt.c
137
WR4(sc, WDT_WSPR, 0xaaaa);
sys/arch/arm/ti/ti_wdt.c
139
WR4(sc, WDT_WSPR, 0x5555);
sys/arch/arm/ti/ti_wdt.c
146
WR4(sc, WDT_WSPR, 0xbbbb);
sys/arch/arm/ti/ti_wdt.c
148
WR4(sc, WDT_WSPR, 0x4444);
sys/arch/arm/ti/ti_wdt.c
176
WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV));
sys/arch/arm/ti/ti_wdt.c
177
WR4(sc, WDT_WLDR, counter_val);
sys/arch/arm/ti/ti_wdt.c
178
WR4(sc, WDT_WCRR, counter_val);
sys/arch/arm/ti/ti_wdt.c
195
WR4(sc, WDT_WTGR, ~val);
sys/arch/arm/xilinx/zynq_gpio.c
108
WR4(sc, OEN_REG(pin), oen);
sys/arch/arm/xilinx/zynq_gpio.c
109
WR4(sc, DIRM_REG(pin), dirm);
sys/arch/arm/xilinx/zynq_gpio.c
224
WR4(sc, MASK_DATA_REG(pin), mask_data);
sys/arch/arm/xilinx/zynq_xadc.c
172
WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_WRITE, reg, data));
sys/arch/arm/xilinx/zynq_xadc.c
207
WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_READ, reg, 0));
sys/arch/arm/xilinx/zynq_xadc.c
208
WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_NOP, 0, 0));
sys/arch/arm/xilinx/zynq_xadc.c
236
WR4(sc, XADCIF_CFG, val);
sys/arch/arm/xilinx/zynq_xadc.c
237
WR4(sc, XADCIF_MCTL, 0);
sys/arch/arm/xscale/ixp425_if_npe.c
1096
WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
sys/arch/arm/xscale/ixp425_if_npe.c
1099
WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
sys/arch/arm/xscale/ixp425_if_npe.c
1102
WR4(sc, NPE_MAC_RX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1104
WR4(sc, NPE_MAC_TX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1110
WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
sys/arch/arm/xscale/ixp425_if_npe.c
1111
WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
sys/arch/arm/xscale/ixp425_if_npe.c
1112
WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
sys/arch/arm/xscale/ixp425_if_npe.c
1114
WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
sys/arch/arm/xscale/ixp425_if_npe.c
1115
WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
sys/arch/arm/xscale/ixp425_if_npe.c
1116
WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT);
sys/arch/arm/xscale/ixp425_if_npe.c
1118
WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
sys/arch/arm/xscale/ixp425_if_npe.c
1119
WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
sys/arch/arm/xscale/ixp425_if_npe.c
1120
WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
sys/arch/arm/xscale/ixp425_if_npe.c
1121
WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
sys/arch/arm/xscale/ixp425_if_npe.c
1122
WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
sys/arch/arm/xscale/ixp425_if_npe.c
1124
WR4(sc, NPE_MAC_TX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1130
WR4(sc, NPE_MAC_RX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1133
WR4(sc, NPE_MAC_RX_CNTRL2, 0);
sys/arch/arm/xscale/ixp425_if_npe.c
1177
WR4(sc, NPE_MAC_RX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1179
WR4(sc, NPE_MAC_TX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1354
WR4(sc, NPE_MAC_RX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1356
WR4(sc, NPE_MAC_TX_CNTRL1,
sys/arch/arm/xscale/ixp425_if_npe.c
1371
WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
sys/arch/arm/xscale/ixp425_if_npe.c
1373
WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
sys/arch/arm/xscale/ixp425_if_npe.c
1374
WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
sys/arch/arm/xscale/ixp425_if_npe.c
1647
WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
sys/arch/arm/xscale/ixp425_if_npe.c
1655
WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT
sys/arch/arm/xscale/ixp425_if_npe.c
1660
WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
sys/arch/arm/xscale/ixp425_if_npe.c
1661
WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
sys/arch/arm/xscale/ixp425_if_npe.c
352
WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN);
sys/arch/arm/xscale/ixp425_if_npe.c
400
WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
sys/arch/arm/xscale/ixp425_if_npe.c
401
WR4(sc, NPE_MAC_ADDR(i), addr[i]);
sys/arch/arm/xscale/ixp425_if_npe.c
742
WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
sys/arch/arm/xscale/ixp425_if_npe.c
743
WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
sys/arch/arm/xscale/ixp425_if_npe.c
744
WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
sys/arch/arm/xscale/ixp425_if_npe.c
745
WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
sys/arch/arm/xscale/ixp425_if_npe.c
746
WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
sys/arch/arm/xscale/ixp425_if_npe.c
747
WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
sys/arch/evbppc/nintendo/dev/ahb.c
179
WR4(HW_PPCIRQMASK, pic_irqmask[0]);
sys/arch/evbppc/nintendo/dev/ahb.c
186
WR4(HW_PPCIRQMASK, pic_irqmask[0]);
sys/arch/evbppc/nintendo/dev/ahb.c
208
WR4(HW_PPCIRQFLAGS, __BIT(irq));
sys/arch/evbppc/nintendo/dev/ahb.c
219
WR4(HW_ARMIRQMASK, val);
sys/arch/evbppc/nintendo/dev/ahb.c
220
WR4(HW_ARMIRQFLAGS, __BIT(irq));
sys/arch/evbppc/nintendo/dev/ahb.c
229
WR4(reg_en, pic_irqmask[irq / 32]);
sys/arch/evbppc/nintendo/dev/ahb.c
238
WR4(reg_en, pic_irqmask[irq / 32]);
sys/arch/evbppc/nintendo/dev/ahb.c
268
WR4(reg_sts, __BIT(irq % 32));
sys/arch/evbppc/nintendo/dev/ahb.c
281
WR4(reg_en, val);
sys/arch/evbppc/nintendo/dev/ahb.c
282
WR4(reg_sts, __BIT(irq % 32));
sys/arch/evbppc/nintendo/dev/ahb.c
294
WR4(LT_PPCnINT1EN(0), 0);
sys/arch/evbppc/nintendo/dev/ahb.c
295
WR4(LT_PPCnINT2EN(0), 0);
sys/arch/evbppc/nintendo/dev/ahb.c
296
WR4(LT_PPCnINT1STS(0), ~0U);
sys/arch/evbppc/nintendo/dev/ahb.c
297
WR4(LT_PPCnINT2STS(0), ~0U);
sys/arch/evbppc/nintendo/dev/ahb.c
301
WR4(HW_PPCIRQMASK, 0);
sys/arch/evbppc/nintendo/dev/ahb.c
302
WR4(HW_PPCIRQFLAGS, ~0U);
sys/arch/evbppc/nintendo/dev/ahb.c
337
WR4(HW_AHBPROT, RD4(HW_AHBPROT) & ~mask);
sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c
108
WR4(sc, SATA_HCCFG_INT_REG, ~0U);
sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c
109
WR4(sc, SATA_HCCFG_INTMSK_REG, SATA_HCCFG_INT_PORT0 |
sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c
75
WR4(sc, SATA_HCCFG_INT_REG, val);
sys/arch/evbppc/nintendo/dev/avenc.c
213
WR4(tag, addr, 0x7a, 0);
sys/arch/evbppc/nintendo/dev/avenc.c
219
WR4(tag, addr, 0x7a, 0);
sys/arch/evbppc/nintendo/dev/bwai.c
221
WR4(sc, AI_CONTROL, 0);
sys/arch/evbppc/nintendo/dev/bwai.c
226
WR4(sc, AI_AIIT, sc->sc_intrnext);
sys/arch/evbppc/nintendo/dev/bwai.c
232
WR4(sc, AI_CONTROL, val);
sys/arch/evbppc/nintendo/dev/bwai.c
235
WR4(sc, AI_CONTROL, val);
sys/arch/evbppc/nintendo/dev/bwai.c
245
WR4(sc, AI_CONTROL, 0);
sys/arch/evbppc/nintendo/dev/bwai.c
98
WR4(sc, AI_AIIT, sc->sc_intrnext);
sys/arch/evbppc/nintendo/dev/bwai.c
99
WR4(sc, AI_CONTROL, val);
sys/arch/evbppc/nintendo/dev/di.c
263
WR4(sc, DICMDBUF0, DI_CMD_REQUEST_ERROR);
sys/arch/evbppc/nintendo/dev/di.c
264
WR4(sc, DICMDBUF1, 0);
sys/arch/evbppc/nintendo/dev/di.c
265
WR4(sc, DICMDBUF2, 0);
sys/arch/evbppc/nintendo/dev/di.c
266
WR4(sc, DILENGTH, 4);
sys/arch/evbppc/nintendo/dev/di.c
267
WR4(sc, DICR, DICR_TSTART);
sys/arch/evbppc/nintendo/dev/di.c
411
WR4(sc, DISR, sr);
sys/arch/evbppc/nintendo/dev/di.c
412
WR4(sc, DICVR, cvr);
sys/arch/evbppc/nintendo/dev/di.c
466
WR4(sc, DISR, DISR_BRKINT |
sys/arch/evbppc/nintendo/dev/di.c
469
WR4(sc, DICVR, DICVR_CVRINT | DICVR_CVRINTMASK);
sys/arch/evbppc/nintendo/dev/di.c
493
WR4(sc, DISR, DISR_BRKINT |
sys/arch/evbppc/nintendo/dev/di.c
496
WR4(sc, DICVR, DICVR_CVRINT | DICVR_CVRINTMASK);
sys/arch/evbppc/nintendo/dev/di.c
512
WR4(sc, DICMDBUF0, DI_CMD_STOP_MOTOR | cmdflags);
sys/arch/evbppc/nintendo/dev/di.c
513
WR4(sc, DICMDBUF1, 0);
sys/arch/evbppc/nintendo/dev/di.c
514
WR4(sc, DICMDBUF2, 0);
sys/arch/evbppc/nintendo/dev/di.c
515
WR4(sc, DILENGTH, 4);
sys/arch/evbppc/nintendo/dev/di.c
516
WR4(sc, DICR, DICR_TSTART);
sys/arch/evbppc/nintendo/dev/di.c
550
WR4(sc, DICMDBUF0, DI_CMD_INQUIRY);
sys/arch/evbppc/nintendo/dev/di.c
551
WR4(sc, DICMDBUF1, 0);
sys/arch/evbppc/nintendo/dev/di.c
552
WR4(sc, DILENGTH, sizeof(struct di_response_inquiry));
sys/arch/evbppc/nintendo/dev/di.c
553
WR4(sc, DIMAR, sc->sc_dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/di.c
554
WR4(sc, DICR, DICR_TSTART | DICR_DMA);
sys/arch/evbppc/nintendo/dev/di.c
562
WR4(sc, DICMDBUF0, DI_CMD_REQUEST_ERROR);
sys/arch/evbppc/nintendo/dev/di.c
563
WR4(sc, DICMDBUF1, 0);
sys/arch/evbppc/nintendo/dev/di.c
564
WR4(sc, DICMDBUF2, 0);
sys/arch/evbppc/nintendo/dev/di.c
565
WR4(sc, DILENGTH, 4);
sys/arch/evbppc/nintendo/dev/di.c
566
WR4(sc, DICR, DICR_TSTART);
sys/arch/evbppc/nintendo/dev/di.c
590
WR4(sc, DICMDBUF0, DI_CMD_READ_DVD);
sys/arch/evbppc/nintendo/dev/di.c
591
WR4(sc, DICMDBUF1, blkno);
sys/arch/evbppc/nintendo/dev/di.c
592
WR4(sc, DICMDBUF2, howmany(xs->datalen, DVDBLOCKSIZE));
sys/arch/evbppc/nintendo/dev/di.c
593
WR4(sc, DILENGTH, roundup(xs->datalen, DVDBLOCKSIZE));
sys/arch/evbppc/nintendo/dev/di.c
594
WR4(sc, DIMAR, sc->sc_dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/di.c
595
WR4(sc, DICR, DICR_TSTART | DICR_DMA);
sys/arch/evbppc/nintendo/dev/di.c
612
WR4(sc, DICMDBUF0, DI_CMD_READ_DVD_STRUCT(cmd->bytes[6]));
sys/arch/evbppc/nintendo/dev/di.c
613
WR4(sc, DICMDBUF1, 0);
sys/arch/evbppc/nintendo/dev/di.c
614
WR4(sc, DICMDBUF2, 0);
sys/arch/evbppc/nintendo/dev/di.c
615
WR4(sc, DILENGTH, roundup(xs->datalen, DVDBLOCKSIZE));
sys/arch/evbppc/nintendo/dev/di.c
616
WR4(sc, DIMAR, sc->sc_dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/di.c
617
WR4(sc, DICR, DICR_TSTART | DICR_DMA);
sys/arch/evbppc/nintendo/dev/di.c
634
WR4(sc, DICMDBUF0, DI_CMD_REPORT_KEY(cmd->bytes[9] >> 2));
sys/arch/evbppc/nintendo/dev/di.c
635
WR4(sc, DICMDBUF1, _4btol(&cmd->bytes[1]));
sys/arch/evbppc/nintendo/dev/di.c
636
WR4(sc, DICMDBUF2, 0);
sys/arch/evbppc/nintendo/dev/di.c
637
WR4(sc, DILENGTH, roundup(xs->datalen, 0x20));
sys/arch/evbppc/nintendo/dev/di.c
638
WR4(sc, DIMAR, sc->sc_dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/di.c
639
WR4(sc, DICR, DICR_TSTART | DICR_DMA);
sys/arch/evbppc/nintendo/dev/di.c
649
WR4(sc, DICMDBUF0, DI_CMD_READ_DVD_STRUCT(DVD_STRUCT_PHYSICAL));
sys/arch/evbppc/nintendo/dev/di.c
650
WR4(sc, DICMDBUF1, 0);
sys/arch/evbppc/nintendo/dev/di.c
651
WR4(sc, DICMDBUF2, 0);
sys/arch/evbppc/nintendo/dev/di.c
652
WR4(sc, DILENGTH, DVDBLOCKSIZE);
sys/arch/evbppc/nintendo/dev/di.c
653
WR4(sc, DIMAR, sc->sc_dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/di.c
654
WR4(sc, DICR, DICR_TSTART | DICR_DMA);
sys/arch/evbppc/nintendo/dev/exi.c
214
WR4(exi_softc, EXI_CSR(chan), val);
sys/arch/evbppc/nintendo/dev/exi.c
229
WR4(exi_softc, EXI_CSR(chan), val);
sys/arch/evbppc/nintendo/dev/exi.c
271
WR4(exi_softc, EXI_DATA(chan), val);
sys/arch/evbppc/nintendo/dev/exi.c
272
WR4(exi_softc, EXI_CR(chan),
sys/arch/evbppc/nintendo/dev/exi.c
291
WR4(exi_softc, EXI_CR(chan),
sys/arch/evbppc/nintendo/dev/exi.c
336
WR4(exi_softc, EXI_DATA(chan), val);
sys/arch/evbppc/nintendo/dev/exi.c
337
WR4(exi_softc, EXI_CR(chan),
sys/arch/evbppc/nintendo/dev/exi.c
383
WR4(exi_softc, EXI_MAR(chan), ch->ch_dmamap->dm_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/exi.c
384
WR4(exi_softc, EXI_LENGTH(chan), datalen);
sys/arch/evbppc/nintendo/dev/exi.c
385
WR4(exi_softc, EXI_CR(chan),
sys/arch/evbppc/nintendo/dev/gecko.c
123
WR4(EXI_CSR(usbgecko_chan), USBGECKO_CSR);
sys/arch/evbppc/nintendo/dev/gecko.c
124
WR4(EXI_DATA(usbgecko_chan), command32);
sys/arch/evbppc/nintendo/dev/gecko.c
125
WR4(EXI_CR(usbgecko_chan), USBGECKO_CR(2, EXI_CR_RW_READWRITE));
sys/arch/evbppc/nintendo/dev/gecko.c
128
WR4(EXI_CSR(usbgecko_chan), 0);
sys/arch/evbppc/nintendo/dev/gecko.c
141
WR4(EXI_CSR(usbgecko_chan), USBGECKO_CSR);
sys/arch/evbppc/nintendo/dev/gecko.c
142
WR4(EXI_DATA(usbgecko_chan), 0);
sys/arch/evbppc/nintendo/dev/gecko.c
143
WR4(EXI_CR(usbgecko_chan), USBGECKO_CR(2, EXI_CR_RW_READWRITE));
sys/arch/evbppc/nintendo/dev/gecko.c
145
WR4(EXI_CR(usbgecko_chan), USBGECKO_CR(sizeof(value),
sys/arch/evbppc/nintendo/dev/gecko.c
149
WR4(EXI_CSR(usbgecko_chan), 0);
sys/arch/evbppc/nintendo/dev/gecko.c
185
WR4(EXI_CSR(0), 0);
sys/arch/evbppc/nintendo/dev/gecko.c
186
WR4(EXI_CSR(1), 0);
sys/arch/evbppc/nintendo/dev/gecko.c
187
WR4(EXI_CSR(2), 0);
sys/arch/evbppc/nintendo/dev/gecko.c
189
WR4(EXI_CSR(0), EXI_CSR_EXTINT | EXI_CSR_EXTINTMASK);
sys/arch/evbppc/nintendo/dev/gecko.c
190
WR4(EXI_CSR(1), EXI_CSR_EXTINT | EXI_CSR_EXTINTMASK);
sys/arch/evbppc/nintendo/dev/hwaes.c
158
WR4(sc, AES_CTRL, 0);
sys/arch/evbppc/nintendo/dev/hwaes.c
259
WR4(sc, AES_SRC, sc->sc_dma_bounce.dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/hwaes.c
260
WR4(sc, AES_DEST, sc->sc_dma_bounce.dma_segs[0].ds_addr);
sys/arch/evbppc/nintendo/dev/hwaes.c
265
WR4(sc, AES_CTRL, ctrl);
sys/arch/evbppc/nintendo/dev/hwaes.c
294
WR4(sc, AES_IV, 0);
sys/arch/evbppc/nintendo/dev/hwaes.c
297
WR4(sc, AES_KEY, enc->aese_aes.aes_rk[n]);
sys/arch/evbppc/nintendo/dev/hwaes.c
336
WR4(sc, AES_IV, 0);
sys/arch/evbppc/nintendo/dev/hwaes.c
339
WR4(sc, AES_KEY, dec->aesd_aes.aes_rk[n]);
sys/arch/evbppc/nintendo/dev/hwaes.c
387
WR4(sc, AES_IV, be32dec(&iv[n * 4]));
sys/arch/evbppc/nintendo/dev/hwaes.c
390
WR4(sc, AES_KEY, enc->aese_aes.aes_rk[n]);
sys/arch/evbppc/nintendo/dev/hwaes.c
445
WR4(sc, AES_IV, be32dec(&iv[n * 4]));
sys/arch/evbppc/nintendo/dev/hwaes.c
451
WR4(sc, AES_KEY, dec->aesd_aes.aes_rk[n]);
sys/arch/evbppc/nintendo/dev/hwgpio.c
157
WR4(sc, GPIOB_OUT, out);
sys/arch/evbppc/nintendo/dev/hwgpio.c
174
WR4(sc, GPIOB_DIR, dir);
sys/arch/evbppc/nintendo/dev/si.c
204
WR4(sc, SIPOLL,
sys/arch/evbppc/nintendo/dev/si.c
207
WR4(sc, SICOMCSR, SICOMCSR_RDSTINT | SICOMCSR_RDSTINTMSK);
sys/arch/evbppc/nintendo/dev/si.c
318
WR4(sc, SICOMCSR, comcsr | SICOMCSR_TCINT);
sys/arch/evbppc/nintendo/dev/si.c
338
WR4(sc, SISR, sr & SISR_ERROR_ACK_ALL);
sys/arch/evbppc/nintendo/dev/si.c
372
WR4(sc, SICOUTBUF(ch->ch_index), 0x00400300);
sys/arch/evbppc/nintendo/dev/si.c
375
WR4(sc, SIPOLL, RD4(sc, SIPOLL) | SIPOLL_EN(ch->ch_index));
sys/arch/evbppc/nintendo/dev/si.c
377
WR4(sc, SISR, SISR_WR(ch->ch_index));
sys/arch/evbppc/nintendo/dev/si.c
378
WR4(sc, SICOMCSR, RD4(sc, SICOMCSR) | SICOMCSR_TSTART);
sys/arch/evbppc/nintendo/dev/si.c
410
WR4(sc, SIPOLL, RD4(sc, SIPOLL) & ~SIPOLL_EN(ch->ch_index));
sys/arch/evbppc/nintendo/dev/wiifb.c
272
WR4(sc, VI_DI0, VI_DI_ENB |
sys/arch/evbppc/nintendo/dev/wiifb.c
275
WR4(sc, VI_DI1, 0);
sys/arch/evbppc/nintendo/dev/wiifb.c
276
WR4(sc, VI_DI2, 0);
sys/arch/evbppc/nintendo/dev/wiifb.c
277
WR4(sc, VI_DI3, 0);
sys/arch/evbppc/nintendo/dev/wiifb.c
678
WR4(sc, VI_DI0, RD4(sc, VI_DI0) & ~VI_DI_INT);
sys/arch/evbppc/nintendo/dev/wiifb.c
679
WR4(sc, VI_DI1, RD4(sc, VI_DI1) & ~VI_DI_INT);
sys/arch/evbppc/nintendo/dev/wiifb.c
680
WR4(sc, VI_DI2, RD4(sc, VI_DI2) & ~VI_DI_INT);
sys/arch/evbppc/nintendo/dev/wiifb.c
681
WR4(sc, VI_DI3, RD4(sc, VI_DI3) & ~VI_DI_INT);
sys/arch/evbppc/nintendo/dev/wiifb.c
729
WR4(sc, VI_HTR0, 0x476901AD);
sys/arch/evbppc/nintendo/dev/wiifb.c
730
WR4(sc, VI_HTR1, 0x02EA5140);
sys/arch/evbppc/nintendo/dev/wiifb.c
731
WR4(sc, VI_VTO, 0x00030018);
sys/arch/evbppc/nintendo/dev/wiifb.c
732
WR4(sc, VI_VTE, 0x00020019);
sys/arch/evbppc/nintendo/dev/wiifb.c
733
WR4(sc, VI_BBOI, 0x410C410C);
sys/arch/evbppc/nintendo/dev/wiifb.c
734
WR4(sc, VI_BBEI, 0x40ED40ED);
sys/arch/evbppc/nintendo/dev/wiifb.c
740
WR4(sc, VI_HTR0, 0x476901ad);
sys/arch/evbppc/nintendo/dev/wiifb.c
741
WR4(sc, VI_HTR1, 0x030a4940);
sys/arch/evbppc/nintendo/dev/wiifb.c
742
WR4(sc, VI_VTO, 0x00060030);
sys/arch/evbppc/nintendo/dev/wiifb.c
743
WR4(sc, VI_VTE, 0x00060030);
sys/arch/evbppc/nintendo/dev/wiifb.c
744
WR4(sc, VI_BBOI, 0x81d881d8);
sys/arch/evbppc/nintendo/dev/wiifb.c
745
WR4(sc, VI_BBEI, 0x81d881d8);
sys/arch/evbppc/nintendo/dev/wiifb.c
751
WR4(sc, VI_HTR0, 0x4b6a01b0);
sys/arch/evbppc/nintendo/dev/wiifb.c
752
WR4(sc, VI_HTR1, 0x02f85640);
sys/arch/evbppc/nintendo/dev/wiifb.c
753
WR4(sc, VI_VTO, 0x00010023);
sys/arch/evbppc/nintendo/dev/wiifb.c
754
WR4(sc, VI_VTE, 0x00000024);
sys/arch/evbppc/nintendo/dev/wiifb.c
755
WR4(sc, VI_BBOI, 0x4d2b4d6d);
sys/arch/evbppc/nintendo/dev/wiifb.c
756
WR4(sc, VI_BBEI, 0x4d8a4d4c);
sys/arch/evbppc/nintendo/dev/wiifb.c
774
WR4(sc, VI_FCT0, 0x1ae771f0);
sys/arch/evbppc/nintendo/dev/wiifb.c
775
WR4(sc, VI_FCT1, 0x0db4a574);
sys/arch/evbppc/nintendo/dev/wiifb.c
776
WR4(sc, VI_FCT2, 0x00c1188e);
sys/arch/evbppc/nintendo/dev/wiifb.c
777
WR4(sc, VI_FCT3, 0xc4c0cbe2);
sys/arch/evbppc/nintendo/dev/wiifb.c
778
WR4(sc, VI_FCT4, 0xfcecdecf);
sys/arch/evbppc/nintendo/dev/wiifb.c
779
WR4(sc, VI_FCT5, 0x13130f08);
sys/arch/evbppc/nintendo/dev/wiifb.c
780
WR4(sc, VI_FCT6, 0x00080C0f);
sys/arch/evbppc/nintendo/dev/wiifb.c
783
WR4(sc, VI_UNKNOWN_68H, 0x00ff0000);
sys/arch/evbppc/nintendo/dev/wiifb.c
785
WR4(sc, VI_UNKNOWN_78H, 0x00ff00ff);
sys/arch/evbppc/nintendo/dev/wiifb.c
786
WR4(sc, VI_UNKNOWN_7CH, 0x00ff00ff);
sys/arch/evbppc/nintendo/dev/wiifb.c
823
WR4(sc, VI_TFBL,
sys/arch/evbppc/nintendo/dev/wiifb.c
827
WR4(sc, VI_TFBR, 0);
sys/arch/evbppc/nintendo/dev/wiifb.c
829
WR4(sc, VI_BFBL,
sys/arch/evbppc/nintendo/dev/wiifb.c
833
WR4(sc, VI_BFBR, 0);
sys/arch/evbppc/nintendo/pic_pi.c
101
WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
sys/arch/evbppc/nintendo/pic_pi.c
141
WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
sys/arch/evbppc/nintendo/pic_pi.c
152
WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
sys/arch/evbppc/nintendo/pic_pi.c
153
WR4(pic_s[cpu_num].intsr, __BIT(irq));
sys/arch/evbppc/nintendo/pic_pi.c
185
WR4(pic_s[cpu_num].intmr, 0);
sys/arch/evbppc/nintendo/pic_pi.c
186
WR4(pic_s[cpu_num].intsr, ~0U);
sys/arch/evbppc/nintendo/pic_pi.c
92
WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
sys/arch/luna68k/dev/lunaws.c
233
setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
sys/arch/luna68k/dev/siotty.c
193
setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
sys/arch/luna68k/dev/siotty.c
449
sc->sc_wr[WR4] = wr4;
sys/arch/luna68k/dev/siotty.c
452
setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
sys/arch/luna68k/dev/siotty.c
722
setsioreg(sio, WR4, ch0_regs[WR4]);
sys/arch/luna68k/stand/boot/sio.c
226
sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY);
sys/arch/luna68k/stand/boot/sio.c
242
sioreg(REG(1, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY);
sys/arch/powerpc/mpc5200/mpc5200_ac97.c
323
WR4(sc, PSC_SICR, SICR_NORMAL_AC97);
sys/arch/powerpc/mpc5200/mpc5200_ac97.c
324
WR4(sc, PSC_AC97SLOTS, AC97SLOTS_TX_STEREO);
sys/arch/powerpc/mpc5200/mpc5200_ac97.c
387
WR4(sc, PSC_AC97CMD, AC97CMD_READ | AC97CMD_INDEX(reg));
sys/arch/powerpc/mpc5200/mpc5200_ac97.c
407
WR4(sc, PSC_AC97CMD, AC97CMD_WRITE(reg, val));
sys/arch/riscv/sifive/fu540_ccache.c
123
WR4(sc, CCACHE_FLUSH32, fpa >> 4);
sys/arch/riscv/sifive/fu540_prci.c
165
WR4(sc, DDRPLLCFG1, val | PLL1_CKE);
sys/arch/riscv/sifive/fu540_prci.c
169
WR4(sc, GEMGXLPLLCFG1, val | PLL1_CKE);
sys/arch/riscv/starfive/jh7110_clkc.c
1012
WR4(sc, assert_reg, val | __BIT(bit));
sys/arch/riscv/starfive/jh7110_clkc.c
1014
WR4(sc, assert_reg, val & ~__BIT(bit));
sys/arch/riscv/starfive/jh7110_pcie.c
371
WR4(sc, PLDA_ISTATUS_LOCAL, status);
sys/arch/riscv/starfive/jh7110_pcie.c
516
WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_LO(0),
sys/arch/riscv/starfive/jh7110_pcie.c
520
WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(0), BUS_ADDR_HI32(sc->sc_cfg_addr));
sys/arch/riscv/starfive/jh7110_pcie.c
521
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(0), 0);
sys/arch/riscv/starfive/jh7110_pcie.c
522
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(0), 0);
sys/arch/riscv/starfive/jh7110_pcie.c
523
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_PARAM(0), PLDA_TRSL_ID_PCIE_CONFIG);
sys/arch/riscv/starfive/jh7110_pcie.c
544
WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_LO(n),
sys/arch/riscv/starfive/jh7110_pcie.c
548
WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(n), BUS_ADDR_HI32(phyaddr));
sys/arch/riscv/starfive/jh7110_pcie.c
549
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(n), BUS_ADDR_LO32(pciaddr));
sys/arch/riscv/starfive/jh7110_pcie.c
550
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(n), BUS_ADDR_HI32(pciaddr));
sys/arch/riscv/starfive/jh7110_pcie.c
551
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_PARAM(n), PLDA_TRSL_ID_PCIE_RX_TX);
sys/arch/riscv/starfive/jh7110_pcie.c
557
WR4(sc, PLDA_ATR0_PCIE_WIN0_SRCADDR_PARAM, val);
sys/arch/riscv/starfive/jh7110_pcie.c
558
WR4(sc, PLDA_ATR0_PCIE_WIN0_SRC_ADDR, 0);
sys/arch/riscv/starfive/jh7110_pcie.c
680
WR4(sc, PLDA_IMASK_LOCAL, 0);
sys/arch/riscv/starfive/jh7110_pcie.c
681
WR4(sc, PLDA_ISTATUS_LOCAL, 0xffffffff);
sys/arch/riscv/starfive/jh7110_pcie.c
85
WR4((sc), (off), RD4((sc), (off)) | (mask))
sys/arch/riscv/starfive/jh7110_pcie.c
87
WR4((sc), (off), RD4((sc), (off)) & ~(mask))
sys/arch/riscv/starfive/jh7110_pcie.c
89
WR4((sc), (off), (RD4((sc), (off)) & ~(clr)) | (set))
sys/arch/riscv/starfive/jh7110_pciephy.c
137
WR4(sc, PCIE_KVCO_LEVEL, PCEI_PHY_KVCO_FINE_TUNE_LEVEL);
sys/arch/riscv/starfive/jh7110_pciephy.c
138
WR4(sc, PCIE_KVCO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNALS);
sys/arch/riscv/starfive/jh7110_pinctrl.c
322
WR4(sc, jfs->jfs_funcreg, funcval);
sys/arch/riscv/starfive/jh7110_pinctrl.c
351
WR4(sc, dout_reg, doutval);
sys/arch/riscv/starfive/jh7110_pinctrl.c
352
WR4(sc, doen_reg, doenval);
sys/arch/riscv/starfive/jh7110_pinctrl.c
367
WR4(sc, din_reg, dinval);
sys/arch/riscv/starfive/jh7110_pinctrl.c
562
WR4(sc, GPO_DOEN_CFG(pin_no), GPO_DISABLE);
sys/arch/riscv/starfive/jh7110_pinctrl.c
679
WR4(sc, sc->sc_jpd->jpd_dout + offset, bank);
sys/arch/riscv/starfive/jh7110_syscon.c
91
WR4(sc, reg, val);
sys/arch/riscv/starfive/jh7110_trng.c
153
WR4(sc, JH7110_TRNG_IENABLE,
sys/arch/riscv/starfive/jh7110_trng.c
163
WR4(sc, JH7110_TRNG_IENABLE, 0);
sys/arch/riscv/starfive/jh7110_trng.c
178
WR4(sc, JH7110_TRNG_ISTATUS,
sys/arch/riscv/starfive/jh7110_trng.c
200
WR4(sc, JH7110_TRNG_CTRL,
sys/arch/riscv/starfive/jh7110_trng.c
206
WR4(sc, JH7110_TRNG_CTRL,
sys/arch/riscv/starfive/jh7110_trng.c
252
WR4(sc, JH7110_TRNG_ISTATUS, istat);
sys/arch/riscv/starfive/jh7110_trng.c
267
WR4(sc, JH7110_TRNG_IENABLE, 0U);
sys/arch/riscv/starfive/jh7110_trng.c
268
WR4(sc, JH7110_TRNG_ISTATUS, ~0U);
sys/arch/riscv/starfive/jh7110_trng.c
270
WR4(sc, JH7110_TRNG_MODE, JH7110_TRNG_MODE_R256);
sys/arch/riscv/starfive/jh7110_trng.c
277
WR4(sc, JH7110_TRNG_CTRL, JH7110_TRNG_CTRL_RANDOM_RESEED);
sys/arch/riscv/starfive/jh71x0_clkc.c
161
WR4(sc, jcc->jcc_reg, val);
sys/arch/riscv/starfive/jh71x0_clkc.c
381
WR4(sc, jcc->jcc_reg, val);
sys/arch/riscv/starfive/jh71x0_clkc.c
60
WR4(sc, jcc->jcc_reg, val);
sys/arch/riscv/starfive/jh71x0_temp.c
100
WR4(sc, JH71X0_TEMP, JH71X0_TEMP_RSTN);
sys/arch/riscv/starfive/jh71x0_temp.c
104
WR4(sc, JH71X0_TEMP, JH71X0_TEMP_RSTN | JH71X0_TEMP_RUN);
sys/arch/riscv/starfive/jh71x0_temp.c
92
WR4(sc, JH71X0_TEMP, JH71X0_TEMP_PD);
sys/arch/riscv/starfive/jh71x0_temp.c
96
WR4(sc, JH71X0_TEMP, 0);
sys/dev/acpi/amdgpio.c
364
WR4(sc, AMDGPIO_PIN_REG(pin), val);
sys/dev/acpi/amdgpio.c
427
WR4(sc, AMDGPIO_PIN_REG(pin), val);
sys/dev/acpi/amdgpio.c
447
WR4(sc, AMDGPIO_PIN_REG(aih->ih_pin), val);
sys/dev/acpi/amdgpio.c
474
WR4(sc, AMDGPIO_PIN_REG(aih->ih_pin), val);
sys/dev/acpi/amdgpio.c
486
WR4(sc, AMDGPIO_PIN_REG(aih->ih_pin), val);
sys/dev/acpi/amdgpio.c
523
WR4(sc, AMDGPIO_PIN_REG(pin), val);
sys/dev/acpi/amdgpio.c
530
WR4(sc, AMDGPIO_INTR_MASTER, val);
sys/dev/acpi/qcomgpio.c
511
WR4(sc, TLMM_GPIO_IN_OUT(pin), val);
sys/dev/acpi/qcomgpio.c
589
WR4(sc, TLMM_GPIO_INTR_CFG(pin), val);
sys/dev/acpi/qcomgpio.c
614
WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
sys/dev/acpi/qcomgpio.c
644
WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
sys/dev/acpi/qcomgpio.c
659
WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
sys/dev/acpi/qcomgpio.c
682
WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val);
sys/dev/fdt/dwc3_fdt.c
158
WR4(sc, DWC3_GUSB2PHYCFG(0), val);
sys/dev/fdt/dwc3_fdt.c
166
WR4(sc, DWC3_GUSB3PIPECTL(0), val);
sys/dev/fdt/dwc3_fdt.c
172
WR4(sc, DWC3_GUCTL1, val);
sys/dev/fdt/dwc3_fdt.c
191
WR4(sc, DWC3_DCFG, val);
sys/dev/fdt/dwc3_fdt.c
202
WR4(sc, DWC3_GCTL, val);
sys/dev/fdt/dwc3_fdt.c
95
WR4((sc), (reg), RD4((sc), (reg)) | (mask))
sys/dev/fdt/dwc3_fdt.c
97
WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
sys/dev/ic/bcmgenet.c
125
WR4(sc, GENET_MDIO_CMD,
sys/dev/ic/bcmgenet.c
167
WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
sys/dev/ic/bcmgenet.c
172
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
191
WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), BUS_ADDR_LO32(paddr));
sys/dev/ic/bcmgenet.c
192
WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), BUS_ADDR_HI32(paddr));
sys/dev/ic/bcmgenet.c
193
WR4(sc, GENET_TX_DESC_STATUS(index), status);
sys/dev/ic/bcmgenet.c
261
WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), BUS_ADDR_LO32(paddr));
sys/dev/ic/bcmgenet.c
262
WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), BUS_ADDR_HI32(paddr));
sys/dev/ic/bcmgenet.c
302
WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
sys/dev/ic/bcmgenet.c
310
WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff);
sys/dev/ic/bcmgenet.c
311
WR4(sc, GENET_INTRL2_CPU_CLEAR, 0xffffffff);
sys/dev/ic/bcmgenet.c
333
WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0);
sys/dev/ic/bcmgenet.c
334
WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1);
sys/dev/ic/bcmgenet.c
384
WR4(sc, GENET_UMAC_CMD, cmd);
sys/dev/ic/bcmgenet.c
385
WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl);
sys/dev/ic/bcmgenet.c
397
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
sys/dev/ic/bcmgenet.c
401
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
sys/dev/ic/bcmgenet.c
404
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
sys/dev/ic/bcmgenet.c
407
WR4(sc, GENET_UMAC_CMD, 0);
sys/dev/ic/bcmgenet.c
408
WR4(sc, GENET_UMAC_CMD,
sys/dev/ic/bcmgenet.c
411
WR4(sc, GENET_UMAC_CMD, 0);
sys/dev/ic/bcmgenet.c
413
WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
sys/dev/ic/bcmgenet.c
415
WR4(sc, GENET_UMAC_MIB_CTRL, 0);
sys/dev/ic/bcmgenet.c
417
WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536);
sys/dev/ic/bcmgenet.c
421
WR4(sc, GENET_RBUF_CTRL, val);
sys/dev/ic/bcmgenet.c
423
WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1);
sys/dev/ic/bcmgenet.c
446
WR4(sc, GENET_RX_DMA_MBUF_DONE_THRES(qid), count);
sys/dev/ic/bcmgenet.c
451
WR4(sc, GENET_RX_DMA_RING_TIMEOUT(qid), val);
sys/dev/ic/bcmgenet.c
462
WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), count);
sys/dev/ic/bcmgenet.c
475
WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08);
sys/dev/ic/bcmgenet.c
477
WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
sys/dev/ic/bcmgenet.c
478
WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
479
WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);
sys/dev/ic/bcmgenet.c
480
WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);
sys/dev/ic/bcmgenet.c
481
WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
sys/dev/ic/bcmgenet.c
484
WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
sys/dev/ic/bcmgenet.c
485
WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
486
WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
sys/dev/ic/bcmgenet.c
488
WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
489
WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
sys/dev/ic/bcmgenet.c
490
WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
sys/dev/ic/bcmgenet.c
491
WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
496
WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
sys/dev/ic/bcmgenet.c
502
WR4(sc, GENET_TX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
508
WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08);
sys/dev/ic/bcmgenet.c
510
WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
sys/dev/ic/bcmgenet.c
511
WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
512
WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);
sys/dev/ic/bcmgenet.c
513
WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);
sys/dev/ic/bcmgenet.c
514
WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
sys/dev/ic/bcmgenet.c
517
WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
sys/dev/ic/bcmgenet.c
518
WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
519
WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
sys/dev/ic/bcmgenet.c
521
WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
522
WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
sys/dev/ic/bcmgenet.c
525
WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
sys/dev/ic/bcmgenet.c
526
WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
sys/dev/ic/bcmgenet.c
534
WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
sys/dev/ic/bcmgenet.c
540
WR4(sc, GENET_RX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
561
WR4(sc, GENET_SYS_PORT_CTRL,
sys/dev/ic/bcmgenet.c
564
WR4(sc, GENET_SYS_PORT_CTRL, 0);
sys/dev/ic/bcmgenet.c
569
WR4(sc, GENET_UMAC_MAC0, val);
sys/dev/ic/bcmgenet.c
571
WR4(sc, GENET_UMAC_MAC1, val);
sys/dev/ic/bcmgenet.c
584
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
657
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
662
WR4(sc, GENET_RX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
667
WR4(sc, GENET_TX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
670
WR4(sc, GENET_UMAC_TX_FLUSH, 1);
sys/dev/ic/bcmgenet.c
672
WR4(sc, GENET_UMAC_TX_FLUSH, 0);
sys/dev/ic/bcmgenet.c
677
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
786
WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
sys/dev/ic/bcmgenet.c
864
WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
sys/dev/ic/bcmgenet.c
885
WR4(sc, GENET_INTRL2_CPU_CLEAR, val);
sys/dev/ic/bcmgenet.c
98
WR4(sc, GENET_MDIO_CMD,
sys/dev/ic/cdnsiic.c
129
WR4(sc, CR_REG,
sys/dev/ic/cdnsiic.c
136
WR4(sc, TIME_OUT_REG, 0xff);
sys/dev/ic/cdnsiic.c
195
WR4(sc, CR_REG, val);
sys/dev/ic/cdnsiic.c
196
WR4(sc, ISR_REG, RD4(sc, ISR_REG));
sys/dev/ic/cdnsiic.c
202
WR4(sc, DATA_REG, *data);
sys/dev/ic/cdnsiic.c
205
WR4(sc, ADDR_REG, addr);
sys/dev/ic/cdnsiic.c
231
WR4(sc, CR_REG, val);
sys/dev/ic/cdnsiic.c
232
WR4(sc, ISR_REG, RD4(sc, ISR_REG));
sys/dev/ic/cdnsiic.c
233
WR4(sc, TRANS_SIZE_REG, datalen);
sys/dev/ic/cdnsiic.c
234
WR4(sc, ADDR_REG, addr);
sys/dev/ic/cdnsiic.c
258
WR4(sc, CR_REG, val | CR_HOLD);
sys/dev/ic/cdnsiic.c
274
WR4(sc, CR_REG, val & ~CR_HOLD);
sys/dev/ic/dwc_eqos.c
1085
WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,
sys/dev/ic/dwc_eqos.c
1242
WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR,
sys/dev/ic/dwc_eqos.c
1270
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable);
sys/dev/ic/dwc_eqos.c
1291
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable);
sys/dev/ic/dwc_eqos.c
1326
WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, new_status);
sys/dev/ic/dwc_eqos.c
1364
WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status);
sys/dev/ic/dwc_eqos.c
1369
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable);
sys/dev/ic/dwc_eqos.c
1377
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable);
sys/dev/ic/dwc_eqos.c
152
WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);
sys/dev/ic/dwc_eqos.c
1578
WR4(sc, GMAC_DMA_SYSBUS_MODE, val);
sys/dev/ic/dwc_eqos.c
178
WR4(sc, GMAC_MAC_MDIO_DATA, val);
sys/dev/ic/dwc_eqos.c
184
WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);
sys/dev/ic/dwc_eqos.c
237
WR4(sc, GMAC_MAC_CONFIGURATION, conf);
sys/dev/ic/dwc_eqos.c
245
WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, flow);
sys/dev/ic/dwc_eqos.c
252
WR4(sc, GMAC_MAC_RX_FLOW_CTRL, flow);
sys/dev/ic/dwc_eqos.c
509
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE,
sys/dev/ic/dwc_eqos.c
521
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0);
sys/dev/ic/dwc_eqos.c
633
WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val);
sys/dev/ic/dwc_eqos.c
636
WR4(sc, GMAC_MAC_ADDRESS0_LOW, val);
sys/dev/ic/dwc_eqos.c
640
WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]);
sys/dev/ic/dwc_eqos.c
641
WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]);
sys/dev/ic/dwc_eqos.c
646
WR4(sc, GMAC_MAC_PACKET_FILTER, pfil);
sys/dev/ic/dwc_eqos.c
666
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/ic/dwc_eqos.c
675
WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR);
sys/dev/ic/dwc_eqos.c
698
WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI,
sys/dev/ic/dwc_eqos.c
700
WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR,
sys/dev/ic/dwc_eqos.c
702
WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1);
sys/dev/ic/dwc_eqos.c
707
WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI,
sys/dev/ic/dwc_eqos.c
709
WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR,
sys/dev/ic/dwc_eqos.c
711
WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1);
sys/dev/ic/dwc_eqos.c
712
WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,
sys/dev/ic/dwc_eqos.c
746
WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->sc_csr_clock / 1000000) - 1);
sys/dev/ic/dwc_eqos.c
749
WR4(sc, GMAC_DMA_CHAN0_RX_WATCHDOG,
sys/dev/ic/dwc_eqos.c
757
WR4(sc, GMAC_DMA_CHAN0_CONTROL, val);
sys/dev/ic/dwc_eqos.c
763
WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
sys/dev/ic/dwc_eqos.c
770
WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
sys/dev/ic/dwc_eqos.c
773
WR4(sc, GMAC_MMC_CONTROL,
sys/dev/ic/dwc_eqos.c
779
WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE,
sys/dev/ic/dwc_eqos.c
782
WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE,
sys/dev/ic/dwc_eqos.c
796
WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);
sys/dev/ic/dwc_eqos.c
803
WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, val);
sys/dev/ic/dwc_eqos.c
809
WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, 0);
sys/dev/ic/dwc_eqos.c
810
WR4(sc, GMAC_MAC_RX_FLOW_CTRL, 0);
sys/dev/ic/dwc_eqos.c
814
WR4(sc, GMAC_RXQ_CTRL0, val);
sys/dev/ic/dwc_eqos.c
824
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/ic/dwc_eqos.c
876
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/ic/dwc_eqos.c
881
WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
sys/dev/ic/dwc_eqos.c
886
WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
sys/dev/ic/dwc_eqos.c
892
WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);
sys/dev/ic/dwc_eqos.c
910
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/ic/dwc_wdt.c
116
WR4(sc, WDT_CRR, crr);
sys/dev/ic/dwc_wdt.c
142
WR4(sc, WDT_TORR, torr);
sys/dev/ic/dwc_wdt.c
147
WR4(sc, WDT_CR, cr);