sys/arch/arm/amlogic/meson_i2c.c

163

uint32_t data = RD4(sc, reg);

sys/arch/arm/amlogic/meson_i2c.c

235

return (RD4(sc, reg) >> pos) & MESONI2C_DATA_MASK;

sys/arch/arm/amlogic/meson_i2c.c

324

if (RD4(sc, MESONI2C_CTRL_REG) & MESONI2C_CTRL_ERROR) {

sys/arch/arm/amlogic/meson_i2c.c

336

u_int count = (RD4(sc, MESONI2C_CTRL_REG) & MESONI2C_CTRL_READ_DATA_MASK)

sys/arch/arm/nvidia/tegra210_xusbpad.c

282

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

295

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

309

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

325

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

338

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

480

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

493

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

507

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

523

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

536

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG);

sys/arch/arm/rockchip/rk3288_iomux.c

184

val = RD4(reg, reg->pull_reg);

sys/arch/arm/rockchip/rk3288_iomux.c

218

val = RD4(reg, reg->drv_reg);

sys/arch/arm/rockchip/rk3288_iomux.c

237

val = RD4(reg, reg->mux_reg);

sys/arch/arm/rockchip/rk3399_iomux.c

248

printf("%s: bank %d idx %d flags %#x: %08x -> ", __func__, bank, idx, flags, RD4(syscon, reg));

sys/arch/arm/rockchip/rk3399_iomux.c

252

printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);

sys/arch/arm/rockchip/rk3399_iomux.c

340

printf("%s: bank %d idx %d val %d: %08x -> ", __func__, bank, idx, val, RD4(syscon, reg));

sys/arch/arm/rockchip/rk3399_iomux.c

344

printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);

sys/arch/arm/rockchip/rk3399_iomux.c

374

printf("%s: bank %d idx %d mux %#x: %08x -> ", __func__, bank, idx, mux, RD4(syscon, reg));

sys/arch/arm/rockchip/rk3399_iomux.c

378

printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);

sys/arch/arm/rockchip/rk3399_iomux.c

471

val = RD4(syscon, GRF_GPIO4B_IOMUX);

sys/arch/arm/rockchip/rk3399_iomux.c

476

val = RD4(syscon, GRF_SOC_CON7);

sys/arch/arm/rockchip/rk_emmcphy.c

188

val = RD4(sc, GRF_EMMCPHY_STATUS);

sys/arch/arm/rockchip/rk_emmcphy.c

208

val = RD4(sc, GRF_EMMCPHY_STATUS);

sys/arch/arm/rockchip/rk_gpio.c

212

data = RD4(sc, GPIO_EXT_PORTA_REG);

sys/arch/arm/rockchip/rk_gpio.c

229

data = RD4(sc, GPIO_SWPORTA_DR_REG);

sys/arch/arm/rockchip/rk_gpio.c

247

ddr = RD4(sc, GPIO_SWPORTA_DDR_REG);

sys/arch/arm/rockchip/rk_gpio.c

268

data = RD4(sc, GPIOV2_EXT_PORT_REG);

sys/arch/arm/rockchip/rk_gpio.c

310

status = RD4(sc, GPIO_INT_STATUS_REG);

sys/arch/arm/rockchip/rk_gpio.c

351

val = RD4(sc, GPIO_INTTYPE_LEVEL_REG);

sys/arch/arm/rockchip/rk_gpio.c

358

val = RD4(sc, GPIO_INT_POLARITY_REG);

sys/arch/arm/rockchip/rk_gpio.c

365

val = RD4(sc, GPIO_INTEN_REG);

sys/arch/arm/rockchip/rk_gpio.c

398

val = RD4(sc, GPIO_INTEN_REG);

sys/arch/arm/rockchip/rk_gpio.c

560

val = RD4(sc, GPIO_INTMASK_REG);

sys/arch/arm/rockchip/rk_gpio.c

572

val = RD4(sc, GPIO_INTMASK_REG);

sys/arch/arm/rockchip/rk_gpio.c

636

ver_id = RD4(sc, GPIO_VER_ID_REG);

sys/arch/arm/rockchip/rk_i2c.c

163

WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD));

sys/arch/arm/rockchip/rk_i2c.c

174

val = RD4(sc, RKI2C_IPD);

sys/arch/arm/rockchip/rk_i2c.c

197

con = RD4(sc, RKI2C_CON);

sys/arch/arm/rockchip/rk_i2c.c

217

con = RD4(sc, RKI2C_CON);

sys/arch/arm/rockchip/rk_i2c.c

320

rxdata[n/4] = RD4(sc, RKI2C_RXDATA(n/4));

sys/arch/arm/rockchip/rk_i2c.c

363

WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD));

sys/arch/arm/rockchip/rk_i2s.c

185

ckr = RD4(sc, I2S_CKR);

sys/arch/arm/rockchip/rk_i2s.c

207

txcr = RD4(sc, I2S_TXCR);

sys/arch/arm/rockchip/rk_i2s.c

218

rxcr = RD4(sc, I2S_RXCR);

sys/arch/arm/rockchip/rk_i2s.c

258

val = RD4(sc, I2S_XFER);

sys/arch/arm/rockchip/rk_i2s.c

265

val = RD4(sc, I2S_INTCR);

sys/arch/arm/rockchip/rk_i2s.c

297

val = RD4(sc, I2S_XFER);

sys/arch/arm/rockchip/rk_i2s.c

302

val = RD4(sc, I2S_INTCR);

sys/arch/arm/rockchip/rk_i2s.c

306

val = RD4(sc, I2S_CLR);

sys/arch/arm/rockchip/rk_i2s.c

310

while ((RD4(sc, I2S_CLR) & CLR_TXC) != 0)

sys/arch/arm/rockchip/rk_i2s.c

328

val = RD4(sc, I2S_XFER);

sys/arch/arm/rockchip/rk_i2s.c

333

val = RD4(sc, I2S_INTCR);

sys/arch/arm/rockchip/rk_i2s.c

378

sr = RD4(sc, I2S_INTSR);

sys/arch/arm/rockchip/rk_i2s.c

382

val = RD4(sc, I2S_RXFIFOLR);

sys/arch/arm/rockchip/rk_i2s.c

385

*rch->ch_data = RD4(sc, I2S_RXDR);

sys/arch/arm/rockchip/rk_i2s.c

396

val = RD4(sc, I2S_TXFIFOLR);

sys/arch/arm/rockchip/rk_i2s.c

444

txcr = RD4(sc, I2S_TXCR);

sys/arch/arm/rockchip/rk_i2s.c

445

rxcr = RD4(sc, I2S_RXCR);

sys/arch/arm/rockchip/rk_i2s.c

446

ckr = RD4(sc, I2S_CKR);

sys/arch/arm/rockchip/rk_vop.c

245

val = RD4(sc, VOP_DSP_CTRL1);

sys/arch/arm/rockchip/rk_vop.c

256

val = RD4(sc, VOP_SYS_CTRL);

sys/arch/arm/rockchip/rk_vop.c

424

val = RD4(sc, VOP_SYS_CTRL);

sys/arch/arm/rockchip/rk_vop.c

507

val = RD4(sc, VOP_SYS_CTRL);

sys/arch/arm/rockchip/rk_vop.c

521

val = RD4(sc, VOP_DSP_CTRL0);

sys/arch/arm/rockchip/rk_vop.c

562

val = RD4(sc, VOP_SYS_CTRL);

sys/arch/arm/rockchip/rk_vop.c

716

intr = RD4(sc, VOP_INTR_STATUS0);

sys/arch/arm/samsung/exynos_uart.c

310

ufstat = RD4(sc, SSCOM_UFSTAT);

sys/arch/arm/samsung/exynos_uart.c

316

c = RD4(sc, SSCOM_URXH);

sys/arch/arm/samsung/exynos_uart.c

334

while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0)

sys/arch/arm/samsung/exynos_uart.c

403

ucon = RD4(sc, SSCOM_UCON);

sys/arch/arm/samsung/exynos_uart.c

433

ucon = RD4(sc, SSCOM_UCON);

sys/arch/arm/samsung/exynos_uart.c

521

while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0)

sys/arch/arm/samsung/exynos_uart.c

598

ack = RD4(sc, SSCOM_UTRSTAT);

sys/arch/arm/samsung/exynos_uart.c

600

ack = RD4(sc, SSCOM_UINTP);

sys/arch/arm/samsung/exynos_uart.c

606

uerstat = RD4(sc, SSCOM_UERSTAT);

sys/arch/arm/samsung/exynos_uart.c

614

ufstat = RD4(sc, SSCOM_UFSTAT);

sys/arch/arm/samsung/exynos_uart.c

619

c = RD4(sc, SSCOM_URXH);

sys/arch/arm/sunxi/sun4i_a10_codec.c

113

WR4((sc), (reg), RD4((sc), (reg)) | (mask))

sys/arch/arm/sunxi/sun4i_a10_codec.c

115

WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))

sys/arch/arm/sunxi/sun4i_a10_codec.c

160

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun4i_a10_codec.c

183

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

164

val = RD4(sc, A64_PR_CFG);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

180

return __SHIFTOUT(RD4(sc, A64_PR_CFG), A64_ACDA_PR_RDAT);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

189

val = RD4(sc, A64_PR_CFG);

sys/arch/arm/sunxi/sun6i_a31_codec.c

156

WR4((sc), (reg), RD4((sc), (reg)) | (mask))

sys/arch/arm/sunxi/sun6i_a31_codec.c

158

WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))

sys/arch/arm/sunxi/sun6i_a31_codec.c

221

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun6i_a31_codec.c

244

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

174

const uint32_t val = RD4(sc, 0);

sys/arch/arm/sunxi/sun8i_codec.c

218

val = RD4(sc, AIF1CLK_CTRL);

sys/arch/arm/sunxi/sun8i_codec.c

290

val = RD4(sc, HMIC_CTRL1);

sys/arch/arm/sunxi/sun8i_codec.c

308

val = RD4(sc, HMIC_STS);

sys/arch/arm/sunxi/sun8i_codec.c

328

val = RD4(sc, HMIC_STS);

sys/arch/arm/sunxi/sun8i_codec.c

421

val = RD4(sc, SYSCLK_CTL);

sys/arch/arm/sunxi/sun8i_codec.c

436

val = RD4(sc, SYS_SR_CTRL);

sys/arch/arm/sunxi/sun8i_codec.c

442

val = RD4(sc, AIF1CLK_CTRL);

sys/arch/arm/sunxi/sun8i_codec.c

448

val = RD4(sc, AIF1_DACDAT_CTRL);

sys/arch/arm/sunxi/sun8i_codec.c

454

val = RD4(sc, DAC_MXR_SRC);

sys/arch/arm/sunxi/sun8i_codec.c

467

val = RD4(sc, HMIC_CTRL1);

sys/arch/arm/sunxi/sun8i_codec.c

471

val = RD4(sc, HMIC_CTRL2);

sys/arch/arm/sunxi/sun8i_h3_codec.c

153

val = RD4(csc, H3_PR_CFG);

sys/arch/arm/sunxi/sun8i_h3_codec.c

169

return __SHIFTOUT(RD4(csc, H3_PR_CFG), H3_ACDA_PR_RDAT);

sys/arch/arm/sunxi/sun8i_h3_codec.c

178

val = RD4(csc, H3_PR_CFG);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

140

val = RD4(csc, V3S_PR_CFG);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

156

return __SHIFTOUT(RD4(csc, V3S_PR_CFG), V3S_ADDA_PR_RDAT);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

165

val = RD4(csc, V3S_PR_CFG);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

176

const uint32_t val = RD4(sc, 0);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

193

const uint32_t val = RD4(sc, 0);

sys/arch/arm/sunxi/sunxi_emac.c

1131

machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;

sys/arch/arm/sunxi/sunxi_emac.c

1132

maclo = RD4(sc, EMAC_ADDR_LOW(0));

sys/arch/arm/sunxi/sunxi_emac.c

217

if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {

sys/arch/arm/sunxi/sunxi_emac.c

218

*val = RD4(sc, EMAC_MII_DATA) & 0xffff;

sys/arch/arm/sunxi/sunxi_emac.c

246

if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)

sys/arch/arm/sunxi/sunxi_emac.c

266

val = RD4(sc, EMAC_BASIC_CTL_0);

sys/arch/arm/sunxi/sunxi_emac.c

282

val = RD4(sc, EMAC_RX_CTL_0);

sys/arch/arm/sunxi/sunxi_emac.c

288

val = RD4(sc, EMAC_TX_FLOW_CTL);

sys/arch/arm/sunxi/sunxi_emac.c

487

val = RD4(sc, EMAC_TX_CTL_1);

sys/arch/arm/sunxi/sunxi_emac.c

636

RD4(sc, regs[n].reg));

sys/arch/arm/sunxi/sunxi_emac.c

650

if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)

sys/arch/arm/sunxi/sunxi_emac.c

696

val = RD4(sc, EMAC_TX_CTL_1);

sys/arch/arm/sunxi/sunxi_emac.c

700

val = RD4(sc, EMAC_RX_CTL_1);

sys/arch/arm/sunxi/sunxi_emac.c

704

val = RD4(sc, EMAC_TX_CTL_0);

sys/arch/arm/sunxi/sunxi_emac.c

708

val = RD4(sc, EMAC_RX_CTL_0);

sys/arch/arm/sunxi/sunxi_emac.c

745

val = RD4(sc, EMAC_TX_CTL_1);

sys/arch/arm/sunxi/sunxi_emac.c

751

val = RD4(sc, EMAC_TX_CTL_0);

sys/arch/arm/sunxi/sunxi_emac.c

755

val = RD4(sc, EMAC_RX_CTL_0);

sys/arch/arm/sunxi/sunxi_emac.c

762

val = RD4(sc, EMAC_TX_CTL_1);

sys/arch/arm/sunxi/sunxi_emac.c

766

val = RD4(sc, EMAC_RX_CTL_1);

sys/arch/arm/sunxi/sunxi_emac.c

900

val = RD4(sc, EMAC_INT_STA);

sys/arch/arm/sunxi/sunxi_gmacclk.c

179

val = RD4(sc, 0);

sys/arch/arm/sunxi/sunxi_gmacclk.c

212

val = RD4(sc, 0);

sys/arch/arm/sunxi/sunxi_thermal.c

374

WR4(sc, THS_INTS, RD4(sc, THS_INTS));

sys/arch/arm/sunxi/sunxi_thermal.c

378

WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);

sys/arch/arm/sunxi/sunxi_thermal.c

388

val = RD4(sc, THS_DATA0 + (sensor * 4));

sys/arch/arm/sunxi/sunxi_thermal.c

398

val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));

sys/arch/arm/sunxi/sunxi_thermal.c

409

val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));

sys/arch/arm/sunxi/sunxi_thermal.c

420

val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));

sys/arch/arm/sunxi/sunxi_thermal.c

431

val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));

sys/arch/arm/sunxi/sunxi_thermal.c

442

val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));

sys/arch/arm/sunxi/sunxi_thermal.c

489

ints = RD4(sc, THS_INTS);

sys/arch/arm/ti/ti_div_clock.c

197

val = RD4(sc);

sys/arch/arm/ti/ti_dpll_clock.c

258

val = RD4(sc, REG_MULT_DIV1);

sys/arch/arm/ti/ti_dpll_clock.c

296

control = RD4(sc, REG_CONTROL);

sys/arch/arm/ti/ti_dpll_clock.c

301

while (RD4(sc, REG_IDLEST) != AM3_ST_MN_BYPASS)

sys/arch/arm/ti/ti_dpll_clock.c

312

while (RD4(sc, REG_IDLEST) != AM3_ST_DPLL_CLK)

sys/arch/arm/ti/ti_dpll_clock.c

336

control = RD4(sc, REG_CONTROL);

sys/arch/arm/ti/ti_dpll_clock.c

351

while ((RD4(sc, REG_IDLEST) & OMAP3_ST_MPU_CLK) != 0)

sys/arch/arm/ti/ti_dpll_clock.c

368

val = RD4(sc, REG_MULT_DIV1);

sys/arch/arm/ti/ti_dpll_clock.c

389

val = RD4(sc, REG_MULT_DIV1);

sys/arch/arm/ti/ti_gate_clock.c

172

val = RD4(sc, 0);

sys/arch/arm/ti/ti_gate_clock.c

186

val = RD4(sc, 0);

sys/arch/arm/ti/ti_gpio.c

157

oe = RD4(sc, GPIO_OE);

sys/arch/arm/ti/ti_gpio.c

229

data = RD4(sc, GPIO_DATAOUT);

sys/arch/arm/ti/ti_gpio.c

231

data = RD4(sc, GPIO_DATAIN);

sys/arch/arm/ti/ti_gpio.c

273

val = RD4(sc, GPIO_IRQENABLE1);

sys/arch/arm/ti/ti_gpio.c

322

val = RD4(sc, GPIO_LEVELDETECT0);

sys/arch/arm/ti/ti_gpio.c

329

val = RD4(sc, GPIO_LEVELDETECT1);

sys/arch/arm/ti/ti_gpio.c

336

val = RD4(sc, GPIO_RISINGDETECT);

sys/arch/arm/ti/ti_gpio.c

343

val = RD4(sc, GPIO_FALLINGDETECT);

sys/arch/arm/ti/ti_gpio.c

352

val = RD4(sc, GPIO_IRQENABLE1);

sys/arch/arm/ti/ti_gpio.c

403

data = RD4(sc, GPIO_DATAIN);

sys/arch/arm/ti/ti_gpio.c

470

val = RD4(sc, GPIO_LEVELDETECT0);

sys/arch/arm/ti/ti_gpio.c

477

val = RD4(sc, GPIO_LEVELDETECT1);

sys/arch/arm/ti/ti_gpio.c

484

val = RD4(sc, GPIO_RISINGDETECT);

sys/arch/arm/ti/ti_gpio.c

492

val = RD4(sc, GPIO_FALLINGDETECT);

sys/arch/arm/ti/ti_gpio.c

502

val = RD4(sc, GPIO_IRQENABLE1);

sys/arch/arm/ti/ti_gpio.c

574

status = RD4(sc, GPIO_IRQSTATUS1);

sys/arch/arm/ti/ti_lcdc.c

274

val = RD4(sc, LCD_RASTER_CTRL);

sys/arch/arm/ti/ti_mux_clock.c

190

val = RD4(sc, 0);

sys/arch/arm/ti/ti_mux_clock.c

210

val = RD4(sc, 0);

sys/arch/arm/ti/ti_omapmusb.c

134

val = RD4(sc, OTG_SYSSTATUS);

sys/arch/arm/ti/ti_omaptimer.c

160

return RD4(sc, TIMER_TCRR);

sys/arch/arm/ti/ti_rng.c

103

if ((RD4(sc, TRNG_CONTROL_REG) & TRNG_CONTROL_ENABLE) == 0) {

sys/arch/arm/ti/ti_rng.c

129

if (RD4(sc, TRNG_STATUS_REG) & TRNG_STATUS_READY)

sys/arch/arm/ti/ti_rng.c

135

buf[0] = RD4(sc, TRNG_OUTPUT_L_REG);

sys/arch/arm/ti/ti_rng.c

136

buf[1] = RD4(sc, TRNG_OUTPUT_H_REG);

sys/arch/arm/ti/ti_usb.c

183

val = RD4(sc, UHH_SYSCONFIG);

sys/arch/arm/ti/ti_usb.c

203

val = RD4(sc, UHH_HOSTCONFIG);

sys/arch/arm/ti/ti_usb.c

278

sc->sc_usbhsrev = RD4(sc, UHH_REVISION);

sys/arch/arm/ti/ti_usbtll.c

117

val = RD4(sc, USBTLL_CHANNEL_CONF(port));

sys/arch/arm/ti/ti_usbtll.c

133

val = RD4(sc, USBTLL_SYSSTATUS);

sys/arch/arm/ti/ti_usbtll.c

155

val = RD4(sc, USBTLL_SHARED_CONF);

sys/arch/arm/ti/ti_wdt.c

100

val = RD4(sc, WDT_WWPS);

sys/arch/arm/ti/ti_wdt.c

121

val = RD4(sc, WDT_WDSC);

sys/arch/arm/ti/ti_wdt.c

125

val = RD4(sc, WDT_WDSC);

sys/arch/arm/ti/ti_wdt.c

194

val = RD4(sc, WDT_WTGR);

sys/arch/arm/xilinx/zynq_gpio.c

100

oen = RD4(sc, OEN_REG(pin));

sys/arch/arm/xilinx/zynq_gpio.c

206

data = RD4(sc, DATA_RO_REG(pin));

sys/arch/arm/xilinx/zynq_gpio.c

99

dirm = RD4(sc, DIRM_REG(pin));

sys/arch/arm/xilinx/zynq_xadc.c

174

if ((RD4(sc, XADCIF_MSTS) & MSTS_CFIFOE) != 0) {

sys/arch/arm/xilinx/zynq_xadc.c

186

RD4(sc, XADCIF_RDFIFO);

sys/arch/arm/xilinx/zynq_xadc.c

210

if ((RD4(sc, XADCIF_MSTS) & MSTS_CFIFOE) != 0) {

sys/arch/arm/xilinx/zynq_xadc.c

219

val = RD4(sc, XADCIF_RDFIFO);

sys/arch/arm/xilinx/zynq_xadc.c

220

val = RD4(sc, XADCIF_RDFIFO);

sys/arch/arm/xilinx/zynq_xadc.c

231

val = RD4(sc, XADCIF_CFG);

sys/arch/arm/xscale/ixp425_if_npe.c

1103

RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);

sys/arch/arm/xscale/ixp425_if_npe.c

1105

RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);

sys/arch/arm/xscale/ixp425_if_npe.c

1178

RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);

sys/arch/arm/xscale/ixp425_if_npe.c

1180

RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);

sys/arch/arm/xscale/ixp425_if_npe.c

1355

RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);

sys/arch/arm/xscale/ixp425_if_npe.c

1357

RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);

sys/arch/arm/xscale/ixp425_if_npe.c

1644

tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);

sys/arch/arm/xscale/ixp425_if_npe.c

1645

rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);

sys/arch/arm/xscale/ixp425_if_npe.c

1653

randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec)

sys/arch/arm/xscale/ixp425_if_npe.c

351

reg = RD4(sc, NPE_MAC_RX_CNTRL1);

sys/arch/arm/xscale/ixp425_if_npe.c

407

| ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16)

sys/arch/arm/xscale/ixp425_if_npe.c

762

eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;

sys/arch/arm/xscale/ixp425_if_npe.c

763

eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;

sys/arch/arm/xscale/ixp425_if_npe.c

764

eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;

sys/arch/arm/xscale/ixp425_if_npe.c

765

eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;

sys/arch/arm/xscale/ixp425_if_npe.c

766

eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;

sys/arch/arm/xscale/ixp425_if_npe.c

767

eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;

sys/arch/evbppc/nintendo/dev/ahb.c

117

val = RD4(LT_CHIPREVID);

sys/arch/evbppc/nintendo/dev/ahb.c

122

val = RD4(HW_VERSION);

sys/arch/evbppc/nintendo/dev/ahb.c

195

raw = RD4(HW_PPCIRQFLAGS);

sys/arch/evbppc/nintendo/dev/ahb.c

217

val = RD4(HW_ARMIRQMASK);

sys/arch/evbppc/nintendo/dev/ahb.c

247

raw = RD4(LT_PPCnINT1STS(0));

sys/arch/evbppc/nintendo/dev/ahb.c

250

raw = RD4(LT_PPCnINT2STS(0));

sys/arch/evbppc/nintendo/dev/ahb.c

279

val = RD4(reg_en);

sys/arch/evbppc/nintendo/dev/ahb.c

337

WR4(HW_AHBPROT, RD4(HW_AHBPROT) & ~mask);

sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c

64

val = RD4(sc, SATA_HCCFG_INT_REG);

sys/arch/evbppc/nintendo/dev/bwai.c

219

val = RD4(sc, AI_CONTROL);

sys/arch/evbppc/nintendo/dev/bwai.c

95

val = RD4(sc, AI_CONTROL);

sys/arch/evbppc/nintendo/dev/di.c

268

while (((RD4(sc, DISR) & DISR_TCINT)) == 0) {

sys/arch/evbppc/nintendo/dev/di.c

271

imm = RD4(sc, DIMMBUF);

sys/arch/evbppc/nintendo/dev/di.c

343

imm = RD4(sc, DIMMBUF);

sys/arch/evbppc/nintendo/dev/di.c

396

sr = RD4(sc, DISR);

sys/arch/evbppc/nintendo/dev/di.c

397

cvr = RD4(sc, DICVR);

sys/arch/evbppc/nintendo/dev/di.c

428

xs->cmd->opcode, RD4(sc, DISR));

sys/arch/evbppc/nintendo/dev/di.c

442

if ((RD4(sc, DICVR) & DICVR_CVR) != 0) {

sys/arch/evbppc/nintendo/dev/exi.c

209

val = RD4(exi_softc, EXI_CSR(chan));

sys/arch/evbppc/nintendo/dev/exi.c

227

val = RD4(exi_softc, EXI_CSR(chan));

sys/arch/evbppc/nintendo/dev/exi.c

242

val = RD4(exi_softc, EXI_CR(chan));

sys/arch/evbppc/nintendo/dev/exi.c

295

val = RD4(exi_softc, EXI_DATA(chan));

sys/arch/evbppc/nintendo/dev/exi.c

341

val = RD4(exi_softc, EXI_DATA(chan));

sys/arch/evbppc/nintendo/dev/gecko.c

104

if ((RD4(EXI_CR(usbgecko_chan)) & EXI_CR_TSTART) == 0) {

sys/arch/evbppc/nintendo/dev/gecko.c

127

value = RD4(EXI_DATA(usbgecko_chan)) >> 16;

sys/arch/evbppc/nintendo/dev/gecko.c

148

value = RD4(EXI_DATA(usbgecko_chan));

sys/arch/evbppc/nintendo/dev/hwaes.c

160

if (RD4(sc, AES_CTRL) == 0) {

sys/arch/evbppc/nintendo/dev/hwaes.c

267

ctrl = RD4(sc, AES_CTRL);

sys/arch/evbppc/nintendo/dev/hwgpio.c

141

return (RD4(sc, GPIOB_IN) & __BIT(pin)) != 0;

sys/arch/evbppc/nintendo/dev/hwgpio.c

151

out = RD4(sc, GPIOB_OUT);

sys/arch/evbppc/nintendo/dev/hwgpio.c

168

dir = RD4(sc, GPIOB_DIR);

sys/arch/evbppc/nintendo/dev/hwgpio.c

235

in = RD4(sc, GPIOB_IN);

sys/arch/evbppc/nintendo/dev/hwgpio.c

236

out = RD4(sc, GPIOB_OUT);

sys/arch/evbppc/nintendo/dev/hwgpio.c

237

dir = RD4(sc, GPIOB_DIR);

sys/arch/evbppc/nintendo/dev/si.c

265

inbuf[0] = RD4(sc, SICINBUFH(chan));

sys/arch/evbppc/nintendo/dev/si.c

266

inbuf[1] = RD4(sc, SICINBUFL(chan));

sys/arch/evbppc/nintendo/dev/si.c

314

comcsr = RD4(sc, SICOMCSR);

sys/arch/evbppc/nintendo/dev/si.c

315

sr = RD4(sc, SISR);

sys/arch/evbppc/nintendo/dev/si.c

368

(void)RD4(sc, SICINBUFH(ch->ch_index));

sys/arch/evbppc/nintendo/dev/si.c

369

(void)RD4(sc, SICINBUFL(ch->ch_index));

sys/arch/evbppc/nintendo/dev/si.c

375

WR4(sc, SIPOLL, RD4(sc, SIPOLL) | SIPOLL_EN(ch->ch_index));

sys/arch/evbppc/nintendo/dev/si.c

378

WR4(sc, SICOMCSR, RD4(sc, SICOMCSR) | SICOMCSR_TSTART);

sys/arch/evbppc/nintendo/dev/si.c

410

WR4(sc, SIPOLL, RD4(sc, SIPOLL) & ~SIPOLL_EN(ch->ch_index));

sys/arch/evbppc/nintendo/dev/wiifb.c

676

di0 = RD4(sc, VI_DI0);

sys/arch/evbppc/nintendo/dev/wiifb.c

678

WR4(sc, VI_DI0, RD4(sc, VI_DI0) & ~VI_DI_INT);

sys/arch/evbppc/nintendo/dev/wiifb.c

679

WR4(sc, VI_DI1, RD4(sc, VI_DI1) & ~VI_DI_INT);

sys/arch/evbppc/nintendo/dev/wiifb.c

680

WR4(sc, VI_DI2, RD4(sc, VI_DI2) & ~VI_DI_INT);

sys/arch/evbppc/nintendo/dev/wiifb.c

681

WR4(sc, VI_DI3, RD4(sc, VI_DI3) & ~VI_DI_INT);

sys/arch/evbppc/nintendo/pic_pi.c

133

raw = RD4(pic_s[cpu_num].intsr);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

386

(void)RD4(sc, PSC_AC97DATA);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

391

*valp = AC97DATA_VALUE(RD4(sc, PSC_AC97DATA));

sys/arch/riscv/sifive/fu540_ccache.c

203

uint32_t l2config = RD4(sc, CCACHE_CONFIG);

sys/arch/riscv/sifive/fu540_ccache.c

216

uint32_t l2wayenable = RD4(sc, CCACHE_WAYENABLE);

sys/arch/riscv/sifive/fu540_prci.c

120

val = RD4(sc, reg);

sys/arch/riscv/sifive/fu540_prci.c

164

val = RD4(sc, DDRPLLCFG1);

sys/arch/riscv/sifive/fu540_prci.c

168

val = RD4(sc, GEMGXLPLLCFG1);

sys/arch/riscv/starfive/jh7110_clkc.c

1010

const uint32_t val = RD4(sc, assert_reg);

sys/arch/riscv/starfive/jh7110_clkc.c

1019

status = RD4(sc, status_reg);

sys/arch/riscv/starfive/jh7110_pcie.c

285

KASSERT((RD4(sc, PLDA_IMASK_LOCAL) & (PLDA_IMASK_INT_INTA << pin)) == 0);

sys/arch/riscv/starfive/jh7110_pcie.c

364

uint32_t status = RD4(sc, PLDA_ISTATUS_LOCAL);

sys/arch/riscv/starfive/jh7110_pcie.c

555

val = RD4(sc, PLDA_ATR0_PCIE_WIN0_SRCADDR_PARAM);

sys/arch/riscv/starfive/jh7110_pcie.c

85

WR4((sc), (off), RD4((sc), (off)) | (mask))

sys/arch/riscv/starfive/jh7110_pcie.c

87

WR4((sc), (off), RD4((sc), (off)) & ~(mask))

sys/arch/riscv/starfive/jh7110_pcie.c

89

WR4((sc), (off), (RD4((sc), (off)) & ~(clr)) | (set))

sys/arch/riscv/starfive/jh7110_pinctrl.c

317

funcold = RD4(sc, jfs->jfs_funcreg);

sys/arch/riscv/starfive/jh7110_pinctrl.c

343

doutold = RD4(sc, dout_reg);

sys/arch/riscv/starfive/jh7110_pinctrl.c

347

doenold = RD4(sc, doen_reg);

sys/arch/riscv/starfive/jh7110_pinctrl.c

359

dinold = RD4(sc, din_reg);

sys/arch/riscv/starfive/jh7110_pinctrl.c

561

RD4(sc, GPO_DOEN_CFG(pin_no)));

sys/arch/riscv/starfive/jh7110_pinctrl.c

647

const uint32_t bank = RD4(sc, sc->sc_jpd->jpd_gpioin + offset);

sys/arch/riscv/starfive/jh7110_pinctrl.c

676

uint32_t bank = RD4(sc, sc->sc_jpd->jpd_dout + offset);

sys/arch/riscv/starfive/jh7110_syscon.c

81

return RD4(sc, reg);

sys/arch/riscv/starfive/jh7110_trng.c

173

const uint32_t stat = RD4(sc, JH7110_TRNG_STAT);

sys/arch/riscv/starfive/jh7110_trng.c

181

data[0] = RD4(sc, JH7110_TRNG_DATA0);

sys/arch/riscv/starfive/jh7110_trng.c

182

data[1] = RD4(sc, JH7110_TRNG_DATA1);

sys/arch/riscv/starfive/jh7110_trng.c

183

data[2] = RD4(sc, JH7110_TRNG_DATA2);

sys/arch/riscv/starfive/jh7110_trng.c

184

data[3] = RD4(sc, JH7110_TRNG_DATA3);

sys/arch/riscv/starfive/jh7110_trng.c

185

data[4] = RD4(sc, JH7110_TRNG_DATA4);

sys/arch/riscv/starfive/jh7110_trng.c

186

data[5] = RD4(sc, JH7110_TRNG_DATA5);

sys/arch/riscv/starfive/jh7110_trng.c

187

data[6] = RD4(sc, JH7110_TRNG_DATA6);

sys/arch/riscv/starfive/jh7110_trng.c

188

data[7] = RD4(sc, JH7110_TRNG_DATA7);

sys/arch/riscv/starfive/jh7110_trng.c

221

const uint32_t istat = RD4(sc, JH7110_TRNG_ISTATUS);

sys/arch/riscv/starfive/jh7110_trng.c

235

const uint32_t istat = RD4(sc, JH7110_TRNG_ISTATUS);

sys/arch/riscv/starfive/jh7110_trng.c

238

KASSERT(RD4(sc, JH7110_TRNG_STAT) & JH7110_TRNG_STAT_SEEDED);

sys/arch/riscv/starfive/jh7110_trng.c

377

RD4(sc, JH7110_TRNG_FEATURES));

sys/arch/riscv/starfive/jh7110_trng.c

381

RD4(sc, JH7110_TRNG_BCONF));

sys/arch/riscv/starfive/jh71x0_clkc.c

158

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

173

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

231

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

301

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

378

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

393

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

420

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_clkc.c

57

uint32_t val = RD4(sc, jcc->jcc_reg);

sys/arch/riscv/starfive/jh71x0_temp.c

72

uint32_t temp = RD4(sc, JH71X0_TEMP);

sys/dev/acpi/amdgpio.c

341

val = RD4(sc, AMDGPIO_PIN_REG(pin));

sys/dev/acpi/amdgpio.c

358

val = RD4(sc, AMDGPIO_PIN_REG(pin));

sys/dev/acpi/amdgpio.c

424

val = RD4(sc, AMDGPIO_PIN_REG(pin));

sys/dev/acpi/amdgpio.c

445

val = RD4(sc, AMDGPIO_PIN_REG(aih->ih_pin));

sys/dev/acpi/amdgpio.c

472

val = RD4(sc, AMDGPIO_PIN_REG(aih->ih_pin));

sys/dev/acpi/amdgpio.c

484

val = RD4(sc, AMDGPIO_PIN_REG(aih->ih_pin));

sys/dev/acpi/amdgpio.c

500

status = RD4(sc, AMDGPIO_INTR_STATUS(1));

sys/dev/acpi/amdgpio.c

502

status |= RD4(sc, AMDGPIO_INTR_STATUS(0));

sys/dev/acpi/amdgpio.c

517

val = RD4(sc, AMDGPIO_PIN_REG(pin));

sys/dev/acpi/amdgpio.c

528

val = RD4(sc, AMDGPIO_INTR_MASTER);

sys/dev/acpi/qcomgpio.c

488

val = RD4(sc, TLMM_GPIO_IN_OUT(pin));

sys/dev/acpi/qcomgpio.c

505

val = RD4(sc, TLMM_GPIO_IN_OUT(pin));

sys/dev/acpi/qcomgpio.c

579

val = RD4(sc, TLMM_GPIO_INTR_CFG(pin));

sys/dev/acpi/qcomgpio.c

612

val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));

sys/dev/acpi/qcomgpio.c

639

val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));

sys/dev/acpi/qcomgpio.c

654

val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));

sys/dev/acpi/qcomgpio.c

675

val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin));

sys/dev/fdt/dwc3_fdt.c

132

val = RD4(sc, DWC3_GUSB2PHYCFG(0));

sys/dev/fdt/dwc3_fdt.c

160

val = RD4(sc, DWC3_GUSB3PIPECTL(0));

sys/dev/fdt/dwc3_fdt.c

169

val = RD4(sc, DWC3_GUCTL1);

sys/dev/fdt/dwc3_fdt.c

179

val = RD4(sc, DWC3_DCFG);

sys/dev/fdt/dwc3_fdt.c

199

val = RD4(sc, DWC3_GCTL);

sys/dev/fdt/dwc3_fdt.c

319

const uint32_t snpsid = RD4(sc, DWC3_SNPSID);

sys/dev/fdt/dwc3_fdt.c

95

WR4((sc), (reg), RD4((sc), (reg)) | (mask))

sys/dev/fdt/dwc3_fdt.c

97

WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))

sys/dev/ic/bcmgenet.c

103

if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0) {

sys/dev/ic/bcmgenet.c

104

*val = RD4(sc, GENET_MDIO_CMD) & 0xffff;

sys/dev/ic/bcmgenet.c

1057

const uint32_t rev = RD4(sc, GENET_SYS_REV_CTRL);

sys/dev/ic/bcmgenet.c

1170

printf("TX CIDX = %08x\n", RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)));

sys/dev/ic/bcmgenet.c

1172

printf("TX PIDX = %08x\n", RD4(sc, GENET_TX_DMA_PROD_INDEX(qid)));

sys/dev/ic/bcmgenet.c

1175

printf("RX CIDX = %08x\n", RD4(sc, GENET_RX_DMA_CONS_INDEX(qid)));

sys/dev/ic/bcmgenet.c

1177

printf("RX PIDX = %08x\n", RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)));

sys/dev/ic/bcmgenet.c

130

if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0)

sys/dev/ic/bcmgenet.c

159

val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);

sys/dev/ic/bcmgenet.c

169

val = RD4(sc, GENET_UMAC_CMD);

sys/dev/ic/bcmgenet.c

351

cmd = RD4(sc, GENET_UMAC_CMD);

sys/dev/ic/bcmgenet.c

395

val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);

sys/dev/ic/bcmgenet.c

419

val = RD4(sc, GENET_RBUF_CTRL);

sys/dev/ic/bcmgenet.c

448

val = RD4(sc, GENET_RX_DMA_RING_TIMEOUT(qid));

sys/dev/ic/bcmgenet.c

499

val = RD4(sc, GENET_TX_DMA_CTRL);

sys/dev/ic/bcmgenet.c

537

val = RD4(sc, GENET_RX_DMA_CTRL);

sys/dev/ic/bcmgenet.c

581

val = RD4(sc, GENET_UMAC_CMD);

sys/dev/ic/bcmgenet.c

655

val = RD4(sc, GENET_UMAC_CMD);

sys/dev/ic/bcmgenet.c

660

val = RD4(sc, GENET_RX_DMA_CTRL);

sys/dev/ic/bcmgenet.c

665

val = RD4(sc, GENET_TX_DMA_CTRL);

sys/dev/ic/bcmgenet.c

675

val = RD4(sc, GENET_UMAC_CMD);

sys/dev/ic/bcmgenet.c

709

pidx = RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)) & 0xffff;

sys/dev/ic/bcmgenet.c

716

status = RD4(sc, GENET_RX_DESC_STATUS(index));

sys/dev/ic/bcmgenet.c

799

cidx = RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)) & 0xffff;

sys/dev/ic/bcmgenet.c

832

sc->sc_tx.queued = (RD4(sc, GENET_TX_DMA_PROD_INDEX(qid))

sys/dev/ic/bcmgenet.c

883

val = RD4(sc, GENET_INTRL2_CPU_STAT);

sys/dev/ic/bcmgenet.c

884

val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);

sys/dev/ic/bcmgenet.c

969

val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);

sys/dev/ic/bcmgenet.c

971

maclo = RD4(sc, GENET_UMAC_MAC0);

sys/dev/ic/bcmgenet.c

972

machi = RD4(sc, GENET_UMAC_MAC1) & 0xffff;

sys/dev/ic/cdnsiic.c

148

sr_val = RD4(sc, SR_REG);

sys/dev/ic/cdnsiic.c

149

isr_val = RD4(sc, ISR_REG);

sys/dev/ic/cdnsiic.c

169

val = RD4(sc, ISR_REG);

sys/dev/ic/cdnsiic.c

192

val = RD4(sc, CR_REG);

sys/dev/ic/cdnsiic.c

196

WR4(sc, ISR_REG, RD4(sc, ISR_REG));

sys/dev/ic/cdnsiic.c

199

fifo_space = FIFO_DEPTH - RD4(sc, TRANS_SIZE_REG);

sys/dev/ic/cdnsiic.c

229

val = RD4(sc, CR_REG);

sys/dev/ic/cdnsiic.c

232

WR4(sc, ISR_REG, RD4(sc, ISR_REG));

sys/dev/ic/cdnsiic.c

241

*data = RD4(sc, DATA_REG) & 0xff;

sys/dev/ic/cdnsiic.c

257

val = RD4(sc, CR_REG);

sys/dev/ic/cdnsiic.c

273

val = RD4(sc, CR_REG);

sys/dev/ic/dwc_eqos.c

1240

RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC),

sys/dev/ic/dwc_eqos.c

1241

RD4(sc, GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR));

sys/dev/ic/dwc_eqos.c

1268

dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE);

sys/dev/ic/dwc_eqos.c

1289

dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE);

sys/dev/ic/dwc_eqos.c

1307

debug_data = RD4(sc, GMAC_MTL_FIFO_DEBUG_DATA);

sys/dev/ic/dwc_eqos.c

1313

ictrl = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS);

sys/dev/ic/dwc_eqos.c

1348

mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS);

sys/dev/ic/dwc_eqos.c

1349

mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE);

sys/dev/ic/dwc_eqos.c

1357

mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS);

sys/dev/ic/dwc_eqos.c

1360

dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE);

sys/dev/ic/dwc_eqos.c

1361

dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS);

sys/dev/ic/dwc_eqos.c

1381

rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS);

sys/dev/ic/dwc_eqos.c

1501

maclo = RD4(sc, GMAC_MAC_ADDRESS0_LOW);

sys/dev/ic/dwc_eqos.c

1502

machi = __SHIFTOUT(RD4(sc, GMAC_MAC_ADDRESS0_HIGH),

sys/dev/ic/dwc_eqos.c

1546

val = RD4(sc, GMAC_DMA_SYSBUS_MODE);

sys/dev/ic/dwc_eqos.c

156

addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);

sys/dev/ic/dwc_eqos.c

158

*val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF;

sys/dev/ic/dwc_eqos.c

1744

const uint32_t ver = RD4(sc, GMAC_MAC_VERSION);

sys/dev/ic/dwc_eqos.c

1780

sc->sc_hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n));

sys/dev/ic/dwc_eqos.c

188

addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);

sys/dev/ic/dwc_eqos.c

2066

reg = RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC);

sys/dev/ic/dwc_eqos.c

2092

reg = RD4(sc, GMAC_DMA_CHAN0_TX_END_ADDR);

sys/dev/ic/dwc_eqos.c

211

conf = RD4(sc, GMAC_MAC_CONFIGURATION);

sys/dev/ic/dwc_eqos.c

2111

reg = RD4(sc, GMAC_DMA_CHAN0_CUR_RX_DESC);

sys/dev/ic/dwc_eqos.c

2130

reg = RD4(sc, GMAC_DMA_CHAN0_RX_END_ADDR);

sys/dev/ic/dwc_eqos.c

562

pfil = RD4(sc, GMAC_MAC_PACKET_FILTER);

sys/dev/ic/dwc_eqos.c

658

val = RD4(sc, GMAC_MAC_CONFIGURATION);

sys/dev/ic/dwc_eqos.c

678

val = RD4(sc, GMAC_DMA_MODE);

sys/dev/ic/dwc_eqos.c

753

val = RD4(sc, GMAC_DMA_CHAN0_CONTROL);

sys/dev/ic/dwc_eqos.c

758

val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);

sys/dev/ic/dwc_eqos.c

764

val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);

sys/dev/ic/dwc_eqos.c

793

val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);

sys/dev/ic/dwc_eqos.c

800

val = RD4(sc, GMAC_MTL_RXQ0_OPERATION_MODE);

sys/dev/ic/dwc_eqos.c

817

val = RD4(sc, GMAC_MAC_CONFIGURATION);

sys/dev/ic/dwc_eqos.c

874

val = RD4(sc, GMAC_MAC_CONFIGURATION);

sys/dev/ic/dwc_eqos.c

879

val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);

sys/dev/ic/dwc_eqos.c

884

val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);

sys/dev/ic/dwc_eqos.c

890

val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);

sys/dev/ic/dwc_eqos.c

895

val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);

sys/dev/ic/dwc_eqos.c

908

val = RD4(sc, GMAC_MAC_CONFIGURATION);

sys/dev/ic/dwc_wdt.c

144

cr = RD4(sc, WDT_CR);