OF_parent
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
const int parent = OF_parent(phandle);
for (child = OF_child(OF_parent(phandle)); child; child = OF_peer(child)) {
return rk3066_smp_enable(OF_parent(phandle), cpuno);
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(OF_parent(phandle)));
rm = fdtbus_syscon_lookup(OF_parent(sc->sc_phy_node));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle));
return of_compatible_match(OF_parent(phy), mdio_internal_compat);
struct syscon *syscon = fdtbus_syscon_lookup(OF_parent(phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle));
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle));
if (fdtbus_get_reg(OF_parent(phandle), 0, &addr, &size) != 0) {
const int prcm_phandle = OF_parent(OF_parent(phandle));
const int prcm_phandle = OF_parent(OF_parent(phandle));
const int prcm_phandle = OF_parent(OF_parent(phandle));
sc->sc_modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
const int prcm_phandle = OF_parent(OF_parent(phandle));
hwmod_phandle = of_hasprop(phandle, "ti,hwmods") ? phandle : OF_parent(phandle);
sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle));
node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1");
node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1");
tc_node = OF_parent(node);
sc->sc_node = OF_parent(sc->sc_node);
extint_node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1");
parent = OF_parent(node);
gpio = of_getnode_byname(OF_parent(node), "gpio");
escc = OF_parent(escc_ch);
obio = OF_parent(escc);
escc = OF_parent(escc_ch);
obio = OF_parent(escc);
int mio = OF_parent(intrparent);
OF_getprop(OF_parent(node), "ATY,RefCLK", &temp,
} else if (OF_getprop(OF_parent(node), "backlight-control", &temp,
node = OF_parent(node);
parent = OF_parent(node);
qhandle = OF_parent(qhandle);
parent = OF_parent(node);
q = OF_parent(q);
OF_getprop(OF_parent(node), "name", name, sizeof(name));
qhandle = OF_parent(qhandle);
if (OF_getprop(OF_parent(node), "#address-cells", &parent_acells,
node = OF_parent(node);
const int cpu_ref = OF_parent(xref);
else if (OF_parent(node) != root) {
node = OF_parent(node);
else if (OF_parent(node) != root) {
next = OF_parent(node);
bi_unit.parent = OF_parent(phandle);
node = OF_parent(OF_parent(ea->ea_node));
node = OF_parent(OF_parent(ea->ea_node));
while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
node = OF_parent(node);
parent = OF_parent(node);
for (node = ofnode; node != 0; node = OF_parent(node)) {
OF_getprop(OF_parent(node), "ATY,RefCLK", &temp,
node = OF_parent(node);
for( ; node; node = OF_parent(node)) {
for (; node; node = OF_parent(node)) {
node = OF_parent(node);
iparent = OF_parent(iparent);
phandle = OF_parent(phandle);
if (of_getprop_uint32(OF_parent(xref), "#pinctrl-cells", &pinctrl_cells) != 0)
const int parent = OF_parent(phandle);
const int addr_cells = fdtbus_get_addr_cells(OF_parent(phandle));
const int size_cells = fdtbus_get_size_cells(OF_parent(phandle));
*paddr = fdtbus_decode_range(OF_parent(phandle), addr);
const int parent = OF_parent(phandle);
parent = OF_parent(node->n_phandle);
parent = OF_parent(parent);
parent = OF_parent(node->n_phandle);
parent = OF_parent(parent);
node = OF_parent(node);
int OF_parent(int);
int parent = OF_parent(node);
parent = OF_parent(parent);
parent = OF_parent(node);
parent = OF_parent(parent);
int parent = OF_parent(node);
int OF_parent(int);