sys/arch/arm/amlogic/meson_i2c.c

156

#define WR4(sc, reg, val) \

sys/arch/arm/nvidia/tegra210_xusbpad.c

220

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk3288_iomux.c

85

#define WR4(reg, off, val) \

sys/arch/arm/rockchip/rk3328_iomux.c

135

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk3399_iomux.c

202

#define WR4(syscon, reg, val) \

sys/arch/arm/rockchip/rk_emmcphy.c

105

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_gpio.c

114

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_i2c.c

126

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_i2s.c

166

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_vop.c

186

#define WR4(sc, reg, val) \

sys/arch/arm/samsung/exynos_uart.c

112

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun4i_a10_codec.c

110

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun50i_a64_acodec.c

155

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun6i_a31_codec.c

153

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_codec.c

131

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_h3_codec.c

128

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_v3s_codec.c

115

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

82

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_emac.c

202

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_gmacclk.c

86

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_thermal.c

340

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_comp_clock.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_div_clock.c

83

#define WR4(sc, val) \

sys/arch/arm/ti/ti_dpll_clock.c

160

#define WR4(sc, space, val) \

sys/arch/arm/ti/ti_gate_clock.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_gpio.c

141

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_lcdc.h

124

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_mux_clock.c

81

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_omapmusb.c

85

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_omaptimer.c

117

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_rng.c

66

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_usb.c

141

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_usbtll.c

99

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_wdt.c

90

#define WR4(sc, reg, val) \

sys/arch/arm/xilinx/zynq_gpio.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/xilinx/zynq_xadc.c

149

#define WR4(sc, reg, val) \

sys/arch/arm/xscale/ixp425_if_npe.c

186

WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)

sys/arch/evbppc/nintendo/dev/ahb.c

48

#define WR4(reg, val) out32(reg, val)

sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c

54

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/avenc.c

61

#define WR4 avenc_write_4

sys/arch/evbppc/nintendo/dev/bwai.c

86

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/di.c

140

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/exi.c

79

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/gecko.c

67

#define WR4(reg, val) out32(EXI_BASE + (reg), val)

sys/arch/evbppc/nintendo/dev/hwaes.c

102

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/hwgpio.c

133

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/si.c

128

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/wiifb.c

162

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/pic_pi.c

65

#define WR4(reg, val) out32(reg, val)

sys/arch/luna68k/dev/sioreg.h

77

#define WR4 0x04

sys/arch/luna68k/stand/boot/sioreg.h

96

#define WR4 0x04

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

195

WR4(struct mpcac97_softc *sc, bus_size_t o, uint32_t v)

sys/arch/riscv/sifive/fu540_ccache.c

100

#define WR4(sc, reg, val) \

sys/arch/riscv/sifive/fu540_prci.c

88

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_clkc.c

969

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_pcie.c

81

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_pciephy.c

59

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_pinctrl.c

104

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_syscon.c

54

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_trng.c

146

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_trng.c

64

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh71x0_clkc.c

48

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh71x0_temp.c

53

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh71x0_usb.c

54

#define WR4(sc, reg, val) \

sys/dev/acpi/amdgpio.c

79

#define WR4(sc, reg, val) \

sys/dev/acpi/qcomgpio.c

105

#define WR4(sc, reg, val) \

sys/dev/fdt/dwc3_fdt.c

92

#define WR4(sc, reg, val) \

sys/dev/ic/bcmgenet.c

89

#define WR4(sc, reg, val) \

sys/dev/ic/cdnsiic.c

90

#define WR4(sc, reg, val) \

sys/dev/ic/dwc_eqos.c

118

#define WR4(sc, reg, val) \

sys/dev/ic/dwc_wdt.c

86

#define WR4(sc, reg, val) \