root/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h 
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * DWMAC4 DMA Header file.
 *
 * Copyright (C) 2007-2015  STMicroelectronics Ltd
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#ifndef __DWMAC4_DMA_H__
#define __DWMAC4_DMA_H__

/* Define the max channel number used for tx (also rx).
 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
 */
#define DMA_CHANNEL_NB_MAX              1

#define DMA_BUS_MODE                    0x00001000

#define DMA_BUS_MODE_DCHE               BIT(19)
#define DMA_BUS_MODE_INTM_MASK          GENMASK(17, 16)
#define DMA_BUS_MODE_INTM_MODE1         0x1
#define DMA_BUS_MODE_SFT_RESET          BIT(0)

#define DMA_SYS_BUS_MODE                0x00001004

#define DMA_BUS_MODE_MB                 BIT(14)
#define DMA_BUS_MODE_FB                 BIT(0)

#define DMA_STATUS                      0x00001008

#define DMA_AXI_BUS_MODE                0x00001028

#define DMA_AXI_EN_LPI                  BIT(31)
#define DMA_AXI_LPI_XIT_FRM             BIT(30)
#define DMA_AXI_WR_OSR_LMT              GENMASK(27, 24)
#define DMA_AXI_RD_OSR_LMT              GENMASK(19, 16)

#define DMA_SYS_BUS_MB                  BIT(14)
#define DMA_SYS_BUS_AAL                 DMA_AXI_AAL
#define DMA_SYS_BUS_EAME                BIT(11)
#define DMA_SYS_BUS_FB                  BIT(0)

#define DMA_TBS_CTRL                    0x00001050

#define DMA_TBS_FTOS                    GENMASK(31, 8)
#define DMA_TBS_FTOV                    BIT(0)
#define DMA_TBS_DEF_FTOS                (DMA_TBS_FTOS | DMA_TBS_FTOV)

/* Following DMA defines are channel-oriented */
#define DMA_CHAN_BASE_ADDR              0x00001100
#define DMA_CHAN_BASE_OFFSET            0x80

static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
                                      const u32 x)
{
        u32 addr;

        if (addrs)
                addr = addrs->dma_chan + (x * addrs->dma_chan_offset);
        else
                addr = DMA_CHAN_BASE_ADDR + (x * DMA_CHAN_BASE_OFFSET);

        return addr;
}

#define DMA_CHAN_CONTROL(addrs, x)      dma_chanx_base_addr(addrs, x)

#define DMA_CHAN_CTRL_PBLX8             BIT(16)
#define DMA_CONTROL_SPH                 BIT(24)

#define DMA_CHAN_TX_CONTROL(addrs, x)   (dma_chanx_base_addr(addrs, x) + 0x4)

#define DMA_CONTROL_EDSE                BIT(28)
#define DMA_CHAN_TX_CTRL_TXPBL_MASK     GENMASK(21, 16)
#define DMA_CONTROL_TSE                 BIT(12)
#define DMA_CONTROL_OSP                 BIT(4)
#define DMA_CONTROL_ST                  BIT(0)

#define DMA_CHAN_RX_CONTROL(addrs, x)   (dma_chanx_base_addr(addrs, x) + 0x8)

#define DMA_CHAN_RX_CTRL_RXPBL_MASK     GENMASK(21, 16)
#define DMA_RBSZ_MASK                   GENMASK(14, 1)
#define DMA_CONTROL_SR                  BIT(0)

#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x)      (dma_chanx_base_addr(addrs, x) + 0x10)
#define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14)
#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x)      (dma_chanx_base_addr(addrs, x) + 0x18)
#define DMA_CHAN_RX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x1c)
#define DMA_CHAN_TX_END_ADDR(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x20)
#define DMA_CHAN_RX_END_ADDR(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x28)
#define DMA_CHAN_TX_RING_LEN(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x2c)
#define DMA_CHAN_RX_RING_LEN(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x30)

#define DMA_CHAN_INTR_ENA(addrs, x)     (dma_chanx_base_addr(addrs, x) + 0x34)

#define DMA_CHAN_INTR_ENA_NIE           BIT(16)
#define DMA_CHAN_INTR_ENA_AIE           BIT(15)
#define DMA_CHAN_INTR_ENA_NIE_4_10      BIT(15)
#define DMA_CHAN_INTR_ENA_AIE_4_10      BIT(14)
#define DMA_CHAN_INTR_ENA_FBE           BIT(12)
#define DMA_CHAN_INTR_ENA_RIE           BIT(6)
#define DMA_CHAN_INTR_ENA_TIE           BIT(0)

#define DMA_CHAN_INTR_NORMAL            (DMA_CHAN_INTR_ENA_NIE | \
                                         DMA_CHAN_INTR_ENA_RIE | \
                                         DMA_CHAN_INTR_ENA_TIE)

#define DMA_CHAN_INTR_ABNORMAL          (DMA_CHAN_INTR_ENA_AIE | \
                                         DMA_CHAN_INTR_ENA_FBE)
/* DMA default interrupt mask for 4.00 */
#define DMA_CHAN_INTR_DEFAULT_MASK      (DMA_CHAN_INTR_NORMAL | \
                                         DMA_CHAN_INTR_ABNORMAL)
#define DMA_CHAN_INTR_DEFAULT_RX        (DMA_CHAN_INTR_ENA_RIE)
#define DMA_CHAN_INTR_DEFAULT_TX        (DMA_CHAN_INTR_ENA_TIE)

#define DMA_CHAN_INTR_NORMAL_4_10       (DMA_CHAN_INTR_ENA_NIE_4_10 | \
                                         DMA_CHAN_INTR_ENA_RIE | \
                                         DMA_CHAN_INTR_ENA_TIE)

#define DMA_CHAN_INTR_ABNORMAL_4_10     (DMA_CHAN_INTR_ENA_AIE_4_10 | \
                                         DMA_CHAN_INTR_ENA_FBE)
/* DMA default interrupt mask for 4.10a */
#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
                                         DMA_CHAN_INTR_ABNORMAL_4_10)
#define DMA_CHAN_INTR_DEFAULT_RX_4_10   (DMA_CHAN_INTR_ENA_RIE)
#define DMA_CHAN_INTR_DEFAULT_TX_4_10   (DMA_CHAN_INTR_ENA_TIE)

#define DMA_CHAN_RX_WATCHDOG(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x38)
#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x)     (dma_chanx_base_addr(addrs, x) + 0x3c)
#define DMA_CHAN_CUR_TX_DESC(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x44)
#define DMA_CHAN_CUR_RX_DESC(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x4c)
#define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x)   (dma_chanx_base_addr(addrs, x) + 0x50)
#define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x)      (dma_chanx_base_addr(addrs, x) + 0x54)
#define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x)   (dma_chanx_base_addr(addrs, x) + 0x58)
#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x)      (dma_chanx_base_addr(addrs, x) + 0x5c)
#define DMA_CHAN_STATUS(addrs, x)       (dma_chanx_base_addr(addrs, x) + 0x60)

/* Interrupt status per channel */
#define DMA_CHAN_STATUS_REB             GENMASK(21, 19)
#define DMA_CHAN_STATUS_NIS             BIT(15)
#define DMA_CHAN_STATUS_AIS             BIT(14)
#define DMA_CHAN_STATUS_CDE             BIT(13)
#define DMA_CHAN_STATUS_FBE             BIT(12)
#define DMA_CHAN_STATUS_ERI             BIT(11)
#define DMA_CHAN_STATUS_ETI             BIT(10)
#define DMA_CHAN_STATUS_RWT             BIT(9)
#define DMA_CHAN_STATUS_RPS             BIT(8)
#define DMA_CHAN_STATUS_RBU             BIT(7)
#define DMA_CHAN_STATUS_RI              BIT(6)
#define DMA_CHAN_STATUS_TBU             BIT(2)
#define DMA_CHAN_STATUS_TPS             BIT(1)
#define DMA_CHAN_STATUS_TI              BIT(0)

#define DMA_CHAN_STATUS_MSK_COMMON      (DMA_CHAN_STATUS_NIS | \
                                         DMA_CHAN_STATUS_AIS | \
                                         DMA_CHAN_STATUS_CDE | \
                                         DMA_CHAN_STATUS_FBE)

#define DMA_CHAN_STATUS_MSK_RX          (DMA_CHAN_STATUS_REB | \
                                         DMA_CHAN_STATUS_ERI | \
                                         DMA_CHAN_STATUS_RWT | \
                                         DMA_CHAN_STATUS_RPS | \
                                         DMA_CHAN_STATUS_RBU | \
                                         DMA_CHAN_STATUS_RI | \
                                         DMA_CHAN_STATUS_MSK_COMMON)

#define DMA_CHAN_STATUS_MSK_TX          (DMA_CHAN_STATUS_ETI | \
                                         DMA_CHAN_STATUS_TBU | \
                                         DMA_CHAN_STATUS_TPS | \
                                         DMA_CHAN_STATUS_TI | \
                                         DMA_CHAN_STATUS_MSK_COMMON)

int dwmac4_dma_reset(void __iomem *ioaddr);
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
                           u32 chan, bool rx, bool tx);
void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
                             u32 chan, bool rx, bool tx);
void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
                            u32 chan, bool rx, bool tx);
void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
                              u32 chan, bool rx, bool tx);
void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
                         u32 chan);
void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
                        u32 chan);
void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
                         u32 chan);
void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
                        u32 chan);
int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
                         struct stmmac_extra_stats *x, u32 chan, u32 dir);
void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
                            u32 len, u32 chan);
void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
                            u32 len, u32 chan);
void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
                            u32 tail_ptr, u32 chan);
void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
                            u32 tail_ptr, u32 chan);

#endif /* __DWMAC4_DMA_H__ */