DMA_CHAN_CONTROL
u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
reg_space[DMA_CHAN_CONTROL(default_addrs, channel) / 4] =
readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel));
value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));