DMA_BUS_MODE
value = readl(ioaddr + DMA_BUS_MODE);
writel(value, ioaddr + DMA_BUS_MODE);
return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
value = readl(ioaddr + DMA_BUS_MODE);
writel(value, ioaddr + DMA_BUS_MODE);
return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
reg_space[DMA_BUS_MODE / 4 + i] =
readl(ioaddr + DMA_BUS_MODE + i * 4);
ioaddr + DMA_BUS_MODE);
reg_space[DMA_BUS_MODE / 4 + i] =
readl(ioaddr + DMA_BUS_MODE + i * 4);
value = readl(ioaddr + DMA_BUS_MODE);
writel(value, ioaddr + DMA_BUS_MODE);
u32 value = readl(ioaddr + DMA_BUS_MODE);
writel(value, ioaddr + DMA_BUS_MODE);
return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
u32 value = readl(ioaddr + DMA_BUS_MODE);
writel(value, ioaddr + DMA_BUS_MODE);
return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
®_space[DMA_BUS_MODE / 4],