DMA_CHAN_INTR_ENA
DMA_CHAN_INTR_ENA(chan));
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
reg_space[DMA_CHAN_INTR_ENA(default_addrs, channel) / 4] =
readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel));
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));