arch/alpha/include/asm/io.h
263
extern void __raw_writew(u16 b, volatile void __iomem *addr);
arch/alpha/include/asm/io.h
271
#define __raw_writew __raw_writew
arch/alpha/include/asm/io.h
485
__raw_writew(b, addr);
arch/alpha/include/asm/vga.h
21
__raw_writew(val, (volatile u16 __iomem *) addr);
arch/alpha/kernel/io.c
168
EXPORT_SYMBOL(__raw_writew);
arch/alpha/kernel/io.c
217
__raw_writew(b, addr);
arch/alpha/kernel/io.c
569
__raw_writew(*(const u16 *)from, to);
arch/alpha/kernel/io.c
603
__raw_writew(c, to);
arch/alpha/kernel/io.c
636
__raw_writew(c, to);
arch/alpha/kernel/io.c
673
__raw_writew(tmp, iod++);
arch/arc/include/asm/io.h
133
#define __raw_writew __raw_writew
arch/arc/include/asm/io.h
226
#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
arch/arc/include/asm/io.h
42
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
arch/arm/include/asm/io.h
236
#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
arch/arm/include/asm/io.h
281
#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
arch/arm/include/asm/io.h
393
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
arch/arm/include/asm/io.h
67
#define __raw_writew __raw_writew
arch/arm/mach-omap1/board-ams-delta.c
660
__raw_writew(latch2, IOMEM(LATCH2_VIRT));
arch/arm/mach-omap1/clock.c
279
__raw_writew(regval, DSP_CKCTL);
arch/arm/mach-omap1/clock.c
423
__raw_writew(ratio_bits, clk->enable_reg);
arch/arm/mach-omap1/clock.c
490
__raw_writew(ratio_bits, clk->enable_reg);
arch/arm/mach-omap1/clock.c
559
__raw_writew(regval16, clk->enable_reg);
arch/arm/mach-omap1/clock.c
604
__raw_writew(regval16, clk->enable_reg);
arch/arm/mach-omap1/dma.c
182
__raw_writew(val, addr);
arch/arm/mach-omap1/dma.c
184
__raw_writew(val >> 16, addr + 2);
arch/arm/mach-omap1/io.c
101
__raw_writew(v, OMAP1_IO_ADDRESS(pa));
arch/arm/mach-omap1/mcbsp.c
53
__raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
arch/arm/mach-omap1/pm.c
282
__raw_writew(0, DSP_IDLECT2);
arch/arm/mach-omap1/pm.h
133
#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
arch/arm/mach-orion5x/pci.c
310
__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
arch/arm64/include/asm/io.h
302
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
arch/arm64/include/asm/io.h
32
#define __raw_writew __raw_writew
arch/hexagon/include/asm/io.h
104
#define __raw_writew __raw_writew
arch/m68k/coldfire/dma_timer.c
62
__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
arch/m68k/coldfire/intc-2.c
172
__raw_writew(pa, MCFEPORT_EPPAR);
arch/m68k/coldfire/intc-simr.c
156
__raw_writew(pa, MCFEPORT_EPPAR);
arch/m68k/coldfire/intc.c
49
__raw_writew(imr | (0x1 << index), MCFSIM_IMR);
arch/m68k/coldfire/intc.c
56
__raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
arch/m68k/coldfire/intc.c
64
__raw_writew(imr, MCFSIM_IMR);
arch/m68k/coldfire/m5272.c
73
__raw_writew(0, MCFSIM_WIRR);
arch/m68k/coldfire/m5272.c
74
__raw_writew(1, MCFSIM_WRRR);
arch/m68k/coldfire/m5272.c
75
__raw_writew(0, MCFSIM_WCR);
arch/m68k/coldfire/pci.c
112
__raw_writew(cpu_to_le16(value), addr);
arch/m68k/coldfire/pci.c
189
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
arch/m68k/coldfire/pci.c
190
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
arch/m68k/coldfire/pit.c
105
__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
arch/m68k/coldfire/pit.c
48
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
arch/m68k/coldfire/pit.c
49
__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
arch/m68k/coldfire/pit.c
50
__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
arch/m68k/coldfire/pit.c
58
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
arch/m68k/coldfire/pit.c
59
__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
arch/m68k/coldfire/pit.c
66
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
arch/m68k/coldfire/pit.c
78
__raw_writew(delta, TA(MCFPIT_PMR));
arch/m68k/coldfire/timers.c
114
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
arch/m68k/coldfire/timers.c
123
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
arch/m68k/coldfire/timers.c
177
__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
arch/m68k/coldfire/timers.c
180
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
arch/m68k/coldfire/timers.c
45
#define __raw_writetrr __raw_writew
arch/m68k/include/asm/io_no.h
105
#define writew __raw_writew
arch/m68k/include/asm/io_no.h
85
__raw_writew(value, addr);
arch/m68k/include/asm/io_no.h
87
__raw_writew(swab16(value), addr);
arch/m68k/include/asm/mcfgpio.h
108
#define mcfgpio_write(data, port) __raw_writew(data, port)
arch/m68k/include/asm/vga.h
34
#define writew __raw_writew
arch/microblaze/include/asm/io.h
39
#define out_be16(a, v) __raw_writew((v), (a))
arch/microblaze/include/asm/io.h
49
#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
arch/mips/alchemy/devboards/bcsr.c
104
__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
arch/mips/alchemy/devboards/bcsr.c
111
__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
arch/mips/alchemy/devboards/bcsr.c
112
__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
arch/mips/alchemy/devboards/bcsr.c
119
__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
arch/mips/alchemy/devboards/bcsr.c
135
__raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
arch/mips/alchemy/devboards/bcsr.c
136
__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
arch/mips/alchemy/devboards/bcsr.c
137
__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
arch/mips/alchemy/devboards/bcsr.c
67
__raw_writew(val, bcsr_regs[reg].raddr);
arch/mips/alchemy/devboards/bcsr.c
82
__raw_writew(r, bcsr_regs[reg].raddr);
arch/mips/include/asm/io.h
370
__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
arch/mips/include/asm/io.h
499
#define __raw_writew __raw_writew
arch/mips/pci/ops-tx4927.c
126
__raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
arch/parisc/lib/iomap.c
206
__raw_writew(datum, addr);
arch/parisc/lib/iomap.c
266
__raw_writew(*(u16 *)s, addr);
arch/riscv/include/asm/mmio.h
25
#define __raw_writew __raw_writew
arch/riscv/include/asm/mmio.h
93
#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
arch/sh/boards/board-magicpanelr2.c
101
__raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
arch/sh/boards/board-magicpanelr2.c
106
__raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
arch/sh/boards/board-magicpanelr2.c
111
__raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
116
__raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
arch/sh/boards/board-magicpanelr2.c
121
__raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
126
__raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
arch/sh/boards/board-magicpanelr2.c
131
__raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
arch/sh/boards/board-magicpanelr2.c
136
__raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
arch/sh/boards/board-magicpanelr2.c
141
__raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
146
__raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
arch/sh/boards/board-magicpanelr2.c
151
__raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
157
__raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
arch/sh/boards/board-magicpanelr2.c
174
__raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
192
__raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
197
__raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
arch/sh/boards/board-magicpanelr2.c
202
__raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
arch/sh/boards/board-magicpanelr2.c
207
__raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
arch/sh/boards/board-magicpanelr2.c
216
__raw_writew(0xAABC, PORT_PSELA);
arch/sh/boards/board-magicpanelr2.c
221
__raw_writew(0x3C00, PORT_PSELB);
arch/sh/boards/board-magicpanelr2.c
225
__raw_writew(0x0000, PORT_PSELC);
arch/sh/boards/board-magicpanelr2.c
229
__raw_writew(0x0000, PORT_PSELD);
arch/sh/boards/board-magicpanelr2.c
231
__raw_writew(0x0101, PORT_UTRCTL);
arch/sh/boards/board-magicpanelr2.c
233
__raw_writew(0xA5C0, PORT_UCLKCR_W);
arch/sh/boards/board-polaris.c
106
__raw_writew(wcr, WCR2);
arch/sh/boards/board-polaris.c
111
__raw_writew(bcr_mask, BCR2);
arch/sh/boards/board-polaris.c
142
__raw_writew(0, BCR_ILCRA);
arch/sh/boards/board-polaris.c
143
__raw_writew(0, BCR_ILCRB);
arch/sh/boards/board-polaris.c
144
__raw_writew(0, BCR_ILCRC);
arch/sh/boards/board-polaris.c
145
__raw_writew(0, BCR_ILCRD);
arch/sh/boards/board-polaris.c
146
__raw_writew(0, BCR_ILCRE);
arch/sh/boards/board-polaris.c
147
__raw_writew(0, BCR_ILCRF);
arch/sh/boards/board-polaris.c
148
__raw_writew(0, BCR_ILCRG);
arch/sh/boards/board-shmin.c
21
__raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
arch/sh/boards/board-shmin.c
22
__raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
arch/sh/boards/board-urquell.c
155
__raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
arch/sh/boards/board-urquell.c
165
__raw_writew(0xa5a5, UBOARDREG(SRSTR));
arch/sh/boards/mach-ap325rxa/setup.c
180
__raw_writew(0x100, FPGA_BKLREG);
arch/sh/boards/mach-ap325rxa/setup.c
182
__raw_writew(0, FPGA_BKLREG);
arch/sh/boards/mach-ap325rxa/setup.c
194
__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
arch/sh/boards/mach-ap325rxa/setup.c
200
__raw_writew(0, FPGA_LCDREG);
arch/sh/boards/mach-ap325rxa/setup.c
480
__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
arch/sh/boards/mach-ap325rxa/setup.c
498
__raw_writew(0, PORT_HIZCRC);
arch/sh/boards/mach-ap325rxa/setup.c
499
__raw_writew(0xFFFF, PORT_DRVCRA);
arch/sh/boards/mach-ap325rxa/setup.c
500
__raw_writew(0xFFFF, PORT_DRVCRB);
arch/sh/boards/mach-ecovec24/setup.c
1134
__raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
arch/sh/boards/mach-ecovec24/setup.c
1154
__raw_writew(0x0000, 0xA4D80000);
arch/sh/boards/mach-ecovec24/setup.c
1155
__raw_writew(0x0000, 0xA4D90000);
arch/sh/boards/mach-ecovec24/setup.c
1162
__raw_writew(0x0600, 0xa40501d4);
arch/sh/boards/mach-ecovec24/setup.c
1163
__raw_writew(0x0600, 0xa4050192);
arch/sh/boards/mach-ecovec24/setup.c
1204
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
arch/sh/boards/mach-ecovec24/setup.c
1214
__raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
arch/sh/boards/mach-ecovec24/setup.c
1357
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000,
arch/sh/boards/mach-highlander/irq-r7785rp.c
71
__raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
arch/sh/boards/mach-highlander/irq-r7785rp.c
74
__raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
arch/sh/boards/mach-highlander/irq-r7785rp.c
75
__raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
arch/sh/boards/mach-highlander/irq-r7785rp.c
76
__raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
arch/sh/boards/mach-highlander/irq-r7785rp.c
77
__raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
arch/sh/boards/mach-highlander/irq-r7785rp.c
78
__raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
arch/sh/boards/mach-highlander/irq-r7785rp.c
79
__raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
arch/sh/boards/mach-highlander/psw.c
45
__raw_writew(l, PA_DBSW);
arch/sh/boards/mach-highlander/setup.c
313
__raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
arch/sh/boards/mach-highlander/setup.c
319
__raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
arch/sh/boards/mach-highlander/setup.c
343
__raw_writew(0x0001, PA_POFF);
arch/sh/boards/mach-highlander/setup.c
378
__raw_writew(0x0000, PA_OBLED); /* Clear LED. */
arch/sh/boards/mach-highlander/setup.c
381
__raw_writew(0x0001, PA_SDPOW); /* SD Power ON */
arch/sh/boards/mach-highlander/setup.c
383
__raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
arch/sh/boards/mach-hp6xx/pm.c
57
__raw_writew(frqcr, FRQCR);
arch/sh/boards/mach-hp6xx/pm.c
65
__raw_writew(mcr & ~MCR_RFSH, MCR);
arch/sh/boards/mach-hp6xx/pm.c
75
__raw_writew(0, RTCNT);
arch/sh/boards/mach-hp6xx/pm.c
76
__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
arch/sh/boards/mach-hp6xx/pm.c
87
__raw_writew(frqcr, FRQCR);
arch/sh/boards/mach-hp6xx/pm.c
90
__raw_writew(frqcr, FRQCR);
arch/sh/boards/mach-hp6xx/setup.c
163
__raw_writew(v, SCPCR);
arch/sh/boards/mach-kfr2r09/setup.c
462
__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
arch/sh/boards/mach-kfr2r09/setup.c
468
__raw_writew(0x0600, 0xa40501d4);
arch/sh/boards/mach-kfr2r09/setup.c
596
__raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
arch/sh/boards/mach-landisk/gio.c
80
__raw_writew((unsigned short int)(0x0ffff & data), addr);
arch/sh/boards/mach-migor/setup.c
568
__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
arch/sh/boards/mach-migor/setup.c
581
__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
arch/sh/boards/mach-r2d/setup.c
262
__raw_writew(0x0001, PA_POWOFF);
arch/sh/boards/mach-r2d/setup.c
278
__raw_writew(0x0000, PA_OUTPORT);
arch/sh/boards/mach-r2d/setup.c
70
__raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE);
arch/sh/boards/mach-sdk7780/irq.c
37
__raw_writew(0xFFFF, FPGA_IRQ0MR);
arch/sh/boards/mach-sdk7780/irq.c
39
__raw_writew(0x0003, FPGA_IMSR);
arch/sh/boards/mach-sdk7780/setup.c
85
__raw_writew(0x0000, GPIO_PECR);
arch/sh/boards/mach-se/7206/irq.c
115
__raw_writew(sts0, INTSTS0);
arch/sh/boards/mach-se/7206/irq.c
116
__raw_writew(sts1, INTSTS1);
arch/sh/boards/mach-se/7206/irq.c
143
__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */
arch/sh/boards/mach-se/7206/irq.c
146
__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
arch/sh/boards/mach-se/7206/irq.c
147
__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
arch/sh/boards/mach-se/7206/irq.c
150
__raw_writew(0x0001,INTSEL);
arch/sh/boards/mach-se/7206/irq.c
39
__raw_writew(val, INTC_IPR01);
arch/sh/boards/mach-se/7206/irq.c
56
__raw_writew(msk0, INTMSK0);
arch/sh/boards/mach-se/7206/irq.c
57
__raw_writew(msk1, INTMSK1);
arch/sh/boards/mach-se/7206/irq.c
70
__raw_writew(val, INTC_IPR01);
arch/sh/boards/mach-se/7206/irq.c
88
__raw_writew(msk0, INTMSK0);
arch/sh/boards/mach-se/7206/irq.c
89
__raw_writew(msk1, INTMSK1);
arch/sh/boards/mach-se/7343/irq.c
120
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
arch/sh/boards/mach-se/7343/setup.c
167
__raw_writew(0xf900, FPGA_OUT); /* FPGA */
arch/sh/boards/mach-se/7343/setup.c
169
__raw_writew(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
arch/sh/boards/mach-se/7343/setup.c
170
__raw_writew(0x0020, PORT_PSELD);
arch/sh/boards/mach-se/770x/irq.c
100
__raw_writew(0, BCR_ILCRA);
arch/sh/boards/mach-se/770x/irq.c
101
__raw_writew(0, BCR_ILCRB);
arch/sh/boards/mach-se/770x/irq.c
102
__raw_writew(0, BCR_ILCRC);
arch/sh/boards/mach-se/770x/irq.c
103
__raw_writew(0, BCR_ILCRD);
arch/sh/boards/mach-se/770x/irq.c
104
__raw_writew(0, BCR_ILCRE);
arch/sh/boards/mach-se/770x/irq.c
105
__raw_writew(0, BCR_ILCRF);
arch/sh/boards/mach-se/770x/irq.c
106
__raw_writew(0, BCR_ILCRG);
arch/sh/boards/mach-se/7721/irq.c
38
__raw_writew(__raw_readw(0xa4050118) & ~0x00ff, 0xa4050118);
arch/sh/boards/mach-se/7721/setup.c
79
__raw_writew(0x0000, 0xA405010C); /* PGCR */
arch/sh/boards/mach-se/7721/setup.c
80
__raw_writew(0x0000, 0xA405010E); /* PHCR */
arch/sh/boards/mach-se/7721/setup.c
81
__raw_writew(0x00AA, 0xA4050118); /* PPCR */
arch/sh/boards/mach-se/7721/setup.c
82
__raw_writew(0x0000, 0xA4050124); /* PSELA */
arch/sh/boards/mach-se/7722/irq.c
112
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
arch/sh/boards/mach-se/7722/setup.c
155
__raw_writew(0x010D, FPGA_OUT); /* FPGA */
arch/sh/boards/mach-se/7722/setup.c
157
__raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
arch/sh/boards/mach-se/7722/setup.c
158
__raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
arch/sh/boards/mach-se/7722/setup.c
161
__raw_writew(0x0020, PORT_PSELD);
arch/sh/boards/mach-se/7722/setup.c
164
__raw_writew(0x0003, PORT_PSELB);
arch/sh/boards/mach-se/7722/setup.c
165
__raw_writew(0xe000, PORT_PSELC);
arch/sh/boards/mach-se/7722/setup.c
166
__raw_writew(0x0000, PORT_PKCR);
arch/sh/boards/mach-se/7722/setup.c
169
__raw_writew(0x4020, PORT_PHCR);
arch/sh/boards/mach-se/7722/setup.c
170
__raw_writew(0x0000, PORT_PLCR);
arch/sh/boards/mach-se/7722/setup.c
171
__raw_writew(0x0000, PORT_PMCR);
arch/sh/boards/mach-se/7722/setup.c
172
__raw_writew(0x0002, PORT_PRCR);
arch/sh/boards/mach-se/7722/setup.c
173
__raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */
arch/sh/boards/mach-se/7722/setup.c
176
__raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
arch/sh/boards/mach-se/7722/setup.c
177
__raw_writew(0x0000, PORT_PYCR);
arch/sh/boards/mach-se/7722/setup.c
178
__raw_writew(0x0000, PORT_PZCR);
arch/sh/boards/mach-se/7722/setup.c
179
__raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
arch/sh/boards/mach-se/7722/setup.c
180
__raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
arch/sh/boards/mach-se/7724/irq.c
116
__raw_writew(0xffff, IRQ0_MR); /* mask all */
arch/sh/boards/mach-se/7724/irq.c
117
__raw_writew(0xffff, IRQ1_MR); /* mask all */
arch/sh/boards/mach-se/7724/irq.c
118
__raw_writew(0xffff, IRQ2_MR); /* mask all */
arch/sh/boards/mach-se/7724/irq.c
119
__raw_writew(0x0000, IRQ0_SR); /* clear irq */
arch/sh/boards/mach-se/7724/irq.c
120
__raw_writew(0x0000, IRQ1_SR); /* clear irq */
arch/sh/boards/mach-se/7724/irq.c
121
__raw_writew(0x0000, IRQ2_SR); /* clear irq */
arch/sh/boards/mach-se/7724/irq.c
122
__raw_writew(0x002a, IRQ_MODE); /* set irq type */
arch/sh/boards/mach-se/7724/irq.c
75
__raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
arch/sh/boards/mach-se/7724/irq.c
83
__raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
arch/sh/boards/mach-se/7724/setup.c
638
__raw_writew(0x0, EEPROM_OP); /* read */
arch/sh/boards/mach-se/7724/setup.c
639
__raw_writew(i*2, EEPROM_ADR);
arch/sh/boards/mach-se/7724/setup.c
640
__raw_writew(0x1, EEPROM_STRT);
arch/sh/boards/mach-se/7724/setup.c
706
__raw_writew(fpga_out | (1 << 4), FPGA_OUT);
arch/sh/boards/mach-se/7724/setup.c
711
__raw_writew(fpga_out | (1 << 5), FPGA_OUT);
arch/sh/boards/mach-se/7724/setup.c
715
__raw_writew(fpga_out, FPGA_OUT);
arch/sh/boards/mach-se/7724/setup.c
718
__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
arch/sh/boards/mach-se/7724/setup.c
730
__raw_writew(0x0600, 0xa40501d4);
arch/sh/boards/mach-se/7724/setup.c
733
__raw_writew(0x0600, 0xa4050192);
arch/sh/boards/mach-se/7724/setup.c
781
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
arch/sh/boards/mach-se/7780/irq.c
24
__raw_writew(0, FPGA_INTMSK1);
arch/sh/boards/mach-se/7780/irq.c
26
__raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
arch/sh/boards/mach-se/7780/irq.c
28
__raw_writew(0, FPGA_INTMSK2);
arch/sh/boards/mach-se/7780/irq.c
32
__raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
arch/sh/boards/mach-se/7780/irq.c
36
__raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
arch/sh/boards/mach-se/7780/irq.c
42
__raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
arch/sh/boards/mach-se/7780/irq.c
63
__raw_writew(0x0013, FPGA_PCI_INTSEL1);
arch/sh/boards/mach-se/7780/irq.c
64
__raw_writew(0xE402, FPGA_PCI_INTSEL2);
arch/sh/boards/mach-se/7780/setup.c
101
__raw_writew(0x0001, FPGA_IVDRPW);
arch/sh/boards/mach-se/7780/setup.c
75
__raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
76
__raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
77
__raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
78
__raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
79
__raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
80
__raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
81
__raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
82
__raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
arch/sh/boards/mach-se/7780/setup.c
93
__raw_writew(0x0213, FPGA_REQSEL);
arch/sh/boards/mach-se/7780/setup.c
96
__raw_writew(0x0000, GPIO_PECR);
arch/sh/boards/mach-se/7780/setup.c
97
__raw_writew(__raw_readw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
arch/sh/boards/mach-se/7780/setup.c
98
__raw_writew(0x0c00, GPIO_PMSELR);
arch/sh/boards/mach-sh7763rdp/setup.c
169
__raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
arch/sh/boards/mach-sh7763rdp/setup.c
171
__raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);
arch/sh/boards/mach-sh7763rdp/setup.c
174
__raw_writew(0x00, USB_USBHSC);
arch/sh/boards/mach-sh7763rdp/setup.c
178
__raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);
arch/sh/boards/mach-sh7763rdp/setup.c
180
__raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);
arch/sh/boards/mach-sh7763rdp/setup.c
181
__raw_writew(0, PORT_PKCR);
arch/sh/boards/mach-sh7763rdp/setup.c
182
__raw_writew(0, PORT_PLCR);
arch/sh/boards/mach-sh7763rdp/setup.c
184
__raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
arch/sh/boards/mach-sh7763rdp/setup.c
186
__raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
arch/sh/boards/mach-sh7763rdp/setup.c
190
__raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
arch/sh/boards/mach-sh7763rdp/setup.c
192
__raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
arch/sh/boards/mach-sh7763rdp/setup.c
195
__raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
arch/sh/boards/mach-sh7763rdp/setup.c
196
__raw_writew(0x0, PORT_PFCR);
arch/sh/boards/mach-sh7763rdp/setup.c
197
__raw_writew(0x0, PORT_PFCR);
arch/sh/boards/mach-sh7763rdp/setup.c
198
__raw_writew(0x0, PORT_PFCR);
arch/sh/boards/mach-sh7763rdp/setup.c
202
__raw_writew(0x0001, PORT_PSEL0);
arch/sh/boards/mach-sh7763rdp/setup.c
205
__raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR);
arch/sh/boards/mach-sh7763rdp/setup.c
206
__raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
arch/sh/boards/mach-x3proto/gpio.c
37
__raw_writew(data, KEYCTLR);
arch/sh/boards/mach-x3proto/ilsel.c
152
__raw_writew(tmp, addr);
arch/sh/boards/mach-x3proto/ilsel.c
77
__raw_writew(tmp, addr);
arch/sh/boot/romimage/mmcif-sh7724.c
45
__raw_writew(0x0000, PTWCR);
arch/sh/boot/romimage/mmcif-sh7724.c
48
__raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
arch/sh/boot/romimage/mmcif-sh7724.c
51
__raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
arch/sh/boot/romimage/mmcif-sh7724.c
54
__raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
arch/sh/boot/romimage/mmcif-sh7724.c
57
__raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
arch/sh/boot/romimage/mmcif-sh7724.c
60
__raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
arch/sh/cchips/hd6446x/hd64461.c
29
__raw_writew(nimr, HD64461_NIMR);
arch/sh/cchips/hd6446x/hd64461.c
40
__raw_writew(nimr, HD64461_NIMR);
arch/sh/cchips/hd6446x/hd64461.c
86
__raw_writew(0x2240, INTC_ICR1);
arch/sh/cchips/hd6446x/hd64461.c
88
__raw_writew(0xffff, HD64461_NIMR);
arch/sh/drivers/dma/dma-sh.c
267
#define dmaor_write_reg(n, data) __raw_writew(data, \
arch/sh/drivers/pci/pci-sh7780.c
113
__raw_writew(cmd, hose->reg_base + PCI_STATUS);
arch/sh/drivers/pci/pci-sh7780.c
172
__raw_writew(PCI_STATUS_DETECTED_PARITY | \
arch/sh/drivers/pci/pci-sh7780.c
236
__raw_writew(tmp, hose->reg_base + PCI_STATUS);
arch/sh/drivers/pci/pci-sh7780.c
379
__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
arch/sh/include/asm/io.h
44
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
arch/sh/include/asm/watchdog.h
134
__raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
arch/sh/include/asm/watchdog.h
156
__raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
arch/sh/include/mach-common/mach/magicpanelr2.h
20
#define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg)
arch/sh/include/mach-common/mach/magicpanelr2.h
23
#define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg)
arch/sh/include/mach-ecovec24/mach/romimage.h
42
__raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
arch/sh/include/mach-se/mach/mrshpc.h
13
__raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
arch/sh/include/mach-se/mach/mrshpc.h
15
__raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
arch/sh/include/mach-se/mach/mrshpc.h
23
__raw_writew(0x8a84, MRSHPC_MW0CR1);
arch/sh/include/mach-se/mach/mrshpc.h
26
__raw_writew(0x0b00, MRSHPC_MW0CR2);
arch/sh/include/mach-se/mach/mrshpc.h
29
__raw_writew(0x0300, MRSHPC_MW0CR2);
arch/sh/include/mach-se/mach/mrshpc.h
32
__raw_writew(0x8a85, MRSHPC_MW1CR1);
arch/sh/include/mach-se/mach/mrshpc.h
35
__raw_writew(0x0a00, MRSHPC_MW1CR2);
arch/sh/include/mach-se/mach/mrshpc.h
38
__raw_writew(0x0200, MRSHPC_MW1CR2);
arch/sh/include/mach-se/mach/mrshpc.h
41
__raw_writew(0x8a86, MRSHPC_IOWCR1);
arch/sh/include/mach-se/mach/mrshpc.h
42
__raw_writew(0x0008, MRSHPC_CDCR); /* I/O card mode */
arch/sh/include/mach-se/mach/mrshpc.h
44
__raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
arch/sh/include/mach-se/mach/mrshpc.h
46
__raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
arch/sh/include/mach-se/mach/mrshpc.h
48
__raw_writew(0x2000, MRSHPC_ICR);
arch/sh/kernel/cpu/irq/ipr.c
35
__raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
arch/sh/kernel/cpu/irq/ipr.c
44
__raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
arch/sh/kernel/cpu/sh2a/setup-sh7264.c
474
__raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
arch/sh/kernel/cpu/sh3/serial-sh770x.c
17
__raw_writew(data & 0x0fcf, SCPCR);
arch/sh/kernel/cpu/sh3/serial-sh770x.c
24
__raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
arch/sh/kernel/cpu/sh3/serial-sh7710.c
13
__raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
arch/sh/kernel/cpu/sh3/serial-sh7710.c
14
__raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
arch/sh/kernel/cpu/sh3/serial-sh7710.c
16
__raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
arch/sh/kernel/cpu/sh3/serial-sh7720.c
17
__raw_writew((data & 0xfc03), PORT_PTCR);
arch/sh/kernel/cpu/sh3/serial-sh7720.c
21
__raw_writew((data & 0xfc03), PORT_PVCR);
arch/sh/kernel/cpu/sh3/serial-sh7720.c
27
__raw_writew((data & 0xffc3), PORT_PTCR);
arch/sh/kernel/cpu/sh3/serial-sh7720.c
31
__raw_writew((data & 0xffc3), PORT_PVCR);
arch/sh/kernel/cpu/sh3/setup-sh3.c
59
__raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
arch/sh/kernel/cpu/sh4/perf_event.c
214
__raw_writew(tmp, PMCR(idx));
arch/sh/kernel/cpu/sh4/perf_event.c
219
__raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx));
arch/sh/kernel/cpu/sh4/perf_event.c
220
__raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx));
arch/sh/kernel/cpu/sh4/perf_event.c
228
__raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i));
arch/sh/kernel/cpu/sh4/perf_event.c
236
__raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i));
arch/sh/kernel/cpu/sh4/setup-sh7750.c
353
__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
arch/sh/kernel/cpu/sh4/setup-sh7760.c
286
__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
arch/sh/kernel/cpu/sh4a/serial-sh7722.c
18
__raw_writew(data, PSCR);
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1202
__raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1232
__raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1233
__raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1234
__raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1235
__raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1236
__raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1237
__raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1238
__raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1239
__raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1240
__raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1241
__raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1242
__raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1243
__raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1259
__raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1260
__raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
arch/sh/kernel/io_trapped.c
208
__raw_writew(tmp, dst_addr);
arch/sh/kernel/kgdb.c
160
__raw_writew(stepped_opcode, stepped_address);
arch/sparc/include/asm/io.h
20
#define writew_be(__l, __addr) __raw_writew(__l, __addr)
arch/sparc/include/asm/io_64.h
331
__raw_writew(w, addr);
arch/sparc/include/asm/io_64.h
446
#define iowrite16be __raw_writew
arch/sparc/include/asm/io_64.h
77
#define __raw_writew __raw_writew
arch/sparc/lib/PeeCeeI.c
28
__raw_writew(*(u16 *)src, addr);
drivers/ata/pata_octeon_cf.c
440
__raw_writew(ap->ctl, base + 0xe);
drivers/ata/pata_octeon_cf.c
442
__raw_writew(ap->ctl | ATA_SRST, base + 0xe);
drivers/ata/pata_octeon_cf.c
444
__raw_writew(ap->ctl, base + 0xe);
drivers/ata/pata_octeon_cf.c
474
__raw_writew(tf->hob_feature << 8, base + 0xc);
drivers/ata/pata_octeon_cf.c
475
__raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
drivers/ata/pata_octeon_cf.c
476
__raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
drivers/ata/pata_octeon_cf.c
479
__raw_writew(tf->feature << 8, base + 0xc);
drivers/ata/pata_octeon_cf.c
480
__raw_writew(tf->nsect | tf->lbal << 8, base + 2);
drivers/ata/pata_octeon_cf.c
481
__raw_writew(tf->lbam | tf->lbah << 8, base + 4);
drivers/ata/pata_octeon_cf.c
508
__raw_writew(blob, base + 6);
drivers/bcma/host_soc.c
115
__raw_writew((__force u16)(*buf), addr);
drivers/dma/sh/shdmac.c
104
__raw_writew(data, addr);
drivers/dma/sh/shdmac.c
275
__raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
drivers/gpio/gpio-mm-lantiq.c
47
__raw_writew(chip->shadow, chip->regs);
drivers/input/keyboard/jornada680_kbd.c
143
__raw_writew((dc_static | *y++), PDCR);
drivers/input/keyboard/jornada680_kbd.c
144
__raw_writew((ec_static | *y++), PECR);
drivers/input/keyboard/jornada680_kbd.c
161
__raw_writew((dc_static | (0x5555 & 0xcc0c)),PDCR);
drivers/input/keyboard/jornada680_kbd.c
162
__raw_writew((ec_static | (0x5555 & 0xf0cf)),PECR);
drivers/mmc/host/dw_mmc.h
473
#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
drivers/mmc/host/omap.c
83
#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
drivers/mtd/maps/physmap-ixp4xx.c
47
__raw_writew(cpu_to_be16(d), (void __iomem *)((unsigned long)addr ^ 0x2));
drivers/mtd/maps/physmap-ixp4xx.c
62
__raw_writew(d, addr);
drivers/mtd/nand/raw/mxc_nand.c
1481
__raw_writew(0xffff, t++);
drivers/mtd/nand/raw/mxc_nand.c
237
__raw_writew(*s++, t++);
drivers/net/ethernet/8390/pcnet_cs.c
1356
do { __raw_writew(*s++, d++); } while (--c);
drivers/net/ethernet/8390/pcnet_cs.c
1448
__raw_writew((i>>1), info->base+offset+i);
drivers/net/ethernet/cirrus/ep93xx_eth.c
180
#define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
drivers/net/ethernet/freescale/enetc/enetc_pf.c
31
__raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
drivers/net/ethernet/freescale/fs_enet/fs_enet.h
199
#define __cbd_out16(addr, x) __raw_writew(x, addr)
drivers/net/ethernet/freescale/fs_enet/mac-fec.c
45
#define __fs_out16(addr, x) __raw_writew(x, addr)
drivers/net/ethernet/freescale/fs_enet/mac-scc.c
41
#define __fs_out16(addr, x) __raw_writew(x, addr)
drivers/net/ethernet/natsemi/sonic.h
356
__raw_writew(val, base + (offset * 2) + 1);
drivers/net/ethernet/natsemi/sonic.h
358
__raw_writew(val, base + (offset * 2) + 0);
drivers/net/ethernet/natsemi/sonic.h
361
__raw_writew(val, base + (offset * 1) + 0);
drivers/parisc/lba_pci.c
132
#define WRITE_U16(value, addr) __raw_writew(value, addr)
drivers/scsi/ncr53c8xx.h
275
#define writew_b2l __raw_writew
drivers/scsi/ncr53c8xx.h
279
#define writew_raw __raw_writew
drivers/sh/intc/access.c
109
__raw_writew(intc_set_field_from_handle(0, data, h), ptr);
drivers/sh/intc/access.c
145
__raw_writew(value, ptr);
drivers/sh/intc/chip.c
104
__raw_writew(0xffff ^ value, addr);
drivers/spi/spi-bcm63xx-hsspi.c
430
__raw_writew(val, bs->fifo);
drivers/spi/spi-bcm63xx-hsspi.c
541
__raw_writew(val, bs->fifo);
drivers/spi/spi-bcmbca-hsspi.c
297
__raw_writew(val, bs->fifo);
drivers/spi/spi-omap-uwire.c
107
__raw_writew(val, uwire_base + (idx << uwire_idx_shift));
drivers/ssb/host_soc.c
139
__raw_writew((__force u16)(*buf), addr);
drivers/ssb/pcmcia.c
401
__raw_writew((__force u16)(*buf), addr);
drivers/ssb/pcmcia.c
412
__raw_writew((__force u16)(*buf), addr);
drivers/ssb/pcmcia.c
414
__raw_writew((__force u16)(*buf), addr + 2);
drivers/usb/c67x00/c67x00-ll-hpi.c
79
__raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep);
drivers/usb/host/isp116x.h
371
__raw_writew(val, isp116x->data_reg);
drivers/usb/isp1760/isp1760-hcd.c
462
__raw_writew(*src, priv->base + ISP1763_HC_DATA);
drivers/usb/musb/musb_core.c
276
__raw_writew(data, addr + offset);
drivers/usb/musb/musb_core.c
339
__raw_writew(*(u16 *)&src[index], fifo);
drivers/usb/musb/tusb6010.c
174
__raw_writew(tmp, addr + (offset & ~1));
drivers/video/fbdev/nvidia/nv_local.h
64
#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
74
__raw_writew((r << 11) | (g << 5) | (b << 0), p);
drivers/video/fbdev/riva/riva_hw.h
80
#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
include/asm-generic/io.h
157
#ifndef __raw_writew
include/asm-generic/io.h
158
#define __raw_writew __raw_writew
include/asm-generic/io.h
279
__raw_writew((u16 __force)cpu_to_le16(value), addr);
include/asm-generic/io.h
399
__raw_writew((u16 __force)cpu_to_le16(value), addr);
include/asm-generic/io.h
523
__raw_writew(*buf++, addr);
include/asm-generic/io.h
650
__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
include/asm-generic/logic_io.h
56
#define __raw_writew __raw_writew
include/asm-generic/logic_io.h
57
void __raw_writew(u16 value, volatile void __iomem *addr);
include/asm-generic/video.h
89
__raw_writew(b, addr);
include/linux/mtd/doc2000.h
98
__raw_writew(data, addr + reg);
include/linux/mtd/map.h
418
__raw_writew(datum.x[0], map->virt + ofs);
lib/iomap.c
347
__raw_writew(*src, addr);
sound/soc/renesas/sh7760-ac97.c
44
__raw_writew(ipsel | (3 << 10), IPSEL);
tools/include/asm-generic/io.h
120
#ifndef __raw_writew
tools/include/asm-generic/io.h
121
#define __raw_writew __raw_writew
tools/include/asm-generic/io.h
227
__raw_writew((u16 __force)cpu_to_le16(value), addr);
tools/include/asm-generic/io.h
329
__raw_writew((u16 __force)cpu_to_le16(value), addr);
tools/include/asm-generic/io.h
446
__raw_writew(*buf++, addr);
