Symbol: SZ_64K
arch/arm/kernel/bios32.c
410
sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
arch/arm/kernel/bios32.c
411
sys->io_res.end = (busnr + 1) * SZ_64K - 1;
arch/arm/kernel/bios32.c
588
.length = SZ_64K,
arch/arm/mach-dove/dove.h
49
#define DOVE_PCIE0_IO_SIZE SZ_64K
arch/arm/mach-dove/dove.h
53
#define DOVE_PCIE1_IO_SIZE SZ_64K
arch/arm/mach-dove/pcie.c
54
realio.start = sys->busnr * SZ_64K;
arch/arm/mach-dove/pcie.c
55
realio.end = realio.start + SZ_64K - 1;
arch/arm/mach-imx/mx31.h
14
#define MX31_X_MEMC_SIZE SZ_64K
arch/arm/mach-imx/mx35.h
14
#define MX35_X_MEMC_SIZE SZ_64K
arch/arm/mach-imx/mx3x.h
130
#define MX3x_X_MEMC_SIZE SZ_64K
arch/arm/mach-mv78xx0/pcie.c
116
realio.start = nr * SZ_64K;
arch/arm/mach-mv78xx0/pcie.c
117
realio.end = realio.start + SZ_64K - 1;
arch/arm/mach-mv78xx0/pcie.c
94
i * SZ_64K, SZ_64K, 0);
arch/arm/mach-mvebu/pmsu.c
134
SRAM_PHYS_BASE, SZ_64K);
arch/arm/mach-mvebu/pmsu.c
136
sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
arch/arm/mach-orion5x/orion5x.h
42
#define ORION5X_PCIE_IO_SIZE SZ_64K
arch/arm/mach-orion5x/orion5x.h
46
#define ORION5X_PCI_IO_SIZE SZ_64K
arch/arm/mach-orion5x/pci.c
165
realio.start = sys->busnr * SZ_64K;
arch/arm/mach-orion5x/pci.c
166
realio.end = realio.start + SZ_64K - 1;
arch/arm/mach-orion5x/pci.c
486
realio.start = sys->busnr * SZ_64K;
arch/arm/mach-orion5x/pci.c
487
realio.end = realio.start + SZ_64K - 1;
arch/arm/mach-sa1100/generic.c
119
[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
arch/arm/mach-sa1100/generic.c
137
[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
arch/arm/mach-sa1100/generic.c
149
[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
arch/arm/mach-sa1100/generic.c
161
[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
arch/arm/mach-sa1100/generic.c
195
[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
arch/arm/mach-sa1100/generic.c
213
[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
arch/arm/mach-sa1100/generic.c
396
DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
arch/arm64/crypto/ghash-ce-glue.c
83
#define MAX_BLOCKS (SZ_64K / GHASH_BLOCK_SIZE)
arch/arm64/include/asm/efi.h
103
#define EFI_ALLOC_ALIGN SZ_64K
arch/arm64/include/asm/kvm_nested.h
262
case SZ_64K: \
arch/arm64/include/asm/memory.h
162
#define SEGMENT_ALIGN SZ_64K
arch/arm64/include/asm/pgtable.h
1608
#define exec_folio_order() ilog2(SZ_64K >> PAGE_SHIFT)
arch/arm64/include/asm/tlbflush.h
443
(lpa2 && __flush_start != ALIGN(__flush_start, SZ_64K))) { \
arch/arm64/include/asm/tlbflush.h
76
case SZ_64K:
arch/arm64/include/uapi/asm/kvm.h
96
#define KVM_VGIC_V3_DIST_SIZE SZ_64K
arch/arm64/include/uapi/asm/kvm.h
97
#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
arch/arm64/include/uapi/asm/kvm.h
98
#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
arch/arm64/kernel/image-vars.h
160
kimage_limit = ALIGN(ABSOLUTE(_end + SZ_64K), SZ_2M);
arch/arm64/kernel/machine_kexec_file.c
122
kbuf.buf_align = SZ_64K; /* largest supported page size */
arch/arm64/kvm/at.c
290
if (wi->txsz > 48 || (BIT(wi->pgshift) == SZ_64K && wi->txsz > 47))
arch/arm64/kvm/at.c
300
case SZ_64K:
arch/arm64/kvm/at.c
39
case SZ_64K:
arch/arm64/kvm/at.c
500
case SZ_64K:
arch/arm64/kvm/at.c
72
case SZ_64K:
arch/arm64/kvm/at.c
767
if (!wi->pa52bit || BIT(wi->pgshift) == SZ_64K)
arch/arm64/kvm/hyp/nvhe/ffa.c
755
min_rxtx_sz = SZ_64K;
arch/arm64/kvm/nested.c
1574
case SZ_64K:
arch/arm64/kvm/nested.c
1600
case SZ_64K:
arch/arm64/kvm/nested.c
164
case SZ_64K:
arch/arm64/kvm/nested.c
256
case SZ_64K:
arch/arm64/kvm/nested.c
473
max_size = SZ_64K;
arch/arm64/kvm/nested.c
552
if (sz < SZ_64K) sz = SZ_64K;
arch/arm64/kvm/reset.c
299
if (!kvm_lpa2_is_enabled() && PAGE_SIZE != SZ_64K)
arch/arm64/kvm/vgic/vgic-its.c
2390
int l2_start_id = id * (SZ_64K / abi->dte_esz);
arch/arm64/kvm/vgic/vgic-its.c
2403
ret = scan_its_table(its, gpa, SZ_64K, dte_esz,
arch/arm64/kvm/vgic/vgic-its.c
2418
int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
arch/arm64/kvm/vgic/vgic-its.c
2517
max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
arch/arm64/kvm/vgic/vgic-its.c
2556
max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
arch/arm64/kvm/vgic/vgic-its.c
2742
addr, SZ_64K, KVM_VGIC_V3_ITS_SIZE);
arch/arm64/kvm/vgic/vgic-its.c
870
int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
arch/arm64/kvm/vgic/vgic-its.c
905
index = id / (SZ_64K / esz);
arch/arm64/kvm/vgic/vgic-its.c
925
index = id % (SZ_64K / esz);
arch/arm64/kvm/vgic/vgic-kvm-device.c
128
alignment = SZ_64K;
arch/arm64/kvm/vgic/vgic-mmio-v3.c
718
REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
721
REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
725
REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
729
REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
733
REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
737
REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
741
REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
745
REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
748
REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
751
REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
754
REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
arch/arm64/kvm/vgic/vgic-mmio-v3.c
766
return SZ_64K;
arch/arm64/kvm/vgic/vgic-mmio-v3.c
824
2 * SZ_64K, &rd_dev->dev);
arch/arm64/kvm/vgic/vgic-mmio-v3.c
938
ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size);
arch/arm64/kvm/vgic/vgic-v3.c
698
rdreg->base, SZ_64K, sz))
arch/arm64/lib/insn.c
896
if (imm & ~(SZ_64K - 1)) {
arch/loongarch/include/asm/efi.h
20
#define EFI_ALLOC_ALIGN SZ_64K
arch/loongarch/kernel/efi.c
49
return early_memremap_ro(fdt_pointer, SZ_64K);
arch/loongarch/kernel/kexec_elf.c
44
kbuf->memsz = ALIGN(phdr->p_memsz, SZ_64K);
arch/loongarch/kernel/machine_kexec_file.c
176
kbuf.buf_align = SZ_64K; /* largest supported page size */
arch/loongarch/kernel/traps.c
1134
long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
arch/loongarch/pci/pci.c
120
regbase = ioremap(readq(base + PCI_BASE_ADDRESS_0) & ~0xffull, SZ_64K);
arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
49
vmlinuz_load_addr += (SZ_64K - vmlinux_size % SZ_64K);
arch/mips/include/asm/mach-ralink/spaces.h
6
#define PCI_IOSIZE SZ_64K
arch/parisc/include/asm/floppy.h
24
((unsigned long)(a) / SZ_64K != ((unsigned long)(a) + (s) - 1) / SZ_64K))
arch/powerpc/platforms/powernv/pci-ioda-tce.c
30
mask = SZ_4K | SZ_64K;
arch/powerpc/platforms/pseries/iommu.c
1384
__builtin_ctzll(SZ_4K), __builtin_ctzll(SZ_64K), __builtin_ctzll(SZ_16M),
arch/powerpc/platforms/pseries/iommu.c
1786
(SZ_4K), (SZ_64K), (SZ_16M),
arch/x86/include/asm/floppy.h
26
((unsigned long)(a) / SZ_64K != ((unsigned long)(a) + (s) - 1) / SZ_64K))
arch/x86/kernel/setup.c
818
memblock_reserve(0, SZ_64K);
drivers/accel/habanalabs/gaudi2/gaudi2.c
2861
if (PAGE_SIZE == SZ_64K) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
6376
if (PAGE_SIZE == SZ_64K) {
drivers/accel/ivpu/ivpu_mmu.c
56
#define IVPU_MMU_REG_EVTQ_PROD_SEC (0x002000a8u + SZ_64K)
drivers/accel/ivpu/ivpu_mmu.c
57
#define IVPU_MMU_REG_EVTQ_CONS_SEC (0x002000acu + SZ_64K)
drivers/accel/ivpu/ivpu_ms.c
16
#define MS_INFO_BUFFER_SIZE SZ_64K
drivers/accel/qaic/qaic_control.c
34
#define QAIC_MANAGE_WIRE_MSG_LENGTH SZ_64K /* Max DMA message length */
drivers/accel/qaic/qaic_ssr.c
19
#define SSR_MHI_BUF_SIZE SZ_64K
drivers/acpi/arm64/iort.c
1273
region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K,
drivers/acpi/arm64/iort.c
1627
return SZ_64K;
drivers/acpi/arm64/iort.c
954
if (!IS_ALIGNED(addr, SZ_64K) || !IS_ALIGNED(size, SZ_64K)) {
drivers/ata/pata_macio.c
218
#define PATA_MACIO_MAX_SEGMENT_SIZE SZ_64K
drivers/clk/tegra/clk-tegra210.c
3762
ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
drivers/cpufreq/tegra186-cpufreq.c
17
#define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4))
drivers/cpufreq/tegra186-cpufreq.c
18
#define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4))
drivers/crypto/hisilicon/qm.c
1239
case SZ_64K:
drivers/cxl/cxl.h
27
#define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
drivers/dma/bcm2835-dma.c
173
#define MAX_LITE_DMA_LEN (SZ_64K - 4)
drivers/dma/mmp_tdma.c
99
#define TDMA_MAX_XFER_BYTES SZ_64K
drivers/dma/qcom/qcom_adm.c
100
#define ADM_MAX_ROWS (SZ_64K - 1)
drivers/dma/qcom/qcom_adm.c
99
#define ADM_MAX_XFER (SZ_64K - 1)
drivers/dma/stm32/stm32-dma3.c
1131
__alignof__(struct stm32_dma3_hwdesc), SZ_64K);
drivers/dma/tegra186-gpc-dma.c
1309
.channel_reg_size = SZ_64K,
drivers/dma/tegra186-gpc-dma.c
1317
.channel_reg_size = SZ_64K,
drivers/dma/tegra186-gpc-dma.c
1325
.channel_reg_size = SZ_64K,
drivers/dma/ti/edma.c
1131
if (len < SZ_64K) {
drivers/dma/ti/edma.c
1240
if (xt->sgl[0].size > SZ_64K || xt->numf > SZ_64K)
drivers/dma/ti/edma.c
1265
if (src_bidx > SZ_64K || dst_bidx > SZ_64K)
drivers/dma/ti/edma.c
930
ccnt = dma_length / acnt / (SZ_64K - 1);
drivers/dma/ti/edma.c
931
bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
drivers/dma/ti/edma.c
939
bcnt = SZ_64K - 1;
drivers/dma/ti/edma.c
954
if (ccnt > (SZ_64K - 1)) {
drivers/dma/ti/k3-udma.c
2856
if (len < SZ_64K) {
drivers/dma/ti/k3-udma.c
2867
*tr0_cnt0 = SZ_64K - BIT(align_to);
drivers/dma/ti/k3-udma.c
2868
if (len / *tr0_cnt0 >= SZ_64K) {
drivers/dma/ti/k3-udma.c
2899
if (sg_dma_len(sgent) < SZ_64K)
drivers/dma/ti/k3-udma.c
3030
if (sg_len / trigger_size < SZ_64K)
drivers/dpll/zl3073x/flash.c
237
*sector_size = SZ_64K;
drivers/firmware/arm_ffa/driver.c
2059
rxtx_bufsz = SZ_64K;
drivers/firmware/efi/libstub/efi-stub.c
258
paddr = round_down(in->phys_addr, SZ_64K);
drivers/firmware/efi/libstub/efi-stub.c
270
efi_virt_base = round_up(efi_virt_base, SZ_64K);
drivers/firmware/efi/vars.c
40
return (size <= SZ_64K) ? EFI_SUCCESS : EFI_OUT_OF_RESOURCES;
drivers/gpu/drm/arm/malidp_planes.c
469
if (pgsize == SZ_64K || pgsize == SZ_2M) {
drivers/gpu/drm/arm/malidp_planes.c
65
#define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K)
drivers/gpu/drm/armada/armada_drv.c
73
if (resource_size(r) > SZ_64K)
drivers/gpu/drm/exynos/exynos_drm_rotator.c
377
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
382
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1381
{ igt_create_internal, SZ_64K, SZ_2M, },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1382
{ igt_create_shmem, SZ_64K, SZ_32M, },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1383
{ igt_create_local, SZ_64K, SZ_1G, },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1473
{ SZ_64K, SZ_64K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1475
{ SZ_2M, SZ_64K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1476
{ SZ_2M - SZ_64K, SZ_64K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1477
{ SZ_2M - SZ_4K, SZ_64K | SZ_4K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1478
{ SZ_2M + SZ_4K, SZ_64K | SZ_4K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1480
{ SZ_2M + SZ_64K, SZ_2M | SZ_64K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
1481
{ SZ_2M + SZ_64K, SZ_64K },
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
872
.size = SZ_64K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
877
.size = SZ_64K + SZ_4K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
882
.size = SZ_64K - SZ_4K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
902
.size = SZ_2M + SZ_64K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
907
.size = SZ_2M - SZ_64K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
913
.size = SZ_64K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
919
.offset = SZ_2M - SZ_64K,
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
959
if (size >= SZ_64K)
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
961
if (size & (SZ_64K - 1))
drivers/gpu/drm/i915/gt/gen6_ppgtt.c
156
start = round_down(start, SZ_64K);
drivers/gpu/drm/i915/gt/gen6_ppgtt.c
157
end = round_up(end, SZ_64K) - start;
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
798
GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
799
GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
drivers/gpu/drm/i915/gt/intel_migrate.c
1001
GEM_BUG_ON(ce->ring->size < SZ_64K);
drivers/gpu/drm/i915/gt/intel_migrate.c
187
sz += (sz / SZ_2M) * SZ_64K;
drivers/gpu/drm/i915/gt/intel_migrate.c
388
offset *= SZ_64K;
drivers/gpu/drm/i915/gt/intel_migrate.c
433
offset = round_up(offset, SZ_64K);
drivers/gpu/drm/i915/gt/intel_migrate.c
703
GEM_BUG_ON(ce->ring->size < SZ_64K);
drivers/gpu/drm/i915/gt/intel_migrate.c
71
d->offset += SZ_64K;
drivers/gpu/drm/i915/gt/intel_region_lmem.c
214
flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
drivers/gpu/drm/i915/gt/selftest_engine_cs.c
226
obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_engine_cs.c
236
memset(cs, 0, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_engine_cs.c
237
cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
drivers/gpu/drm/i915/gt/selftest_lrc.c
1150
batch = create_user_vma(ce->vm, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_lrc.c
1428
ref[0] = create_result_vma(A->vm, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_lrc.c
1434
ref[1] = create_result_vma(A->vm, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_lrc.c
1456
result[0] = create_result_vma(A->vm, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_lrc.c
1462
result[1] = create_result_vma(A->vm, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_lrc.c
979
batch = create_user_vma(ce->vm, SZ_64K);
drivers/gpu/drm/i915/gt/selftest_migrate.c
154
GEM_BUG_ON(ce->ring->size < SZ_64K);
drivers/gpu/drm/i915/gt/selftest_migrate.c
16
SZ_64K,
drivers/gpu/drm/i915/gt/selftest_migrate.c
896
SZ_64K,
drivers/gpu/drm/i915/gt/selftest_migrate.c
979
SZ_64K,
drivers/gpu/drm/i915/gt/selftest_tlb.c
89
if (align == SZ_64K)
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
29
#define GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE SZ_64K
drivers/gpu/drm/i915/i915_gpu_error.c
112
e->size = ALIGN(len + 1, SZ_64K);
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
18
#define PXP43_MAX_HECI_INOUT_SIZE (PAGE_ALIGN(SZ_64K + SZ_1K))
drivers/gpu/drm/i915/selftests/intel_memory_region.c
1312
SZ_64K,
drivers/gpu/drm/i915/selftests/intel_memory_region.c
309
target = SZ_64K;
drivers/gpu/drm/i915/selftests/intel_memory_region.c
471
ps = SZ_64K; /* For something like DG2 */
drivers/gpu/drm/i915/selftests/intel_memory_region.c
563
ps = SZ_64K; /* For something like DG2 */
drivers/gpu/drm/imagination/pvr_fw.c
32
#define PVR_ROGUE_FW_CONFIG_HEAP_GRANULARITY SZ_64K
drivers/gpu/drm/imagination/pvr_mmu.c
40
#elif (PVR_DEVICE_PAGE_SIZE == SZ_64K)
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
478
vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", SZ_16M, 0xfff * SZ_64K, true);
drivers/gpu/drm/msm/adreno/a2xx_gpummu.c
23
#define GPUMMU_VA_RANGE (0xfff * SZ_64K)
drivers/gpu/drm/panthor/panthor_sched.c
3509
if (args->ringbuf_size < SZ_4K || args->ringbuf_size > SZ_64K ||
drivers/gpu/drm/tests/drm_buddy_test.c
105
KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, SZ_8K, SZ_64K,
drivers/gpu/drm/tests/drm_buddy_test.c
53
num_blocks = mm_size / SZ_64K;
drivers/gpu/drm/tests/drm_buddy_test.c
58
KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, SZ_8K, SZ_64K,
drivers/gpu/drm/tests/drm_buddy_test.c
75
KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, SZ_64K, SZ_64K,
drivers/gpu/drm/tests/drm_buddy_test.c
77
"buddy_alloc hit an error size=%u\n", SZ_64K);
drivers/gpu/drm/v3d/v3d_bo.c
121
else if (obj->size >= SZ_64K)
drivers/gpu/drm/v3d/v3d_bo.c
122
align = SZ_64K;
drivers/gpu/drm/v3d/v3d_mmu.c
109
} else if (len >= SZ_64K &&
drivers/gpu/drm/v3d/v3d_mmu.c
110
v3d_mmu_is_aligned(page, page_address, SZ_64K)) {
drivers/gpu/drm/v3d/v3d_mmu.c
111
page_size = SZ_64K;
drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h
21
#define PXP_MAX_PACKET_SIZE SZ_64K
drivers/gpu/drm/xe/display/xe_fb_pin.c
241
align = max(align, SZ_64K);
drivers/gpu/drm/xe/display/xe_initial_plane.c
51
u64 page_size = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
drivers/gpu/drm/xe/tests/xe_dma_buf.c
127
size = SZ_64K;
drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c
62
KUNIT_EXPECT_EQ(test, GUC_ID_MAX + 1, SZ_64K);
drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c
79
KUNIT_EXPECT_EQ(test, SZ_64K - SZ_1K, pf_profile_fair_ctxs(gt, 1));
drivers/gpu/drm/xe/xe_bo.c
2164
size_t align = flags & XE_BO_FLAG_NEEDS_2M ? SZ_2M : SZ_64K;
drivers/gpu/drm/xe/xe_bo.c
3214
IS_ALIGNED(args->size, SZ_64K))
drivers/gpu/drm/xe/xe_bo.c
3636
xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K);
drivers/gpu/drm/xe/xe_ggtt.c
870
alignment = SZ_64K;
drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
434
return IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
drivers/gpu/drm/xe/xe_guc_ads.c
61
#define GUC_UM_QUEUE_SIZE (SZ_64K)
drivers/gpu/drm/xe/xe_guc_log.h
20
#define XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE SZ_64K
drivers/gpu/drm/xe/xe_lmtt.c
207
lmtt_assert(lmtt, IS_ALIGNED(offset, SZ_64K));
drivers/gpu/drm/xe/xe_lmtt.c
209
config = LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K);
drivers/gpu/drm/xe/xe_lmtt_2l.c
134
XE_WARN_ON(!IS_ALIGNED(offset, SZ_64K));
drivers/gpu/drm/xe/xe_lmtt_2l.c
135
XE_WARN_ON(!FIELD_FIT(LMTT_2L_PDE_LMTT_PTR, offset / SZ_64K));
drivers/gpu/drm/xe/xe_lmtt_2l.c
136
return FIELD_PREP(LMTT_2L_PDE_LMTT_PTR, offset / SZ_64K) | LMTT_2L_PDE_VALID;
drivers/gpu/drm/xe/xe_lmtt_2l.c
82
BUILD_BUG_ON(LMTT_2L_HAW == 37 && LMTT_2L_PTE_MAX_NUM != SZ_64K);
drivers/gpu/drm/xe/xe_lmtt_ml.c
145
XE_WARN_ON(!IS_ALIGNED(offset, SZ_64K));
drivers/gpu/drm/xe/xe_lmtt_ml.c
146
XE_WARN_ON(!FIELD_FIT(LMTT_ML_PDE_LMTT_PTR, offset / SZ_64K));
drivers/gpu/drm/xe/xe_lmtt_ml.c
147
return FIELD_PREP(LMTT_ML_PDE_LMTT_PTR, offset / SZ_64K) | LMTT_ML_PDE_VALID;
drivers/gpu/drm/xe/xe_migrate.c
203
BUILD_BUG_ON(NUM_PT_SLOTS * XE_PAGE_SIZE % SZ_64K);
drivers/gpu/drm/xe/xe_migrate.c
501
m->min_chunk_size = SZ_4K * SZ_64K /
drivers/gpu/drm/xe/xe_migrate.c
502
xe_device_ccs_bytes(xe, SZ_64K);
drivers/gpu/drm/xe/xe_migrate.c
505
m->min_chunk_size = SZ_64K;
drivers/gpu/drm/xe/xe_migrate.c
642
xe_assert(xe, (va & (SZ_64K - 1)) ==
drivers/gpu/drm/xe/xe_migrate.c
643
(addr & (SZ_64K - 1)));
drivers/gpu/drm/xe/xe_pt.c
1615
reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_64K); /* reclamation_size = 4 */
drivers/gpu/drm/xe/xe_pt.c
1616
xe_tile_assert(tile, phys_addr % SZ_64K == 0);
drivers/gpu/drm/xe/xe_pt.c
472
if (!IS_ALIGNED(addr, SZ_64K))
drivers/gpu/drm/xe/xe_pt.c
483
for (; addr < next; addr += SZ_64K) {
drivers/gpu/drm/xe/xe_pt.c
484
if (!IS_ALIGNED(xe_res_dma(&curs), SZ_64K) || curs.size < SZ_64K)
drivers/gpu/drm/xe/xe_pt.c
487
xe_res_next(&curs, SZ_64K);
drivers/gpu/drm/xe/xe_pt.c
505
if (xe_walk->found_64K && addr - xe_walk->addr_64K < SZ_64K)
drivers/gpu/drm/xe/xe_pt.c
508
xe_walk->found_64K = xe_pt_scan_64K(addr, addr + SZ_64K, xe_walk);
drivers/gpu/drm/xe/xe_query.c
287
SZ_64K : PAGE_SIZE;
drivers/gpu/drm/xe/xe_query.c
347
xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
drivers/gpu/drm/xe/xe_svm.c
1128
if (range_size < SZ_64K && !supports_4K_migration(vm->xe)) {
drivers/gpu/drm/xe/xe_svm.c
1144
case SZ_64K: \
drivers/gpu/drm/xe/xe_svm.c
1169
case SZ_64K: \
drivers/gpu/drm/xe/xe_svm.c
1194
.check_pages_threshold = devmem_possible ? SZ_64K : 0,
drivers/gpu/drm/xe/xe_svm.c
800
SZ_64K,
drivers/gpu/drm/xe/xe_vm.c
2504
return SZ_64K;
drivers/gpu/drm/xe/xe_vm.c
2520
case SZ_64K:
drivers/gpu/drm/xe/xe_vm.c
2939
ctx.check_pages_threshold = devmem_possible ? SZ_64K : 0;
drivers/gpu/drm/xe/xe_vram.c
99
offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
drivers/gpu/ipu-v3/ipu-ic.c
640
priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K);
drivers/i2c/busses/i2c-qup.c
127
#define MX_TX_RX_LEN SZ_64K
drivers/i2c/busses/i2c-tegra.c
1603
.max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
drivers/infiniband/hw/irdma/hw.c
22
.qplimit = SZ_64K,
drivers/infiniband/hw/mana/mana_ib.h
21
(SZ_4K | SZ_8K | SZ_16K | SZ_32K | SZ_64K | SZ_128K | SZ_256K | \
drivers/input/touchscreen/goodix_berlin_core.c
624
0, SZ_64K - 1, 0, 0);
drivers/input/touchscreen/goodix_berlin_core.c
626
0, SZ_64K - 1, 0, 0);
drivers/input/touchscreen/ili210x.c
1008
max_xy = (chip->resolution ?: SZ_64K) - 1;
drivers/input/touchscreen/ili210x.c
611
u8* fw_buf __free(kvfree) = kvmalloc(SZ_64K, GFP_KERNEL);
drivers/input/touchscreen/ili210x.c
621
if (fw_addr + fw_len > SZ_64K || fw_addr > SZ_64K - 32)
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
218
if (PAGE_SIZE != SZ_64K)
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
42
PAGE_SIZE == SZ_64K);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
43
if (PAGE_SIZE == SZ_64K)
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4527
smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4728
return SZ_64K;
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4864
if (arm_smmu_resource_size(smmu) > SZ_64K) {
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4865
smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
378
#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / sizeof(struct arm_smmu_cd))
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
1261
ret = iommufd_viommu_alloc_mmap(&vintf->vsmmu.core, page0_base, SZ_64K,
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
1266
data.out_vintf_mmap_length = SZ_64K;
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
19
#define TEGRA241_CMDQV_CONFIG_SIZE (SZ_64K)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
20
#define TEGRA241_VCMDQ_PAGE0_BASE (TEGRA241_CMDQV_CONFIG_BASE + SZ_64K)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
21
#define TEGRA241_VCMDQ_PAGE1_BASE (TEGRA241_VCMDQ_PAGE0_BASE + SZ_64K)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
22
#define TEGRA241_VINTF_PAGE_BASE (TEGRA241_VCMDQ_PAGE1_BASE + SZ_64K)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
93
#define TEGRA241_VINTFi_PAGE1(i) (TEGRA241_VINTFi_PAGE0(i) + SZ_64K)
drivers/iommu/arm/arm-smmu/arm-smmu.c
1918
smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
drivers/iommu/arm/arm-smmu/arm-smmu.c
1925
smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
drivers/iommu/io-pgtable-arm-selftests.c
159
SZ_64K | SZ_512M,
drivers/iommu/io-pgtable-arm-v7s.c
726
cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
drivers/iommu/io-pgtable-arm-v7s.c
820
.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
drivers/iommu/io-pgtable-arm.c
1001
case SZ_64K:
drivers/iommu/io-pgtable-arm.c
1108
case SZ_64K:
drivers/iommu/io-pgtable-arm.c
199
if (ARM_LPAE_GRANULE(data) < SZ_64K)
drivers/iommu/io-pgtable-arm.c
901
case SZ_64K:
drivers/iommu/io-pgtable-arm.c
903
page_sizes = (SZ_64K | SZ_512M);
drivers/iommu/io-pgtable-arm.c
924
if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
drivers/iommu/msm_iommu.c
34
#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
drivers/iommu/mtk_iommu.c
711
dom->domain.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M;
drivers/iommu/omap-iommu.c
40
#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
drivers/iommu/omap-iommu.h
212
((bytes) >= SZ_64K) ? SZ_64K : \
drivers/iommu/omap-iommu.h
218
((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
drivers/iommu/omap-iommu.h
224
((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
drivers/irqchip/irq-gic-v3-its.c
2413
if (psz != SZ_64K) {
drivers/irqchip/irq-gic-v3-its.c
2441
case SZ_64K:
drivers/irqchip/irq-gic-v3-its.c
2618
u64 psz = SZ_64K;
drivers/irqchip/irq-gic-v3-its.c
2627
case SZ_64K:
drivers/irqchip/irq-gic-v3-its.c
2648
case SZ_64K:
drivers/irqchip/irq-gic-v3-its.c
2861
psz = SZ_64K;
drivers/irqchip/irq-gic-v3-its.c
2903
unsigned int psz = SZ_64K;
drivers/irqchip/irq-gic-v3-its.c
2956
psz = SZ_64K;
drivers/irqchip/irq-gic-v3-its.c
5108
its_base = ioremap(res->start, SZ_64K);
drivers/irqchip/irq-gic-v3-its.c
5261
its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K);
drivers/irqchip/irq-gic-v3-its.c
539
#define ITS_CMD_QUEUE_SZ SZ_64K
drivers/irqchip/irq-gic-v3-its.c
65
#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
drivers/irqchip/irq-gic-v3-its.c
66
#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
drivers/irqchip/irq-gic-v3.c
1013
ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
drivers/irqchip/irq-gic-v3.c
1015
ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
drivers/irqchip/irq-gic-v3.c
1834
t241_dist_base_alias[i] = ioremap(phys, SZ_64K);
drivers/irqchip/irq-gic-v3.c
2320
u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
drivers/irqchip/irq-gic-v3.c
240
#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
drivers/irqchip/irq-gic-v3.c
2493
#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
drivers/irqchip/irq-gic-v5-irs.c
272
case SZ_64K:
drivers/irqchip/irq-gic-v5-irs.c
845
#define ACPI_GICV5_IRS_MEM_SIZE (SZ_64K)
drivers/irqchip/irq-gic-v5-its.c
1240
#define ACPI_GICV5_ITS_MEM_SIZE (SZ_64K)
drivers/irqchip/irq-gic-v5-its.c
303
case SZ_64K:
drivers/irqchip/irq-sa11x0.c
153
iobase = ioremap(io_start, SZ_64K);
drivers/mailbox/tegra-hsp.c
289
offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
drivers/mailbox/tegra-hsp.c
693
mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
drivers/media/pci/intel/ipu6/ipu6-cpd.c
34
#define MAX_METADATA_SIZE SZ_64K
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
23
#define VP8_PP_WRAPY_SZ SZ_64K
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
24
#define VP8_PP_WRAPC_SZ SZ_64K
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
25
#define VP8_VLD_PRED_SZ SZ_64K
drivers/media/platform/renesas/rcar_drif.c
121
#define RCAR_SDR_BUFFER_SIZE SZ_64K
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.c
39
unsigned int align = (SZ_64K >> PAGE_SHIFT) - 1;
drivers/misc/pci_endpoint_test.c
1366
.alignment = SZ_64K,
drivers/misc/pci_endpoint_test.c
1374
.alignment = SZ_64K,
drivers/mmc/core/sd.c
54
0, SZ_16K / 512, SZ_32K / 512, SZ_64K / 512,
drivers/mmc/host/sdhci.c
4201
bounce_size = SZ_64K;
drivers/mmc/host/tmio_mmc_core.c
789
if (host->mmc->max_blk_count >= SZ_64K)
drivers/mtd/parsers/bcm63xxpart.c
30
#define BCM963XX_CFE_BLOCK_SIZE SZ_64K /* always at least 64KiB */
drivers/mtd/spi-nor/core.h
19
#define SPI_NOR_DEFAULT_SECTOR_SIZE SZ_64K
drivers/mtd/spi-nor/issi.c
53
.size = SZ_64K,
drivers/mtd/spi-nor/issi.c
66
.size = SZ_64K,
drivers/mtd/spi-nor/macronix.c
103
.size = SZ_64K,
drivers/mtd/spi-nor/micron-st.c
255
.size = SZ_64K,
drivers/mtd/spi-nor/micron-st.c
286
.size = SZ_64K,
drivers/mtd/spi-nor/sst.c
79
.size = SZ_64K,
drivers/mtd/spi-nor/winbond.c
153
.size = SZ_64K,
drivers/net/ethernet/lantiq_xrx200.c
25
#define XRX200_DMA_DATA_LEN (SZ_64K - 1)
drivers/net/ethernet/marvell/mvneta.c
3480
mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
958
#define MVPP22_ADDR_SPACE_SZ SZ_64K
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
19
#define MBOX_SIZE SZ_64K
drivers/net/ethernet/meta/fbnic/fbnic_txrx.h
42
#define FBNIC_QUEUE_SIZE_MAX SZ_64K
drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h
19
#define NFDK_TX_MAX_DATA_PER_BLOCK SZ_64K
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1230
nfp_cpp_area_cache_add(cpp, SZ_64K);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1231
nfp_cpp_area_cache_add(cpp, SZ_64K);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_arm.h
149
#define NFP_ARM_GCSR_SIZE SZ_64K
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_arm.h
214
#define NFP_ARM_PCSR_SIZE SZ_64K
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c
16
.max_qc_size = SZ_64K,
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c
28
.max_qc_size = SZ_64K,
drivers/net/ethernet/ti/icssg/icssg_config.c
301
if (addr % SZ_64K) {
drivers/net/ethernet/ti/icssg/icssg_config.c
388
if (addr % SZ_64K) {
drivers/net/ethernet/ti/icssg/icssg_config.h
189
#define MSMC_RAM_SIZE_SR1 (SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */
drivers/net/ethernet/ti/icssg/icssg_prueth.c
1961
.align = SZ_64K,
drivers/net/ethernet/ti/icssm/icssm_prueth.c
1938
prueth->ocmc_ram_size = (SZ_64K - SZ_8K);
drivers/net/ethernet/ti/icssm/icssm_prueth.c
37
#define OCMC_RAM_SIZE (SZ_64K)
drivers/net/thunderbolt/main.c
40
#define TBNET_MAX_MTU SZ_64K
drivers/net/wireless/realtek/rtw88/sdio.c
1068
} while (total_rx_bytes < SZ_64K && hisr & REG_SDIO_HISR_RX_REQUEST);
drivers/ntb/hw/mscc/ntb_hw_switchtec.c
43
#define LUT_SIZE SZ_64K
drivers/pci/controller/dwc/pci-imx6.c
1440
.align = SZ_64K,
drivers/pci/controller/dwc/pci-imx6.c
1449
.align = SZ_64K,
drivers/pci/controller/dwc/pci-imx6.c
1467
.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
drivers/pci/controller/dwc/pci-keystone.c
107
#define AM654_WIN_SIZE SZ_64K
drivers/pci/controller/dwc/pci-keystone.c
939
.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
drivers/pci/controller/dwc/pci-keystone.c
942
.align = SZ_64K,
drivers/pci/controller/dwc/pcie-dw-rockchip.c
397
.align = SZ_64K,
drivers/pci/controller/dwc/pcie-dw-rockchip.c
418
.align = SZ_64K,
drivers/pci/controller/dwc/pcie-dw-rockchip.c
608
rockchip->pci.ep.page_size = SZ_64K;
drivers/pci/controller/dwc/pcie-stm32-ep.c
75
.align = SZ_64K,
drivers/pci/controller/dwc/pcie-tegra194.c
2001
.align = SZ_64K,
drivers/pci/controller/dwc/pcie-tegra194.c
2028
ep->page_size = SZ_64K;
drivers/pci/controller/pci-mvebu.c
1149
return round_up(start, max_t(resource_size_t, SZ_64K,
drivers/pci/controller/pci-mvebu.c
1432
IO_SPACE_LIMIT - SZ_64K,
drivers/pci/controller/pci-thunder-pem.c
404
resource_set_size(res_pem, SZ_64K);
drivers/perf/arm-cci.c
1495
.cntr_size = SZ_64K,
drivers/perf/arm-cci.c
1519
.cntr_size = SZ_64K,
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
146
lane->ctrl_off = SZ_64K;
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
150
lane->phy_off = SZ_64K;
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
167
lane->phy_off = SZ_64K;
drivers/remoteproc/ti_k3_r5_remoteproc.c
791
WARN_ON(kproc->mem[0].size != SZ_64K);
drivers/remoteproc/ti_k3_r5_remoteproc.c
792
WARN_ON(kproc->mem[1].size != SZ_64K);
drivers/scsi/elx/libefc_sli/sli4.c
336
page_size = SZ_64K;
drivers/soc/qcom/ocmem.c
68
#define OCMEM_MIN_ALIGN SZ_64K
drivers/soc/qcom/ocmem.c
69
#define OCMEM_MIN_ALLOC SZ_64K
drivers/spi/spi-axiado.c
730
if (op->data.nbytes > SZ_64K) {
drivers/spi/spi-axiado.c
731
op->data.nbytes = SZ_64K;
drivers/spi/spi-mt65xx.c
104
#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
drivers/spi/spi-pxa2xx.h
124
#define MAX_DMA_LEN SZ_64K
drivers/spi/spi-qup.c
118
#define SPI_MAX_XFER (SZ_64K - 64)
drivers/spi/spi-tegra210-quad.c
163
#define DEFAULT_QSPI_DMA_BUF_LEN SZ_64K
drivers/spi/spi-ti-qspi.c
124
#define QSPI_DMA_BUFFER_SIZE SZ_64K
drivers/staging/media/meson/vdec/vdec.c
37
return ALIGN(width * height, SZ_64K);
drivers/staging/media/meson/vdec/vdec_helpers.c
76
amvdec_am21c_head_size(width, height), SZ_64K);
drivers/ufs/host/ufs-hisi.c
340
ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), SZ_64K - 1);
drivers/ufs/host/ufs-hisi.c
346
ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), SZ_64K - 1);
drivers/ufs/host/ufs-hisi.c
352
ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), SZ_64K - 1);
drivers/ufs/host/ufs-hisi.c
358
ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), SZ_64K - 1);
drivers/usb/host/ohci-sa1111.c
224
ret = usb_hcd_setup_local_mem(hcd, 0, 0, SZ_64K);
fs/btrfs/ctree.c
1334
nread_max = SZ_64K;
fs/btrfs/extent-tree.c
2821
*empty_cluster = SZ_64K;
fs/btrfs/free-space-cache.c
35
#define MAX_CACHE_BYTES_PER_GIG SZ_64K
fs/btrfs/fs.h
64
#define BTRFS_MAX_BLOCKSIZE (SZ_64K)
fs/btrfs/fs.h
80
#define BTRFS_SUPER_INFO_OFFSET SZ_64K
fs/btrfs/inode.c
1487
inode_should_defrag(inode, start, end, num_bytes, SZ_64K);
fs/btrfs/inode.c
9443
if (fs_info->sectorsize < SZ_4K || fs_info->sectorsize > SZ_64K)
fs/btrfs/ioctl.c
3248
size = min_t(u32, loi->size, SZ_64K);
fs/btrfs/send.c
5956
const u64 sectorsize = SZ_64K;
fs/btrfs/send.h
30
#define BTRFS_SEND_BUF_SIZE_V1 SZ_64K
fs/btrfs/tests/extent-map-tests.c
692
end = SZ_64K - 1;
fs/btrfs/tests/raid-stripe-tree-tests.c
1004
u64 len = SZ_64K;
fs/btrfs/tests/raid-stripe-tree-tests.c
1015
bioc->size = SZ_64K;
fs/btrfs/tests/raid-stripe-tree-tests.c
1056
if (len != SZ_64K) {
fs/btrfs/tests/raid-stripe-tree-tests.c
1058
(u64)SZ_64K, len);
fs/btrfs/tests/raid-stripe-tree-tests.c
368
u64 hole_len = SZ_64K;
fs/btrfs/tests/raid-stripe-tree-tests.c
484
hole_start, hole_start + SZ_64K);
fs/btrfs/tests/raid-stripe-tree-tests.c
652
u64 len = SZ_64K;
fs/btrfs/tests/raid-stripe-tree-tests.c
699
if (len != SZ_64K) {
fs/btrfs/tests/raid-stripe-tree-tests.c
701
(u64)SZ_64K, len);
fs/btrfs/tests/raid-stripe-tree-tests.c
718
logical + SZ_16K, logical + SZ_64K);
fs/btrfs/tests/raid-stripe-tree-tests.c
761
u64 len = SZ_64K;
fs/btrfs/tests/raid-stripe-tree-tests.c
814
if (len != SZ_64K) {
fs/btrfs/tests/raid-stripe-tree-tests.c
816
(u64)SZ_64K, len);
fs/btrfs/tests/raid-stripe-tree-tests.c
824
logical + SZ_48K, logical + SZ_64K);
fs/btrfs/tests/raid-stripe-tree-tests.c
855
logical + SZ_48K, logical + SZ_64K);
fs/btrfs/tests/raid-stripe-tree-tests.c
883
u64 len = SZ_64K;
fs/btrfs/tests/raid-stripe-tree-tests.c
936
if (len != SZ_64K) {
fs/btrfs/tests/raid-stripe-tree-tests.c
938
(u64)SZ_64K, len);
fs/btrfs/tests/raid-stripe-tree-tests.c
976
if (len != SZ_64K) {
fs/btrfs/tests/raid-stripe-tree-tests.c
978
(u64)SZ_64K, len);
fs/btrfs/volumes.h
45
#define BTRFS_STRIPE_LEN SZ_64K
fs/nfs/dir.c
75
#define NFS_INIT_DTSIZE SZ_64K
fs/xfs/xfs_healthmon.c
59
#define XFS_HEALTHMON_MAX_OUTBUF SZ_64K
include/linux/blkdev.h
280
#define BLK_MAX_BLOCK_SIZE SZ_64K
include/linux/dma-mapping.h
653
return SZ_64K;
kernel/liveupdate/kexec_handover.c
1566
.buf_align = SZ_64K, /* Makes it easier to map */
lib/logic_pio.c
76
if (mmio_end + SZ_64K - 1 > MMIO_UPPER_LIMIT) {
lib/logic_pio.c
80
new_range->size = SZ_64K;
sound/soc/ti/udma-pcm.c
24
.period_bytes_max = SZ_64K,
tools/arch/arm64/include/uapi/asm/kvm.h
96
#define KVM_VGIC_V3_DIST_SIZE SZ_64K
tools/arch/arm64/include/uapi/asm/kvm.h
97
#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
tools/arch/arm64/include/uapi/asm/kvm.h
98
#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
tools/testing/memblock/tests/basic_api.c
752
.size = SZ_64K
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
104
gic_rdist_enable_lpis(test_data.lpi_prop_table, SZ_64K,
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
105
test_data.lpi_pend_tables + (cpuid * SZ_64K));
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
115
its_init(test_data.collection_table, SZ_64K,
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
116
test_data.device_table, SZ_64K,
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
117
test_data.cmdq_base, SZ_64K);
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
156
sz = (3 + test_data.nr_devices) * SZ_64K;
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
163
sz += (1 + test_data.nr_cpus) * SZ_64K;
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
188
size_t pages_per_64k = vm_calc_num_guest_pages(vm->mode, SZ_64K);
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
76
vm_paddr_t itt_base = test_data.itt_tables + (device_id * SZ_64K);
tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
79
itt_base, SZ_64K, true);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
31
#define sgi_base_from_redist(redist_base) (redist_base + SZ_64K)
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
56
return GICR_BASE_GVA + cpu * SZ_64K * 2;
tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c
62
baser = ((size / SZ_64K) - 1) |
tools/testing/selftests/kvm/lib/arm64/vgic.c
169
attr += SZ_64K;
tools/testing/selftests/kvm/memslot_perf_test.c
30
#define MEM_EXTRA_SIZE SZ_64K
tools/testing/selftests/kvm/memslot_perf_test.c
76
#define MEM_TEST_MOVE_SIZE (3 * SZ_64K)
tools/testing/selftests/kvm/memslot_perf_test.c
930
if (host_page_size > SZ_64K || guest_page_size > SZ_64K) {