PCI_COMMAND_MEMORY
*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MEMORY;
mcf_write32(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
if (value & PCI_COMMAND_MEMORY)
hi |= PCI_COMMAND_MEMORY;
hi &= ~PCI_COMMAND_MEMORY;
if (hi & PCI_COMMAND_MEMORY)
conf_data |= PCI_COMMAND_MEMORY;
if (value & PCI_COMMAND_MEMORY)
hi |= PCI_COMMAND_MEMORY;
hi &= ~PCI_COMMAND_MEMORY;
if (hi & PCI_COMMAND_MEMORY)
conf_data |= PCI_COMMAND_MEMORY;
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
__raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))
== (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
bit = PCI_COMMAND_MEMORY;
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
disabled = !(command & PCI_COMMAND_MEMORY);
if ((command & PCI_COMMAND_MEMORY) == 0)
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
cmdreg|PCI_COMMAND_MEMORY);
if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
disabled = !(command & PCI_COMMAND_MEMORY);
PCI_COMMAND_MEMORY |
PCI_COMMAND_MEMORY |
if (cmd & PCI_COMMAND_MEMORY)
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MEMORY;
cmd &= ~PCI_COMMAND_MEMORY;
if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
if (!(command & PCI_COMMAND_MEMORY))
if (!(command & PCI_COMMAND_MEMORY))
if (!(cmd & PCI_COMMAND_MEMORY)) {
cmd |= PCI_COMMAND_MEMORY;
cmd &= ~PCI_COMMAND_MEMORY;
cmd &= ~PCI_COMMAND_MEMORY;
cmd & ~PCI_COMMAND_MEMORY);
pci_cmd & ~PCI_COMMAND_MEMORY);
if (!(changed & PCI_COMMAND_MEMORY))
if (old & PCI_COMMAND_MEMORY) {
vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
| PCI_COMMAND_MEMORY
if (cmd & PCI_COMMAND_MEMORY) {
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY);
cmd = (cmd | PCI_COMMAND_MEMORY );
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
#define ALX_PCI_CMD (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
if (0 == (cmd & PCI_COMMAND_MEMORY))
cmd |= PCI_COMMAND_MEMORY;
if (!(pcicmd & PCI_COMMAND_MEMORY)) {
pci_cmd &= ~PCI_COMMAND_MEMORY;
cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
cpu_to_le32(PCI_COMMAND_MEMORY |
cpu_to_le32(PCI_COMMAND_MEMORY |
if (!(cmd & PCI_COMMAND_MEMORY)) {
cmd |= PCI_COMMAND_MEMORY;
if (!(cmd & PCI_COMMAND_MEMORY)) {
cmd |= PCI_COMMAND_MEMORY;
iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
val &= ~PCI_COMMAND_MEMORY;
val |= PCI_COMMAND_MEMORY;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
pcie_rc_cfg_wr_mask(pcie, PCI_COMMAND, PCI_COMMAND_MEMORY, 0);
value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
val |= PCI_COMMAND_MEMORY;
command &= ~PCI_COMMAND_MEMORY;
ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
cmd & ~PCI_COMMAND_MEMORY);
WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
command &= ~PCI_COMMAND_MEMORY;
#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
cmd &= ~PCI_COMMAND_MEMORY;
if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
return cmd & PCI_COMMAND_MEMORY;
if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
cmd & ~PCI_COMMAND_MEMORY);
cmd |= PCI_COMMAND_MEMORY;
pci_bits |= PCI_COMMAND_MEMORY;
if (pci_bits & PCI_COMMAND_MEMORY)
pci_bits |= PCI_COMMAND_MEMORY;
if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
if (boot_cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
if (cmd & PCI_COMMAND_MEMORY)
if (!(configbyte & PCI_COMMAND_MEMORY)) {
configbyte |= PCI_COMMAND_MEMORY;
PCI_COMMAND_MEMORY |
if (cmd_reg & PCI_COMMAND_MEMORY) {
if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
if ((rc != PCIBIOS_SUCCESSFUL || (!(pci_reg & PCI_COMMAND_MEMORY))) &&
if ((rc == PCIBIOS_SUCCESSFUL) && (pci_reg & PCI_COMMAND_MEMORY)) {
| PCI_COMMAND_MEMORY);
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
msg16 |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
if (!(byte & PCI_COMMAND_MEMORY)) {
byte |= PCI_COMMAND_MEMORY;
#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
cpu_to_le16(PCI_COMMAND_MEMORY);
(pdev->no_command_memory || (cmd & PCI_COMMAND_MEMORY));
tmp_val |= cmd & PCI_COMMAND_MEMORY;
phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
if (!(cmd & PCI_COMMAND_MEMORY))
cmd | PCI_COMMAND_MEMORY);
if (!(tmp & PCI_COMMAND_MEMORY)) {
tmp |= PCI_COMMAND_MEMORY;
if (cmd & PCI_COMMAND_MEMORY) {
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
if (dev->msi_enabled || !(cmd & PCI_COMMAND_MEMORY))
PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
PCI_COMMAND_MEMORY |
PCI_COMMAND_MEMORY |