// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * the OHCI Virtual Support Module of AMD CS5536
 *
 * Copyright (C) 2007 Lemote, Inc.
 * Author : jlliu, liujl@lemote.com
 *
 * Copyright (C) 2009 Lemote, Inc.
 * Author: Wu Zhangjin, wuzhangjin@gmail.com
 */

#include <cs5536/cs5536.h>
#include <cs5536/cs5536_pci.h>

void pci_ohci_write_reg(int reg, u32 value)
{
        u32 hi = 0, lo = value;

        switch (reg) {
        case PCI_COMMAND:
                _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
                if (value & PCI_COMMAND_MASTER)
                        hi |= PCI_COMMAND_MASTER;
                else
                        hi &= ~PCI_COMMAND_MASTER;

                if (value & PCI_COMMAND_MEMORY)
                        hi |= PCI_COMMAND_MEMORY;
                else
                        hi &= ~PCI_COMMAND_MEMORY;
                _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
                break;
        case PCI_STATUS:
                if (value & PCI_STATUS_PARITY) {
                        _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
                        if (lo & SB_PARE_ERR_FLAG) {
                                lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
                                _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
                        }
                }
                break;
        case PCI_BAR0_REG:
                if (value == PCI_BAR_RANGE_MASK) {
                        _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
                        lo |= SOFT_BAR_OHCI_FLAG;
                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
                } else if ((value & 0x01) == 0x00) {
                        _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
                        lo = value;
                        _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);

                        value &= 0xfffffff0;
                        hi = 0x40000000 | ((value & 0xff000000) >> 24);
                        lo = 0x000fffff | ((value & 0x00fff000) << 8);
                        _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
                }
                break;
        case PCI_OHCI_INT_REG:
                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
                lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
                if (value)      /* enable all the usb interrupt in PIC */
                        lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
                _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
                break;
        default:
                break;
        }
}

u32 pci_ohci_read_reg(int reg)
{
        u32 conf_data = 0;
        u32 hi, lo;

        switch (reg) {
        case PCI_VENDOR_ID:
                conf_data =
                    CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
                break;
        case PCI_COMMAND:
                _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
                if (hi & PCI_COMMAND_MASTER)
                        conf_data |= PCI_COMMAND_MASTER;
                if (hi & PCI_COMMAND_MEMORY)
                        conf_data |= PCI_COMMAND_MEMORY;
                break;
        case PCI_STATUS:
                conf_data |= PCI_STATUS_66MHZ;
                conf_data |= PCI_STATUS_FAST_BACK;
                _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
                if (lo & SB_PARE_ERR_FLAG)
                        conf_data |= PCI_STATUS_PARITY;
                conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
                break;
        case PCI_CLASS_REVISION:
                _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
                conf_data = lo & 0x000000ff;
                conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
                break;
        case PCI_CACHE_LINE_SIZE:
                conf_data =
                    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
                                            PCI_NORMAL_LATENCY_TIMER);
                break;
        case PCI_BAR0_REG:
                _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
                if (lo & SOFT_BAR_OHCI_FLAG) {
                        conf_data = CS5536_OHCI_RANGE |
                            PCI_BASE_ADDRESS_SPACE_MEMORY;
                        lo &= ~SOFT_BAR_OHCI_FLAG;
                        _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
                } else {
                        _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
                        conf_data = lo & 0xffffff00;
                        conf_data &= ~0x0000000f;       /* 32bit mem */
                }
                break;
        case PCI_CARDBUS_CIS:
                conf_data = PCI_CARDBUS_CIS_POINTER;
                break;
        case PCI_SUBSYSTEM_VENDOR_ID:
                conf_data =
                    CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
                break;
        case PCI_ROM_ADDRESS:
                conf_data = PCI_EXPANSION_ROM_BAR;
                break;
        case PCI_CAPABILITY_LIST:
                conf_data = PCI_CAPLIST_USB_POINTER;
                break;
        case PCI_INTERRUPT_LINE:
                conf_data =
                    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
                break;
        case PCI_OHCI_INT_REG:
                _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
                if (((lo >> PIC_YSEL_LOW_USB_SHIFT) & 0xf) == CS5536_USB_INTR)
                        conf_data = 1;
                break;
        default:
                break;
        }

        return conf_data;
}