DMA_COMPLETE
if (dma_wait_for_async_tx(depend_tx) != DMA_COMPLETE)
if (dma_wait_for_async_tx(*tx) != DMA_COMPLETE)
if (status != DMA_COMPLETE)
if (status == DMA_ERROR || status == DMA_COMPLETE)
if (status != DMA_ERROR && status != DMA_COMPLETE &&
desc->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE) {
NULL, NULL) != DMA_COMPLETE)
if (ret == DMA_COMPLETE)
if (ret != DMA_COMPLETE) {
if (desc->status != DMA_COMPLETE) {
desc->status = DMA_COMPLETE;
if (desc->status != DMA_COMPLETE) {
desc->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE || !txstate)
dch->status = DMA_COMPLETE;
dch->status = DMA_COMPLETE;
if (dma_status == DMA_COMPLETE || !txstate)
if (ret == DMA_COMPLETE || !txstate)
if (ret == DMA_COMPLETE)
if (ret == DMA_COMPLETE || !txstate)
if ((status == DMA_COMPLETE) || (txstate == NULL))
return DMA_COMPLETE;
if (status == DMA_COMPLETE)
} else if (status != DMA_COMPLETE &&
if (status == DMA_COMPLETE || !txstate)
} else if (dw_edma_core_ch_status(chan) == DMA_COMPLETE) {
if (ret == DMA_COMPLETE)
return DMA_COMPLETE;
return DMA_COMPLETE;
if (ret == DMA_COMPLETE)
if (ret == DMA_COMPLETE)
fsl_chan->status = DMA_COMPLETE;
if (status == DMA_COMPLETE)
fsl_chan->status = DMA_COMPLETE;
fsl_comp->qchan->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
desc->status = DMA_COMPLETE;
if (status == DMA_COMPLETE)
desc->status = DMA_COMPLETE;
if (status == DMA_COMPLETE)
if (ret == DMA_COMPLETE)
desc->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE || !txstate)
sdmac->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
!= DMA_COMPLETE) {
dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
if (ret == DMA_COMPLETE)
enum dma_status status = DMA_COMPLETE;
if (status == DMA_COMPLETE)
desc->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE || !txstate)
if (ret == DMA_COMPLETE || !txstate)
if (stat == DMA_COMPLETE || !txstate)
tdmac->status = DMA_COMPLETE;
tdmac->status = DMA_COMPLETE;
if (tdmac->status != DMA_COMPLETE) {
tdmac->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
DMA_COMPLETE) {
DMA_COMPLETE) {
mxs_chan->status = DMA_COMPLETE;
mxs_chan->status = DMA_COMPLETE;
} else if (mxs_chan->status != DMA_COMPLETE) {
mxs_chan->status = DMA_COMPLETE;
if (mxs_chan->status == DMA_COMPLETE) {
if (ret == DMA_COMPLETE || !state)
if (ret == DMA_COMPLETE)
ret = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
if (ret == DMA_COMPLETE)
if (ret == DMA_COMPLETE)
if (llstat == DMA_COMPLETE) {
if (ret == DMA_COMPLETE) {
ret = DMA_COMPLETE;
if (ret == DMA_COMPLETE || !txstate)
if (ret == DMA_COMPLETE)
chan->status = DMA_COMPLETE;
if (status == DMA_COMPLETE)
if (status == DMA_COMPLETE || !txstate)
return DMA_COMPLETE;
if (status != DMA_COMPLETE) {
if (status == DMA_COMPLETE)
if (ret == DMA_COMPLETE || !txstate)
fchan->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE || !txstate)
if (ret != DMA_COMPLETE && txstate)
if (status == DMA_COMPLETE)
chan->status = DMA_COMPLETE;
chan->status = DMA_COMPLETE;
if (status == DMA_COMPLETE)
chan->dma_status = DMA_COMPLETE;
if ((status == DMA_COMPLETE) || (!state))
if (!state || (ret == DMA_COMPLETE))
if (ret == DMA_COMPLETE || !state)
tdc->status = DMA_COMPLETE;
tdc->status = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
dma_desc->dma_status = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
if (ret == DMA_COMPLETE || !txstate)
if (ret == DMA_COMPLETE)
if (ret != DMA_COMPLETE && !txstate->residue &&
ret = DMA_COMPLETE;
ret = DMA_COMPLETE;
if (ret == DMA_COMPLETE || !txstate)
ret = DMA_COMPLETE;
ret = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
ret = DMA_COMPLETE;
if (ret == DMA_COMPLETE)
return DMA_COMPLETE;
if (stat == DMA_COMPLETE || !txstate)
if (ret == DMA_COMPLETE)
if (ret == DMA_COMPLETE || !txstate)
if (status != DMA_COMPLETE)
last_status != DMA_COMPLETE) {
case DMA_COMPLETE:
} else if (status != DMA_COMPLETE) {
if (status == DMA_COMPLETE)
if (likely(status == DMA_COMPLETE)) {
if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
if (likely(status == DMA_COMPLETE)) {
} while (status != DMA_COMPLETE && status != DMA_ERROR &&
if (dma_sync_wait(chan, cookie) != DMA_COMPLETE) {
if (epf_test->transfer_status == DMA_COMPLETE ||
if (req->status != DMA_COMPLETE) {
if (req->status != DMA_COMPLETE) {
desc->status = DMA_COMPLETE;
if (state == DMA_COMPLETE) {
if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != DMA_COMPLETE)
if (status == DMA_COMPLETE) {
if (status == DMA_COMPLETE) {
if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
if (status != DMA_COMPLETE) {
return DMA_COMPLETE;
return DMA_COMPLETE;
return DMA_COMPLETE;
return DMA_COMPLETE;
ret = (status == DMA_COMPLETE) ? 0 : -EPROTO;