arch/alpha/include/asm/core_wildfire.h

63

wildfire_64 scratch[4];

arch/alpha/kernel/err_marvel.c

153

int scratch, i;

arch/alpha/kernel/err_marvel.c

198

scratch = EXTRACT(uncrr_sym, IO7__PO7_UNCRR_SYM__CLK);

arch/alpha/kernel/err_marvel.c

199

for (i = 0; i < 4; i++, scratch >>= 2) {

arch/alpha/kernel/err_marvel.c

200

if (scratch & 0x3)

arch/alpha/kernel/err_marvel.c

203

clk_names[i], clk_decode[scratch & 0x3]);

arch/alpha/kernel/err_marvel.c

232

if ((scratch = EXTRACT(uncrr_sym, IO7__PO7_UNCRR_SYM__VICTIM_SP))) {

arch/alpha/kernel/err_marvel.c

233

int lost = scratch & (1UL << 4);

arch/alpha/kernel/err_marvel.c

234

scratch &= ~lost;

arch/alpha/kernel/err_marvel.c

235

for (i = 0; i < 8; i++, scratch >>= 1) {

arch/alpha/kernel/err_marvel.c

236

if (!(scratch & 1))

arch/alpha/kernel/err_marvel.c

246

if ((scratch = EXTRACT(uncrr_sym, IO7__PO7_UNCRR_SYM__DETECT_SP))) {

arch/alpha/kernel/err_marvel.c

247

for (i = 0; i < 8; i++, scratch >>= 1) {

arch/alpha/kernel/err_marvel.c

248

if (!(scratch & 1))

arch/alpha/kernel/err_marvel.c

258

scratch = EXTRACT(uncrr_sym, IO7__PO7_UNCRR_SYM__STRV_VTR);

arch/alpha/kernel/err_marvel.c

259

if (scratch & IO7__STRV_VTR__IS_MSI)

arch/alpha/kernel/err_marvel.c

262

EXTRACT(scratch, IO7__STRV_VTR__MSI__INTNUM));

arch/alpha/kernel/err_marvel.c

266

'A' + EXTRACT(scratch,

arch/alpha/kernel/err_marvel.c

268

EXTRACT(scratch, IO7__STRV_VTR__LSI__BUS),

arch/alpha/kernel/err_marvel.c

269

EXTRACT(scratch, IO7__STRV_VTR__LSI__SLOT));

arch/arc/include/asm/entry-arcv2.h

89

; _HARD saves r10 clobbered by _SOFT as scratch hence comes first

arch/arc/include/asm/irqflags-arcv2.h

163

.macro IRQ_DISABLE scratch

arch/arc/include/asm/irqflags-arcv2.h

168

.macro IRQ_ENABLE scratch

arch/arc/include/asm/irqflags-compact.h

185

.macro IRQ_DISABLE scratch

arch/arc/include/asm/irqflags-compact.h

192

.macro IRQ_ENABLE scratch

arch/arc/include/uapi/asm/ptrace.h

42

} scratch;

arch/arc/kernel/ptrace.c

192

REG_IN_ONE(scratch.bta, &ptregs->bta);

arch/arc/kernel/ptrace.c

193

REG_IN_ONE(scratch.lp_start, &ptregs->lp_start);

arch/arc/kernel/ptrace.c

194

REG_IN_ONE(scratch.lp_end, &ptregs->lp_end);

arch/arc/kernel/ptrace.c

195

REG_IN_ONE(scratch.lp_count, &ptregs->lp_count);

arch/arc/kernel/ptrace.c

197

REG_IGNORE_ONE(scratch.status32);

arch/arc/kernel/ptrace.c

199

REG_IN_ONE(scratch.ret, &ptregs->ret);

arch/arc/kernel/ptrace.c

200

REG_IN_ONE(scratch.blink, &ptregs->blink);

arch/arc/kernel/ptrace.c

201

REG_IN_ONE(scratch.fp, &ptregs->fp);

arch/arc/kernel/ptrace.c

202

REG_IN_ONE(scratch.gp, &ptregs->r26);

arch/arc/kernel/ptrace.c

203

REG_IN_ONE(scratch.r12, &ptregs->r12);

arch/arc/kernel/ptrace.c

204

REG_IN_ONE(scratch.r11, &ptregs->r11);

arch/arc/kernel/ptrace.c

205

REG_IN_ONE(scratch.r10, &ptregs->r10);

arch/arc/kernel/ptrace.c

206

REG_IN_ONE(scratch.r9, &ptregs->r9);

arch/arc/kernel/ptrace.c

207

REG_IN_ONE(scratch.r8, &ptregs->r8);

arch/arc/kernel/ptrace.c

208

REG_IN_ONE(scratch.r7, &ptregs->r7);

arch/arc/kernel/ptrace.c

209

REG_IN_ONE(scratch.r6, &ptregs->r6);

arch/arc/kernel/ptrace.c

210

REG_IN_ONE(scratch.r5, &ptregs->r5);

arch/arc/kernel/ptrace.c

211

REG_IN_ONE(scratch.r4, &ptregs->r4);

arch/arc/kernel/ptrace.c

212

REG_IN_ONE(scratch.r3, &ptregs->r3);

arch/arc/kernel/ptrace.c

213

REG_IN_ONE(scratch.r2, &ptregs->r2);

arch/arc/kernel/ptrace.c

214

REG_IN_ONE(scratch.r1, &ptregs->r1);

arch/arc/kernel/ptrace.c

215

REG_IN_ONE(scratch.r0, &ptregs->r0);

arch/arc/kernel/ptrace.c

216

REG_IN_ONE(scratch.sp, &ptregs->sp);

arch/arc/kernel/signal.c

108

uregs.scratch.bta = regs->bta;

arch/arc/kernel/signal.c

109

uregs.scratch.lp_start = regs->lp_start;

arch/arc/kernel/signal.c

110

uregs.scratch.lp_end = regs->lp_end;

arch/arc/kernel/signal.c

111

uregs.scratch.lp_count = regs->lp_count;

arch/arc/kernel/signal.c

112

uregs.scratch.status32 = regs->status32;

arch/arc/kernel/signal.c

113

uregs.scratch.ret = regs->ret;

arch/arc/kernel/signal.c

114

uregs.scratch.blink = regs->blink;

arch/arc/kernel/signal.c

115

uregs.scratch.fp = regs->fp;

arch/arc/kernel/signal.c

116

uregs.scratch.gp = regs->r26;

arch/arc/kernel/signal.c

117

uregs.scratch.r12 = regs->r12;

arch/arc/kernel/signal.c

118

uregs.scratch.r11 = regs->r11;

arch/arc/kernel/signal.c

119

uregs.scratch.r10 = regs->r10;

arch/arc/kernel/signal.c

120

uregs.scratch.r9 = regs->r9;

arch/arc/kernel/signal.c

121

uregs.scratch.r8 = regs->r8;

arch/arc/kernel/signal.c

122

uregs.scratch.r7 = regs->r7;

arch/arc/kernel/signal.c

123

uregs.scratch.r6 = regs->r6;

arch/arc/kernel/signal.c

124

uregs.scratch.r5 = regs->r5;

arch/arc/kernel/signal.c

125

uregs.scratch.r4 = regs->r4;

arch/arc/kernel/signal.c

126

uregs.scratch.r3 = regs->r3;

arch/arc/kernel/signal.c

127

uregs.scratch.r2 = regs->r2;

arch/arc/kernel/signal.c

128

uregs.scratch.r1 = regs->r1;

arch/arc/kernel/signal.c

129

uregs.scratch.r0 = regs->r0;

arch/arc/kernel/signal.c

130

uregs.scratch.sp = regs->sp;

arch/arc/kernel/signal.c

132

err = __copy_to_user(&(sf->uc.uc_mcontext.regs.scratch), &uregs.scratch,

arch/arc/kernel/signal.c

133

sizeof(sf->uc.uc_mcontext.regs.scratch));

arch/arc/kernel/signal.c

150

err |= __copy_from_user(&uregs.scratch,

arch/arc/kernel/signal.c

151

&(sf->uc.uc_mcontext.regs.scratch),

arch/arc/kernel/signal.c

152

sizeof(sf->uc.uc_mcontext.regs.scratch));

arch/arc/kernel/signal.c

161

regs->bta = uregs.scratch.bta;

arch/arc/kernel/signal.c

162

regs->lp_start = uregs.scratch.lp_start;

arch/arc/kernel/signal.c

163

regs->lp_end = uregs.scratch.lp_end;

arch/arc/kernel/signal.c

164

regs->lp_count = uregs.scratch.lp_count;

arch/arc/kernel/signal.c

165

regs->status32 = uregs.scratch.status32;

arch/arc/kernel/signal.c

166

regs->ret = uregs.scratch.ret;

arch/arc/kernel/signal.c

167

regs->blink = uregs.scratch.blink;

arch/arc/kernel/signal.c

168

regs->fp = uregs.scratch.fp;

arch/arc/kernel/signal.c

169

regs->r26 = uregs.scratch.gp;

arch/arc/kernel/signal.c

170

regs->r12 = uregs.scratch.r12;

arch/arc/kernel/signal.c

171

regs->r11 = uregs.scratch.r11;

arch/arc/kernel/signal.c

172

regs->r10 = uregs.scratch.r10;

arch/arc/kernel/signal.c

173

regs->r9 = uregs.scratch.r9;

arch/arc/kernel/signal.c

174

regs->r8 = uregs.scratch.r8;

arch/arc/kernel/signal.c

175

regs->r7 = uregs.scratch.r7;

arch/arc/kernel/signal.c

176

regs->r6 = uregs.scratch.r6;

arch/arc/kernel/signal.c

177

regs->r5 = uregs.scratch.r5;

arch/arc/kernel/signal.c

178

regs->r4 = uregs.scratch.r4;

arch/arc/kernel/signal.c

179

regs->r3 = uregs.scratch.r3;

arch/arc/kernel/signal.c

180

regs->r2 = uregs.scratch.r2;

arch/arc/kernel/signal.c

181

regs->r1 = uregs.scratch.r1;

arch/arc/kernel/signal.c

182

regs->r0 = uregs.scratch.r0;

arch/arc/kernel/signal.c

183

regs->sp = uregs.scratch.sp;

arch/arm/probes/decode.c

33

int addr, scratch, ret;

arch/arm/probes/decode.c

40

: [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));

arch/mips/ath25/ar5312.c

286

u32 scratch, devid, clock_ctl1;

arch/mips/ath25/ar5312.c

292

scratch = ar5312_rst_reg_read(AR5312_SCRATCH);

arch/mips/ath25/ar5312.c

293

if (scratch)

arch/mips/ath25/ar5312.c

294

return scratch;

arch/mips/mm/tlbex.c

1056

const int scratch = 1; /* Our extra working register */

arch/mips/mm/tlbex.c

1058

rv.huge_pte = scratch;

arch/mips/mm/tlbex.c

1071

UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);

arch/mips/mm/tlbex.c

1073

UASM_i_SW(p, scratch, scratchpad_offset(0), 0);

arch/mips/mm/tlbex.c

1075

uasm_i_dsrl_safe(p, scratch, tmp,

arch/mips/mm/tlbex.c

1077

uasm_il_bnez(p, r, scratch, label_vmalloc);

arch/mips/mm/tlbex.c

1093

UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);

arch/mips/mm/tlbex.c

1095

UASM_i_SW(p, scratch, scratchpad_offset(0), 0);

arch/mips/mm/tlbex.c

1113

#define LOC_PTEP scratch

arch/mips/mm/tlbex.c

1120

uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);

arch/mips/mm/tlbex.c

1132

uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);

arch/mips/mm/tlbex.c

1137

uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);

arch/mips/mm/tlbex.c

1140

UASM_i_LWX(p, LOC_PTEP, scratch, ptr);

arch/mips/mm/tlbex.c

1142

uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */

arch/mips/mm/tlbex.c

1148

uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);

arch/mips/mm/tlbex.c

1149

uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);

arch/mips/mm/tlbex.c

1152

UASM_i_LWX(p, ptr, scratch, ptr);

arch/mips/mm/tlbex.c

1154

uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */

arch/mips/mm/tlbex.c

1163

uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);

arch/mips/mm/tlbex.c

1164

uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);

arch/mips/mm/tlbex.c

1168

UASM_i_LWX(p, scratch, scratch, ptr);

arch/mips/mm/tlbex.c

1170

uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */

arch/mips/mm/tlbex.c

1171

UASM_i_LW(p, scratch, 0, ptr);

arch/mips/mm/tlbex.c

1178

uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);

arch/mips/mm/tlbex.c

1193

UASM_i_LWX(p, even, scratch, tmp);

arch/mips/mm/tlbex.c

1195

UASM_i_LWX(p, odd, scratch, tmp);

arch/mips/mm/tlbex.c

1197

UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */

arch/mips/mm/tlbex.c

1216

UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);

arch/mips/mm/tlbex.c

1223

UASM_i_LW(p, scratch, scratchpad_offset(0), 0);

arch/mips/mm/tlbex.c

1225

UASM_i_LW(p, scratch, scratchpad_offset(0), 0);

arch/mips/mm/tlbex.c

1636

unsigned int mode, unsigned int scratch)

arch/mips/mm/tlbex.c

1642

uasm_i_lui(p, scratch, swmode >> 16);

arch/mips/mm/tlbex.c

1643

uasm_i_or(p, pte, pte, scratch);

arch/mips/mm/tlbex.c

1704

int pte, int ptr, int scratch, enum label_id lid)

arch/mips/mm/tlbex.c

1706

int t = scratch >= 0 ? scratch : pte;

arch/mips/mm/tlbex.c

1742

unsigned int ptr, unsigned int scratch)

arch/mips/mm/tlbex.c

1746

iPTE_SW(p, r, pte, ptr, mode, scratch);

arch/mips/mm/tlbex.c

1755

unsigned int pte, unsigned int ptr, int scratch,

arch/mips/mm/tlbex.c

1758

int t = scratch >= 0 ? scratch : pte;

arch/mips/mm/tlbex.c

1782

unsigned int ptr, unsigned int scratch)

arch/mips/mm/tlbex.c

1787

iPTE_SW(p, r, pte, ptr, mode, scratch);

arch/mips/mm/tlbex.c

1796

unsigned int pte, unsigned int ptr, int scratch,

arch/mips/mm/tlbex.c

1803

int t = scratch >= 0 ? scratch : pte;

arch/powerpc/include/asm/ppc_asm.h

509

#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \

arch/powerpc/include/asm/ppc_asm.h

510

lis scratch,0x60000000@h; \

arch/powerpc/include/asm/ppc_asm.h

513

dcbt 0,scratch,0b01010; \

arch/powerpc/include/asm/ppc_asm.h

516

#define DCBT_SETUP_STREAMS(from, from_parms, to, to_parms, scratch) \

arch/powerpc/include/asm/ppc_asm.h

517

lis scratch,0x8000; /* GO=1 */ \

arch/powerpc/include/asm/ppc_asm.h

518

clrldi scratch,scratch,32; \

arch/powerpc/include/asm/ppc_asm.h

528

dcbt 0,scratch,0b01010; /* all streams GO */ \

arch/powerpc/platforms/powermac/low_i2c.c

1230

u8 scratch[MAX_I2C_DATA];

arch/powerpc/platforms/powermac/low_i2c.c

1308

inst->scratch[i] = (inst->buffer[i] & mask[i]) | val[i];

arch/powerpc/platforms/powermac/low_i2c.c

1311

inst->scratch[i] = (inst->buffer[i] & ~mask[i])

arch/powerpc/platforms/powermac/low_i2c.c

1329

inst->scratch, totallen);

arch/powerpc/platforms/powermac/low_i2c.c

1370

subaddr, inst->scratch, totallen);

arch/riscv/kernel/module-sections.c

121

Elf_Rela *scratch = NULL;

arch/riscv/kernel/module-sections.c

169

scratch_size_needed = (num_scratch_relas + num_relas) * sizeof(*scratch);

arch/riscv/kernel/module-sections.c

172

new_scratch = kvrealloc(scratch, scratch_size, GFP_KERNEL);

arch/riscv/kernel/module-sections.c

174

kvfree(scratch);

arch/riscv/kernel/module-sections.c

177

scratch = new_scratch;

arch/riscv/kernel/module-sections.c

182

scratch[num_scratch_relas++] = relas[j];

arch/riscv/kernel/module-sections.c

185

if (scratch) {

arch/riscv/kernel/module-sections.c

187

sort(scratch, num_scratch_relas, sizeof(*scratch), cmp_rela, NULL);

arch/riscv/kernel/module-sections.c

188

count_max_entries(scratch, num_scratch_relas, &num_plts, &num_gots);

arch/riscv/kernel/module-sections.c

189

kvfree(scratch);

arch/sparc/include/asm/winmacro.h

100

STORE_WINDOW(scratch + TI_REG_WINDOW); \

arch/sparc/include/asm/winmacro.h

101

sub %scratch, %cur_reg, %scratch; \

arch/sparc/include/asm/winmacro.h

102

srl %scratch, 6, %scratch; \

arch/sparc/include/asm/winmacro.h

103

add %scratch, 1, %scratch; \

arch/sparc/include/asm/winmacro.h

104

st %scratch, [%cur_reg + TI_W_SAVED];

arch/sparc/include/asm/winmacro.h

50

#define LOAD_PT_YREG(base_reg, scratch) \

arch/sparc/include/asm/winmacro.h

51

ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \

arch/sparc/include/asm/winmacro.h

52

wr %scratch, 0x0, %y;

arch/sparc/include/asm/winmacro.h

59

#define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \

arch/sparc/include/asm/winmacro.h

60

LOAD_PT_YREG(base_reg, scratch) \

arch/sparc/include/asm/winmacro.h

77

#define STORE_PT_YREG(base_reg, scratch) \

arch/sparc/include/asm/winmacro.h

78

rd %y, %scratch; \

arch/sparc/include/asm/winmacro.h

79

st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];

arch/sparc/include/asm/winmacro.h

92

#define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \

arch/sparc/include/asm/winmacro.h

93

ld [%cur_reg + TI_W_SAVED], %scratch; \

arch/sparc/include/asm/winmacro.h

94

sll %scratch, 2, %scratch; \

arch/sparc/include/asm/winmacro.h

95

add %scratch, %cur_reg, %scratch; \

arch/sparc/include/asm/winmacro.h

96

st %sp, [%scratch + TI_RWIN_SPTRS]; \

arch/sparc/include/asm/winmacro.h

97

sub %scratch, %cur_reg, %scratch; \

arch/sparc/include/asm/winmacro.h

98

sll %scratch, 4, %scratch; \

arch/sparc/include/asm/winmacro.h

99

add %scratch, %cur_reg, %scratch; \

arch/x86/include/asm/bootparam_utils.h

52

static struct boot_params scratch;

arch/x86/include/asm/bootparam_utils.h

54

char *save_base = (char *)&scratch;

arch/x86/include/asm/bootparam_utils.h

68

BOOT_PARAM_PRESERVE(scratch),

arch/x86/include/asm/bootparam_utils.h

80

memset(&scratch, 0, sizeof(scratch));

arch/x86/include/uapi/asm/bootparam.h

136

__u32 scratch; /* Scratch field! */ /* 0x1e4 */

arch/x86/kernel/amd_gart_64.c

718

unsigned long scratch;

arch/x86/kernel/amd_gart_64.c

806

scratch = get_zeroed_page(GFP_KERNEL);

arch/x86/kernel/amd_gart_64.c

807

if (!scratch)

arch/x86/kernel/amd_gart_64.c

809

gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));

arch/x86/kernel/asm-offsets.c

100

OFFSET(BP_scratch, boot_params, scratch);

arch/x86/kernel/kexec-bzimage64.c

288

if (!image->kho.fdt || !image->kho.scratch)

arch/x86/kernel/kexec-bzimage64.c

294

kho->scratch_addr = image->kho.scratch->mem;

arch/x86/kernel/kexec-bzimage64.c

295

kho->scratch_size = image->kho.scratch->bufsz;

crypto/scompress.c

100

struct scomp_scratch *scratch;

crypto/scompress.c

102

scratch = per_cpu_ptr(&scomp_scratch, cpu);

crypto/scompress.c

103

if (context_unsafe(scratch->src))

crypto/scompress.c

105

if (scomp_alloc_scratch(scratch, cpu))

crypto/scompress.c

116

struct scomp_scratch *scratch;

crypto/scompress.c

118

scratch = per_cpu_ptr(&scomp_scratch, i);

crypto/scompress.c

119

return scomp_alloc_scratch(scratch, i);

crypto/scompress.c

146

struct scomp_scratch *scratch;

crypto/scompress.c

148

scratch = per_cpu_ptr(&scomp_scratch, cpu);

crypto/scompress.c

149

spin_lock(&scratch->lock);

crypto/scompress.c

150

if (likely(scratch->src))

crypto/scompress.c

151

return scratch;

crypto/scompress.c

152

spin_unlock(&scratch->lock);

crypto/scompress.c

157

scratch = per_cpu_ptr(&scomp_scratch, cpumask_first(cpu_possible_mask));

crypto/scompress.c

158

spin_lock(&scratch->lock);

crypto/scompress.c

159

return scratch;

crypto/scompress.c

162

static inline void scomp_unlock_scratch(struct scomp_scratch *scratch)

crypto/scompress.c

163

__releases(&scratch->lock)

crypto/scompress.c

165

spin_unlock(&scratch->lock);

crypto/scompress.c

237

struct scomp_scratch *scratch = scomp_lock_scratch();

crypto/scompress.c

238

const u8 *src = scratch->src;

crypto/scompress.c

240

memcpy_from_sglist(scratch->src, req->src, 0, slen);

crypto/scompress.c

249

scomp_unlock_scratch(scratch);

crypto/scompress.c

70

struct scomp_scratch *scratch;

crypto/scompress.c

74

scratch = per_cpu_ptr(&scomp_scratch, i);

crypto/scompress.c

76

free_page(scratch->saddr);

crypto/scompress.c

77

scratch->src = NULL;

crypto/scompress.c

81

static int scomp_alloc_scratch(struct scomp_scratch *scratch, int cpu)

crypto/scompress.c

89

spin_lock_bh(&scratch->lock);

crypto/scompress.c

90

scratch->src = page_address(page);

crypto/scompress.c

91

spin_unlock_bh(&scratch->lock);

drivers/ata/pata_parport/bpck.c

475

char scratch[128];

drivers/ata/pata_parport/bpck.c

477

bpck_read_eeprom(pi,scratch);

drivers/ata/pata_parport/bpck.c

478

print_hex_dump_bytes("bpck EEPROM: ", DUMP_PREFIX_NONE, scratch, 128);

drivers/ata/pata_parport/bpck.c

481

&scratch[110], pi->unit, pi->port, pi->mode,

drivers/ata/pata_parport/epat.c

276

char scratch[512];

drivers/ata/pata_parport/epat.c

297

epat_read_block(pi, scratch, 512);

drivers/ata/pata_parport/epat.c

300

if ((scratch[2 * k] & 0xff) != k)

drivers/ata/pata_parport/epat.c

302

if ((scratch[2 * k + 1] & 0xff) != 0xff - k)

drivers/ata/pata_parport/epia.c

247

char scratch[512];

drivers/ata/pata_parport/epia.c

265

epia_read_block(pi, scratch, 512);

drivers/ata/pata_parport/epia.c

267

if ((scratch[2 * k] & 0xff) != ((k + 1) & 0xff))

drivers/ata/pata_parport/epia.c

269

if ((scratch[2 * k + 1] & 0xff) != ((-2 - k) & 0xff))

drivers/ata/pata_parport/friq.c

184

char scratch[512];

drivers/ata/pata_parport/friq.c

204

friq_read_block_int(pi, scratch, 512, 0x10);

drivers/ata/pata_parport/friq.c

207

if (scratch[k] != k)

drivers/ata/pata_parport/frpw.c

223

char scratch[512];

drivers/ata/pata_parport/frpw.c

252

frpw_read_block_int(pi, scratch, 512, 0x10);

drivers/ata/pata_parport/frpw.c

255

if (scratch[k] != k)

drivers/char/agp/uninorth-agp.c

230

u32 command, scratch, status;

drivers/char/agp/uninorth-agp.c

267

&scratch);

drivers/char/agp/uninorth-agp.c

268

} while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);

drivers/char/agp/uninorth-agp.c

269

if ((scratch & PCI_AGP_COMMAND_AGP) == 0)

drivers/char/tpm/tpm2-sessions.c

114

u8 scratch[AES_KEY_BYTES + AES_BLOCK_SIZE];

drivers/char/tpm/tpm2-sessions.c

677

auth->scratch);

drivers/char/tpm/tpm2-sessions.c

680

aes_prepareenckey(&auth->aes_key, auth->scratch, AES_KEY_BYTES);

drivers/char/tpm/tpm2-sessions.c

683

auth->scratch + AES_KEY_BYTES);

drivers/char/tpm/tpm2-sessions.c

858

auth->scratch);

drivers/char/tpm/tpm2-sessions.c

861

aes_prepareenckey(&auth->aes_key, auth->scratch, AES_KEY_BYTES);

drivers/char/tpm/tpm2-sessions.c

864

auth->scratch + AES_KEY_BYTES);

drivers/crypto/ccp/sev-dev-tio.c

109

struct sla_addr_t scratch;

drivers/crypto/ccp/sev-dev-tio.c

552

rc2 = sla_expand(&dev_data->scratch, &dev_data->scratch_len);

drivers/crypto/ccp/sev-dev-tio.c

635

ctrl->scratch = dev_data->scratch;

drivers/crypto/ccp/sev-dev-tio.c

653

sla_free(dev_data->scratch, tio_status->spdm_scratch_size_max, true);

drivers/crypto/ccp/sev-dev-tio.c

657

dev_data->scratch.sla = 0;

drivers/crypto/ccp/sev-dev-tio.c

672

dev_data->scratch = sla_alloc(dev_data->scratch_len, true);

drivers/crypto/ccp/sev-dev-tio.c

677

IS_SLA_NULL(dev_data->scratch) || IS_SLA_NULL(dev_data->dev_ctx)) {

drivers/crypto/ccp/sev-dev-tio.h

39

struct sla_addr_t scratch;

drivers/firmware/cirrus/cs_dsp.c

766

void *scratch;

drivers/firmware/cirrus/cs_dsp.c

774

scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);

drivers/firmware/cirrus/cs_dsp.c

775

if (!scratch)

drivers/firmware/cirrus/cs_dsp.c

778

ret = regmap_raw_write(dsp->regmap, reg, scratch,

drivers/firmware/cirrus/cs_dsp.c

783

kfree(scratch);

drivers/firmware/cirrus/cs_dsp.c

788

kfree(scratch);

drivers/firmware/cirrus/cs_dsp.c

871

void *scratch;

drivers/firmware/cirrus/cs_dsp.c

879

scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);

drivers/firmware/cirrus/cs_dsp.c

880

if (!scratch)

drivers/firmware/cirrus/cs_dsp.c

883

ret = regmap_raw_read(dsp->regmap, reg, scratch, len);

drivers/firmware/cirrus/cs_dsp.c

887

kfree(scratch);

drivers/firmware/cirrus/cs_dsp.c

892

memcpy(buf, scratch, len);

drivers/firmware/cirrus/cs_dsp.c

893

kfree(scratch);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1701

ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1702

if (!ctx->scratch)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1878

kfree(adev->mode_info.atom_context->scratch);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

207

ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

208

if (!ctx->scratch)

drivers/gpu/drm/amd/amdgpu/atom.c

293

val = gctx->scratch[(gctx->fb_base / 4) + idx];

drivers/gpu/drm/amd/amdgpu/atom.c

555

gctx->scratch[(gctx->fb_base / 4) + idx] = val;

drivers/gpu/drm/amd/amdgpu/atom.h

147

uint32_t *scratch;

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

75

base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);

drivers/gpu/drm/amd/amdgpu/atombios_i2c.c

54

base = (unsigned char *)adev->mode_info.atom_context->scratch;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4036

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4041

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4050

amdgpu_ring_write(ring, scratch -

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4056

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

566

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

571

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

580

gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

583

amdgpu_ring_write(ring, scratch -

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

590

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

454

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

459

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

469

gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

472

amdgpu_ring_write(ring, scratch -

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

479

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1197

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1202

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1208

amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1213

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

285

dma_addr_t *scratch, u64 ttm_res_offset)

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

300

src = scratch;

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

301

dst = (u64 *)(scratch + npages);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

405

dma_addr_t *scratch;

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

424

scratch = (dma_addr_t *)(migrate.dst + npages);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

450

r = svm_migrate_copy_to_vram(node, prange, &migrate, &mfence, scratch, ttm_res_offset);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

460

svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

590

dma_addr_t *scratch, u64 npages)

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

605

src = (u64 *)(scratch + npages);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

606

dst = scratch;

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

704

dma_addr_t *scratch;

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

727

scratch = (dma_addr_t *)(migrate.dst + npages);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

754

scratch, npages);

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

764

svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages);

drivers/gpu/drm/amd/display/dc/core/dc.c

2095

memset(dc->scratch.pipes_to_unlock_first, 0, sizeof(dc->scratch.pipes_to_unlock_first));

drivers/gpu/drm/amd/display/dc/core/dc.c

2108

dc->scratch.pipes_to_unlock_first[i] = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

3377

struct dc_scratch_space *scratch,

drivers/gpu/drm/amd/display/dc/core/dc.c

3387

dc_plane_copy_config(&scratch->plane_states[i], status->plane_states[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

3389

scratch->stream_state = *stream;

drivers/gpu/drm/amd/display/dc/core/dc.c

3393

struct dc_scratch_space *scratch,

drivers/gpu/drm/amd/display/dc/core/dc.c

3403

dc_plane_copy_config(status->plane_states[i], &scratch->plane_states[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

3408

*stream = scratch->stream_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

3553

backup_planes_and_stream_state(&dc->scratch.current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

3677

backup_planes_and_stream_state(&dc->scratch.new_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4870

restore_planes_and_stream_state(&dc->scratch.current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4900

restore_planes_and_stream_state(&dc->scratch.new_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5456

struct dc_update_scratch_space *scratch = dc_update_planes_and_stream_init(

drivers/gpu/drm/amd/display/dc/core/dc.c

5466

if (!dc_update_planes_and_stream_prepare(scratch))

drivers/gpu/drm/amd/display/dc/core/dc.c

5469

dc_update_planes_and_stream_execute(scratch);

drivers/gpu/drm/amd/display/dc/core/dc.c

5470

more = dc_update_planes_and_stream_cleanup(scratch);

drivers/gpu/drm/amd/display/dc/core/dc.c

7218

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7222

dc_exit_ips_for_hw_access(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7224

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7225

scratch->surface_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

7226

scratch->surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

7227

scratch->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

7228

scratch->stream_update

drivers/gpu/drm/amd/display/dc/core/dc.c

7233

const struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7237

(void) scratch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7241

const struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7244

if (scratch->do_clear_update_flags)

drivers/gpu/drm/amd/display/dc/core/dc.c

7245

clear_update_flags(scratch->surface_updates, scratch->surface_count, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7251

struct dc_update_scratch_space *scratch,

drivers/gpu/drm/amd/display/dc/core/dc.c

7256

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7260

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7261

scratch->dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

7262

scratch->intermediate_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

7263

scratch->new_context

drivers/gpu/drm/amd/display/dc/core/dc.c

7276

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7279

if (scratch->flow == UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7282

ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID);

drivers/gpu/drm/amd/display/dc/core/dc.c

7283

dc_exit_ips_for_hw_access(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7286

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7287

scratch->surface_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

7288

scratch->surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

7289

scratch->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

7290

scratch->stream_update,

drivers/gpu/drm/amd/display/dc/core/dc.c

7291

&scratch->update_type,

drivers/gpu/drm/amd/display/dc/core/dc.c

7292

&scratch->new_context

drivers/gpu/drm/amd/display/dc/core/dc.c

7297

if (scratch->new_context == scratch->dc->current_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7298

ASSERT(scratch->update_type < UPDATE_TYPE_FULL);

drivers/gpu/drm/amd/display/dc/core/dc.c

7305

scratch->surface_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

7306

scratch->surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

7307

scratch->stream_update

drivers/gpu/drm/amd/display/dc/core/dc.c

7310

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7312

scratch->surface_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

7313

scratch->surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

7314

scratch->stream_update,

drivers/gpu/drm/amd/display/dc/core/dc.c

7315

scratch->stream

drivers/gpu/drm/amd/display/dc/core/dc.c

7318

&& !scratch->dc->check_config.enable_legacy_fast_update;

drivers/gpu/drm/amd/display/dc/core/dc.c

7319

scratch->flow = fast

drivers/gpu/drm/amd/display/dc/core/dc.c

7325

ASSERT(scratch->update_type >= UPDATE_TYPE_FULL);

drivers/gpu/drm/amd/display/dc/core/dc.c

7327

const bool seamless = scratch->dc->hwss.is_pipe_topology_transition_seamless(

drivers/gpu/drm/amd/display/dc/core/dc.c

7328

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7329

scratch->dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

7330

scratch->new_context

drivers/gpu/drm/amd/display/dc/core/dc.c

7333

scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS;

drivers/gpu/drm/amd/display/dc/core/dc.c

7334

if (scratch->dc->check_config.deferred_transition_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

7336

transition_countdown_init(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7340

if (!scratch->dc->debug.disable_deferred_minimal_transitions) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7341

scratch->dc->check_config.deferred_transition_state = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

7342

transition_countdown_init(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7345

scratch->intermediate_context = create_minimal_transition_state(

drivers/gpu/drm/amd/display/dc/core/dc.c

7346

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7347

scratch->new_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

7348

&scratch->intermediate_policy

drivers/gpu/drm/amd/display/dc/core/dc.c

7350

if (scratch->intermediate_context) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7351

if (update_planes_and_stream_prepare_v3_intermediate_seamless(scratch)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7352

scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW;

drivers/gpu/drm/amd/display/dc/core/dc.c

7356

update_planes_and_stream_cleanup_v3_release_minimal(scratch, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

7359

scratch->backup_context = scratch->dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

7360

restore_planes_and_stream_state(&scratch->dc->scratch.current_state, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7361

dc_state_retain(scratch->backup_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

7362

scratch->intermediate_context = create_minimal_transition_state(

drivers/gpu/drm/amd/display/dc/core/dc.c

7363

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7364

scratch->backup_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

7365

&scratch->intermediate_policy

drivers/gpu/drm/amd/display/dc/core/dc.c

7367

if (scratch->intermediate_context) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7368

if (update_planes_and_stream_prepare_v3_intermediate_seamless(scratch)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7369

scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT;

drivers/gpu/drm/amd/display/dc/core/dc.c

7370

scratch->intermediate_count = initialize_empty_surface_updates(

drivers/gpu/drm/amd/display/dc/core/dc.c

7371

scratch->stream, scratch->intermediate_updates

drivers/gpu/drm/amd/display/dc/core/dc.c

7376

update_planes_and_stream_cleanup_v3_release_minimal(scratch, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

7379

scratch->flow = UPDATE_V3_FLOW_INVALID;

drivers/gpu/drm/amd/display/dc/core/dc.c

7380

dc_state_release(scratch->backup_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

7381

restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7386

const struct dc_update_scratch_space *scratch,

drivers/gpu/drm/amd/display/dc/core/dc.c

7393

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7394

intermediate_update ? scratch->intermediate_updates : scratch->surface_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

7395

intermediate_update ? scratch->intermediate_count : scratch->surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

7396

scratch->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

7397

use_stream_update ? scratch->stream_update : NULL,

drivers/gpu/drm/amd/display/dc/core/dc.c

7398

intermediate_context ? UPDATE_TYPE_FULL : scratch->update_type,

drivers/gpu/drm/amd/display/dc/core/dc.c

7400

intermediate_context ? scratch->intermediate_context : scratch->new_context

drivers/gpu/drm/amd/display/dc/core/dc.c

7405

const struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7408

switch (scratch->flow) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7411

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7412

scratch->surface_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

7413

scratch->surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

7414

scratch->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

7415

scratch->stream_update,

drivers/gpu/drm/amd/display/dc/core/dc.c

7416

scratch->update_type,

drivers/gpu/drm/amd/display/dc/core/dc.c

7417

scratch->new_context

drivers/gpu/drm/amd/display/dc/core/dc.c

7423

update_planes_and_stream_execute_v3_commit(scratch, false, false, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

7427

update_planes_and_stream_execute_v3_commit(scratch, false, true,

drivers/gpu/drm/amd/display/dc/core/dc.c

7428

scratch->dc->check_config.deferred_transition_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

7432

update_planes_and_stream_execute_v3_commit(scratch, true, true, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

7442

struct dc_update_scratch_space *scratch,

drivers/gpu/drm/amd/display/dc/core/dc.c

7447

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7448

scratch->intermediate_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

7449

backup ? scratch->backup_context : scratch->new_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

7450

&scratch->intermediate_policy

drivers/gpu/drm/amd/display/dc/core/dc.c

7455

struct dc_update_scratch_space *scratch,

drivers/gpu/drm/amd/display/dc/core/dc.c

7459

swap_and_release_current_context(scratch->dc, scratch->intermediate_context, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7460

dc_state_retain(scratch->dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

7461

update_planes_and_stream_cleanup_v3_release_minimal(scratch, backup);

drivers/gpu/drm/amd/display/dc/core/dc.c

7465

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7468

switch (scratch->flow) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7471

if (scratch->dc->check_config.transition_countdown_to_steady_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

7472

scratch->dc->check_config.transition_countdown_to_steady_state--;

drivers/gpu/drm/amd/display/dc/core/dc.c

7476

swap_and_release_current_context(scratch->dc, scratch->new_context, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7480

update_planes_and_stream_cleanup_v3_intermediate(scratch, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

7481

if (scratch->dc->check_config.deferred_transition_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7482

dc_state_release(scratch->new_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

7484

scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS;

drivers/gpu/drm/amd/display/dc/core/dc.c

7490

update_planes_and_stream_cleanup_v3_intermediate(scratch, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

7491

dc_state_release(scratch->backup_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

7492

restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7493

scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS;

drivers/gpu/drm/amd/display/dc/core/dc.c

7501

if (scratch->do_clear_update_flags)

drivers/gpu/drm/amd/display/dc/core/dc.c

7502

clear_update_flags(scratch->surface_updates, scratch->surface_count, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

7516

struct dc_update_scratch_space *scratch = stream->update_scratch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7518

*scratch = (struct dc_update_scratch_space){

drivers/gpu/drm/amd/display/dc/core/dc.c

7528

return scratch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7532

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7535

return scratch->update_v3

drivers/gpu/drm/amd/display/dc/core/dc.c

7536

? update_planes_and_stream_prepare_v3(scratch)

drivers/gpu/drm/amd/display/dc/core/dc.c

7537

: update_planes_and_stream_prepare_v2(scratch);

drivers/gpu/drm/amd/display/dc/core/dc.c

7541

const struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7544

scratch->update_v3

drivers/gpu/drm/amd/display/dc/core/dc.c

7545

? update_planes_and_stream_execute_v3(scratch)

drivers/gpu/drm/amd/display/dc/core/dc.c

7546

: update_planes_and_stream_execute_v2(scratch);

drivers/gpu/drm/amd/display/dc/core/dc.c

7550

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/core/dc.c

7553

return scratch->update_v3

drivers/gpu/drm/amd/display/dc/core/dc.c

7554

? update_planes_and_stream_cleanup_v3(scratch)

drivers/gpu/drm/amd/display/dc/core/dc.c

7555

: update_planes_and_stream_cleanup_v2(scratch);

drivers/gpu/drm/amd/display/dc/dc.h

1822

} scratch;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

975

DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

976

DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

977

DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

978

DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

979

DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

980

DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

981

DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

982

DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

983

DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

984

DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

985

DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

986

DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

987

DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

988

DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

989

DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

990

DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]);

drivers/gpu/drm/amd/display/dc/dc_stream.h

418

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/dc_stream.h

423

const struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/dc_stream.h

428

struct dc_update_scratch_space *scratch

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2403

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

325

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

592

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

731

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

234

dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

268

dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

1000

struct CalculatePrefetchSchedule_locals_st *s = &scratch->CalculatePrefetchSchedule_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

186

static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

2823

struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

2826

struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st *s = &scratch->CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

3762

static void CalculateStutterEfficiency(struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

4085

static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

454

struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

4598

static void UseMinimumDCFCLK(struct display_mode_lib_scratch_st *scratch, struct UseMinimumDCFCLK_params_st *p)

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

4600

struct UseMinimumDCFCLK_locals_st *s = &scratch->UseMinimumDCFCLK_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

5052

static void CalculateVMRowAndSwath(struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

5055

struct CalculateVMRowAndSwath_locals_st *s = &scratch->CalculateVMRowAndSwath_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

573

struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

577

struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6272

struct dml_core_mode_support_locals_st *s = &mode_lib->scratch.dml_core_mode_support_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6273

struct CalculatePrefetchSchedule_params_st *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6274

struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6414

CalculatePrefetchSchedule(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6708

CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6716

struct CalculateVMRowAndSwath_params_st *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6717

struct dml_core_mode_support_locals_st *s = &mode_lib->scratch.dml_core_mode_support_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6787

struct dml_core_mode_support_locals_st *s = &mode_lib->scratch.dml_core_mode_support_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6788

struct UseMinimumDCFCLK_params_st *UseMinimumDCFCLK_params = &mode_lib->scratch.UseMinimumDCFCLK_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6789

struct CalculateSwathAndDETConfiguration_params_st *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

6790

struct CalculateVMRowAndSwath_params_st *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

7100

CalculateSwathAndDETConfiguration(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

7639

CalculateSwathAndDETConfiguration(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

7758

CalculateVMRowAndSwath(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8018

UseMinimumDCFCLK(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8301

struct dml_core_mode_programming_locals_st *s = &mode_lib->scratch.dml_core_mode_programming_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8302

struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8303

struct CalculateVMRowAndSwath_params_st *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8304

struct CalculateSwathAndDETConfiguration_params_st *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8305

struct CalculateStutterEfficiency_params_st *CalculateStutterEfficiency_params = &mode_lib->scratch.CalculateStutterEfficiency_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8306

struct CalculatePrefetchSchedule_params_st *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8564

CalculateSwathAndDETConfiguration(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

8770

CalculateVMRowAndSwath(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

9060

CalculatePrefetchSchedule(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

9481

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

9837

CalculateStutterEfficiency(&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

997

static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

1913

struct display_mode_lib_scratch_st scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c

404

dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported");

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c

405

dml_print("DML: MODE SUPPORT: dram clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.dram_clock_change_support == true ? "Supported" : "NOT Supported");

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c

406

dml_print("DML: MODE SUPPORT: f_clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.f_clock_change_support == true ? "Supported" : "NOT Supported");

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

472

struct pipe_ctx *temp_pipe = &dml_ctx->v21.scratch.temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

212

memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

272

memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

283

dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

316

struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

191

struct dml2_core_scratch *scratch)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

199

memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

200

memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

201

memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

214

scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

215

scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

223

scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

224

scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

237

phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

239

main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

242

scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

243

scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

255

const struct dml2_display_cfg *svp_expanded_display_cfg, struct dml2_display_cfg_programming *programming, struct dml2_core_scratch *scratch)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

285

phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[stream_index]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

367

main_plane_index = scratch->phantom_plane_index_to_main_plane_index[plane_index];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

413

struct dml2_core_mode_support_locals *l = &core->scratch.mode_support_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

419

expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

544

struct dml2_core_mode_programming_locals *l = &core->scratch.mode_programming_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

555

expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

570

pack_mode_programming_params_with_implicit_subvp(core, in_out->display_cfg, &l->svp_expanded_display_cfg, in_out->programming, &core->scratch);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

638

in_out->programming->informative.voltage_level = in_out->instance->scratch.mode_programming_locals.mode_programming_ex_params.min_clk_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

640

in_out->programming->informative.voltage_level = in_out->instance->scratch.mode_support_locals.mode_support_ex_params.min_clk_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10091

static void CalculateStutterEfficiency(struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10094

struct dml2_core_calcs_CalculateStutterEfficiency_locals *l = &scratch->CalculateStutterEfficiency_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10388

struct dml2_core_calcs_mode_programming_locals *s = &mode_lib->scratch.dml_core_mode_programming_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10389

struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10390

struct dml2_core_calcs_CalculateVMRowAndSwath_params *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10391

struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10392

struct dml2_core_calcs_CalculateStutterEfficiency_params *CalculateStutterEfficiency_params = &mode_lib->scratch.CalculateStutterEfficiency_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10393

struct dml2_core_calcs_CalculatePrefetchSchedule_params *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10394

struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *CheckGlobalPrefetchAdmissibility_params = &mode_lib->scratch.CheckGlobalPrefetchAdmissibility_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10395

struct dml2_core_calcs_calculate_mcache_setting_params *calculate_mcache_setting_params = &mode_lib->scratch.calculate_mcache_setting_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10396

struct dml2_core_calcs_calculate_tdlut_setting_params *calculate_tdlut_setting_params = &mode_lib->scratch.calculate_tdlut_setting_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10397

struct dml2_core_shared_CalculateMetaAndPTETimes_params *CalculateMetaAndPTETimes_params = &mode_lib->scratch.CalculateMetaAndPTETimes_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10398

struct dml2_core_calcs_calculate_peak_bandwidth_required_params *calculate_peak_bandwidth_params = &mode_lib->scratch.calculate_peak_bandwidth_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10399

struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *calculate_bytes_to_fetch_required_to_hide_latency_params = &mode_lib->scratch.calculate_bytes_to_fetch_required_to_hide_latency_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10412

memset(&mode_lib->scratch, 0, sizeof(struct dml2_core_internal_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10667

CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10816

CalculateVMRowAndSwath(&mode_lib->scratch, CalculateVMRowAndSwath_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10887

calculate_mcache_setting(&mode_lib->scratch, calculate_mcache_setting_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10951

calculate_tdlut_setting(&mode_lib->scratch, calculate_tdlut_setting_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11203

CheckGlobalPrefetchAdmissibility(&mode_lib->scratch, CheckGlobalPrefetchAdmissibility_params); // dont care about the check output for mode programming

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11339

mode_lib->mp.NoTimeToPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11476

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11534

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11609

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11755

CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&mode_lib->scratch, CalculateWatermarks_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11800

CalculateMetaAndPTETimes_params->scratch = &mode_lib->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12016

CalculateStutterEfficiency(&mode_lib->scratch, CalculateStutterEfficiency_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12029

CalculateStutterEfficiency(&mode_lib->scratch, CalculateStutterEfficiency_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12134

mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportStationary = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12135

mode_lib->scratch.calculate_vm_and_row_bytes_params.DCCEnable = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12136

mode_lib->scratch.calculate_vm_and_row_bytes_params.NumberOfDPPs = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12137

mode_lib->scratch.calculate_vm_and_row_bytes_params.BlockHeight256Bytes = BlockHeight256Bytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12138

mode_lib->scratch.calculate_vm_and_row_bytes_params.BlockWidth256Bytes = BlockWidth256Bytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12139

mode_lib->scratch.calculate_vm_and_row_bytes_params.SourcePixelFormat = SourcePixelFormat;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12140

mode_lib->scratch.calculate_vm_and_row_bytes_params.SurfaceTiling = SurfaceTiling;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12141

mode_lib->scratch.calculate_vm_and_row_bytes_params.BytePerPixel = BytePerPixel;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12142

mode_lib->scratch.calculate_vm_and_row_bytes_params.RotationAngle = ScanDirection;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12143

mode_lib->scratch.calculate_vm_and_row_bytes_params.SwathWidth = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12144

mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportHeight = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12145

mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportXStart = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12146

mode_lib->scratch.calculate_vm_and_row_bytes_params.ViewportYStart = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12147

mode_lib->scratch.calculate_vm_and_row_bytes_params.GPUVMEnable = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12148

mode_lib->scratch.calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = 4;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12149

mode_lib->scratch.calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = GPUVMMinPageSizeKBytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12150

mode_lib->scratch.calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = PTEBufferSizeInRequests;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12151

mode_lib->scratch.calculate_vm_and_row_bytes_params.Pitch = pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12152

mode_lib->scratch.calculate_vm_and_row_bytes_params.MacroTileWidth = MacroTileWidth;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12153

mode_lib->scratch.calculate_vm_and_row_bytes_params.MacroTileHeight = MacroTileHeight;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12154

mode_lib->scratch.calculate_vm_and_row_bytes_params.is_phantom = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12155

mode_lib->scratch.calculate_vm_and_row_bytes_params.DCCMetaPitch = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12156

mode_lib->scratch.calculate_vm_and_row_bytes_params.mrq_present = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12158

mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &dummy_integer[1];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12159

mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &dummy_integer[2];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12160

mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_width_ub = &dummy_integer[3];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12161

mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_height = dpte_row_height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12162

mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_height_linear = &dummy_integer[4];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12163

mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &dummy_integer[5];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12164

mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &dummy_integer[6];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12165

mode_lib->scratch.calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &dummy_integer[7];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12166

mode_lib->scratch.calculate_vm_and_row_bytes_params.vmpg_width = &dummy_integer[8];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12167

mode_lib->scratch.calculate_vm_and_row_bytes_params.vmpg_height = &dummy_integer[9];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12168

mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &dummy_integer[11];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12169

mode_lib->scratch.calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &dummy_integer[12];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12170

mode_lib->scratch.calculate_vm_and_row_bytes_params.PTERequestSize = &dummy_integer[13];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12171

mode_lib->scratch.calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &dummy_integer[14];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12173

mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_row_bytes = &dummy_integer[15];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12174

mode_lib->scratch.calculate_vm_and_row_bytes_params.MetaRequestWidth = &dummy_integer[16];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12175

mode_lib->scratch.calculate_vm_and_row_bytes_params.MetaRequestHeight = &dummy_integer[17];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12176

mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_row_width = &dummy_integer[18];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12177

mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_row_height = &dummy_integer[19];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12178

mode_lib->scratch.calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &dummy_integer[20];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12181

CalculateVMAndRowBytes(&mode_lib->scratch.calculate_vm_and_row_bytes_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12753

rq_dlg_get_dlg_reg(&mode_lib->scratch, &out->dlg_regs, &out->ttu_regs, display_cfg, mode_lib, pipe_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2270

struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2419

struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2424

struct dml2_core_shared_calculate_mcache_setting_locals *l = &scratch->calculate_mcache_setting_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2480

calculate_mcache_row_bytes(scratch, &l->l_p);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2516

calculate_mcache_row_bytes(scratch, &l->c_p);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2866

static void CalculateVMRowAndSwath(struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2869

struct dml2_core_calcs_CalculateVMRowAndSwath_locals *s = &scratch->CalculateVMRowAndSwath_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2891

scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2892

scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2893

scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2894

scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2895

scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2896

scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2897

scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2898

scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2899

scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2900

scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthC[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2901

scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeightC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2902

scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStartC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2903

scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStartC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2904

scratch->calculate_vm_and_row_bytes_params.GPUVMEnable = p->display_cfg->gpuvm_enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2905

scratch->calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = p->display_cfg->gpuvm_max_page_table_levels;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2906

scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2907

scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForChroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2908

scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2909

scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2910

scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2911

scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2912

scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchC;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2913

scratch->calculate_vm_and_row_bytes_params.mrq_present = p->mrq_present;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2915

scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowC[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2916

scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageC[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2917

scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_chroma_ub[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2918

scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_chroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2919

scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_chroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2920

scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowC_one_row_per_frame[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2921

scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_chroma_ub_one_row_per_frame[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2922

scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_chroma_one_row_per_frame[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2923

scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_c[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2924

scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_c[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2925

scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthC[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2926

scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightC[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2927

scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeC[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2928

scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_c[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2930

scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_c[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2931

scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_chroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2932

scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_chroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2933

scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_chroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2934

scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_chroma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2935

scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_c[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2937

s->vm_bytes_c = CalculateVMAndRowBytes(&scratch->calculate_vm_and_row_bytes_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2969

scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2970

scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2971

scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2972

scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2973

scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2974

scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2975

scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2976

scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2977

scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2978

scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthY[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2979

scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeight;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2980

scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStart;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2981

scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStart;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2982

scratch->calculate_vm_and_row_bytes_params.GPUVMEnable = p->display_cfg->gpuvm_enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2983

scratch->calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = p->display_cfg->gpuvm_max_page_table_levels;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2984

scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2985

scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForLuma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2986

scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2987

scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2988

scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2989

scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2990

scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchY;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2991

scratch->calculate_vm_and_row_bytes_params.mrq_present = p->mrq_present;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2993

scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowY[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2994

scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageY[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2995

scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_luma_ub[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2996

scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_luma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2997

scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_luma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2998

scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowY_one_row_per_frame[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2999

scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_luma_ub_one_row_per_frame[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3000

scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_luma_one_row_per_frame[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3001

scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_y[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3002

scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_y[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3003

scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthY[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3004

scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightY[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3005

scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeY[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3006

scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_l[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3008

scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_l[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3009

scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_luma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3010

scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_luma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3011

scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_luma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3012

scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_luma[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3013

scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_l[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3015

s->vm_bytes_l = CalculateVMAndRowBytes(&scratch->calculate_vm_and_row_bytes_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3693

static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3777

&scratch->CalculateDETBufferSize_locals,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4620

struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5096

static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch, struct dml2_core_calcs_CalculatePrefetchSchedule_params *p)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5098

struct dml2_core_calcs_CalculatePrefetchSchedule_locals *s = &scratch->CalculatePrefetchSchedule_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5987

static noinline_for_stack bool CheckGlobalPrefetchAdmissibility(struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5990

struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals *s = &scratch->CheckGlobalPrefetchAdmissibility_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6685

struct dml2_core_internal_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6688

struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals *s = &scratch->CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7309

struct dml2_core_calcs_mode_support_locals *s = &mode_lib->scratch.dml_core_mode_support_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7310

struct dml2_core_calcs_calculate_tdlut_setting_params *calculate_tdlut_setting_params = &mode_lib->scratch.calculate_tdlut_setting_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7311

struct dml2_core_calcs_CalculatePrefetchSchedule_params *CalculatePrefetchSchedule_params = &mode_lib->scratch.CalculatePrefetchSchedule_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7312

struct dml2_core_calcs_calculate_peak_bandwidth_required_params *calculate_peak_bandwidth_params = &mode_lib->scratch.calculate_peak_bandwidth_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7314

struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *CheckGlobalPrefetchAdmissibility_params = &mode_lib->scratch.CheckGlobalPrefetchAdmissibility_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7316

struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *CalculateWatermarks_params = &mode_lib->scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7359

calculate_tdlut_setting(&mode_lib->scratch, calculate_tdlut_setting_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7552

mode_lib->ms.NoTimeForPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7691

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7749

mode_lib->ms.support.PrefetchSupported = CheckGlobalPrefetchAdmissibility(&mode_lib->scratch, CheckGlobalPrefetchAdmissibility_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7783

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7858

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7940

CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&mode_lib->scratch, CalculateWatermarks_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7956

struct dml2_core_calcs_mode_support_locals *s = &mode_lib->scratch.dml_core_mode_support_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7957

struct dml2_core_calcs_CalculateVMRowAndSwath_params *CalculateVMRowAndSwath_params = &mode_lib->scratch.CalculateVMRowAndSwath_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7958

struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *CalculateSwathAndDETConfiguration_params = &mode_lib->scratch.CalculateSwathAndDETConfiguration_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7959

struct dml2_core_calcs_calculate_mcache_setting_params *calculate_mcache_setting_params = &mode_lib->scratch.calculate_mcache_setting_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7960

struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *calculate_bytes_to_fetch_required_to_hide_latency_params = &mode_lib->scratch.calculate_bytes_to_fetch_required_to_hide_latency_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7963

memset(&mode_lib->scratch, 0, sizeof(struct dml2_core_internal_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8380

CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8453

&mode_lib->scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8883

CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9026

CalculateVMRowAndSwath(&mode_lib->scratch, CalculateVMRowAndSwath_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9413

calculate_mcache_setting(&mode_lib->scratch, calculate_mcache_setting_params);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h

1659

struct dml2_core_internal_scratch *scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h

2317

struct dml2_core_internal_scratch scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

611

struct dml2_core_scratch *scratch)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

619

memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

620

memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

621

memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

634

scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

635

scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

643

scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

644

scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

657

phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

659

main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

662

scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

663

scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h

33

struct dml2_core_scratch *scratch);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

125

if (pmo->scratch.pmo_dcn3.current_candidate[0] > 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

126

pmo->scratch.pmo_dcn3.current_candidate[0]--;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

129

for (borrow_from = 1; borrow_from < size && pmo->scratch.pmo_dcn3.current_candidate[borrow_from] == 0; borrow_from++)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

133

pmo->scratch.pmo_dcn3.current_candidate[borrow_from]--;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

135

pmo->scratch.pmo_dcn3.current_candidate[i] = pmo->scratch.pmo_dcn3.reserved_time_candidates_count[i] - 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

538

pmo->scratch.pmo_dcn3.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

539

pmo->scratch.pmo_dcn3.max_latency_index = pmo->mcg_clock_table_size - 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

540

pmo->scratch.pmo_dcn3.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

542

pmo->scratch.pmo_dcn3.stream_mask = 0xF;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

565

pmo->scratch.pmo_dcn3.stream_mask &= ~(0x1 << plane_descriptor->stream_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

601

pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][0] = min_reserved_vblank_time;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

602

pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] = candidate_count;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

604

if (!(pmo->scratch.pmo_dcn3.stream_mask & (0x1 << stream_index)))

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

611

if (are_timings_trivially_synchronizable(in_out->base_display_config, pmo->scratch.pmo_dcn3.stream_mask)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

612

pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

620

if (are_timings_trivially_synchronizable(in_out->base_display_config, pmo->scratch.pmo_dcn3.stream_mask)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

621

pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

630

pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

634

pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] = candidate_count;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

637

sort(pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

638

pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

640

remove_duplicates(pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

641

&pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

643

pmo->scratch.pmo_dcn3.current_candidate[stream_index] =

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

644

pmo->scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] - 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

660

pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][pmo->scratch.pmo_dcn3.current_candidate[stream_index]] * 1000) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

678

if (pmo->scratch.pmo_dcn3.cur_latency_index < pmo->scratch.pmo_dcn3.max_latency_index) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

680

pmo->scratch.pmo_dcn3.cur_latency_index++;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

688

pmo->scratch.pmo_dcn3.cur_latency_index = pmo->scratch.pmo_dcn3.min_latency_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

697

in_out->optimized_display_config->stage3.min_clk_index_for_latency = pmo->scratch.pmo_dcn3.cur_latency_index;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

701

pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][pmo->scratch.pmo_dcn3.current_candidate[stream_index]]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1003

set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1023

valid &= is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.stream_vactive_capability_mask, i);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1041

if (mask != pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[i]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1072

stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1150

stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1156

microschedule_vlines = calc_svp_microschedule(&pmo->scratch.pmo_dcn4.stream_pstate_meta[i]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1177

static void insert_into_candidate_list(const struct dml2_pmo_pstate_strategy *pstate_strategy, int stream_count, struct dml2_pmo_scratch *scratch)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1179

scratch->pmo_dcn4.pstate_strategy_candidates[scratch->pmo_dcn4.num_pstate_candidates] = *pstate_strategy;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1180

scratch->pmo_dcn4.num_pstate_candidates++;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1283

stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_vactive.common;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1287

stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_vblank.common;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1291

stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_subvp.common;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1294

stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_drr.common;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1320

struct dml2_pmo_scratch *s = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1339

if (is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], i)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1363

build_method_scheduling_params(group_pstate_meta, &pmo->scratch.pmo_dcn4.stream_pstate_meta[base_stream_idx]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1376

struct dml2_pmo_scratch *s = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1593

struct dml2_pmo_scratch *s = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1695

struct dml2_pstate_meta *stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1845

struct dml2_implicit_svp_meta *stream_svp_meta = &pmo->scratch.pmo_dcn4.stream_svp_meta[stream_index];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1846

struct dml2_pstate_meta *stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1860

struct dml2_pmo_scratch *s = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1882

pmo->scratch.pmo_dcn4.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1883

pmo->scratch.pmo_dcn4.max_latency_index = pmo->mcg_clock_table_size;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1884

pmo->scratch.pmo_dcn4.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2005

struct dml2_pmo_scratch *scratch = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2019

&scratch->pmo_dcn4.stream_svp_meta[stream_index],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2028

struct dml2_pmo_scratch *scratch = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2042

&scratch->pmo_dcn4.stream_svp_meta[stream_index],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2099

(unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2120

(unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2128

struct dml2_pmo_scratch *scratch = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2138

if (pmo->scratch.pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_na) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2141

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_vactive) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2142

setup_planes_for_vactive_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2143

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_vblank) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2144

setup_planes_for_vblank_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2145

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2147

setup_planes_for_svp_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2148

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vactive_drr) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2150

setup_planes_for_vactive_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2151

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vblank_drr) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2153

setup_planes_for_vblank_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2154

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp_drr) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2156

setup_planes_for_svp_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2157

} else if (scratch->pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_drr) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2159

setup_planes_for_drr_by_mask(display_config, pmo, scratch->pmo_dcn4.stream_plane_mask[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2167

&scratch->pmo_dcn4.stream_pstate_meta,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2192

struct dml2_pmo_scratch *s = &in_out->instance->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2251

struct dml2_pmo_scratch *s = &in_out->instance->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2275

setup_display_config(in_out->optimized_display_config, in_out->instance, in_out->instance->scratch.pmo_dcn4.cur_pstate_candidate);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2320

pmo->scratch.pmo_dcn4.num_stutter_candidates = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2321

pmo->scratch.pmo_dcn4.cur_stutter_candidate = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2325

pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2326

pmo->scratch.pmo_dcn4.num_stutter_candidates++;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2327

pmo->scratch.pmo_dcn4.z8_vblank_optimizable = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2330

pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2334

pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2335

pmo->scratch.pmo_dcn4.num_stutter_candidates++;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2338

if (pmo->scratch.pmo_dcn4.num_stutter_candidates == 0)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2353

pmo->scratch.pmo_dcn4.z8_vblank_optimizable &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2377

if (pmo->scratch.pmo_dcn4.cur_stutter_candidate < pmo->scratch.pmo_dcn4.num_stutter_candidates) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2381

(long)math_max2(pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate] * 1000,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

966

struct dml2_pmo_scratch *s = &pmo->scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

1112

struct dml2_initialize_instance_locals *l = &dml->scratch.initialize_instance_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

511

struct dml2_top_mcache_validate_admissability_locals *l = &dml->scratch.mcache_validate_admissability_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

731

struct dml2_top_mcache_verify_mcache_size_locals *l = &dml->scratch.mcache_verify_mcache_size_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

778

struct dml2_check_mode_supported_locals *l = &dml->scratch.check_mode_supported_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

827

struct dml2_build_mode_programming_locals *l = &dml->scratch.build_mode_programming_locals;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

1003

} scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

1008

} scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

496

struct dml2_core_scratch scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

757

struct dml2_pmo_scratch scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1048

struct dc_pipe_mapping_scratch scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1076

memset(&scratch, 0, sizeof(struct dc_pipe_mapping_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1085

scratch.odm_info.odm_factor = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1087

scratch.odm_info.odm_factor = 2;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1089

scratch.odm_info.odm_factor = 4;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1092

scratch.odm_info.odm_factor = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1100

scratch.odm_info.odm_factor = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1102

scratch.odm_info.odm_factor = 2;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1104

scratch.odm_info.odm_factor = 4;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1107

scratch.odm_info.odm_factor = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1110

calculate_odm_slices(state->streams[stream_index], scratch.odm_info.odm_factor, scratch.odm_info.odm_slice_end_x);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1114

map_pipes_for_stream(ctx, state, state->streams[stream_index], &scratch, existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1124

scratch.mpc_info.prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1125

if (scratch.odm_info.odm_factor == 1 && plane_disp_cfg_index < disp_cfg_index_max) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1128

scratch.mpc_info.mpc_factor = DPPPerSurface[plane_disp_cfg_index];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1132

scratch.mpc_info.mpc_factor = 2;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1136

scratch.mpc_info.mpc_factor = 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1139

ASSERT(scratch.odm_info.odm_factor * scratch.mpc_info.mpc_factor > 0);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1142

memset(&scratch.pipe_pool, 0, sizeof(struct dc_plane_pipe_pool));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1145

state->stream_status[stream_index].plane_states[plane_index], plane_index, &scratch, existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

132

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

155

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx],

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

535

struct dc_pipe_mapping_scratch *scratch,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

543

ASSERT(scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine == 1 || scratch->pipe_pool.num_pipes_assigned_to_plane_for_odm_combine == 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

545

for (i = 0; i < scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

546

pipe = &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

548

if (scratch->mpc_info.prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

549

scratch->mpc_info.prev_odm_pipe->next_odm_pipe = pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

551

pipe->prev_odm_pipe = scratch->mpc_info.prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

554

scratch->mpc_info.prev_odm_pipe = pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

62

bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

704

bool is_plane_duplicate = ctx->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

710

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

735

struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

741

master_pipe = assign_pipes_to_stream(ctx, state, stream, scratch->odm_info.odm_factor, &scratch->pipe_pool, existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

742

sort_pipes_for_splitting(&scratch->pipe_pool);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

744

for (odm_slice_index = 0; odm_slice_index < scratch->odm_info.odm_factor; odm_slice_index++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

745

remove_pipes_from_blend_trees(ctx, state, &scratch->pipe_pool, odm_slice_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

747

add_odm_slice_to_odm_tree(ctx, state, scratch, odm_slice_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

750

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][0]], true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

755

int plane_index, struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

767

master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

768

scratch->mpc_info.mpc_factor, plane_index, &scratch->pipe_pool, existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

769

sort_pipes_for_splitting(&scratch->pipe_pool);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

771

for (odm_slice_index = 0; odm_slice_index < scratch->odm_info.odm_factor; odm_slice_index++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

773

scratch->odm_info.next_higher_pipe_for_odm_slice[odm_slice_index] = add_plane_to_blend_tree(ctx, state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

775

&scratch->pipe_pool,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

777

scratch->odm_info.next_higher_pipe_for_odm_slice[odm_slice_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

779

add_odm_slice_to_odm_tree(ctx, state, scratch, odm_slice_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

781

for (i = 0; i < scratch->pipe_pool.num_pipes_assigned_to_plane_for_mpcc_combine; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

784

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]], true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

788

free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id, plane_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

143

struct dml2_wrapper_scratch scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

147

struct dml21_wrapper_scratch scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1140

if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1153

bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1186

if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1200

struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1277

dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1287

dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1301

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1302

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1303

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1304

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1353

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1354

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1365

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1397

&dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1398

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1419

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1420

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

331

struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

332

struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

350

p->in_states = &dml2->v20.scratch.create_scratch.in_states;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

796

if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

797

out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

198

if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

209

if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

220

bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

283

struct dml2_calculate_rq_and_dlg_params_scratch *s = &in_ctx->v20.scratch.calculate_rq_and_dlg_params_scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

307

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

315

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

316

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

364

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

366

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

524

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

539

det_scratch->dpps_per_surface[i] = in_ctx->v20.scratch.cur_display_config.hw.DPPPerSurface[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

100

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

161

struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

162

struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

270

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

368

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

403

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

426

memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

520

memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

527

map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

529

dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

532

&dml2->v20.scratch.cur_display_config,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

533

&dml2->v20.scratch.mode_support_info,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

537

result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

86

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

87

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

88

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

89

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1879

if (dc->scratch.pipes_to_unlock_first[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1889

if (dc->scratch.pipes_to_unlock_first[i])

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

371

uint32_t scratch[17];

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

124

scratch = dmub->hw_funcs.get_gpint_response(dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

125

if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

433

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

434

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

435

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

436

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

437

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

438

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

439

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

440

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

441

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

442

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

443

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

444

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

445

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

446

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

447

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

448

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

98

uint32_t in_reset, scratch, i;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

111

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

112

if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

435

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

436

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

437

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

438

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

439

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

440

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

441

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

442

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

443

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

444

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

445

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

446

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

447

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

448

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

449

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

450

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

87

uint32_t in_reset, is_enabled, scratch, i, pwait_mode;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

110

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

111

if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

454

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

455

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

456

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

457

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

458

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

459

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

460

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

461

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

462

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

463

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

464

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

465

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

466

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

467

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

468

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

469

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

470

dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

95

uint32_t enabled, in_reset, scratch, pwait_mode;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

112

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

113

if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

476

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

477

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

478

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

479

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

480

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

481

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

482

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

483

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

484

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

485

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

486

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

487

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

488

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

489

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

490

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

491

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

492

dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

92

uint32_t in_reset, is_enabled, scratch, i, pwait_mode;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

441

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

442

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

443

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

444

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

445

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

446

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

447

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

448

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

449

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

450

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

451

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

452

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

453

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

454

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

455

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

456

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

457

dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

69

uint32_t enabled, in_reset, scratch, pwait_mode;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

84

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

85

if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

729

unsigned long scratch;

drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c

128

obj->scratch = phys_size;

drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c

14

unsigned long nreal = obj->scratch / PAGE_SIZE;

drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c

31

const unsigned long nreal = obj->scratch / PAGE_SIZE;

drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h

24

return obj->scratch;

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

105

struct blit_buffer scratch;

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

268

i915_vma_put(t->scratch.vma);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

312

t->scratch.vma = create_vma(t, false);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

313

if (IS_ERR(t->scratch.vma)) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

315

return PTR_ERR(t->scratch.vma);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

339

t->scratch.start_val = val;

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

343

i915_gem_object_flush_map(t->scratch.vma->obj);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

608

map = i915_gem_object_pin_map_unlocked(t->scratch.vma->obj, I915_MAP_WC);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

615

GEM_BUG_ON(verify_buffer(t, &t->scratch, prng));

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

619

&t->scratch, t->hole);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

628

i915_gem_object_unpin_map(t->scratch.vma->obj);

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1755

if (!vm->scratch[0]) {

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1760

vaddr = __px_vaddr(vm->scratch[0]);

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

191

const unsigned int nreal = obj->scratch / PAGE_SIZE;

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

194

GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

193

fill32_px(pt, vm->scratch[0]->encode);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

228

vm->scratch[0]->encode =

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

229

vm->pte_encode(px_dma(vm->scratch[0]),

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

23

dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

234

vm->scratch[1] = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

235

if (IS_ERR(vm->scratch[1])) {

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

236

ret = PTR_ERR(vm->scratch[1]);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

240

ret = map_pt_dma(vm, vm->scratch[1]);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

244

fill32_px(vm->scratch[1], vm->scratch[0]->encode);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

249

i915_gem_object_put(vm->scratch[1]);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

251

i915_gem_object_put(vm->scratch[0]);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

252

vm->scratch[0] = NULL;

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

79

const gen6_pte_t scratch_pte = vm->scratch[0]->encode;

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

243

const struct drm_i915_gem_object * const scratch = vm->scratch[lvl];

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

261

clear_pd_entry(pd, idx, scratch);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

293

vm->scratch[0]->encode,

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

300

if (release_pd_entry(pd, idx, pt, scratch))

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

351

fill_px(pt, vm->scratch[lvl]->encode);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

721

encode = vm->scratch[0]->encode;

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

843

vm->scratch[i] = i915_gem_object_get(clone->scratch[i]);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

853

if (i915_gem_object_is_lmem(vm->scratch[0]))

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

856

vm->scratch[0]->encode =

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

857

vm->pte_encode(px_dma(vm->scratch[0]),

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

877

fill_px(obj, vm->scratch[i - 1]->encode);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

880

vm->scratch[i] = obj;

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

887

i915_gem_object_put(vm->scratch[i]);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

888

vm->scratch[0] = NULL;

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

915

fill_px(pde, vm->scratch[1]->encode);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

948

fill_page_dma(px_base(pd), vm->scratch[vm->top]->encode, count);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1312

GEM_BUG_ON(!engine->gt->scratch);

drivers/gpu/drm/i915/gt/intel_ggtt.c

1014

i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);

drivers/gpu/drm/i915/gt/intel_ggtt.c

1016

i915_gem_object_unlock(ppgtt->vm.scratch[0]);

drivers/gpu/drm/i915/gt/intel_ggtt.c

1233

if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))

drivers/gpu/drm/i915/gt/intel_ggtt.c

1236

ggtt->vm.scratch[0]->encode =

drivers/gpu/drm/i915/gt/intel_ggtt.c

1237

ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),

drivers/gpu/drm/i915/gt/intel_ggtt.c

346

const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;

drivers/gpu/drm/i915/gt/intel_ggtt.c

513

gen8_set_pte(gte++, vm->scratch[0]->encode);

drivers/gpu/drm/i915/gt/intel_ggtt.c

522

gen8_set_pte(gte++, vm->scratch[0]->encode);

drivers/gpu/drm/i915/gt/intel_ggtt.c

536

gen8_pte_t scratch_pte = vm->scratch[0]->encode;

drivers/gpu/drm/i915/gt/intel_ggtt.c

581

const gen8_pte_t scratch_pte = vm->scratch[0]->encode;

drivers/gpu/drm/i915/gt/intel_ggtt.c

602

const gen8_pte_t scratch_pte = vm->scratch[0]->encode;

drivers/gpu/drm/i915/gt/intel_ggtt.c

665

iowrite32(vm->scratch[0]->encode, gte++);

drivers/gpu/drm/i915/gt/intel_ggtt.c

673

iowrite32(vm->scratch[0]->encode, gte++);

drivers/gpu/drm/i915/gt/intel_ggtt.c

772

scratch_pte = vm->scratch[0]->encode;

drivers/gpu/drm/i915/gt/intel_gt.c

492

gt->scratch = i915_vma_make_unshrinkable(vma);

drivers/gpu/drm/i915/gt/intel_gt.c

503

i915_vma_unpin_and_release(&gt->scratch, 0);

drivers/gpu/drm/i915/gt/intel_gt.h

158

return i915_ggtt_offset(gt->scratch) + field;

drivers/gpu/drm/i915/gt/intel_gt_types.h

235

struct i915_vma *scratch;

drivers/gpu/drm/i915/gt/intel_gtt.c

200

if (vm->scratch[0]->base.resv == &vm->_resv) {

drivers/gpu/drm/i915/gt/intel_gtt.c

201

return i915_gem_object_lock(vm->scratch[0], ww);

drivers/gpu/drm/i915/gt/intel_gtt.c

346

static void poison_scratch_page(struct drm_i915_gem_object *scratch)

drivers/gpu/drm/i915/gt/intel_gtt.c

348

void *vaddr = __px_vaddr(scratch);

drivers/gpu/drm/i915/gt/intel_gtt.c

355

memset(vaddr, val, scratch->base.size);

drivers/gpu/drm/i915/gt/intel_gtt.c

356

drm_clflush_virt_range(vaddr, scratch->base.size);

drivers/gpu/drm/i915/gt/intel_gtt.c

409

vm->scratch[0] = obj;

drivers/gpu/drm/i915/gt/intel_gtt.c

427

if (!vm->scratch[0])

drivers/gpu/drm/i915/gt/intel_gtt.c

431

i915_gem_object_put(vm->scratch[i]);

drivers/gpu/drm/i915/gt/intel_gtt.h

274

struct drm_i915_gem_object *scratch[4];

drivers/gpu/drm/i915/gt/intel_gtt.h

583

return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);

drivers/gpu/drm/i915/gt/intel_gtt.h

660

const struct drm_i915_gem_object * const scratch);

drivers/gpu/drm/i915/gt/intel_gtt.h

666

const struct drm_i915_gem_object * const scratch);

drivers/gpu/drm/i915/gt/intel_ppgtt.c

115

const struct drm_i915_gem_object * const scratch)

drivers/gpu/drm/i915/gt/intel_ppgtt.c

119

write_dma_entry(px_base(pd), idx, scratch->encode);

drivers/gpu/drm/i915/gt/intel_ppgtt.c

128

const struct drm_i915_gem_object * const scratch)

drivers/gpu/drm/i915/gt/intel_ppgtt.c

137

clear_pd_entry(pd, idx, scratch);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4195

struct i915_vma *scratch;

drivers/gpu/drm/i915/gt/selftest_execlists.c

4201

scratch =

drivers/gpu/drm/i915/gt/selftest_execlists.c

4204

if (IS_ERR(scratch))

drivers/gpu/drm/i915/gt/selftest_execlists.c

4205

return PTR_ERR(scratch);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4207

err = i915_vma_sync(scratch);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4247

*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4267

cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4282

i915_gem_object_unpin_map(scratch->obj);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4293

i915_vma_unpin_and_release(&scratch, 0);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1040

*cs++ = lower_32_bits(i915_vma_offset(scratch) + x);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1041

*cs++ = upper_32_bits(i915_vma_offset(scratch) + x);

drivers/gpu/drm/i915/gt/selftest_lrc.c

404

struct i915_vma *scratch)

drivers/gpu/drm/i915/gt/selftest_lrc.c

425

err = i915_gem_object_lock(scratch->obj, &ww);

drivers/gpu/drm/i915/gt/selftest_lrc.c

446

*cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);

drivers/gpu/drm/i915/gt/selftest_lrc.c

453

*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);

drivers/gpu/drm/i915/gt/selftest_lrc.c

456

err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);

drivers/gpu/drm/i915/gt/selftest_lrc.c

471

cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);

drivers/gpu/drm/i915/gt/selftest_lrc.c

486

i915_gem_object_unpin_map(scratch->obj);

drivers/gpu/drm/i915/gt/selftest_lrc.c

507

struct i915_vma *scratch;

drivers/gpu/drm/i915/gt/selftest_lrc.c

516

scratch = create_scratch(gt);

drivers/gpu/drm/i915/gt/selftest_lrc.c

517

if (IS_ERR(scratch))

drivers/gpu/drm/i915/gt/selftest_lrc.c

518

return PTR_ERR(scratch);

drivers/gpu/drm/i915/gt/selftest_lrc.c

521

err = __live_lrc_state(engine, scratch);

drivers/gpu/drm/i915/gt/selftest_lrc.c

529

i915_vma_unpin_and_release(&scratch, 0);

drivers/gpu/drm/i915/gt/selftest_lrc.c

565

__gpr_read(struct intel_context *ce, struct i915_vma *scratch, u32 *slot)

drivers/gpu/drm/i915/gt/selftest_lrc.c

599

*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);

drivers/gpu/drm/i915/gt/selftest_lrc.c

603

err = igt_vma_move_to_active_unlocked(scratch, rq, EXEC_OBJECT_WRITE);

drivers/gpu/drm/i915/gt/selftest_lrc.c

616

struct i915_vma *scratch,

drivers/gpu/drm/i915/gt/selftest_lrc.c

637

rq = __gpr_read(ce, scratch, slot);

drivers/gpu/drm/i915/gt/selftest_lrc.c

669

cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);

drivers/gpu/drm/i915/gt/selftest_lrc.c

686

i915_gem_object_unpin_map(scratch->obj);

drivers/gpu/drm/i915/gt/selftest_lrc.c

701

struct i915_vma *scratch;

drivers/gpu/drm/i915/gt/selftest_lrc.c

710

scratch = create_scratch(gt);

drivers/gpu/drm/i915/gt/selftest_lrc.c

711

if (IS_ERR(scratch))

drivers/gpu/drm/i915/gt/selftest_lrc.c

712

return PTR_ERR(scratch);

drivers/gpu/drm/i915/gt/selftest_lrc.c

717

err = __live_lrc_gpr(engine, scratch, false);

drivers/gpu/drm/i915/gt/selftest_lrc.c

721

err = __live_lrc_gpr(engine, scratch, true);

drivers/gpu/drm/i915/gt/selftest_lrc.c

733

i915_vma_unpin_and_release(&scratch, 0);

drivers/gpu/drm/i915/gt/selftest_lrc.c

973

store_context(struct intel_context *ce, struct i915_vma *scratch)

drivers/gpu/drm/i915/gt/selftest_mocs.c

20

struct i915_vma *scratch;

drivers/gpu/drm/i915/gt/selftest_mocs.c

220

struct i915_vma *vma = arg->scratch;

drivers/gpu/drm/i915/gt/selftest_mocs.c

79

arg->scratch =

drivers/gpu/drm/i915/gt/selftest_mocs.c

81

if (IS_ERR(arg->scratch))

drivers/gpu/drm/i915/gt/selftest_mocs.c

82

return PTR_ERR(arg->scratch);

drivers/gpu/drm/i915/gt/selftest_mocs.c

84

arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB);

drivers/gpu/drm/i915/gt/selftest_mocs.c

93

i915_vma_unpin_and_release(&arg->scratch, 0);

drivers/gpu/drm/i915/gt/selftest_mocs.c

99

i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1061

struct i915_vma *scratch[2];

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1076

client[i].scratch[0] =

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1078

if (IS_ERR(client[i].scratch[0])) {

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1079

err = PTR_ERR(client[i].scratch[0]);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1083

client[i].scratch[1] =

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1085

if (IS_ERR(client[i].scratch[1])) {

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1086

err = PTR_ERR(client[i].scratch[1]);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1087

i915_vma_unpin_and_release(&client[i].scratch[0], 0);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1114

err = read_whitelisted_registers(ce[0], client[0].scratch[0]);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1124

err = read_whitelisted_registers(ce[1], client[1].scratch[0]);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1130

client[0].scratch[0],

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1131

client[1].scratch[0],

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1137

err = read_whitelisted_registers(ce[0], client[0].scratch[1]);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1143

client[0].scratch[0],

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1144

client[0].scratch[1],

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1155

i915_vma_unpin_and_release(&client[i].scratch[1], 0);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1156

i915_vma_unpin_and_release(&client[i].scratch[0], 0);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

503

struct i915_vma *scratch;

drivers/gpu/drm/i915/gt/selftest_workarounds.c

509

scratch = __vm_create_scratch_for_read_pinned(ce->vm, sz);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

510

if (IS_ERR(scratch))

drivers/gpu/drm/i915/gt/selftest_workarounds.c

511

return PTR_ERR(scratch);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

522

u64 addr = i915_vma_offset(scratch);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

540

err = i915_gem_object_lock(scratch->obj, &ww);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

554

results = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

604

GEM_BUG_ON(idx * sizeof(u32) > scratch->size);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

635

err = i915_vma_move_to_active(scratch, rq,

drivers/gpu/drm/i915/gt/selftest_workarounds.c

730

i915_gem_object_unpin_map(scratch->obj);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

752

i915_vma_unpin_and_release(&scratch, 0);

drivers/gpu/drm/i915/i915_perf.c

1372

struct i915_vma *scratch;

drivers/gpu/drm/i915/i915_perf.c

1376

scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);

drivers/gpu/drm/i915/i915_perf.c

1377

if (IS_ERR(scratch))

drivers/gpu/drm/i915/i915_perf.c

1378

return PTR_ERR(scratch);

drivers/gpu/drm/i915/i915_perf.c

1380

err = i915_vma_sync(scratch);

drivers/gpu/drm/i915/i915_perf.c

1385

i915_ggtt_offset(scratch));

drivers/gpu/drm/i915/i915_perf.c

1389

val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);

drivers/gpu/drm/i915/i915_perf.c

1396

i915_gem_object_unpin_map(scratch->obj);

drivers/gpu/drm/i915/i915_perf.c

1399

i915_vma_unpin_and_release(&scratch, 0);

drivers/gpu/drm/i915/selftests/i915_perf.c

296

void *scratch;

drivers/gpu/drm/i915/selftests/i915_perf.c

316

scratch = __px_vaddr(ce->vm->scratch[0]);

drivers/gpu/drm/i915/selftests/i915_perf.c

317

memset(scratch, POISON_FREE, PAGE_SIZE);

drivers/gpu/drm/i915/selftests/i915_perf.c

405

if (memchr_inv(scratch, POISON_FREE, PAGE_SIZE)) {

drivers/gpu/drm/i915/selftests/i915_perf.c

407

igt_hexdump(scratch, 4096);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1113

u32 scratch[] = {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1123

return adreno_fault_handler(gpu, iova, flags, info, block, scratch);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1826

u32 scratch[] = {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1836

return adreno_fault_handler(gpu, iova, flags, info, block, scratch);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

871

u32 scratch[] = {

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

881

return adreno_fault_handler(gpu, iova, flags, info, block, scratch);

drivers/gpu/drm/msm/adreno/adreno_gpu.c

285

u32 scratch[4])

drivers/gpu/drm/msm/adreno/adreno_gpu.c

316

scratch[0], scratch[1], scratch[2], scratch[3]);

drivers/gpu/drm/msm/adreno/adreno_gpu.c

332

scratch[0], scratch[1], scratch[2], scratch[3]);

drivers/gpu/drm/msm/adreno/adreno_gpu.h

662

u32 scratch[4]);

drivers/gpu/drm/radeon/atom.c

1434

ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);

drivers/gpu/drm/radeon/atom.c

1435

if (!ctx->scratch)

drivers/gpu/drm/radeon/atom.c

291

val = gctx->scratch[(gctx->fb_base / 4) + idx];

drivers/gpu/drm/radeon/atom.c

554

gctx->scratch[(gctx->fb_base / 4) + idx] = val;

drivers/gpu/drm/radeon/atom.h

141

uint32_t *scratch;

drivers/gpu/drm/radeon/atombios_dp.c

103

base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);

drivers/gpu/drm/radeon/atombios_i2c.c

53

base = (unsigned char *)rdev->mode_info.atom_context->scratch;

drivers/gpu/drm/radeon/cik.c

3426

rdev->scratch.num_reg = 7;

drivers/gpu/drm/radeon/cik.c

3427

rdev->scratch.reg_base = SCRATCH_REG0;

drivers/gpu/drm/radeon/cik.c

3428

for (i = 0; i < rdev->scratch.num_reg; i++) {

drivers/gpu/drm/radeon/cik.c

3429

rdev->scratch.free[i] = true;

drivers/gpu/drm/radeon/cik.c

3430

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

drivers/gpu/drm/radeon/cik.c

3447

uint32_t scratch;

drivers/gpu/drm/radeon/cik.c

3452

r = radeon_scratch_get(rdev, &scratch);

drivers/gpu/drm/radeon/cik.c

3457

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/radeon/cik.c

3461

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/cik.c

3465

radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));

drivers/gpu/drm/radeon/cik.c

3470

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/cik.c

3479

ring->idx, scratch, tmp);

drivers/gpu/drm/radeon/cik.c

3482

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/cik.c

3772

uint32_t scratch;

drivers/gpu/drm/radeon/cik.c

3777

r = radeon_scratch_get(rdev, &scratch);

drivers/gpu/drm/radeon/cik.c

3782

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/radeon/cik.c

3786

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/cik.c

3790

ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);

drivers/gpu/drm/radeon/cik.c

3795

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/cik.c

3804

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/cik.c

3809

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/cik.c

3815

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/cik.c

3824

scratch, tmp);

drivers/gpu/drm/radeon/cik.c

3827

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/r100.c

3672

uint32_t scratch;

drivers/gpu/drm/radeon/r100.c

3677

r = radeon_scratch_get(rdev, &scratch);

drivers/gpu/drm/radeon/r100.c

3682

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/radeon/r100.c

3686

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/r100.c

3689

radeon_ring_write(ring, PACKET0(scratch, 0));

drivers/gpu/drm/radeon/r100.c

3693

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r100.c

3703

scratch, tmp);

drivers/gpu/drm/radeon/r100.c

3706

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/r100.c

3728

uint32_t scratch;

drivers/gpu/drm/radeon/r100.c

3733

r = radeon_scratch_get(rdev, &scratch);

drivers/gpu/drm/radeon/r100.c

3738

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/radeon/r100.c

3744

ib.ptr[0] = PACKET0(scratch, 0);

drivers/gpu/drm/radeon/r100.c

3770

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r100.c

3780

scratch, tmp);

drivers/gpu/drm/radeon/r100.c

3786

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/r600.c

2815

rdev->scratch.num_reg = 7;

drivers/gpu/drm/radeon/r600.c

2816

rdev->scratch.reg_base = SCRATCH_REG0;

drivers/gpu/drm/radeon/r600.c

2817

for (i = 0; i < rdev->scratch.num_reg; i++) {

drivers/gpu/drm/radeon/r600.c

2818

rdev->scratch.free[i] = true;

drivers/gpu/drm/radeon/r600.c

2819

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

drivers/gpu/drm/radeon/r600.c

2825

uint32_t scratch;

drivers/gpu/drm/radeon/r600.c

2830

r = radeon_scratch_get(rdev, &scratch);

drivers/gpu/drm/radeon/r600.c

2835

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/radeon/r600.c

2839

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/r600.c

2843

radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));

drivers/gpu/drm/radeon/r600.c

2847

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r600.c

2856

ring->idx, scratch, tmp);

drivers/gpu/drm/radeon/r600.c

2859

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/r600.c

3399

uint32_t scratch;

drivers/gpu/drm/radeon/r600.c

3404

r = radeon_scratch_get(rdev, &scratch);

drivers/gpu/drm/radeon/r600.c

3409

WREG32(scratch, 0xCAFEDEAD);

drivers/gpu/drm/radeon/r600.c

3416

ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);

drivers/gpu/drm/radeon/r600.c

3436

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r600.c

3445

scratch, tmp);

drivers/gpu/drm/radeon/r600.c

3451

radeon_scratch_free(rdev, scratch);

drivers/gpu/drm/radeon/radeon.h

2362

struct radeon_scratch scratch;

drivers/gpu/drm/radeon/radeon_device.c

1025

kfree(rdev->mode_info.atom_context->scratch);

drivers/gpu/drm/radeon/radeon_device.c

273

rdev->scratch.num_reg = 5;

drivers/gpu/drm/radeon/radeon_device.c

275

rdev->scratch.num_reg = 7;

drivers/gpu/drm/radeon/radeon_device.c

277

rdev->scratch.reg_base = RADEON_SCRATCH_REG0;

drivers/gpu/drm/radeon/radeon_device.c

278

for (i = 0; i < rdev->scratch.num_reg; i++) {

drivers/gpu/drm/radeon/radeon_device.c

279

rdev->scratch.free[i] = true;

drivers/gpu/drm/radeon/radeon_device.c

280

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

drivers/gpu/drm/radeon/radeon_device.c

297

for (i = 0; i < rdev->scratch.num_reg; i++) {

drivers/gpu/drm/radeon/radeon_device.c

298

if (rdev->scratch.free[i]) {

drivers/gpu/drm/radeon/radeon_device.c

299

rdev->scratch.free[i] = false;

drivers/gpu/drm/radeon/radeon_device.c

300

*reg = rdev->scratch.reg[i];

drivers/gpu/drm/radeon/radeon_device.c

319

for (i = 0; i < rdev->scratch.num_reg; i++) {

drivers/gpu/drm/radeon/radeon_device.c

320

if (rdev->scratch.reg[i] == reg) {

drivers/gpu/drm/radeon/radeon_device.c

321

rdev->scratch.free[i] = true;

drivers/gpu/drm/radeon/radeon_fence.c

788

rdev->scratch.reg_base;

drivers/gpu/drm/radeon/si.c

3342

rdev->scratch.num_reg = 7;

drivers/gpu/drm/radeon/si.c

3343

rdev->scratch.reg_base = SCRATCH_REG0;

drivers/gpu/drm/radeon/si.c

3344

for (i = 0; i < rdev->scratch.num_reg; i++) {

drivers/gpu/drm/radeon/si.c

3345

rdev->scratch.free[i] = true;

drivers/gpu/drm/radeon/si.c

3346

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

drivers/gpu/drm/xe/xe_exec_queue.c

1651

int xe_exec_queue_contexts_hwsp_rebase(struct xe_exec_queue *q, void *scratch)

drivers/gpu/drm/xe/xe_exec_queue.c

1664

xe_lrc_update_memirq_regs_with_address(lrc, q->hwe, scratch);

drivers/gpu/drm/xe/xe_exec_queue.c

1666

err = xe_lrc_setup_wa_bb_with_scratch(lrc, q->hwe, scratch);

drivers/gpu/drm/xe/xe_exec_queue.h

160

int xe_exec_queue_contexts_hwsp_rebase(struct xe_exec_queue *q, void *scratch);

drivers/gpu/drm/xe/xe_ggtt.c

209

if (ggtt->scratch)

drivers/gpu/drm/xe/xe_ggtt.c

210

scratch_pte = xe_bo_addr(ggtt->scratch, 0, XE_PAGE_SIZE) |

drivers/gpu/drm/xe/xe_ggtt.c

211

ggtt->pt_ops->pte_encode_flags(ggtt->scratch,

drivers/gpu/drm/xe/xe_ggtt.c

270

ggtt->scratch = NULL;

drivers/gpu/drm/xe/xe_ggtt.c

495

ggtt->scratch = xe_managed_bo_create_pin_map(xe, ggtt->tile, XE_PAGE_SIZE, flags);

drivers/gpu/drm/xe/xe_ggtt.c

496

if (IS_ERR(ggtt->scratch)) {

drivers/gpu/drm/xe/xe_ggtt.c

497

err = PTR_ERR(ggtt->scratch);

drivers/gpu/drm/xe/xe_ggtt.c

501

xe_map_memset(xe, &ggtt->scratch->vmap, 0, 0, xe_bo_size(ggtt->scratch));

drivers/gpu/drm/xe/xe_ggtt.c

507

ggtt->scratch = NULL;

drivers/gpu/drm/xe/xe_ggtt_types.h

42

struct xe_bo *scratch;

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1254

void *buf = gt->sriov.vf.migration.scratch;

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1441

gt->sriov.vf.migration.scratch = buf;

drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h

56

void *scratch;

drivers/gpu/drm/xe/xe_guc_submit.c

3381

int xe_guc_contexts_hwsp_rebase(struct xe_guc *guc, void *scratch)

drivers/gpu/drm/xe/xe_guc_submit.c

3393

err = xe_exec_queue_contexts_hwsp_rebase(q, scratch);

drivers/gpu/drm/xe/xe_guc_submit.h

57

int xe_guc_contexts_hwsp_rebase(struct xe_guc *guc, void *scratch);

drivers/gpu/drm/xe/xe_lrc.c

1286

int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe, u32 *scratch)

drivers/gpu/drm/xe/xe_lrc.c

1298

.buffer = scratch,

drivers/gpu/drm/xe/xe_lrc.h

152

u32 *scratch);

drivers/infiniband/hw/irdma/cm.c

344

sqbuf->scratch = cm_node;

drivers/infiniband/hw/irdma/cm.c

461

sqbuf->scratch = cm_node;

drivers/infiniband/hw/irdma/ctrl.c

1156

static int irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

1162

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

1192

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

1197

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

1228

static int irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

1235

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

1452

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

1470

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

1519

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

1553

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

1613

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

1620

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

1653

struct irdma_mw_alloc_info *info, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

1661

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

192

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

197

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

227

static int irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

233

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2464

u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

2472

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2511

bool alloc, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

2516

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2547

struct irdma_up_info *info, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

2553

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2590

enum irdma_ws_node_op node_op, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

2595

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

262

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

2631

struct irdma_qp_flush_info *info, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

2655

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

267

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2714

struct irdma_gen_ae_info *info, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

2723

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2755

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

2762

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2795

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

2804

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2833

u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

2838

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2863

u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

2868

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2931

static int irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

2945

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

2995

int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

3002

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

3057

struct irdma_modify_cq_info *info, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

3071

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

310

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

318

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

3200

bool first, u64 *scratch,

drivers/infiniband/hw/irdma/ctrl.c

3206

*scratch = 0;

drivers/infiniband/hw/irdma/ctrl.c

3214

*scratch = ooo_op->scratch;

drivers/infiniband/hw/irdma/ctrl.c

3224

if (first && !*scratch)

drivers/infiniband/hw/irdma/ctrl.c

3244

u64 scratch = 0;

drivers/infiniband/hw/irdma/ctrl.c

3247

scratch = ooo_op->scratch;

drivers/infiniband/hw/irdma/ctrl.c

3256

return scratch;

drivers/infiniband/hw/irdma/ctrl.c

3803

__le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

3824

cqp->scratch_array[*wqe_idx] = scratch;

drivers/infiniband/hw/irdma/ctrl.c

3916

ooo_op->scratch = info->scratch;

drivers/infiniband/hw/irdma/ctrl.c

3945

info->scratch = 0;

drivers/infiniband/hw/irdma/ctrl.c

3952

info->scratch = ooo_op->scratch;

drivers/infiniband/hw/irdma/ctrl.c

3959

if (!info->scratch)

drivers/infiniband/hw/irdma/ctrl.c

4012

info->scratch = cqp->scratch_array[wqe_idx];

drivers/infiniband/hw/irdma/ctrl.c

4116

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

4121

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4171

static int irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

4181

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4232

static int irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

4242

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4320

static int irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

4328

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4394

int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

4401

ret_code = irdma_sc_ceq_create(ceq, scratch, true);

drivers/infiniband/hw/irdma/ctrl.c

4414

int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

4421

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4568

static int irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

4576

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4610

static int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

4624

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

4920

int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

4925

ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq);

drivers/infiniband/hw/irdma/ctrl.c

4945

int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

4954

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

496

static int irdma_sc_srq_create(struct irdma_sc_srq *srq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

509

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

5123

struct irdma_update_sds_info *info, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

5133

wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);

drivers/infiniband/hw/irdma/ctrl.c

5202

struct irdma_update_sds_info *info, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

5207

ret_code = cqp_sds_wqe_fill(cqp, info, scratch);

drivers/infiniband/hw/irdma/ctrl.c

5245

int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

5253

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

5344

struct irdma_dma_mem *buf, u64 scratch)

drivers/infiniband/hw/irdma/ctrl.c

5351

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

560

struct irdma_modify_srq_info *info, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

573

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

6031

pcmdinfo->in.u.ceq_destroy.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6036

pcmdinfo->in.u.aeq_destroy.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6042

pcmdinfo->in.u.ceq_create.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6047

pcmdinfo->in.u.aeq_create.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6053

pcmdinfo->in.u.qp_upload_context.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6058

pcmdinfo->in.u.cq_create.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6065

pcmdinfo->in.u.cq_modify.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6070

pcmdinfo->in.u.cq_destroy.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6076

pcmdinfo->in.u.qp_flush_wqes.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6082

pcmdinfo->in.u.gen_ae.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6088

pcmdinfo->in.u.manage_push_page.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6094

pcmdinfo->in.u.update_pe_sds.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6101

pcmdinfo->in.u.manage_hmc_pm.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6107

pcmdinfo->in.u.suspend_resume.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6112

pcmdinfo->in.u.suspend_resume.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6118

pcmdinfo->in.u.query_fpm_val.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6126

pcmdinfo->in.u.commit_fpm_val.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6139

pcmdinfo->in.u.stats_manage.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6144

pcmdinfo->in.u.stats_gather.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6150

pcmdinfo->in.u.ws_node.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6156

pcmdinfo->in.u.ws_node.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6162

pcmdinfo->in.u.ws_node.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6167

pcmdinfo->in.u.up_map.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6172

pcmdinfo->in.u.query_rdma.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6176

pcmdinfo->in.u.del_arp_cache_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6183

pcmdinfo->in.u.manage_apbvt_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6189

pcmdinfo->in.u.manage_qhash_table_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6195

pcmdinfo->in.u.qp_modify.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6201

pcmdinfo->in.u.qp_create.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6206

pcmdinfo->in.u.qp_destroy.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6214

pcmdinfo->in.u.alloc_stag.scratch,

drivers/infiniband/hw/irdma/ctrl.c

622

static int irdma_sc_srq_destroy(struct irdma_sc_srq *srq, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

6220

pcmdinfo->in.u.mr_reg_non_shared.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6226

pcmdinfo->in.u.dealloc_stag.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6232

pcmdinfo->in.u.mw_alloc.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6238

pcmdinfo->in.u.add_arp_cache_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6243

pcmdinfo->in.u.alloc_local_mac_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6249

pcmdinfo->in.u.add_local_mac_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6254

pcmdinfo->in.u.del_local_mac_entry.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6262

pcmdinfo->in.u.ah_create.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6267

pcmdinfo->in.u.ah_destroy.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6272

pcmdinfo->in.u.mc_create.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6277

pcmdinfo->in.u.mc_destroy.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6282

pcmdinfo->in.u.mc_modify.scratch);

drivers/infiniband/hw/irdma/ctrl.c

6286

pcmdinfo->in.u.srq_create.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6292

pcmdinfo->in.u.srq_modify.scratch,

drivers/infiniband/hw/irdma/ctrl.c

6297

pcmdinfo->in.u.srq_destroy.scratch,

drivers/infiniband/hw/irdma/ctrl.c

631

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

660

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

671

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

711

u64 scratch, bool post_sq)

drivers/infiniband/hw/irdma/ctrl.c

720

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/ctrl.c

780

int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,

drivers/infiniband/hw/irdma/ctrl.c

788

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/hw.c

2220

(unsigned long)info.scratch;

drivers/infiniband/hw/irdma/hw.c

2338

cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

2370

cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

2373

cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

2405

cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

2440

cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

2546

cqp_info->in.u.add_arp_cache_entry.scratch =

drivers/infiniband/hw/irdma/hw.c

255

u64 scratch;

drivers/infiniband/hw/irdma/hw.c

2551

cqp_info->in.u.del_arp_cache_entry.scratch =

drivers/infiniband/hw/irdma/hw.c

260

&scratch, &sw_def_info);

drivers/infiniband/hw/irdma/hw.c

261

while (scratch) {

drivers/infiniband/hw/irdma/hw.c

263

(struct irdma_cqp_request *)(uintptr_t)scratch;

drivers/infiniband/hw/irdma/hw.c

2654

cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

267

&scratch, &sw_def_info);

drivers/infiniband/hw/irdma/hw.c

2731

cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/hw.c

2778

cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req;

drivers/infiniband/hw/irdma/hw.c

2836

cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/protos.h

20

__le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch);

drivers/infiniband/hw/irdma/protos.h

78

int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/puda.c

447

qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch;

drivers/infiniband/hw/irdma/puda.c

531

info.scratch = buf;

drivers/infiniband/hw/irdma/puda.h

53

void *scratch;

drivers/infiniband/hw/irdma/puda.h

61

void *scratch;

drivers/infiniband/hw/irdma/type.h

1335

int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1337

int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq);

drivers/infiniband/hw/irdma/type.h

1343

int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch);

drivers/infiniband/hw/irdma/type.h

1346

int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq);

drivers/infiniband/hw/irdma/type.h

1366

bool first, u64 *scratch,

drivers/infiniband/hw/irdma/type.h

1379

struct irdma_create_qp_info *info, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1381

int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1384

struct irdma_qp_flush_info *info, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1388

struct irdma_modify_qp_info *info, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1398

int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq);

drivers/infiniband/hw/irdma/type.h

1401

int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1413

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1419

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1424

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1431

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1438

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1443

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1449

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1455

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1461

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1467

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1473

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1478

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1485

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1490

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1497

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1503

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1509

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1515

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1520

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1525

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1530

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1535

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1541

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1547

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1555

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1563

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1569

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1575

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1581

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1587

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1593

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1599

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1605

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1611

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1617

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1623

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1629

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1635

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1641

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1647

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1652

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1658

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1663

u64 scratch;

drivers/infiniband/hw/irdma/type.h

1676

__le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch,

drivers/infiniband/hw/irdma/type.h

1684

static inline __le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch)

drivers/infiniband/hw/irdma/type.h

1688

return irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);

drivers/infiniband/hw/irdma/type.h

421

u64 scratch;

drivers/infiniband/hw/irdma/type.h

825

u64 scratch;

drivers/infiniband/hw/irdma/uda.c

117

u64 scratch)

drivers/infiniband/hw/irdma/uda.c

126

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/uda.c

21

u32 op, u64 scratch)

drivers/infiniband/hw/irdma/uda.c

26

wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

drivers/infiniband/hw/irdma/uda.h

40

u32 op, u64 scratch);

drivers/infiniband/hw/irdma/uda.h

43

u64 scratch);

drivers/infiniband/hw/irdma/uda.h

51

struct irdma_ah_info *info, u64 scratch)

drivers/infiniband/hw/irdma/uda.h

54

scratch);

drivers/infiniband/hw/irdma/uda.h

58

struct irdma_ah_info *info, u64 scratch)

drivers/infiniband/hw/irdma/uda.h

61

scratch);

drivers/infiniband/hw/irdma/uda.h

66

u64 scratch)

drivers/infiniband/hw/irdma/uda.h

69

scratch);

drivers/infiniband/hw/irdma/uda.h

74

u64 scratch)

drivers/infiniband/hw/irdma/uda.h

77

scratch);

drivers/infiniband/hw/irdma/uda.h

82

u64 scratch)

drivers/infiniband/hw/irdma/uda.h

85

scratch);

drivers/infiniband/hw/irdma/utils.c

1046

cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1079

cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1114

cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1193

cqp_info->in.u.srq_destroy.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1217

cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1268

cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1302

cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1351

cqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1756

cqp_info->in.u.stats_gather.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1795

cqp_info->in.u.stats_manage.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1827

cqp_info->in.u.ceq_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1857

cqp_info->in.u.aeq_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1896

cqp_info->in.u.ws_node.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1951

cqp_info->in.u.ah_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

1955

cqp_info->in.u.ah_destroy.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

534

u64 scratch;

drivers/infiniband/hw/irdma/utils.c

537

while ((scratch = irdma_sc_cqp_cleanup_handler(dev)))

drivers/infiniband/hw/irdma/utils.c

539

(uintptr_t)scratch);

drivers/infiniband/hw/irdma/utils.c

901

cqp_info->in.u.update_pe_sds.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/utils.c

931

cqp_info->in.u.suspend_resume.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

2135

cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

2235

cqp_info->in.u.srq_modify.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

2408

cqp_info->in.u.srq_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

264

cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

2654

cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

3030

cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

3092

cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

3129

cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

3300

cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

3671

cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

4763

cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request;

drivers/infiniband/hw/irdma/verbs.c

783

cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;

drivers/input/touchscreen/ads7846.c

332

u16 scratch;

drivers/input/touchscreen/ads7846.c

373

req->xfer[1].rx_buf = &req->scratch;

drivers/input/touchscreen/ads7846.c

406

req->xfer[5].rx_buf = &req->scratch;

drivers/input/touchscreen/ads7846.c

411

req->scratch = 0;

drivers/input/touchscreen/ads7846.c

412

req->xfer[6].tx_buf = &req->scratch;

drivers/input/touchscreen/ads7846.c

416

req->xfer[7].rx_buf = &req->scratch;

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1051

u32 (*scratch)(u32 width, u32 height, bool is_interlaced);

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1058

u32 (*scratch)(u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1067

.scratch = h264d_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1073

.scratch = h265d_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1079

.scratch = vpxd_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1085

.scratch = vpxd_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1091

.scratch = mpeg2d_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1097

.scratch = h264e_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1104

.scratch = h265e_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1111

.scratch = vp8e_scratch_size,

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1245

bufreq->size = dec_ops->scratch(width, height, is_interlaced);

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1310

bufreq->size = enc_ops->scratch(width, height, work_mode,

drivers/media/platform/renesas/rcar-vin/rcar-dma.c

1355

vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,

drivers/media/platform/renesas/rcar-vin/rcar-dma.c

1357

if (!vin->scratch)

drivers/media/platform/renesas/rcar-vin/rcar-dma.c

1366

dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,

drivers/media/platform/renesas/rcar-vin/rcar-dma.c

1427

dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,

drivers/media/platform/renesas/rcar-vin/rcar-vin.h

193

void *scratch;

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h

162

void *scratch;

drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c

777

cru->scratch = dma_alloc_coherent(cru->dev, cru->format.sizeimage,

drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c

779

if (!cru->scratch) {

drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c

800

dma_free_coherent(cru->dev, cru->format.sizeimage, cru->scratch,

drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c

825

cru->scratch, cru->scratch_phys);

drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h

126

} scratch;

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

255

csi->scratch.size = 0;

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

257

csi->scratch.size += csi->fmt.plane_fmt[i].sizeimage;

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

259

csi->scratch.vaddr = dma_alloc_coherent(csi->dev,

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

260

csi->scratch.size,

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

261

&csi->scratch.paddr,

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

263

if (!csi->scratch.vaddr) {

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

336

dma_free_coherent(csi->dev, csi->scratch.size, csi->scratch.vaddr,

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

337

csi->scratch.paddr);

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

364

dma_free_coherent(csi->dev, csi->scratch.size, csi->scratch.vaddr,

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

365

csi->scratch.paddr);

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

96

dma_addr_t addr = csi->scratch.paddr;

drivers/media/rc/serial_ir.c

398

u8 scratch, scratch2, scratch3;

drivers/media/rc/serial_ir.c

404

scratch = sinp(UART_IER);

drivers/media/rc/serial_ir.c

415

soutp(UART_IER, scratch);

drivers/mmc/core/mmc_test.c

146

u8 scratch[BUFFER_SIZE];

drivers/mmc/core/mmc_test.c

929

test->scratch[i] = i;

drivers/mmc/core/mmc_test.c

931

memset(test->scratch, 0, BUFFER_SIZE);

drivers/mmc/core/mmc_test.c

933

sg_copy_from_buffer(sg, sg_len, test->scratch, BUFFER_SIZE);

drivers/mmc/core/mmc_test.c

978

sg_copy_to_buffer(sg, sg_len, test->scratch, BUFFER_SIZE);

drivers/mmc/core/mmc_test.c

980

if (test->scratch[i] != (u8)i)

drivers/mmc/host/mmc_spi.c

122

struct scratch *data;

drivers/mmc/host/mmc_spi.c

402

struct scratch *data = host->data;

drivers/mmc/host/mmc_spi.c

512

struct scratch *scratch = host->data;

drivers/mmc/host/mmc_spi.c

524

scratch->data_token = SPI_TOKEN_MULTI_WRITE;

drivers/mmc/host/mmc_spi.c

526

scratch->data_token = SPI_TOKEN_SINGLE;

drivers/mmc/host/mmc_spi.c

527

t->tx_buf = &scratch->data_token;

drivers/mmc/host/mmc_spi.c

545

t->tx_buf = &scratch->crc_val;

drivers/mmc/host/mmc_spi.c

548

t->rx_buf = &scratch->crc_val;

drivers/mmc/host/mmc_spi.c

569

t->len = sizeof(scratch->status);

drivers/mmc/host/mmc_spi.c

571

t->rx_buf = scratch->status;

drivers/mmc/host/mmc_spi.c

595

struct scratch *scratch = host->data;

drivers/mmc/host/mmc_spi.c

599

scratch->crc_val = cpu_to_be16(crc_itu_t(0, t->tx_buf, t->len));

drivers/mmc/host/mmc_spi.c

619

pattern = get_unaligned_be32(scratch->status);

drivers/mmc/host/mmc_spi.c

650

scratch->status[0], status);

drivers/mmc/host/mmc_spi.c

659

for (i = 4; i < sizeof(scratch->status); i++) {

drivers/mmc/host/mmc_spi.c

661

if (scratch->status[i] & 0x01)

drivers/mmc/host/mmc_spi.c

689

struct scratch *scratch = host->data;

drivers/mmc/host/mmc_spi.c

699

status = scratch->status[0];

drivers/mmc/host/mmc_spi.c

737

cp = (u8 *) &scratch->crc_val;

drivers/mmc/host/mmc_spi.c

748

be16_to_cpus(&scratch->crc_val);

drivers/mmc/host/mmc_spi.c

749

if (scratch->crc_val != crc) {

drivers/mmc/host/mmc_spi.c

752

scratch->crc_val, crc, t->len);

drivers/mmc/host/mmc_spi.c

849

struct scratch *scratch = host->data;

drivers/mmc/host/mmc_spi.c

851

const unsigned statlen = sizeof(scratch->status);

drivers/mmc/host/mmc_spi.c

864

memset(scratch->status, 0xff, statlen);

drivers/mmc/host/mmc_spi.c

865

scratch->status[0] = SPI_TOKEN_STOP_TRAN;

drivers/mmc/host/mmc_spi.c

882

if (scratch->status[tmp] != 0)

drivers/mmc/host/sdhci-pci-core.c

1372

u8 scratch;

drivers/mmc/host/sdhci-pci-core.c

1375

ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);

drivers/mmc/host/sdhci-pci-core.c

1384

scratch |= 0x47;

drivers/mmc/host/sdhci-pci-core.c

1386

scratch &= ~0x47;

drivers/mmc/host/sdhci-pci-core.c

1388

ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);

drivers/mmc/host/sdhci-pci-core.c

1459

u8 scratch;

drivers/mmc/host/sdhci-pci-core.c

1461

scratch = readb(host->ioaddr + 0xC0);

drivers/mmc/host/sdhci-pci-core.c

1464

scratch |= 0x01;

drivers/mmc/host/sdhci-pci-core.c

1466

scratch &= ~0x01;

drivers/mmc/host/sdhci-pci-core.c

1468

writeb(scratch, host->ioaddr + 0xC0);

drivers/mmc/host/sdhci-pci-core.c

2252

u32 scratch;

drivers/mmc/host/sdhci-pci-core.c

2255

scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);

drivers/mmc/host/sdhci-pci-core.c

2256

if (scratch == (u32)-1)

drivers/mmc/host/sdhci-pci-o2micro.c

1018

O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

1021

scratch |= 0x80;

drivers/mmc/host/sdhci-pci-o2micro.c

1022

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

1029

ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

1032

scratch &= 0x7f;

drivers/mmc/host/sdhci-pci-o2micro.c

1033

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

1058

ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

1061

scratch |= 0x80;

drivers/mmc/host/sdhci-pci-o2micro.c

1062

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

112

u16 scratch;

drivers/mmc/host/sdhci-pci-o2micro.c

132

scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);

drivers/mmc/host/sdhci-pci-o2micro.c

133

if (scratch & O2_PLL_LOCK_STATUS)

drivers/mmc/host/sdhci-pci-o2micro.c

321

u16 scratch = 0;

drivers/mmc/host/sdhci-pci-o2micro.c

338

scratch = sdhci_readw(host, O2_SD_MISC_CTRL);

drivers/mmc/host/sdhci-pci-o2micro.c

339

scratch |= O2_SD_PWR_FORCE_L0;

drivers/mmc/host/sdhci-pci-o2micro.c

340

sdhci_writew(host, scratch, O2_SD_MISC_CTRL);

drivers/mmc/host/sdhci-pci-o2micro.c

420

scratch = sdhci_readw(host, O2_SD_MISC_CTRL);

drivers/mmc/host/sdhci-pci-o2micro.c

421

scratch &= ~(O2_SD_PWR_FORCE_L0);

drivers/mmc/host/sdhci-pci-o2micro.c

422

sdhci_writew(host, scratch, O2_SD_MISC_CTRL);

drivers/mmc/host/sdhci-pci-o2micro.c

581

u8 scratch;

drivers/mmc/host/sdhci-pci-o2micro.c

595

pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

596

scratch &= 0x7f;

drivers/mmc/host/sdhci-pci-o2micro.c

597

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

627

pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

628

scratch |= 0x80;

drivers/mmc/host/sdhci-pci-o2micro.c

629

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

813

u8 scratch;

drivers/mmc/host/sdhci-pci-o2micro.c

824

O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

827

scratch &= 0x7f;

drivers/mmc/host/sdhci-pci-o2micro.c

828

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

835

O2_SD_CLKREQ, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

838

scratch |= 0x20;

drivers/mmc/host/sdhci-pci-o2micro.c

839

pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

844

ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

847

scratch |= 0x01;

drivers/mmc/host/sdhci-pci-o2micro.c

848

pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

857

O2_SD_INF_MOD, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

860

scratch |= 0x08;

drivers/mmc/host/sdhci-pci-o2micro.c

861

pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

865

O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

868

scratch |= 0x80;

drivers/mmc/host/sdhci-pci-o2micro.c

869

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

876

O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

880

scratch &= 0x7f;

drivers/mmc/host/sdhci-pci-o2micro.c

881

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

962

O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

965

scratch |= 0x80;

drivers/mmc/host/sdhci-pci-o2micro.c

966

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

972

O2_SD_LOCK_WP, &scratch);

drivers/mmc/host/sdhci-pci-o2micro.c

976

scratch &= 0x7f;

drivers/mmc/host/sdhci-pci-o2micro.c

977

pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

drivers/mmc/host/sdhci-pic32.c

215

u32 scratch;

drivers/mmc/host/sdhci-pic32.c

217

scratch = readl(host->ioaddr + SDHCI_INT_STATUS);

drivers/mmc/host/sdhci-pic32.c

218

sdhci_remove_host(host, scratch == (u32)~0);

drivers/mmc/host/sdhci-spear.c

123

u32 scratch;

drivers/mmc/host/sdhci-spear.c

125

scratch = readl(host->ioaddr + SDHCI_INT_STATUS);

drivers/mmc/host/sdhci-spear.c

126

if (scratch == (u32)-1)

drivers/mmc/host/sdhci.c

539

u32 scratch;

drivers/mmc/host/sdhci.c

559

scratch = sdhci_readl(host, SDHCI_BUFFER);

drivers/mmc/host/sdhci.c

563

*buf = scratch & 0xFF;

drivers/mmc/host/sdhci.c

566

scratch >>= 8;

drivers/mmc/host/sdhci.c

578

u32 scratch;

drivers/mmc/host/sdhci.c

585

scratch = 0;

drivers/mmc/host/sdhci.c

598

scratch |= (u32)*buf << (chunk * 8);

drivers/mmc/host/sdhci.c

605

sdhci_writel(host, scratch, SDHCI_BUFFER);

drivers/mmc/host/sdhci.c

607

scratch = 0;

drivers/mtd/devices/mtd_dataflash.c

461

u8 *scratch;

drivers/mtd/devices/mtd_dataflash.c

474

scratch = kzalloc(l, GFP_KERNEL);

drivers/mtd/devices/mtd_dataflash.c

475

if (!scratch)

drivers/mtd/devices/mtd_dataflash.c

481

scratch[0] = OP_READ_SECURITY;

drivers/mtd/devices/mtd_dataflash.c

484

t.tx_buf = scratch;

drivers/mtd/devices/mtd_dataflash.c

485

t.rx_buf = scratch;

drivers/mtd/devices/mtd_dataflash.c

493

memcpy(buf, scratch + 4 + base + off, len);

drivers/mtd/devices/mtd_dataflash.c

497

kfree(scratch);

drivers/mtd/devices/mtd_dataflash.c

540

u8 *scratch;

drivers/mtd/devices/mtd_dataflash.c

561

scratch = kzalloc(l, GFP_KERNEL);

drivers/mtd/devices/mtd_dataflash.c

562

if (!scratch)

drivers/mtd/devices/mtd_dataflash.c

564

scratch[0] = OP_WRITE_SECURITY;

drivers/mtd/devices/mtd_dataflash.c

565

memcpy(scratch + 4 + from, buf, len);

drivers/mtd/devices/mtd_dataflash.c

570

t.tx_buf = scratch;

drivers/mtd/devices/mtd_dataflash.c

582

kfree(scratch);

drivers/mtd/maps/amd76xrom.c

71

struct amd76xrom_map_info *map, *scratch;

drivers/mtd/maps/amd76xrom.c

82

list_for_each_entry_safe(map, scratch, &window->maps, list) {

drivers/mtd/maps/ck804xrom.c

84

struct ck804xrom_map_info *map, *scratch;

drivers/mtd/maps/ck804xrom.c

94

list_for_each_entry_safe(map, scratch, &window->maps, list) {

drivers/mtd/maps/esb2rom.c

120

struct esb2rom_map_info *map, *scratch;

drivers/mtd/maps/esb2rom.c

129

list_for_each_entry_safe(map, scratch, &window->maps, list) {

drivers/mtd/maps/ichxrom.c

59

struct ichxrom_map_info *map, *scratch;

drivers/mtd/maps/ichxrom.c

70

list_for_each_entry_safe(map, scratch, &window->maps, list) {

drivers/net/usb/kaweth.c

228

__u8 scratch[KAWETH_SCRATCH_SIZE];

drivers/net/usb/kaweth.c

259

&kaweth->scratch, 0,

drivers/net/usb/kaweth.c

274

&kaweth->scratch, 0,

drivers/net/usb/kaweth.c

291

&kaweth->scratch, 0,

drivers/net/usb/kaweth.c

799

&kaweth->scratch, 0,

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

1386

if (devinfo->shared.scratch)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

1389

devinfo->shared.scratch,

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

1404

devinfo->shared.scratch =

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

1409

if (!devinfo->shared.scratch)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

313

void *scratch;

drivers/net/wireless/intel/iwlegacy/4965-mac.c

1855

offsetof(struct il_tx_cmd, scratch);

drivers/net/wireless/intel/iwlegacy/commands.h

1475

struct il_dram_scratch scratch;

drivers/net/wireless/intel/iwlwifi/dvm/commands.h

1208

struct iwl_dram_scratch scratch;

drivers/net/wireless/intel/iwlwifi/fw/api/tx.h

227

} scratch; /* DRAM_SCRATCH_API_U_VER_1 */

drivers/net/wireless/intel/iwlwifi/fw/dump.c

474

u32 scratch = iwl_read32(fwrt->trans, CSR_FUNC_SCRATCH);

drivers/net/wireless/intel/iwlwifi/fw/dump.c

477

IWL_ERR(fwrt, "0x%08X | Func Scratch\n", scratch);

drivers/net/wireless/intel/iwlwifi/pcie/drv.c

1239

u32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH);

drivers/net/wireless/intel/iwlwifi/pcie/drv.c

1241

if (!(scratch & CSR_FUNC_SCRATCH_POWER_OFF_MASK) ||

drivers/net/wireless/intel/iwlwifi/pcie/drv.c

1242

scratch == ~0U)

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/tx.c

2186

offsetof(struct iwl_tx_cmd_v6_params, scratch);

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/tx.c

2226

offsetofend(struct iwl_tx_cmd_v6_params, scratch) >

drivers/net/wireless/marvell/libertas/if_sdio.c

147

u16 scratch;

drivers/net/wireless/marvell/libertas/if_sdio.c

149

scratch = sdio_readb(card->func, card->scratch_reg, &ret);

drivers/net/wireless/marvell/libertas/if_sdio.c

151

scratch |= sdio_readb(card->func, card->scratch_reg + 1,

drivers/net/wireless/marvell/libertas/if_sdio.c

160

return scratch;

drivers/net/wireless/marvell/libertas/if_sdio.c

638

u16 scratch;

drivers/net/wireless/marvell/libertas/if_sdio.c

640

scratch = if_sdio_read_scratch(card, &ret);

drivers/net/wireless/marvell/libertas/if_sdio.c

644

if (scratch == IF_SDIO_FIRMWARE_OK)

drivers/net/wireless/marvell/libertas/if_sdio.c

696

u16 scratch;

drivers/net/wireless/marvell/libertas/if_sdio.c

706

scratch = if_sdio_read_scratch(card, &ret);

drivers/net/wireless/marvell/libertas/if_sdio.c

709

lbs_deb_sdio("firmware status = %#x\n", scratch);

drivers/net/wireless/marvell/libertas/if_sdio.c

726

if (scratch == IF_SDIO_FIRMWARE_OK) {

drivers/net/wireless/marvell/libertas/if_sdio.c

730

} else if ((card->model == MODEL_8686) && (scratch & 0x7fff)) {

drivers/net/wireless/marvell/libertas/if_spi.c

1012

u32 scratch;

drivers/net/wireless/marvell/libertas/if_spi.c

1023

err = spu_read_u32(card, IF_SPI_SCRATCH_4_REG, &scratch);

drivers/net/wireless/marvell/libertas/if_spi.c

1026

if (scratch == SUCCESSFUL_FW_DOWNLOAD_MAGIC)

drivers/of/kexec.c

274

if (!image->kho.fdt || !image->kho.scratch)

drivers/of/kexec.c

279

scratch_mem = image->kho.scratch->mem;

drivers/of/kexec.c

280

scratch_len = image->kho.scratch->bufsz;

drivers/pnp/pnpbios/core.c

118

scratch = buf;

drivers/pnp/pnpbios/core.c

121

envp[i++] = scratch;

drivers/pnp/pnpbios/core.c

122

scratch += sprintf(scratch, "ACTION=%s", dock ? "add" : "remove") + 1;

drivers/pnp/pnpbios/core.c

125

envp[i++] = scratch;

drivers/pnp/pnpbios/core.c

126

scratch += sprintf(scratch, "DOCK=%x/%x/%x",

drivers/pnp/pnpbios/core.c

89

char *argv[3], **envp, *buf, *scratch;

drivers/ptp/ptp_clockmatrix.c

1244

u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);

drivers/ptp/ptp_clockmatrix.c

1294

if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)

drivers/ptp/ptp_clockmatrix.c

65

u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);

drivers/ptp/ptp_clockmatrix.c

73

full_count = (scratch - GPIO_USER_CONTROL) -

drivers/ptp/ptp_clockmatrix.c

74

((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;

drivers/ptp/ptp_clockmatrix.c

91

if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)

drivers/scsi/esas2r/esas2r.h

694

u8 *scratch;

drivers/scsi/esas2r/esas2r_flash.c

1412

fc->scratch = ((struct esas2r_flash_img *)fi)->scratch_buf;

drivers/scsi/esas2r/esas2r_flash.c

315

memset(fc->scratch, 0, FM_BUF_SZ);

drivers/scsi/esas2r/esas2r_flash.c

346

p = fc->scratch;

drivers/scsi/esas2r/esas2r_flash.c

369

((u8 *)fc->scratch - (u8 *)fi);

drivers/scsi/esas2r/esas2r_flash.c

408

+ ((u8 *)fc->scratch -

drivers/scsi/esas2r/esas2r_flash.c

443

+ ((u8 *)fc->scratch -

drivers/scsi/esas2r/esas2r_flash.c

479

+ ((u8 *)fc->scratch -

drivers/scsi/esas2r/esas2r_flash.c

513

+ ((u8 *)fc->scratch -

drivers/scsi/ipr.c

670

ipr_cmd->u.scratch = 0;

drivers/scsi/ipr.h

1569

unsigned long scratch;

drivers/scsi/ips.c

1068

ips_copp_wait_item_t *scratch;

drivers/scsi/ips.c

1089

scratch = kmalloc_obj(ips_copp_wait_item_t, GFP_ATOMIC);

drivers/scsi/ips.c

1091

if (!scratch) {

drivers/scsi/ips.c

1098

scratch->scsi_cmd = SC;

drivers/scsi/ips.c

1099

scratch->next = NULL;

drivers/scsi/ips.c

1101

ips_putq_copp_tail(&ha->copp_waitlist, scratch);

drivers/scsi/ncr53c8xx.c

1716

u_char scratch; /* Scratch for SCSI receive */

drivers/scsi/ncr53c8xx.c

2204

NADDR (scratch),

drivers/scsi/ncr53c8xx.c

2208

NADDR (scratch),

drivers/scsi/ncr53c8xx.c

2238

NADDR (scratch),

drivers/scsi/ncr53c8xx.c

2242

NADDR (scratch),

drivers/scsi/ncr53c8xx.c

2256

NADDR (scratch),

drivers/scsi/ncr53c8xx.c

2866

NADDR (scratch),

drivers/scsi/ses.c

184

struct ses_device *ses_dev = edev->scratch;

drivers/scsi/ses.c

214

struct ses_device *ses_dev = edev->scratch;

drivers/scsi/ses.c

378

struct ses_device *ses_dev = edev->scratch;

drivers/scsi/ses.c

40

struct ses_device *ses_dev = edev->scratch;

drivers/scsi/ses.c

475

struct ses_component *scomp = ecomp->scratch;

drivers/scsi/ses.c

537

scomp = edev->component[i].scratch;

drivers/scsi/ses.c

557

struct ses_device *ses_dev = edev->scratch;

drivers/scsi/ses.c

815

edev->scratch = ses_dev;

drivers/scsi/ses.c

817

edev->component[i].scratch = scomp + i;

drivers/scsi/ses.c

871

ses_dev = edev->scratch;

drivers/scsi/ses.c

872

edev->scratch = NULL;

drivers/scsi/ses.c

880

kfree(edev->component[0].scratch);

drivers/scsi/stex.c

1114

__le32 *scratch;

drivers/scsi/stex.c

1186

scratch = hba->scratch;

drivers/scsi/stex.c

1188

while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {

drivers/scsi/stex.c

1214

memset(scratch, 0, scratch_size);

drivers/scsi/stex.c

1769

hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);

drivers/scsi/stex.c

335

__le32 *scratch;

drivers/scsi/stex.c

915

__le32 *scratch;

drivers/scsi/stex.c

926

scratch = hba->scratch + hba->status_tail;

drivers/scsi/stex.c

927

value = le32_to_cpu(*scratch);

drivers/scsi/stex.c

932

*scratch = 0;

drivers/scsi/sym53c8xx_2/sym_fw1.h

1081

PADDR_B (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1406

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1412

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1477

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1582

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1610

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1756

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1763

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

1768

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

189

u32 scratch [ 1];

drivers/scsi/sym53c8xx_2/sym_fw1.h

405

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

411

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw1.h

610

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

1352

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

1455

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

1483

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

183

u32 scratch [ 1];

drivers/scsi/sym53c8xx_2/sym_fw2.h

1844

offsetof(struct sym_hcb, scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

1849

offsetof(struct sym_hcb, scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

1854

offsetof(struct sym_hcb, scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

390

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

396

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

599

HADDR_1 (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

692

PADDR_B (scratch),

drivers/scsi/sym53c8xx_2/sym_fw2.h

696

PADDR_B (scratch),

drivers/scsi/sym53c8xx_2/sym_hipd.c

1014

np->scratch = cpu_to_scr(host_wr);

drivers/scsi/sym53c8xx_2/sym_hipd.c

1055

host_rd = scr_to_cpu(np->scratch);

drivers/scsi/sym53c8xx_2/sym_hipd.h

952

u32 scratch; /* Scratch for SCSI receive */

drivers/soc/tegra/pmc.c

3129

pmc->scratch = base;

drivers/soc/tegra/pmc.c

3150

pmc->scratch = devm_ioremap_resource(&pdev->dev, res);

drivers/soc/tegra/pmc.c

3151

if (IS_ERR(pmc->scratch))

drivers/soc/tegra/pmc.c

3152

return PTR_ERR(pmc->scratch);

drivers/soc/tegra/pmc.c

3154

pmc->scratch = NULL;

drivers/soc/tegra/pmc.c

3167

if (pmc->scratch) {

drivers/soc/tegra/pmc.c

447

void __iomem *scratch;

drivers/soc/tegra/pmc.c

552

return readl(pmc->scratch + offset);

drivers/soc/tegra/pmc.c

561

writel(value, pmc->scratch + offset);

drivers/tty/serial/8250/8250_port.c

1070

unsigned char status1, scratch, scratch2, scratch3;

drivers/tty/serial/8250/8250_port.c

1104

scratch = serial_in(up, UART_IER);

drivers/tty/serial/8250/8250_port.c

1119

serial_out(up, UART_IER, scratch);

drivers/tty/serial/8250/8250_port.c

874

unsigned char scratch, status1, status2;

drivers/tty/serial/8250/8250_port.c

878

scratch = serial_in(up, UART_SCR);

drivers/tty/serial/8250/8250_port.c

883

serial_out(up, UART_SCR, scratch);

drivers/tty/serial/sunsu.c

1008

unsigned char status1, status2, scratch, scratch2, scratch3;

drivers/tty/serial/sunsu.c

1030

scratch = serial_in(up, UART_IER);

drivers/tty/serial/sunsu.c

1041

serial_out(up, UART_IER, scratch);

drivers/tty/serial/sunsu.c

1069

scratch = serial_in(up, UART_IIR) >> 6;

drivers/tty/serial/sunsu.c

1070

switch (scratch) {

drivers/tty/serial/sunsu.c

1100

scratch = serial_in(up, UART_IIR) >> 5;

drivers/tty/serial/sunsu.c

1101

if (scratch == 7) {

drivers/tty/serial/sunsu.c

1112

scratch = serial_in(up, UART_IIR) >> 5;

drivers/tty/serial/sunsu.c

1113

if (scratch == 6)

drivers/tty/serial/sunsu.c

1120

scratch = serial_in(up, UART_SCR);

drivers/tty/serial/sunsu.c

1125

serial_out(up, UART_SCR, scratch);

drivers/usb/fotg210/fotg210-hcd.c

322

static inline char speed_char(u32 scratch)

drivers/usb/fotg210/fotg210-hcd.c

324

switch (scratch & (3 << 12)) {

drivers/usb/fotg210/fotg210-hcd.c

356

u32 scratch;

drivers/usb/fotg210/fotg210-hcd.c

378

scratch = hc32_to_cpup(fotg210, &hw->hw_info1);

drivers/usb/fotg210/fotg210-hcd.c

382

qh, scratch & 0x007f,

drivers/usb/fotg210/fotg210-hcd.c

383

speed_char(scratch),

drivers/usb/fotg210/fotg210-hcd.c

384

(scratch >> 8) & 0x000f,

drivers/usb/fotg210/fotg210-hcd.c

385

scratch, hc32_to_cpup(fotg210, &hw->hw_info2),

drivers/usb/fotg210/fotg210-hcd.c

395

scratch = hc32_to_cpup(fotg210, &td->hw_token);

drivers/usb/fotg210/fotg210-hcd.c

401

else if (QTD_LENGTH(scratch)) {

drivers/usb/fotg210/fotg210-hcd.c

410

switch ((scratch>>8)&0x03) {

drivers/usb/fotg210/fotg210-hcd.c

424

(scratch >> 16) & 0x7fff,

drivers/usb/fotg210/fotg210-hcd.c

425

scratch,

drivers/usb/fotg210/fotg210-hcd.c

482

u32 scratch = hc32_to_cpup(fotg210, &hw->hw_info1);

drivers/usb/fotg210/fotg210-hcd.c

501

speed_char(scratch), scratch & 0x007f,

drivers/usb/fotg210/fotg210-hcd.c

502

(scratch >> 8) & 0x000f, type, qh->usecs,

drivers/usb/fotg210/fotg210-hcd.c

503

qh->c_usecs, temp, (scratch >> 16) & 0x7ff);

drivers/usb/fotg210/fotg210-hcd.c

638

char *next, scratch[80];

drivers/usb/fotg210/fotg210-hcd.c

686

temp = dbg_status_buf(scratch, sizeof(scratch), label,

drivers/usb/fotg210/fotg210-hcd.c

688

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/fotg210/fotg210-hcd.c

692

temp = dbg_command_buf(scratch, sizeof(scratch), label,

drivers/usb/fotg210/fotg210-hcd.c

694

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/fotg210/fotg210-hcd.c

698

temp = dbg_intr_buf(scratch, sizeof(scratch), label,

drivers/usb/fotg210/fotg210-hcd.c

700

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/gadget/udc/net2280.c

1979

u32 scratch;

drivers/usb/gadget/udc/net2280.c

1983

scratch = get_idx_reg(dev->regs, SCRATCH);

drivers/usb/gadget/udc/net2280.c

1985

WARN_ON((scratch & (0xf << DEFECT7374_FSM_FIELD))

drivers/usb/gadget/udc/net2280.c

1988

scratch &= ~(0xf << DEFECT7374_FSM_FIELD);

drivers/usb/gadget/udc/net2280.c

2043

scratch |= DEFECT7374_FSM_WAITING_FOR_CONTROL_READ;

drivers/usb/gadget/udc/net2280.c

2044

set_idx_reg(dev->regs, SCRATCH, scratch);

drivers/usb/gadget/udc/net2280.c

2778

u32 scratch, fsmvalue;

drivers/usb/gadget/udc/net2280.c

2782

scratch = get_idx_reg(dev->regs, SCRATCH);

drivers/usb/gadget/udc/net2280.c

2783

fsmvalue = scratch & (0xf << DEFECT7374_FSM_FIELD);

drivers/usb/gadget/udc/net2280.c

2784

scratch &= ~(0xf << DEFECT7374_FSM_FIELD);

drivers/usb/gadget/udc/net2280.c

2798

scratch |= DEFECT7374_FSM_NON_SS_CONTROL_READ;

drivers/usb/gadget/udc/net2280.c

2812

scratch |= DEFECT7374_FSM_SS_CONTROL_READ;

drivers/usb/gadget/udc/net2280.c

2843

set_idx_reg(dev->regs, SCRATCH, scratch);

drivers/usb/gadget/udc/net2280.c

3095

u32 num, scratch;

drivers/usb/gadget/udc/net2280.c

3192

scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |

drivers/usb/gadget/udc/net2280.c

3197

scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) |

drivers/usb/gadget/udc/net2280.c

3200

writel(scratch, &dev->epregs[0].ep_irqenb);

drivers/usb/gadget/udc/net2280.c

3329

scratch = stat & 0x7f;

drivers/usb/gadget/udc/net2280.c

3331

for (num = 0; scratch; num++) {

drivers/usb/gadget/udc/net2280.c

3336

if ((scratch & t) == 0)

drivers/usb/gadget/udc/net2280.c

3338

scratch ^= t;

drivers/usb/gadget/udc/net2280.c

3363

u32 tmp, num, mask, scratch;

drivers/usb/gadget/udc/net2280.c

3463

scratch = stat & DMA_INTERRUPTS;

drivers/usb/gadget/udc/net2280.c

3465

scratch >>= 9;

drivers/usb/gadget/udc/net2280.c

3466

for (num = 0; scratch; num++) {

drivers/usb/gadget/udc/net2280.c

3470

if ((tmp & scratch) == 0)

drivers/usb/gadget/udc/net2280.c

3472

scratch ^= tmp;

drivers/usb/host/ehci-dbg.c

373

u32 scratch;

drivers/usb/host/ehci-dbg.c

396

scratch = hc32_to_cpup(ehci, &hw->hw_info1);

drivers/usb/host/ehci-dbg.c

401

qh, scratch & 0x007f,

drivers/usb/host/ehci-dbg.c

402

speed_char (scratch),

drivers/usb/host/ehci-dbg.c

403

(scratch >> 8) & 0x000f,

drivers/usb/host/ehci-dbg.c

404

scratch, hc32_to_cpup(ehci, &hw->hw_info2),

drivers/usb/host/ehci-dbg.c

420

scratch = hc32_to_cpup(ehci, &td->hw_token);

drivers/usb/host/ehci-dbg.c

426

} else if (QTD_LENGTH(scratch)) {

drivers/usb/host/ehci-dbg.c

432

switch ((scratch >> 8) & 0x03) {

drivers/usb/host/ehci-dbg.c

450

(scratch >> 16) & 0x7fff,

drivers/usb/host/ehci-dbg.c

451

scratch,

drivers/usb/host/ehci-dbg.c

596

u32 scratch = hc32_to_cpup(ehci, &hw->hw_info1);

drivers/usb/host/ehci-dbg.c

615

speed_char(scratch), scratch & 0x007f,

drivers/usb/host/ehci-dbg.c

616

(scratch >> 8) & 0x000f, type, qh->ps.usecs,

drivers/usb/host/ehci-dbg.c

617

qh->ps.c_usecs, temp, 0x7ff & (scratch >> 16));

drivers/usb/host/ehci-dbg.c

761

char *next, scratch[80];

drivers/usb/host/ehci-dbg.c

847

temp = dbg_status_buf(scratch, sizeof(scratch), label,

drivers/usb/host/ehci-dbg.c

849

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/host/ehci-dbg.c

853

temp = dbg_command_buf(scratch, sizeof(scratch), label,

drivers/usb/host/ehci-dbg.c

855

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/host/ehci-dbg.c

859

temp = dbg_intr_buf(scratch, sizeof(scratch), label,

drivers/usb/host/ehci-dbg.c

861

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/host/ehci-dbg.c

871

temp = dbg_port_buf(scratch, sizeof(scratch), label, i,

drivers/usb/host/ehci-dbg.c

874

temp = scnprintf(next, size, fmt, temp, scratch);

drivers/usb/isp1760/isp1760-hcd.c

723

u32 scratch;

drivers/usb/isp1760/isp1760-hcd.c

738

scratch = isp1760_hcd_read(hcd, HC_SCRATCH);

drivers/usb/isp1760/isp1760-hcd.c

739

if (scratch != pattern) {

drivers/usb/isp1760/isp1760-hcd.c

741

scratch);

drivers/usb/isp1760/isp1760-udc.c

1500

u16 scratch;

drivers/usb/isp1760/isp1760-udc.c

1512

scratch = isp1760_udc_read(udc, DC_SCRATCH);

drivers/usb/isp1760/isp1760-udc.c

1514

if (scratch != 0xbabe) {

drivers/usb/isp1760/isp1760-udc.c

1517

scratch, chipid);

drivers/watchdog/nct6694_wdt.c

65

u8 scratch;

fs/nfs/blocklayout/blocklayout.c

679

struct folio *scratch;

fs/nfs/blocklayout/blocklayout.c

692

scratch = folio_alloc(gfp_mask, 0);

fs/nfs/blocklayout/blocklayout.c

693

if (!scratch)

fs/nfs/blocklayout/blocklayout.c

698

xdr_set_scratch_folio(&xdr, scratch);

fs/nfs/blocklayout/blocklayout.c

747

folio_put(scratch);

fs/nfs/blocklayout/dev.c

546

struct folio *scratch;

fs/nfs/blocklayout/dev.c

550

scratch = folio_alloc(gfp_mask, 0);

fs/nfs/blocklayout/dev.c

551

if (!scratch)

fs/nfs/blocklayout/dev.c

555

xdr_set_scratch_folio(&xdr, scratch);

fs/nfs/blocklayout/dev.c

586

folio_put(scratch);

fs/nfs/dir.c

833

struct folio *scratch;

fs/nfs/dir.c

838

scratch = folio_alloc(GFP_KERNEL, 0);

fs/nfs/dir.c

839

if (scratch == NULL)

fs/nfs/dir.c

843

xdr_set_scratch_folio(&stream, scratch);

fs/nfs/dir.c

895

folio_put(scratch);

fs/nfs/filelayout/filelayout.c

649

struct folio *scratch;

fs/nfs/filelayout/filelayout.c

656

scratch = folio_alloc(gfp_flags, 0);

fs/nfs/filelayout/filelayout.c

657

if (!scratch)

fs/nfs/filelayout/filelayout.c

661

xdr_set_scratch_folio(&stream, scratch);

fs/nfs/filelayout/filelayout.c

727

folio_put(scratch);

fs/nfs/filelayout/filelayout.c

731

folio_put(scratch);

fs/nfs/filelayout/filelayoutdev.c

189

folio_put(scratch);

fs/nfs/filelayout/filelayoutdev.c

207

folio_put(scratch);

fs/nfs/filelayout/filelayoutdev.c

76

struct folio *scratch;

fs/nfs/filelayout/filelayoutdev.c

82

scratch = folio_alloc(gfp_flags, 0);

fs/nfs/filelayout/filelayoutdev.c

83

if (!scratch)

fs/nfs/filelayout/filelayoutdev.c

87

xdr_set_scratch_folio(&stream, scratch);

fs/nfs/flexfilelayout/flexfilelayout.c

454

struct folio *scratch;

fs/nfs/flexfilelayout/flexfilelayout.c

462

scratch = folio_alloc(gfp_flags, 0);

fs/nfs/flexfilelayout/flexfilelayout.c

463

if (!scratch)

fs/nfs/flexfilelayout/flexfilelayout.c

468

xdr_set_scratch_folio(&stream, scratch);

fs/nfs/flexfilelayout/flexfilelayout.c

647

folio_put(scratch);

fs/nfs/flexfilelayout/flexfilelayoutdev.c

165

folio_put(scratch);

fs/nfs/flexfilelayout/flexfilelayoutdev.c

179

folio_put(scratch);

fs/nfs/flexfilelayout/flexfilelayoutdev.c

47

struct folio *scratch;

fs/nfs/flexfilelayout/flexfilelayoutdev.c

59

scratch = folio_alloc(gfp_flags, 0);

fs/nfs/flexfilelayout/flexfilelayoutdev.c

60

if (!scratch)

fs/nfs/flexfilelayout/flexfilelayoutdev.c

73

xdr_set_scratch_folio(&stream, scratch);

fs/nfs/nfs42proc.c

1529

res.scratch = folio_alloc(GFP_KERNEL, 0);

fs/nfs/nfs42proc.c

1530

if (!res.scratch)

fs/nfs/nfs42proc.c

1567

folio_put(res.scratch);

fs/nfs/nfs42xdr.c

1588

xdr_set_scratch_buffer(xdr, res->scratch, READ_PLUS_SCRATCH_SIZE);

fs/nfs/nfs42xdr.c

1784

xdr_set_scratch_folio(xdr, res->scratch);

fs/nfs/read.c

116

WARN_ON(hdr->res.scratch != NULL);

fs/nfs/read.c

117

hdr->res.scratch = kmalloc(size, GFP_KERNEL);

fs/nfs/read.c

118

return hdr->res.scratch != NULL;

fs/nfs/read.c

51

kfree(rhdr->res.scratch);

fs/nfsd/nfs3xdr.c

1110

struct svc_fh *fhp = &resp->scratch;

fs/nfsd/nfs4xdr.c

163

if (p != argp->xdr->scratch.iov_base)

fs/nfsd/nfs4xdr.c

4103

xdr->scratch.iov_len = 0;

fs/nfsd/xdr3.h

180

struct svc_fh scratch;

fs/xfs/libxfs/xfs_parent.c

312

struct xfs_da_args *scratch)

fs/xfs/libxfs/xfs_parent.c

314

memset(scratch, 0, sizeof(struct xfs_da_args));

fs/xfs/libxfs/xfs_parent.c

315

xfs_parent_da_args_init(scratch, tp, pptr, ip, ip->i_ino, parent_name);

fs/xfs/libxfs/xfs_parent.c

316

return xfs_attr_get_ilocked(scratch);

fs/xfs/libxfs/xfs_parent.c

348

struct xfs_da_args *scratch)

fs/xfs/libxfs/xfs_parent.c

355

memset(scratch, 0, sizeof(struct xfs_da_args));

fs/xfs/libxfs/xfs_parent.c

356

xfs_parent_da_args_init(scratch, NULL, pptr, ip, owner, parent_name);

fs/xfs/libxfs/xfs_parent.c

357

return xfs_attr_set(scratch, XFS_ATTRUPDATE_CREATE, false);

fs/xfs/libxfs/xfs_parent.c

371

struct xfs_da_args *scratch)

fs/xfs/libxfs/xfs_parent.c

378

memset(scratch, 0, sizeof(struct xfs_da_args));

fs/xfs/libxfs/xfs_parent.c

379

xfs_parent_da_args_init(scratch, NULL, pptr, ip, owner, parent_name);

fs/xfs/libxfs/xfs_parent.c

380

return xfs_attr_set(scratch, XFS_ATTRUPDATE_REMOVE, false);

fs/xfs/libxfs/xfs_parent.h

102

struct xfs_da_args *scratch);

fs/xfs/libxfs/xfs_parent.h

105

struct xfs_da_args *scratch);

fs/xfs/libxfs/xfs_parent.h

108

struct xfs_da_args *scratch);

fs/xfs/scrub/xfarray.c

1015

if (p != scratch)

fs/xfs/scrub/xfarray.c

1016

memcpy(scratch, p, si->array->obj_size);

fs/xfs/scrub/xfarray.c

1023

error = xfarray_sort_store(si, hi--, scratch);

fs/xfs/scrub/xfarray.c

547

void *scratch = xfarray_sortinfo_isort_scratch(si);

fs/xfs/scrub/xfarray.c

555

error = xfile_load(si->array->xfile, scratch, len, lo_pos);

fs/xfs/scrub/xfarray.c

560

sort(scratch, hi - lo + 1, si->array->obj_size, si->cmp_fn, NULL);

fs/xfs/scrub/xfarray.c

563

return xfile_store(si->array->xfile, scratch, len, lo_pos);

fs/xfs/scrub/xfarray.c

912

void *scratch = xfarray_scratch(array);

fs/xfs/scrub/xfarray.c

989

if (p != scratch)

fs/xfs/scrub/xfarray.c

990

memcpy(scratch, p, si->array->obj_size);

fs/xfs/scrub/xfarray.c

997

error = xfarray_sort_store(si, lo++, scratch);

include/linux/enclosure.h

85

void *scratch;

include/linux/enclosure.h

99

void *scratch;

include/linux/kexec.h

421

struct kexec_segment *scratch;

include/linux/nfs_xdr.h

1603

struct folio *scratch;

include/linux/nfs_xdr.h

700

void * scratch; /* used by read */

include/linux/sunrpc/xdr.h

226

struct kvec scratch; /* Scratch buffer */

include/linux/sunrpc/xdr.h

286

xdr->scratch.iov_base = buf;

include/linux/sunrpc/xdr.h

287

xdr->scratch.iov_len = buflen;

include/linux/sunrpc/xdr.h

325

if (unlikely(xdr->scratch.iov_len))

include/net/tcp.h

1981

void *scratch;

include/uapi/drm/radeon_drm.h

277

} scratch;

kernel/liveupdate/kexec_handover.c

1463

struct kho_scratch *scratch = NULL;

kernel/liveupdate/kexec_handover.c

1492

scratch = early_memremap(scratch_phys, scratch_len);

kernel/liveupdate/kexec_handover.c

1493

if (!scratch) {

kernel/liveupdate/kexec_handover.c

1505

struct kho_scratch *area = &scratch[i];

kernel/liveupdate/kexec_handover.c

1538

early_memunmap(scratch, scratch_len);

kernel/liveupdate/kexec_handover.c

1552

struct kexec_buf scratch;

kernel/liveupdate/kexec_handover.c

1560

scratch = (struct kexec_buf){

kernel/liveupdate/kexec_handover.c

1570

err = kexec_add_buffer(&scratch);

kernel/liveupdate/kexec_handover.c

1573

image->kho.scratch = &image->segment[image->nr_segments - 1];

kernel/trace/trace.c

5391

tscratch = tr->scratch;

kernel/trace/trace.c

5427

tscratch = tr->scratch;

kernel/trace/trace.c

5466

if (tr->scratch) {

kernel/trace/trace.c

5467

struct trace_scratch *tscratch = tr->scratch;

kernel/trace/trace.c

5489

if (!tr->scratch)

kernel/trace/trace.c

5492

tscratch = tr->scratch;

kernel/trace/trace.c

6349

struct trace_scratch *tscratch = tr->scratch;

kernel/trace/trace.c

6384

struct trace_scratch *tscratch = tr->scratch;

kernel/trace/trace.c

7054

if (tr->scratch && !(tr->flags & TRACE_ARRAY_FL_LAST_BOOT)) {

kernel/trace/trace.c

7055

struct trace_scratch *tscratch = tr->scratch;

kernel/trace/trace.c

9271

tscratch = tr->scratch;

kernel/trace/trace.c

9311

tr->scratch = tscratch;

kernel/trace/trace.h

369

void *scratch; /* pointer in persistent memory */

lib/kobject_uevent.c

284

char *scratch;

lib/kobject_uevent.c

294

scratch = skb_put(skb, len);

lib/kobject_uevent.c

295

sprintf(scratch, "%s@%s", action_string, devpath);

lib/tests/kunit_iov_iter.c

105

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

112

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

114

scratch[i] = pattern(i);

lib/tests/kunit_iov_iter.c

123

copied = copy_to_iter(scratch, size, &iter);

lib/tests/kunit_iov_iter.c

131

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

134

scratch[i] = pattern(patt++);

lib/tests/kunit_iov_iter.c

138

KUNIT_EXPECT_EQ_MSG(test, buffer[i], scratch[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

139

if (buffer[i] != scratch[i])

lib/tests/kunit_iov_iter.c

155

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

166

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

167

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

173

copied = copy_from_iter(scratch, size, &iter);

lib/tests/kunit_iov_iter.c

193

KUNIT_EXPECT_EQ_MSG(test, scratch[i], buffer[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

194

if (scratch[i] != buffer[i])

lib/tests/kunit_iov_iter.c

264

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

271

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

273

scratch[i] = pattern(i);

lib/tests/kunit_iov_iter.c

282

copied = copy_to_iter(scratch, size, &iter);

lib/tests/kunit_iov_iter.c

291

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

293

u8 *p = scratch + pr->page * PAGE_SIZE;

lib/tests/kunit_iov_iter.c

301

KUNIT_EXPECT_EQ_MSG(test, buffer[i], scratch[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

302

if (buffer[i] != scratch[i])

lib/tests/kunit_iov_iter.c

318

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

329

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

330

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

336

copied = copy_from_iter(scratch, size, &iter);

lib/tests/kunit_iov_iter.c

358

KUNIT_EXPECT_EQ_MSG(test, scratch[i], buffer[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

359

if (scratch[i] != buffer[i])

lib/tests/kunit_iov_iter.c

422

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

431

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

433

scratch[i] = pattern(i);

lib/tests/kunit_iov_iter.c

447

copied = copy_to_iter(scratch + i, size, &iter);

lib/tests/kunit_iov_iter.c

459

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

462

scratch[i] = pattern(patt++);

lib/tests/kunit_iov_iter.c

466

KUNIT_EXPECT_EQ_MSG(test, buffer[i], scratch[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

467

if (buffer[i] != scratch[i])

lib/tests/kunit_iov_iter.c

484

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

497

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

498

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

509

copied = copy_from_iter(scratch + i, size, &iter);

lib/tests/kunit_iov_iter.c

531

KUNIT_EXPECT_EQ_MSG(test, scratch[i], buffer[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

532

if (scratch[i] != buffer[i])

lib/tests/kunit_iov_iter.c

584

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

593

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

595

scratch[i] = pattern(i);

lib/tests/kunit_iov_iter.c

608

copied = copy_to_iter(scratch + i, size, &iter);

lib/tests/kunit_iov_iter.c

618

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

621

scratch[i] = pattern(patt++);

lib/tests/kunit_iov_iter.c

625

KUNIT_EXPECT_EQ_MSG(test, buffer[i], scratch[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

626

if (buffer[i] != scratch[i])

lib/tests/kunit_iov_iter.c

642

u8 *scratch, *buffer;

lib/tests/kunit_iov_iter.c

655

scratch = iov_kunit_create_buffer(test, &spages, npages);

lib/tests/kunit_iov_iter.c

656

memset(scratch, 0, bufsize);

lib/tests/kunit_iov_iter.c

666

copied = copy_from_iter(scratch + i, size, &iter);

lib/tests/kunit_iov_iter.c

688

KUNIT_EXPECT_EQ_MSG(test, scratch[i], buffer[i], "at i=%x", i);

lib/tests/kunit_iov_iter.c

689

if (scratch[i] != buffer[i])

mm/mempolicy.c

1071

NODEMASK_SCRATCH(scratch);

mm/mempolicy.c

1074

if (!scratch)

mm/mempolicy.c

1084

ret = mpol_set_nodemask(new, nodes, scratch);

mm/mempolicy.c

1102

NODEMASK_SCRATCH_FREE(scratch);

mm/mempolicy.c

1533

NODEMASK_SCRATCH(scratch);

mm/mempolicy.c

1534

if (scratch) {

mm/mempolicy.c

1536

err = mpol_set_nodemask(new, nmask, scratch);

mm/mempolicy.c

1541

NODEMASK_SCRATCH_FREE(scratch);

mm/mempolicy.c

1870

NODEMASK_SCRATCH(scratch);

mm/mempolicy.c

1872

if (!scratch)

mm/mempolicy.c

1875

old = &scratch->mask1;

mm/mempolicy.c

1876

new = &scratch->mask2;

mm/mempolicy.c

1937

NODEMASK_SCRATCH_FREE(scratch);

mm/mempolicy.c

3220

NODEMASK_SCRATCH(scratch);

mm/mempolicy.c

3222

if (!scratch)

mm/mempolicy.c

3231

ret = mpol_set_nodemask(npol, &mpol->w.user_nodemask, scratch);

mm/mempolicy.c

3243

NODEMASK_SCRATCH_FREE(scratch);

net/ipv4/tcp_ao.c

1405

void *scratch = hp.scratch;

net/ipv4/tcp_ao.c

1412

memset(scratch, 0, 16);

net/ipv4/tcp_ao.c

1413

err = crypto_ahash_setkey(tfm, scratch, 16);

net/ipv4/tcp_ao.c

357

tmp = hp.scratch;

net/ipv4/tcp_ao.c

445

bp = hp->scratch;

net/ipv4/tcp_ao.c

518

bp = (__be32 *)hp->scratch;

net/ipv4/tcp_ao.c

532

u8 *hdr = hp->scratch;

net/ipv4/tcp_sigpool.c

288

c->scratch = rcu_dereference_bh(*this_cpu_ptr(&sigpool_scratch.pad));

net/ipv4/tcp_sigpool.c

74

void *scratch, *old_scratch;

net/ipv4/tcp_sigpool.c

76

scratch = kmalloc_node(size, GFP_KERNEL, cpu_to_node(cpu));

net/ipv4/tcp_sigpool.c

77

if (!scratch) {

net/ipv4/tcp_sigpool.c

83

scratch, lockdep_is_held(&cpool_mutex));

net/ipv4/udp.c

1592

struct udp_dev_scratch *scratch = udp_skb_scratch(skb);

net/ipv4/udp.c

1595

scratch->_tsize_state = skb->truesize;

net/ipv4/udp.c

1597

scratch->len = skb->len;

net/ipv4/udp.c

1598

scratch->csum_unnecessary = !!skb_csum_unnecessary(skb);

net/ipv4/udp.c

1599

scratch->is_linear = !skb_is_nonlinear(skb);

net/ipv4/udp.c

1602

scratch->_tsize_state |= UDP_SKB_IS_STATELESS;

net/ipv6/tcp_ao.c

122

bp = hp->scratch;

net/ipv6/tcp_ao.c

35

tmp = hp.scratch;

net/mac80211/mlme.c

11109

u8 *scratch __free(kfree) = kzalloc(scratch_len, GFP_KERNEL);

net/mac80211/mlme.c

11116

if (WARN_ON(!scratch))

net/mac80211/mlme.c

11146

scratch, scratch_len,

net/mac80211/mlme.c

11151

pos = scratch + sizeof(control);

net/mac80211/parse.c

1003

elems_parse->scratch +

net/mac80211/parse.c

1024

elems_parse->scratch +

net/mac80211/parse.c

1051

elems_parse = kzalloc_flex(*elems_parse, scratch, scratch_len,

net/mac80211/parse.c

1057

elems_parse->scratch_pos = elems_parse->scratch;

net/mac80211/parse.c

59

u8 scratch[] __counted_by(scratch_len);

net/mac80211/parse.c

896

elems_parse->scratch +

net/mac80211/parse.c

946

elems_parse->scratch +

net/netfilter/nft_set_pipapo.c

1201

s = *per_cpu_ptr(m->scratch, cpu);

net/netfilter/nft_set_pipapo.c

1219

struct nft_pipapo_scratch *scratch;

net/netfilter/nft_set_pipapo.c

1221

scratch = kvzalloc_node(struct_size(scratch, __map, bsize_max * 2) +

net/netfilter/nft_set_pipapo.c

1224

if (!scratch) {

net/netfilter/nft_set_pipapo.c

1236

local_lock_init(&scratch->bh_lock);

net/netfilter/nft_set_pipapo.c

1237

*per_cpu_ptr(clone->scratch, i) = scratch;

net/netfilter/nft_set_pipapo.c

1384

if (!*get_cpu_ptr(m->scratch) || bsize_max > m->bsize_max) {

net/netfilter/nft_set_pipapo.c

1385

put_cpu_ptr(m->scratch);

net/netfilter/nft_set_pipapo.c

1393

put_cpu_ptr(m->scratch);

net/netfilter/nft_set_pipapo.c

1423

new->scratch = alloc_percpu(*new->scratch);

net/netfilter/nft_set_pipapo.c

1424

if (!new->scratch)

net/netfilter/nft_set_pipapo.c

1428

*per_cpu_ptr(new->scratch, i) = NULL;

net/netfilter/nft_set_pipapo.c

1492

free_percpu(new->scratch);

net/netfilter/nft_set_pipapo.c

1799

free_percpu(m->scratch);

net/netfilter/nft_set_pipapo.c

2286

m->scratch = alloc_percpu(struct nft_pipapo_scratch *);

net/netfilter/nft_set_pipapo.c

2287

if (!m->scratch) {

net/netfilter/nft_set_pipapo.c

2292

*per_cpu_ptr(m->scratch, i) = NULL;

net/netfilter/nft_set_pipapo.c

422

struct nft_pipapo_scratch *scratch;

net/netfilter/nft_set_pipapo.c

429

scratch = *raw_cpu_ptr(m->scratch);

net/netfilter/nft_set_pipapo.c

430

if (unlikely(!scratch))

net/netfilter/nft_set_pipapo.c

432

__local_lock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo.c

434

map_index = scratch->map_index;

net/netfilter/nft_set_pipapo.c

436

map = NFT_PIPAPO_LT_ALIGN(&scratch->__map[0]);

net/netfilter/nft_set_pipapo.c

468

scratch->map_index = map_index;

net/netfilter/nft_set_pipapo.c

469

__local_unlock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo.c

488

scratch->map_index = map_index;

net/netfilter/nft_set_pipapo.c

489

__local_unlock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo.c

504

__local_unlock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo.h

148

struct nft_pipapo_scratch * __percpu *scratch;

net/netfilter/nft_set_pipapo_avx2.c

1156

struct nft_pipapo_scratch *scratch;

net/netfilter/nft_set_pipapo_avx2.c

1162

scratch = *raw_cpu_ptr(m->scratch);

net/netfilter/nft_set_pipapo_avx2.c

1163

if (unlikely(!scratch))

net/netfilter/nft_set_pipapo_avx2.c

1166

__local_lock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo_avx2.c

1167

map_index = scratch->map_index;

net/netfilter/nft_set_pipapo_avx2.c

1168

map = NFT_PIPAPO_LT_ALIGN(&scratch->__map[0]);

net/netfilter/nft_set_pipapo_avx2.c

1230

scratch->map_index = map_index;

net/netfilter/nft_set_pipapo_avx2.c

1232

__local_unlock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo_avx2.c

1247

scratch->map_index = map_index;

net/netfilter/nft_set_pipapo_avx2.c

1249

__local_unlock_nested_bh(&scratch->bh_lock);

net/netfilter/nft_set_pipapo_avx2.c

1259

__local_unlock_nested_bh(&scratch->bh_lock);

net/sunrpc/auth_gss/gss_rpc_xdr.c

843

struct folio *scratch;

net/sunrpc/auth_gss/gss_rpc_xdr.c

845

scratch = folio_alloc(GFP_KERNEL, 0);

net/sunrpc/auth_gss/gss_rpc_xdr.c

846

if (!scratch)

net/sunrpc/auth_gss/gss_rpc_xdr.c

848

xdr_set_scratch_folio(xdr, scratch);

net/sunrpc/auth_gss/gss_rpc_xdr.c

893

folio_put(scratch);

net/sunrpc/xdr.c

1002

memcpy(xdr->scratch.iov_base, page, shift);

net/sunrpc/xdr.c

1466

char *cpdest = xdr->scratch.iov_base;

net/sunrpc/xdr.c

1469

if (nbytes > xdr->scratch.iov_len)

net/sunrpc/xdr.c

1483

return xdr->scratch.iov_base;

net/sunrpc/xdr.c

998

size_t shift = xdr->scratch.iov_len;

security/keys/trusted-keys/trusted_tpm2.c

28

u8 *scratch = kmalloc(SCRATCH_SIZE, GFP_KERNEL);

security/keys/trusted-keys/trusted_tpm2.c

29

u8 *work = scratch, *work1;

security/keys/trusted-keys/trusted_tpm2.c

30

u8 *end_work = scratch + SCRATCH_SIZE;

security/keys/trusted-keys/trusted_tpm2.c

43

if (!scratch)

security/keys/trusted-keys/trusted_tpm2.c

66

if (WARN(work - scratch + pub_len + priv_len + 14 > SCRATCH_SIZE,

security/keys/trusted-keys/trusted_tpm2.c

78

scratch, work - scratch);

security/keys/trusted-keys/trusted_tpm2.c

85

kfree(scratch);

security/keys/trusted-keys/trusted_tpm2.c

89

kfree(scratch);

sound/soc/codecs/wm_adsp.c

419

void *scratch __free(kvfree) = vmemdup_user(bytes, size);

sound/soc/codecs/wm_adsp.c

421

if (IS_ERR(scratch))

sound/soc/codecs/wm_adsp.c

422

return PTR_ERR(scratch);

sound/soc/codecs/wm_adsp.c

424

return cs_dsp_coeff_lock_and_write_ctrl(cs_ctl, 0, scratch, size);

sound/soc/intel/catpt/core.h

93

struct resource *scratch;

sound/soc/intel/catpt/messages.c

48

struct resource *scratch,

sound/soc/intel/catpt/messages.c

76

if (scratch) {

sound/soc/intel/catpt/messages.c

77

input.scratch_mem.offset = catpt_to_dsp_offset(scratch->start);

sound/soc/intel/catpt/messages.c

78

input.scratch_mem.size = resource_size(scratch);

sound/soc/intel/catpt/messages.h

215

struct resource *scratch,

sound/soc/intel/catpt/pcm.c

1170

cdev->scratch = res;

sound/soc/intel/catpt/pcm.c

408

cdev->scratch,

tools/lib/bpf/bpf_tracing.h

394

#define __PT_PARM1_REG scratch.r0

tools/lib/bpf/bpf_tracing.h

395

#define __PT_PARM2_REG scratch.r1

tools/lib/bpf/bpf_tracing.h

396

#define __PT_PARM3_REG scratch.r2

tools/lib/bpf/bpf_tracing.h

397

#define __PT_PARM4_REG scratch.r3

tools/lib/bpf/bpf_tracing.h

398

#define __PT_PARM5_REG scratch.r4

tools/lib/bpf/bpf_tracing.h

399

#define __PT_PARM6_REG scratch.r5

tools/lib/bpf/bpf_tracing.h

400

#define __PT_PARM7_REG scratch.r6

tools/lib/bpf/bpf_tracing.h

401

#define __PT_PARM8_REG scratch.r7

tools/lib/bpf/bpf_tracing.h

412

#define __PT_RET_REG scratch.blink

tools/lib/bpf/bpf_tracing.h

413

#define __PT_FP_REG scratch.fp

tools/lib/bpf/bpf_tracing.h

414

#define __PT_RC_REG scratch.r0

tools/lib/bpf/bpf_tracing.h

415

#define __PT_SP_REG scratch.sp

tools/lib/bpf/bpf_tracing.h

416

#define __PT_IP_REG scratch.ret

tools/testing/selftests/bpf/disasm_helpers.c

31

snprintf(ctx->scratch, sizeof(ctx->scratch), "%+d", insn->off);

tools/testing/selftests/bpf/disasm_helpers.c

32

return ctx->scratch;

tools/testing/selftests/bpf/disasm_helpers.c

7

char scratch[16];

tools/testing/selftests/bpf/progs/test_cls_redirect.c

184

static __always_inline void *buf_assign(buf_t *buf, const size_t len, void *scratch)

tools/testing/selftests/bpf/progs/test_cls_redirect.c

187

if (scratch == NULL) {

tools/testing/selftests/bpf/progs/test_cls_redirect.c

191

return buf_copy(buf, scratch, len) ? scratch : NULL;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

214

static __always_inline struct iphdr *pkt_parse_ipv4(buf_t *pkt, struct iphdr *scratch)

tools/testing/selftests/bpf/progs/test_cls_redirect.c

216

struct iphdr *ipv4 = buf_assign(pkt, sizeof(*ipv4), scratch);

tools/testing/selftests/bpf/progs/test_cls_redirect.c

349

pkt_parse_ipv6(buf_t *pkt, struct ipv6hdr *scratch, uint8_t *proto,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

352

struct ipv6hdr *ipv6 = buf_assign(pkt, sizeof(*ipv6), scratch);

tools/testing/selftests/mm/protection_keys.c

1403

int scratch;

tools/testing/selftests/mm/protection_keys.c

1408

lots_o_noops_around_write(&scratch);

tools/testing/selftests/mm/protection_keys.c

1422

lots_o_noops_around_write(&scratch);

tools/testing/selftests/mm/protection_keys.c

1435

int scratch;

tools/testing/selftests/mm/protection_keys.c

1442

lots_o_noops_around_write(&scratch);

tools/testing/selftests/mm/protection_keys.c

1461

lots_o_noops_around_write(&scratch);

tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h

50

#define DCBT_SETUP_STREAMS(from, from_parms, to, to_parms, scratch) \

tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h

51

lis scratch,0x8000; /* GO=1 */ \

tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h

52

clrldi scratch,scratch,32; \

tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h

60

dcbt 0,scratch,0b01010; /* all streams GO */

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

509

#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

510

lis scratch,0x60000000@h; \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

513

dcbt 0,scratch,0b01010; \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

516

#define DCBT_SETUP_STREAMS(from, from_parms, to, to_parms, scratch) \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

517

lis scratch,0x8000; /* GO=1 */ \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

518

clrldi scratch,scratch,32; \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

528

dcbt 0,scratch,0b01010; /* all streams GO */ \