arch/arm/mach-qcom/platsmp.c

103

reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;

arch/arm/mach-qcom/platsmp.c

104

writel(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

111

reg_val &= ~CORE_MEM_CLAMP;

arch/arm/mach-qcom/platsmp.c

112

writel(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

113

reg_val |= L2DT_SLP;

arch/arm/mach-qcom/platsmp.c

114

writel(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

117

reg_val = (reg_val | BIT(17)) & ~CLAMP;

arch/arm/mach-qcom/platsmp.c

118

writel(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

122

reg_val &= ~(CORE_RST | COREPOR_RST);

arch/arm/mach-qcom/platsmp.c

123

writel(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

124

reg_val |= CORE_PWRD_UP;

arch/arm/mach-qcom/platsmp.c

125

writel(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

219

unsigned reg_val;

arch/arm/mach-qcom/platsmp.c

257

reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;

arch/arm/mach-qcom/platsmp.c

258

writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);

arch/arm/mach-qcom/platsmp.c

264

reg_val |= 0x3f << BHS_SEG_SHIFT;

arch/arm/mach-qcom/platsmp.c

265

writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);

arch/arm/mach-qcom/platsmp.c

271

reg_val |= 0x3f << LDO_BYP_SHIFT;

arch/arm/mach-qcom/platsmp.c

272

writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);

arch/arm/mach-qcom/platsmp.c

279

reg_val = COREPOR_RST | CLAMP;

arch/arm/mach-qcom/platsmp.c

280

writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

284

reg_val &= ~CLAMP;

arch/arm/mach-qcom/platsmp.c

285

writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

289

reg_val &= ~COREPOR_RST;

arch/arm/mach-qcom/platsmp.c

290

writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

293

reg_val |= CORE_PWRD_UP;

arch/arm/mach-qcom/platsmp.c

294

writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);

arch/arm/mach-qcom/platsmp.c

84

u32 reg_val;

arch/arm/plat-orion/gpio.c

498

u32 reg_val;

arch/arm/plat-orion/gpio.c

502

reg_val = irq_reg_readl(gc, ct->regs.mask);

arch/arm/plat-orion/gpio.c

503

reg_val |= mask;

arch/arm/plat-orion/gpio.c

504

irq_reg_writel(gc, reg_val, ct->regs.mask);

arch/arm/plat-orion/gpio.c

512

u32 reg_val;

arch/arm/plat-orion/gpio.c

515

reg_val = irq_reg_readl(gc, ct->regs.mask);

arch/arm/plat-orion/gpio.c

516

reg_val &= ~mask;

arch/arm/plat-orion/gpio.c

517

irq_reg_writel(gc, reg_val, ct->regs.mask);

arch/mips/include/asm/mips-cps.h

76

uint##sz##_t reg_val = read_##unit##_##name(); \

arch/mips/include/asm/mips-cps.h

77

reg_val &= ~mask; \

arch/mips/include/asm/mips-cps.h

78

reg_val |= val; \

arch/mips/include/asm/mips-cps.h

79

write_##unit##_##name(reg_val); \

arch/mips/kernel/traps.c

1837

unsigned int reg_val;

arch/mips/kernel/traps.c

1842

reg_val = read_c0_cacheerr();

arch/mips/kernel/traps.c

1843

printk("c0_cacheerr == %08x\n", reg_val);

arch/mips/kernel/traps.c

1846

reg_val & (1<<30) ? "secondary" : "primary",

arch/mips/kernel/traps.c

1847

reg_val & (1<<31) ? "data" : "insn");

arch/mips/kernel/traps.c

1851

reg_val & (1<<29) ? "ED " : "",

arch/mips/kernel/traps.c

1852

reg_val & (1<<28) ? "ET " : "",

arch/mips/kernel/traps.c

1853

reg_val & (1<<27) ? "ES " : "",

arch/mips/kernel/traps.c

1854

reg_val & (1<<26) ? "EE " : "",

arch/mips/kernel/traps.c

1855

reg_val & (1<<25) ? "EB " : "",

arch/mips/kernel/traps.c

1856

reg_val & (1<<24) ? "EI " : "",

arch/mips/kernel/traps.c

1857

reg_val & (1<<23) ? "E1 " : "",

arch/mips/kernel/traps.c

1858

reg_val & (1<<22) ? "E0 " : "");

arch/mips/kernel/traps.c

1861

reg_val & (1<<29) ? "ED " : "",

arch/mips/kernel/traps.c

1862

reg_val & (1<<28) ? "ET " : "",

arch/mips/kernel/traps.c

1863

reg_val & (1<<26) ? "EE " : "",

arch/mips/kernel/traps.c

1864

reg_val & (1<<25) ? "EB " : "",

arch/mips/kernel/traps.c

1865

reg_val & (1<<24) ? "EI " : "",

arch/mips/kernel/traps.c

1866

reg_val & (1<<23) ? "E1 " : "",

arch/mips/kernel/traps.c

1867

reg_val & (1<<22) ? "E0 " : "");

arch/mips/kernel/traps.c

1869

printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));

arch/mips/kernel/traps.c

1872

if (reg_val & (1<<22))

arch/mips/kernel/traps.c

1875

if (reg_val & (1<<23))

arch/mips/kernel/traps.c

1885

unsigned int reg_val;

arch/mips/kernel/traps.c

1894

reg_val = read_c0_cacheerr();

arch/mips/kernel/traps.c

1895

pr_err("c0_cacheerr == %08x\n", reg_val);

arch/mips/kernel/traps.c

1897

if ((reg_val & 0xc0000000) == 0xc0000000) {

arch/mips/kernel/traps.c

1901

reg_val & (1<<30) ? "secondary" : "primary",

arch/mips/kernel/traps.c

1902

reg_val & (1<<31) ? "data" : "insn");

arch/mips/pci/fixup-malta.c

109

pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);

arch/mips/pci/fixup-malta.c

110

reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;

arch/mips/pci/fixup-malta.c

111

pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);

arch/mips/pci/fixup-malta.c

124

unsigned char reg_val;

arch/mips/pci/fixup-malta.c

132

&reg_val);

arch/mips/pci/fixup-malta.c

134

reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);

arch/mips/pci/fixup-malta.c

136

&reg_val);

arch/mips/pci/fixup-malta.c

138

reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);

arch/mips/pci/fixup-malta.c

70

unsigned char reg_val;

arch/mips/pci/fixup-malta.c

84

pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);

arch/mips/pci/fixup-malta.c

85

if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)

arch/mips/pci/fixup-malta.c

88

pci_irq[PCIA+i] = piixirqmap[reg_val &

arch/mips/pci/fixup-malta.c

98

pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);

arch/mips/pci/fixup-malta.c

99

pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |

arch/powerpc/platforms/powernv/opal-fadump.h

101

regs->link = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

104

regs->xer = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

107

regs->dar = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

110

regs->dsisr = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

113

regs->nip = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

116

regs->msr = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

119

regs->ccr = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

137

val = (cpu_endian ? be64_to_cpu(reg_entry->reg_val) :

arch/powerpc/platforms/powernv/opal-fadump.h

138

(u64 __force)(reg_entry->reg_val));

arch/powerpc/platforms/powernv/opal-fadump.h

83

__be64 reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

88

u64 reg_val)

arch/powerpc/platforms/powernv/opal-fadump.h

92

regs->gpr[reg_num] = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

98

regs->ctr = reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

307

static void __init rtas_fadump_set_regval(struct pt_regs *regs, u64 reg_id, u64 reg_val)

arch/powerpc/platforms/pseries/rtas-fadump.c

313

regs->gpr[i] = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

315

regs->nip = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

317

regs->msr = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

319

regs->ctr = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

321

regs->link = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

323

regs->xer = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

325

regs->ccr = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

327

regs->dar = (unsigned long)reg_val;

arch/powerpc/platforms/pseries/rtas-fadump.c

329

regs->dsisr = (unsigned long)reg_val;

arch/riscv/include/asm/kvm_vcpu_sbi.h

67

unsigned long reg_size, void *reg_val);

arch/riscv/include/asm/kvm_vcpu_sbi.h

69

unsigned long reg_size, const void *reg_val);

arch/riscv/kvm/vcpu_fp.c

100

reg_val = &cntx->fp.f.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

108

reg_val = &cntx->fp.d.fcsr;

arch/riscv/kvm/vcpu_fp.c

115

reg_val = &cntx->fp.d.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

121

if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_fp.c

137

void *reg_val;

arch/riscv/kvm/vcpu_fp.c

144

reg_val = &cntx->fp.f.fcsr;

arch/riscv/kvm/vcpu_fp.c

149

reg_val = &cntx->fp.f.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

157

reg_val = &cntx->fp.d.fcsr;

arch/riscv/kvm/vcpu_fp.c

164

reg_val = &cntx->fp.d.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

170

if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_fp.c

88

void *reg_val;

arch/riscv/kvm/vcpu_fp.c

95

reg_val = &cntx->fp.f.fcsr;

arch/riscv/kvm/vcpu_onereg.c

283

unsigned long reg_val;

arch/riscv/kvm/vcpu_onereg.c

290

reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;

arch/riscv/kvm/vcpu_onereg.c

295

reg_val = riscv_cbom_block_size;

arch/riscv/kvm/vcpu_onereg.c

300

reg_val = riscv_cboz_block_size;

arch/riscv/kvm/vcpu_onereg.c

305

reg_val = riscv_cbop_block_size;

arch/riscv/kvm/vcpu_onereg.c

308

reg_val = vcpu->arch.mvendorid;

arch/riscv/kvm/vcpu_onereg.c

311

reg_val = vcpu->arch.marchid;

arch/riscv/kvm/vcpu_onereg.c

314

reg_val = vcpu->arch.mimpid;

arch/riscv/kvm/vcpu_onereg.c

317

reg_val = satp_mode >> SATP_MODE_SHIFT;

arch/riscv/kvm/vcpu_onereg.c

323

if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

337

unsigned long i, isa_ext, reg_val;

arch/riscv/kvm/vcpu_onereg.c

342

if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

351

if (fls(reg_val) >= RISCV_ISA_EXT_BASE)

arch/riscv/kvm/vcpu_onereg.c

358

if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK))

arch/riscv/kvm/vcpu_onereg.c

366

reg_val &= ~BIT(i);

arch/riscv/kvm/vcpu_onereg.c

370

if (reg_val & BIT(i))

arch/riscv/kvm/vcpu_onereg.c

371

reg_val &= ~BIT(i);

arch/riscv/kvm/vcpu_onereg.c

373

if (!(reg_val & BIT(i)))

arch/riscv/kvm/vcpu_onereg.c

374

reg_val |= BIT(i);

arch/riscv/kvm/vcpu_onereg.c

376

reg_val &= riscv_isa_extension_base(NULL);

arch/riscv/kvm/vcpu_onereg.c

378

reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |

arch/riscv/kvm/vcpu_onereg.c

379

(reg_val & KVM_RISCV_BASE_ISA_MASK);

arch/riscv/kvm/vcpu_onereg.c

380

vcpu->arch.isa[0] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

389

if (reg_val != riscv_cbom_block_size)

arch/riscv/kvm/vcpu_onereg.c

395

if (reg_val != riscv_cboz_block_size)

arch/riscv/kvm/vcpu_onereg.c

401

if (reg_val != riscv_cbop_block_size)

arch/riscv/kvm/vcpu_onereg.c

405

if (reg_val == vcpu->arch.mvendorid)

arch/riscv/kvm/vcpu_onereg.c

408

vcpu->arch.mvendorid = reg_val;

arch/riscv/kvm/vcpu_onereg.c

413

if (reg_val == vcpu->arch.marchid)

arch/riscv/kvm/vcpu_onereg.c

416

vcpu->arch.marchid = reg_val;

arch/riscv/kvm/vcpu_onereg.c

421

if (reg_val == vcpu->arch.mimpid)

arch/riscv/kvm/vcpu_onereg.c

424

vcpu->arch.mimpid = reg_val;

arch/riscv/kvm/vcpu_onereg.c

429

if (reg_val != (satp_mode >> SATP_MODE_SHIFT))

arch/riscv/kvm/vcpu_onereg.c

449

unsigned long reg_val;

arch/riscv/kvm/vcpu_onereg.c

459

reg_val = cntx->sepc;

arch/riscv/kvm/vcpu_onereg.c

462

reg_val = ((unsigned long *)cntx)[reg_num];

arch/riscv/kvm/vcpu_onereg.c

464

reg_val = (cntx->sstatus & SR_SPP) ?

arch/riscv/kvm/vcpu_onereg.c

469

if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

485

unsigned long reg_val;

arch/riscv/kvm/vcpu_onereg.c

494

if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

498

cntx->sepc = reg_val;

arch/riscv/kvm/vcpu_onereg.c

501

((unsigned long *)cntx)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

503

if (reg_val == KVM_RISCV_MODE_S)

arch/riscv/kvm/vcpu_onereg.c

537

unsigned long reg_val)

arch/riscv/kvm/vcpu_onereg.c

548

reg_val &= VSIP_VALID_MASK;

arch/riscv/kvm/vcpu_onereg.c

549

reg_val <<= VSIP_TO_HVIP_SHIFT;

arch/riscv/kvm/vcpu_onereg.c

552

((unsigned long *)csr)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

562

unsigned long reg_val)

arch/riscv/kvm/vcpu_onereg.c

575

((unsigned long *)csr)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

607

unsigned long reg_val, reg_subtype;

arch/riscv/kvm/vcpu_onereg.c

616

rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

619

rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

622

rc = kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

631

if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

646

unsigned long reg_val, reg_subtype;

arch/riscv/kvm/vcpu_onereg.c

651

if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

658

rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

661

rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

664

rc = kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

678

unsigned long *reg_val)

arch/riscv/kvm/vcpu_onereg.c

687

*reg_val = 0;

arch/riscv/kvm/vcpu_onereg.c

689

*reg_val = 1; /* Mark the given extension as available */

arch/riscv/kvm/vcpu_onereg.c

696

unsigned long reg_val)

arch/riscv/kvm/vcpu_onereg.c

705

if (reg_val == test_bit(guest_ext, vcpu->arch.isa))

arch/riscv/kvm/vcpu_onereg.c

713

if (reg_val == 1 &&

arch/riscv/kvm/vcpu_onereg.c

716

else if (!reg_val &&

arch/riscv/kvm/vcpu_onereg.c

731

unsigned long *reg_val)

arch/riscv/kvm/vcpu_onereg.c

746

*reg_val |= KVM_REG_RISCV_ISA_MULTI_MASK(ext_id);

arch/riscv/kvm/vcpu_onereg.c

754

unsigned long reg_val, bool enable)

arch/riscv/kvm/vcpu_onereg.c

761

for_each_set_bit(i, &reg_val, BITS_PER_LONG) {

arch/riscv/kvm/vcpu_onereg.c

781

unsigned long reg_val, reg_subtype;

arch/riscv/kvm/vcpu_onereg.c

789

reg_val = 0;

arch/riscv/kvm/vcpu_onereg.c

792

rc = riscv_vcpu_get_isa_ext_single(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

796

rc = riscv_vcpu_get_isa_ext_multi(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

798

reg_val = ~reg_val;

arch/riscv/kvm/vcpu_onereg.c

806

if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

820

unsigned long reg_val, reg_subtype;

arch/riscv/kvm/vcpu_onereg.c

828

if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_onereg.c

833

return riscv_vcpu_set_isa_ext_single(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

835

return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, true);

arch/riscv/kvm/vcpu_onereg.c

837

return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false);

arch/riscv/kvm/vcpu_sbi.c

220

unsigned long reg_val)

arch/riscv/kvm/vcpu_sbi.c

225

if (reg_val != 1 && reg_val != 0)

arch/riscv/kvm/vcpu_sbi.c

232

scontext->ext_status[sext->ext_idx] = (reg_val) ?

arch/riscv/kvm/vcpu_sbi.c

241

unsigned long *reg_val)

arch/riscv/kvm/vcpu_sbi.c

250

*reg_val = scontext->ext_status[sext->ext_idx] ==

arch/riscv/kvm/vcpu_sbi.c

258

unsigned long reg_val, bool enable)

arch/riscv/kvm/vcpu_sbi.c

265

for_each_set_bit(i, &reg_val, BITS_PER_LONG) {

arch/riscv/kvm/vcpu_sbi.c

278

unsigned long *reg_val)

arch/riscv/kvm/vcpu_sbi.c

293

*reg_val |= KVM_REG_RISCV_SBI_MULTI_MASK(ext_id);

arch/riscv/kvm/vcpu_sbi.c

332

unsigned long reg_val, reg_subtype;

arch/riscv/kvm/vcpu_sbi.c

343

if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_sbi.c

348

return riscv_vcpu_set_sbi_ext_single(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_sbi.c

350

return riscv_vcpu_set_sbi_ext_multi(vcpu, reg_num, reg_val, true);

arch/riscv/kvm/vcpu_sbi.c

352

return riscv_vcpu_set_sbi_ext_multi(vcpu, reg_num, reg_val, false);

arch/riscv/kvm/vcpu_sbi.c

369

unsigned long reg_val, reg_subtype;

arch/riscv/kvm/vcpu_sbi.c

377

reg_val = 0;

arch/riscv/kvm/vcpu_sbi.c

380

rc = riscv_vcpu_get_sbi_ext_single(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_sbi.c

384

rc = riscv_vcpu_get_sbi_ext_multi(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_sbi.c

386

reg_val = ~reg_val;

arch/riscv/kvm/vcpu_sbi.c

394

if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_sbi.c

476

void *reg_val;

arch/riscv/kvm/vcpu_sbi.c

484

reg_val = &data8;

arch/riscv/kvm/vcpu_sbi.c

487

reg_val = &data16;

arch/riscv/kvm/vcpu_sbi.c

490

reg_val = &data32;

arch/riscv/kvm/vcpu_sbi.c

493

reg_val = &data64;

arch/riscv/kvm/vcpu_sbi.c

499

if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_sbi.c

509

return ext->set_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val);

arch/riscv/kvm/vcpu_sbi.c

521

void *reg_val;

arch/riscv/kvm/vcpu_sbi.c

530

reg_val = &data8;

arch/riscv/kvm/vcpu_sbi.c

533

reg_val = &data16;

arch/riscv/kvm/vcpu_sbi.c

536

reg_val = &data32;

arch/riscv/kvm/vcpu_sbi.c

539

reg_val = &data64;

arch/riscv/kvm/vcpu_sbi.c

552

ret = ext->get_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val);

arch/riscv/kvm/vcpu_sbi.c

556

if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_sbi_fwft.c

450

unsigned long reg_size, void *reg_val)

arch/riscv/kvm/vcpu_sbi_fwft.c

459

value = reg_val;

arch/riscv/kvm/vcpu_sbi_fwft.c

487

unsigned long reg_size, const void *reg_val)

arch/riscv/kvm/vcpu_sbi_fwft.c

496

value = *(const unsigned long *)reg_val;

arch/riscv/kvm/vcpu_sbi_sta.c

155

unsigned long reg_size, void *reg_val)

arch/riscv/kvm/vcpu_sbi_sta.c

161

value = reg_val;

arch/riscv/kvm/vcpu_sbi_sta.c

181

unsigned long reg_size, const void *reg_val)

arch/riscv/kvm/vcpu_sbi_sta.c

187

value = *(const unsigned long *)reg_val;

arch/riscv/kvm/vcpu_timer.c

169

u64 reg_val;

arch/riscv/kvm/vcpu_timer.c

178

reg_val = riscv_timebase;

arch/riscv/kvm/vcpu_timer.c

181

reg_val = kvm_riscv_current_cycles(gt);

arch/riscv/kvm/vcpu_timer.c

184

reg_val = t->next_cycles;

arch/riscv/kvm/vcpu_timer.c

187

reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON :

arch/riscv/kvm/vcpu_timer.c

194

if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_timer.c

209

u64 reg_val;

arch/riscv/kvm/vcpu_timer.c

217

if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))

arch/riscv/kvm/vcpu_timer.c

222

if (reg_val != riscv_timebase)

arch/riscv/kvm/vcpu_timer.c

226

gt->time_delta = reg_val - get_cycles64();

arch/riscv/kvm/vcpu_timer.c

229

t->next_cycles = reg_val;

arch/riscv/kvm/vcpu_timer.c

232

if (reg_val == KVM_RISCV_TIMER_STATE_ON)

arch/riscv/kvm/vcpu_timer.c

233

ret = kvm_riscv_vcpu_timer_next_event(vcpu, reg_val);

arch/riscv/kvm/vcpu_vector.c

183

unsigned long reg_val;

arch/riscv/kvm/vcpu_vector.c

185

if (reg_size != sizeof(reg_val))

arch/riscv/kvm/vcpu_vector.c

187

if (copy_from_user(&reg_val, uaddr, reg_size))

arch/riscv/kvm/vcpu_vector.c

189

if (reg_val != cntx->vector.vlenb)

arch/sparc/include/asm/hypervisor.h

3446

unsigned long *reg_val);

arch/sparc/include/asm/hypervisor.h

3448

unsigned long reg_val);

arch/sparc/include/asm/hypervisor.h

3456

unsigned long *reg_val);

arch/sparc/include/asm/hypervisor.h

3458

unsigned long reg_val);

arch/sparc/include/asm/hypervisor.h

3467

unsigned long *reg_val);

arch/sparc/include/asm/hypervisor.h

3469

unsigned long reg_val);

arch/x86/hyperv/hv_apic.c

39

u64 reg_val;

arch/x86/hyperv/hv_apic.c

41

rdmsrq(HV_X64_MSR_ICR, reg_val);

arch/x86/hyperv/hv_apic.c

42

return reg_val;

arch/x86/hyperv/hv_apic.c

47

u64 reg_val;

arch/x86/hyperv/hv_apic.c

49

reg_val = SET_XAPIC_DEST_FIELD(id);

arch/x86/hyperv/hv_apic.c

50

reg_val = reg_val << 32;

arch/x86/hyperv/hv_apic.c

51

reg_val |= low;

arch/x86/hyperv/hv_apic.c

53

wrmsrq(HV_X64_MSR_ICR, reg_val);

arch/x86/hyperv/hv_apic.c

63

u32 reg_val, hi;

arch/x86/hyperv/hv_apic.c

67

rdmsr(HV_X64_MSR_EOI, reg_val, hi);

arch/x86/hyperv/hv_apic.c

69

return reg_val;

arch/x86/hyperv/hv_apic.c

71

rdmsr(HV_X64_MSR_TPR, reg_val, hi);

arch/x86/hyperv/hv_apic.c

73

return reg_val;

drivers/accel/habanalabs/common/firmware_if.c

1557

u32 reg_val;

drivers/accel/habanalabs/common/firmware_if.c

1577

reg_val = RREG32(pre_fw_load->sts_boot_dev_sts0_reg);

drivers/accel/habanalabs/common/firmware_if.c

1578

if (reg_val & CPU_BOOT_DEV_STS0_ENABLED) {

drivers/accel/habanalabs/common/firmware_if.c

1580

prop->fw_preboot_cpu_boot_dev_sts0 = reg_val;

drivers/accel/habanalabs/common/firmware_if.c

1583

reg_val = RREG32(pre_fw_load->sts_boot_dev_sts1_reg);

drivers/accel/habanalabs/common/firmware_if.c

1584

if (reg_val & CPU_BOOT_DEV_STS1_ENABLED) {

drivers/accel/habanalabs/common/firmware_if.c

1586

prop->fw_preboot_cpu_boot_dev_sts1 = reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

3598

u32 reg_base, reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

3622

reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

3623

WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

3632

reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

3633

WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4363

u32 reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

4365

reg_val = FIELD_PREP(PDMA0_CORE_CFG_1_HALT_MASK, 0x1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4366

WREG32(reg_base + DMA_CORE_CFG_1_OFFSET, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4434

u32 reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

4440

reg_val = FIELD_PREP(ROT_MSS_HALT_WBC_MASK, 0x1) |

drivers/accel/habanalabs/gaudi2/gaudi2.c

4448

WREG32(mmROT0_MSS_HALT + i * ROT_OFFSET, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4851

u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4870

WREG32(mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4891

u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4910

WREG32(mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4945

u32 reg_base, reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

4949

reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4951

reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

4953

WREG32(reg_base + ARC_HALT_REQ_OFFSET, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5054

u32 reg_base, reg_addr, reg_val, tpc_id;

drivers/accel/habanalabs/gaudi2/gaudi2.c

5065

reg_val = FIELD_PREP(DCORE0_TPC0_CFG_TPC_STALL_V_MASK,

drivers/accel/habanalabs/gaudi2/gaudi2.c

5067

WREG32(reg_addr, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5081

u32 reg_base, reg_addr, reg_val, mme_id;

drivers/accel/habanalabs/gaudi2/gaudi2.c

5089

reg_val = FIELD_PREP(DCORE0_MME_CTRL_LO_QM_STALL_V_MASK,

drivers/accel/habanalabs/gaudi2/gaudi2.c

5091

WREG32(reg_addr, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5099

u32 reg_base, reg_addr, reg_val, edma_id;

drivers/accel/habanalabs/gaudi2/gaudi2.c

5110

reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK,

drivers/accel/habanalabs/gaudi2/gaudi2.c

5112

WREG32(reg_addr, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5115

reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK, 0x1) |

drivers/accel/habanalabs/gaudi2/gaudi2.c

5117

WREG32(reg_addr, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5758

u32 reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

5762

reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5763

reg_val |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5766

WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5769

reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5770

WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5800

u32 reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

5803

reg_val = FIELD_PREP(MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK, 0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5804

reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5805

reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5806

reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NAN_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5807

reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5808

reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK, 1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5810

WREG32(reg_base + MME_ACC_INTR_MASK_OFFSET, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

6704

u32 reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

6713

reg_val,

drivers/accel/habanalabs/gaudi2/gaudi2.c

6714

reg_val == 0,

drivers/accel/habanalabs/gaudi2/gaudi2.c

6719

dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7943

u32 vdec_id, i, ports_offset, reg_val;

drivers/accel/habanalabs/gaudi2/gaudi2.c

7969

reg_val = (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT) |

drivers/accel/habanalabs/gaudi2/gaudi2.c

7971

WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID + dcore_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8038

u32 reg_base, reg_offset, reg_val = 0;

drivers/accel/habanalabs/gaudi2/gaudi2.c

8043

reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK, 0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8044

reg_val |= FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK, asid);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8047

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8050

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8053

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8056

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8059

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8062

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8065

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8068

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8071

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8074

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8077

WREG32(reg_base + reg_offset, reg_val);

drivers/accel/ivpu/ivpu_hw_reg_io.h

66

u32 reg_val;

drivers/accel/ivpu/ivpu_hw_reg_io.h

72

ret = read_poll_timeout(readl, reg_val, (reg_val & reg_mask) == exp_masked_val,

drivers/accel/ivpu/ivpu_hw_reg_io.h

81

func_name, reg_name, reg_offset, fld_name, ret ? "ETIMEDOUT" : "OK", reg_val);

drivers/acpi/pmic/intel_pmic_bxtwc.c

300

unsigned int val, adc_val, reg_val;

drivers/acpi/pmic/intel_pmic_bxtwc.c

315

reg_val = temp_l | WHISKEY_COVE_ADC_HIGH_BIT(temp_h);

drivers/acpi/pmic/intel_pmic_bxtwc.c

318

adc_val = reg_val * rlsb / 1000;

drivers/ata/ahci_imx.c

602

u32 reg_val;

drivers/ata/ahci_imx.c

626

reg_val = readl(mmio + IMX_P0PHYCR);

drivers/ata/ahci_imx.c

627

writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);

drivers/ata/ahci_imx.c

862

unsigned int reg_val;

drivers/ata/ahci_imx.c

948

reg_val = readl(hpriv->mmio + HOST_CAP);

drivers/ata/ahci_imx.c

949

if (!(reg_val & HOST_CAP_SSS)) {

drivers/ata/ahci_imx.c

950

reg_val |= HOST_CAP_SSS;

drivers/ata/ahci_imx.c

951

writel(reg_val, hpriv->mmio + HOST_CAP);

drivers/ata/ahci_imx.c

953

reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);

drivers/ata/ahci_imx.c

954

if (!(reg_val & 0x1)) {

drivers/ata/ahci_imx.c

955

reg_val |= 0x1;

drivers/ata/ahci_imx.c

956

writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);

drivers/ata/ahci_imx.c

970

reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;

drivers/ata/ahci_imx.c

971

writel(reg_val, hpriv->mmio + IMX_TIMER1MS);

drivers/ata/ahci_sunxi.c

114

reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);

drivers/ata/ahci_sunxi.c

115

if (reg_val == 0x02)

drivers/ata/ahci_sunxi.c

129

reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);

drivers/ata/ahci_sunxi.c

130

if (reg_val == 0x00)

drivers/ata/ahci_sunxi.c

55

u32 reg_val;

drivers/ata/ahci_sunxi.c

57

reg_val = readl(reg);

drivers/ata/ahci_sunxi.c

58

reg_val &= ~(clr_val);

drivers/ata/ahci_sunxi.c

59

writel(reg_val, reg);

drivers/ata/ahci_sunxi.c

64

u32 reg_val;

drivers/ata/ahci_sunxi.c

66

reg_val = readl(reg);

drivers/ata/ahci_sunxi.c

67

reg_val |= set_val;

drivers/ata/ahci_sunxi.c

68

writel(reg_val, reg);

drivers/ata/ahci_sunxi.c

73

u32 reg_val;

drivers/ata/ahci_sunxi.c

75

reg_val = readl(reg);

drivers/ata/ahci_sunxi.c

76

reg_val &= ~(clr_val);

drivers/ata/ahci_sunxi.c

77

reg_val |= set_val;

drivers/ata/ahci_sunxi.c

78

writel(reg_val, reg);

drivers/ata/ahci_sunxi.c

88

u32 reg_val;

drivers/base/regmap/regmap.c

3101

unsigned int reg_val;

drivers/base/regmap/regmap.c

3102

ret = regmap_read(field->regmap, field->reg, &reg_val);

drivers/base/regmap/regmap.c

3106

reg_val &= field->mask;

drivers/base/regmap/regmap.c

3107

reg_val >>= field->shift;

drivers/base/regmap/regmap.c

3108

*val = reg_val;

drivers/base/regmap/regmap.c

3128

unsigned int reg_val;

drivers/base/regmap/regmap.c

3135

&reg_val);

drivers/base/regmap/regmap.c

3139

reg_val &= field->mask;

drivers/base/regmap/regmap.c

3140

reg_val >>= field->shift;

drivers/base/regmap/regmap.c

3141

*val = reg_val;

drivers/bluetooth/btrtl.c

1078

u8 reg_val[2];

drivers/bluetooth/btrtl.c

1089

ret = btrtl_vendor_read_reg16(hdev, RTL_CHIP_SUBVER, reg_val);

drivers/bluetooth/btrtl.c

1092

lmp_subver = get_unaligned_le16(reg_val);

drivers/bluetooth/btrtl.c

1095

ret = btrtl_vendor_read_reg16(hdev, RTL_CHIP_REV, reg_val);

drivers/bluetooth/btrtl.c

1098

hci_rev = get_unaligned_le16(reg_val);

drivers/bluetooth/btrtl.c

1188

rc = btrtl_vendor_read_reg16(hdev, RTL_SEC_PROJ, reg_val);

drivers/bluetooth/btrtl.c

1192

key_id = reg_val[0];

drivers/char/hw_random/cctrng.c

26

#define CC_REG_FLD_GET(reg_name, fld_name, reg_val) \

drivers/char/hw_random/cctrng.c

27

(FIELD_GET(CC_GENMASK(CC_ ## reg_name ## _ ## fld_name), reg_val))

drivers/clk/bcm/clk-kona.c

112

__ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val)

drivers/clk/bcm/clk-kona.c

114

writel(reg_val, ccu->base + reg_offset);

drivers/clk/bcm/clk-kona.c

312

u32 reg_val;

drivers/clk/bcm/clk-kona.c

314

reg_val = __ccu_read(ccu, offset);

drivers/clk/bcm/clk-kona.c

315

reg_val |= mask;

drivers/clk/bcm/clk-kona.c

316

__ccu_write(ccu, offset, reg_val);

drivers/clk/bcm/clk-kona.c

336

u32 reg_val;

drivers/clk/bcm/clk-kona.c

343

reg_val = __ccu_read(ccu, gate->offset);

drivers/clk/bcm/clk-kona.c

345

return (reg_val & bit_mask) != 0;

drivers/clk/bcm/clk-kona.c

35

static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width)

drivers/clk/bcm/clk-kona.c

37

return (reg_val & bitfield_mask(shift, width)) >> shift;

drivers/clk/bcm/clk-kona.c

373

u32 reg_val;

drivers/clk/bcm/clk-kona.c

381

reg_val = __ccu_read(ccu, gate->offset);

drivers/clk/bcm/clk-kona.c

387

reg_val |= mask;

drivers/clk/bcm/clk-kona.c

389

reg_val &= ~mask;

drivers/clk/bcm/clk-kona.c

402

reg_val |= mask;

drivers/clk/bcm/clk-kona.c

404

reg_val &= ~mask;

drivers/clk/bcm/clk-kona.c

406

__ccu_write(ccu, gate->offset, reg_val);

drivers/clk/bcm/clk-kona.c

41

static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val)

drivers/clk/bcm/clk-kona.c

45

return (reg_val & ~mask) | (val << shift);

drivers/clk/bcm/clk-kona.c

505

u32 reg_val;

drivers/clk/bcm/clk-kona.c

515

reg_val = __ccu_read(ccu, offset);

drivers/clk/bcm/clk-kona.c

516

reg_val |= mask;

drivers/clk/bcm/clk-kona.c

517

__ccu_write(ccu, offset, reg_val);

drivers/clk/bcm/clk-kona.c

542

u32 reg_val;

drivers/clk/bcm/clk-kona.c

549

reg_val = __ccu_read(ccu, div->u.s.offset);

drivers/clk/bcm/clk-kona.c

553

reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width);

drivers/clk/bcm/clk-kona.c

571

u32 reg_val;

drivers/clk/bcm/clk-kona.c

582

reg_val = __ccu_read(ccu, div->u.s.offset);

drivers/clk/bcm/clk-kona.c

583

reg_div = bitfield_extract(reg_val, div->u.s.shift,

drivers/clk/bcm/clk-kona.c

601

reg_val = __ccu_read(ccu, div->u.s.offset);

drivers/clk/bcm/clk-kona.c

602

reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width,

drivers/clk/bcm/clk-kona.c

604

__ccu_write(ccu, div->u.s.offset, reg_val);

drivers/clk/bcm/clk-kona.c

818

u32 reg_val;

drivers/clk/bcm/clk-kona.c

828

reg_val = __ccu_read(ccu, sel->offset);

drivers/clk/bcm/clk-kona.c

831

parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);

drivers/clk/bcm/clk-kona.c

853

u32 reg_val;

drivers/clk/bcm/clk-kona.c

867

reg_val = __ccu_read(ccu, sel->offset);

drivers/clk/bcm/clk-kona.c

868

parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);

drivers/clk/bcm/clk-kona.c

886

reg_val = __ccu_read(ccu, sel->offset);

drivers/clk/bcm/clk-kona.c

887

reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel);

drivers/clk/bcm/clk-kona.c

888

__ccu_write(ccu, sel->offset, reg_val);

drivers/clk/clk-axi-clkgen.c

269

unsigned int reg_val;

drivers/clk/clk-axi-clkgen.c

276

reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;

drivers/clk/clk-axi-clkgen.c

277

reg_val |= (reg << 16);

drivers/clk/clk-axi-clkgen.c

279

axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);

drivers/clk/clk-axi-clkgen.c

294

unsigned int reg_val = 0;

drivers/clk/clk-axi-clkgen.c

302

axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);

drivers/clk/clk-axi-clkgen.c

303

reg_val &= ~mask;

drivers/clk/clk-axi-clkgen.c

306

reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);

drivers/clk/clk-axi-clkgen.c

308

axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);

drivers/clk/thead/clk-th1520-ap.c

251

unsigned int curr_val, reg_val;

drivers/clk/thead/clk-th1520-ap.c

256

regmap_read(cd->common.map, cd->common.cfg0, &reg_val);

drivers/clk/thead/clk-th1520-ap.c

257

curr_val = reg_val >> cd->div.shift;

drivers/clk/thead/clk-th1520-ap.c

263

reg_val &= ~cd->div_en;

drivers/clk/thead/clk-th1520-ap.c

264

regmap_write(cd->common.map, cd->common.cfg0, reg_val);

drivers/clk/thead/clk-th1520-ap.c

267

reg_val &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);

drivers/clk/thead/clk-th1520-ap.c

268

reg_val |= val << cd->div.shift;

drivers/clk/thead/clk-th1520-ap.c

269

regmap_write(cd->common.map, cd->common.cfg0, reg_val);

drivers/clk/thead/clk-th1520-ap.c

271

reg_val |= cd->div_en;

drivers/clk/thead/clk-th1520-ap.c

272

regmap_write(cd->common.map, cd->common.cfg0, reg_val);

drivers/crypto/hisilicon/qm.c

1535

u32 reg_val, type, vf_num, qp_id;

drivers/crypto/hisilicon/qm.c

1547

reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);

drivers/crypto/hisilicon/qm.c

1548

type = (reg_val & QM_DB_TIMEOUT_TYPE) >>

drivers/crypto/hisilicon/qm.c

1550

vf_num = reg_val & QM_DB_TIMEOUT_VF;

drivers/crypto/hisilicon/qm.c

1551

qp_id = reg_val >> QM_DB_TIMEOUT_QP_SHIFT;

drivers/crypto/hisilicon/qm.c

1555

reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);

drivers/crypto/hisilicon/qm.c

1556

type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>

drivers/crypto/hisilicon/qm.c

1558

vf_num = reg_val & QM_FIFO_OVERFLOW_VF;

drivers/crypto/hisilicon/qm.c

1559

qp_id = reg_val >> QM_FIFO_OVERFLOW_QP_SHIFT;

drivers/crypto/hisilicon/qm.c

1566

reg_val = readl(qm->io_base + QM_ABNORMAL_INF02);

drivers/crypto/hisilicon/qm.c

1567

if (reg_val & QM_AXI_POISON_ERR)

drivers/crypto/intel/qat/qat_common/adf_admin.c

547

u64 reg_val;

drivers/crypto/intel/qat/qat_common/adf_admin.c

581

reg_val = (u64)admin->phy_addr;

drivers/crypto/intel/qat/qat_common/adf_admin.c

582

ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val));

drivers/crypto/intel/qat/qat_common/adf_admin.c

583

ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val));

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

42

u64 reg_val = 0;

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

44

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

46

ctx->val.vu8 = (reg_val >> 18) & 0x1;

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

58

u64 reg_val = 0;

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

65

&reg_val, BLKADDR_CPT0);

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

66

reg_val &= ~(0x1ULL << 18);

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

67

reg_val |= ((u64)ctx->val.vu8 & 0x1) << 18;

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

69

CPT_AF_CTL, reg_val, BLKADDR_CPT0);

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

595

u64 reg_val = 0x0;

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

601

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

603

if ((cpt_feature_sgv2(pdev) && (reg_val & BIT_ULL(18))) ||

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1155

u64 reg_val;

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1241

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1248

reg_val |= OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16);

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1250

reg_val, BLKADDR_CPT0);

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1267

&reg_val, BLKADDR_CPT0);

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1269

reg_val | BIT_ULL(24), BLKADDR_CPT0);

drivers/dma/tegra186-gpc-dma.c

1348

unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);

drivers/dma/tegra186-gpc-dma.c

1350

reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);

drivers/dma/tegra186-gpc-dma.c

1351

reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);

drivers/dma/tegra186-gpc-dma.c

1353

reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);

drivers/dma/tegra186-gpc-dma.c

1354

reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);

drivers/dma/tegra186-gpc-dma.c

1356

tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);

drivers/edac/dmc520_edac.c

255

u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG);

drivers/edac/dmc520_edac.c

257

return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val);

drivers/edac/dmc520_edac.c

263

u32 reg_val, scrub_cfg;

drivers/edac/dmc520_edac.c

265

reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW);

drivers/edac/dmc520_edac.c

266

scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val);

drivers/edac/dmc520_edac.c

280

u32 reg_val;

drivers/edac/dmc520_edac.c

282

reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL);

drivers/edac/dmc520_edac.c

283

mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val);

drivers/edac/dmc520_edac.c

296

u32 reg_val;

drivers/edac/dmc520_edac.c

298

reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);

drivers/edac/dmc520_edac.c

299

type = FIELD_GET(REG_FIELD_MEMORY_TYPE, reg_val);

drivers/edac/dmc520_edac.c

318

u32 reg_val;

drivers/edac/dmc520_edac.c

320

reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);

drivers/edac/dmc520_edac.c

321

device_width = FIELD_GET(REG_FIELD_DEVICE_WIDTH, reg_val);

drivers/edac/dmc520_edac.c

342

u32 reg_val, rank_bits;

drivers/edac/dmc520_edac.c

344

reg_val = readl(reg_base + REG_OFFSET_ADDRESS_CONTROL_NOW);

drivers/edac/dmc520_edac.c

345

rank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_RANK, reg_val);

drivers/edac/dmc520_edac.c

352

u32 reg_val, col_bits, row_bits, bank_bits;

drivers/edac/dmc520_edac.c

354

reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW);

drivers/edac/dmc520_edac.c

356

col_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_COL, reg_val) +

drivers/edac/dmc520_edac.c

358

row_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_ROW, reg_val) +

drivers/edac/dmc520_edac.c

360

bank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_BANK, reg_val);

drivers/edac/dmc520_edac.c

485

u32 reg_val;

drivers/edac/dmc520_edac.c

552

reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);

drivers/edac/dmc520_edac.c

553

dmc520_write_reg(pvt, reg_val & (~irq_mask_all),

drivers/edac/dmc520_edac.c

587

dmc520_write_reg(pvt, reg_val | irq_mask_all,

drivers/edac/dmc520_edac.c

605

u32 reg_val, idx, irq_mask_all = 0;

drivers/edac/dmc520_edac.c

613

reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);

drivers/edac/dmc520_edac.c

614

dmc520_write_reg(pvt, reg_val & (~irq_mask_all),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

127

u32 reg_val, payload_data;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

153

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

156

&reg_val, sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

158

KUNIT_EXPECT_EQ(test, reg_val, payload_data);

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

2109

u32 reg_val, payload_data;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

2150

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

2153

&reg_val, sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

2155

KUNIT_EXPECT_EQ(test, reg_val, payload_data);

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

342

u32 reg_val;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

373

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

375

regmap_raw_read(priv->dsp->regmap, reg_addr, &reg_val,

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

376

sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

378

KUNIT_EXPECT_MEMEQ(test, &reg_val, &payload_data[i], sizeof(reg_val));

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

402

u32 reg_val;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

454

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

456

regmap_raw_read(priv->dsp->regmap, reg_addr, &reg_val, sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

458

KUNIT_EXPECT_EQ(test, reg_val, payload_data[0]);

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

464

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

466

regmap_raw_read(priv->dsp->regmap, reg_addr, &reg_val, sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

468

KUNIT_EXPECT_EQ(test, reg_val, payload_data[1]);

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

475

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

477

regmap_raw_read(priv->dsp->regmap, reg_addr, &reg_val,

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

478

sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

480

KUNIT_EXPECT_EQ(test, reg_val, payload_data[2]);

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

502

u32 reg_val;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

533

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

535

regmap_raw_read(priv->dsp->regmap, reg_addr, &reg_val,

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

536

sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

538

KUNIT_EXPECT_EQ(test, reg_val, payload_data[i]);

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

562

u32 reg_val;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

597

reg_val = 0;

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

599

regmap_raw_read(priv->dsp->regmap, reg_addr, &reg_val,

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

600

sizeof(reg_val)),

drivers/firmware/cirrus/test/cs_dsp_test_bin.c

602

KUNIT_EXPECT_EQ(test, reg_val, payload_data[i]);

drivers/firmware/cirrus/test/cs_dsp_test_control_parse.c

915

u32 reg_val;

drivers/firmware/cirrus/test/cs_dsp_test_control_parse.c

921

reg_val = 0xf11100;

drivers/firmware/cirrus/test/cs_dsp_test_control_parse.c

924

&reg_val, sizeof(reg_val));

drivers/firmware/cirrus/test/cs_dsp_test_control_parse.c

953

u32 reg_val;

drivers/firmware/cirrus/test/cs_dsp_test_control_parse.c

959

reg_val = 0xf11100;

drivers/firmware/cirrus/test/cs_dsp_test_control_parse.c

962

&reg_val, sizeof(reg_val));

drivers/gpio/gpio-adp5520.c

26

uint8_t reg_val;

drivers/gpio/gpio-adp5520.c

36

adp5520_read(dev->master, ADP5520_GPIO_OUT, &reg_val);

drivers/gpio/gpio-adp5520.c

38

adp5520_read(dev->master, ADP5520_GPIO_IN, &reg_val);

drivers/gpio/gpio-adp5520.c

40

return !!(reg_val & dev->lut[off]);

drivers/gpio/gpio-aspeed-sgpio.c

141

case reg_val:

drivers/gpio/gpio-aspeed-sgpio.c

166

case reg_val:

drivers/gpio/gpio-aspeed-sgpio.c

233

reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;

drivers/gpio/gpio-aspeed-sgpio.c

246

gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, val);

drivers/gpio/gpio-aspeed-sgpio.c

454

if (reg == reg_val) {

drivers/gpio/gpio-aspeed-sgpio.c

463

addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_val);

drivers/gpio/gpio-aspeed-sgpio.c

562

if (reg == reg_val)

drivers/gpio/gpio-aspeed.c

1044

if (reg == reg_val)

drivers/gpio/gpio-aspeed.c

1054

if (reg == reg_val)

drivers/gpio/gpio-aspeed.c

1172

if (reg == reg_val)

drivers/gpio/gpio-aspeed.c

257

case reg_val:

drivers/gpio/gpio-aspeed.c

290

case reg_val:

drivers/gpio/gpio-aspeed.c

410

return gpio->config->llops->reg_bit_get(gpio, offset, reg_val);

drivers/gpio/gpio-aspeed.c

418

gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val);

drivers/gpio/gpio-aspeed.c

420

gpio->config->llops->reg_bit_get(gpio, offset, reg_val);

drivers/gpio/gpio-madera.c

100

MADERA_GP1_LVL_MASK, reg_val);

drivers/gpio/gpio-madera.c

76

unsigned int reg_val = value ? MADERA_GP1_LVL : 0;

drivers/gpio/gpio-madera.c

87

MADERA_GP1_LVL_MASK, reg_val);

drivers/gpio/gpio-madera.c

96

unsigned int reg_val = value ? MADERA_GP1_LVL : 0;

drivers/gpio/gpio-max732x.c

193

uint8_t reg_val;

drivers/gpio/gpio-max732x.c

196

ret = max732x_readb(chip, is_group_a(chip, off), &reg_val);

drivers/gpio/gpio-max732x.c

200

return !!(reg_val & (1u << (off & 0x7)));

drivers/gpio/gpio-ml-ioh.c

101

reg_val |= BIT(nr);

drivers/gpio/gpio-ml-ioh.c

103

reg_val &= ~BIT(nr);

drivers/gpio/gpio-ml-ioh.c

105

iowrite32(reg_val, &chip->reg->regs[chip->ch].po);

drivers/gpio/gpio-ml-ioh.c

123

u32 reg_val;

drivers/gpio/gpio-ml-ioh.c

132

reg_val = ioread32(&chip->reg->regs[chip->ch].po);

drivers/gpio/gpio-ml-ioh.c

134

reg_val |= BIT(nr);

drivers/gpio/gpio-ml-ioh.c

136

reg_val &= ~BIT(nr);

drivers/gpio/gpio-ml-ioh.c

137

iowrite32(reg_val, &chip->reg->regs[chip->ch].po);

drivers/gpio/gpio-ml-ioh.c

353

u32 reg_val;

drivers/gpio/gpio-ml-ioh.c

358

reg_val = ioread32(&chip->reg->regs[i].istatus);

drivers/gpio/gpio-ml-ioh.c

360

if (reg_val & BIT(j)) {

drivers/gpio/gpio-ml-ioh.c

363

__func__, j, irq, reg_val);

drivers/gpio/gpio-ml-ioh.c

94

u32 reg_val;

drivers/gpio/gpio-ml-ioh.c

99

reg_val = ioread32(&chip->reg->regs[chip->ch].po);

drivers/gpio/gpio-nct6694.c

100

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

107

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

111

data->reg_val |= BIT(offset);

drivers/gpio/gpio-nct6694.c

112

ret = nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

118

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

123

data->reg_val |= BIT(offset);

drivers/gpio/gpio-nct6694.c

125

data->reg_val &= ~BIT(offset);

drivers/gpio/gpio-nct6694.c

127

return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

136

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

142

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

146

if (BIT(offset) & data->reg_val) {

drivers/gpio/gpio-nct6694.c

148

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

152

return !!(BIT(offset) & data->reg_val);

drivers/gpio/gpio-nct6694.c

156

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

160

return !!(BIT(offset) & data->reg_val);

drivers/gpio/gpio-nct6694.c

170

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

176

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

181

data->reg_val |= BIT(offset);

drivers/gpio/gpio-nct6694.c

183

data->reg_val &= ~BIT(offset);

drivers/gpio/gpio-nct6694.c

185

return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

195

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

201

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

207

data->reg_val |= BIT(offset);

drivers/gpio/gpio-nct6694.c

210

data->reg_val &= ~BIT(offset);

drivers/gpio/gpio-nct6694.c

216

return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

227

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

233

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

237

*valid_mask = data->reg_val;

drivers/gpio/gpio-nct6694.c

248

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

255

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

259

status = data->reg_val;

drivers/gpio/gpio-nct6694.c

264

data->reg_val = BIT(bit);

drivers/gpio/gpio-nct6694.c

268

nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

279

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

353

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

44

unsigned char reg_val;

drivers/gpio/gpio-nct6694.c

59

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

65

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

69

return !(BIT(offset) & data->reg_val);

drivers/gpio/gpio-nct6694.c

78

.len = cpu_to_le16(sizeof(data->reg_val))

drivers/gpio/gpio-nct6694.c

84

ret = nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-nct6694.c

88

data->reg_val &= ~BIT(offset);

drivers/gpio/gpio-nct6694.c

90

return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val);

drivers/gpio/gpio-pca953x.c

653

u32 reg_val;

drivers/gpio/gpio-pca953x.c

657

ret = regmap_read(chip->regmap, inreg, &reg_val);

drivers/gpio/gpio-pca953x.c

661

return !!(reg_val & bit);

drivers/gpio/gpio-pca953x.c

681

u32 reg_val;

drivers/gpio/gpio-pca953x.c

685

ret = regmap_read(chip->regmap, dirreg, &reg_val);

drivers/gpio/gpio-pca953x.c

690

if (reg_val & bit) {

drivers/gpio/gpio-pca953x.c

706

DECLARE_BITMAP(reg_val, MAX_LINE);

drivers/gpio/gpio-pca953x.c

710

ret = pca953x_read_regs(chip, chip->regs->input, reg_val);

drivers/gpio/gpio-pca953x.c

714

bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);

drivers/gpio/gpio-pca953x.c

722

DECLARE_BITMAP(reg_val, MAX_LINE);

drivers/gpio/gpio-pca953x.c

727

ret = pca953x_read_regs(chip, chip->regs->output, reg_val);

drivers/gpio/gpio-pca953x.c

731

bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);

drivers/gpio/gpio-pca953x.c

733

return pca953x_write_regs(chip, chip->regs->output, reg_val);

drivers/gpio/gpio-pch.c

104

u32 reg_val;

drivers/gpio/gpio-pch.c

109

reg_val = ioread32(&chip->reg->po);

drivers/gpio/gpio-pch.c

111

reg_val |= BIT(nr);

drivers/gpio/gpio-pch.c

113

reg_val &= ~BIT(nr);

drivers/gpio/gpio-pch.c

115

iowrite32(reg_val, &chip->reg->po);

drivers/gpio/gpio-pch.c

133

u32 reg_val;

drivers/gpio/gpio-pch.c

138

reg_val = ioread32(&chip->reg->po);

drivers/gpio/gpio-pch.c

140

reg_val |= BIT(nr);

drivers/gpio/gpio-pch.c

142

reg_val &= ~BIT(nr);

drivers/gpio/gpio-pch.c

143

iowrite32(reg_val, &chip->reg->po);

drivers/gpio/gpio-pch.c

311

unsigned long reg_val = ioread32(&chip->reg->istatus);

drivers/gpio/gpio-pch.c

314

dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);

drivers/gpio/gpio-pch.c

316

reg_val &= BIT(gpio_pins[chip->ioh]) - 1;

drivers/gpio/gpio-pch.c

318

for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])

drivers/gpio/gpio-pch.c

321

return IRQ_RETVAL(reg_val);

drivers/gpio/gpio-realtek-otto.c

175

u32 reg_val;

drivers/gpio/gpio-realtek-otto.c

178

reg_val = ioread32(reg);

drivers/gpio/gpio-realtek-otto.c

179

reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift);

drivers/gpio/gpio-realtek-otto.c

180

reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift;

drivers/gpio/gpio-realtek-otto.c

181

iowrite32(reg_val, reg);

drivers/gpio/gpio-sch.c

73

u8 reg_val;

drivers/gpio/gpio-sch.c

78

reg_val = !!(ioread8(sch->regs + offset) & BIT(bit));

drivers/gpio/gpio-sch.c

80

return reg_val;

drivers/gpio/gpio-sch.c

87

u8 reg_val;

drivers/gpio/gpio-sch.c

92

reg_val = ioread8(sch->regs + offset);

drivers/gpio/gpio-sch.c

95

reg_val |= BIT(bit);

drivers/gpio/gpio-sch.c

97

reg_val &= ~BIT(bit);

drivers/gpio/gpio-sch.c

99

iowrite8(reg_val, sch->regs + offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

955

unsigned int reg_val;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

965

reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

967

wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;

drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c

30

uint32_t reg_index, uint32_t reg_val,

drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c

38

if ((val & mask) == reg_val)

drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h

44

uint32_t reg_val, uint32_t mask);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

590

int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

605

if (val != reg_val)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

608

if ((val & mask) == reg_val)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

617

reg_index, mask, val, reg_val);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

623

uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

634

if ((val & mask) == reg_val)

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

738

uint32_t reg_status = 0, reg_val = 0;

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

743

reg_val |= (cmd << 16);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

744

WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

599

uint32_t reg_status = 0, reg_val = 0;

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

604

reg_val |= (cmd << 16);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

605

WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115, reg_val);

drivers/gpu/drm/amd/display/dc/dc_helper.c

144

uint32_t reg_val)

drivers/gpu/drm/amd/display/dc/dc_helper.c

162

cmd_buf->write_values[offload->reg_seq_count] = reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

227

uint32_t reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

243

reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

244

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

drivers/gpu/drm/amd/display/dc/dc_helper.c

245

dm_write_reg(ctx, addr, reg_val);

drivers/gpu/drm/amd/display/dc/dc_helper.c

246

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

250

uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dc/dc_helper.c

265

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

drivers/gpu/drm/amd/display/dc/dc_helper.c

269

return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);

drivers/gpu/drm/amd/display/dc/dc_helper.c

273

dm_write_reg(ctx, addr, reg_val);

drivers/gpu/drm/amd/display/dc/dc_helper.c

274

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

280

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

281

*field_value = get_reg_field_value_ex(reg_val, mask, shift);

drivers/gpu/drm/amd/display/dc/dc_helper.c

282

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

289

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

290

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

291

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

292

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

300

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

301

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

302

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

303

*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);

drivers/gpu/drm/amd/display/dc/dc_helper.c

304

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

313

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

314

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

315

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

316

*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);

drivers/gpu/drm/amd/display/dc/dc_helper.c

317

*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);

drivers/gpu/drm/amd/display/dc/dc_helper.c

318

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

328

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

329

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

330

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

331

*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);

drivers/gpu/drm/amd/display/dc/dc_helper.c

332

*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);

drivers/gpu/drm/amd/display/dc/dc_helper.c

333

*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);

drivers/gpu/drm/amd/display/dc/dc_helper.c

334

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

345

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

346

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

347

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

348

*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);

drivers/gpu/drm/amd/display/dc/dc_helper.c

349

*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);

drivers/gpu/drm/amd/display/dc/dc_helper.c

350

*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);

drivers/gpu/drm/amd/display/dc/dc_helper.c

351

*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);

drivers/gpu/drm/amd/display/dc/dc_helper.c

352

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

364

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

365

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

366

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

367

*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);

drivers/gpu/drm/amd/display/dc/dc_helper.c

368

*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);

drivers/gpu/drm/amd/display/dc/dc_helper.c

369

*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);

drivers/gpu/drm/amd/display/dc/dc_helper.c

370

*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);

drivers/gpu/drm/amd/display/dc/dc_helper.c

371

*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);

drivers/gpu/drm/amd/display/dc/dc_helper.c

372

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

385

uint32_t reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

386

*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

387

*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);

drivers/gpu/drm/amd/display/dc/dc_helper.c

388

*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);

drivers/gpu/drm/amd/display/dc/dc_helper.c

389

*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);

drivers/gpu/drm/amd/display/dc/dc_helper.c

390

*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);

drivers/gpu/drm/amd/display/dc/dc_helper.c

391

*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);

drivers/gpu/drm/amd/display/dc/dc_helper.c

392

*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);

drivers/gpu/drm/amd/display/dc/dc_helper.c

393

*field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);

drivers/gpu/drm/amd/display/dc/dc_helper.c

394

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

433

uint32_t reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

459

reg_val = dm_read_reg(ctx, addr);

drivers/gpu/drm/amd/display/dc/dc_helper.c

461

field_value = get_reg_field_value_ex(reg_val, mask, shift);

drivers/gpu/drm/amd/display/dc/dc_helper.c

538

uint32_t index, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dc/dc_helper.c

549

reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

556

reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);

drivers/gpu/drm/amd/display/dc/dc_helper.c

560

generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val);

drivers/gpu/drm/amd/display/dc/dc_helper.c

563

return reg_val;

drivers/gpu/drm/amd/display/dc/dc_helper.c

568

uint32_t index, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dc/dc_helper.c

579

reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);

drivers/gpu/drm/amd/display/dc/dc_helper.c

586

reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);

drivers/gpu/drm/amd/display/dc/dc_helper.c

590

dm_write_index_reg(ctx, CGS_IND_REG__PCIE, index, reg_val);

drivers/gpu/drm/amd/display/dc/dc_helper.c

593

return reg_val;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

167

uint32_t reg_val;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

179

reg_val = tmds_div == PIXEL_RATE_DIV_BY_4 ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

184

OTG0_TMDS_PIXEL_RATE_DIV, reg_val);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

190

OTG1_TMDS_PIXEL_RATE_DIV, reg_val);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

196

OTG2_TMDS_PIXEL_RATE_DIV, reg_val);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

202

OTG3_TMDS_PIXEL_RATE_DIV, reg_val);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1079

const uint16_t *reg_val)

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1081

if (reg_val) {

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1083

GAMUT_REMAP_C11, reg_val[0],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1084

GAMUT_REMAP_C12, reg_val[1]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1086

GAMUT_REMAP_C13, reg_val[2],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1087

GAMUT_REMAP_C14, reg_val[3]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1089

GAMUT_REMAP_C21, reg_val[4],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1090

GAMUT_REMAP_C22, reg_val[5]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1092

GAMUT_REMAP_C23, reg_val[6],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1093

GAMUT_REMAP_C24, reg_val[7]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1095

GAMUT_REMAP_C31, reg_val[8],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1096

GAMUT_REMAP_C32, reg_val[9]);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1098

GAMUT_REMAP_C33, reg_val[10],

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1099

GAMUT_REMAP_C34, reg_val[11]);

drivers/gpu/drm/amd/display/dc/dm_services.h

120

uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

51

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

53

if (reg_val) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

969

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

971

if (reg_val) {

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

88

uint32_t reg_val;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

94

reg_val = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

95

if (reg_val) {

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

497

uint32_t index, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

535

uint32_t index, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

678

uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

680

straps->audio_stream_number = get_reg_field_value(reg_val,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

683

straps->hdmi_disable = get_reg_field_value(reg_val,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

687

reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

688

straps->dc_pinstraps_audio = get_reg_field_value(reg_val,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

100

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

101

srv->funcs.reg_write(srv->user_ctx, addr, reg_val);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

107

uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

108

*field_value = get_reg_field_value_ex(reg_val, mask, shift);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

76

uint32_t reg_val;

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

84

reg_val = srv->funcs.reg_read(srv->user_ctx, addr);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

85

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

86

srv->funcs.reg_write(srv->user_ctx, addr, reg_val);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

89

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

114

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/bridge/analogix/anx7625.c

115

u8 reg_addr, u8 reg_val)

drivers/gpu/drm/bridge/analogix/anx7625.c

122

ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);

drivers/gpu/drm/bridge/ite-it6505.c

569

unsigned int reg_val)

drivers/gpu/drm/bridge/ite-it6505.c

577

err = regmap_write(it6505->regmap, reg_addr, reg_val);

drivers/gpu/drm/bridge/ite-it6505.c

581

reg_addr, reg_val, err);

drivers/gpu/drm/bridge/lontium-lt8912b.c

392

unsigned int reg_val;

drivers/gpu/drm/bridge/lontium-lt8912b.c

394

ret = regmap_read(lt->regmap[I2C_MAIN], 0xC1, &reg_val);

drivers/gpu/drm/bridge/lontium-lt8912b.c

398

if (reg_val & BIT(7))

drivers/gpu/drm/bridge/lontium-lt9611.c

550

unsigned int reg_val = 0;

drivers/gpu/drm/bridge/lontium-lt9611.c

553

regmap_read(lt9611->regmap, 0x825e, &reg_val);

drivers/gpu/drm/bridge/lontium-lt9611.c

554

connected = (reg_val & (BIT(2) | BIT(0)));

drivers/gpu/drm/bridge/lontium-lt9611uxc.c

359

unsigned int reg_val = 0;

drivers/gpu/drm/bridge/lontium-lt9611uxc.c

366

ret = regmap_read(lt9611uxc->regmap, 0xb023, &reg_val);

drivers/gpu/drm/bridge/lontium-lt9611uxc.c

371

connected = reg_val & BIT(1);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

243

unsigned int reg_val;

drivers/gpu/drm/bridge/ti-sn65dsi86.c

245

ret = regmap_read(pdata->regmap, reg, &reg_val);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

251

*val = (u8)reg_val;

drivers/gpu/drm/gma500/psb_irq.c

383

uint32_t reg_val = 0;

drivers/gpu/drm/gma500/psb_irq.c

387

reg_val = REG_READ(pipeconf_reg);

drivers/gpu/drm/gma500/psb_irq.c

391

if (!(reg_val & PIPEACONF_ENABLE))

drivers/gpu/drm/gma500/psb_irq.c

441

uint32_t reg_val = 0;

drivers/gpu/drm/gma500/psb_irq.c

465

reg_val = REG_READ(pipeconf_reg);

drivers/gpu/drm/gma500/psb_irq.c

467

if (!(reg_val & PIPEACONF_ENABLE)) {

drivers/gpu/drm/i915/display/intel_gmbus.c

323

u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);

drivers/gpu/drm/i915/display/intel_gmbus.c

327

reg_val |= mask_bits;

drivers/gpu/drm/i915/display/intel_gmbus.c

329

reg_val &= ~mask_bits;

drivers/gpu/drm/i915/display/intel_gmbus.c

331

intel_de_write_notrace(display, bus->gpio_reg, reg_val);

drivers/gpu/drm/i915/display/intel_vrr.c

984

u32 reg_val;

drivers/gpu/drm/i915/display/intel_vrr.c

992

reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

993

crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0;

drivers/gpu/drm/i915/display/intel_vrr.c

995

reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

996

crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

233

u32 reg_val = intel_uncore_read(uncore,

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

240

IS_GM45(i915) ? "CTG" : "ELK", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

242

if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0)

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

251

reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

253

if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

256

*base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

258

(reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

268

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

270

drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

272

if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

275

*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

277

switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) {

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

292

MISSING_CASE(reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

301

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

304

drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

306

if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

309

switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

311

MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

330

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

332

drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

334

if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

337

*base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

339

switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

348

MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

357

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

359

drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

361

if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

364

*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

366

switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

381

MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

390

u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

393

drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

395

if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

398

if (!(reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK))

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

401

*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

410

u64 reg_val = intel_uncore_read64(uncore, GEN6_STOLEN_RESERVED);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

412

drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

435

switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

450

MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

457

*base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;

drivers/gpu/drm/i915/gvt/handlers.c

987

u32 reg_val;

drivers/gpu/drm/i915/gvt/handlers.c

990

reg_val = *((u32 *)p_data);

drivers/gpu/drm/i915/gvt/handlers.c

993

vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |

drivers/gpu/drm/i915/gvt/handlers.c

995

vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);

drivers/gpu/drm/i915/i915_hwmon.c

143

u32 reg_val;

drivers/gpu/drm/i915/i915_hwmon.c

153

reg_val = intel_uncore_read(uncore, rgaddr);

drivers/gpu/drm/i915/i915_hwmon.c

155

if (reg_val >= ei->reg_val_prev)

drivers/gpu/drm/i915/i915_hwmon.c

156

ei->accum_energy += reg_val - ei->reg_val_prev;

drivers/gpu/drm/i915/i915_hwmon.c

158

ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;

drivers/gpu/drm/i915/i915_hwmon.c

159

ei->reg_val_prev = reg_val;

drivers/gpu/drm/i915/i915_hwmon.c

332

u32 reg_val;

drivers/gpu/drm/i915/i915_hwmon.c

337

reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_temp);

drivers/gpu/drm/i915/i915_hwmon.c

340

*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;

drivers/gpu/drm/i915/i915_hwmon.c

677

u32 reg_val;

drivers/gpu/drm/i915/i915_hwmon.c

683

reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.fan_speed);

drivers/gpu/drm/i915/i915_hwmon.c

690

rotations = (reg_val - fi->reg_val_prev) / 2;

drivers/gpu/drm/i915/i915_hwmon.c

705

fi->reg_val_prev = reg_val;

drivers/gpu/drm/i915/intel_uncore.h

486

u32 reg_val;

drivers/gpu/drm/i915/intel_uncore.h

489

reg_val = intel_uncore_read(uncore, reg);

drivers/gpu/drm/i915/intel_uncore.h

491

return (reg_val & mask) != expected_val ? -EINVAL : 0;

drivers/gpu/drm/imagination/pvr_fw_startstop.c

23

u64 reg_val =

drivers/gpu/drm/imagination/pvr_fw_startstop.c

33

pvr_cr_write64(pvr_dev, ROGUE_CR_AXI_ACE_LITE_CONFIGURATION, reg_val);

drivers/gpu/drm/imagination/pvr_fw_startstop.c

66

u32 reg_val;

drivers/gpu/drm/imagination/pvr_fw_startstop.c

76

reg_val = (pvr_cr_read32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC) &

drivers/gpu/drm/imagination/pvr_fw_startstop.c

86

reg_val |= ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN;

drivers/gpu/drm/imagination/pvr_fw_startstop.c

89

reg_val |= ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_EN;

drivers/gpu/drm/imagination/pvr_fw_startstop.c

91

pvr_cr_write32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC, reg_val);

drivers/gpu/drm/kmb/kmb_drv.h

100

kmb_write_lcd(dev_p, reg, (reg_val & (~mask)));

drivers/gpu/drm/kmb/kmb_drv.h

90

u32 reg_val = kmb_read_lcd(dev_p, reg);

drivers/gpu/drm/kmb/kmb_drv.h

92

kmb_write_lcd(dev_p, reg, (reg_val | mask));

drivers/gpu/drm/kmb/kmb_drv.h

98

u32 reg_val = kmb_read_lcd(dev_p, reg);

drivers/gpu/drm/kmb/kmb_dsi.h

353

u32 reg_val = kmb_read_mipi(kmb_dsi, reg);

drivers/gpu/drm/kmb/kmb_dsi.h

358

reg_val &= (~mask);

drivers/gpu/drm/kmb/kmb_dsi.h

359

reg_val |= (value << offset);

drivers/gpu/drm/kmb/kmb_dsi.h

360

kmb_write_mipi(kmb_dsi, reg, reg_val);

drivers/gpu/drm/kmb/kmb_dsi.h

366

u32 reg_val = kmb_read_mipi(kmb_dsi, reg);

drivers/gpu/drm/kmb/kmb_dsi.h

368

kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset));

drivers/gpu/drm/kmb/kmb_dsi.h

374

u32 reg_val = kmb_read_mipi(kmb_dsi, reg);

drivers/gpu/drm/kmb/kmb_dsi.h

376

kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset)));

drivers/gpu/drm/mediatek/mtk_dsi.c

1070

u32 reg_val, cmdq_mask, i;

drivers/gpu/drm/mediatek/mtk_dsi.c

1085

reg_val = (msg->tx_len << 16) | (type << 8) | config;

drivers/gpu/drm/mediatek/mtk_dsi.c

1090

reg_val = (type << 8) | config;

drivers/gpu/drm/mediatek/mtk_dsi.c

1098

mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

562

u32 reg_val, new_val;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

565

reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

568

new_val = reg_val | BIT(clk_ctrl_reg->bit_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

570

new_val = reg_val & ~BIT(clk_ctrl_reg->bit_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

574

clk_forced_on = !(reg_val & BIT(clk_ctrl_reg->bit_off));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

102

reg_val = DPU_REG_READ(c, reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

103

reg_val &= ~(0xFF << bit_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

104

reg_val |= (limit) << bit_off;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

105

DPU_REG_WRITE(c, reg_off, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

112

u32 reg_val;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

124

reg_val = DPU_REG_READ(c, reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

125

limit = (reg_val >> bit_off) & 0xFF;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

134

u32 reg_val;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

136

reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

139

reg_val |= BIT(xin_id);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

141

reg_val &= ~BIT(xin_id);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

143

DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

150

u32 reg_val;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

152

reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

154

return (reg_val & BIT(xin_id)) ? true : false;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

161

u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

172

reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

177

reg_val &= ~mask;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

178

reg_val |= (remap_level << reg_shift) & mask;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

183

DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

190

u32 reg_val;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

197

reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

198

reg_val |= BIT(xin_id);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

199

DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

63

u32 reg_val;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

81

reg_val = DPU_REG_READ(c, reg_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

82

reg_val &= ~(0x7 << bit_off);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

83

reg_val |= (value & 0x7) << bit_off;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

84

DPU_REG_WRITE(c, reg_off, reg_val);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

91

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1120

u32 reg_val, data, reg;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1127

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1128

DBG("HDCP_SHA_STATUS=%08x", reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1131

if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) {

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1139

if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE))

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1157

reg_val = ksv_fifo[i] << 16;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1159

reg_val |= HDMI_HDCP_SHA_DATA_DONE;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1162

data = reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1307

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1318

reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1319

reg_val &= ~HDMI_CTRL_ENCRYPTED;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1320

hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1333

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1348

reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1349

reg_val &= ~HDMI_HPD_CTRL_ENABLE;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1350

hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1378

reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1379

reg_val &= ~HDMI_CTRL_ENCRYPTED;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1380

hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1383

reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1384

reg_val |= HDMI_HPD_CTRL_ENABLE;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

1385

hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

199

u32 reg_val, hdcp_int_status;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

203

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

204

hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

210

reg_val |= hdcp_int_status << 1;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

213

reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

214

hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

228

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

230

__func__, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

284

u32 reg_val, failure, nack0;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

288

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

289

failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

290

nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

292

reg_val, failure, nack0);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

309

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

310

reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

311

hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

314

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

315

if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED)

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

327

reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

328

reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

329

hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

333

reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

334

reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

335

hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

338

reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

339

reg_val |= HDMI_DDC_CTRL_SOFT_RESET;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

340

hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

346

reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

347

reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

348

hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

402

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

412

reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

413

reg_val &= ~HDMI_HPD_CTRL_ENABLE;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

414

hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

434

reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

435

reg_val |= HDMI_HPD_CTRL_ENABLE;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

436

hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

45

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

459

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

475

reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

476

reg_val &= ~HDMI_CTRL_ENCRYPTED;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

477

hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

480

reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

481

reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

482

hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

501

reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

502

reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

503

hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

540

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

546

reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

547

reg_val &= ~HDMI_CTRL_ENCRYPTED;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

548

hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

558

u32 reg_val;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

566

reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

567

reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

568

hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

573

reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

574

reg_val |= HDMI_CTRL_ENCRYPTED;

drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c

575

hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);

drivers/gpu/drm/sprd/megacores_pll.c

102

regmap_write(regmap, reg_addr[i], reg_val[i]);

drivers/gpu/drm/sprd/megacores_pll.c

103

DRM_DEBUG("%02x: %02x\n", reg_addr[i], reg_val[i]);

drivers/gpu/drm/sprd/megacores_pll.c

83

u8 reg_val[9] = {0};

drivers/gpu/drm/sprd/megacores_pll.c

91

reg_val[0] = 1 | (1 << 1) | (pll->lpf_sel << 2);

drivers/gpu/drm/sprd/megacores_pll.c

92

reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7);

drivers/gpu/drm/sprd/megacores_pll.c

93

reg_val[2] = pll->nint;

drivers/gpu/drm/sprd/megacores_pll.c

94

reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2);

drivers/gpu/drm/sprd/megacores_pll.c

95

reg_val[4] = pll->kint >> 12;

drivers/gpu/drm/sprd/megacores_pll.c

96

reg_val[5] = pll->kint >> 4;

drivers/gpu/drm/sprd/megacores_pll.c

97

reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);

drivers/gpu/drm/sprd/megacores_pll.c

98

reg_val[7] = 1 << 4;

drivers/gpu/drm/sprd/megacores_pll.c

99

reg_val[8] = pll->det_delay;

drivers/gpu/drm/sprd/sprd_dpu.c

463

u32 reg_val;

drivers/gpu/drm/sprd/sprd_dpu.c

472

reg_val = ctx->vm.hsync_len << 0 |

drivers/gpu/drm/sprd/sprd_dpu.c

475

writel(reg_val, ctx->base + REG_DPI_H_TIMING);

drivers/gpu/drm/sprd/sprd_dpu.c

477

reg_val = ctx->vm.vsync_len << 0 |

drivers/gpu/drm/sprd/sprd_dpu.c

480

writel(reg_val, ctx->base + REG_DPI_V_TIMING);

drivers/gpu/drm/sprd/sprd_dpu.c

751

u32 reg_val, int_mask = 0;

drivers/gpu/drm/sprd/sprd_dpu.c

753

reg_val = readl(ctx->base + REG_DPU_INT_STS);

drivers/gpu/drm/sprd/sprd_dpu.c

756

if (reg_val & BIT_DPU_INT_ERR) {

drivers/gpu/drm/sprd/sprd_dpu.c

762

if (reg_val & BIT_DPU_INT_UPDATE_DONE) {

drivers/gpu/drm/sprd/sprd_dpu.c

768

if (reg_val & BIT_DPU_INT_DONE) {

drivers/gpu/drm/sprd/sprd_dpu.c

773

if (reg_val & BIT_DPU_INT_VSYNC)

drivers/gpu/drm/sprd/sprd_dpu.c

776

writel(reg_val, ctx->base + REG_DPU_INT_CLR);

drivers/gpu/drm/xe/tests/xe_mocs.c

47

u32 reg_val;

drivers/gpu/drm/xe/tests/xe_mocs.c

56

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i >> 1));

drivers/gpu/drm/xe/tests/xe_mocs.c

58

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i >> 1));

drivers/gpu/drm/xe/tests/xe_mocs.c

60

mocs_dbg(gt, "reg_val=0x%x\n", reg_val);

drivers/gpu/drm/xe/tests/xe_mocs.c

63

reg_val >>= 16;

drivers/gpu/drm/xe/tests/xe_mocs.c

67

l3cc = reg_val & 0xffff;

drivers/gpu/drm/xe/tests/xe_mocs.c

83

u32 reg_val;

drivers/gpu/drm/xe/tests/xe_mocs.c

93

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/tests/xe_mocs.c

95

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/tests/xe_mocs.c

98

mocs = reg_val;

drivers/gpu/drm/xe/xe_gt_topology.c

38

u32 reg_val = xe_mmio_read32(&gt->mmio, XELP_EU_ENABLE);

drivers/gpu/drm/xe/xe_gt_topology.c

49

reg_val = ~reg_val & XELP_EU_MASK;

drivers/gpu/drm/xe/xe_gt_topology.c

54

val = reg_val;

drivers/gpu/drm/xe/xe_gt_topology.c

58

for (i = 0; i < fls(reg_val); i++)

drivers/gpu/drm/xe/xe_gt_topology.c

59

if (reg_val & BIT(i))

drivers/gpu/drm/xe/xe_hwmon.c

1005

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));

drivers/gpu/drm/xe/xe_hwmon.c

1008

*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;

drivers/gpu/drm/xe/xe_hwmon.c

1015

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));

drivers/gpu/drm/xe/xe_hwmon.c

1020

*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *

drivers/gpu/drm/xe/xe_hwmon.c

1021

(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *

drivers/gpu/drm/xe/xe_hwmon.c

1292

u32 reg_val;

drivers/gpu/drm/xe/xe_hwmon.c

1297

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel));

drivers/gpu/drm/xe/xe_hwmon.c

1304

rotations = (reg_val - fi->reg_val_prev) / 2;

drivers/gpu/drm/xe/xe_hwmon.c

1318

fi->reg_val_prev = reg_val;

drivers/gpu/drm/xe/xe_hwmon.c

331

u32 reg_val = 0;

drivers/gpu/drm/xe/xe_hwmon.c

339

xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

343

reg_val = xe_mmio_read32(mmio, rapl_limit);

drivers/gpu/drm/xe/xe_hwmon.c

347

if (!(reg_val & PWR_LIM_EN)) {

drivers/gpu/drm/xe/xe_hwmon.c

350

PWR_ATTR_TO_STR(attr), channel, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

354

reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

355

*value = mul_u32_u32(reg_val, SF_POWER) >> hwmon->scl_shift_power;

drivers/gpu/drm/xe/xe_hwmon.c

377

u32 reg_val, max;

drivers/gpu/drm/xe/xe_hwmon.c

391

xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

393

reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);

drivers/gpu/drm/xe/xe_hwmon.c

394

reg_val = xe_mmio_read32(mmio, rapl_limit);

drivers/gpu/drm/xe/xe_hwmon.c

397

if (reg_val & PWR_LIM_EN) {

drivers/gpu/drm/xe/xe_hwmon.c

419

reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);

drivers/gpu/drm/xe/xe_hwmon.c

429

if (reg_val > max) {

drivers/gpu/drm/xe/xe_hwmon.c

430

reg_val = max;

drivers/gpu/drm/xe/xe_hwmon.c

433

reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

437

reg_val = PWR_LIM_EN | REG_FIELD_PREP(PWR_LIM_VAL, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

440

ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

442

reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

452

u32 reg_val;

drivers/gpu/drm/xe/xe_hwmon.c

456

xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, &reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

465

reg_val = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_hwmon.c

468

reg_val = REG_FIELD_GET(PKG_TDP, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

469

*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/xe/xe_hwmon.c

497

u32 reg_val;

drivers/gpu/drm/xe/xe_hwmon.c

519

reg_val = REG_FIELD_GET64(ENERGY_PKG, pmt_val);

drivers/gpu/drm/xe/xe_hwmon.c

521

reg_val = REG_FIELD_GET64(ENERGY_CARD, pmt_val);

drivers/gpu/drm/xe/xe_hwmon.c

523

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS,

drivers/gpu/drm/xe/xe_hwmon.c

527

ei->accum_energy += reg_val - ei->reg_val_prev;

drivers/gpu/drm/xe/xe_hwmon.c

528

ei->reg_val_prev = reg_val;

drivers/gpu/drm/xe/xe_hwmon.c

540

u32 reg_val, x, y, x_w = 2; /* 2 bits */

drivers/gpu/drm/xe/xe_hwmon.c

552

ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

556

channel, power_attr, reg_val, ret);

drivers/gpu/drm/xe/xe_hwmon.c

557

reg_val = 0;

drivers/gpu/drm/xe/xe_hwmon.c

560

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,

drivers/gpu/drm/xe/xe_hwmon.c

566

x = REG_FIELD_GET(PWR_LIM_TIME_X, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

567

y = REG_FIELD_GET(PWR_LIM_TIME_Y, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

911

u64 reg_val;

drivers/gpu/drm/xe/xe_hwmon.c

913

reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel));

drivers/gpu/drm/xe/xe_hwmon.c

915

*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);

drivers/gpu/drm/xe/xe_hwmon.c

998

u64 reg_val;

drivers/gpu/drm/xe/xe_mert.c

102

u32 reg_val;

drivers/gpu/drm/xe/xe_mert.c

111

reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);

drivers/gpu/drm/xe/xe_mert.c

112

if (!(reg_val & MERT_TLB_INV_DESC_A_VALID)) {

drivers/gpu/drm/xe/xe_mert.c

62

u32 reg_val, vfid, code;

drivers/gpu/drm/xe/xe_mert.c

64

reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT);

drivers/gpu/drm/xe/xe_mert.c

65

if (!reg_val)

drivers/gpu/drm/xe/xe_mert.c

69

vfid = FIELD_GET(CATERR_VFID, reg_val);

drivers/gpu/drm/xe/xe_mert.c

70

code = FIELD_GET(CATERR_CODES, reg_val);

drivers/gpu/drm/xe/xe_mmio.c

203

u32 old, reg_val;

drivers/gpu/drm/xe/xe_mmio.c

206

reg_val = (old & ~clr) | set;

drivers/gpu/drm/xe/xe_mmio.c

207

xe_mmio_write32(mmio, reg, reg_val);

drivers/gpu/drm/xe/xe_mmio.c

215

u32 reg_val;

drivers/gpu/drm/xe/xe_mmio.c

218

reg_val = xe_mmio_read32(mmio, reg);

drivers/gpu/drm/xe/xe_mmio.c

220

return (reg_val & mask) != eval ? -EINVAL : 0;

drivers/gpu/drm/xe/xe_mocs.c

271

u32 reg_val;

drivers/gpu/drm/xe/xe_mocs.c

277

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

279

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

283

!!(reg_val & L3_ESC_MASK),

drivers/gpu/drm/xe/xe_mocs.c

284

REG_FIELD_GET(L3_SCC_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

285

REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

286

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

290

!!(reg_val & L3_UPPER_IDX_ESC_MASK),

drivers/gpu/drm/xe/xe_mocs.c

291

REG_FIELD_GET(L3_UPPER_IDX_SCC_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

292

REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

293

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

301

u32 reg_val;

drivers/gpu/drm/xe/xe_mocs.c

309

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

311

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

315

REG_FIELD_GET(LE_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

316

REG_FIELD_GET(LE_TGT_CACHE_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

317

REG_FIELD_GET(LE_LRUM_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

318

!!(reg_val & LE_AOM_MASK),

drivers/gpu/drm/xe/xe_mocs.c

319

!!(reg_val & LE_RSC_MASK),

drivers/gpu/drm/xe/xe_mocs.c

320

REG_FIELD_GET(LE_SCC_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

321

REG_FIELD_GET(LE_PFM_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

322

!!(reg_val & LE_SCF_MASK),

drivers/gpu/drm/xe/xe_mocs.c

323

REG_FIELD_GET(LE_COS_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

324

REG_FIELD_GET(LE_SSE_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

325

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

376

u32 reg_val;

drivers/gpu/drm/xe/xe_mocs.c

382

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

384

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

388

!!(reg_val & L3_LKUP_MASK),

drivers/gpu/drm/xe/xe_mocs.c

389

!!(reg_val & L3_GLBGO_MASK),

drivers/gpu/drm/xe/xe_mocs.c

390

REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

391

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

395

!!(reg_val & L3_UPPER_LKUP_MASK),

drivers/gpu/drm/xe/xe_mocs.c

396

!!(reg_val & L3_UPPER_GLBGO_MASK),

drivers/gpu/drm/xe/xe_mocs.c

397

REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

398

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

421

u32 reg_val;

drivers/gpu/drm/xe/xe_mocs.c

427

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

429

reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

433

REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

434

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

438

REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

439

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

502

u32 reg_val;

drivers/gpu/drm/xe/xe_mocs.c

509

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

511

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

515

!!(reg_val & IG_PAT),

drivers/gpu/drm/xe/xe_mocs.c

516

REG_FIELD_GET(L4_CACHE_POLICY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

517

reg_val);

drivers/gpu/drm/xe/xe_mocs.c

545

u32 reg_val;

drivers/gpu/drm/xe/xe_mocs.c

552

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

554

reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

558

!!(reg_val & IG_PAT),

drivers/gpu/drm/xe/xe_mocs.c

559

REG_FIELD_GET(XE2_L3_CLOS_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

560

REG_FIELD_GET(L4_CACHE_POLICY_MASK, reg_val),

drivers/gpu/drm/xe/xe_mocs.c

561

reg_val);

drivers/hwmon/aspeed-g6-pwm-tach.c

319

u32 reg_val;

drivers/hwmon/aspeed-g6-pwm-tach.c

326

reg_val = readl(priv->base + TACH_ASPEED_CTRL(channel));

drivers/hwmon/aspeed-g6-pwm-tach.c

327

reg_val = FIELD_GET(TACH_ASPEED_CLK_DIV_T_MASK, reg_val);

drivers/hwmon/aspeed-g6-pwm-tach.c

328

*val = BIT(reg_val << 1);

drivers/hwmon/aspeed-g6-pwm-tach.c

341

u32 reg_val;

drivers/hwmon/aspeed-g6-pwm-tach.c

349

reg_val = readl(priv->base + TACH_ASPEED_CTRL(channel));

drivers/hwmon/aspeed-g6-pwm-tach.c

350

reg_val &= ~TACH_ASPEED_CLK_DIV_T_MASK;

drivers/hwmon/aspeed-g6-pwm-tach.c

351

reg_val |= FIELD_PREP(TACH_ASPEED_CLK_DIV_T_MASK,

drivers/hwmon/aspeed-g6-pwm-tach.c

353

writel(reg_val, priv->base + TACH_ASPEED_CTRL(channel));

drivers/hwmon/chipcap2.c

323

u16 reg_val;

drivers/hwmon/chipcap2.c

326

ret = cc2_read_reg(data, reg, &reg_val);

drivers/hwmon/chipcap2.c

328

*val = cc2_rh_convert(reg_val);

drivers/hwmon/chipcap2.c

421

u16 reg_val;

drivers/hwmon/chipcap2.c

424

ret = cc2_read_reg(data, reg, &reg_val);

drivers/hwmon/chipcap2.c

428

*hyst = cc2_rh_convert(reg_val);

drivers/hwmon/ltc2991.c

120

int reg_val, ret;

drivers/hwmon/ltc2991.c

122

ret = ltc2991_read_reg(st, reg, 2, &reg_val);

drivers/hwmon/ltc2991.c

127

*val = DIV_ROUND_CLOSEST(sign_extend32(reg_val, 14) * 19075,

drivers/hwmon/ltc2991.c

151

int reg_val, ret;

drivers/hwmon/ltc2991.c

153

ret = ltc2991_read_reg(st, reg, 2, &reg_val);

drivers/hwmon/ltc2991.c

158

*val = DIV_ROUND_CLOSEST(sign_extend32(reg_val, 12) * 1000, 16);

drivers/hwmon/ltc2991.c

82

int reg_val, ret, offset = 0;

drivers/hwmon/ltc2991.c

84

ret = ltc2991_read_reg(st, reg, 2, &reg_val);

drivers/hwmon/ltc2991.c

93

*val = DIV_ROUND_CLOSEST(sign_extend32(reg_val, 14) * 30518,

drivers/hwmon/ltc2992.c

420

int reg_val;

drivers/hwmon/ltc2992.c

422

reg_val = ltc2992_read_reg(st, reg, 2);

drivers/hwmon/ltc2992.c

423

if (reg_val < 0)

drivers/hwmon/ltc2992.c

424

return reg_val;

drivers/hwmon/ltc2992.c

426

reg_val = reg_val >> 4;

drivers/hwmon/ltc2992.c

427

*val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);

drivers/hwmon/ltc2992.c

442

int reg_val;

drivers/hwmon/ltc2992.c

450

reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);

drivers/hwmon/ltc2992.c

451

if (reg_val < 0)

drivers/hwmon/ltc2992.c

452

return reg_val;

drivers/hwmon/ltc2992.c

454

*val = !!(reg_val & mask);

drivers/hwmon/ltc2992.c

455

reg_val &= ~mask;

drivers/hwmon/ltc2992.c

457

return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);

drivers/hwmon/ltc2992.c

493

int reg_val;

drivers/hwmon/ltc2992.c

501

reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);

drivers/hwmon/ltc2992.c

502

if (reg_val < 0)

drivers/hwmon/ltc2992.c

503

return reg_val;

drivers/hwmon/ltc2992.c

505

*val = !!(reg_val & mask);

drivers/hwmon/ltc2992.c

506

reg_val &= ~mask;

drivers/hwmon/ltc2992.c

508

return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);

drivers/hwmon/ltc2992.c

547

int reg_val;

drivers/hwmon/ltc2992.c

549

reg_val = ltc2992_read_reg(st, reg, 2);

drivers/hwmon/ltc2992.c

550

if (reg_val < 0)

drivers/hwmon/ltc2992.c

551

return reg_val;

drivers/hwmon/ltc2992.c

553

reg_val = reg_val >> 4;

drivers/hwmon/ltc2992.c

554

*val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);

drivers/hwmon/ltc2992.c

561

u32 reg_val;

drivers/hwmon/ltc2992.c

563

reg_val = DIV_ROUND_CLOSEST(val * st->r_sense_uohm[channel], LTC2992_IADC_NANOV_LSB);

drivers/hwmon/ltc2992.c

564

reg_val = reg_val << 4;

drivers/hwmon/ltc2992.c

566

return ltc2992_write_reg(st, reg, 2, reg_val);

drivers/hwmon/ltc2992.c

571

int reg_val;

drivers/hwmon/ltc2992.c

579

reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);

drivers/hwmon/ltc2992.c

580

if (reg_val < 0)

drivers/hwmon/ltc2992.c

581

return reg_val;

drivers/hwmon/ltc2992.c

583

*val = !!(reg_val & mask);

drivers/hwmon/ltc2992.c

585

reg_val &= ~mask;

drivers/hwmon/ltc2992.c

586

return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);

drivers/hwmon/ltc2992.c

622

int reg_val;

drivers/hwmon/ltc2992.c

624

reg_val = ltc2992_read_reg(st, reg, 3);

drivers/hwmon/ltc2992.c

625

if (reg_val < 0)

drivers/hwmon/ltc2992.c

626

return reg_val;

drivers/hwmon/ltc2992.c

628

*val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,

drivers/hwmon/ltc2992.c

636

u32 reg_val;

drivers/hwmon/ltc2992.c

638

reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,

drivers/hwmon/ltc2992.c

641

return ltc2992_write_reg(st, reg, 3, reg_val);

drivers/hwmon/ltc2992.c

646

int reg_val;

drivers/hwmon/ltc2992.c

654

reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);

drivers/hwmon/ltc2992.c

655

if (reg_val < 0)

drivers/hwmon/ltc2992.c

656

return reg_val;

drivers/hwmon/ltc2992.c

658

*val = !!(reg_val & mask);

drivers/hwmon/ltc2992.c

659

reg_val &= ~mask;

drivers/hwmon/ltc2992.c

661

return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);

drivers/hwmon/ltc4282.c

1172

u32 reg_val, ilm_adjust;

drivers/hwmon/ltc4282.c

1175

ret = regmap_read(st->map, LTC4282_ADC_CTRL, &reg_val);

drivers/hwmon/ltc4282.c

1179

st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val);

drivers/hwmon/ltc4282.c

1181

ret = regmap_read(st->map, LTC4282_CTRL_MSB, &reg_val);

drivers/hwmon/ltc4282.c

1185

*vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val);

drivers/hwmon/ltc4282.c

1187

ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, &reg_val);

drivers/hwmon/ltc4282.c

1191

ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val);

drivers/hwmon/ltc4282.c

1391

int reg_val;

drivers/hwmon/ltc4282.c

1395

reg_val = 0;

drivers/hwmon/ltc4282.c

1398

reg_val = 1;

drivers/hwmon/ltc4282.c

1401

reg_val = 2;

drivers/hwmon/ltc4282.c

1404

reg_val = 3;

drivers/hwmon/ltc4282.c

1407

reg_val = 4;

drivers/hwmon/ltc4282.c

1410

reg_val = 5;

drivers/hwmon/ltc4282.c

1413

reg_val = 6;

drivers/hwmon/ltc4282.c

1416

reg_val = 7;

drivers/hwmon/ltc4282.c

1426

FIELD_PREP(LTC4282_ILIM_ADJUST_MASK, reg_val));

drivers/hwmon/max31760.c

243

u8 reg_val[2];

drivers/hwmon/max31760.c

259

reg_val[0] = temp >> 8;

drivers/hwmon/max31760.c

260

reg_val[1] = temp & 0xFF;

drivers/hwmon/max31760.c

262

return regmap_bulk_write(state->regmap, reg_temp, reg_val, 2);

drivers/hwmon/mc33xs2410_hwmon.c

65

u16 reg_val;

drivers/hwmon/mc33xs2410_hwmon.c

73

ret = mc33xs2410_read_reg_diag(spi, reg, &reg_val);

drivers/hwmon/mc33xs2410_hwmon.c

78

*val = FIELD_GET(MC33XS2410_TS_TEMP_MASK, reg_val) * 250 - 40000;

drivers/hwmon/mc33xs2410_hwmon.c

82

&reg_val);

drivers/hwmon/mc33xs2410_hwmon.c

86

*val = FIELD_GET(MC33XS2410_OUT_STA_OTW, reg_val);

drivers/hwmon/mc33xs2410_hwmon.c

89

ret = mc33xs2410_read_reg_ctrl(spi, MC33XS2410_TEMP_WT, &reg_val);

drivers/hwmon/mc33xs2410_hwmon.c

94

*val = FIELD_GET(MC33XS2410_TEMP_WT_MASK, reg_val) * 1000 - 40000;

drivers/hwmon/peci/dimmtemp.c

496

u32 reg_val;

drivers/hwmon/peci/dimmtemp.c

501

ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd4, &reg_val);

drivers/hwmon/peci/dimmtemp.c

502

if (ret || !(reg_val & BIT(31)))

drivers/hwmon/peci/dimmtemp.c

505

ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd0, &reg_val);

drivers/hwmon/peci/dimmtemp.c

522

ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),

drivers/hwmon/peci/dimmtemp.c

533

u32 reg_val;

drivers/hwmon/peci/dimmtemp.c

538

ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, &reg_val);

drivers/hwmon/peci/dimmtemp.c

539

if (ret || !(reg_val & BIT(31)))

drivers/hwmon/peci/dimmtemp.c

542

ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, &reg_val);

drivers/hwmon/peci/dimmtemp.c

559

ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),

drivers/hwmon/sy7636a-hwmon.c

25

int ret, reg_val;

drivers/hwmon/sy7636a-hwmon.c

28

SY7636A_REG_TERMISTOR_READOUT, &reg_val);

drivers/hwmon/sy7636a-hwmon.c

32

*temp = reg_val * 1000;

drivers/i2c/busses/i2c-eg20t.c

604

u32 reg_val;

drivers/i2c/busses/i2c-eg20t.c

620

reg_val = ioread32(p + PCH_I2CSR);

drivers/i2c/busses/i2c-eg20t.c

621

if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {

drivers/i2c/busses/i2c-xiic.c

408

u32 reg_val;

drivers/i2c/busses/i2c-xiic.c

444

reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;

drivers/i2c/busses/i2c-xiic.c

445

if (reg_val == 0)

drivers/i2c/busses/i2c-xiic.c

448

xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);

drivers/i2c/busses/i2c-xiic.c

451

xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);

drivers/i2c/busses/i2c-xiic.c

454

reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;

drivers/i2c/busses/i2c-xiic.c

455

xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);

drivers/i2c/busses/i2c-xiic.c

458

reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;

drivers/i2c/busses/i2c-xiic.c

459

xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);

drivers/i2c/busses/i2c-xiic.c

462

reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;

drivers/i2c/busses/i2c-xiic.c

463

xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);

drivers/i2c/busses/i2c-xiic.c

466

reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;

drivers/i2c/busses/i2c-xiic.c

467

xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);

drivers/i2c/busses/i2c-xiic.c

470

reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;

drivers/i2c/busses/i2c-xiic.c

471

xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);

drivers/i3c/master/dw-i3c-master.c

1720

u32 pos, reg_val;

drivers/i3c/master/dw-i3c-master.c

1729

reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));

drivers/i3c/master/dw-i3c-master.c

1732

reg_val &= ~DEV_ADDR_TABLE_STATIC_MASK;

drivers/i3c/master/dw-i3c-master.c

1733

reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV |

drivers/i3c/master/dw-i3c-master.c

1736

reg_val &= ~DEV_ADDR_TABLE_DYNAMIC_MASK;

drivers/i3c/master/dw-i3c-master.c

1737

reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);

drivers/i3c/master/dw-i3c-master.c

1740

writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));

drivers/iio/accel/adxl372.c

470

unsigned int reg_val, scale_factor;

drivers/iio/accel/adxl372.c

482

reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor);

drivers/iio/accel/adxl372.c

485

if (reg_val > 0xFF)

drivers/iio/accel/adxl372.c

486

reg_val = 0xFF;

drivers/iio/accel/adxl372.c

488

ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val);

drivers/iio/accel/adxl380.c

1004

unsigned int reg_val;

drivers/iio/accel/adxl380.c

1008

ret = regmap_read(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, &reg_val);

drivers/iio/accel/adxl380.c

1012

*calibbias = sign_extend32(reg_val, 7);

drivers/iio/accel/adxl380.c

1048

unsigned int reg_val;

drivers/iio/accel/adxl380.c

1050

ret = regmap_read(st->regmap, ADXL380_DIG_EN_REG, &reg_val);

drivers/iio/accel/adxl380.c

1055

FIELD_GET(ADXL380_FIFO_EN_MSK, reg_val));

drivers/iio/accel/adxl380.c

1869

unsigned int reg_val;

drivers/iio/accel/adxl380.c

1874

ret = regmap_read(st->regmap, ADXL380_DEVID_AD_REG, &reg_val);

drivers/iio/accel/adxl380.c

1878

if (reg_val != ADXL380_DEVID_AD_VAL)

drivers/iio/accel/adxl380.c

1879

dev_warn(st->dev, "Unknown chip id %x\n", reg_val);

drivers/iio/accel/adxl380.c

1892

ret = regmap_read(st->regmap, ADXL380_MISC_0_REG, &reg_val);

drivers/iio/accel/adxl380.c

1897

if (reg_val & ADXL380_XL382_MSK)

drivers/iio/accel/adxl380.c

368

unsigned int reg_val;

drivers/iio/accel/adxl380.c

372

reg_val = DIV_ROUND_CLOSEST(us, 1250);

drivers/iio/accel/adxl380.c

373

if (reg_val > ADXL380_TAP_TIME_MAX)

drivers/iio/accel/adxl380.c

374

reg_val = ADXL380_TAP_TIME_MAX;

drivers/iio/accel/adxl380.c

376

ret = regmap_write(st->regmap, reg, reg_val);

drivers/iio/accel/adxl380.c

409

unsigned int reg_val;

drivers/iio/accel/adxl380.c

413

reg_val = DIV_ROUND_CLOSEST(us, 625);

drivers/iio/accel/adxl380.c

419

ret = regmap_write(st->regmap, ADXL380_TAP_DUR_REG, reg_val);

drivers/iio/accel/adxl380.c

656

unsigned int reg_val;

drivers/iio/accel/adxl380.c

660

reg_val = min(DIV_ROUND_CLOSEST(ms * 1000, 500), ADXL380_TIME_MAX);

drivers/iio/accel/adxl380.c

662

put_unaligned_be24(reg_val, &st->transf_buf[0]);

drivers/iio/accel/adxl380.c

749

unsigned int reg_val;

drivers/iio/accel/adxl380.c

753

ret = regmap_read(st->regmap, st->int_map[0], &reg_val);

drivers/iio/accel/adxl380.c

758

*en = FIELD_GET(ADXL380_INT_MAP0_ACT_INT0_MSK, reg_val);

drivers/iio/accel/adxl380.c

760

*en = FIELD_GET(ADXL380_INT_MAP0_INACT_INT0_MSK, reg_val);

drivers/iio/accel/adxl380.c

822

unsigned int reg_val;

drivers/iio/accel/adxl380.c

824

ret = regmap_read(st->regmap, st->int_map[1], &reg_val);

drivers/iio/accel/adxl380.c

829

*en = FIELD_GET(ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK, reg_val);

drivers/iio/accel/adxl380.c

831

*en = FIELD_GET(ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK, reg_val);

drivers/iio/accel/bma180.c

189

u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1));

drivers/iio/accel/bma180.c

194

return i2c_smbus_write_byte_data(data->client, reg, reg_val);

drivers/iio/accel/bma180.c

302

u8 reg_val = mode ? data->part_info->lowpower_val : 0;

drivers/iio/accel/bma180.c

304

data->part_info->power_mask, reg_val);

drivers/iio/accel/bma400_core.c

1387

int ret, reg_val, raw;

drivers/iio/accel/bma400_core.c

1438

&reg_val);

drivers/iio/accel/bma400_core.c

1442

*val = FIELD_GET(BMA400_TAP_CONFIG_SEN_MASK, reg_val);

drivers/iio/accel/bma400_core.c

1446

&reg_val);

drivers/iio/accel/bma400_core.c

1450

raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIET_MASK, reg_val);

drivers/iio/accel/bma400_core.c

1456

&reg_val);

drivers/iio/accel/bma400_core.c

1460

raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIETDT_MASK, reg_val);

drivers/iio/accel/bma400_core.c

311

int ret, reg_val, raw, vals[2];

drivers/iio/accel/bma400_core.c

313

ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, &reg_val);

drivers/iio/accel/bma400_core.c

317

raw = FIELD_GET(BMA400_TAP_CONFIG1_TICSTH_MASK, reg_val);

drivers/iio/accel/mma9553.c

264

u16 reg_val, config;

drivers/iio/accel/mma9553.c

266

reg_val = *p_reg_val;

drivers/iio/accel/mma9553.c

267

if (val == mma9553_get_bits(reg_val, mask))

drivers/iio/accel/mma9553.c

270

reg_val = mma9553_set_bits(reg_val, val, mask);

drivers/iio/accel/mma9553.c

272

reg, reg_val);

drivers/iio/accel/mma9553.c

279

*p_reg_val = reg_val;

drivers/iio/accel/sca3300.c

325

int reg_val = 0;

drivers/iio/accel/sca3300.c

332

ret = sca3300_transfer(sca_data, &reg_val);

drivers/iio/accel/sca3300.c

351

int reg_val;

drivers/iio/accel/sca3300.c

355

ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, &reg_val);

drivers/iio/accel/sca3300.c

360

if (sca_data->chip->avail_modes_table[i] == reg_val)

drivers/iio/accel/stk8ba50.c

273

stk8ba50_scale_table[index].reg_val);

drivers/iio/accel/stk8ba50.c

292

stk8ba50_samp_freq_table[index].reg_val);

drivers/iio/accel/stk8ba50.c

65

u8 reg_val;

drivers/iio/accel/stk8ba50.c

73

u8 reg_val;

drivers/iio/adc/ad4000.c

1001

return ad4000_write_reg(st, reg_val);

drivers/iio/adc/ad4000.c

735

unsigned int reg_val;

drivers/iio/adc/ad4000.c

741

ret = ad4000_read_reg(st, &reg_val);

drivers/iio/adc/ad4000.c

746

reg_val &= ~AD4000_CFG_SPAN_COMP;

drivers/iio/adc/ad4000.c

747

reg_val |= FIELD_PREP(AD4000_CFG_SPAN_COMP, span_comp_en);

drivers/iio/adc/ad4000.c

749

ret = ad4000_write_reg(st, reg_val);

drivers/iio/adc/ad4000.c

993

unsigned int reg_val = AD4000_CONFIG_REG_DEFAULT;

drivers/iio/adc/ad4000.c

996

reg_val |= FIELD_PREP(AD4000_CFG_HIGHZ, 1);

drivers/iio/adc/ad4000.c

999

reg_val |= FIELD_PREP(AD4000_CFG_TURBO, 1);

drivers/iio/adc/ad4062.c

1362

unsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW;

drivers/iio/adc/ad4062.c

1367

FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val));

drivers/iio/adc/ad4062.c

1371

FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val));

drivers/iio/adc/ad4062.c

1377

unsigned int reg_val;

drivers/iio/adc/ad4062.c

1380

ret = regmap_read(st->regmap, AD4062_REG_GP_CONF, &reg_val);

drivers/iio/adc/ad4062.c

1385

reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val);

drivers/iio/adc/ad4062.c

1387

reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val);

drivers/iio/adc/ad4062.c

1389

return reg_val == AD4062_GP_STATIC_HIGH;

drivers/iio/adc/ad4062.c

830

const u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro);

drivers/iio/adc/ad4062.c

834

if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1)

drivers/iio/adc/ad4062.c

837

st->buf.be16 = cpu_to_be16(reg_val);

drivers/iio/adc/ad4170-4.c

2133

unsigned int num_exc_pins, reg_val;

drivers/iio/adc/ad4170-4.c

2165

reg_val = BIT(chan->channel2);

drivers/iio/adc/ad4170-4.c

2166

ret = regmap_write(st->regmap, AD4170_V_BIAS_REG, reg_val);

drivers/iio/adc/ad4695.c

1055

unsigned int reg_val;

drivers/iio/adc/ad4695.c

1117

&reg_val);

drivers/iio/adc/ad4695.c

1121

*val = reg_val;

drivers/iio/adc/ad4695.c

1135

&reg_val);

drivers/iio/adc/ad4695.c

1140

tmp = sign_extend32(reg_val, 15);

drivers/iio/adc/ad4695.c

1277

unsigned int reg_val;

drivers/iio/adc/ad4695.c

1288

reg_val = 0;

drivers/iio/adc/ad4695.c

1290

reg_val = U16_MAX;

drivers/iio/adc/ad4695.c

1292

reg_val = (val * (1 << 16) +

drivers/iio/adc/ad4695.c

1298

reg_val);

drivers/iio/adc/ad4695.c

1305

reg_val = ad4695_get_calibbias(val, val2, osr);

drivers/iio/adc/ad4695.c

1308

reg_val);

drivers/iio/adc/ad4851.c

113

u8 reg_val;

drivers/iio/adc/ad4851.c

607

unsigned int reg_val;

drivers/iio/adc/ad4851.c

613

ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), &reg_val);

drivers/iio/adc/ad4851.c

617

gain = reg_val << 8;

drivers/iio/adc/ad4851.c

619

ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), &reg_val);

drivers/iio/adc/ad4851.c

623

gain |= reg_val;

drivers/iio/adc/ad4851.c

749

scale_table[i].reg_val);

drivers/iio/adc/ad4851.c

779

if (softspan_val == scale_table[i].reg_val)

drivers/iio/adc/adi-axi-adc.c

514

u32 addr, reg_val;

drivers/iio/adc/adi-axi-adc.c

524

axi_adc_raw_read(back, &reg_val);

drivers/iio/adc/adi-axi-adc.c

526

*val = FIELD_GET(ADI_AXI_REG_VALUE_MASK, reg_val);

drivers/iio/adc/max11410.c

459

int ret, reg_val, filter, rate;

drivers/iio/adc/max11410.c

479

ret = max11410_sample(state, &reg_val, chan);

drivers/iio/adc/max11410.c

488

*val = reg_val;

drivers/iio/adc/max11410.c

492

ret = regmap_read(state->regmap, MAX11410_REG_FILTER, &reg_val);

drivers/iio/adc/max11410.c

496

filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);

drivers/iio/adc/max11410.c

497

rate = reg_val & MAX11410_FILTER_RATE_MASK;

drivers/iio/adc/max11410.c

512

int ret, i, reg_val, filter;

drivers/iio/adc/max11410.c

516

ret = regmap_read(st->regmap, MAX11410_REG_FILTER, &reg_val);

drivers/iio/adc/max11410.c

520

filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);

drivers/iio/adc/max11410.c

585

int ret, reg_val, filter;

drivers/iio/adc/max11410.c

589

ret = regmap_read(st->regmap, MAX11410_REG_FILTER, &reg_val);

drivers/iio/adc/max11410.c

593

filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);

drivers/iio/adc/max77541-adc.c

47

unsigned int reg_val;

drivers/iio/adc/max77541-adc.c

56

ret = regmap_read(*regmap, MAX77541_REG_M2_CFG1, &reg_val);

drivers/iio/adc/max77541-adc.c

60

reg_val = FIELD_GET(MAX77541_BITS_MX_CFG1_RNG, reg_val);

drivers/iio/adc/max77541-adc.c

61

switch (reg_val) {

drivers/iio/adc/mt6370-adc.c

135

unsigned int reg_val;

drivers/iio/adc/mt6370-adc.c

145

ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL3, &reg_val);

drivers/iio/adc/mt6370-adc.c

149

reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val);

drivers/iio/adc/mt6370-adc.c

150

switch (reg_val) {

drivers/iio/adc/mt6370-adc.c

168

ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL7, &reg_val);

drivers/iio/adc/mt6370-adc.c

172

reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val);

drivers/iio/adc/mt6370-adc.c

173

switch (reg_val) {

drivers/iio/adc/mt6370-adc.c

70

unsigned int reg_val;

drivers/iio/adc/mt6370-adc.c

76

reg_val = MT6370_ADC_START_MASK |

drivers/iio/adc/mt6370-adc.c

78

ret = regmap_write(priv->regmap, MT6370_REG_CHG_ADC, reg_val);

drivers/iio/adc/mt6370-adc.c

85

MT6370_REG_CHG_ADC, reg_val,

drivers/iio/adc/mt6370-adc.c

86

!(reg_val & MT6370_ADC_START_MASK),

drivers/iio/adc/pac1921.c

528

unsigned int reg_val;

drivers/iio/adc/pac1921.c

534

reg_val = (gain << __ffs(mask)) & mask;

drivers/iio/adc/pac1921.c

535

ret = pac1921_update_cfg_reg(priv, PAC1921_REG_GAIN_CFG, mask, reg_val);

drivers/iio/adc/pac1921.c

611

unsigned int reg_val;

drivers/iio/adc/pac1921.c

624

reg_val = FIELD_PREP(PAC1921_INT_CFG_SMPL_MASK, n_samples);

drivers/iio/adc/pac1921.c

627

PAC1921_INT_CFG_SMPL_MASK, reg_val);

drivers/iio/dac/max22007.c

208

unsigned int reg_val;

drivers/iio/dac/max22007.c

213

reg_val = FIELD_PREP(MAX22007_DAC_DATA_MASK, data);

drivers/iio/dac/max22007.c

215

return regmap_write(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), reg_val);

drivers/iio/dac/max22007.c

221

unsigned int reg_val;

drivers/iio/dac/max22007.c

224

ret = regmap_read(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), &reg_val);

drivers/iio/dac/max22007.c

228

*data = FIELD_GET(MAX22007_DAC_DATA_MASK, reg_val);

drivers/iio/dac/max22007.c

283

unsigned int reg_val;

drivers/iio/dac/max22007.c

287

ret = regmap_read(st->regmap, MAX22007_CHANNEL_MODE_REG, &reg_val);

drivers/iio/dac/max22007.c

291

powerdown = !(reg_val & MAX22007_CH_PWRON_CH_MASK(chan->channel));

drivers/iio/health/afe4403.c

141

unsigned int reg_val;

drivers/iio/health/afe4403.c

145

ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);

drivers/iio/health/afe4403.c

149

if (reg_val >= afe440x_attr->table_size)

drivers/iio/health/afe4403.c

152

vals[0] = afe440x_attr->val_table[reg_val].integer;

drivers/iio/health/afe4403.c

153

vals[1] = afe440x_attr->val_table[reg_val].fract;

drivers/iio/health/afe4404.c

172

unsigned int reg_val;

drivers/iio/health/afe4404.c

176

ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);

drivers/iio/health/afe4404.c

180

if (reg_val >= afe440x_attr->table_size)

drivers/iio/health/afe4404.c

183

vals[0] = afe440x_attr->val_table[reg_val].integer;

drivers/iio/health/afe4404.c

184

vals[1] = afe440x_attr->val_table[reg_val].fract;

drivers/iio/humidity/hdc3020.c

490

u16 reg, reg_val, reg_thresh_rd, reg_clr_rd, reg_thresh_wr, reg_clr_wr;

drivers/iio/humidity/hdc3020.c

527

reg_val = hdc3020_thresh_set_temp(s_val, thresh);

drivers/iio/humidity/hdc3020.c

528

ret = _hdc3020_write_thresh(data, reg, reg_val);

drivers/iio/humidity/hdc3020.c

538

thresh = reg_val;

drivers/iio/humidity/hdc3020.c

560

reg_val = hdc3020_thresh_set_temp(s_clr, clr);

drivers/iio/humidity/hdc3020.c

571

reg_val = hdc3020_thresh_set_hum(s_val, thresh);

drivers/iio/humidity/hdc3020.c

572

ret = _hdc3020_write_thresh(data, reg, reg_val);

drivers/iio/humidity/hdc3020.c

582

thresh = reg_val;

drivers/iio/humidity/hdc3020.c

603

reg_val = hdc3020_thresh_set_hum(s_clr, clr);

drivers/iio/humidity/hdc3020.c

613

return _hdc3020_write_thresh(data, reg, reg_val);

drivers/iio/imu/bmi323/bmi323_core.c

810

int ret, value, reg_val;

drivers/iio/imu/bmi323/bmi323_core.c

841

ret = regmap_read(data->regmap, BMI323_INT_MAP1_REG, &reg_val);

drivers/iio/imu/bmi323/bmi323_core.c

845

return FIELD_GET(BMI323_STEP_CNT_MSK, reg_val) ? 1 : 0;

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

978

unsigned int reg_val, val;

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

989

reg_val = INV_MPU6500_BIT_WOM_INT_EN;

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

992

reg_val = INV_ICM20608_BIT_WOM_INT_EN;

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

996

val = on ? reg_val : 0;

drivers/iio/imu/inv_mpu6050/inv_mpu_core.c

998

return regmap_update_bits(st->map, st->reg->int_enable, reg_val, val);

drivers/iio/imu/smi330/smi330_core.c

345

int ret, reg, reg_val, i;

drivers/iio/imu/smi330/smi330_core.c

352

ret = regmap_read(data->regmap, reg, &reg_val);

drivers/iio/imu/smi330/smi330_core.c

360

reg_val = field_get(attr->mask, reg_val);

drivers/iio/imu/smi330/smi330_core.c

364

if (attr->reg_vals[i] == reg_val) {

drivers/iio/imu/smi330/smi330_core.c

371

if (attr->reg_vals[i] == reg_val) {

drivers/iio/imu/smi330/smi330_core.c

386

int ret, i, reg, reg_val, error;

drivers/iio/imu/smi330/smi330_core.c

396

reg_val = attr->reg_vals[i];

drivers/iio/imu/smi330/smi330_core.c

398

reg_val = attr->reg_vals[i / 2];

drivers/iio/imu/smi330/smi330_core.c

409

reg_val = field_prep(attr->mask, reg_val);

drivers/iio/imu/smi330/smi330_core.c

410

ret = regmap_update_bits(data->regmap, reg, attr->mask, reg_val);

drivers/iio/light/ltrf216a.c

167

u8 reg_val;

drivers/iio/light/ltrf216a.c

177

reg_val = ltrf216a_int_time_reg[i][1];

drivers/iio/light/ltrf216a.c

179

ret = regmap_write(data->regmap, LTRF216A_ALS_MEAS_RES, reg_val);

drivers/iio/light/tsl2772.c

708

u8 *dev_reg, reg_val;

drivers/iio/light/tsl2772.c

790

reg_val = TSL2772_CNTL_PWR_ON | TSL2772_CNTL_ADC_ENBL |

drivers/iio/light/tsl2772.c

793

reg_val |= TSL2772_CNTL_ALS_INT_ENBL;

drivers/iio/light/tsl2772.c

795

reg_val |= TSL2772_CNTL_PROX_INT_ENBL;

drivers/iio/light/tsl2772.c

797

ret = tsl2772_write_control_reg(chip, reg_val);

drivers/iio/light/vl6180.c

472

unsigned int reg_val = 0;

drivers/iio/light/vl6180.c

475

reg_val = period < 2550 ? (DIV_ROUND_CLOSEST(period, 10) - 1) : 254;

drivers/iio/light/vl6180.c

477

return reg_val;

drivers/iio/light/vl6180.c

485

unsigned int reg_val;

drivers/iio/light/vl6180.c

503

reg_val = vl6180_meas_reg_val_from_mhz(val);

drivers/iio/light/vl6180.c

505

VL6180_RANGE_INTER_MEAS_TIME, reg_val);

drivers/iio/light/vl6180.c

509

reg_val = vl6180_meas_reg_val_from_mhz(val);

drivers/iio/light/vl6180.c

511

VL6180_ALS_INTER_MEAS_TIME, reg_val);

drivers/iio/magnetometer/bmc150_magn.c

150

u8 reg_val;

drivers/iio/magnetometer/bmc150_magn.c

277

int ret, reg_val;

drivers/iio/magnetometer/bmc150_magn.c

280

ret = regmap_read(data->regmap, BMC150_MAGN_REG_OPMODE_ODR, &reg_val);

drivers/iio/magnetometer/bmc150_magn.c

283

odr_val = (reg_val & BMC150_MAGN_MASK_ODR) >> BMC150_MAGN_SHIFT_ODR;

drivers/iio/magnetometer/bmc150_magn.c

286

if (bmc150_magn_samp_freq_table[i].reg_val == odr_val) {

drivers/iio/magnetometer/bmc150_magn.c

305

reg_val <<

drivers/iio/magnetometer/bmc150_magn.c

319

int ret, reg_val, max_odr;

drivers/iio/magnetometer/bmc150_magn.c

323

&reg_val);

drivers/iio/magnetometer/bmc150_magn.c

326

rep_xy = BMC150_MAGN_REGVAL_TO_REPXY(reg_val);

drivers/iio/magnetometer/bmc150_magn.c

330

&reg_val);

drivers/iio/magnetometer/bmc150_magn.c

333

rep_z = BMC150_MAGN_REGVAL_TO_REPZ(reg_val);

drivers/iio/pressure/bmp280-core.c

2453

u8 reg_val;

drivers/iio/pressure/bmp280-core.c

2469

reg_val = FIELD_PREP(BMP580_DSP_COMP_MASK, BMP580_DSP_PRESS_TEMP_COMP_EN) |

drivers/iio/pressure/bmp280-core.c

2475

BMP580_DSP_SHDW_IIR_PRESS_EN, reg_val);

drivers/iio/pressure/bmp280-core.c

2482

reg_val = FIELD_PREP(BMP580_OSR_TEMP_MASK, data->oversampling_temp) |

drivers/iio/pressure/bmp280-core.c

2490

reg_val, &aux);

drivers/iio/pressure/bmp280-core.c

2508

reg_val = FIELD_PREP(BMP580_DSP_IIR_PRESS_MASK, data->iir_filter_coeff) |

drivers/iio/pressure/bmp280-core.c

2513

reg_val);

drivers/iio/pressure/dps310.c

261

int reg_val, rc;

drivers/iio/pressure/dps310.c

263

rc = regmap_read(data->regmap, DPS310_PRS_CFG, &reg_val);

drivers/iio/pressure/dps310.c

267

*val = BIT(reg_val & GENMASK(2, 0));

drivers/iio/pressure/dps310.c

274

int reg_val, rc;

drivers/iio/pressure/dps310.c

276

rc = regmap_read(data->regmap, DPS310_TMP_CFG, &reg_val);

drivers/iio/pressure/dps310.c

284

*val = BIT(reg_val & GENMASK(2, 0));

drivers/iio/pressure/dps310.c

357

int reg_val, rc;

drivers/iio/pressure/dps310.c

359

rc = regmap_read(data->regmap, DPS310_PRS_CFG, &reg_val);

drivers/iio/pressure/dps310.c

363

*val = BIT((reg_val & DPS310_PRS_RATE_BITS) >> 4);

drivers/iio/pressure/dps310.c

370

int reg_val, rc;

drivers/iio/pressure/dps310.c

372

rc = regmap_read(data->regmap, DPS310_TMP_CFG, &reg_val);

drivers/iio/pressure/dps310.c

376

*val = BIT((reg_val & DPS310_TMP_RATE_BITS) >> 4);

drivers/iio/pressure/dps310.c

383

int reg_val, rc;

drivers/iio/pressure/dps310.c

385

rc = regmap_read(data->regmap, DPS310_PRS_CFG, &reg_val);

drivers/iio/pressure/dps310.c

389

*val = scale_factors[reg_val & GENMASK(2, 0)];

drivers/iio/pressure/dps310.c

396

int reg_val, rc;

drivers/iio/pressure/dps310.c

398

rc = regmap_read(data->regmap, DPS310_TMP_CFG, &reg_val);

drivers/iio/pressure/dps310.c

402

*val = scale_factors[reg_val & GENMASK(2, 0)];

drivers/iio/proximity/aw96103.c

298

unsigned int reg_val;

drivers/iio/proximity/aw96103.c

302

AW96103_REG_PROXCTRL_CH(chan->channel), &reg_val);

drivers/iio/proximity/aw96103.c

305

*val = FIELD_GET(AW96103_OUTDEB_MASK, reg_val);

drivers/iio/proximity/aw96103.c

313

unsigned int reg_val;

drivers/iio/proximity/aw96103.c

317

AW96103_REG_PROXCTRL_CH(chan->channel), &reg_val);

drivers/iio/proximity/aw96103.c

320

*val = FIELD_GET(AW96103_INDEB_MASK, reg_val);

drivers/iio/proximity/aw96103.c

328

unsigned int reg_val;

drivers/iio/proximity/aw96103.c

332

AW96103_REG_PROXCTRL_CH(chan->channel), &reg_val);

drivers/iio/proximity/aw96103.c

335

*val = FIELD_GET(AW96103_THHYST_MASK, reg_val);

drivers/iio/proximity/aw96103.c

730

u32 reg_val = 0;

drivers/iio/proximity/aw96103.c

741

&reg_val);

drivers/iio/proximity/aw96103.c

752

if (FIELD_GET(AW96103_CHIPID_MASK, reg_val) != AW96103_CHIP_ID)

drivers/iio/proximity/aw96103.c

754

"unexpected chipid, id=0x%08X\n", reg_val);

drivers/iio/resolver/ad2s1210.c

1333

unsigned int reg_val;

drivers/iio/resolver/ad2s1210.c

1335

ret = regmap_read(st->regmap, AD2S1210_REG_FAULT, &reg_val);

drivers/iio/resolver/ad2s1210.c

1339

st->sample.fault = reg_val;

drivers/iio/resolver/ad2s1210.c

460

unsigned int reg_val;

drivers/iio/resolver/ad2s1210.c

483

ret = regmap_read(st->regmap, AD2S1210_REG_FAULT, &reg_val);

drivers/iio/resolver/ad2s1210.c

487

st->sample.fault = reg_val;

drivers/iio/resolver/ad2s1210.c

602

unsigned int reg_val;

drivers/iio/resolver/ad2s1210.c

606

ret = regmap_read(st->regmap, reg, &reg_val);

drivers/iio/resolver/ad2s1210.c

610

*val = reg_val * THRESHOLD_MILLIVOLT_PER_LSB;

drivers/iio/resolver/ad2s1210.c

617

unsigned int reg_val;

drivers/iio/resolver/ad2s1210.c

619

reg_val = val / THRESHOLD_MILLIVOLT_PER_LSB;

drivers/iio/resolver/ad2s1210.c

622

return regmap_write(st->regmap, reg, reg_val);

drivers/iio/resolver/ad2s1210.c

628

unsigned int reg_val;

drivers/iio/resolver/ad2s1210.c

632

ret = regmap_read(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, &reg_val);

drivers/iio/resolver/ad2s1210.c

637

*val2 = reg_val * ad2s1210_lot_threshold_urad_per_lsb[st->resolution];

drivers/iio/resolver/ad2s1210.c

701

unsigned int reg_val, hysteresis;

drivers/iio/resolver/ad2s1210.c

712

ret = regmap_read(st->regmap, AD2S1210_REG_LOT_HIGH_THRD, &reg_val);

drivers/iio/resolver/ad2s1210.c

717

reg_val - hysteresis);

drivers/iio/resolver/ad2s1210.c

722

unsigned int reg_val;

drivers/iio/resolver/ad2s1210.c

727

ret = regmap_read(st->regmap, AD2S1210_REG_EXCIT_FREQ, &reg_val);

drivers/iio/resolver/ad2s1210.c

731

*val = reg_val * st->clkin_hz / (1 << 15);

drivers/iio/temperature/max31856.c

162

u8 reg_val[3];

drivers/iio/temperature/max31856.c

170

ret = max31856_read(data, MAX31856_LTCBH_REG, reg_val, 3);

drivers/iio/temperature/max31856.c

174

*val = get_unaligned_be24(&reg_val[0]) >> 5;

drivers/iio/temperature/max31856.c

176

if (reg_val[0] & 0x80)

drivers/iio/temperature/max31856.c

185

ret = max31856_read(data, MAX31856_CJTO_REG, reg_val, 3);

drivers/iio/temperature/max31856.c

189

offset_cjto = reg_val[0];

drivers/iio/temperature/max31856.c

191

*val = get_unaligned_be16(&reg_val[1]) >> 2;

drivers/iio/temperature/max31856.c

195

if (reg_val[1] & 0x80)

drivers/iio/temperature/max31856.c

203

ret = max31856_read(data, MAX31856_SR_REG, reg_val, 1);

drivers/iio/temperature/max31856.c

207

if (reg_val[0] & (MAX31856_FAULT_OVUV | MAX31856_FAULT_OPEN))

drivers/iio/temperature/max31856.c

315

u8 reg_val;

drivers/iio/temperature/max31856.c

319

ret = max31856_read(data, MAX31856_SR_REG, &reg_val, 1);

drivers/iio/temperature/max31856.c

323

fault = reg_val & faultbit;

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1031

u32 reg_val;

drivers/infiniband/hw/efa/efa_com.c

122

err = read_resp->reg_val;

drivers/infiniband/hw/irdma/ctrl.c

6358

u32 reg_val;

drivers/infiniband/hw/irdma/ctrl.c

6360

reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) |

drivers/infiniband/hw/irdma/ctrl.c

6363

writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);

drivers/infiniband/hw/irdma/i40iw_hw.c

111

u32 reg_val;

drivers/infiniband/hw/irdma/i40iw_hw.c

113

reg_val = FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_INDX, ceq_id) |

drivers/infiniband/hw/irdma/i40iw_hw.c

115

wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val);

drivers/infiniband/hw/irdma/i40iw_hw.c

117

reg_val = FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX, 0x3) |

drivers/infiniband/hw/irdma/i40iw_hw.c

119

wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val);

drivers/infiniband/hw/irdma/i40iw_hw.c

121

reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |

drivers/infiniband/hw/irdma/i40iw_hw.c

126

wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val);

drivers/infiniband/hw/irdma/icrdma_hw.c

100

u32 reg_val;

drivers/infiniband/hw/irdma/icrdma_hw.c

102

reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |

drivers/infiniband/hw/irdma/icrdma_hw.c

106

writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);

drivers/input/keyboard/imx_keypad.c

100

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

104

reg_val = readw(keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

105

reg_val |= (keypad->cols_en_mask & 0xff) << 8;

drivers/input/keyboard/imx_keypad.c

106

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

113

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

114

reg_val &= ~(1 << (8 + col));

drivers/input/keyboard/imx_keypad.c

115

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

127

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

128

matrix_volatile_state[col] = (~reg_val) & keypad->rows_en_mask;

drivers/input/keyboard/imx_keypad.c

135

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

136

reg_val &= 0x00ff;

drivers/input/keyboard/imx_keypad.c

137

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

189

unsigned short reg_val;

drivers/input/keyboard/imx_keypad.c

260

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

261

reg_val |= KBD_STAT_KPKD | KBD_STAT_KDSC;

drivers/input/keyboard/imx_keypad.c

262

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

264

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

265

reg_val |= KBD_STAT_KDIE;

drivers/input/keyboard/imx_keypad.c

266

reg_val &= ~KBD_STAT_KRIE;

drivers/input/keyboard/imx_keypad.c

267

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

278

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

279

reg_val |= KBD_STAT_KPKR | KBD_STAT_KRSS;

drivers/input/keyboard/imx_keypad.c

280

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

282

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

283

reg_val |= KBD_STAT_KRIE;

drivers/input/keyboard/imx_keypad.c

284

reg_val &= ~KBD_STAT_KDIE;

drivers/input/keyboard/imx_keypad.c

285

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

292

unsigned short reg_val;

drivers/input/keyboard/imx_keypad.c

294

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

297

reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE);

drivers/input/keyboard/imx_keypad.c

299

reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD;

drivers/input/keyboard/imx_keypad.c

300

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

316

unsigned short reg_val;

drivers/input/keyboard/imx_keypad.c

322

reg_val = readw(keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

323

reg_val |= keypad->rows_en_mask & 0xff; /* rows */

drivers/input/keyboard/imx_keypad.c

324

reg_val |= (keypad->cols_en_mask & 0xff) << 8; /* cols */

drivers/input/keyboard/imx_keypad.c

325

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

328

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

329

reg_val &= 0x00ff;

drivers/input/keyboard/imx_keypad.c

330

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

339

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

340

reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD |

drivers/input/keyboard/imx_keypad.c

342

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

345

reg_val |= KBD_STAT_KDIE;

drivers/input/keyboard/imx_keypad.c

346

reg_val &= ~KBD_STAT_KRIE;

drivers/input/keyboard/imx_keypad.c

347

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

352

unsigned short reg_val;

drivers/input/keyboard/imx_keypad.c

355

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

356

reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE);

drivers/input/keyboard/imx_keypad.c

357

reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD;

drivers/input/keyboard/imx_keypad.c

358

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

361

reg_val = (keypad->cols_en_mask & 0xff) << 8;

drivers/input/keyboard/imx_keypad.c

362

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

523

unsigned short reg_val = readw(kbd->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

532

if (reg_val & KBD_STAT_KPKD)

drivers/input/keyboard/imx_keypad.c

533

reg_val |= KBD_STAT_KRIE;

drivers/input/keyboard/imx_keypad.c

534

if (reg_val & KBD_STAT_KPKR)

drivers/input/keyboard/imx_keypad.c

535

reg_val |= KBD_STAT_KDIE;

drivers/input/keyboard/imx_keypad.c

536

writew(reg_val, kbd->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

83

unsigned short reg_val;

drivers/input/keyboard/imx_keypad.c

94

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

95

reg_val |= 0xff00;

drivers/input/keyboard/imx_keypad.c

96

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

98

reg_val = readw(keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

99

reg_val &= ~((keypad->cols_en_mask & 0xff) << 8);

drivers/input/misc/atc260x-onkey.c

78

u32 reg_bm, reg_val;

drivers/input/misc/atc260x-onkey.c

86

reg_val = reg_bm | press_time;

drivers/input/misc/atc260x-onkey.c

94

reg_val |= onkey->params->reset_en_bm | reset_time;

drivers/input/misc/atc260x-onkey.c

98

onkey->params->reg_int_ctl, reg_bm, reg_val);

drivers/input/misc/aw86927.c

227

unsigned int reg_val;

drivers/input/misc/aw86927.c

230

err = regmap_read_poll_timeout(haptics->regmap, AW86927_GLBRD5_REG, reg_val,

drivers/input/misc/aw86927.c

231

(FIELD_GET(AW86927_GLBRD5_STATE_MASK, reg_val) ==

drivers/input/misc/aw86927.c

678

unsigned int reg_val;

drivers/input/misc/aw86927.c

681

err = regmap_read(haptics->regmap, AW86927_SYSINT_REG, &reg_val);

drivers/input/misc/aw86927.c

687

if (reg_val & AW86927_SYSINT_BST_SCPI)

drivers/input/misc/aw86927.c

689

if (reg_val & AW86927_SYSINT_BST_OVPI)

drivers/input/misc/aw86927.c

691

if (reg_val & AW86927_SYSINT_UVLI)

drivers/input/misc/aw86927.c

693

if (reg_val & AW86927_SYSINT_OCDI)

drivers/input/misc/aw86927.c

695

if (reg_val & AW86927_SYSINT_OTI)

drivers/input/misc/aw86927.c

698

if (reg_val & AW86927_SYSINT_DONEI)

drivers/input/misc/aw86927.c

700

if (reg_val & AW86927_SYSINT_FF_AFI)

drivers/input/misc/aw86927.c

702

if (reg_val & AW86927_SYSINT_FF_AEI)

drivers/input/mouse/alps.c

1935

u16 reg_val = 0x181;

drivers/input/mouse/alps.c

1942

ret = alps_monitor_mode_write_reg(psmouse, 0x000, reg_val);

drivers/input/mouse/alps.c

2099

int reg_val, ret = -1;

drivers/input/mouse/alps.c

2104

reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x0008);

drivers/input/mouse/alps.c

2105

if (reg_val == -1)

drivers/input/mouse/alps.c

2109

reg_val |= 0x01;

drivers/input/mouse/alps.c

2111

reg_val &= ~0x01;

drivers/input/mouse/alps.c

2113

ret = __alps_command_mode_write_reg(psmouse, reg_val);

drivers/input/mouse/alps.c

2124

int reg_val;

drivers/input/mouse/alps.c

2126

reg_val = alps_command_mode_read_reg(psmouse, 0x0004);

drivers/input/mouse/alps.c

2127

if (reg_val == -1)

drivers/input/mouse/alps.c

2130

reg_val |= 0x06;

drivers/input/mouse/alps.c

2131

if (__alps_command_mode_write_reg(psmouse, reg_val))

drivers/input/mouse/alps.c

2139

int ret = -EIO, reg_val;

drivers/input/mouse/alps.c

2144

reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08);

drivers/input/mouse/alps.c

2145

if (reg_val == -1)

drivers/input/mouse/alps.c

2149

ret = reg_val & 0x80 ? 0 : -ENODEV;

drivers/input/mouse/alps.c

2159

int reg_val;

drivers/input/mouse/alps.c

2202

reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08);

drivers/input/mouse/alps.c

2203

if (reg_val == -1) {

drivers/input/mouse/alps.c

2210

reg_val |= BIT(1);

drivers/input/mouse/alps.c

2211

if (__alps_command_mode_write_reg(psmouse, reg_val))

drivers/input/mouse/alps.c

2225

int reg_val;

drivers/input/mouse/alps.c

2238

reg_val = alps_command_mode_read_reg(psmouse, 0x0006);

drivers/input/mouse/alps.c

2239

if (reg_val == -1)

drivers/input/mouse/alps.c

2241

if (__alps_command_mode_write_reg(psmouse, reg_val | 0x01))

drivers/input/mouse/alps.c

2244

reg_val = alps_command_mode_read_reg(psmouse, 0x0007);

drivers/input/mouse/alps.c

2245

if (reg_val == -1)

drivers/input/mouse/alps.c

2247

if (__alps_command_mode_write_reg(psmouse, reg_val | 0x01))

drivers/input/mouse/alps.c

2335

int reg_val, ret = -1;

drivers/input/mouse/alps.c

2338

reg_val = alps_setup_trackstick_v3(psmouse,

drivers/input/mouse/alps.c

2340

if (reg_val == -EIO)

drivers/input/mouse/alps.c

2352

reg_val = alps_command_mode_read_reg(psmouse, 0xc2c6);

drivers/input/mouse/alps.c

2353

if (reg_val == -1)

drivers/input/mouse/alps.c

2355

if (__alps_command_mode_write_reg(psmouse, reg_val & 0xfd))

drivers/input/mouse/alps.c

2362

reg_val = alps_command_mode_read_reg(psmouse, 0xc2c4);

drivers/input/mouse/alps.c

2363

if (reg_val == -1)

drivers/input/mouse/alps.c

2365

if (__alps_command_mode_write_reg(psmouse, reg_val | 0x02))

drivers/input/mouse/alps.c

2379

int reg_val;

drivers/input/mouse/alps.c

2381

reg_val = alps_command_mode_read_reg(psmouse, 0x0004);

drivers/input/mouse/alps.c

2382

if (reg_val == -1)

drivers/input/mouse/alps.c

2385

reg_val |= 0x02;

drivers/input/mouse/alps.c

2386

if (__alps_command_mode_write_reg(psmouse, reg_val))

drivers/input/mouse/alps.c

2557

int reg_val = 0;

drivers/input/mouse/alps.c

2567

reg_val = alps_command_mode_read_reg(psmouse,

drivers/input/mouse/alps.c

2573

if (reg_val == 0x0C || reg_val == 0x1D)

drivers/input/mouse/alps.c

2671

int reg_val, ret = -1;

drivers/input/mouse/alps.c

2683

reg_val = alps_command_mode_read_reg(psmouse, 0xc2c4);

drivers/input/mouse/alps.c

2684

if (reg_val == -1)

drivers/input/mouse/alps.c

2686

if (__alps_command_mode_write_reg(psmouse, reg_val | 0x02))

drivers/input/mouse/sentelic.c

116

*reg_val = param[2];

drivers/input/mouse/sentelic.c

124

reg_addr, *reg_val, rc);

drivers/input/mouse/sentelic.c

128

static int fsp_reg_write(struct psmouse *psmouse, int reg_addr, int reg_val)

drivers/input/mouse/sentelic.c

157

if ((v = fsp_test_invert_cmd(reg_val)) != reg_val) {

drivers/input/mouse/sentelic.c

160

} else if ((v = fsp_test_swap_cmd(reg_val)) != reg_val) {

drivers/input/mouse/sentelic.c

176

reg_addr, reg_val, rc);

drivers/input/mouse/sentelic.c

201

static int fsp_page_reg_read(struct psmouse *psmouse, int *reg_val)

drivers/input/mouse/sentelic.c

227

*reg_val = param[2];

drivers/input/mouse/sentelic.c

235

*reg_val, rc);

drivers/input/mouse/sentelic.c

239

static int fsp_page_reg_write(struct psmouse *psmouse, int reg_val)

drivers/input/mouse/sentelic.c

256

if ((v = fsp_test_invert_cmd(reg_val)) != reg_val) {

drivers/input/mouse/sentelic.c

258

} else if ((v = fsp_test_swap_cmd(reg_val)) != reg_val) {

drivers/input/mouse/sentelic.c

273

reg_val, rc);

drivers/input/mouse/sentelic.c

37

static unsigned char fsp_test_swap_cmd(unsigned char reg_val)

drivers/input/mouse/sentelic.c

39

switch (reg_val) {

drivers/input/mouse/sentelic.c

46

return (reg_val >> 4) | (reg_val << 4);

drivers/input/mouse/sentelic.c

48

return reg_val; /* swap isn't necessary */

drivers/input/mouse/sentelic.c

56

static unsigned char fsp_test_invert_cmd(unsigned char reg_val)

drivers/input/mouse/sentelic.c

58

switch (reg_val) {

drivers/input/mouse/sentelic.c

65

return ~reg_val;

drivers/input/mouse/sentelic.c

67

return reg_val; /* inversion isn't necessary */

drivers/input/mouse/sentelic.c

71

static int fsp_reg_read(struct psmouse *psmouse, int reg_addr, int *reg_val)

drivers/input/touchscreen/sun4i-ts.c

117

static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val)

drivers/input/touchscreen/sun4i-ts.c

121

if (reg_val & FIFO_DATA_PENDING) {

drivers/input/touchscreen/sun4i-ts.c

140

if (reg_val & TP_UP_PENDING) {

drivers/input/touchscreen/sun4i-ts.c

150

u32 reg_val;

drivers/input/touchscreen/sun4i-ts.c

152

reg_val = readl(ts->base + TP_INT_FIFOS);

drivers/input/touchscreen/sun4i-ts.c

154

if (reg_val & TEMP_DATA_PENDING)

drivers/input/touchscreen/sun4i-ts.c

158

sun4i_ts_irq_handle_input(ts, reg_val);

drivers/input/touchscreen/sun4i-ts.c

160

writel(reg_val, ts->base + TP_INT_FIFOS);

drivers/isdn/hardware/mISDN/hfcsusb.c

67

cpu_to_le16(hw->ctrl_buff[hw->ctrl_out_idx].reg_val);

drivers/isdn/hardware/mISDN/hfcsusb.c

92

buf->reg_val = val;

drivers/isdn/hardware/mISDN/hfcsusb.h

117

__u8 reg_val; /* value to be written (or read) */

drivers/leds/blink/leds-lgm-sso.c

446

u32 reg_val;

drivers/leds/blink/leds-lgm-sso.c

448

regmap_read(priv->mmap, SSO_CPU, &reg_val);

drivers/leds/blink/leds-lgm-sso.c

450

return !!(reg_val & BIT(offset));

drivers/leds/leds-lm3530.c

230

u8 reg_val[LM3530_REG_MAX];

drivers/leds/leds-lm3530.c

266

reg_val[0] = gen_config; /* LM3530_GEN_CONFIG */

drivers/leds/leds-lm3530.c

267

reg_val[1] = als.config; /* LM3530_ALS_CONFIG */

drivers/leds/leds-lm3530.c

268

reg_val[2] = brt_ramp; /* LM3530_BRT_RAMP_RATE */

drivers/leds/leds-lm3530.c

269

reg_val[3] = als.imp_sel; /* LM3530_ALS_IMP_SELECT */

drivers/leds/leds-lm3530.c

270

reg_val[4] = brightness; /* LM3530_BRT_CTRL_REG */

drivers/leds/leds-lm3530.c

271

reg_val[5] = als.zones[0]; /* LM3530_ALS_ZB0_REG */

drivers/leds/leds-lm3530.c

272

reg_val[6] = als.zones[1]; /* LM3530_ALS_ZB1_REG */

drivers/leds/leds-lm3530.c

273

reg_val[7] = als.zones[2]; /* LM3530_ALS_ZB2_REG */

drivers/leds/leds-lm3530.c

274

reg_val[8] = als.zones[3]; /* LM3530_ALS_ZB3_REG */

drivers/leds/leds-lm3530.c

275

reg_val[9] = LM3530_DEF_ZT_0; /* LM3530_ALS_Z0T_REG */

drivers/leds/leds-lm3530.c

276

reg_val[10] = LM3530_DEF_ZT_1; /* LM3530_ALS_Z1T_REG */

drivers/leds/leds-lm3530.c

277

reg_val[11] = LM3530_DEF_ZT_2; /* LM3530_ALS_Z2T_REG */

drivers/leds/leds-lm3530.c

278

reg_val[12] = LM3530_DEF_ZT_3; /* LM3530_ALS_Z3T_REG */

drivers/leds/leds-lm3530.c

279

reg_val[13] = LM3530_DEF_ZT_4; /* LM3530_ALS_Z4T_REG */

drivers/leds/leds-lm3530.c

290

pwm->pwm_set_intensity(reg_val[i],

drivers/leds/leds-lm3530.c

296

lm3530_reg[i], reg_val[i]);

drivers/leds/leds-lm355x.c

161

unsigned int reg_val;

drivers/leds/leds-lm355x.c

167

reg_val = (u32)pdata->pin_tx2 | (u32)pdata->ntc_pin;

drivers/leds/leds-lm355x.c

168

ret = regmap_update_bits(chip->regmap, 0xE0, 0x28, reg_val);

drivers/leds/leds-lm355x.c

171

reg_val = (u32)pdata->pass_mode;

drivers/leds/leds-lm355x.c

172

ret = regmap_update_bits(chip->regmap, 0xA0, 0x04, reg_val);

drivers/leds/leds-lm355x.c

178

reg_val = (u32)pdata->pin_tx2 | (u32)pdata->ntc_pin |

drivers/leds/leds-lm355x.c

180

ret = regmap_update_bits(chip->regmap, 0x0A, 0xC4, reg_val);

drivers/leds/leds-lm355x.c

199

unsigned int reg_val;

drivers/leds/leds-lm355x.c

251

reg_val = 0x00;

drivers/leds/leds-lm355x.c

253

reg_val = 0x01;

drivers/leds/leds-lm355x.c

258

reg_val <<

drivers/leds/leds-lp50xx.c

311

u8 led_offset, reg_val;

drivers/leds/leds-lp50xx.c

317

reg_val = led_chip->bank_brt_reg;

drivers/leds/leds-lp50xx.c

319

reg_val = led_chip->led_brightness0_reg +

drivers/leds/leds-lp50xx.c

322

ret = regmap_write(led->priv->regmap, reg_val, brightness);

drivers/leds/leds-lp50xx.c

331

reg_val = led_chip->bank_mix_reg + i;

drivers/leds/leds-lp50xx.c

334

reg_val = led_chip->mix_out0_reg + led_offset;

drivers/leds/leds-lp50xx.c

337

ret = regmap_write(led->priv->regmap, reg_val,

drivers/leds/leds-wm831x-status.c

248

drvdata->reg_val = wm831x_reg_read(wm831x, drvdata->reg);

drivers/leds/leds-wm831x-status.c

250

if (drvdata->reg_val & WM831X_LED_MODE_MASK)

drivers/leds/leds-wm831x-status.c

259

drvdata->src = drvdata->reg_val;

drivers/leds/leds-wm831x-status.c

26

int reg_val; /* Control register value */

drivers/leds/leds-wm831x-status.c

44

led->reg_val &= ~(WM831X_LED_SRC_MASK | WM831X_LED_MODE_MASK |

drivers/leds/leds-wm831x-status.c

49

led->reg_val |= led->src << WM831X_LED_SRC_SHIFT;

drivers/leds/leds-wm831x-status.c

51

led->reg_val |= 2 << WM831X_LED_MODE_SHIFT;

drivers/leds/leds-wm831x-status.c

52

led->reg_val |= led->blink_time << WM831X_LED_DUR_SHIFT;

drivers/leds/leds-wm831x-status.c

53

led->reg_val |= led->blink_cyc;

drivers/leds/leds-wm831x-status.c

56

led->reg_val |= 1 << WM831X_LED_MODE_SHIFT;

drivers/leds/leds-wm831x-status.c

61

wm831x_reg_write(led->wm831x, led->reg, led->reg_val);

drivers/leds/rgb/leds-lp5812.c

138

static int lp5812_read_tsd_config_status(struct lp5812_chip *chip, u8 *reg_val)

drivers/leds/rgb/leds-lp5812.c

140

return lp5812_read(chip, LP5812_TSD_CONFIG_STATUS, reg_val);

drivers/leds/rgb/leds-lp5812.c

145

u8 reg_val;

drivers/leds/rgb/leds-lp5812.c

152

ret = lp5812_read_tsd_config_status(chip, &reg_val);

drivers/leds/rgb/leds-lp5812.c

156

return reg_val & LP5812_CFG_ERR_STATUS_MASK;

drivers/leds/rgb/leds-lp5812.c

225

u8 reg_val;

drivers/leds/rgb/leds-lp5812.c

239

ret = lp5812_read(chip, reg, &reg_val);

drivers/leds/rgb/leds-lp5812.c

244

reg_val &= ~(LP5812_ENABLE << (led_number % LP5812_NUMBER_LED_IN_REG));

drivers/leds/rgb/leds-lp5812.c

246

reg_val |= (LP5812_ENABLE << (led_number % LP5812_NUMBER_LED_IN_REG));

drivers/leds/rgb/leds-lp5812.c

248

ret = lp5812_write(chip, reg, reg_val);

drivers/leds/rgb/leds-lp5812.c

382

u8 reg_val;

drivers/leds/rgb/leds-lp5812.c

415

ret = lp5812_read(chip, reg, &reg_val);

drivers/leds/rgb/leds-lp5812.c

419

reg_val |= (LP5812_ENABLE << (chip->led_config[i].led_id[j] %

drivers/leds/rgb/leds-lp5812.c

422

ret = lp5812_write(chip, reg, reg_val);

drivers/media/dvb-frontends/af9033.c

33

const struct reg_val *tab, int tab_len)

drivers/media/dvb-frontends/af9033.c

75

const struct reg_val *init;

drivers/media/dvb-frontends/af9033_priv.h

1020

static const struct reg_val tuner_init_it9135_52[] = {

drivers/media/dvb-frontends/af9033_priv.h

1238

static const struct reg_val ofsm_init_it9135_v2[] = {

drivers/media/dvb-frontends/af9033_priv.h

1340

static const struct reg_val tuner_init_it9135_60[] = {

drivers/media/dvb-frontends/af9033_priv.h

1556

static const struct reg_val tuner_init_it9135_61[] = {

drivers/media/dvb-frontends/af9033_priv.h

1772

static const struct reg_val tuner_init_it9135_62[] = {

drivers/media/dvb-frontends/af9033_priv.h

202

static const struct reg_val tuner_init_tua9001[] = {

drivers/media/dvb-frontends/af9033_priv.h

246

static const struct reg_val tuner_init_fc0011[] = {

drivers/media/dvb-frontends/af9033_priv.h

309

static const struct reg_val tuner_init_fc0012[] = {

drivers/media/dvb-frontends/af9033_priv.h

354

static const struct reg_val tuner_init_mxl5007t[] = {

drivers/media/dvb-frontends/af9033_priv.h

391

static const struct reg_val tuner_init_tda18218[] = {

drivers/media/dvb-frontends/af9033_priv.h

427

static const struct reg_val tuner_init_fc2580[] = {

drivers/media/dvb-frontends/af9033_priv.h

467

static const struct reg_val ofsm_init_it9135_v1[] = {

drivers/media/dvb-frontends/af9033_priv.h

582

static const struct reg_val tuner_init_it9135_38[] = {

drivers/media/dvb-frontends/af9033_priv.h

801

static const struct reg_val tuner_init_it9135_51[] = {

drivers/media/dvb-frontends/af9033_priv.h

87

static const struct reg_val ofsm_init[] = {

drivers/media/dvb-frontends/au8522_decoder.c

285

filter_coef[i].reg_val[filter_coef_type]);

drivers/media/dvb-frontends/au8522_decoder.c

407

lpfilter_coef[i].reg_val[0]);

drivers/media/dvb-frontends/au8522_decoder.c

41

u8 reg_val[8];

drivers/media/dvb-frontends/mxl692.c

570

u32 ix, reg_val = 0x1;

drivers/media/dvb-frontends/mxl692.c

596

status = mxl692_memwrite(dev, 0x70000018, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

653

u32 dev_type = MXL_EAGLE_DEVICE_MAX, reg_val = 0x2;

drivers/media/dvb-frontends/mxl692.c

658

status = mxl692_memwrite(dev, 0x80000100, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

680

u32 reg_val;

drivers/media/dvb-frontends/mxl692.c

685

status = mxl692_memread(dev, 0x90000000, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

689

reg_val &= 0x00FFFFFF;

drivers/media/dvb-frontends/mxl692.c

690

reg_val |= (power_supply == MXL_EAGLE_POWER_SUPPLY_SOURCE_SINGLE) ?

drivers/media/dvb-frontends/mxl692.c

693

status = mxl692_memwrite(dev, 0x90000000, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

698

status = mxl692_memread(dev, 0x90000018, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

702

reg_val |= 0x800;

drivers/media/dvb-frontends/mxl692.c

704

status = mxl692_memwrite(dev, 0x90000018, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

716

u32 reg_val, reg_val1;

drivers/media/dvb-frontends/mxl692.c

720

status = mxl692_memread(dev, 0x90000000, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

725

reg_val &= 0xFFFFFFE0;

drivers/media/dvb-frontends/mxl692.c

726

reg_val |= dev_xtal->xtal_cap;

drivers/media/dvb-frontends/mxl692.c

729

reg_val = dev_xtal->clk_out_enable ? (reg_val | 0x0100) : (reg_val & 0xFFFFFEFF);

drivers/media/dvb-frontends/mxl692.c

731

status = mxl692_memwrite(dev, 0x90000000, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

736

reg_val = dev_xtal->clk_out_div_enable ? (reg_val | 0x0200) : (reg_val & 0xFFFFFDFF);

drivers/media/dvb-frontends/mxl692.c

738

status = mxl692_memwrite(dev, 0x90000000, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

743

reg_val = dev_xtal->xtal_sharing_enable ? (reg_val | 0x010400) : (reg_val & 0xFFFEFBFF);

drivers/media/dvb-frontends/mxl692.c

745

status = mxl692_memwrite(dev, 0x90000000, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

771

status = mxl692_memread(dev, 0x9000002c, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

775

reg_val &= 0xC0FFFFFF;

drivers/media/dvb-frontends/mxl692.c

776

reg_val |= 0xA000000;

drivers/media/dvb-frontends/mxl692.c

778

status = mxl692_memwrite(dev, 0x9000002c, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

784

status = mxl692_memread(dev, 0x70000010, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

788

reg_val |= 0x8;

drivers/media/dvb-frontends/mxl692.c

790

status = mxl692_memwrite(dev, 0x70000010, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

794

status = mxl692_memread(dev, 0x70000018, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

798

reg_val |= 0x10;

drivers/media/dvb-frontends/mxl692.c

800

status = mxl692_memwrite(dev, 0x70000018, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

804

status = mxl692_memread(dev, 0x9001014c, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

808

reg_val &= 0xFFFFEFFF;

drivers/media/dvb-frontends/mxl692.c

810

status = mxl692_memwrite(dev, 0x9001014c, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/mxl692.c

814

reg_val |= 0x1000;

drivers/media/dvb-frontends/mxl692.c

816

status = mxl692_memwrite(dev, 0x9001014c, (u8 *)&reg_val, sizeof(u32));

drivers/media/dvb-frontends/tc90522.c

100

struct reg_val set_tsid[] = {

drivers/media/dvb-frontends/tc90522.c

112

struct reg_val rv;

drivers/media/dvb-frontends/tc90522.c

46

reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)

drivers/media/dvb-frontends/tc90522.c

474

static const struct reg_val reset_sat = { 0x03, 0x01 };

drivers/media/dvb-frontends/tc90522.c

475

static const struct reg_val reset_ter = { 0x01, 0x40 };

drivers/media/dvb-frontends/tc90522.c

530

struct reg_val agc_sat[] = {

drivers/media/dvb-frontends/tc90522.c

536

struct reg_val agc_ter[] = {

drivers/media/dvb-frontends/tc90522.c

542

struct reg_val *rv;

drivers/media/dvb-frontends/tc90522.c

562

static const struct reg_val sleep_sat = { 0x17, 0x01 };

drivers/media/dvb-frontends/tc90522.c

563

static const struct reg_val sleep_ter = { 0x03, 0x90 };

drivers/media/dvb-frontends/tc90522.c

589

static const struct reg_val wakeup_sat = { 0x17, 0x00 };

drivers/media/dvb-frontends/tc90522.c

590

static const struct reg_val wakeup_ter = { 0x03, 0x80 };

drivers/media/i2c/imx274.c

1562

u8 reg_val;

drivers/media/i2c/imx274.c

1564

reg_val = ffs(dgain);

drivers/media/i2c/imx274.c

1566

if (reg_val)

drivers/media/i2c/imx274.c

1567

reg_val--;

drivers/media/i2c/imx274.c

1569

reg_val = clamp(reg_val, (u8)0, (u8)3);

drivers/media/i2c/imx274.c

1572

reg_val & IMX274_MASK_LSB_4_BITS);

drivers/media/i2c/lm3560.c

169

unsigned int reg_val;

drivers/media/i2c/lm3560.c

170

rval = regmap_read(flash->regmap, REG_FLAG, &reg_val);

drivers/media/i2c/lm3560.c

173

if (reg_val & FAULT_SHORT_CIRCUIT)

drivers/media/i2c/lm3560.c

175

if (reg_val & FAULT_OVERTEMP)

drivers/media/i2c/lm3560.c

177

if (reg_val & FAULT_TIMEOUT)

drivers/media/i2c/lm3560.c

377

unsigned int reg_val;

drivers/media/i2c/lm3560.c

390

rval = regmap_read(flash->regmap, REG_FLAG, &reg_val);

drivers/media/i2c/lm3646.c

102

unsigned int reg_val;

drivers/media/i2c/lm3646.c

108

rval = regmap_read(flash->regmap, REG_FLAG, &reg_val);

drivers/media/i2c/lm3646.c

113

if (reg_val & FAULT_TIMEOUT)

drivers/media/i2c/lm3646.c

115

if (reg_val & FAULT_SHORT_CIRCUIT)

drivers/media/i2c/lm3646.c

117

if (reg_val & FAULT_UVLO)

drivers/media/i2c/lm3646.c

119

if (reg_val & FAULT_IVFM)

drivers/media/i2c/lm3646.c

121

if (reg_val & FAULT_OCP)

drivers/media/i2c/lm3646.c

123

if (reg_val & FAULT_OVERTEMP)

drivers/media/i2c/lm3646.c

125

if (reg_val & FAULT_NTC_TRIP)

drivers/media/i2c/lm3646.c

127

if (reg_val & FAULT_OVP)

drivers/media/i2c/lm3646.c

136

unsigned int reg_val;

drivers/media/i2c/lm3646.c

155

rval = regmap_read(flash->regmap, REG_ENABLE, &reg_val);

drivers/media/i2c/lm3646.c

156

if (rval < 0 || ((reg_val & MASK_ENABLE) != MODE_SHDN))

drivers/media/i2c/lm3646.c

168

rval = regmap_read(flash->regmap, REG_ENABLE, &reg_val);

drivers/media/i2c/lm3646.c

171

if ((reg_val & MASK_ENABLE) == MODE_FLASH)

drivers/media/i2c/lm3646.c

296

unsigned int reg_val;

drivers/media/i2c/lm3646.c

300

rval = regmap_read(flash->regmap, REG_ENABLE, &reg_val);

drivers/media/i2c/lm3646.c

303

flash->mode_reg = reg_val & 0xfc;

drivers/media/i2c/lm3646.c

334

return regmap_read(flash->regmap, REG_FLAG, &reg_val);

drivers/media/i2c/mt9m111.c

224

unsigned int reg_val;

drivers/media/i2c/mt9m111.c

257

.reg_val = MT9M111_RM_LOW_POWER_RD,

drivers/media/i2c/mt9m111.c

266

.reg_val = MT9M111_RM_FULL_POWER_RD,

drivers/media/i2c/mt9m111.c

275

.reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X |

drivers/media/i2c/mt9m111.c

938

mt9m111->current_mode->reg_val,

drivers/media/i2c/ov7640.c

21

static const struct reg_val regval_init[] = {

drivers/media/i2c/ov7640.c

31

const struct reg_val *rv, int len)

drivers/media/i2c/s5c73m3/s5c73m3-core.c

380

prev_size->width, prev_size->height, prev_size->reg_val);

drivers/media/i2c/s5c73m3/s5c73m3-core.c

382

chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW;

drivers/media/i2c/s5c73m3/s5c73m3-core.c

387

cap_size->width, cap_size->height, cap_size->reg_val);

drivers/media/i2c/s5c73m3/s5c73m3-core.c

388

chg_mode |= cap_size->reg_val;

drivers/media/i2c/s5c73m3/s5c73m3.h

416

u8 reg_val;

drivers/media/pci/pt3/pt3.c

139

struct reg_val rv = { 0x1e, 0x99 };

drivers/media/pci/pt3/pt3.c

217

static const struct reg_val init0_sat[] = {

drivers/media/pci/pt3/pt3.c

221

static const struct reg_val init0_ter[] = {

drivers/media/pci/pt3/pt3.c

225

static const struct reg_val cfg_sat[] = {

drivers/media/pci/pt3/pt3.c

229

static const struct reg_val cfg_ter[] = {

drivers/media/pci/pt3/pt3.c

92

pt3_demod_write(struct pt3_adapter *adap, const struct reg_val *data, int num)

drivers/media/platform/chips-media/wave5/wave5-hw.c

101

reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1010

u32 index, nal_unit_type, reg_val, sub_layer_info;

drivers/media/platform/chips-media/wave5/wave5-hw.c

102

dev_dbg(dev, "%s: queueing failure: 0x%x\n", func, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1023

reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1025

p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1026

p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1031

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1033

nal_unit_type = (reg_val >> 4) & 0x3f;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1036

if (reg_val & 0x04)

drivers/media/platform/chips-media/wave5/wave5-hw.c

1038

else if (reg_val & 0x02)

drivers/media/platform/chips-media/wave5/wave5-hw.c

1040

else if (reg_val & 0x01)

drivers/media/platform/chips-media/wave5/wave5-hw.c

1048

if (reg_val & 0x04)

drivers/media/platform/chips-media/wave5/wave5-hw.c

1050

else if (reg_val & 0x02)

drivers/media/platform/chips-media/wave5/wave5-hw.c

1052

else if (reg_val & 0x01)

drivers/media/platform/chips-media/wave5/wave5-hw.c

1076

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1077

result->dec_pic_width = reg_val >> 16;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1078

result->dec_pic_height = reg_val & 0xffff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1119

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1177

reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1178

if (FIELD_GET(W521_FEATURE_BACKBONE, reg_val)) {

drivers/media/platform/chips-media/wave5/wave5-hw.c

1179

reg_val = ((WAVE5_PROC_AXI_ID << 28) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1187

wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1234

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1304

reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1305

if (FIELD_GET(W521_FEATURE_BACKBONE, reg_val)) {

drivers/media/platform/chips-media/wave5/wave5-hw.c

1306

reg_val = ((WAVE5_PROC_AXI_ID << 28) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1314

wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1555

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1581

reg_val = (open_param->line_buf_int_en << 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1582

vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1702

u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1755

reg_val = p_param->profile |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1759

reg_val |= (p_param->tier << 12) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1765

vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1767

reg_val = (p_param->lossless_enable) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1778

vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1798

reg_val = (p_param->rdo_skip << 2) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1804

vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1816

reg_val = p_open_param->rc_enable |

drivers/media/platform/chips-media/wave5/wave5-hw.c

1822

reg_val |= (p_param->mb_level_rc_enable << 1);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1824

reg_val |= (p_param->cu_level_rc_enable << 1);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1825

vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1890

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1900

reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1902

p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

1903

p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

1941

u32 reg_val = 0, pic_size = 0, mv_col_size, fbc_y_tbl_size, fbc_c_tbl_size;

drivers/media/platform/chips-media/wave5/wave5-hw.c

2084

reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2085

vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2161

u32 reg_val = 0;

drivers/media/platform/chips-media/wave5/wave5-hw.c

2179

reg_val = wave5_vpu_enc_validate_sec_axi(inst);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2180

vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2322

ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, &reg_val, fail_res);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2326

p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

2327

p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2339

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

2349

reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2351

p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

2352

p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2362

reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE);

drivers/media/platform/chips-media/wave5/wave5-hw.c

2363

result->pic_type = reg_val & 0xFFFF;

drivers/media/platform/chips-media/wave5/wave5-hw.c

319

u32 reg_val = 0;

drivers/media/platform/chips-media/wave5/wave5-hw.c

323

reg_val |= BIT(INT_WAVE5_ENC_SET_PARAM);

drivers/media/platform/chips-media/wave5/wave5-hw.c

324

reg_val |= BIT(INT_WAVE5_ENC_PIC);

drivers/media/platform/chips-media/wave5/wave5-hw.c

325

reg_val |= BIT(INT_WAVE5_BSBUF_FULL);

drivers/media/platform/chips-media/wave5/wave5-hw.c

330

reg_val |= BIT(INT_WAVE5_INIT_SEQ);

drivers/media/platform/chips-media/wave5/wave5-hw.c

331

reg_val |= BIT(INT_WAVE5_DEC_PIC);

drivers/media/platform/chips-media/wave5/wave5-hw.c

332

reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);

drivers/media/platform/chips-media/wave5/wave5-hw.c

335

return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

342

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

351

reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME);

drivers/media/platform/chips-media/wave5/wave5-hw.c

352

str = (u8 *)&reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

402

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

409

reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION);

drivers/media/platform/chips-media/wave5/wave5-hw.c

411

*revision = reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

430

u32 i, reg_val, reason_code;

drivers/media/platform/chips-media/wave5/wave5-hw.c

483

reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);

drivers/media/platform/chips-media/wave5/wave5-hw.c

484

if (FIELD_GET(W521_FEATURE_BACKBONE, reg_val)) {

drivers/media/platform/chips-media/wave5/wave5-hw.c

485

reg_val = ((WAVE5_PROC_AXI_ID << 28) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

493

wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

604

u32 reg_val = 0;

drivers/media/platform/chips-media/wave5/wave5-hw.c

608

ret = send_firmware_command(inst, W5_FLUSH_INSTANCE, true, &reg_val, &fail_res);

drivers/media/platform/chips-media/wave5/wave5-hw.c

612

instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

613

report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

639

u32 reg_val, fail_res;

drivers/media/platform/chips-media/wave5/wave5-hw.c

659

ret = send_firmware_command(inst, W5_INIT_SEQ, true, &reg_val, &fail_res);

drivers/media/platform/chips-media/wave5/wave5-hw.c

663

p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

664

p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

674

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

683

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE);

drivers/media/platform/chips-media/wave5/wave5-hw.c

684

info->pic_width = ((reg_val >> 16) & 0xffff);

drivers/media/platform/chips-media/wave5/wave5-hw.c

685

info->pic_height = (reg_val & 0xffff);

drivers/media/platform/chips-media/wave5/wave5-hw.c

688

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT);

drivers/media/platform/chips-media/wave5/wave5-hw.c

689

info->pic_crop_rect.left = (reg_val >> 16) & 0xffff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

690

info->pic_crop_rect.right = reg_val & 0xffff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

691

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM);

drivers/media/platform/chips-media/wave5/wave5-hw.c

692

info->pic_crop_rect.top = (reg_val >> 16) & 0xffff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

693

info->pic_crop_rect.bottom = reg_val & 0xffff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

695

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO);

drivers/media/platform/chips-media/wave5/wave5-hw.c

696

info->luma_bitdepth = reg_val & 0xf;

drivers/media/platform/chips-media/wave5/wave5-hw.c

697

info->chroma_bitdepth = (reg_val >> 4) & 0xf;

drivers/media/platform/chips-media/wave5/wave5-hw.c

699

reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM);

drivers/media/platform/chips-media/wave5/wave5-hw.c

700

profile_compatibility_flag = (reg_val >> 12) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

701

info->profile = (reg_val >> 24) & 0x1f;

drivers/media/platform/chips-media/wave5/wave5-hw.c

717

info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

731

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

743

reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);

drivers/media/platform/chips-media/wave5/wave5-hw.c

745

p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

746

p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/chips-media/wave5/wave5-hw.c

770

u32 reg_val, cbcr_interleave, nv21, pic_size;

drivers/media/platform/chips-media/wave5/wave5-hw.c

856

reg_val = (bwb_flag << 28) |

drivers/media/platform/chips-media/wave5/wave5-hw.c

864

vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

870

reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3);

drivers/media/platform/chips-media/wave5/wave5-hw.c

871

vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

906

reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS);

drivers/media/platform/chips-media/wave5/wave5-hw.c

907

if (!reg_val) {

drivers/media/platform/chips-media/wave5/wave5-hw.c

967

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

97

u32 reg_val;

drivers/media/platform/chips-media/wave5/wave5-hw.c

977

reg_val = wave5_vpu_dec_validate_sec_axi(inst);

drivers/media/platform/chips-media/wave5/wave5-hw.c

978

vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val);

drivers/media/platform/chips-media/wave5/wave5-hw.c

991

ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, &reg_val, fail_res);

drivers/media/platform/chips-media/wave5/wave5-hw.c

995

p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff;

drivers/media/platform/chips-media/wave5/wave5-hw.c

996

p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK);

drivers/media/platform/qcom/iris/iris_vpu3x.c

122

reg_val, reg_val & BIT(0), 200, 2000);

drivers/media/platform/qcom/iris/iris_vpu3x.c

32

u32 reg_val = 0, value, i;

drivers/media/platform/qcom/iris/iris_vpu3x.c

46

reg_val, reg_val & 0x400000, 2000, 20000);

drivers/media/platform/qcom/iris/iris_vpu3x.c

54

reg_val, reg_val & 0x3, 200, 2000);

drivers/media/platform/qcom/iris/iris_vpu3x.c

61

reg_val, !(reg_val & 0x3), 200, 2000);

drivers/media/platform/qcom/iris/iris_vpu3x.c

77

u32 reg_val = 0, value, i;

drivers/media/platform/qcom/iris/iris_vpu3x.c

92

reg_val, reg_val & 0x400000, 2000, 20000);

drivers/media/platform/qcom/venus/core.c

1031

static const struct reg_val sm7280_reg_preset[] = {

drivers/media/platform/qcom/venus/core.c

667

static const struct reg_val msm8916_reg_preset[] = {

drivers/media/platform/qcom/venus/core.c

699

static const struct reg_val msm8996_reg_preset[] = {

drivers/media/platform/qcom/venus/core.c

732

static const struct reg_val msm8998_reg_preset[] = {

drivers/media/platform/qcom/venus/core.c

771

static const struct reg_val sdm660_reg_preset[] = {

drivers/media/platform/qcom/venus/core.c

973

static const struct reg_val sm8250_reg_preset[] = {

drivers/media/platform/qcom/venus/core.h

75

const struct reg_val *reg_tbl;

drivers/media/platform/qcom/venus/hfi_venus.c

370

const struct reg_val *tbl = res->reg_tbl;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

543

u32 reg_val = 0;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

558

reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

560

reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

562

reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

563

rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10, reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

583

u32 reg_val = 0;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

598

reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

600

reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

602

reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

603

reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

604

reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

605

rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12, reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

620

u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

623

reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

627

reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

629

reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

632

reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

639

reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

650

u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

653

reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

657

reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

659

reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

662

reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

669

reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

180

u32 reg_val;

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

183

reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

185

RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

186

reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

189

RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

191

RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

193

RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

201

u32 reg_val;

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

204

reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

206

RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

207

reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

210

RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

212

RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

214

RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

279

u32 reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);

drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c

281

pbuf->params.hist.hist_bins[i] = RKISP1_CIF_ISP_HIST_GET_BIN_V10(reg_val);

drivers/media/tuners/mxl301rf.c

142

static const struct reg_val set_idac[] = {

drivers/media/tuners/mxl301rf.c

155

struct reg_val tune0[] = {

drivers/media/tuners/mxl301rf.c

165

struct reg_val tune1[] = {

drivers/media/tuners/mxl301rf.c

229

static const struct reg_val standby_data[] = {

drivers/media/usb/as102/as10x_cmd.h

288

struct as10x_register_value reg_val;

drivers/media/usb/as102/as10x_cmd.h

299

struct as10x_register_value reg_val;

drivers/media/usb/as102/as10x_cmd.h

315

struct as10x_register_value reg_val;

drivers/media/usb/as102/as10x_cmd.h

341

struct as10x_register_value reg_val;

drivers/media/usb/as102/as10x_cmd_cfg.c

63

*pvalue = le32_to_cpu((__force __le32)prsp->body.context.rsp.reg_val.u.value32);

drivers/media/usb/as102/as10x_cmd_cfg.c

95

pcmd->body.context.req.reg_val.u.value32 = (__force u32)cpu_to_le32(value);

drivers/memory/mtk-smi.c

197

u32 sec_con_val, reg_val;

drivers/memory/mtk-smi.c

211

reg_val = readl(common->smi_ao_base

drivers/memory/mtk-smi.c

213

reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);

drivers/memory/mtk-smi.c

214

reg_val |= sec_con_val;

drivers/memory/mtk-smi.c

215

reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);

drivers/memory/mtk-smi.c

216

writel(reg_val,

drivers/mfd/adp5520.c

106

uint8_t reg_val;

drivers/mfd/adp5520.c

111

ret = __adp5520_read(chip->client, reg, &reg_val);

drivers/mfd/adp5520.c

113

if (!ret && ((reg_val & bit_mask) != bit_mask)) {

drivers/mfd/adp5520.c

114

reg_val |= bit_mask;

drivers/mfd/adp5520.c

115

ret = __adp5520_write(chip->client, reg, reg_val);

drivers/mfd/adp5520.c

126

uint8_t reg_val;

drivers/mfd/adp5520.c

131

ret = __adp5520_read(chip->client, reg, &reg_val);

drivers/mfd/adp5520.c

133

if (!ret && (reg_val & bit_mask)) {

drivers/mfd/adp5520.c

134

reg_val &= ~bit_mask;

drivers/mfd/adp5520.c

135

ret = __adp5520_write(chip->client, reg, reg_val);

drivers/mfd/adp5520.c

178

uint8_t reg_val;

drivers/mfd/adp5520.c

181

ret = __adp5520_read(chip->client, ADP5520_MODE_STATUS, &reg_val);

drivers/mfd/adp5520.c

185

events = reg_val & (ADP5520_OVP_INT | ADP5520_CMPR_INT |

drivers/mfd/adp5520.c

75

uint8_t reg_val;

drivers/mfd/adp5520.c

80

ret = __adp5520_read(client, reg, &reg_val);

drivers/mfd/adp5520.c

83

reg_val |= bit_mask;

drivers/mfd/adp5520.c

84

ret = __adp5520_write(client, reg, reg_val);

drivers/mfd/adp5585.c

537

unsigned int reg_val = 0, i;

drivers/mfd/adp5585.c

589

reg_val = ADP5585_R4_EXTEND_CFG_RESET1;

drivers/mfd/adp5585.c

592

reg_val |= ADP5585_C4_EXTEND_CFG_RESET2;

drivers/mfd/adp5585.c

596

reg_val);

drivers/mfd/adp5585.c

603

ret = regmap_read(adp5585->regmap, ADP5585_FIFO_1 + i, &reg_val);

drivers/mfd/da903x.c

173

uint8_t reg_val;

drivers/mfd/da903x.c

178

ret = __da903x_read(chip->client, reg, &reg_val);

drivers/mfd/da903x.c

182

if ((reg_val & bit_mask) != bit_mask) {

drivers/mfd/da903x.c

183

reg_val |= bit_mask;

drivers/mfd/da903x.c

184

ret = __da903x_write(chip->client, reg, reg_val);

drivers/mfd/da903x.c

195

uint8_t reg_val;

drivers/mfd/da903x.c

200

ret = __da903x_read(chip->client, reg, &reg_val);

drivers/mfd/da903x.c

204

if (reg_val & bit_mask) {

drivers/mfd/da903x.c

205

reg_val &= ~bit_mask;

drivers/mfd/da903x.c

206

ret = __da903x_write(chip->client, reg, reg_val);

drivers/mfd/da903x.c

217

uint8_t reg_val;

drivers/mfd/da903x.c

222

ret = __da903x_read(chip->client, reg, &reg_val);

drivers/mfd/da903x.c

226

if ((reg_val & mask) != val) {

drivers/mfd/da903x.c

227

reg_val = (reg_val & ~mask) | val;

drivers/mfd/da903x.c

228

ret = __da903x_write(chip->client, reg, reg_val);

drivers/mfd/da9052-i2c.c

88

int reg_val, ret;

drivers/mfd/da9052-i2c.c

90

ret = regmap_read(da9052->regmap, DA9052_CONTROL_B_REG, &reg_val);

drivers/mfd/da9052-i2c.c

94

if (!(reg_val & DA9052_CONTROL_B_WRITEMODE)) {

drivers/mfd/da9052-i2c.c

95

reg_val |= DA9052_CONTROL_B_WRITEMODE;

drivers/mfd/da9052-i2c.c

97

reg_val);

drivers/misc/xilinx_sdfec.c

255

u32 reg_val;

drivers/misc/xilinx_sdfec.c

258

reg_val = xsdfec_regread(xsdfec, reg_offset);

drivers/misc/xilinx_sdfec.c

259

*config_value = (reg_val & bit_mask) > 0;

drivers/mmc/host/cqhci-crypto.c

178

cq_host->crypto_capabilities.reg_val =

drivers/mmc/host/cqhci-crypto.c

215

cq_host->crypto_cap_array[cap_idx].reg_val =

drivers/mmc/host/cqhci-crypto.c

39

cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));

drivers/mmc/host/cqhci-crypto.c

43

cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]),

drivers/mmc/host/cqhci-crypto.c

44

slot_offset + i * sizeof(cfg->reg_val[0]));

drivers/mmc/host/cqhci-crypto.c

47

cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]),

drivers/mmc/host/cqhci-crypto.c

48

slot_offset + 17 * sizeof(cfg->reg_val[0]));

drivers/mmc/host/cqhci-crypto.c

50

cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),

drivers/mmc/host/cqhci-crypto.c

51

slot_offset + 16 * sizeof(cfg->reg_val[0]));

drivers/mmc/host/cqhci.h

164

__le32 reg_val;

drivers/mmc/host/cqhci.h

190

__le32 reg_val;

drivers/mmc/host/cqhci.h

203

__le32 reg_val[32];

drivers/mmc/host/omap_hsmmc.c

1107

u32 reg_val = 0;

drivers/mmc/host/omap_hsmmc.c

1126

reg_val = OMAP_HSMMC_READ(host->base, HCTL);

drivers/mmc/host/omap_hsmmc.c

1144

reg_val |= SDVS18;

drivers/mmc/host/omap_hsmmc.c

1146

reg_val |= SDVS30;

drivers/mmc/host/omap_hsmmc.c

1148

OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);

drivers/mmc/host/sdhci-msm.c

1926

caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));

drivers/mmc/host/sdhci-msm.c

1945

cap.reg_val = cpu_to_le32(cqhci_readl(cq_host,

drivers/mmc/host/sdhci-pci-o2micro.c

323

u32 reg_val;

drivers/mmc/host/sdhci-pci-o2micro.c

350

reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);

drivers/mmc/host/sdhci-pci-o2micro.c

351

reg_val &= ~SDHCI_CLOCK_CARD_EN;

drivers/mmc/host/sdhci-pci-o2micro.c

352

sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);

drivers/mmc/host/sdhci-pci-o2micro.c

362

pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);

drivers/mmc/host/sdhci-pci-o2micro.c

363

reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);

drivers/mmc/host/sdhci-pci-o2micro.c

364

reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);

drivers/mmc/host/sdhci-pci-o2micro.c

365

pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);

drivers/mmc/host/sdhci-pci-o2micro.c

374

reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);

drivers/mmc/host/sdhci-pci-o2micro.c

375

reg_val |= SDHCI_CLOCK_CARD_EN;

drivers/mmc/host/sdhci-pci-o2micro.c

376

sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);

drivers/mmc/host/sdhci-pxav3.c

281

u8 reg_val = readb(pxa->sdio3_conf_reg);

drivers/mmc/host/sdhci-pxav3.c

285

reg_val &= ~SDIO3_CONF_CLK_INV;

drivers/mmc/host/sdhci-pxav3.c

286

reg_val |= SDIO3_CONF_SD_FB_CLK;

drivers/mmc/host/sdhci-pxav3.c

288

reg_val &= ~SDIO3_CONF_CLK_INV;

drivers/mmc/host/sdhci-pxav3.c

289

reg_val &= ~SDIO3_CONF_SD_FB_CLK;

drivers/mmc/host/sdhci-pxav3.c

291

reg_val |= SDIO3_CONF_CLK_INV;

drivers/mmc/host/sdhci-pxav3.c

292

reg_val &= ~SDIO3_CONF_SD_FB_CLK;

drivers/mmc/host/sdhci-pxav3.c

294

writeb(reg_val, pxa->sdio3_conf_reg);

drivers/mtd/nand/ecc-mtk.c

306

u16 reg_val;

drivers/mtd/nand/ecc-mtk.c

325

reg_val = ECC_IRQ_EN;

drivers/mtd/nand/ecc-mtk.c

332

reg_val |= ECC_PG_IRQ_SEL;

drivers/mtd/nand/ecc-mtk.c

334

writew(reg_val, ecc->regs +

drivers/mtd/nand/ecc-mtk.c

337

writew(reg_val, ecc->regs +

drivers/mtd/nand/raw/omap_elm.c

106

u32 reg_val;

drivers/mtd/nand/raw/omap_elm.c

124

reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16);

drivers/mtd/nand/raw/omap_elm.c

125

elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val);

drivers/mtd/nand/raw/omap_elm.c

145

u32 reg_val;

drivers/mtd/nand/raw/omap_elm.c

147

reg_val = elm_read_reg(info, ELM_PAGE_CTRL);

drivers/mtd/nand/raw/omap_elm.c

149

reg_val |= BIT(index); /* enable page mode */

drivers/mtd/nand/raw/omap_elm.c

151

reg_val &= ~BIT(index); /* disable page mode */

drivers/mtd/nand/raw/omap_elm.c

153

elm_write_reg(info, ELM_PAGE_CTRL, reg_val);

drivers/mtd/nand/raw/omap_elm.c

254

u32 reg_val;

drivers/mtd/nand/raw/omap_elm.c

264

reg_val = elm_read_reg(info, offset);

drivers/mtd/nand/raw/omap_elm.c

265

reg_val |= ELM_SYNDROME_VALID;

drivers/mtd/nand/raw/omap_elm.c

266

elm_write_reg(info, offset, reg_val);

drivers/mtd/nand/raw/omap_elm.c

287

u32 reg_val;

drivers/mtd/nand/raw/omap_elm.c

294

reg_val = elm_read_reg(info, offset);

drivers/mtd/nand/raw/omap_elm.c

297

if (reg_val & ECC_CORRECTABLE_MASK) {

drivers/mtd/nand/raw/omap_elm.c

302

err_vec[i].error_count = reg_val &

drivers/mtd/nand/raw/omap_elm.c

308

reg_val = elm_read_reg(info, offset);

drivers/mtd/nand/raw/omap_elm.c

309

err_vec[i].error_loc[j] = reg_val &

drivers/mtd/nand/raw/omap_elm.c

341

u32 reg_val;

drivers/mtd/nand/raw/omap_elm.c

344

reg_val = elm_read_reg(info, ELM_IRQSTATUS);

drivers/mtd/nand/raw/omap_elm.c

345

elm_write_reg(info, ELM_IRQSTATUS, reg_val & INTR_STATUS_PAGE_VALID);

drivers/mtd/nand/raw/omap_elm.c

358

reg_val = elm_read_reg(info, ELM_IRQENABLE);

drivers/mtd/nand/raw/omap_elm.c

359

elm_write_reg(info, ELM_IRQENABLE, reg_val & ~INTR_EN_PAGE_MASK);

drivers/mtd/nand/raw/omap_elm.c

366

u32 reg_val;

drivers/mtd/nand/raw/omap_elm.c

369

reg_val = elm_read_reg(info, ELM_IRQSTATUS);

drivers/mtd/nand/raw/omap_elm.c

372

if (reg_val & INTR_STATUS_PAGE_VALID) {

drivers/mtd/nand/raw/omap_elm.c

374

reg_val & INTR_STATUS_PAGE_VALID);

drivers/net/dsa/microchip/ksz8.c

1087

u8 reg_val = 0;

drivers/net/dsa/microchip/ksz8.c

1091

reg_val |= PORT_FORCE_LINK;

drivers/net/dsa/microchip/ksz8.c

1094

reg_val |= PORT_POWER_SAVING;

drivers/net/dsa/microchip/ksz8.c

1097

reg_val |= PORT_PHY_REMOTE_LOOPBACK;

drivers/net/dsa/microchip/ksz8.c

1100

PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);

drivers/net/dsa/microchip/ksz8.c

829

u8 reg_val;

drivers/net/dsa/microchip/ksz8.c

834

ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], &reg_val);

drivers/net/dsa/microchip/ksz8.c

838

if (reg_val & PORT_MDIX_STATUS)

drivers/net/dsa/microchip/ksz8.c

841

ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, &reg_val);

drivers/net/dsa/microchip/ksz8.c

845

if (reg_val & PORT_FORCE_LINK)

drivers/net/dsa/microchip/ksz8.c

848

if (reg_val & PORT_POWER_SAVING)

drivers/net/dsa/microchip/ksz8.c

851

if (reg_val & PORT_PHY_REMOTE_LOOPBACK)

drivers/net/dsa/microchip/ksz_common.c

211

u32 reg_val;

drivers/net/dsa/microchip/ksz_common.c

5144

return array[i].reg_val;

drivers/net/ethernet/adi/adin1110.c

477

int reg, u16 reg_val)

drivers/net/ethernet/adi/adin1110.c

490

val |= FIELD_PREP(ADIN1110_MDIO_DATA, reg_val);

drivers/net/ethernet/allwinner/sun4i-emac.c

105

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

108

reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

109

reg_val &= ~EMAC_MAC_SUPP_100M;

drivers/net/ethernet/allwinner/sun4i-emac.c

111

reg_val |= EMAC_MAC_SUPP_100M;

drivers/net/ethernet/allwinner/sun4i-emac.c

112

writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

118

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

121

reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

122

reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

124

reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

125

writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

250

u32 reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

261

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

262

reg_val &= ~EMAC_RX_CTL_DMA_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

263

writel(reg_val, db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

266

reg_val = readl(db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

267

reg_val |= EMAC_INT_CTL_RX_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

268

writel(reg_val, db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

364

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

367

reg_val = readl(db->membase + EMAC_TX_MODE_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

369

writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,

drivers/net/ethernet/allwinner/sun4i-emac.c

374

reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

375

writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |

drivers/net/ethernet/allwinner/sun4i-emac.c

380

reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

381

reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

382

reg_val |= EMAC_MAC_CTL1_CRC_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

383

reg_val |= EMAC_MAC_CTL1_PAD_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

384

writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

407

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

410

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

413

reg_val |= EMAC_RX_CTL_PASS_ALL_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

415

reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

417

writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |

drivers/net/ethernet/allwinner/sun4i-emac.c

427

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

431

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

432

reg_val |= EMAC_RX_CTL_FLUSH_FIFO;

drivers/net/ethernet/allwinner/sun4i-emac.c

433

writel(reg_val, db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

438

reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

439

reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;

drivers/net/ethernet/allwinner/sun4i-emac.c

440

writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

443

reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

444

reg_val &= ~EMAC_MAC_MCFG_MII_CLKD_MASK;

drivers/net/ethernet/allwinner/sun4i-emac.c

445

reg_val |= EMAC_MAC_MCFG_MII_CLKD_72;

drivers/net/ethernet/allwinner/sun4i-emac.c

446

writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

453

reg_val = readl(db->membase + EMAC_INT_STA_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

454

writel(reg_val, db->membase + EMAC_INT_STA_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

495

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

503

reg_val = readl(db->membase + EMAC_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

504

writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,

drivers/net/ethernet/allwinner/sun4i-emac.c

508

reg_val = readl(db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

509

reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN | EMAC_INT_CTL_RX_EN);

drivers/net/ethernet/allwinner/sun4i-emac.c

510

writel(reg_val, db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

623

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

639

reg_val = readl(db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

640

reg_val |= (EMAC_INT_CTL_TX_EN |

drivers/net/ethernet/allwinner/sun4i-emac.c

643

writel(reg_val, db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

651

reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

653

dev_dbg(db->dev, "receive header: %x\n", reg_val);

drivers/net/ethernet/allwinner/sun4i-emac.c

654

if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {

drivers/net/ethernet/allwinner/sun4i-emac.c

656

reg_val = readl(db->membase + EMAC_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

657

writel(reg_val & ~EMAC_CTL_RX_EN,

drivers/net/ethernet/allwinner/sun4i-emac.c

661

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

662

writel(reg_val | (1 << 3),

drivers/net/ethernet/allwinner/sun4i-emac.c

666

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

667

} while (reg_val & (1 << 3));

drivers/net/ethernet/allwinner/sun4i-emac.c

670

reg_val = readl(db->membase + EMAC_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

671

writel(reg_val | EMAC_CTL_RX_EN,

drivers/net/ethernet/allwinner/sun4i-emac.c

673

reg_val = readl(db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

674

reg_val |= (EMAC_INT_CTL_TX_EN |

drivers/net/ethernet/allwinner/sun4i-emac.c

677

writel(reg_val, db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

735

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

736

reg_val |= EMAC_RX_CTL_DMA_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

737

writel(reg_val, db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

742

reg_val = readl(db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

743

reg_val &= ~EMAC_RX_CTL_DMA_EN;

drivers/net/ethernet/allwinner/sun4i-emac.c

744

writel(reg_val, db->membase + EMAC_RX_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

764

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

798

reg_val = readl(db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

799

reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN | EMAC_INT_CTL_RX_EN);

drivers/net/ethernet/allwinner/sun4i-emac.c

800

writel(reg_val, db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

802

reg_val = readl(db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

803

reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN);

drivers/net/ethernet/allwinner/sun4i-emac.c

804

writel(reg_val, db->membase + EMAC_INT_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

857

unsigned int reg_val;

drivers/net/ethernet/allwinner/sun4i-emac.c

864

reg_val = readl(db->membase + EMAC_INT_STA_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

865

writel(reg_val, db->membase + EMAC_INT_STA_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

868

reg_val = readl(db->membase + EMAC_CTL_REG);

drivers/net/ethernet/allwinner/sun4i-emac.c

869

reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);

drivers/net/ethernet/allwinner/sun4i-emac.c

870

writel(reg_val, db->membase + EMAC_CTL_REG);

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1215

u32 reg_val;

drivers/net/ethernet/amazon/ena/ena_com.c

842

ret = read_resp->reg_val;

drivers/net/ethernet/amd/amd8111e.c

102

unsigned int reg_val;

drivers/net/ethernet/amd/amd8111e.c

105

reg_val = readl(mmio + PHY_ACCESS);

drivers/net/ethernet/amd/amd8111e.c

106

while (reg_val & PHY_CMD_ACTIVE)

drivers/net/ethernet/amd/amd8111e.c

107

reg_val = readl(mmio + PHY_ACCESS);

drivers/net/ethernet/amd/amd8111e.c

112

reg_val = readl(mmio + PHY_ACCESS);

drivers/net/ethernet/amd/amd8111e.c

114

} while (--repeat && (reg_val & PHY_CMD_ACTIVE));

drivers/net/ethernet/amd/amd8111e.c

115

if (reg_val & PHY_RD_ERR)

drivers/net/ethernet/amd/amd8111e.c

118

*val = reg_val & 0xffff;

drivers/net/ethernet/amd/amd8111e.c

132

unsigned int reg_val;

drivers/net/ethernet/amd/amd8111e.c

134

reg_val = readl(mmio + PHY_ACCESS);

drivers/net/ethernet/amd/amd8111e.c

135

while (reg_val & PHY_CMD_ACTIVE)

drivers/net/ethernet/amd/amd8111e.c

136

reg_val = readl(mmio + PHY_ACCESS);

drivers/net/ethernet/amd/amd8111e.c

142

reg_val = readl(mmio + PHY_ACCESS);

drivers/net/ethernet/amd/amd8111e.c

144

} while (--repeat && (reg_val & PHY_CMD_ACTIVE));

drivers/net/ethernet/amd/amd8111e.c

146

if (reg_val & PHY_RD_ERR)

drivers/net/ethernet/amd/amd8111e.c

160

unsigned int reg_val;

drivers/net/ethernet/amd/amd8111e.c

162

amd8111e_read_phy(lp, phy_id, reg_num, &reg_val);

drivers/net/ethernet/amd/amd8111e.c

163

return reg_val;

drivers/net/ethernet/amd/amd8111e.c

425

int i, reg_val;

drivers/net/ethernet/amd/amd8111e.c

440

reg_val = readl(mmio + CTRL1);

drivers/net/ethernet/amd/amd8111e.c

441

reg_val &= ~XMTSP_MASK;

drivers/net/ethernet/amd/amd8111e.c

442

writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);

drivers/net/ethernet/amd/amd8111e.c

500

unsigned int reg_val;

drivers/net/ethernet/amd/amd8111e.c

537

reg_val = readl(mmio + INT0);

drivers/net/ethernet/amd/amd8111e.c

538

writel(reg_val, mmio + INT0);

drivers/net/ethernet/amd/amd8111e.c

571

reg_val = readl(mmio + SRAM_SIZE);

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1452

u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1453

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1456

XGMAC_IOWRITE((_pdata), _reg, reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1478

u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1479

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1482

XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1502

u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1503

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1506

XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1560

u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1561

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1564

XSIR0_IOWRITE((_pdata), _reg, reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1580

u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1581

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1584

XSIR1_IOWRITE((_pdata), _reg, reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1603

u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1604

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1607

XRXTX_IOWRITE((_pdata), _reg, reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1636

u32 reg_val = XP_IOREAD((_pdata), (_reg)); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1637

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1640

XP_IOWRITE((_pdata), (_reg), reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1669

u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1670

SET_BITS(reg_val, \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1673

XI2C_IOWRITE((_pdata), (_reg), reg_val); \

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

1392

unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

1398

reg_val |= (1 << port);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

1406

XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2528

unsigned int i, j, reg, reg_val;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2560

reg_val = 0;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2577

reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2582

XGMAC_IOWRITE(pdata, reg, reg_val);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2584

reg_val = 0;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2589

reg_val = 0;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2591

reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2596

XGMAC_IOWRITE(pdata, reg, reg_val);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2599

reg_val = 0;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2637

unsigned int mask, reg, reg_val;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2666

reg_val = XGMAC_IOREAD(pdata, reg);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2668

reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3));

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2669

reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3));

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

2671

XGMAC_IOWRITE(pdata, reg, reg_val);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

3295

unsigned int reg_val, i;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

3306

reg_val = 0;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

3308

reg_val |= (0x02 << (i << 1));

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

3309

XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

447

unsigned int reg, reg_val;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

458

reg_val = XGMAC_IOREAD(pdata, reg);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

459

XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

460

XGMAC_IOWRITE(pdata, reg, reg_val);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

472

unsigned int reg, reg_val;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

500

reg_val = XGMAC_IOREAD(pdata, reg);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

503

XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

505

XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

507

XGMAC_IOWRITE(pdata, reg, reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

678

u32 reg_val;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

681

reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

684

reg_val |= mcp_attn_ctl_regs[i].bits;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

686

reg_val &= ~mcp_attn_ctl_regs[i].bits;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

688

REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

728

u32 reg_val, mcp_aeu_bits =

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

744

reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

746

if (reg_val & reg_mask)

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

750

reg_val & reg_mask);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

755

reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

756

if (reg_val & mcp_aeu_bits)

drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h

758

reg_val & mcp_aeu_bits);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5037

u16 reg_val;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5042

MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5046

reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5048

reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5053

MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5059

MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5060

reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5062

reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5064

reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5066

reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5070

MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5076

&reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5079

reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5083

reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5089

reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5110

&reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5113

reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5116

reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5121

reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5124

reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5127

reg_val = 0;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5131

MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5140

u16 reg_val;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5145

MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5146

reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5150

reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5153

MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5160

MDIO_SERDES_DIGITAL_MISC1, &reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5162

DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5164

reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5171

reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5174

reg_val |=

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

5180

MDIO_SERDES_DIGITAL_MISC1, reg_val);

drivers/net/ethernet/cadence/macb_ptp.c

395

u32 reg_val;

drivers/net/ethernet/cadence/macb_ptp.c

397

reg_val = macb_readl(bp, NCR);

drivers/net/ethernet/cadence/macb_ptp.c

400

macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE));

drivers/net/ethernet/cadence/macb_ptp.c

402

macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

136

u64 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

145

reg_val =

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

150

reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

153

reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

157

reg_val = reg_val |

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

161

reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

165

reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

169

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

199

u64 reg_val = octeon_read_csr64(oct,

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

201

while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

202

!(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

204

WRITE_ONCE(reg_val, octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

213

WRITE_ONCE(reg_val, READ_ONCE(reg_val) &

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

216

READ_ONCE(reg_val));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

218

WRITE_ONCE(reg_val, octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

220

if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

235

u64 intr_threshold, reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

254

reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

264

reg_val |= vf_num << CN23XX_PKT_INPUT_CTL_VF_NUM_POS;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

265

reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

268

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

284

reg_val =

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

287

reg_val |= CN23XX_PKT_INPUT_CTL_MASK;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

290

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

308

u32 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

325

reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

328

reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

331

reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

334

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

340

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

341

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

344

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

346

reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

352

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

353

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

355

reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

358

octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

461

u32 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

485

reg_val =

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

487

reg_val |= CN23XX_PKT_OUTPUT_CTL_TENB;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

489

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

493

reg_val =

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

495

reg_val |= CN23XX_PKT_OUTPUT_CTL_CENB;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

497

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

621

u64 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

631

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

633

reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

635

oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

643

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

646

if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

647

while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

648

!(reg_val &

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

651

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

661

reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

664

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

666

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

668

if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

675

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

677

reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

679

oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

683

u32 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

686

reg_val = octeon_read_csr(

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

688

reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

690

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

153

u32 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

160

reg_val =

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

163

reg_val &= 0xEFFFFFFFFFFFFFFFL;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

165

reg_val =

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

169

reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

172

reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

175

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

180

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

181

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

184

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

186

reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

191

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

192

reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

194

reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

198

reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

321

u64 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

325

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

327

reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

329

oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

334

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

336

reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

338

oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

342

u32 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

346

reg_val = octeon_read_csr(

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

348

reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

350

oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

620

u64 reg_val;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

626

reg_val = octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(0));

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

628

oct->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

630

oct->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

633

reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

635

rings_per_vf = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

68

u64 reg_val = octeon_read_csr64(oct,

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

70

while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

71

!(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

73

WRITE_ONCE(reg_val, octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

83

WRITE_ONCE(reg_val, READ_ONCE(reg_val) &

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

86

READ_ONCE(reg_val));

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

88

WRITE_ONCE(reg_val, octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

90

if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

524

u64 reg_val = 0ULL;

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

527

reg_val = octeon_read_csr64(oct, ctrl);

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

528

reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

529

max_combined = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

634

u64 reg_val = 0ULL;

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

637

reg_val = octeon_read_csr64(oct, ctrl);

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

638

reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

639

max_combined = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1008

u32 reg_val = 0;

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1012

reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1015

reg_val = reg_val | (1 << q_no);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1017

reg_val = reg_val & (~(1 << q_no));

drivers/net/ethernet/cavium/liquidio/octeon_device.c

1019

octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

969

u64 reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/octeon_device.c

972

while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&

drivers/net/ethernet/cavium/liquidio/octeon_device.c

973

!(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&

drivers/net/ethernet/cavium/liquidio/octeon_device.c

975

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/octeon_device.c

986

reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;

drivers/net/ethernet/cavium/liquidio/octeon_device.c

989

reg_val);

drivers/net/ethernet/cavium/liquidio/octeon_device.c

991

reg_val = octeon_read_csr64(

drivers/net/ethernet/cavium/liquidio/octeon_device.c

993

if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1724

u64 reg_val;

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1728

reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1731

reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1734

reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1737

reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1740

reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1743

reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1746

reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1749

reg_val = 0;

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

1752

return reg_val;

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

36

u64 reg_val;

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

43

reg_val = nicvf_queue_reg_read(nic, reg, qidx);

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

44

if (((reg_val & bit_mask) >> bit_pos) == val)

drivers/net/ethernet/cavium/thunder/thunder_bgx.c

131

u64 reg_val;

drivers/net/ethernet/cavium/thunder/thunder_bgx.c

134

reg_val = bgx_reg_read(bgx, lmac, reg);

drivers/net/ethernet/cavium/thunder/thunder_bgx.c

135

if (zero && !(reg_val & mask))

drivers/net/ethernet/cavium/thunder/thunder_bgx.c

137

if (!zero && (reg_val & mask))

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

295

static const struct reg_val regs[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

327

static const struct reg_val regs[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

331

static const struct reg_val preemphasis[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

396

static const struct reg_val regs0[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

406

static const struct reg_val regs1[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

525

static const struct reg_val regs[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

554

static const struct reg_val uCclock40MHz[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

561

static const struct reg_val uCclockActivate[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

567

static const struct reg_val uCactivate[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

627

static const struct reg_val regs[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

667

static const struct reg_val regs[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

704

static const struct reg_val ael2020_reset_regs[] = {

drivers/net/ethernet/chelsio/cxgb3/ael1002.c

84

static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)

drivers/net/ethernet/emulex/benet/be_cmds.c

4771

u32 reg_val;

drivers/net/ethernet/emulex/benet/be_cmds.c

4775

reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);

drivers/net/ethernet/emulex/benet/be_cmds.c

4776

if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

305

u32 reg_val = 0;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

311

reg_val |= RESET_REQ_OR_DREQ;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

312

reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

319

dsaf_write_sub(dsaf_dev, reg_addr, reg_val);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

397

u32 reg_val = 0;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

400

reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

407

dsaf_write_sub(dsaf_dev, reg_addr, reg_val);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

419

u32 reg_val;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

426

reg_val = RESET_REQ_OR_DREQ;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

433

reg_val = 0x100 << dsaf_dev->reset_offset;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

441

dsaf_write_sub(dsaf_dev, reg_addr, reg_val);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

365

u32 reg_val;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

371

reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG);

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

372

if (0x1 != (reg_val & 0x1)) {

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

374

"RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

11

u32 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

18

reg_val = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

19

reg_val &= HCLGE_COMM_NIC_SW_RST_RDY;

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

20

reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

21

hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

29

reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

30

hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

391

unsigned int reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

419

reg_val = readl(tqp_vector->mask_addr + gl_offset) &

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

421

seq_printf(s, "%-7u", reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

423

reg_val = readl(tqp_vector->mask_addr + ql_offset) &

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

425

seq_printf(s, "%u\n", reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

877

__le16 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

2751

u32 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

2753

reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

2756

reg_val |= BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

2758

reg_val &= ~BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

2760

hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4003

u32 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4005

reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4006

if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4008

reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4009

hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4012

if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4014

reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4015

hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4140

u32 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4142

reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4144

reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4146

reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4148

hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4166

u32 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4197

reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

4199

BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c

295

*val = le16_to_cpu(req->reg_val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c

309

req->reg_val = cpu_to_le16(val);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

180

u32 *reg_val = data;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

215

*reg_val++ = le32_to_cpu(*desc_data++);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

234

u64 *reg_val = data;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

269

*reg_val++ = le64_to_cpu(*desc_data++);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

1463

u32 reg_val;

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

1465

reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

1467

reg_val |= HCLGEVF_NIC_SW_RST_RDY;

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

1469

reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

1472

reg_val);

drivers/net/ethernet/hisilicon/hns_mdio.c

317

u16 reg_val;

drivers/net/ethernet/hisilicon/hns_mdio.c

341

reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);

drivers/net/ethernet/hisilicon/hns_mdio.c

342

if (reg_val) {

drivers/net/ethernet/hisilicon/hns_mdio.c

348

reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,

drivers/net/ethernet/hisilicon/hns_mdio.c

351

return reg_val;

drivers/net/ethernet/hisilicon/hns_mdio.c

368

u16 reg_val;

drivers/net/ethernet/hisilicon/hns_mdio.c

406

reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);

drivers/net/ethernet/hisilicon/hns_mdio.c

407

if (reg_val) {

drivers/net/ethernet/hisilicon/hns_mdio.c

413

reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,

drivers/net/ethernet/hisilicon/hns_mdio.c

416

return reg_val;

drivers/net/ethernet/intel/e1000e/netdev.c

2999

u32 reg_val;

drivers/net/ethernet/intel/e1000e/netdev.c

3001

reg_val = er32(IOSFPC);

drivers/net/ethernet/intel/e1000e/netdev.c

3002

reg_val |= E1000_RCTL_RDMTS_HEX;

drivers/net/ethernet/intel/e1000e/netdev.c

3003

ew32(IOSFPC, reg_val);

drivers/net/ethernet/intel/e1000e/netdev.c

3005

reg_val = er32(TARC(0));

drivers/net/ethernet/intel/e1000e/netdev.c

3010

reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;

drivers/net/ethernet/intel/e1000e/netdev.c

3011

reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;

drivers/net/ethernet/intel/e1000e/netdev.c

3012

ew32(TARC(0), reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

2423

u32 reg_addr, u64 *reg_val,

drivers/net/ethernet/intel/i40e/i40e_common.c

2430

if (reg_val == NULL)

drivers/net/ethernet/intel/i40e/i40e_common.c

2441

*reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |

drivers/net/ethernet/intel/i40e/i40e_common.c

2458

u32 reg_addr, u64 reg_val,

drivers/net/ethernet/intel/i40e/i40e_common.c

2469

cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));

drivers/net/ethernet/intel/i40e/i40e_common.c

2470

cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));

drivers/net/ethernet/intel/i40e/i40e_common.c

4314

u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));

drivers/net/ethernet/intel/i40e/i40e_common.c

4316

return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;

drivers/net/ethernet/intel/i40e/i40e_common.c

4326

u32 *reg_val)

drivers/net/ethernet/intel/i40e/i40e_common.c

4333

*reg_val = 0;

drivers/net/ethernet/intel/i40e/i40e_common.c

4340

reg_val, NULL);

drivers/net/ethernet/intel/i40e/i40e_common.c

4348

(u16 *)reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4360

u32 reg_val)

drivers/net/ethernet/intel/i40e/i40e_common.c

4373

reg_val, NULL);

drivers/net/ethernet/intel/i40e/i40e_common.c

4381

(u16)reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4402

u16 reg_val;

drivers/net/ethernet/intel/i40e/i40e_common.c

4427

&reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4430

*val = reg_val;

drivers/net/ethernet/intel/i40e/i40e_common.c

4431

if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {

drivers/net/ethernet/intel/i40e/i40e_common.c

4499

u32 reg_addr, u32 *reg_val,

drivers/net/ethernet/intel/i40e/i40e_common.c

4506

if (!reg_val)

drivers/net/ethernet/intel/i40e/i40e_common.c

4517

*reg_val = le32_to_cpu(cmd_resp->value);

drivers/net/ethernet/intel/i40e/i40e_common.c

4565

u32 reg_addr, u32 reg_val,

drivers/net/ethernet/intel/i40e/i40e_common.c

4576

cmd->value = cpu_to_le32(reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4589

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)

drivers/net/ethernet/intel/i40e/i40e_common.c

4601

reg_val, NULL);

drivers/net/ethernet/intel/i40e/i40e_common.c

4611

wr32(hw, reg_addr, reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4658

u32 reg_addr, u32 reg_val,

drivers/net/ethernet/intel/i40e/i40e_common.c

4672

cmd->reg_value = cpu_to_le32(reg_val);

drivers/net/ethernet/intel/i40e/i40e_common.c

4703

u32 reg_addr, u32 *reg_val,

drivers/net/ethernet/intel/i40e/i40e_common.c

4725

*reg_val = le32_to_cpu(cmd->reg_value);

drivers/net/ethernet/intel/i40e/i40e_common.c

486

u32 reg_val;

drivers/net/ethernet/intel/i40e/i40e_common.c

493

reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));

drivers/net/ethernet/intel/i40e/i40e_common.c

494

reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;

drivers/net/ethernet/intel/i40e/i40e_common.c

495

reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);

drivers/net/ethernet/intel/i40e/i40e_common.c

498

reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;

drivers/net/ethernet/intel/i40e/i40e_common.c

500

reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;

drivers/net/ethernet/intel/i40e/i40e_common.c

502

wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);

drivers/net/ethernet/intel/i40e/i40e_diag.c

121

u16 reg_val;

drivers/net/ethernet/intel/i40e/i40e_diag.c

124

ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);

drivers/net/ethernet/intel/i40e/i40e_diag.c

126

((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==

drivers/net/ethernet/intel/i40e/i40e_main.c

12477

u32 reg_val;

drivers/net/ethernet/intel/i40e/i40e_main.c

12490

reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);

drivers/net/ethernet/intel/i40e/i40e_main.c

12491

reg_val = (pf->rss_table_size == 512) ?

drivers/net/ethernet/intel/i40e/i40e_main.c

12492

(reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :

drivers/net/ethernet/intel/i40e/i40e_main.c

12493

(reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);

drivers/net/ethernet/intel/i40e/i40e_main.c

12494

i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);

drivers/net/ethernet/intel/i40e/i40e_prototype.h

402

u32 reg_addr, u32 *reg_val,

drivers/net/ethernet/intel/i40e/i40e_prototype.h

406

u32 reg_addr, u32 reg_val,

drivers/net/ethernet/intel/i40e/i40e_prototype.h

408

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);

drivers/net/ethernet/intel/i40e/i40e_prototype.h

413

u32 reg_addr, u32 reg_val,

drivers/net/ethernet/intel/i40e/i40e_prototype.h

419

u32 reg_addr, u32 *reg_val,

drivers/net/ethernet/intel/i40e/i40e_prototype.h

76

u32 reg_addr, u64 reg_val,

drivers/net/ethernet/intel/i40e/i40e_prototype.h

79

u32 reg_addr, u64 *reg_val,

drivers/net/ethernet/intel/iavf/iavf_main.c

2868

u32 reg_val;

drivers/net/ethernet/intel/iavf/iavf_main.c

2921

reg_val = rd32(hw, IAVF_VFGEN_RSTAT) &

drivers/net/ethernet/intel/iavf/iavf_main.c

2923

if (reg_val == VIRTCHNL_VFR_VFACTIVE ||

drivers/net/ethernet/intel/iavf/iavf_main.c

2924

reg_val == VIRTCHNL_VFR_COMPLETED) {

drivers/net/ethernet/intel/iavf/iavf_main.c

2970

reg_val = rd32(hw, IAVF_VF_ARQLEN1) & IAVF_VF_ARQLEN1_ARQENABLE_MASK;

drivers/net/ethernet/intel/iavf/iavf_main.c

2971

if (!reg_val) {

drivers/net/ethernet/intel/iavf/iavf_main.c

3110

u32 reg_val;

drivers/net/ethernet/intel/iavf/iavf_main.c

3130

reg_val = rd32(hw, IAVF_VF_ARQLEN1) &

drivers/net/ethernet/intel/iavf/iavf_main.c

3132

if (!reg_val)

drivers/net/ethernet/intel/iavf/iavf_main.c

3146

reg_val = rd32(hw, IAVF_VFGEN_RSTAT) &

drivers/net/ethernet/intel/iavf/iavf_main.c

3148

if (reg_val == VIRTCHNL_VFR_VFACTIVE)

drivers/net/ethernet/intel/iavf/iavf_main.c

3157

reg_val);

drivers/net/ethernet/intel/ice/ice_common.c

2636

u32 reg_val, gsize, bsize;

drivers/net/ethernet/intel/ice/ice_common.c

2638

reg_val = rd32(hw, GLQF_FD_SIZE);

drivers/net/ethernet/intel/ice/ice_common.c

2641

gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);

drivers/net/ethernet/intel/ice/ice_common.c

2642

bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);

drivers/net/ethernet/intel/ice/ice_common.c

2646

gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);

drivers/net/ethernet/intel/ice/ice_common.c

2647

bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);

drivers/net/ethernet/intel/idpf/idpf_lib.c

1864

u32 reg_val = readl(reset_reg->rstat);

drivers/net/ethernet/intel/idpf/idpf_lib.c

1870

if (reg_val != 0xFFFFFFFF && (reg_val & reset_reg->rstat_m))

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1328

struct idpf_vec_regs reg_val;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1342

reg_val.dyn_ctl_reg = le32_to_cpu(chunk->dynctl_reg_start);

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1343

reg_val.itrn_reg = le32_to_cpu(chunk->itrn_reg_start);

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1344

reg_val.itrn_index_spacing = le32_to_cpu(chunk->itrn_index_spacing);

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1350

reg_vals[num_regs].dyn_ctl_reg = reg_val.dyn_ctl_reg;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1351

reg_vals[num_regs].itrn_reg = reg_val.itrn_reg;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1353

reg_val.itrn_index_spacing;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1355

reg_val.dyn_ctl_reg += dynctl_reg_spacing;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1356

reg_val.itrn_reg += itrn_reg_spacing;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1381

u32 reg_val;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1392

reg_val = chunk->qtail_reg_start;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1394

reg_vals[reg_filled++] = reg_val;

drivers/net/ethernet/intel/idpf/idpf_virtchnl.c

1395

reg_val += chunk->qtail_reg_spacing;

drivers/net/ethernet/intel/igb/e1000_82575.c

2070

u32 reg_val, reg_offset;

drivers/net/ethernet/intel/igb/e1000_82575.c

2084

reg_val = rd32(reg_offset);

drivers/net/ethernet/intel/igb/e1000_82575.c

2086

reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |

drivers/net/ethernet/intel/igb/e1000_82575.c

2091

reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));

drivers/net/ethernet/intel/igb/e1000_82575.c

2093

reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |

drivers/net/ethernet/intel/igb/e1000_82575.c

2096

wr32(reg_offset, reg_val);

drivers/net/ethernet/intel/igb/e1000_i210.c

829

u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;

drivers/net/ethernet/intel/igb/e1000_i210.c

836

reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;

drivers/net/ethernet/intel/igb/e1000_i210.c

837

wr32(E1000_MDICNFG, reg_val);

drivers/net/ethernet/intel/igb/e1000_i210.c

866

reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);

drivers/net/ethernet/intel/igb/e1000_i210.c

867

wr32(E1000_EEARBC_I210, reg_val);

drivers/net/ethernet/intel/igb/e1000_i210.c

875

reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);

drivers/net/ethernet/intel/igb/e1000_i210.c

876

wr32(E1000_EEARBC_I210, reg_val);

drivers/net/ethernet/intel/igb/igb_main.c

10013

u32 reg_val, reg_offset;

drivers/net/ethernet/intel/igb/igb_main.c

10022

reg_val = rd32(reg_offset);

drivers/net/ethernet/intel/igb/igb_main.c

10024

reg_val |= (BIT(vf) |

drivers/net/ethernet/intel/igb/igb_main.c

10027

reg_val &= ~(BIT(vf) |

drivers/net/ethernet/intel/igb/igb_main.c

10029

wr32(reg_offset, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

177

u32 *reg_val)

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

192

*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

2657

int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

2660

*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

2671

int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

2673

IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

727

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

751

reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

752

reg_val &= ~IXGBE_RXDCTL_ENABLE;

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

753

reg_val |= IXGBE_RXDCTL_SWFLSH;

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

754

IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

79

int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

80

int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

706

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

754

reg_val = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(reg_idx));

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

757

if (reg_val) {

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

758

reg_val |= IXGBE_TXDCTL_ENABLE;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

759

IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(reg_idx), reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

760

reg_val &= ~IXGBE_TXDCTL_ENABLE;

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

761

IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(reg_idx), reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1437

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1443

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1447

reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1450

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1457

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1461

reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1462

reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1463

reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1466

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1472

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1476

reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1477

reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1478

reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1481

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1488

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1492

reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1493

reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1494

reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1495

reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1498

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1559

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1569

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1573

reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1574

reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1579

reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1582

reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1591

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1656

u16 reg_slice, reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1678

reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1680

reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1683

reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1699

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1705

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1709

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1710

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1711

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1712

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1717

reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1720

reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

1729

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2537

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2542

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2546

reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2547

reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2552

reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2556

reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2560

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2566

IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2571

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2572

reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2573

reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2574

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2575

reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2579

IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2859

u32 reg_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2910

&reg_val);

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2914

reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2917

reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2919

reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

2923

reg_val);

drivers/net/ethernet/intel/ixgbevf/vf.c

161

u32 reg_val;

drivers/net/ethernet/intel/ixgbevf/vf.c

172

reg_val = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));

drivers/net/ethernet/intel/ixgbevf/vf.c

173

if (reg_val & IXGBE_RXDCTL_ENABLE) {

drivers/net/ethernet/intel/ixgbevf/vf.c

174

reg_val &= ~IXGBE_RXDCTL_ENABLE;

drivers/net/ethernet/intel/ixgbevf/vf.c

175

IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);

drivers/net/ethernet/intel/ixgbevf/vf.c

190

reg_val = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));

drivers/net/ethernet/intel/ixgbevf/vf.c

191

if (reg_val & IXGBE_TXDCTL_ENABLE) {

drivers/net/ethernet/intel/ixgbevf/vf.c

192

reg_val &= ~IXGBE_TXDCTL_ENABLE;

drivers/net/ethernet/intel/ixgbevf/vf.c

193

IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), reg_val);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1987

unsigned int mask = 0xfff, reg_val, shift;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1999

reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2000

if (reg_val & MVPP2_DSA_EXTENDED)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2109

unsigned int reg_val, shift;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2121

reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2122

if (reg_val & MVPP2_DSA_EXTENDED)

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

267

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

270

reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

273

if (!(reg_val & CN93_R_IN_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

275

reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

276

} while (!(reg_val & CN93_R_IN_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

279

reg_val |= CN93_R_IN_CTL_RDSIZE;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

280

reg_val |= CN93_R_IN_CTL_IS_64B;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

281

reg_val |= CN93_R_IN_CTL_ESR;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

282

octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

305

reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

306

octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

312

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

318

reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

321

if (!(reg_val & CN93_R_OUT_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

323

reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

324

} while (!(reg_val & CN93_R_OUT_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

327

reg_val &= ~(CN93_R_OUT_CTL_IMODE);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

328

reg_val &= ~(CN93_R_OUT_CTL_ROR_P);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

329

reg_val &= ~(CN93_R_OUT_CTL_NSR_P);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

330

reg_val &= ~(CN93_R_OUT_CTL_ROR_I);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

331

reg_val &= ~(CN93_R_OUT_CTL_NSR_I);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

332

reg_val &= ~(CN93_R_OUT_CTL_ES_I);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

333

reg_val &= ~(CN93_R_OUT_CTL_ROR_D);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

334

reg_val &= ~(CN93_R_OUT_CTL_NSR_D);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

335

reg_val &= ~(CN93_R_OUT_CTL_ES_D);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

336

reg_val |= (CN93_R_OUT_CTL_ES_P);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

338

octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

355

reg_val = ((u64)time_threshold << 32) |

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

357

octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

455

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

459

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_IRERR_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

460

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

462

"received IRERR_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

463

octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

466

reg_val = octep_read_csr64(oct,

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

468

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

471

i, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

473

reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

485

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

489

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_ORERR_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

490

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

492

"Received ORERR_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

493

octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

495

reg_val = octep_read_csr64(oct, CN93_SDP_R_ERR_TYPE(i));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

496

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

499

i, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

501

reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

513

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

516

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

517

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

519

"Received VFIRE_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

520

octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

530

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

533

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

534

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

536

"Received VFORE_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

537

octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

546

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

549

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

550

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

551

octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

561

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

564

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

565

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

567

"Received DMA_VF_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

568

octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

578

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

581

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

582

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

584

"Received PP_VF_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

585

octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

595

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

598

reg_val = octep_read_csr64(oct, CN93_SDP_EPF_MISC_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

599

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

601

"Received MISC_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

602

octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

713

u64 reg_val, intr_mask = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

721

reg_val = octep_read_csr64(oct,

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

723

reg_val &= ~CN93_INT_ENA_BIT;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

725

CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

727

reg_val = octep_read_csr64(oct,

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

729

reg_val &= ~CN93_INT_ENA_BIT;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

731

CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

768

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

779

reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

780

reg_val |= (0x1ULL << 62);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

781

octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

783

reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

784

reg_val |= 0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

785

octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

791

u64 reg_val = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

795

reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

796

reg_val |= (0x1ULL << 62);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

797

octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

801

reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

802

reg_val |= 0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

803

octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

820

u64 reg_val = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

824

reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

825

reg_val &= ~0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

826

octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

832

u64 reg_val = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

835

reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

836

reg_val &= ~0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

837

octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

288

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

291

reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

294

if (!(reg_val & CNXK_R_IN_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

296

reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

297

} while (!(reg_val & CNXK_R_IN_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

300

reg_val |= CNXK_R_IN_CTL_RDSIZE;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

301

reg_val |= CNXK_R_IN_CTL_IS_64B;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

302

reg_val |= CNXK_R_IN_CTL_ESR;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

303

octep_write_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

326

reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

327

octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

338

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

341

reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

344

if (!(reg_val & CNXK_R_OUT_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

346

reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

347

} while (!(reg_val & CNXK_R_OUT_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

380

reg_val &= ~(CNXK_R_OUT_CTL_IMODE);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

381

reg_val &= ~(CNXK_R_OUT_CTL_ROR_P);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

382

reg_val &= ~(CNXK_R_OUT_CTL_NSR_P);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

383

reg_val &= ~(CNXK_R_OUT_CTL_ROR_I);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

384

reg_val &= ~(CNXK_R_OUT_CTL_NSR_I);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

385

reg_val &= ~(CNXK_R_OUT_CTL_ES_I);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

386

reg_val &= ~(CNXK_R_OUT_CTL_ROR_D);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

387

reg_val &= ~(CNXK_R_OUT_CTL_NSR_D);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

388

reg_val &= ~(CNXK_R_OUT_CTL_ES_D);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

389

reg_val |= (CNXK_R_OUT_CTL_ES_P);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

391

octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

408

reg_val = ((u64)time_threshold << 32) |

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

410

octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

413

reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

414

reg_val &= ~0xFFFFFFFFULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

415

reg_val |= CFG_GET_OQ_WMARK(oct->conf);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

416

octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

505

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

509

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_IRERR_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

510

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

512

"received IRERR_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

513

octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

516

reg_val = octep_read_csr64(oct,

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

518

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

521

i, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

523

reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

535

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

539

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_ORERR_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

540

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

542

"Received ORERR_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

543

octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

545

reg_val = octep_read_csr64(oct, CNXK_SDP_R_ERR_TYPE(i));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

546

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

549

i, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

551

reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

563

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

566

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

567

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

569

"Received VFIRE_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

570

octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

580

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

583

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_VFORE_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

584

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

586

"Received VFORE_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

587

octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

596

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

599

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_DMA_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

600

if (reg_val)

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

601

octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

611

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

614

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

615

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

617

"Received DMA_VF_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

618

octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

628

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

631

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT(0));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

632

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

634

"Received PP_VF_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

635

octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

645

u64 reg_val = 0;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

648

reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_MISC_RINT);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

649

if (reg_val) {

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

651

"Received MISC_RINT intr: 0x%llx\n", reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

652

octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT, reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

753

u64 reg_val, intr_mask = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

761

reg_val = octep_read_csr64(oct,

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

763

reg_val &= ~CNXK_INT_ENA_BIT;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

765

CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

767

reg_val = octep_read_csr64(oct,

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

769

reg_val &= ~CNXK_INT_ENA_BIT;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

771

CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

807

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

818

reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

819

reg_val |= (0x1ULL << 62);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

820

octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

822

reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

823

reg_val |= 0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

824

octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

830

u64 reg_val = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

834

reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

835

reg_val |= (0x1ULL << 62);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

836

octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

840

reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

841

reg_val |= 0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

842

octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

859

u64 reg_val = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

863

reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

864

reg_val &= ~0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

865

octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

871

u64 reg_val = 0ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

874

reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

875

reg_val &= ~0x1ULL;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

876

octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

139

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

141

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

142

conf->ring_cfg.max_io_rings = (reg_val >> CN93_VF_R_IN_CTL_RPVF_POS) &

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

165

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

167

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

170

if (!(reg_val & CN93_VF_R_IN_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

172

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

173

} while (!(reg_val & CN93_VF_R_IN_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

175

reg_val |= CN93_VF_R_IN_CTL_RDSIZE;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

176

reg_val |= CN93_VF_R_IN_CTL_IS_64B;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

177

reg_val |= CN93_VF_R_IN_CTL_ESR;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

178

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

194

reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

195

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

204

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

206

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

209

if (!(reg_val & CN93_VF_R_OUT_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

211

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

212

} while (!(reg_val & CN93_VF_R_OUT_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

215

reg_val &= ~(CN93_VF_R_OUT_CTL_IMODE);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

216

reg_val &= ~(CN93_VF_R_OUT_CTL_ROR_P);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

217

reg_val &= ~(CN93_VF_R_OUT_CTL_NSR_P);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

218

reg_val &= ~(CN93_VF_R_OUT_CTL_ROR_I);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

219

reg_val &= ~(CN93_VF_R_OUT_CTL_NSR_I);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

220

reg_val &= ~(CN93_VF_R_OUT_CTL_ES_I);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

221

reg_val &= ~(CN93_VF_R_OUT_CTL_ROR_D);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

222

reg_val &= ~(CN93_VF_R_OUT_CTL_NSR_D);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

223

reg_val &= ~(CN93_VF_R_OUT_CTL_ES_D);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

224

reg_val |= (CN93_VF_R_OUT_CTL_ES_P);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

226

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

240

reg_val = ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

241

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

275

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

281

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_MBOX_PF_VF_INT(0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

282

if (reg_val & CN93_VF_SDP_R_MBOX_PF_VF_INT_STATUS) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

284

octep_vf_write_csr64(oct, CN93_VF_SDP_R_MBOX_PF_VF_INT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

313

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

317

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

318

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

319

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

321

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

322

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

323

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

334

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

342

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

343

reg_val &= ~BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

344

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

346

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

347

reg_val &= ~BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

348

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

370

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

379

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

380

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

381

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

383

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

384

reg_val |= ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

385

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

391

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

393

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

394

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

395

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

399

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

400

reg_val |= ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

401

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

418

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

420

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

421

reg_val &= ~ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

422

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

428

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

430

reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

431

reg_val &= ~ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

432

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

141

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

143

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

144

conf->ring_cfg.max_io_rings = (reg_val >> CNXK_VF_R_IN_CTL_RPVF_POS) &

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

168

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

170

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

173

if (!(reg_val & CNXK_VF_R_IN_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

175

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

176

} while (!(reg_val & CNXK_VF_R_IN_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

178

reg_val |= CNXK_VF_R_IN_CTL_RDSIZE;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

179

reg_val |= CNXK_VF_R_IN_CTL_IS_64B;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

180

reg_val |= CNXK_VF_R_IN_CTL_ESR;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

181

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

197

reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

198

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

209

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

211

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

214

if (!(reg_val & CNXK_VF_R_OUT_CTL_IDLE)) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

216

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

217

} while (!(reg_val & CNXK_VF_R_OUT_CTL_IDLE));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

252

reg_val &= ~(CNXK_VF_R_OUT_CTL_IMODE);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

253

reg_val &= ~(CNXK_VF_R_OUT_CTL_ROR_P);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

254

reg_val &= ~(CNXK_VF_R_OUT_CTL_NSR_P);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

255

reg_val &= ~(CNXK_VF_R_OUT_CTL_ROR_I);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

256

reg_val &= ~(CNXK_VF_R_OUT_CTL_NSR_I);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

257

reg_val &= ~(CNXK_VF_R_OUT_CTL_ES_I);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

258

reg_val &= ~(CNXK_VF_R_OUT_CTL_ROR_D);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

259

reg_val &= ~(CNXK_VF_R_OUT_CTL_NSR_D);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

260

reg_val &= ~(CNXK_VF_R_OUT_CTL_ES_D);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

261

reg_val |= (CNXK_VF_R_OUT_CTL_ES_P);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

263

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

277

reg_val = ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

278

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

281

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

282

reg_val &= ~GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

283

reg_val |= CFG_GET_OQ_WMARK(oct->conf);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

284

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

318

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

324

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_MBOX_PF_VF_INT(0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

325

if (reg_val & CNXK_VF_SDP_R_MBOX_PF_VF_INT_STATUS) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

327

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_MBOX_PF_VF_INT(0), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

356

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

360

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

361

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

362

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

364

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

365

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

366

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

377

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

385

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

386

reg_val &= ~BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

387

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

389

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

390

reg_val &= ~BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

391

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

413

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

422

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

423

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

424

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

426

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

427

reg_val |= ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

428

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

434

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

436

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

437

reg_val |= BIT_ULL_MASK(62);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

438

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

442

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

443

reg_val |= ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

444

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

461

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

463

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

464

reg_val &= ~ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

465

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

471

u64 reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

473

reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

474

reg_val &= ~ULL(1);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

475

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no), reg_val);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.c

117

u64 reg_val = 0ull;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.c

132

reg_val = readq(mbox->mbox_write_reg);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.c

133

if (reg_val != cmd.u64) {

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.c

134

rsp->u64 = reg_val;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.c

146

rsp->u64 = reg_val;

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

103

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

107

reg_val = readq(reg);

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

108

if (zero && !(reg_val & mask))

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

110

if (!zero && (reg_val & mask))

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1297

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1309

reg_val = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_RXC_CFG1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1310

reg_val &= ~MAX_RXC_ICB_CNT;

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1311

reg_val |= FIELD_PREP(MAX_RXC_ICB_CNT,

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1313

rvu_write64(rvu, BLKADDR_CPT0, CPT_AF_RXC_CFG1, reg_val);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

634

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

639

reg_val = FIELD_PREP(GENMASK_ULL(39, 32), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

642

reg_val |= FIELD_PREP(GENMASK_ULL(18, 16), ETH_ALEN - 1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

645

reg_val |= FIELD_PREP(GENMASK_ULL(11, 11), 1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

646

reg_val |= FIELD_PREP(GENMASK_ULL(10, 8), NPC_LID_LA);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

651

reg_val |= FIELD_PREP(GENMASK_ULL(12, 12), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

654

reg_val |= FIELD_PREP(GENMASK_ULL(7, 4), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

657

reg_val |= FIELD_PREP(GENMASK_ULL(3, 0), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

659

rvu_write64(rvu, blkaddr, NPC_AF_INTFX_EXACT_CFG(NIX_INTF_RX), reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

143

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

146

reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

147

reg_val |= BIT_ULL(16);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

148

otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

151

reg_val = otx2_read64(pf, CN10K_CPT_LF_CTL);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

152

reg_val |= BIT_ULL(0);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

153

otx2_write64(pf, CN10K_CPT_LF_CTL, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

161

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

171

reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

172

inflight = FIELD_GET(CPT_LF_INPROG_INFLIGHT, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

186

reg_val &= ~BIT_ULL(16);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

187

otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

192

reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

193

if (reg_val & BIT_ULL(31))

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

197

reg_val = otx2_read64(pf, CN10K_CPT_LF_Q_GRP_PTR);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

198

nq_ptr = FIELD_GET(CPT_LF_Q_GRP_PTR_DQ_PTR, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

199

dq_ptr = FIELD_GET(CPT_LF_Q_GRP_PTR_DQ_PTR, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

204

reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

205

inflight = FIELD_GET(CPT_LF_INPROG_INFLIGHT, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

206

grb_cnt = FIELD_GET(CPT_LF_INPROG_GRB_CNT, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

207

gwb_cnt = FIELD_GET(CPT_LF_INPROG_GWB_CNT, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

269

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

284

reg_val = FIELD_PREP(CPT_LF_Q_SIZE_DIV40, CN10K_CPT_SIZE_DIV40 +

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

286

otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, reg_val);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

435

u64 reg_val;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

484

reg_val = FIELD_PREP(CPT_LF_CTX_FLUSH_CPTR, sa_iova >> 7);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c

485

otx2_write64(pf, CN10K_CPT_LF_CTX_FLUSH, reg_val);

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3030

u32 reg_val;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3032

reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3035

mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3040

mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3045

u32 reg_val;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3047

reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

3050

mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));

drivers/net/ethernet/microchip/lan743x_ethtool.c

75

u32 reg_val;

drivers/net/ethernet/microchip/lan743x_ethtool.c

85

reg_val = lan743x_csr_read(adapter, OTP_STATUS);

drivers/net/ethernet/microchip/lan743x_ethtool.c

86

} while (reg_val & OTP_STATUS_BUSY_);

drivers/net/ethernet/microchip/lan743x_main.h

553

#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)

drivers/net/ethernet/qlogic/qed/qed_debug.c

1380

u32 reg_val[NUM_DBG_RESET_REGS] = { 0 };

drivers/net/ethernet/qlogic/qed/qed_debug.c

1397

reg_val[rst_reg_id] = qed_rd(p_hwfn, p_ptt,

drivers/net/ethernet/qlogic/qed/qed_debug.c

1414

!(reg_val[blk->reset_reg_id] &

drivers/net/ethernet/qlogic/qed/qed_debug.c

1709

u32 reg_val[NUM_DBG_RESET_REGS] = { 0 };

drivers/net/ethernet/qlogic/qed/qed_debug.c

1731

reg_val[block->reset_reg_id] |=

drivers/net/ethernet/qlogic/qed/qed_debug.c

1747

if (reg_val[reset_reg_id]) {

drivers/net/ethernet/qlogic/qed/qed_debug.c

1755

reg_val[reset_reg_id]);

drivers/net/ethernet/qlogic/qed/qed_debug.c

3195

u32 block_size, ram_size, offset = 0, reg_val, i;

drivers/net/ethernet/qlogic/qed/qed_debug.c

3203

reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr);

drivers/net/ethernet/qlogic/qed/qed_debug.c

3204

block_size = reg_val &

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1253

u32 reg_val;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1257

reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1258

SET_FIELD(reg_val,

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1260

qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1261

if (reg_val) {

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1262

reg_val =

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1266

if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1272

reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1274

SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1275

qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1286

u32 reg_val;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1290

reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1291

SET_FIELD(reg_val,

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1294

SET_FIELD(reg_val,

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1297

qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1298

if (reg_val) {

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1299

reg_val =

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1303

if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1309

reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1311

SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1313

SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1314

qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1341

u32 reg_val;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1344

reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1345

SET_FIELD(reg_val,

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1348

SET_FIELD(reg_val,

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1351

qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1352

if (reg_val) {

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1353

reg_val =

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1357

if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1388

u32 reg_val, cfg_mask;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1391

reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1398

reg_val |= cfg_mask;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1407

reg_val &= ~cfg_mask;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1411

qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1449

u32 reg_val, cam_line;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1462

reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1464

reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

1465

qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

884

u32 reg_val, i;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

886

for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;

drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

889

reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);

drivers/net/ethernet/realtek/r8169_phy_config.c

433

u16 reg_val;

drivers/net/ethernet/realtek/r8169_phy_config.c

437

reg_val = phy_read(phydev, 0x06);

drivers/net/ethernet/realtek/r8169_phy_config.c

440

if (reg_val != val)

drivers/net/ethernet/renesas/rswitch_l2.c

198

u32 reg_val;

drivers/net/ethernet/renesas/rswitch_l2.c

206

reg_val = FIELD_PREP(FWMACAGC_MACAGT, time);

drivers/net/ethernet/renesas/rswitch_l2.c

207

reg_val |= FWMACAGC_MACAGE | FWMACAGC_MACAGSL;

drivers/net/ethernet/renesas/rswitch_l2.c

208

iowrite32(reg_val, rdev->priv->addr + FWMACAGC);

drivers/net/ethernet/renesas/rswitch_main.c

122

u32 reg_val;

drivers/net/ethernet/renesas/rswitch_main.c

142

reg_val = FIELD_PREP(FWMACAGC_MACAGT, RSW_AGEING_TIME);

drivers/net/ethernet/renesas/rswitch_main.c

143

reg_val |= FWMACAGC_MACAGE | FWMACAGC_MACAGSL;

drivers/net/ethernet/renesas/rswitch_main.c

144

iowrite32(reg_val, priv->addr + FWMACAGC);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

168

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

170

reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

171

reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

172

reg_val |= SXGBE_CORE_RXQ_ENABLE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

173

writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

178

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

180

reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

181

reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

182

reg_val |= SXGBE_CORE_RXQ_DISABLE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c

183

writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

23

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

25

reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

33

reg_val |= SXGBE_DMA_AXI_UNDEF_BURST;

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

36

reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT);

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

38

writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

47

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

50

reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

53

reg_val |= SXGBE_DMA_PBL_X8MODE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

54

writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

56

reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

57

reg_val |= (pbl << SXGBE_DMA_TXPBL_LSHIFT);

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

58

writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

60

reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

61

reg_val |= (pbl << SXGBE_DMA_RXPBL_LSHIFT);

drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

62

writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

352

u32 reg_val = 0;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

369

reg_val = SXGBE_CORE_RSS_CTL_TCP4TE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

378

reg_val = SXGBE_CORE_RSS_CTL_UDP4TE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

395

reg_val = SXGBE_CORE_RSS_CTL_IP2TE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

402

reg_val |= readl(priv->ioaddr + SXGBE_CORE_RSS_CTL_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c

403

writel(reg_val, priv->ioaddr + SXGBE_CORE_RSS_CTL_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

100

writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

106

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

108

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

109

reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_ACTIVE);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

110

reg_val |= (threshold << RX_FC_ACTIVE);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

112

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

117

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

119

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

120

reg_val |= SXGBE_MTL_ENABLE_FC;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

121

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

127

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

129

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

130

reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_DEACTIVE);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

131

reg_val |= (threshold << RX_FC_DEACTIVE);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

133

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

138

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

140

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

141

reg_val |= SXGBE_MTL_RXQ_OP_FEP;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

143

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

148

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

150

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

151

reg_val &= ~(SXGBE_MTL_RXQ_OP_FEP);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

153

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

158

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

160

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

161

reg_val |= SXGBE_MTL_RXQ_OP_FUP;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

163

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

168

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

170

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

171

reg_val &= ~(SXGBE_MTL_RXQ_OP_FUP);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

173

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

180

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

182

reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

185

reg_val |= SXGBE_MTL_SFMODE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

189

reg_val |= MTL_CONTROL_TTC_64;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

191

reg_val |= MTL_CONTROL_TTC_96;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

193

reg_val |= MTL_CONTROL_TTC_128;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

195

reg_val |= MTL_CONTROL_TTC_192;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

197

reg_val |= MTL_CONTROL_TTC_256;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

199

reg_val |= MTL_CONTROL_TTC_384;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

201

reg_val |= MTL_CONTROL_TTC_512;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

205

writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

211

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

213

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

216

reg_val |= SXGBE_RX_MTL_SFMODE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

219

reg_val |= MTL_CONTROL_RTC_64;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

221

reg_val |= MTL_CONTROL_RTC_96;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

223

reg_val |= MTL_CONTROL_RTC_128;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

227

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

23

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

25

reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

26

reg_val &= ETS_RST;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

31

reg_val &= ETS_WRR;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

34

reg_val |= ETS_WFQ;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

37

reg_val |= ETS_DWRR;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

40

writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

44

reg_val &= RAA_SP;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

47

reg_val |= RAA_WSP;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

50

writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

64

u32 fifo_bits, reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

68

reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

69

reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

70

writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

76

u32 fifo_bits, reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

80

reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

81

reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

82

writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

87

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

89

reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

90

reg_val |= SXGBE_MTL_ENABLE_QUEUE;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

91

writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

96

u32 reg_val;

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

98

reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));

drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

99

reg_val &= ~SXGBE_MTL_ENABLE_QUEUE;

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

150

u32 reg_val = mask << 16;

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

153

reg_val |= mask & (val << (ffs(mask) - 1));

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

155

return reg_val;

drivers/net/ethernet/sun/niu.c

2745

static u64 vlan_entry_set_parity(u64 reg_val)

drivers/net/ethernet/sun/niu.c

2753

if (hweight64(reg_val & port01_mask) & 1)

drivers/net/ethernet/sun/niu.c

2754

reg_val |= ENET_VLAN_TBL_PARITY0;

drivers/net/ethernet/sun/niu.c

2756

reg_val &= ~ENET_VLAN_TBL_PARITY0;

drivers/net/ethernet/sun/niu.c

2758

if (hweight64(reg_val & port23_mask) & 1)

drivers/net/ethernet/sun/niu.c

2759

reg_val |= ENET_VLAN_TBL_PARITY1;

drivers/net/ethernet/sun/niu.c

2761

reg_val &= ~ENET_VLAN_TBL_PARITY1;

drivers/net/ethernet/sun/niu.c

2763

return reg_val;

drivers/net/ethernet/sun/niu.c

2769

u64 reg_val = nr64(ENET_VLAN_TBL(index));

drivers/net/ethernet/sun/niu.c

2771

reg_val &= ~((ENET_VLAN_TBL_VPR |

drivers/net/ethernet/sun/niu.c

2775

reg_val |= (ENET_VLAN_TBL_VPR <<

drivers/net/ethernet/sun/niu.c

2777

reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));

drivers/net/ethernet/sun/niu.c

2779

reg_val = vlan_entry_set_parity(reg_val);

drivers/net/ethernet/sun/niu.c

2781

nw64(ENET_VLAN_TBL(index), reg_val);

drivers/net/ethernet/sun/sungem.c

250

static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)

drivers/net/ethernet/sun/sungem.c

517

u32 reg_val, changed_bits;

drivers/net/ethernet/sun/sungem.c

519

reg_val = (mif_status & MIF_STATUS_DATA) >> 16;

drivers/net/ethernet/sun/sungem.c

522

gem_handle_mif_event(gp, reg_val, changed_bits);

drivers/net/ethernet/wangxun/libwx/wx_sriov.c

496

u32 max_frs, reg_val;

drivers/net/ethernet/wangxun/libwx/wx_sriov.c

508

reg_val = rd32(wx, WX_MAC_WDG_TIMEOUT) & WX_MAC_WDG_TIMEOUT_WTO_MASK;

drivers/net/ethernet/wangxun/libwx/wx_sriov.c

509

if (max_frs > (reg_val + WX_MAC_WDG_TIMEOUT_WTO_DELTA))

drivers/net/ethernet/wangxun/libwx/wx_vf.c

138

u32 reg_val;

drivers/net/ethernet/wangxun/libwx/wx_vf.c

153

reg_val = rd32(wx, WX_VXRXDCTL(i));

drivers/net/ethernet/wangxun/libwx/wx_vf.c

154

reg_val &= ~WX_VXRXDCTL_ENABLE;

drivers/net/ethernet/wangxun/libwx/wx_vf.c

155

wr32(wx, WX_VXRXDCTL(i), reg_val);

drivers/net/phy/mediatek/mtk-ge-soc.c

389

int reg_val;

drivers/net/phy/mediatek/mtk-ge-soc.c

398

MTK_PHY_RG_AD_CAL_CLK, reg_val,

drivers/net/phy/mediatek/mtk-ge-soc.c

399

reg_val & MTK_PHY_DA_CAL_CLK, 500,

drivers/net/phy/micrel.c

251

#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)

drivers/net/phy/micrel.c

252

#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)

drivers/net/phy/mscc/mscc_main.c

1076

static const struct reg_val pre_init1[] = {

drivers/net/phy/mscc/mscc_main.c

1124

static const struct reg_val pre_init2[] = {

drivers/net/phy/mscc/mscc_main.c

1365

static const struct reg_val pre_init1[] = {

drivers/net/phy/mscc/mscc_main.c

1389

static const struct reg_val pre_init2[] = {

drivers/net/phy/mscc/mscc_main.c

1984

static const struct reg_val pre_init1[] = {

drivers/net/phy/mscc/mscc_main.c

215

u16 reg_val;

drivers/net/phy/mscc/mscc_main.c

217

reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);

drivers/net/phy/mscc/mscc_main.c

218

if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)

drivers/net/phy/mscc/mscc_main.c

2231

u16 reg_val = 0;

drivers/net/phy/mscc/mscc_main.c

2234

reg_val = MSCC_PHY_SERDES_ANEG;

drivers/net/phy/mscc/mscc_main.c

2238

reg_val);

drivers/net/phy/mscc/mscc_main.c

229

u16 reg_val;

drivers/net/phy/mscc/mscc_main.c

231

reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);

drivers/net/phy/mscc/mscc_main.c

233

reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |

drivers/net/phy/mscc/mscc_main.c

237

reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |

drivers/net/phy/mscc/mscc_main.c

241

rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);

drivers/net/phy/mscc/mscc_main.c

245

reg_val = 0;

drivers/net/phy/mscc/mscc_main.c

248

reg_val = FORCE_MDI_CROSSOVER_MDI;

drivers/net/phy/mscc/mscc_main.c

250

reg_val = FORCE_MDI_CROSSOVER_MDIX;

drivers/net/phy/mscc/mscc_main.c

254

reg_val);

drivers/net/phy/mscc/mscc_main.c

263

int reg_val;

drivers/net/phy/mscc/mscc_main.c

265

reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,

drivers/net/phy/mscc/mscc_main.c

267

if (reg_val < 0)

drivers/net/phy/mscc/mscc_main.c

268

return reg_val;

drivers/net/phy/mscc/mscc_main.c

270

reg_val &= DOWNSHIFT_CNTL_MASK;

drivers/net/phy/mscc/mscc_main.c

271

if (!(reg_val & DOWNSHIFT_EN))

drivers/net/phy/mscc/mscc_main.c

274

*count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;

drivers/net/phy/mscc/mscc_main.c

302

u16 reg_val;

drivers/net/phy/mscc/mscc_main.c

338

reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);

drivers/net/phy/mscc/mscc_main.c

340

reg_val |= SECURE_ON_ENABLE;

drivers/net/phy/mscc/mscc_main.c

342

reg_val &= ~SECURE_ON_ENABLE;

drivers/net/phy/mscc/mscc_main.c

343

__phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);

drivers/net/phy/mscc/mscc_main.c

351

reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);

drivers/net/phy/mscc/mscc_main.c

352

reg_val |= MII_VSC85XX_INT_MASK_WOL;

drivers/net/phy/mscc/mscc_main.c

353

rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);

drivers/net/phy/mscc/mscc_main.c

358

reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);

drivers/net/phy/mscc/mscc_main.c

359

reg_val &= (~MII_VSC85XX_INT_MASK_WOL);

drivers/net/phy/mscc/mscc_main.c

360

rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);

drivers/net/phy/mscc/mscc_main.c

365

reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);

drivers/net/phy/mscc/mscc_main.c

374

u16 reg_val;

drivers/net/phy/mscc/mscc_main.c

383

reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);

drivers/net/phy/mscc/mscc_main.c

384

if (reg_val & SECURE_ON_ENABLE)

drivers/net/phy/mscc/mscc_main.c

504

u16 reg_val;

drivers/net/phy/mscc/mscc_main.c

507

reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);

drivers/net/phy/mscc/mscc_main.c

508

reg_val &= ~(MAC_IF_SELECTION_MASK);

drivers/net/phy/mscc/mscc_main.c

514

reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);

drivers/net/phy/mscc/mscc_main.c

517

reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);

drivers/net/phy/mscc/mscc_main.c

521

reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);

drivers/net/phy/mscc/mscc_main.c

527

rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);

drivers/net/phy/mscc/mscc_main.c

553

u16 reg_val = 0;

drivers/net/phy/mscc/mscc_main.c

591

reg_val |= rx_delay << rgmii_rx_delay_pos;

drivers/net/phy/mscc/mscc_main.c

592

reg_val |= tx_delay << rgmii_tx_delay_pos;

drivers/net/phy/mscc/mscc_main.c

596

rgmii_cntl, mask, reg_val);

drivers/net/phy/mscc/mscc_main.c

644

static const struct reg_val init_seq[] = {

drivers/net/phy/mscc/mscc_main.c

688

static const struct reg_val init_eee[] = {

drivers/net/phy/mscc/mscc_main.c

867

u16 reg_val;

drivers/net/phy/mscc/mscc_main.c

876

reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);

drivers/net/phy/mscc/mscc_main.c

878

(reg_val & PROC_CMD_NCOMPLETED) &&

drivers/net/phy/mscc/mscc_main.c

879

!(reg_val & PROC_CMD_FAILED));

drivers/net/phy/mscc/mscc_main.c

883

if (reg_val & PROC_CMD_FAILED)

drivers/net/phy/mscc/mscc_main.c

886

if (reg_val & PROC_CMD_NCOMPLETED)

drivers/net/phy/mscc/mscc_serdes.c

100

reg_val = (des_phy_ctrl << PHY_S6G_DES_PHY_CTRL_POS) |

drivers/net/phy/mscc/mscc_serdes.c

107

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

120

u32 reg_val;

drivers/net/phy/mscc/mscc_serdes.c

126

reg_val = base_val | (ib_rtrm_adj << 25) |

drivers/net/phy/mscc/mscc_serdes.c

132

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

146

u32 reg_val = 0;

drivers/net/phy/mscc/mscc_serdes.c

152

reg_val = (ib_tjtag << 17) + (ib_tsdet << 12) + (ib_scaly << 8) +

drivers/net/phy/mscc/mscc_serdes.c

156

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

190

u32 reg_val;

drivers/net/phy/mscc/mscc_serdes.c

193

reg_val = (ib_ini_hp << 24) + (ib_ini_mid << 16) +

drivers/net/phy/mscc/mscc_serdes.c

197

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

209

u32 reg_val;

drivers/net/phy/mscc/mscc_serdes.c

212

reg_val = (ib_max_hp << 24) + (ib_max_mid << 16) +

drivers/net/phy/mscc/mscc_serdes.c

216

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

255

u32 reg_val;

drivers/net/phy/mscc/mscc_serdes.c

259

reg_val = (rx_ji_ampl << 8) | (rx_step_freq << 4) |

drivers/net/phy/mscc/mscc_serdes.c

264

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

275

u32 reg_val;

drivers/net/phy/mscc/mscc_serdes.c

279

reg_val = (prbs_sel << 20) | (test_mode << 16) | (rx_dft_ena << 2);

drivers/net/phy/mscc/mscc_serdes.c

282

reg_val);

drivers/net/phy/mscc/mscc_serdes.c

293

u32 reg_val;

drivers/net/phy/mscc/mscc_serdes.c

299

reg_val = base_val | (selbgv820 << 23);

drivers/net/phy/mscc/mscc_serdes.c

301

PHY_S6G_PLL5G_CFG0, reg_val);

drivers/net/phy/mscc/mscc_serdes.c

96

u32 reg_val;

drivers/net/phy/nxp-tja11xx.c

302

u16 reg_mask, reg_val;

drivers/net/phy/nxp-tja11xx.c

317

reg_val = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |

drivers/net/phy/nxp-tja11xx.c

325

reg_val |= (ret & 0xffff);

drivers/net/phy/nxp-tja11xx.c

326

ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);

drivers/net/phy/nxp-tja11xx.c

337

reg_val = ret & 0xffff;

drivers/net/phy/nxp-tja11xx.c

338

ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);

drivers/net/phy/vitesse.c

385

u16 reg_val;

drivers/net/phy/vitesse.c

387

reg_val = phy_read(phydev, MII_VSC73XX_PHY_AUX_CTRL_STAT);

drivers/net/phy/vitesse.c

388

if (reg_val & MII_VSC73XX_PACS_NO_MDI_X_IND)

drivers/net/pse-pd/tps23881.c

101

reg_val >>= 8;

drivers/net/pse-pd/tps23881.c

103

return (reg_val >> field_offset) & field_mask;

drivers/net/pse-pd/tps23881.c

1132

static u8 tps23881_irq_export_chans_helper(u16 reg_val, u8 field_offset)

drivers/net/pse-pd/tps23881.c

1136

val = (reg_val >> (4 + field_offset) & 0xf0) |

drivers/net/pse-pd/tps23881.c

1137

(reg_val >> field_offset & 0x0f);

drivers/net/pse-pd/tps23881.c

1171

u16 reg_val,

drivers/net/pse-pd/tps23881.c

1177

if (reg_val & TPS23881_REG_TSD) {

drivers/net/pse-pd/tps23881.c

1189

u16 reg_val,

drivers/net/pse-pd/tps23881.c

119

static u16 tps23881_set_val(u16 reg_val, u8 chan, u8 field_offset,

drivers/net/pse-pd/tps23881.c

1196

chans = tps23881_irq_export_chans_helper(reg_val, 0);

drivers/net/pse-pd/tps23881.c

1227

u16 reg_val,

drivers/net/pse-pd/tps23881.c

1233

chans = tps23881_irq_export_chans_helper(reg_val, 4);

drivers/net/pse-pd/tps23881.c

1240

u16 reg_val,

drivers/net/pse-pd/tps23881.c

1248

chans = tps23881_irq_export_chans_helper(reg_val, 0);

drivers/net/pse-pd/tps23881.c

125

reg_val &= ~(field_mask << field_offset);

drivers/net/pse-pd/tps23881.c

126

reg_val |= (field_val << field_offset);

drivers/net/pse-pd/tps23881.c

1270

u16 reg_val,

drivers/net/pse-pd/tps23881.c

1277

chans = tps23881_irq_export_chans_helper(reg_val, 4);

drivers/net/pse-pd/tps23881.c

128

reg_val &= ~(field_mask << (field_offset + 8));

drivers/net/pse-pd/tps23881.c

129

reg_val |= (field_val << (field_offset + 8));

drivers/net/pse-pd/tps23881.c

132

return reg_val;

drivers/net/pse-pd/tps23881.c

97

static u16 tps23881_calc_val(u16 reg_val, u8 chan, u8 field_offset,

drivers/net/wireless/ath/ath10k/bmi.c

198

int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val)

drivers/net/wireless/ath/ath10k/bmi.c

206

address, reg_val);

drivers/net/wireless/ath/ath10k/bmi.c

215

cmd.write_soc_reg.value = __cpu_to_le32(reg_val);

drivers/net/wireless/ath/ath10k/bmi.c

227

int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val)

drivers/net/wireless/ath/ath10k/bmi.c

253

*reg_val = __le32_to_cpu(resp.read_soc_reg.value);

drivers/net/wireless/ath/ath10k/bmi.c

256

*reg_val);

drivers/net/wireless/ath/ath10k/bmi.h

273

int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val);

drivers/net/wireless/ath/ath10k/bmi.h

274

int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val);

drivers/net/wireless/ath/ath10k/debug.c

691

u32 reg_addr, reg_val;

drivers/net/wireless/ath/ath10k/debug.c

704

reg_val = ath10k_hif_read32(ar, reg_addr);

drivers/net/wireless/ath/ath10k/debug.c

705

len = scnprintf(buf, sizeof(buf), "0x%08x:0x%08x\n", reg_addr, reg_val);

drivers/net/wireless/ath/ath10k/debug.c

720

u32 reg_addr, reg_val;

drivers/net/wireless/ath/ath10k/debug.c

733

ret = kstrtou32_from_user(user_buf, count, 0, &reg_val);

drivers/net/wireless/ath/ath10k/debug.c

737

ath10k_hif_write32(ar, reg_addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

746

u32 addr, reg_val, mem_val;

drivers/net/wireless/ath/ath10k/hw.c

763

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

768

if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)

drivers/net/wireless/ath/ath10k/hw.c

771

hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];

drivers/net/wireless/ath/ath10k/hw.c

775

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

779

reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);

drivers/net/wireless/ath/ath10k/hw.c

780

reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |

drivers/net/wireless/ath/ath10k/hw.c

782

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

788

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

792

reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;

drivers/net/wireless/ath/ath10k/hw.c

793

reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);

drivers/net/wireless/ath/ath10k/hw.c

794

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

800

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

804

reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;

drivers/net/wireless/ath/ath10k/hw.c

805

reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);

drivers/net/wireless/ath/ath10k/hw.c

806

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

819

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

823

reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |

drivers/net/wireless/ath/ath10k/hw.c

826

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

834

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

838

if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))

drivers/net/wireless/ath/ath10k/hw.c

846

if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))

drivers/net/wireless/ath/ath10k/hw.c

851

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

855

reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;

drivers/net/wireless/ath/ath10k/hw.c

856

reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);

drivers/net/wireless/ath/ath10k/hw.c

857

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

865

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

869

if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))

drivers/net/wireless/ath/ath10k/hw.c

877

if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))

drivers/net/wireless/ath/ath10k/hw.c

882

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

886

reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;

drivers/net/wireless/ath/ath10k/hw.c

887

reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);

drivers/net/wireless/ath/ath10k/hw.c

888

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath10k/hw.c

894

ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);

drivers/net/wireless/ath/ath10k/hw.c

898

reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;

drivers/net/wireless/ath/ath10k/hw.c

899

ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);

drivers/net/wireless/ath/ath6kl/debug.c

1088

u32 reg_addr, reg_val;

drivers/net/wireless/ath/ath6kl/debug.c

1107

if (kstrtou32(sptr, 0, &reg_val))

drivers/net/wireless/ath/ath6kl/debug.c

1111

ar->debug.diag_reg_val_wr = reg_val;

drivers/net/wireless/ath/ath6kl/debug.c

946

__le32 reg_val;

drivers/net/wireless/ath/ath6kl/debug.c

968

(u32 *)&reg_val);

drivers/net/wireless/ath/ath6kl/debug.c

973

"0x%06x 0x%08x\n", addr, le32_to_cpu(reg_val));

drivers/net/wireless/ath/ath6kl/debug.c

984

(u32 *)&reg_val);

drivers/net/wireless/ath/ath6kl/debug.c

990

addr, le32_to_cpu(reg_val));

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3957

u32 reg_val;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4004

reg_val = le32_to_cpu(pBase->swreg);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4005

REG_WRITE(ah, AR_PHY_PMU1(ah), reg_val);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4011

reg_val = le32_to_cpu(pBase->swreg);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4015

REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4040

reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK(ah)) |

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4042

REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), reg_val);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

3955

u32 reg_val;

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

4049

reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

4053

reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

4055

brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

4061

reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

4065

reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c

4067

brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err);

drivers/net/wireless/intel/iwlegacy/4965-mac.c

5161

u32 reg_val;

drivers/net/wireless/intel/iwlegacy/4965-mac.c

5189

reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);

drivers/net/wireless/intel/iwlegacy/4965-mac.c

5191

reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);

drivers/net/wireless/intel/iwlwifi/dvm/main.c

2008

u32 reg_val =

drivers/net/wireless/intel/iwlwifi/dvm/main.c

2020

reg_val);

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

101

reg_val = CSR_HW_REV_STEP_DASH(mvm->trans->info.hw_rev);

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

104

reg_val |= radio_cfg_type << CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE;

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

105

reg_val |= radio_cfg_step << CSR_HW_IF_CONFIG_REG_POS_PHY_STEP;

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

106

reg_val |= radio_cfg_dash << CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

120

reg_val |= CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI;

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

123

reg_val |= CSR_HW_IF_CONFIG_REG_D3_DEBUG;

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

133

reg_val);

drivers/net/wireless/intel/iwlwifi/mvm/ops.c

84

u32 reg_val;

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/tx.c

485

u32 reg_val;

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/tx.c

526

reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/tx.c

528

reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

865

u32 val, tx_alc, reg_val;

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

889

reg_val = mt76_rr(dev, MT_BBP(IBI, 9));

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

907

mt76_wr(dev, MT_BBP(IBI, 9), reg_val);

drivers/net/wireless/realtek/rtw89/coex.c

1012

u32 reg_val;

drivers/net/wireless/realtek/rtw89/coex.c

1033

reg_val = rtw89_phy_read32(rtwdev, R_BTC_BB_BTG_RX);

drivers/net/wireless/realtek/rtw89/coex.c

1034

*val = !(reg_val & B_BTC_BB_GNT_MUX);

drivers/net/wireless/realtek/rtw89/coex.c

1047

reg_val = le32_to_cpu(pmreg->v1.mreg_val[idx]);

drivers/net/wireless/realtek/rtw89/coex.c

1048

*val = !(reg_val & B_BTC_BB_GNT_MUX);

drivers/net/wireless/realtek/rtw89/coex.c

1056

reg_val = le32_to_cpu(pmreg->v2.mreg_val[idx]);

drivers/net/wireless/realtek/rtw89/coex.c

1057

*val = !(reg_val & B_BTC_BB_GNT_MUX);

drivers/net/wireless/realtek/rtw89/coex.c

1062

reg_val = rtw89_phy_read32(rtwdev, pre_agc_addr);

drivers/net/wireless/realtek/rtw89/coex.c

1063

reg_val &= B_BTC_BB_PRE_AGC_MASK;

drivers/net/wireless/realtek/rtw89/coex.c

1064

*val = (reg_val == B_BTC_BB_PRE_AGC_VAL);

drivers/net/wireless/realtek/rtw89/coex.c

1077

reg_val = le32_to_cpu(pmreg->v1.mreg_val[idx]) &

drivers/net/wireless/realtek/rtw89/coex.c

1079

*val = (reg_val == B_BTC_BB_PRE_AGC_VAL);

drivers/net/wireless/realtek/rtw89/coex.c

1087

reg_val = le32_to_cpu(pmreg->v2.mreg_val[idx]) &

drivers/net/wireless/realtek/rtw89/coex.c

1089

*val = (reg_val == B_BTC_BB_PRE_AGC_VAL);

drivers/ntb/hw/amd/ntb_hw_amd.c

126

u64 base_addr, limit, reg_val;

drivers/ntb/hw/amd/ntb_hw_amd.c

156

reg_val = read64(peer_mmio + xlat_reg);

drivers/ntb/hw/amd/ntb_hw_amd.c

157

if (reg_val != addr) {

drivers/ntb/hw/amd/ntb_hw_amd.c

164

reg_val = read64(peer_mmio + limit_reg);

drivers/ntb/hw/amd/ntb_hw_amd.c

165

if (reg_val != limit) {

drivers/ntb/hw/amd/ntb_hw_amd.c

179

reg_val = read64(peer_mmio + xlat_reg);

drivers/ntb/hw/amd/ntb_hw_amd.c

180

if (reg_val != addr) {

drivers/ntb/hw/amd/ntb_hw_amd.c

187

reg_val = readl(peer_mmio + limit_reg);

drivers/ntb/hw/amd/ntb_hw_amd.c

188

if (reg_val != limit) {

drivers/ntb/hw/intel/ntb_hw_gen1.c

1221

u16 reg_val;

drivers/ntb/hw/intel/ntb_hw_gen1.c

1229

XEON_LINK_STATUS_OFFSET, &reg_val);

drivers/ntb/hw/intel/ntb_hw_gen1.c

1233

if (reg_val == ndev->lnk_sta)

drivers/ntb/hw/intel/ntb_hw_gen1.c

1236

ndev->lnk_sta = reg_val;

drivers/ntb/hw/intel/ntb_hw_gen1.c

850

u64 base, limit, reg_val;

drivers/ntb/hw/intel/ntb_hw_gen1.c

894

reg_val = ioread64(mmio + xlat_reg);

drivers/ntb/hw/intel/ntb_hw_gen1.c

895

if (reg_val != addr) {

drivers/ntb/hw/intel/ntb_hw_gen1.c

902

reg_val = ioread64(mmio + limit_reg);

drivers/ntb/hw/intel/ntb_hw_gen1.c

903

if (reg_val != limit) {

drivers/ntb/hw/intel/ntb_hw_gen1.c

925

reg_val = ioread32(mmio + xlat_reg);

drivers/ntb/hw/intel/ntb_hw_gen1.c

926

if (reg_val != addr) {

drivers/ntb/hw/intel/ntb_hw_gen1.c

933

reg_val = ioread32(mmio + limit_reg);

drivers/ntb/hw/intel/ntb_hw_gen1.c

934

if (reg_val != limit) {

drivers/ntb/hw/intel/ntb_hw_gen3.c

103

GEN3_LINK_STATUS_OFFSET, &reg_val);

drivers/ntb/hw/intel/ntb_hw_gen3.c

107

if (reg_val == ndev->lnk_sta)

drivers/ntb/hw/intel/ntb_hw_gen3.c

110

ndev->lnk_sta = reg_val;

drivers/ntb/hw/intel/ntb_hw_gen3.c

453

u64 base, limit, reg_val;

drivers/ntb/hw/intel/ntb_hw_gen3.c

494

reg_val = ioread64(mmio + xlat_reg);

drivers/ntb/hw/intel/ntb_hw_gen3.c

495

if (reg_val != addr) {

drivers/ntb/hw/intel/ntb_hw_gen3.c

500

dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);

drivers/ntb/hw/intel/ntb_hw_gen3.c

504

reg_val = ioread64(mmio + limit_reg);

drivers/ntb/hw/intel/ntb_hw_gen3.c

505

if (reg_val != limit) {

drivers/ntb/hw/intel/ntb_hw_gen3.c

511

dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);

drivers/ntb/hw/intel/ntb_hw_gen3.c

525

reg_val = ioread64(mmio + limit_reg);

drivers/ntb/hw/intel/ntb_hw_gen3.c

526

if (reg_val != limit) {

drivers/ntb/hw/intel/ntb_hw_gen3.c

532

dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);

drivers/ntb/hw/intel/ntb_hw_gen3.c

95

u16 reg_val;

drivers/ntb/hw/intel/ntb_hw_gen4.c

355

u64 base, limit, reg_val;

drivers/ntb/hw/intel/ntb_hw_gen4.c

405

reg_val = ioread64(mmio + xlat_reg);

drivers/ntb/hw/intel/ntb_hw_gen4.c

406

if (reg_val != addr) {

drivers/ntb/hw/intel/ntb_hw_gen4.c

411

dev_dbg(&ntb->pdev->dev, "BAR %d IMXBASE: %#Lx\n", bar, reg_val);

drivers/ntb/hw/intel/ntb_hw_gen4.c

415

reg_val = ioread64(mmio + limit_reg);

drivers/ntb/hw/intel/ntb_hw_gen4.c

416

if (reg_val != limit) {

drivers/ntb/hw/intel/ntb_hw_gen4.c

422

dev_dbg(&ntb->pdev->dev, "BAR %d IMXLMT: %#Lx\n", bar, reg_val);

drivers/ntb/hw/intel/ntb_hw_gen4.c

61

u16 reg_val;

drivers/ntb/hw/intel/ntb_hw_gen4.c

72

reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET);

drivers/ntb/hw/intel/ntb_hw_gen4.c

73

if (reg_val == ndev->lnk_sta)

drivers/ntb/hw/intel/ntb_hw_gen4.c

76

ndev->lnk_sta = reg_val;

drivers/nvmem/sunxi_sid.c

66

u32 reg_val;

drivers/nvmem/sunxi_sid.c

70

reg_val = (offset & SUN8I_SID_OFFSET_MASK)

drivers/nvmem/sunxi_sid.c

72

reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ;

drivers/nvmem/sunxi_sid.c

73

writel(reg_val, sid->base + SUN8I_SID_PRCTL);

drivers/nvmem/sunxi_sid.c

75

ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val,

drivers/nvmem/sunxi_sid.c

76

!(reg_val & SUN8I_SID_READ), 100, 250000);

drivers/pci/controller/dwc/pcie-al.c

125

u8 reg_val;

drivers/pci/controller/dwc/pcie-al.c

227

if (busnr_reg != target_bus_cfg->reg_val) {

drivers/pci/controller/dwc/pcie-al.c

229

target_bus_cfg->reg_val, busnr_reg);

drivers/pci/controller/dwc/pcie-al.c

230

target_bus_cfg->reg_val = busnr_reg;

drivers/pci/controller/dwc/pcie-al.c

232

target_bus_cfg->reg_val,

drivers/pci/controller/dwc/pcie-al.c

275

target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;

drivers/pci/controller/dwc/pcie-al.c

277

al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,

drivers/pci/controller/dwc/pcie-kirin.c

202

u32 reg_val;

drivers/pci/controller/dwc/pcie-kirin.c

204

reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);

drivers/pci/controller/dwc/pcie-kirin.c

205

reg_val &= ~PHY_REF_PAD_BIT;

drivers/pci/controller/dwc/pcie-kirin.c

206

kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);

drivers/pci/controller/dwc/pcie-kirin.c

208

reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0);

drivers/pci/controller/dwc/pcie-kirin.c

209

reg_val &= ~PHY_PWR_DOWN_BIT;

drivers/pci/controller/dwc/pcie-kirin.c

210

kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0);

drivers/pci/controller/dwc/pcie-kirin.c

213

reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);

drivers/pci/controller/dwc/pcie-kirin.c

214

reg_val &= ~PHY_RST_ACK_BIT;

drivers/pci/controller/dwc/pcie-kirin.c

215

kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);

drivers/pci/controller/dwc/pcie-kirin.c

218

reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0);

drivers/pci/controller/dwc/pcie-kirin.c

219

if (reg_val & PIPE_CLK_STABLE)

drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

165

u32 reg_addr, u32 reg_val)

drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

179

put_unaligned_le32(reg_val, &msg_buf[3]);

drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

187

u32 reg_addr, u32 *reg_val)

drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

211

*reg_val = get_unaligned_le32(&rd_data);

drivers/perf/marvell_cn10k_tad_pmu.c

108

reg_val = event_idx & 0xFF;

drivers/perf/marvell_cn10k_tad_pmu.c

109

writeq_relaxed(reg_val, tad_pmu->regions[i].base +

drivers/perf/marvell_cn10k_tad_pmu.c

94

u64 reg_val;

drivers/phy/intel/phy-intel-lgm-combo.c

133

u32 reg_val;

drivers/phy/intel/phy-intel-lgm-combo.c

135

reg_val = readl(base + reg);

drivers/phy/intel/phy-intel-lgm-combo.c

136

reg_val &= ~mask;

drivers/phy/intel/phy-intel-lgm-combo.c

137

reg_val |= val;

drivers/phy/intel/phy-intel-lgm-combo.c

138

writel(reg_val, base + reg);

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

535

seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask);

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

89

u8 reg_val;

drivers/pinctrl/actions/pinctrl-owl.c

60

u32 reg_val;

drivers/pinctrl/actions/pinctrl-owl.c

62

reg_val = readl_relaxed(base);

drivers/pinctrl/actions/pinctrl-owl.c

64

reg_val = (reg_val & ~mask) | (val & mask);

drivers/pinctrl/actions/pinctrl-owl.c

66

writel_relaxed(reg_val, base);

drivers/pinctrl/bcm/pinctrl-bcm281xx.c

1567

static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,

drivers/pinctrl/bcm/pinctrl-bcm281xx.c

1571

*reg_val &= ~param_mask;

drivers/pinctrl/bcm/pinctrl-bcm281xx.c

1572

*reg_val |= (param_val << param_shift) & param_mask;

drivers/pinctrl/cix/pinctrl-sky1-base.c

286

u32 reg_val;

drivers/pinctrl/cix/pinctrl-sky1-base.c

290

reg_val = readl(pin_reg);

drivers/pinctrl/cix/pinctrl-sky1-base.c

291

reg_val &= ~SKY1_MUX_MASK;

drivers/pinctrl/cix/pinctrl-sky1-base.c

292

reg_val |= muxval << SKY1_MUX_SHIFT;

drivers/pinctrl/cix/pinctrl-sky1-base.c

293

writel(reg_val, pin_reg);

drivers/pinctrl/cix/pinctrl-sky1-base.c

296

pin * SKY1_PIN_SIZE, reg_val);

drivers/pinctrl/cix/pinctrl-sky1-base.c

355

u32 reg_val, reg_pullsel = 0;

drivers/pinctrl/cix/pinctrl-sky1-base.c

359

reg_val = readl(pin_reg);

drivers/pinctrl/cix/pinctrl-sky1-base.c

360

reg_val &= ~SKY1_PULLCONF_MASK;

drivers/pinctrl/cix/pinctrl-sky1-base.c

371

reg_val |= reg_pullsel;

drivers/pinctrl/cix/pinctrl-sky1-base.c

372

writel(reg_val, pin_reg);

drivers/pinctrl/cix/pinctrl-sky1-base.c

375

pin * SKY1_PIN_SIZE, reg_val);

drivers/pinctrl/cix/pinctrl-sky1-base.c

392

unsigned int reg_val, val;

drivers/pinctrl/cix/pinctrl-sky1-base.c

399

reg_val = readl(pin_reg);

drivers/pinctrl/cix/pinctrl-sky1-base.c

400

reg_val &= ~SKY1_DS_MASK;

drivers/pinctrl/cix/pinctrl-sky1-base.c

402

reg_val |= (val & SKY1_DS_MASK);

drivers/pinctrl/cix/pinctrl-sky1-base.c

403

writel(reg_val, pin_reg);

drivers/pinctrl/cix/pinctrl-sky1-base.c

406

pin * SKY1_PIN_SIZE, reg_val);

drivers/pinctrl/pinctrl-cy8c95x0.c

728

unsigned int reg_val;

drivers/pinctrl/pinctrl-cy8c95x0.c

731

ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, &reg_val);

drivers/pinctrl/pinctrl-cy8c95x0.c

742

return reg_val ? 1 : 0;

drivers/pinctrl/pinctrl-cy8c95x0.c

761

unsigned int reg_val;

drivers/pinctrl/pinctrl-cy8c95x0.c

764

ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, &reg_val);

drivers/pinctrl/pinctrl-cy8c95x0.c

768

if (reg_val)

drivers/pinctrl/pinctrl-cy8c95x0.c

781

unsigned int reg_val;

drivers/pinctrl/pinctrl-cy8c95x0.c

839

ret = cy8c95x0_regmap_read_bits(chip, reg, port, bit, &reg_val);

drivers/pinctrl/pinctrl-cy8c95x0.c

843

if (reg_val)

drivers/pinctrl/pinctrl-keembay.c

1199

unsigned int reg_val;

drivers/pinctrl/pinctrl-keembay.c

1201

reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin);

drivers/pinctrl/pinctrl-keembay.c

1203

keembay_write_gpio_reg(reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),

drivers/pinctrl/pinctrl-keembay.c

1206

keembay_write_gpio_reg(~reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),

drivers/pinctrl/pinctrl-lpc18xx.c

1001

reg_val = readl(scu->base + reg_offset);

drivers/pinctrl/pinctrl-lpc18xx.c

1002

reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);

drivers/pinctrl/pinctrl-lpc18xx.c

1003

reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);

drivers/pinctrl/pinctrl-lpc18xx.c

1004

writel(reg_val, scu->base + reg_offset);

drivers/pinctrl/pinctrl-lpc18xx.c

736

u32 reg_val;

drivers/pinctrl/pinctrl-lpc18xx.c

739

reg_val = readl(addr);

drivers/pinctrl/pinctrl-lpc18xx.c

741

if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)

drivers/pinctrl/pinctrl-lpc18xx.c

744

reg_val >>= BITS_PER_BYTE;

drivers/pinctrl/pinctrl-lpc18xx.c

987

u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

219

u32 reg_mask, reg_val, tmp_val;

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

239

reg_val = reg->signature_value << __ffs(reg->signature_mask);

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

248

reg_val |= tmp_val;

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

257

reg_val |= tmp_val;

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

266

reg_val |= reg->unlock_val << __ffs(reg->lock_mask);

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

267

r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);

drivers/pinctrl/ti/pinctrl-ti-iodelay.c

271

f_elements, reg_val);

drivers/platform/x86/intel/bytcrc_pwrsrc.c

74

const char * const *info, unsigned int reg_val)

drivers/platform/x86/intel/bytcrc_pwrsrc.c

79

if (reg_val & BIT(i))

drivers/platform/x86/intel/bytcrc_pwrsrc.c

87

unsigned int reg_val;

drivers/platform/x86/intel/bytcrc_pwrsrc.c

90

ret = regmap_read(data->regmap, CRYSTALCOVE_SPWRSRC_REG, &reg_val);

drivers/platform/x86/intel/bytcrc_pwrsrc.c

94

crc_pwrsrc_log(seq, "System powered", pwrsrc_pwrsrc_info, reg_val);

drivers/pmdomain/imx/gpcv2.c

317

u32 reg_val, pgc;

drivers/pmdomain/imx/gpcv2.c

357

domain->regs->pup, reg_val,

drivers/pmdomain/imx/gpcv2.c

358

!(reg_val & domain->bits.pxx),

drivers/pmdomain/imx/gpcv2.c

403

regmap_read_bypassed(domain->regmap, domain->regs->hsk, &reg_val);

drivers/pmdomain/imx/gpcv2.c

427

u32 reg_val, pgc;

drivers/pmdomain/imx/gpcv2.c

445

reg_val,

drivers/pmdomain/imx/gpcv2.c

446

!(reg_val & domain->bits.hskack),

drivers/pmdomain/imx/gpcv2.c

469

domain->regs->pdn, reg_val,

drivers/pmdomain/imx/gpcv2.c

470

!(reg_val & domain->bits.pxx),

drivers/pmdomain/qcom/cpr.c

344

u32 reg_val;

drivers/pmdomain/qcom/cpr.c

346

reg_val = cpr_read(drv, REG_RBCPR_CTL);

drivers/pmdomain/qcom/cpr.c

347

return reg_val & RBCPR_CTL_LOOP_EN;

drivers/pmdomain/qcom/cpr.c

352

u32 reg_val;

drivers/pmdomain/qcom/cpr.c

354

reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);

drivers/pmdomain/qcom/cpr.c

355

return reg_val & RBCPR_RESULT0_BUSY_MASK;

drivers/power/reset/atc260x-poweroff.c

107

reg_val = restart ? ATC2609A_PMU_SYS_CTL0_RESTART_EN : 0;

drivers/power/reset/atc260x-poweroff.c

111

reg_mask, reg_val);

drivers/power/reset/atc260x-poweroff.c

25

uint reg_mask, reg_val;

drivers/power/reset/atc260x-poweroff.c

34

reg_val = ATC2603C_PMU_SYS_CTL0_ONOFF_LONG_WK_EN |

drivers/power/reset/atc260x-poweroff.c

39

ATC2603C_PMU_SYS_CTL0_WK_ALL, reg_val);

drivers/power/reset/atc260x-poweroff.c

56

reg_val = restart ? ATC2603C_PMU_SYS_CTL0_RESTART_EN : 0;

drivers/power/reset/atc260x-poweroff.c

60

reg_mask, reg_val);

drivers/power/reset/atc260x-poweroff.c

76

uint reg_mask, reg_val;

drivers/power/reset/atc260x-poweroff.c

85

reg_val = ATC2609A_PMU_SYS_CTL0_ONOFF_LONG_WK_EN |

drivers/power/reset/atc260x-poweroff.c

90

ATC2609A_PMU_SYS_CTL0_WK_ALL, reg_val);

drivers/power/reset/tdx-ec-poweroff.c

128

u8 reg_val[EC_ID_VERSION_LEN];

drivers/power/reset/tdx-ec-poweroff.c

136

err = regmap_bulk_read(regmap, EC_CHIP_ID_REG, &reg_val, EC_ID_VERSION_LEN);

drivers/power/reset/tdx-ec-poweroff.c

142

reg_val[0], reg_val[1], reg_val[2]);

drivers/power/supply/ab8500_fg.c

533

u8 reg_val;

drivers/power/supply/ab8500_fg.c

540

AB8500_RTC_CC_CONF_REG, &reg_val);

drivers/power/supply/ab8500_fg.c

544

if (!(reg_val & CC_PWR_UP_ENA)) {

drivers/power/supply/axp288_charger.c

155

u8 reg_val;

drivers/power/supply/axp288_charger.c

163

reg_val = (cc - CHRG_CCCV_CC_OFFSET) / CHRG_CCCV_CC_LSB_RES;

drivers/power/supply/axp288_charger.c

164

cc = (reg_val * CHRG_CCCV_CC_LSB_RES) + CHRG_CCCV_CC_OFFSET;

drivers/power/supply/axp288_charger.c

165

reg_val = reg_val << CHRG_CCCV_CC_BIT_POS;

drivers/power/supply/axp288_charger.c

169

CHRG_CCCV_CC_MASK, reg_val);

drivers/power/supply/axp288_charger.c

178

u8 reg_val;

drivers/power/supply/axp288_charger.c

182

reg_val = CHRG_CCCV_CV_4350MV;

drivers/power/supply/axp288_charger.c

185

reg_val = CHRG_CCCV_CV_4200MV;

drivers/power/supply/axp288_charger.c

188

reg_val = CHRG_CCCV_CV_4150MV;

drivers/power/supply/axp288_charger.c

191

reg_val = CHRG_CCCV_CV_4100MV;

drivers/power/supply/axp288_charger.c

195

reg_val = reg_val << CHRG_CCCV_CV_BIT_POS;

drivers/power/supply/axp288_charger.c

199

CHRG_CCCV_CV_MASK, reg_val);

drivers/power/supply/axp288_charger.c

241

u8 reg_val;

drivers/power/supply/axp288_charger.c

244

reg_val = CHRG_VBUS_ILIM_4000MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

246

reg_val = CHRG_VBUS_ILIM_3500MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

248

reg_val = CHRG_VBUS_ILIM_3000MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

250

reg_val = CHRG_VBUS_ILIM_2500MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

252

reg_val = CHRG_VBUS_ILIM_2000MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

254

reg_val = CHRG_VBUS_ILIM_1500MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

256

reg_val = CHRG_VBUS_ILIM_900MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

258

reg_val = CHRG_VBUS_ILIM_500MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

260

reg_val = CHRG_VBUS_ILIM_100MA << CHRG_VBUS_ILIM_BIT_POS;

drivers/power/supply/axp288_charger.c

263

CHRG_VBUS_ILIM_MASK, reg_val);

drivers/power/supply/bq27xxx_battery.c

2059

int reg_val, qv;

drivers/power/supply/bq27xxx_battery.c

2066

reg_val = bq27xxx_read(di, BQ27XXX_REG_PKCFG, true);

drivers/power/supply/bq27xxx_battery.c

2067

if (reg_val < 0) {

drivers/power/supply/bq27xxx_battery.c

2069

return reg_val;

drivers/power/supply/bq27xxx_battery.c

2072

qv = (reg_val >> 5) & 0x3;

drivers/power/supply/cw2015_battery.c

103

ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, &reg_val);

drivers/power/supply/cw2015_battery.c

107

reset_val = reg_val;

drivers/power/supply/cw2015_battery.c

108

if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) {

drivers/power/supply/cw2015_battery.c

122

reg_val |= CW2015_CONFIG_UPDATE_FLG;

drivers/power/supply/cw2015_battery.c

123

reg_val &= ~CW2015_MASK_ATHD;

drivers/power/supply/cw2015_battery.c

124

reg_val |= CW2015_ATHD(cw_bat->alert_level);

drivers/power/supply/cw2015_battery.c

125

ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val);

drivers/power/supply/cw2015_battery.c

131

reg_val = reset_val | CW2015_MODE_RESTART;

drivers/power/supply/cw2015_battery.c

132

ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val);

drivers/power/supply/cw2015_battery.c

146

reg_val, reg_val <= 100,

drivers/power/supply/cw2015_battery.c

160

unsigned int reg_val = CW2015_MODE_SLEEP;

drivers/power/supply/cw2015_battery.c

162

if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) {

drivers/power/supply/cw2015_battery.c

163

reg_val = CW2015_MODE_NORMAL;

drivers/power/supply/cw2015_battery.c

164

ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val);

drivers/power/supply/cw2015_battery.c

169

ret = regmap_read(cw_bat->regmap, CW2015_REG_CONFIG, &reg_val);

drivers/power/supply/cw2015_battery.c

173

if ((reg_val & CW2015_MASK_ATHD) != CW2015_ATHD(cw_bat->alert_level)) {

drivers/power/supply/cw2015_battery.c

175

reg_val &= ~CW2015_MASK_ATHD;

drivers/power/supply/cw2015_battery.c

176

reg_val |= ~CW2015_ATHD(cw_bat->alert_level);

drivers/power/supply/cw2015_battery.c

177

ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val);

drivers/power/supply/cw2015_battery.c

182

ret = regmap_read(cw_bat->regmap, CW2015_REG_CONFIG, &reg_val);

drivers/power/supply/cw2015_battery.c

186

if (!(reg_val & CW2015_CONFIG_UPDATE_FLG)) {

drivers/power/supply/cw2015_battery.c

308

u16 reg_val;

drivers/power/supply/cw2015_battery.c

312

ret = cw_read_word(cw_bat, CW2015_REG_VCELL, &reg_val);

drivers/power/supply/cw2015_battery.c

316

avg += reg_val;

drivers/power/supply/cw2015_battery.c

328

voltage_mv, reg_val);

drivers/power/supply/cw2015_battery.c

424

unsigned int reg_val;

drivers/power/supply/cw2015_battery.c

428

ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, &reg_val);

drivers/power/supply/cw2015_battery.c

432

if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) {

drivers/power/supply/cw2015_battery.c

99

unsigned int reg_val;

drivers/power/supply/intel_dc_ti_battery.c

132

unsigned int reg_val;

drivers/power/supply/intel_dc_ti_battery.c

165

ret = regmap_read(chip->regmap, DC_TI_CC_ACC0_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

169

acc = reg_val;

drivers/power/supply/intel_dc_ti_battery.c

171

ret = regmap_read(chip->regmap, DC_TI_CC_ACC1_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

175

acc |= reg_val << 8;

drivers/power/supply/intel_dc_ti_battery.c

177

ret = regmap_read(chip->regmap, DC_TI_CC_ACC2_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

181

acc |= reg_val << 16;

drivers/power/supply/intel_dc_ti_battery.c

183

ret = regmap_read(chip->regmap, DC_TI_CC_ACC3_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

187

acc |= reg_val << 24;

drivers/power/supply/intel_dc_ti_battery.c

190

ret = regmap_read(chip->regmap, DC_TI_SMPL_CTR0_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

194

smpl_ctr = reg_val;

drivers/power/supply/intel_dc_ti_battery.c

196

ret = regmap_read(chip->regmap, DC_TI_SMPL_CTR1_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

200

smpl_ctr |= reg_val << 8;

drivers/power/supply/intel_dc_ti_battery.c

202

ret = regmap_read(chip->regmap, DC_TI_SMPL_CTR2_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

206

smpl_ctr |= reg_val << 16;

drivers/power/supply/intel_dc_ti_battery.c

239

unsigned int reg_val;

drivers/power/supply/intel_dc_ti_battery.c

257

ret = regmap_read(chip->regmap, DC_TI_PMIC_VERSION_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

261

pmic_version = reg_val;

drivers/power/supply/intel_dc_ti_battery.c

280

ret = regmap_read(chip->regmap, DC_TI_EEPROM_CC_GAIN_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

284

cc_trim_rev = FIELD_GET(CC_TRIM_REVISION, reg_val);

drivers/power/supply/intel_dc_ti_battery.c

294

chip->cc_gain = 1 - (int)FIELD_GET(CC_GAIN_CORRECTION, reg_val);

drivers/power/supply/intel_dc_ti_battery.c

301

ret = regmap_read(chip->regmap, DC_TI_EEPROM_CC_OFFSET_REG, &reg_val);

drivers/power/supply/intel_dc_ti_battery.c

305

chip->cc_offset = (s8)reg_val;

drivers/power/supply/max1720x_battery.c

366

unsigned int reg_val;

drivers/power/supply/max1720x_battery.c

371

ret = max172xx_battery_health(info, &reg_val);

drivers/power/supply/max1720x_battery.c

372

val->intval = reg_val;

drivers/power/supply/max1720x_battery.c

380

ret = regmap_read(info->regmap, MAX172XX_STATUS, &reg_val);

drivers/power/supply/max1720x_battery.c

386

val->intval = !FIELD_GET(MAX172XX_STATUS_BAT_ABSENT, reg_val);

drivers/power/supply/max1720x_battery.c

389

ret = regmap_read(info->regmap, MAX172XX_REPSOC, &reg_val);

drivers/power/supply/max1720x_battery.c

390

val->intval = max172xx_percent_to_ps(reg_val);

drivers/power/supply/max1720x_battery.c

393

ret = regmap_read(info->regmap, MAX172XX_BATT, &reg_val);

drivers/power/supply/max1720x_battery.c

394

val->intval = max172xx_voltage_to_ps(reg_val);

drivers/power/supply/max1720x_battery.c

397

ret = regmap_read(info->regmap, MAX172XX_DESIGN_CAP, &reg_val);

drivers/power/supply/max1720x_battery.c

398

val->intval = max172xx_capacity_to_ps(reg_val, info);

drivers/power/supply/max1720x_battery.c

401

ret = regmap_read(info->regmap, MAX172XX_REPCAP, &reg_val);

drivers/power/supply/max1720x_battery.c

402

val->intval = max172xx_capacity_to_ps(reg_val, info);

drivers/power/supply/max1720x_battery.c

405

ret = regmap_read(info->regmap, MAX172XX_TTE, &reg_val);

drivers/power/supply/max1720x_battery.c

406

val->intval = max172xx_time_to_ps(reg_val);

drivers/power/supply/max1720x_battery.c

409

ret = regmap_read(info->regmap, MAX172XX_TTF, &reg_val);

drivers/power/supply/max1720x_battery.c

410

val->intval = max172xx_time_to_ps(reg_val);

drivers/power/supply/max1720x_battery.c

413

ret = regmap_read(info->regmap, MAX172XX_TEMP, &reg_val);

drivers/power/supply/max1720x_battery.c

414

val->intval = max172xx_temperature_to_ps(reg_val);

drivers/power/supply/max1720x_battery.c

417

ret = regmap_read(info->regmap, MAX172XX_CURRENT, &reg_val);

drivers/power/supply/max1720x_battery.c

418

val->intval = max172xx_current_to_voltage(reg_val) / info->rsense;

drivers/power/supply/max1720x_battery.c

421

ret = regmap_read(info->regmap, MAX172XX_AVG_CURRENT, &reg_val);

drivers/power/supply/max1720x_battery.c

422

val->intval = max172xx_current_to_voltage(reg_val) / info->rsense;

drivers/power/supply/max1720x_battery.c

425

ret = regmap_read(info->regmap, MAX172XX_FULL_CAP, &reg_val);

drivers/power/supply/max1720x_battery.c

426

val->intval = max172xx_capacity_to_ps(reg_val, info);

drivers/power/supply/max1720x_battery.c

429

ret = regmap_read(info->regmap, MAX172XX_DEV_NAME, &reg_val);

drivers/power/supply/max1720x_battery.c

432

reg_val = FIELD_GET(MAX172XX_DEV_NAME_TYPE_MASK, reg_val);

drivers/power/supply/max1720x_battery.c

433

if (reg_val == MAX172XX_DEV_NAME_TYPE_MAX17201)

drivers/power/supply/max1720x_battery.c

435

else if (reg_val == MAX172XX_DEV_NAME_TYPE_MAX17205)

drivers/power/supply/mt6370-charger.c

182

unsigned int reg_val;

drivers/power/supply/mt6370-charger.c

184

ret = regmap_field_read(priv->rmap_fields[fd], &reg_val);

drivers/power/supply/mt6370-charger.c

190

reg_val, val);

drivers/power/supply/mt6370-charger.c

192

*val = reg_val;

drivers/power/supply/rt9467-charger.c

415

unsigned int adc_stat, reg_val, adc_sel;

drivers/power/supply/rt9467-charger.c

431

reg_val = RT9467_MASK_ADC_START | FIELD_PREP(RT9467_MASK_ADC_IN_SEL, adc_sel);

drivers/power/supply/rt9467-charger.c

432

ret = regmap_write(data->regmap, RT9467_REG_CHG_ADC, reg_val);

drivers/power/supply/wm831x_power.c

177

int reg_val;

drivers/power/supply/wm831x_power.c

257

*reg |= map[i].reg_val;

drivers/ptp/ptp_dte.c

279

ptp_dte->reg_val[i] =

drivers/ptp/ptp_dte.c

296

writel(ptp_dte->reg_val[i],

drivers/ptp/ptp_dte.c

299

writel(((ptp_dte->reg_val[i] &

drivers/ptp/ptp_dte.c

49

u32 reg_val[DTE_NUM_REGS_TO_RESTORE];

drivers/rapidio/rio.c

1348

u32 reg_val;

drivers/rapidio/rio.c

1353

&reg_val);

drivers/rapidio/rio.c

1356

RIO_ASM_INFO_CAR, &reg_val);

drivers/rapidio/rio.c

1357

return reg_val & RIO_EXT_FTR_PTR_MASK;

drivers/rapidio/rio.c

1360

rio_local_read_config_32(port, from, &reg_val);

drivers/rapidio/rio.c

1363

from, &reg_val);

drivers/rapidio/rio.c

1364

return RIO_GET_BLOCK_ID(reg_val);

drivers/regulator/da903x-regulator.c

157

uint8_t reg_val;

drivers/regulator/da903x-regulator.c

160

ret = da903x_read(da9034_dev, info->enable_reg, &reg_val);

drivers/regulator/da903x-regulator.c

164

return !!(reg_val & (1 << info->enable_bit));

drivers/regulator/da9052-regulator.c

115

int reg_val = 0;

drivers/regulator/da9052-regulator.c

127

reg_val = i;

drivers/regulator/da9052-regulator.c

142

reg_val << 2);

drivers/regulator/da9052-regulator.c

147

reg_val << 6);

drivers/regulator/da9211-regulator.c

342

int reg_val, err, ret = IRQ_NONE;

drivers/regulator/da9211-regulator.c

344

err = regmap_read(chip->regmap, DA9211_REG_EVENT_B, &reg_val);

drivers/regulator/da9211-regulator.c

348

if (reg_val & DA9211_E_OV_CURR_A) {

drivers/regulator/da9211-regulator.c

360

if (reg_val & DA9211_E_OV_CURR_B) {

drivers/regulator/hi6421-regulator.c

388

unsigned int reg_val;

drivers/regulator/hi6421-regulator.c

391

regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);

drivers/regulator/hi6421-regulator.c

392

if (reg_val & info->mode_mask)

drivers/regulator/hi6421-regulator.c

401

unsigned int reg_val;

drivers/regulator/hi6421-regulator.c

404

regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);

drivers/regulator/hi6421-regulator.c

405

if (reg_val & info->mode_mask)

drivers/regulator/hi6421v530-regulator.c

111

unsigned int reg_val;

drivers/regulator/hi6421v530-regulator.c

114

regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);

drivers/regulator/hi6421v530-regulator.c

116

if (reg_val & (info->mode_mask))

drivers/regulator/hi6421v600-regulator.c

122

unsigned int reg_val;

drivers/regulator/hi6421v600-regulator.c

125

regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);

drivers/regulator/hi6421v600-regulator.c

127

if (reg_val & sreg->eco_mode_mask)

drivers/regulator/max8660.c

80

u8 reg_val = (max8660->shadow_regs[reg] & mask) | val;

drivers/regulator/max8660.c

83

max8660_addresses[reg], reg_val);

drivers/regulator/max8660.c

86

max8660_addresses[reg], reg_val);

drivers/regulator/max8660.c

88

max8660->shadow_regs[reg] = reg_val;

drivers/regulator/pv88060-regulator.c

228

int i, reg_val, err, ret = IRQ_NONE;

drivers/regulator/pv88060-regulator.c

230

err = regmap_read(chip->regmap, PV88060_REG_EVENT_A, &reg_val);

drivers/regulator/pv88060-regulator.c

234

if (reg_val & PV88060_E_VDD_FLT) {

drivers/regulator/pv88060-regulator.c

250

if (reg_val & PV88060_E_OVER_TEMP) {

drivers/regulator/pv88080-regulator.c

315

int i, reg_val, err, ret = IRQ_NONE;

drivers/regulator/pv88080-regulator.c

317

err = regmap_read(chip->regmap, PV88080_REG_EVENT_A, &reg_val);

drivers/regulator/pv88080-regulator.c

321

if (reg_val & PV88080_E_VDD_FLT) {

drivers/regulator/pv88080-regulator.c

337

if (reg_val & PV88080_E_OVER_TEMP) {

drivers/regulator/pv88090-regulator.c

221

int i, reg_val, err, ret = IRQ_NONE;

drivers/regulator/pv88090-regulator.c

223

err = regmap_read(chip->regmap, PV88090_REG_EVENT_A, &reg_val);

drivers/regulator/pv88090-regulator.c

227

if (reg_val & PV88090_E_VDD_FLT) {

drivers/regulator/pv88090-regulator.c

243

if (reg_val & PV88090_E_OVER_TEMP) {

drivers/regulator/tps65910-regulator.c

929

u8 reg_val = srvsel & VDD1_OP_SEL_MASK;

drivers/regulator/tps65910-regulator.c

931

ret = regmap_write(mfd->regmap, op_reg_add, reg_val);

drivers/remoteproc/pru_rproc.c

440

u32 reg_val;

drivers/remoteproc/pru_rproc.c

446

reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL);

drivers/remoteproc/pru_rproc.c

449

pru->dbg_continuous = reg_val;

drivers/remoteproc/pru_rproc.c

452

reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN;

drivers/remoteproc/pru_rproc.c

454

reg_val = pru->dbg_continuous;

drivers/remoteproc/pru_rproc.c

457

pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val);

drivers/rtc/rtc-amlogic-a4.c

186

u32 reg_val;

drivers/rtc/rtc-amlogic-a4.c

194

regmap_read(rtc->map, RTC_SEC_ADJUST_REG, &reg_val);

drivers/rtc/rtc-amlogic-a4.c

195

enable = FIELD_GET(RTC_ADJ_VALID, reg_val);

drivers/rtc/rtc-amlogic-a4.c

199

sign = FIELD_GET(RTC_SEC_ADJUST_CTRL, reg_val);

drivers/rtc/rtc-amlogic-a4.c

200

match_counter = FIELD_GET(RTC_MATCH_COUNTER, reg_val);

drivers/rtc/rtc-amlogic-a4.c

216

u32 reg_val;

drivers/rtc/rtc-amlogic-a4.c

230

reg_val = FIELD_PREP(RTC_ADJ_VALID, enable) |

drivers/rtc/rtc-amlogic-a4.c

233

regmap_write(rtc->map, RTC_SEC_ADJUST_REG, reg_val);

drivers/rtc/rtc-amlogic-a4.c

281

u32 reg_val = 0;

drivers/rtc/rtc-amlogic-a4.c

294

reg_val = FIELD_PREP(RTC_OSCIN_IN_EN, 1)

drivers/rtc/rtc-amlogic-a4.c

300

| RTC_OSCIN_OUT_N1M1, reg_val);

drivers/rtc/rtc-amlogic-a4.c

303

reg_val = FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_M0)

drivers/rtc/rtc-amlogic-a4.c

306

| RTC_OSCIN_OUT_N1M1, reg_val);

drivers/rtc/rtc-isl12022.c

396

unsigned int reg_mask, reg_val;

drivers/rtc/rtc-isl12022.c

410

reg_val = ISL12022_INT_ARST | ISL12022_INT_FO_OFF;

drivers/rtc/rtc-isl12022.c

412

reg_mask, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

540

u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

542

reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

543

hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

547

reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

548

reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

549

hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1331

int i, reg_val;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1337

reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1338

if (!(reg_val & BIT(0))) {

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1352

int i, reg_val;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1354

reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1355

for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1359

if (reg_val & BIT(i)) {

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

3098

u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

3099

u32 dev_id = reg_val & ITCT_DEV_MSK;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

980

u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

987

if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

993

reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

994

hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2219

u32 reg_val;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2221

reg_val = hisi_sas_read32(hisi_hba,

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2224

reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2226

AM_CTRL_GLOBAL, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2233

u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2234

u32 dev_id = reg_val & ITCT_DEV_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2750

u32 status, reg_val;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2760

reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2762

reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

2764

AM_CTRL_GLOBAL, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3235

u32 reg_val;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3248

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3249

reg_val |= CFG_ALOS_CHK_DISABLE_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3250

hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3255

u32 reg_val;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3259

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3260

reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3262

hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3265

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3266

reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3267

hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3270

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3272

reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3273

reg_val |= (SAS_LINK_RATE_1_5_GBPS << CFG_PROG_OOB_PHY_LINK_RATE_OFF);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3274

hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3287

u32 reg_val, mode_tmp;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3310

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3312

reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3313

reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3315

reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3318

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3320

reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3323

reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3327

reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3331

reg_val = hisi_hba->debugfs_bist_fixed_code[0];

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3333

SAS_PHY_BIST_CODE, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3335

reg_val = hisi_hba->debugfs_bist_fixed_code[1];

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3337

SAS_PHY_BIST_CODE1, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3348

reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

3350

reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4457

u32 reg_val;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4465

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4467

reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4470

reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4474

reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4477

hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4489

reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4490

reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

4491

hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

5158

u32 reg_val;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

5164

reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

5166

reg_val &= ~AM_CTRL_SHUTDOWN_REQ_MSK;

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

5168

AM_CTRL_GLOBAL, reg_val);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

927

u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

933

if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

938

reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

939

hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);

drivers/scsi/lpfc/lpfc_attr.c

1828

uint32_t reg_val;

drivers/scsi/lpfc/lpfc_attr.c

1863

reg_val = readl(phba->sli4_hba.conf_regs_memmap_p +

drivers/scsi/lpfc/lpfc_attr.c

1867

reg_val |= LPFC_FW_DUMP_REQUEST;

drivers/scsi/lpfc/lpfc_attr.c

1869

reg_val |= LPFC_CTL_PDEV_CTL_FRST;

drivers/scsi/lpfc/lpfc_attr.c

1871

reg_val |= LPFC_CTL_PDEV_CTL_DRST;

drivers/scsi/lpfc/lpfc_attr.c

1873

writel(reg_val, phba->sli4_hba.conf_regs_memmap_p +

drivers/scsi/lpfc/lpfc_attr.c

1885

"access: x%x\n", reg_val);

drivers/scsi/lpfc/lpfc_attr.c

1890

"access: x%x\n", reg_val);

drivers/scsi/lpfc/lpfc_debugfs.c

4719

uint32_t drb_reg_id, value, reg_val = 0;

drivers/scsi/lpfc/lpfc_debugfs.c

4775

reg_val = value;

drivers/scsi/lpfc/lpfc_debugfs.c

4777

reg_val = readl(drb_reg);

drivers/scsi/lpfc/lpfc_debugfs.c

4778

reg_val |= value;

drivers/scsi/lpfc/lpfc_debugfs.c

4781

reg_val = readl(drb_reg);

drivers/scsi/lpfc/lpfc_debugfs.c

4782

reg_val &= ~value;

drivers/scsi/lpfc/lpfc_debugfs.c

4784

writel(reg_val, drb_reg);

drivers/scsi/lpfc/lpfc_debugfs.c

4934

uint32_t ctl_reg_id, value, reg_val = 0;

drivers/scsi/lpfc/lpfc_debugfs.c

4999

reg_val = value;

drivers/scsi/lpfc/lpfc_debugfs.c

5001

reg_val = readl(ctl_reg);

drivers/scsi/lpfc/lpfc_debugfs.c

5002

reg_val |= value;

drivers/scsi/lpfc/lpfc_debugfs.c

5005

reg_val = readl(ctl_reg);

drivers/scsi/lpfc/lpfc_debugfs.c

5006

reg_val &= ~value;

drivers/scsi/lpfc/lpfc_debugfs.c

5008

writel(reg_val, ctl_reg);

drivers/scsi/pm8001/pm80xx_hwi.c

314

reg_val = pm8001_mr32(fatal_table_address,

drivers/scsi/pm8001/pm80xx_hwi.c

316

} while ((reg_val) && time_before(jiffies, start));

drivers/scsi/pm8001/pm80xx_hwi.c

318

if (reg_val != 0) {

drivers/scsi/pm8001/pm80xx_hwi.c

321

reg_val);

drivers/scsi/pm8001/pm80xx_hwi.c

337

reg_val = pm8001_mr32(fatal_table_address,

drivers/scsi/pm8001/pm80xx_hwi.c

339

} while (((reg_val != 2) && (reg_val != 3)) &&

drivers/scsi/pm8001/pm80xx_hwi.c

342

if (reg_val < 2) {

drivers/scsi/pm8001/pm80xx_hwi.c

345

reg_val);

drivers/scsi/pm8001/pm80xx_hwi.c

396

u32 reg_val = 0;

drivers/scsi/pm8001/pm80xx_hwi.c

465

reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &

drivers/scsi/pm8001/pm80xx_hwi.c

467

} while ((reg_val != 0) && time_before(jiffies, start));

drivers/scsi/pm8001/pm80xx_hwi.c

475

reg_val = pm8001_mr32(nonfatal_table_address,

drivers/scsi/pm8001/pm80xx_hwi.c

477

} while ((!reg_val) && time_before(jiffies, start));

drivers/scsi/pm8001/pm80xx_hwi.c

479

if ((reg_val == 0x00) ||

drivers/scsi/pm8001/pm80xx_hwi.c

480

(reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||

drivers/scsi/pm8001/pm80xx_hwi.c

481

(reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {

drivers/scsi/pm8001/pm80xx_hwi.c

486

} else if (reg_val ==

drivers/scsi/pm8001/pm80xx_hwi.c

489

} else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||

drivers/scsi/pm8001/pm80xx_hwi.c

53

u32 reg_val;

drivers/scsi/pm8001/pm80xx_hwi.c

59

reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);

drivers/scsi/pm8001/pm80xx_hwi.c

60

} while ((reg_val != shift_value) && time_before(jiffies, start));

drivers/scsi/pm8001/pm80xx_hwi.c

61

if (reg_val != shift_value) {

drivers/scsi/pm8001/pm80xx_hwi.c

63

reg_val);

drivers/scsi/pm8001/pm80xx_hwi.c

92

u32 accum_len, reg_val, index, *temp;

drivers/scsi/qla2xxx/qla_mr.c

530

uint32_t reg_val;

drivers/scsi/qla2xxx/qla_mr.c

544

reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);

drivers/scsi/qla2xxx/qla_mr.c

545

reg_val &= ~(1<<12);

drivers/scsi/qla2xxx/qla_mr.c

546

QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);

drivers/scsi/qla2xxx/qla_mr.c

548

reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);

drivers/scsi/qla2xxx/qla_mr.c

549

reg_val &= ~(1<<12);

drivers/scsi/qla2xxx/qla_mr.c

550

QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);

drivers/scsi/qla2xxx/qla_mr.c

552

reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);

drivers/scsi/qla2xxx/qla_mr.c

553

reg_val &= ~(1<<12);

drivers/scsi/qla2xxx/qla_mr.c

554

QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);

drivers/scsi/qla2xxx/qla_mr.c

556

reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);

drivers/scsi/qla2xxx/qla_mr.c

557

reg_val &= ~(1<<12);

drivers/scsi/qla2xxx/qla_mr.c

558

QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);

drivers/scsi/qla4xxx/ql4_os.c

302

u32 reg_val = 0;

drivers/scsi/qla4xxx/ql4_os.c

306

reg_val = readl(&ha->qla4_82xx_reg->host_status);

drivers/scsi/qla4xxx/ql4_os.c

308

reg_val = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);

drivers/scsi/qla4xxx/ql4_os.c

310

reg_val = readw(&ha->reg->ctrl_status);

drivers/scsi/qla4xxx/ql4_os.c

312

if (reg_val == QL4_ISP_REG_DISCONNECT)

drivers/soc/fsl/rcpm.c

32

u32 reg_val;

drivers/soc/fsl/rcpm.c

43

reg_val = ioread32be(regs + SCFG_SPARECR8);

drivers/soc/fsl/rcpm.c

44

iowrite32be(val | reg_val, regs + SCFG_SPARECR8);

drivers/soc/sunxi/sunxi_sram.c

149

func->reg_val == val ?

drivers/soc/sunxi/sunxi_sram.c

204

*reg_value = func->reg_val;

drivers/soc/sunxi/sunxi_sram.c

28

u32 reg_val;

drivers/soc/sunxi/sunxi_sram.c

48

.reg_val = _reg_val, \

drivers/soc/ti/smartreflex.c

47

u32 reg_val;

drivers/soc/ti/smartreflex.c

63

reg_val = __raw_readl(sr->base + offset);

drivers/soc/ti/smartreflex.c

64

reg_val &= ~mask;

drivers/soc/ti/smartreflex.c

68

reg_val |= value;

drivers/soc/ti/smartreflex.c

70

__raw_writel(reg_val, (sr->base + offset));

drivers/soundwire/qcom.c

1509

int reg, reg_val, ret;

drivers/soundwire/qcom.c

1521

ctrl->reg_read(ctrl, reg, &reg_val);

drivers/soundwire/qcom.c

1522

seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);

drivers/spi/spi-axiado.c

558

u32 reg_val;

drivers/spi/spi-axiado.c

608

reg_val = ax_spi_read(xspi, AX_SPI_CR2);

drivers/spi/spi-axiado.c

609

reg_val |= AX_SPI_CR2_SWD | AX_SPI_CR2_SRI | AX_SPI_CR2_SRD;

drivers/spi/spi-axiado.c

610

ax_spi_write(xspi, AX_SPI_CR2, reg_val);

drivers/spi/spi-axiado.c

628

reg_val = ax_spi_read(xspi, AX_SPI_CR2);

drivers/spi/spi-axiado.c

629

reg_val |= AX_SPI_CR2_HTE;

drivers/spi/spi-axiado.c

630

ax_spi_write(xspi, AX_SPI_CR2, reg_val);

drivers/spi/spi-mt65xx.c

1001

u32 reg_val, nio, tx_size;

drivers/spi/spi-mt65xx.c

1012

reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);

drivers/spi/spi-mt65xx.c

1014

reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;

drivers/spi/spi-mt65xx.c

1015

reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;

drivers/spi/spi-mt65xx.c

1018

reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;

drivers/spi/spi-mt65xx.c

1020

reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<

drivers/spi/spi-mt65xx.c

1025

reg_val |= SPI_CFG3_IPM_NODATA_FLAG;

drivers/spi/spi-mt65xx.c

1028

reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;

drivers/spi/spi-mt65xx.c

1035

reg_val |= SPI_CFG3_IPM_XMODE_EN;

drivers/spi/spi-mt65xx.c

1037

reg_val &= ~SPI_CFG3_IPM_XMODE_EN;

drivers/spi/spi-mt65xx.c

1051

reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;

drivers/spi/spi-mt65xx.c

1052

reg_val |= PIN_MODE_CFG(nio);

drivers/spi/spi-mt65xx.c

1054

reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;

drivers/spi/spi-mt65xx.c

1056

reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;

drivers/spi/spi-mt65xx.c

1058

reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;

drivers/spi/spi-mt65xx.c

1059

writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);

drivers/spi/spi-mt65xx.c

1122

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

1123

reg_val |= SPI_CMD_TX_DMA;

drivers/spi/spi-mt65xx.c

1125

reg_val |= SPI_CMD_RX_DMA;

drivers/spi/spi-mt65xx.c

1126

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

1138

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

1139

reg_val &= ~SPI_CMD_TX_DMA;

drivers/spi/spi-mt65xx.c

1141

reg_val &= ~SPI_CMD_RX_DMA;

drivers/spi/spi-mt65xx.c

1142

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

286

u32 reg_val;

drivers/spi/spi-mt65xx.c

289

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

290

reg_val |= SPI_CMD_RST;

drivers/spi/spi-mt65xx.c

291

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

293

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

294

reg_val &= ~SPI_CMD_RST;

drivers/spi/spi-mt65xx.c

295

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

305

u32 reg_val;

drivers/spi/spi-mt65xx.c

324

reg_val = readl(mdata->base + SPI_CFG0_REG);

drivers/spi/spi-mt65xx.c

328

reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);

drivers/spi/spi-mt65xx.c

329

reg_val |= (((hold - 1) & 0xffff)

drivers/spi/spi-mt65xx.c

334

reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);

drivers/spi/spi-mt65xx.c

335

reg_val |= (((setup - 1) & 0xffff)

drivers/spi/spi-mt65xx.c

341

reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);

drivers/spi/spi-mt65xx.c

342

reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);

drivers/spi/spi-mt65xx.c

346

reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);

drivers/spi/spi-mt65xx.c

347

reg_val |= (((setup - 1) & 0xff)

drivers/spi/spi-mt65xx.c

351

writel(reg_val, mdata->base + SPI_CFG0_REG);

drivers/spi/spi-mt65xx.c

356

reg_val = readl(mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

357

reg_val &= ~SPI_CFG1_CS_IDLE_MASK;

drivers/spi/spi-mt65xx.c

358

reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);

drivers/spi/spi-mt65xx.c

359

writel(reg_val, mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

369

u32 reg_val;

drivers/spi/spi-mt65xx.c

377

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

380

reg_val |= SPI_CMD_IPM_NONIDLE_MODE;

drivers/spi/spi-mt65xx.c

382

reg_val |= SPI_CMD_IPM_SPIM_LOOP;

drivers/spi/spi-mt65xx.c

384

reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;

drivers/spi/spi-mt65xx.c

388

reg_val |= SPI_CMD_CPHA;

drivers/spi/spi-mt65xx.c

390

reg_val &= ~SPI_CMD_CPHA;

drivers/spi/spi-mt65xx.c

392

reg_val |= SPI_CMD_CPOL;

drivers/spi/spi-mt65xx.c

394

reg_val &= ~SPI_CMD_CPOL;

drivers/spi/spi-mt65xx.c

398

reg_val &= ~SPI_CMD_TXMSBF;

drivers/spi/spi-mt65xx.c

399

reg_val &= ~SPI_CMD_RXMSBF;

drivers/spi/spi-mt65xx.c

401

reg_val |= SPI_CMD_TXMSBF;

drivers/spi/spi-mt65xx.c

402

reg_val |= SPI_CMD_RXMSBF;

drivers/spi/spi-mt65xx.c

407

reg_val &= ~SPI_CMD_TX_ENDIAN;

drivers/spi/spi-mt65xx.c

408

reg_val &= ~SPI_CMD_RX_ENDIAN;

drivers/spi/spi-mt65xx.c

410

reg_val |= SPI_CMD_TX_ENDIAN;

drivers/spi/spi-mt65xx.c

411

reg_val |= SPI_CMD_RX_ENDIAN;

drivers/spi/spi-mt65xx.c

417

reg_val |= SPI_CMD_CS_POL;

drivers/spi/spi-mt65xx.c

419

reg_val &= ~SPI_CMD_CS_POL;

drivers/spi/spi-mt65xx.c

422

reg_val |= SPI_CMD_SAMPLE_SEL;

drivers/spi/spi-mt65xx.c

424

reg_val &= ~SPI_CMD_SAMPLE_SEL;

drivers/spi/spi-mt65xx.c

428

reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;

drivers/spi/spi-mt65xx.c

431

reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);

drivers/spi/spi-mt65xx.c

434

reg_val &= ~SPI_CMD_DEASSERT;

drivers/spi/spi-mt65xx.c

436

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

446

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

447

reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;

drivers/spi/spi-mt65xx.c

448

reg_val |= ((chip_config->tick_delay & 0x7)

drivers/spi/spi-mt65xx.c

450

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

452

reg_val = readl(mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

453

reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;

drivers/spi/spi-mt65xx.c

454

reg_val |= ((chip_config->tick_delay & 0x7)

drivers/spi/spi-mt65xx.c

456

writel(reg_val, mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

459

reg_val = readl(mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

460

reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;

drivers/spi/spi-mt65xx.c

461

reg_val |= ((chip_config->tick_delay & 0x3)

drivers/spi/spi-mt65xx.c

463

writel(reg_val, mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

488

u32 reg_val;

drivers/spi/spi-mt65xx.c

494

reg_val = readl(mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

496

reg_val |= SPI_CMD_PAUSE_EN;

drivers/spi/spi-mt65xx.c

497

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

499

reg_val &= ~SPI_CMD_PAUSE_EN;

drivers/spi/spi-mt65xx.c

500

writel(reg_val, mdata->base + SPI_CMD_REG);

drivers/spi/spi-mt65xx.c

509

u32 div, sck_time, reg_val;

drivers/spi/spi-mt65xx.c

520

reg_val = readl(mdata->base + SPI_CFG2_REG);

drivers/spi/spi-mt65xx.c

521

reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);

drivers/spi/spi-mt65xx.c

522

reg_val |= (((sck_time - 1) & 0xffff)

drivers/spi/spi-mt65xx.c

524

reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);

drivers/spi/spi-mt65xx.c

525

reg_val |= (((sck_time - 1) & 0xffff)

drivers/spi/spi-mt65xx.c

527

writel(reg_val, mdata->base + SPI_CFG2_REG);

drivers/spi/spi-mt65xx.c

529

reg_val = readl(mdata->base + SPI_CFG0_REG);

drivers/spi/spi-mt65xx.c

530

reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);

drivers/spi/spi-mt65xx.c

531

reg_val |= (((sck_time - 1) & 0xff)

drivers/spi/spi-mt65xx.c

533

reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);

drivers/spi/spi-mt65xx.c

534

reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);

drivers/spi/spi-mt65xx.c

535

writel(reg_val, mdata->base + SPI_CFG0_REG);

drivers/spi/spi-mt65xx.c

541

u32 packet_size, packet_loop, reg_val;

drivers/spi/spi-mt65xx.c

555

reg_val = readl(mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

557

reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;

drivers/spi/spi-mt65xx.c

559

reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;

drivers/spi/spi-mt65xx.c

560

reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;

drivers/spi/spi-mt65xx.c

561

reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;

drivers/spi/spi-mt65xx.c

562

reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;

drivers/spi/spi-mt65xx.c

563

writel(reg_val, mdata->base + SPI_CFG1_REG);

drivers/spi/spi-mt65xx.c

669

u32 reg_val;

drivers/spi/spi-mt65xx.c

683

reg_val = 0;

drivers/spi/spi-mt65xx.c

684

memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);

drivers/spi/spi-mt65xx.c

685

writel(reg_val, mdata->base + SPI_TX_DATA_REG);

drivers/spi/spi-mt65xx.c

744

u32 reg_val = 0;

drivers/spi/spi-mt65xx.c

749

reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_EN;

drivers/spi/spi-mt65xx.c

751

reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;

drivers/spi/spi-mt65xx.c

752

reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;

drivers/spi/spi-mt65xx.c

753

reg_val |= mtk_spi_set_nbit(xfer->tx_nbits);

drivers/spi/spi-mt65xx.c

755

reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;

drivers/spi/spi-mt65xx.c

756

reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;

drivers/spi/spi-mt65xx.c

757

reg_val |= mtk_spi_set_nbit(xfer->rx_nbits);

drivers/spi/spi-mt65xx.c

759

writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);

drivers/spi/spi-mt65xx.c

794

u32 cmd, reg_val, cnt, remainder, len;

drivers/spi/spi-mt65xx.c

806

reg_val = readl(mdata->base + SPI_RX_DATA_REG);

drivers/spi/spi-mt65xx.c

808

&reg_val,

drivers/spi/spi-mt65xx.c

830

reg_val = 0;

drivers/spi/spi-mt65xx.c

831

memcpy(&reg_val,

drivers/spi/spi-mt65xx.c

834

writel(reg_val, mdata->base + SPI_TX_DATA_REG);

drivers/spi/spi-mt65xx.c

886

u32 reg_val;

drivers/spi/spi-mt65xx.c

888

reg_val = readl(mdata->base + SPI_STATUS0_REG);

drivers/spi/spi-mt65xx.c

889

if (reg_val & MTK_SPI_PAUSE_INT_STATUS)

drivers/spi/spi-slave-mt27xx.c

100

u32 reg_val;

drivers/spi/spi-slave-mt27xx.c

102

reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

103

reg_val &= ~RX_DMA_EN;

drivers/spi/spi-slave-mt27xx.c

104

reg_val &= ~TX_DMA_EN;

drivers/spi/spi-slave-mt27xx.c

105

writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

110

u32 reg_val;

drivers/spi/spi-slave-mt27xx.c

112

reg_val = readl(mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

113

reg_val &= ~SPIS_TX_EN;

drivers/spi/spi-slave-mt27xx.c

114

reg_val &= ~SPIS_RX_EN;

drivers/spi/spi-slave-mt27xx.c

115

writel(reg_val, mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

135

u32 reg_val;

drivers/spi/spi-slave-mt27xx.c

140

reg_val = readl(mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

142

reg_val |= SPIS_CPHA;

drivers/spi/spi-slave-mt27xx.c

144

reg_val &= ~SPIS_CPHA;

drivers/spi/spi-slave-mt27xx.c

146

reg_val |= SPIS_CPOL;

drivers/spi/spi-slave-mt27xx.c

148

reg_val &= ~SPIS_CPOL;

drivers/spi/spi-slave-mt27xx.c

151

reg_val &= ~(SPIS_TXMSBF | SPIS_RXMSBF);

drivers/spi/spi-slave-mt27xx.c

153

reg_val |= SPIS_TXMSBF | SPIS_RXMSBF;

drivers/spi/spi-slave-mt27xx.c

155

reg_val &= ~SPIS_TX_ENDIAN;

drivers/spi/spi-slave-mt27xx.c

156

reg_val &= ~SPIS_RX_ENDIAN;

drivers/spi/spi-slave-mt27xx.c

157

writel(reg_val, mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

167

int reg_val, cnt, remainder, ret;

drivers/spi/spi-slave-mt27xx.c

171

reg_val = readl(mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

173

reg_val |= SPIS_RX_EN;

drivers/spi/spi-slave-mt27xx.c

175

reg_val |= SPIS_TX_EN;

drivers/spi/spi-slave-mt27xx.c

176

writel(reg_val, mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

185

reg_val = 0;

drivers/spi/spi-slave-mt27xx.c

186

memcpy(&reg_val, xfer->tx_buf + cnt * 4, remainder);

drivers/spi/spi-slave-mt27xx.c

187

writel(reg_val, mdata->base + SPIS_TX_DATA_REG);

drivers/spi/spi-slave-mt27xx.c

205

int reg_val, ret;

drivers/spi/spi-slave-mt27xx.c

238

reg_val = readl(mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

240

reg_val |= SPIS_TX_EN;

drivers/spi/spi-slave-mt27xx.c

242

reg_val |= SPIS_RX_EN;

drivers/spi/spi-slave-mt27xx.c

243

writel(reg_val, mdata->base + SPIS_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

246

reg_val = 0;

drivers/spi/spi-slave-mt27xx.c

247

reg_val |= (xfer->len - 1) & TX_DMA_LEN;

drivers/spi/spi-slave-mt27xx.c

248

writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

250

reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

252

reg_val |= TX_DMA_EN;

drivers/spi/spi-slave-mt27xx.c

254

reg_val |= RX_DMA_EN;

drivers/spi/spi-slave-mt27xx.c

255

reg_val |= TX_DMA_TRIG_EN;

drivers/spi/spi-slave-mt27xx.c

256

writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);

drivers/spi/spi-slave-mt27xx.c

301

u32 reg_val;

drivers/spi/spi-slave-mt27xx.c

303

reg_val = DMA_DONE_EN | DATA_DONE_EN |

drivers/spi/spi-slave-mt27xx.c

305

writel(reg_val, mdata->base + SPIS_IRQ_EN_REG);

drivers/spi/spi-slave-mt27xx.c

307

reg_val = DMA_DONE_MASK | DATA_DONE_MASK |

drivers/spi/spi-slave-mt27xx.c

309

writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG);

drivers/spi/spi-slave-mt27xx.c

332

u32 int_status, reg_val, cnt, remainder;

drivers/spi/spi-slave-mt27xx.c

365

reg_val = readl(mdata->base + SPIS_RX_DATA_REG);

drivers/spi/spi-slave-mt27xx.c

367

&reg_val, remainder);

drivers/staging/media/ipu7/ipu7-buttress.c

767

u32 reg_val;

drivers/staging/media/ipu7/ipu7-buttress.c

777

reg_val = readl(isp->base + BUTTRESS_REG_IS_WORKPOINT_REQ);

drivers/staging/media/ipu7/ipu7-buttress.c

782

*freq = (reg_val & BUTTRESS_IS_FREQ_CTL_RATIO_MASK) * 25;

drivers/staging/media/ipu7/ipu7-buttress.c

784

*freq = (reg_val & BUTTRESS_IS_FREQ_CTL_RATIO_MASK) * 50 / 3;

drivers/staging/media/ipu7/ipu7-buttress.c

792

u32 reg_val;

drivers/staging/media/ipu7/ipu7-buttress.c

802

reg_val = readl(isp->base + BUTTRESS_REG_PS_WORKPOINT_REQ);

drivers/staging/media/ipu7/ipu7-buttress.c

806

reg_val &= BUTTRESS_PS_FREQ_CTL_RATIO_MASK;

drivers/staging/media/ipu7/ipu7-buttress.c

807

*freq = BUTTRESS_PS_FREQ_RATIO_STEP * reg_val;

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

120

u32 reg_val, reg_add;

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

124

reg_val = AWB_X_SYMBOL_H(symbol_h) | AWB_X_SYMBOL_L(symbol_l);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

127

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

132

reg_val = AWB_Y_SYMBOL_H(symbol_h) | AWB_Y_SYMBOL_L(symbol_l);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

135

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

140

reg_val = AWB_S_SYMBOL_H(symbol_h) | AWB_S_SYMBOL_L(symbol_l);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

143

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

15

u32 reg_val, reg_add;

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

180

u32 reg_val, reg_add;

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

184

reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

185

stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL0, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

189

reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

19

reg_val = GAIN_D_POINT(0x40) | GAIN_C_POINT(0x40) |

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

190

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

197

reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

198

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

204

reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

205

stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL14, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

22

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

26

reg_val = OFFSET_D_POINT(0) | OFFSET_C_POINT(0) |

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

268

u32 reg_val;

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

270

reg_val = YUVSW5(7) | YUVSW4(7) | YUVSW3(7) | YUVSW2(7) |

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

272

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR0, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

273

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR0, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

275

reg_val = YUVSW3(7) | YUVSW2(7) | YUVSW1(7) | YUVSW0(7);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

276

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR1, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

277

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR1, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

279

reg_val = CURVE_D_H(0x60) | CURVE_D_L(0x40);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

280

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR0, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

281

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR0, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

283

reg_val = CURVE_D_H(0xd8) | CURVE_D_L(0x90);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

284

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR1, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

285

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR1, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

287

reg_val = CURVE_D_H(0x1e6) | CURVE_D_L(0x144);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

288

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR2, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

289

stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR2, reg_val);

drivers/staging/media/starfive/camss/stf-isp-hw-ops.c

29

stf_isp_reg_write(stfcamss, reg_add, reg_val);

drivers/staging/octeon/ethernet.c

611

(const struct device_node *parent, int reg_val)

drivers/staging/octeon/ethernet.c

619

if (addr && (be32_to_cpu(*addr) == reg_val))

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

110

reg_val = readq((void __iomem *) (proc_priv->mmio_base + data->offset));

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

111

ret = (reg_val >> mmio_regs[ret].shift) & mmio_regs[ret].mask;

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

130

u64 mask, reg_val;

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

139

reg_val = readq((void __iomem *) (proc_priv->mmio_base + offset));

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

140

reg_val &= ~mask;

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

141

reg_val |= (value << ptc_mmio_regs[index].shift);

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

142

writeq(reg_val, (void __iomem *) (proc_priv->mmio_base + offset));

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

98

u64 reg_val;

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

195

u32 reg_val;\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

211

reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

212

ret = (reg_val >> mmio_regs[ret].shift) & mmio_regs[ret].mask;\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

233

u32 reg_val;\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

261

reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

262

reg_val &= ~mask;\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

263

reg_val |= (input << mmio_regs[ret].shift);\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

264

writel(reg_val, (void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\

drivers/thermal/intel/intel_bxt_pmic_thermal.c

160

u8 reg_val, mask, irq_stat;

drivers/thermal/intel/intel_bxt_pmic_thermal.c

181

reg_val = (u8)ret;

drivers/thermal/intel/intel_bxt_pmic_thermal.c

201

regmap_write(regmap, reg, reg_val & mask);

drivers/thermal/renesas/rcar_gen3_thermal.c

330

u32 reg_val;

drivers/thermal/renesas/rcar_gen3_thermal.c

332

reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);

drivers/thermal/renesas/rcar_gen3_thermal.c

333

reg_val &= ~THCTR_PONM;

drivers/thermal/renesas/rcar_gen3_thermal.c

334

rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val);

drivers/thermal/renesas/rcar_gen3_thermal.c

344

reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);

drivers/thermal/renesas/rcar_gen3_thermal.c

345

reg_val |= THCTR_THSST;

drivers/thermal/renesas/rcar_gen3_thermal.c

346

rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val);

drivers/thermal/renesas/rzg2l_thermal.c

123

u32 reg_val;

drivers/thermal/renesas/rzg2l_thermal.c

135

reg_val = rzg2l_thermal_read(priv, TSU_ST);

drivers/thermal/renesas/rzg2l_thermal.c

136

reg_val |= TSU_ST_START;

drivers/thermal/renesas/rzg2l_thermal.c

137

rzg2l_thermal_write(priv, TSU_ST, reg_val);

drivers/thermal/renesas/rzg2l_thermal.c

139

return readl_poll_timeout(priv->base + TSU_SS, reg_val,

drivers/thermal/renesas/rzg2l_thermal.c

140

reg_val == TSU_SS_CONV_RUNNING, 50,

drivers/thermal/ti-soc-thermal/ti-bandgap.c

361

int reg_val;

drivers/thermal/ti-soc-thermal/ti-bandgap.c

365

reg_val = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl);

drivers/thermal/ti-soc-thermal/ti-bandgap.c

366

reg_val = (reg_val & tsr->mask_counter_delay_mask) >>

drivers/thermal/ti-soc-thermal/ti-bandgap.c

368

switch (reg_val) {

drivers/thermal/ti-soc-thermal/ti-bandgap.c

389

reg_val);

drivers/ufs/core/ufshcd-crypto.c

166

hba->crypto_capabilities.reg_val =

drivers/ufs/core/ufshcd-crypto.c

197

hba->crypto_cap_array[cap_idx].reg_val =

drivers/ufs/core/ufshcd-crypto.c

29

ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));

drivers/ufs/core/ufshcd-crypto.c

31

ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),

drivers/ufs/core/ufshcd-crypto.c

32

slot_offset + i * sizeof(cfg->reg_val[0]));

drivers/ufs/core/ufshcd-crypto.c

35

ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),

drivers/ufs/core/ufshcd-crypto.c

36

slot_offset + 17 * sizeof(cfg->reg_val[0]));

drivers/ufs/core/ufshcd-crypto.c

38

ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),

drivers/ufs/core/ufshcd-crypto.c

39

slot_offset + 16 * sizeof(cfg->reg_val[0]));

drivers/ufs/host/ufs-qcom.c

192

caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));

drivers/ufs/host/ufs-qcom.c

211

cap.reg_val = cpu_to_le32(ufshcd_readl(hba,

drivers/ufs/host/ufs-qcom.c

788

u32 reg_val;

drivers/ufs/host/ufs-qcom.c

799

reg_val = ufshcd_readl(hba, UFS_MEM_ICE_CFG);

drivers/ufs/host/ufs-qcom.c

800

reg_val &= ~(UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW);

drivers/ufs/host/ufs-qcom.c

807

ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG);

drivers/usb/musb/tusb6010.c

42

#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)

drivers/usb/musb/tusb6010.c

43

#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)

drivers/usb/typec/anx7411.c

318

u8 reg_addr, u8 reg_val)

drivers/usb/typec/anx7411.c

320

return i2c_smbus_write_byte_data(client, reg_addr, reg_val);

drivers/usb/typec/hd3ss3220.c

164

unsigned int reg_val;

drivers/usb/typec/hd3ss3220.c

169

&reg_val);

drivers/usb/typec/hd3ss3220.c

173

switch (reg_val & HD3SS3220_REG_CN_STAT_CTRL_ATTACHED_STATE_MASK) {

drivers/usb/typec/mux/ptn36502.c

270

unsigned int reg_val;

drivers/usb/typec/mux/ptn36502.c

274

&reg_val);

drivers/usb/typec/mux/ptn36502.c

278

if (reg_val != PTN36502_CHIP_ID)

drivers/usb/typec/mux/ptn36502.c

279

return dev_err_probe(dev, -ENODEV, "Unexpected chip ID: %x\n", reg_val);

drivers/usb/typec/mux/ptn36502.c

282

&reg_val);

drivers/usb/typec/mux/ptn36502.c

287

FIELD_GET(PTN36502_CHIP_REVISION_BASE_MASK, reg_val),

drivers/usb/typec/mux/ptn36502.c

288

FIELD_GET(PTN36502_CHIP_REVISION_METAL_MASK, reg_val));

drivers/video/backlight/adp5520_bl.c

138

uint8_t reg_val;

drivers/video/backlight/adp5520_bl.c

141

ret = adp5520_read(data->master, reg, &reg_val);

drivers/video/backlight/adp5520_bl.c

147

return sprintf(buf, "%u\n", reg_val);

drivers/video/backlight/adp5520_bl.c

74

uint8_t reg_val;

drivers/video/backlight/adp5520_bl.c

76

error = adp5520_read(data->master, ADP5520_BL_VALUE, &reg_val);

drivers/video/backlight/adp5520_bl.c

78

return error ? data->current_brightness : reg_val;

drivers/video/backlight/adp8860_bl.c

140

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

145

ret = adp8860_read(client, reg, &reg_val);

drivers/video/backlight/adp8860_bl.c

147

if (!ret && ((reg_val & bit_mask) != bit_mask)) {

drivers/video/backlight/adp8860_bl.c

148

reg_val |= bit_mask;

drivers/video/backlight/adp8860_bl.c

149

ret = adp8860_write(client, reg, reg_val);

drivers/video/backlight/adp8860_bl.c

159

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

164

ret = adp8860_read(client, reg, &reg_val);

drivers/video/backlight/adp8860_bl.c

166

if (!ret && (reg_val & bit_mask)) {

drivers/video/backlight/adp8860_bl.c

167

reg_val &= ~bit_mask;

drivers/video/backlight/adp8860_bl.c

168

ret = adp8860_write(client, reg, reg_val);

drivers/video/backlight/adp8860_bl.c

424

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

427

error = adp8860_read(data->client, reg, &reg_val);

drivers/video/backlight/adp8860_bl.c

433

return sprintf(buf, "%u\n", reg_val);

drivers/video/backlight/adp8860_bl.c

554

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

558

error = adp8860_read(data->client, ADP8860_PH1LEVL, &reg_val);

drivers/video/backlight/adp8860_bl.c

560

ret_val = reg_val;

drivers/video/backlight/adp8860_bl.c

561

error = adp8860_read(data->client, ADP8860_PH1LEVH, &reg_val);

drivers/video/backlight/adp8860_bl.c

569

ret_val += (reg_val & 0x1F) << 8;

drivers/video/backlight/adp8860_bl.c

581

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

584

error = adp8860_read(data->client, ADP8860_CFGR, &reg_val);

drivers/video/backlight/adp8860_bl.c

591

((reg_val >> CFGR_BLV_SHIFT) & CFGR_BLV_MASK) + 1);

drivers/video/backlight/adp8860_bl.c

600

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

616

ret = adp8860_read(data->client, ADP8860_CFGR, &reg_val);

drivers/video/backlight/adp8860_bl.c

618

reg_val &= ~(CFGR_BLV_MASK << CFGR_BLV_SHIFT);

drivers/video/backlight/adp8860_bl.c

619

reg_val |= (val - 1) << CFGR_BLV_SHIFT;

drivers/video/backlight/adp8860_bl.c

620

adp8860_write(data->client, ADP8860_CFGR, reg_val);

drivers/video/backlight/adp8860_bl.c

658

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

676

ret = adp8860_read(client, ADP8860_MFDVID, &reg_val);

drivers/video/backlight/adp8860_bl.c

680

switch (ADP8860_MANID(reg_val)) {

drivers/video/backlight/adp8860_bl.c

697

data->revid = ADP8860_DEVID(reg_val);

drivers/video/backlight/adp8870_bl.c

155

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

160

ret = adp8870_read(client, reg, &reg_val);

drivers/video/backlight/adp8870_bl.c

162

if (!ret && ((reg_val & bit_mask) != bit_mask)) {

drivers/video/backlight/adp8870_bl.c

163

reg_val |= bit_mask;

drivers/video/backlight/adp8870_bl.c

164

ret = adp8870_write(client, reg, reg_val);

drivers/video/backlight/adp8870_bl.c

174

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

179

ret = adp8870_read(client, reg, &reg_val);

drivers/video/backlight/adp8870_bl.c

181

if (!ret && (reg_val & bit_mask)) {

drivers/video/backlight/adp8870_bl.c

182

reg_val &= ~bit_mask;

drivers/video/backlight/adp8870_bl.c

183

ret = adp8870_write(client, reg, reg_val);

drivers/video/backlight/adp8870_bl.c

545

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

548

error = adp8870_read(data->client, reg, &reg_val);

drivers/video/backlight/adp8870_bl.c

554

return sprintf(buf, "%u\n", reg_val);

drivers/video/backlight/adp8870_bl.c

736

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

740

error = adp8870_read(data->client, ADP8870_PH1LEVL, &reg_val);

drivers/video/backlight/adp8870_bl.c

745

ret_val = reg_val;

drivers/video/backlight/adp8870_bl.c

746

error = adp8870_read(data->client, ADP8870_PH1LEVH, &reg_val);

drivers/video/backlight/adp8870_bl.c

753

ret_val += (reg_val & 0x1F) << 8;

drivers/video/backlight/adp8870_bl.c

765

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

768

error = adp8870_read(data->client, ADP8870_CFGR, &reg_val);

drivers/video/backlight/adp8870_bl.c

775

((reg_val >> CFGR_BLV_SHIFT) & CFGR_BLV_MASK) + 1);

drivers/video/backlight/adp8870_bl.c

784

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

800

ret = adp8870_read(data->client, ADP8870_CFGR, &reg_val);

drivers/video/backlight/adp8870_bl.c

802

reg_val &= ~(CFGR_BLV_MASK << CFGR_BLV_SHIFT);

drivers/video/backlight/adp8870_bl.c

803

reg_val |= (val - 1) << CFGR_BLV_SHIFT;

drivers/video/backlight/adp8870_bl.c

804

adp8870_write(data->client, ADP8870_CFGR, reg_val);

drivers/video/backlight/adp8870_bl.c

846

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

860

ret = adp8870_read(client, ADP8870_MFDVID, &reg_val);

drivers/video/backlight/adp8870_bl.c

864

if (ADP8870_MANID(reg_val) != ADP8870_MANUFID) {

drivers/video/backlight/adp8870_bl.c

873

data->revid = ADP8870_DEVID(reg_val);

drivers/video/backlight/lm3630a_bl.c

62

unsigned int reg_val;

drivers/video/backlight/lm3630a_bl.c

64

rval = regmap_read(pchip->regmap, reg, &reg_val);

drivers/video/backlight/lm3630a_bl.c

67

return reg_val & 0xFF;

drivers/video/backlight/lm3639_bl.c

101

ret = regmap_read(pchip->regmap, REG_FLAG, &reg_val);

drivers/video/backlight/lm3639_bl.c

105

if (reg_val != 0)

drivers/video/backlight/lm3639_bl.c

106

dev_info(pchip->dev, "last flag is 0x%x\n", reg_val);

drivers/video/backlight/lm3639_bl.c

143

unsigned int reg_val;

drivers/video/backlight/lm3639_bl.c

156

ret = regmap_read(pchip->regmap, REG_BL_CONF_1, &reg_val);

drivers/video/backlight/lm3639_bl.c

159

if (reg_val & 0x10)

drivers/video/backlight/lm3639_bl.c

160

ret = regmap_read(pchip->regmap, REG_BL_CONF_4, &reg_val);

drivers/video/backlight/lm3639_bl.c

162

ret = regmap_read(pchip->regmap, REG_BL_CONF_3, &reg_val);

drivers/video/backlight/lm3639_bl.c

165

bl->props.brightness = reg_val;

drivers/video/backlight/lm3639_bl.c

223

unsigned int reg_val;

drivers/video/backlight/lm3639_bl.c

228

ret = regmap_read(pchip->regmap, REG_FLAG, &reg_val);

drivers/video/backlight/lm3639_bl.c

231

if (reg_val != 0)

drivers/video/backlight/lm3639_bl.c

232

dev_info(pchip->dev, "last flag is 0x%x\n", reg_val);

drivers/video/backlight/lm3639_bl.c

260

unsigned int reg_val;

drivers/video/backlight/lm3639_bl.c

265

ret = regmap_read(pchip->regmap, REG_FLAG, &reg_val);

drivers/video/backlight/lm3639_bl.c

268

if (reg_val != 0)

drivers/video/backlight/lm3639_bl.c

269

dev_info(pchip->dev, "last flag is 0x%x\n", reg_val);

drivers/video/backlight/lm3639_bl.c

50

unsigned int reg_val;

drivers/video/backlight/lm3639_bl.c

60

reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx;

drivers/video/backlight/lm3639_bl.c

61

ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val);

drivers/video/backlight/lm3639_bl.c

76

reg_val = pdata->fled_pins;

drivers/video/backlight/lm3639_bl.c

77

reg_val |= pdata->bled_pins;

drivers/video/backlight/lm3639_bl.c

79

reg_val = pdata->fled_pins;

drivers/video/backlight/lm3639_bl.c

80

reg_val |= pdata->bled_pins | 0x01;

drivers/video/backlight/lm3639_bl.c

83

ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val);

drivers/video/backlight/lm3639_bl.c

97

unsigned int reg_val;

drivers/video/backlight/mp3309c.c

103

reg_val = 0x00;

drivers/video/backlight/mp3309c.c

105

reg_val |= REG_I2C_1_SYNC;

drivers/video/backlight/mp3309c.c

106

reg_val |= chip->pdata->over_voltage_protection;

drivers/video/backlight/mp3309c.c

107

ret = regmap_write(chip->regmap, REG_I2C_1, reg_val);

drivers/video/backlight/mp3309c.c

89

u8 reg_val;

drivers/video/fbdev/aty/radeon_base.c

243

static reg_val common_regs[] = {

drivers/video/fbdev/via/viafbdev.c

1133

u8 reg_val = 0;

drivers/video/fbdev/via/viafbdev.c

1145

if (kstrtou8(value, 0, &reg_val) < 0)

drivers/video/fbdev/via/viafbdev.c

1148

reg_val);

drivers/video/fbdev/via/viafbdev.c

1152

reg_val, 0x0f);

drivers/video/fbdev/via/viafbdev.c

1156

reg_val << 4, BIT5);

drivers/video/fbdev/via/viafbdev.c

1158

reg_val << 1, BIT1);

drivers/video/fbdev/via/viafbdev.c

1162

reg_val << 3, BIT4);

drivers/video/fbdev/via/viafbdev.c

1164

reg_val << 2, BIT2);

drivers/video/fbdev/via/viafbdev.c

1203

u8 reg_val = 0;

drivers/video/fbdev/via/viafbdev.c

1215

if (kstrtou8(value, 0, &reg_val) < 0)

drivers/video/fbdev/via/viafbdev.c

1220

reg_val, 0x0f);

drivers/video/fbdev/via/viafbdev.c

1224

reg_val << 2, 0x0c);

drivers/video/fbdev/via/viafbdev.c

1228

reg_val, 0x03);

drivers/video/fbdev/via/viafbdev.c

1265

u8 reg_val;

drivers/video/fbdev/via/viafbdev.c

1266

err = kstrtou8_from_user(buffer, count, 0, &reg_val);

drivers/video/fbdev/via/viafbdev.c

1270

viafb_write_reg_mask(CR97, VIACR, reg_val, 0x0f);

drivers/video/fbdev/via/viafbdev.c

1299

u8 reg_val;

drivers/video/fbdev/via/viafbdev.c

1300

err = kstrtou8_from_user(buffer, count, 0, &reg_val);

drivers/video/fbdev/via/viafbdev.c

1304

viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f);

drivers/video/fbdev/via/viafbdev.c

1357

struct IODATA reg_val;

drivers/video/fbdev/via/viafbdev.c

1371

if (kstrtou8(value, 0, &reg_val.Data) < 0)

drivers/video/fbdev/via/viafbdev.c

1375

reg_val.Index = 0x08;

drivers/video/fbdev/via/viafbdev.c

1376

reg_val.Mask = 0x0f;

drivers/video/fbdev/via/viafbdev.c

1381

reg_val);

drivers/video/fbdev/via/viafbdev.c

1384

reg_val.Index = 0x09;

drivers/video/fbdev/via/viafbdev.c

1385

reg_val.Mask = 0x1f;

drivers/video/fbdev/via/viafbdev.c

1390

reg_val);

drivers/video/fbdev/via/viafbdev.c

1408

if (kstrtou8(value, 0, &reg_val.Data) < 0)

drivers/video/fbdev/via/viafbdev.c

1412

reg_val.Index = 0x08;

drivers/video/fbdev/via/viafbdev.c

1413

reg_val.Mask = 0x0f;

drivers/video/fbdev/via/viafbdev.c

1418

reg_val);

drivers/video/fbdev/via/viafbdev.c

1421

reg_val.Index = 0x09;

drivers/video/fbdev/via/viafbdev.c

1422

reg_val.Mask = 0x1f;

drivers/video/fbdev/via/viafbdev.c

1427

reg_val);

drivers/watchdog/da9052_wdt.c

46

u8 reg_val;

drivers/watchdog/da9052_wdt.c

96

da9052_wdt_maps[i].reg_val);

drivers/watchdog/da9055_wdt.c

37

u8 reg_val;

drivers/watchdog/da9055_wdt.c

68

da9055_wdt_maps[i].reg_val <<

drivers/watchdog/rn5t618_wdt.c

38

u8 reg_val;

drivers/watchdog/rn5t618_wdt.c

63

rn5t618_wdt_map[i].reg_val);

include/linux/mfd/axp20x.h

979

unsigned int reg_val, result;

include/linux/mfd/axp20x.h

982

err = regmap_read(regmap, reg, &reg_val);

include/linux/mfd/axp20x.h

986

result = reg_val << (width - 8);

include/linux/mfd/axp20x.h

988

err = regmap_read(regmap, reg + 1, &reg_val);

include/linux/mfd/axp20x.h

992

result |= reg_val;

include/linux/mfd/da9052/da9052.h

188

unsigned char reg_val)

include/linux/mfd/da9052/da9052.h

192

ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);

include/linux/mfd/da9055/core.h

69

unsigned char reg_val)

include/linux/mfd/da9055/core.h

71

return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);

include/ufs/ufshci.h

372

__le32 reg_val;

include/ufs/ufshci.h

398

__le32 reg_val;

include/ufs/ufshci.h

411

__le32 reg_val[32];

sound/drivers/opl3/opl3_drums.c

126

unsigned char reg_val;

sound/drivers/opl3/opl3_drums.c

130

reg_val = data->ksl_level;

sound/drivers/opl3/opl3_drums.c

131

snd_opl3_calc_volume(&reg_val, vel, chan);

sound/drivers/opl3/opl3_drums.c

133

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_drums.c

137

reg_val = data->feedback_connection | OPL3_STEREO_BITS;

sound/drivers/opl3/opl3_drums.c

139

reg_val &= ~OPL3_VOICE_TO_RIGHT;

sound/drivers/opl3/opl3_drums.c

141

reg_val &= ~OPL3_VOICE_TO_LEFT;

sound/drivers/opl3/opl3_drums.c

143

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

299

unsigned char reg_val;

sound/drivers/opl3/opl3_midi.c

391

reg_val = vp->keyon_reg & ~OPL3_KEYON_BIT;

sound/drivers/opl3/opl3_midi.c

392

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

399

reg_val = vp->keyon_reg & ~OPL3_KEYON_BIT;

sound/drivers/opl3/opl3_midi.c

400

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

458

reg_val = fm->op[i].am_vib;

sound/drivers/opl3/opl3_midi.c

460

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

463

reg_val = vol_op[i];

sound/drivers/opl3/opl3_midi.c

465

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

468

reg_val = fm->op[i].attack_decay;

sound/drivers/opl3/opl3_midi.c

470

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

473

reg_val = fm->op[i].sustain_release;

sound/drivers/opl3/opl3_midi.c

475

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

478

reg_val = fm->op[i].wave_select;

sound/drivers/opl3/opl3_midi.c

480

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

484

reg_val = fm->feedback_connection[0];

sound/drivers/opl3/opl3_midi.c

486

reg_val |= OPL3_STEREO_BITS;

sound/drivers/opl3/opl3_midi.c

488

reg_val &= ~OPL3_VOICE_TO_RIGHT;

sound/drivers/opl3/opl3_midi.c

490

reg_val &= ~OPL3_VOICE_TO_LEFT;

sound/drivers/opl3/opl3_midi.c

492

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_midi.c

496

reg_val = fm->feedback_connection[1] & OPL3_CONNECTION_BIT;

sound/drivers/opl3/opl3_midi.c

498

reg_val |= OPL3_STEREO_BITS;

sound/drivers/opl3/opl3_midi.c

500

reg_val &= ~OPL3_VOICE_TO_RIGHT;

sound/drivers/opl3/opl3_midi.c

502

reg_val &= ~OPL3_VOICE_TO_LEFT;

sound/drivers/opl3/opl3_midi.c

505

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

394

unsigned char reg_val;

sound/drivers/opl3/opl3_synth.c

414

reg_val = (unsigned char) note->fnum;

sound/drivers/opl3/opl3_synth.c

416

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

418

reg_val = 0x00;

sound/drivers/opl3/opl3_synth.c

421

reg_val |= OPL3_KEYON_BIT;

sound/drivers/opl3/opl3_synth.c

423

reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK;

sound/drivers/opl3/opl3_synth.c

425

reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK;

sound/drivers/opl3/opl3_synth.c

429

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

442

unsigned char reg_val;

sound/drivers/opl3/opl3_synth.c

468

reg_val = 0x00;

sound/drivers/opl3/opl3_synth.c

471

reg_val |= OPL3_TREMOLO_ON;

sound/drivers/opl3/opl3_synth.c

474

reg_val |= OPL3_VIBRATO_ON;

sound/drivers/opl3/opl3_synth.c

477

reg_val |= OPL3_SUSTAIN_ON;

sound/drivers/opl3/opl3_synth.c

480

reg_val |= OPL3_KSR;

sound/drivers/opl3/opl3_synth.c

482

reg_val |= voice->harmonic & OPL3_MULTIPLE_MASK;

sound/drivers/opl3/opl3_synth.c

486

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

489

reg_val = (voice->scale_level << 6) & OPL3_KSL_MASK;

sound/drivers/opl3/opl3_synth.c

491

reg_val |= ~voice->volume & OPL3_TOTAL_LEVEL_MASK;

sound/drivers/opl3/opl3_synth.c

495

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

498

reg_val = (voice->attack << 4) & OPL3_ATTACK_MASK;

sound/drivers/opl3/opl3_synth.c

500

reg_val |= voice->decay & OPL3_DECAY_MASK;

sound/drivers/opl3/opl3_synth.c

504

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

507

reg_val = (voice->sustain << 4) & OPL3_SUSTAIN_MASK;

sound/drivers/opl3/opl3_synth.c

509

reg_val |= voice->release & OPL3_RELEASE_MASK;

sound/drivers/opl3/opl3_synth.c

513

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

516

reg_val = (voice->feedback << 1) & OPL3_FEEDBACK_MASK;

sound/drivers/opl3/opl3_synth.c

519

reg_val |= OPL3_CONNECTION_BIT;

sound/drivers/opl3/opl3_synth.c

523

reg_val |= OPL3_VOICE_TO_LEFT;

sound/drivers/opl3/opl3_synth.c

525

reg_val |= OPL3_VOICE_TO_RIGHT;

sound/drivers/opl3/opl3_synth.c

529

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

532

reg_val = voice->waveform & OPL3_WAVE_SELECT_MASK;

sound/drivers/opl3/opl3_synth.c

534

opl3->command(opl3, opl3_reg, reg_val);

sound/drivers/opl3/opl3_synth.c

541

unsigned char reg_val;

sound/drivers/opl3/opl3_synth.c

543

reg_val = 0x00;

sound/drivers/opl3/opl3_synth.c

546

reg_val |= OPL3_KEYBOARD_SPLIT;

sound/drivers/opl3/opl3_synth.c

547

opl3->command(opl3, OPL3_LEFT | OPL3_REG_KBD_SPLIT, reg_val);

sound/drivers/opl3/opl3_synth.c

549

reg_val = 0x00;

sound/drivers/opl3/opl3_synth.c

552

reg_val |= OPL3_TREMOLO_DEPTH;

sound/drivers/opl3/opl3_synth.c

555

reg_val |= OPL3_VIBRATO_DEPTH;

sound/drivers/opl3/opl3_synth.c

558

reg_val |= OPL3_PERCUSSION_ENABLE;

sound/drivers/opl3/opl3_synth.c

565

reg_val |= OPL3_BASSDRUM_ON;

sound/drivers/opl3/opl3_synth.c

567

reg_val |= OPL3_SNAREDRUM_ON;

sound/drivers/opl3/opl3_synth.c

569

reg_val |= OPL3_TOMTOM_ON;

sound/drivers/opl3/opl3_synth.c

571

reg_val |= OPL3_CYMBAL_ON;

sound/drivers/opl3/opl3_synth.c

573

reg_val |= OPL3_HIHAT_ON;

sound/drivers/opl3/opl3_synth.c

575

opl3->command(opl3, OPL3_LEFT | OPL3_REG_PERCUSSION, reg_val);

sound/drivers/opl3/opl3_synth.c

593

unsigned char reg_val;

sound/drivers/opl3/opl3_synth.c

599

reg_val = connection & (OPL3_RIGHT_4OP_0 | OPL3_RIGHT_4OP_1 | OPL3_RIGHT_4OP_2 |

sound/drivers/opl3/opl3_synth.c

602

opl3->command(opl3, OPL3_RIGHT | OPL3_REG_CONNECTION_SELECT, reg_val);

sound/hda/codecs/side-codecs/cs35l56_hda.c

182

unsigned int reg_val;

sound/hda/codecs/side-codecs/cs35l56_hda.c

187

regmap_read(cs35l56->base.regmap, kcontrol->private_value, &reg_val);

sound/hda/codecs/side-codecs/cs35l56_hda.c

188

reg_val &= CS35L56_ASP_TXn_SRC_MASK;

sound/hda/codecs/side-codecs/cs35l56_hda.c

191

if (cs35l56_tx_input_values[i] == reg_val) {

sound/pci/aw2/aw2-saa7146.c

431

unsigned int reg_val = READREG(GPIO_CTRL);

sound/pci/aw2/aw2-saa7146.c

432

if ((reg_val & 0xFF) == 0x40)

sound/pci/azt3328.c

643

unsigned short reg_val = 0;

sound/pci/azt3328.c

652

reg_val = snd_azf3328_mixer_inw(chip,

sound/pci/azt3328.c

669

reg_val |= azf_emulated_ac97_caps;

sound/pci/azt3328.c

672

reg_val |= azf_emulated_ac97_powerdown;

sound/pci/azt3328.c

677

reg_val |= 0;

sound/pci/azt3328.c

680

reg_val = azf_emulated_ac97_vendor_id >> 16;

sound/pci/azt3328.c

683

reg_val = azf_emulated_ac97_vendor_id & 0xffff;

sound/pci/azt3328.c

694

return reg_val;

sound/soc/amd/acp/acp-i2s.c

201

u32 reg_val, fmt_reg, tdm_fmt;

sound/soc/amd/acp/acp-i2s.c

229

reg_val = ACP_BTTDM_ITER;

sound/soc/amd/acp/acp-i2s.c

233

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/acp/acp-i2s.c

237

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/acp/acp-i2s.c

248

reg_val = ACP_BTTDM_IRER;

sound/soc/amd/acp/acp-i2s.c

252

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/acp/acp-i2s.c

256

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/acp/acp-i2s.c

266

val = readl(chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

269

writel(val, chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

272

val = readl(chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

273

writel(val | BIT(1), chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

393

u32 val, period_bytes, reg_val, ier_val, water_val, buf_size, buf_reg;

sound/soc/amd/acp/acp-i2s.c

407

reg_val = ACP_BTTDM_ITER;

sound/soc/amd/acp/acp-i2s.c

413

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/acp/acp-i2s.c

419

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/acp/acp-i2s.c

431

reg_val = ACP_BTTDM_IRER;

sound/soc/amd/acp/acp-i2s.c

437

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/acp/acp-i2s.c

443

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/acp/acp-i2s.c

457

val = readl(chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

459

writel(val, chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

468

reg_val = ACP_BTTDM_ITER;

sound/soc/amd/acp/acp-i2s.c

471

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/acp/acp-i2s.c

474

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/acp/acp-i2s.c

484

reg_val = ACP_BTTDM_IRER;

sound/soc/amd/acp/acp-i2s.c

487

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/acp/acp-i2s.c

490

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/acp/acp-i2s.c

497

val = readl(chip->base + reg_val);

sound/soc/amd/acp/acp-i2s.c

499

writel(val, chip->base + reg_val);

sound/soc/amd/acp/acp-legacy-common.c

317

u32 tdm_fmt, reg_val, fmt_reg, val;

sound/soc/amd/acp/acp-legacy-common.c

325

reg_val = ACP_BTTDM_ITER;

sound/soc/amd/acp/acp-legacy-common.c

329

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/acp/acp-legacy-common.c

333

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/acp/acp-legacy-common.c

345

reg_val = ACP_BTTDM_IRER;

sound/soc/amd/acp/acp-legacy-common.c

349

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/acp/acp-legacy-common.c

353

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/acp/acp-legacy-common.c

362

writel(val, chip->base + reg_val);

sound/soc/amd/acp/acp-legacy-common.c

365

val = readl(chip->base + reg_val);

sound/soc/amd/acp/acp-legacy-common.c

366

writel(val | 0x2, chip->base + reg_val);

sound/soc/amd/acp/acp-platform.c

113

u32 reg_val;

sound/soc/amd/acp/acp-platform.c

115

reg_val = rsrc->sram_pte_offset;

sound/soc/amd/acp/acp-platform.c

118

writel((reg_val + GRP1_OFFSET) | BIT(31), chip->base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);

sound/soc/amd/acp/acp-platform.c

121

writel((reg_val + GRP2_OFFSET) | BIT(31), chip->base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2);

sound/soc/amd/acp/acp-platform.c

124

writel(reg_val | BIT(31), chip->base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_5);

sound/soc/amd/raven/acp3x-i2s.c

116

reg_val = mmACP_BTTDM_ITER;

sound/soc/amd/raven/acp3x-i2s.c

121

reg_val = mmACP_I2STDM_ITER;

sound/soc/amd/raven/acp3x-i2s.c

127

reg_val = mmACP_BTTDM_IRER;

sound/soc/amd/raven/acp3x-i2s.c

132

reg_val = mmACP_I2STDM_IRER;

sound/soc/amd/raven/acp3x-i2s.c

137

val = rv_readl(rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

138

rv_writel(val | 0x2, rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

141

val = rv_readl(rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

144

rv_writel(val, rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

152

u32 val, period_bytes, reg_val, ier_val, water_val;

sound/soc/amd/raven/acp3x-i2s.c

172

reg_val = mmACP_BTTDM_ITER;

sound/soc/amd/raven/acp3x-i2s.c

180

reg_val = mmACP_I2STDM_ITER;

sound/soc/amd/raven/acp3x-i2s.c

189

reg_val = mmACP_BTTDM_IRER;

sound/soc/amd/raven/acp3x-i2s.c

197

reg_val = mmACP_I2STDM_IRER;

sound/soc/amd/raven/acp3x-i2s.c

204

val = rv_readl(rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

206

rv_writel(val, rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

216

reg_val = mmACP_BTTDM_ITER;

sound/soc/amd/raven/acp3x-i2s.c

220

reg_val = mmACP_I2STDM_ITER;

sound/soc/amd/raven/acp3x-i2s.c

226

reg_val = mmACP_BTTDM_IRER;

sound/soc/amd/raven/acp3x-i2s.c

230

reg_val = mmACP_I2STDM_IRER;

sound/soc/amd/raven/acp3x-i2s.c

233

val = rv_readl(rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

235

rv_writel(val, rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-i2s.c

81

u32 reg_val, frmt_reg;

sound/soc/amd/raven/acp3x-pcm-dma.c

433

u32 val, reg_val, frmt_val;

sound/soc/amd/raven/acp3x-pcm-dma.c

435

reg_val = 0;

sound/soc/amd/raven/acp3x-pcm-dma.c

445

reg_val = mmACP_BTTDM_ITER;

sound/soc/amd/raven/acp3x-pcm-dma.c

450

reg_val = mmACP_I2STDM_ITER;

sound/soc/amd/raven/acp3x-pcm-dma.c

454

rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-pcm-dma.c

462

reg_val = mmACP_BTTDM_IRER;

sound/soc/amd/raven/acp3x-pcm-dma.c

467

reg_val = mmACP_I2STDM_IRER;

sound/soc/amd/raven/acp3x-pcm-dma.c

471

rtd->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-pcm-dma.c

475

val = rv_readl(adata->acp3x_base + reg_val);

sound/soc/amd/raven/acp3x-pcm-dma.c

476

rv_writel(val | 0x2, adata->acp3x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

131

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/vangogh/acp5x-i2s.c

136

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/vangogh/acp5x-i2s.c

142

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/vangogh/acp5x-i2s.c

147

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/vangogh/acp5x-i2s.c

152

val = acp_readl(rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

153

acp_writel(val | 0x2, rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

156

val = acp_readl(rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

159

acp_writel(val, rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

237

u32 val, period_bytes, reg_val, ier_val, water_val;

sound/soc/amd/vangogh/acp5x-i2s.c

258

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/vangogh/acp5x-i2s.c

266

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/vangogh/acp5x-i2s.c

275

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/vangogh/acp5x-i2s.c

283

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/vangogh/acp5x-i2s.c

292

val = acp_readl(rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

294

acp_writel(val, rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

304

reg_val = ACP_HSTDM_ITER;

sound/soc/amd/vangogh/acp5x-i2s.c

308

reg_val = ACP_I2STDM_ITER;

sound/soc/amd/vangogh/acp5x-i2s.c

314

reg_val = ACP_HSTDM_IRER;

sound/soc/amd/vangogh/acp5x-i2s.c

318

reg_val = ACP_I2STDM_IRER;

sound/soc/amd/vangogh/acp5x-i2s.c

321

val = acp_readl(rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

323

acp_writel(val, rtd->acp5x_base + reg_val);

sound/soc/amd/vangogh/acp5x-i2s.c

93

u32 reg_val, frmt_reg;

sound/soc/codecs/aw88081.c

151

unsigned int reg_val;

sound/soc/codecs/aw88081.c

155

ret = regmap_read(aw_dev->regmap, AW88081_PWMCTRL4_REG, &reg_val);

sound/soc/codecs/aw88081.c

159

if (reg_val & (~AW88081_NOISE_GATE_EN_MASK))

sound/soc/codecs/aw88081.c

165

ret = regmap_read(aw_dev->regmap, AW88081_SYSST_REG, &reg_val);

sound/soc/codecs/aw88081.c

169

value = reg_val & (~AW88081_BIT_SYSST_CHECK_MASK) & check_val;

sound/soc/codecs/aw88081.c

172

reg_val, check_val);

sound/soc/codecs/aw88081.c

336

unsigned char reg_addr, unsigned short *reg_val)

sound/soc/codecs/aw88081.c

341

*reg_val &= ~(~AW88081_EN_PA_MASK |

sound/soc/codecs/aw88081.c

346

*reg_val |= AW88081_EN_PA_POWER_DOWN_VALUE |

sound/soc/codecs/aw88081.c

353

read_vol = (*reg_val & (~AW88081_VOL_MASK)) >> AW88081_VOL_START_BIT;

sound/soc/codecs/aw88081.c

360

*reg_val &= AW88081_I2STXEN_MASK;

sound/soc/codecs/aw88081.c

361

*reg_val |= AW88081_I2STXEN_DISABLE_VALUE;

sound/soc/codecs/aw88081.c

368

unsigned char reg_addr, unsigned short *reg_val)

sound/soc/codecs/aw88081.c

373

*reg_val &= ~(~AW88083_AMPPD_MASK |

sound/soc/codecs/aw88081.c

378

*reg_val |= AW88083_AMPPD_POWER_DOWN_VALUE |

sound/soc/codecs/aw88081.c

385

read_vol = (*reg_val & (~AW88081_VOL_MASK)) >> AW88081_VOL_START_BIT;

sound/soc/codecs/aw88081.c

393

unsigned char reg_addr, unsigned short *reg_val)

sound/soc/codecs/aw88081.c

400

ret = aw88081_dev_reg_value_check(aw_dev, reg_addr, reg_val);

sound/soc/codecs/aw88081.c

403

ret = aw88083_dev_reg_value_check(aw_dev, reg_addr, reg_val);

sound/soc/codecs/aw88081.c

421

u16 reg_val;

sound/soc/codecs/aw88081.c

439

reg_val = reg_data[i + 1];

sound/soc/codecs/aw88081.c

441

ret = aw88081_reg_value_check(aw88081, reg_addr, &reg_val);

sound/soc/codecs/aw88081.c

445

ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);

sound/soc/codecs/aw88081.c

50

unsigned int reg_val;

sound/soc/codecs/aw88081.c

53

ret = regmap_read(aw_dev->regmap, AW88081_SYSST_REG, &reg_val);

sound/soc/codecs/aw88081.c

56

if ((reg_val & AW88081_BIT_PLL_CHECK) != AW88081_BIT_PLL_CHECK) {

sound/soc/codecs/aw88081.c

57

dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88081.c

83

unsigned int reg_val;

sound/soc/codecs/aw88081.c

86

ret = regmap_read(aw_dev->regmap, AW88081_PLLCTRL1_REG, &reg_val);

sound/soc/codecs/aw88081.c

90

reg_val &= (~AW88081_CCO_MUX_MASK);

sound/soc/codecs/aw88081.c

91

if (reg_val == AW88081_CCO_MUX_DIVIDED_VALUE) {

sound/soc/codecs/aw88166.c

1000

aw88166->crc_init_val = reg_val;

sound/soc/codecs/aw88166.c

1002

ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);

sound/soc/codecs/aw88166.c

120

unsigned int reg_val;

sound/soc/codecs/aw88166.c

1207

u16 reg_val;

sound/soc/codecs/aw88166.c

1209

aw_dev_get_int_status(aw_dev, &reg_val);

sound/soc/codecs/aw88166.c

1210

if (reg_val & AW88166_BIT_SYSINT_CHECK) {

sound/soc/codecs/aw88166.c

1211

dev_err(aw_dev->dev, "pa stop check fail:0x%04x\n", reg_val);

sound/soc/codecs/aw88166.c

123

ret = regmap_read(aw_dev->regmap, AW88166_PLLCTRL2_REG, &reg_val);

sound/soc/codecs/aw88166.c

127

reg_val &= (~AW88166_CCO_MUX_MASK);

sound/soc/codecs/aw88166.c

128

if (reg_val == AW88166_CCO_MUX_DIVIDED_VALUE) {

sound/soc/codecs/aw88166.c

188

unsigned int reg_val;

sound/soc/codecs/aw88166.c

191

ret = regmap_read(aw_dev->regmap, AW88166_PWMCTRL3_REG, &reg_val);

sound/soc/codecs/aw88166.c

195

if (reg_val & (~AW88166_NOISE_GATE_EN_MASK))

sound/soc/codecs/aw88166.c

201

ret = regmap_read(aw_dev->regmap, AW88166_SYSST_REG, &reg_val);

sound/soc/codecs/aw88166.c

205

if ((reg_val & (~AW88166_BIT_SYSST_CHECK_MASK) & check_val) != check_val) {

sound/soc/codecs/aw88166.c

207

i, reg_val, AW88166_BIT_SYSST_NOSWS_CHECK);

sound/soc/codecs/aw88166.c

320

unsigned int reg_val;

sound/soc/codecs/aw88166.c

341

reg_val = (uint32_t)vcalb;

sound/soc/codecs/aw88166.c

343

regmap_write(aw_dev->regmap, AW88166_DSPVCALB_REG, reg_val);

sound/soc/codecs/aw88166.c

449

unsigned int reg_val;

sound/soc/codecs/aw88166.c

467

regmap_read(aw_dev->regmap, AW88166_HAGCST_REG, &reg_val);

sound/soc/codecs/aw88166.c

471

check_val = (reg_val & (~AW88166_CRC_CHECK_BITS_MASK)) >> AW88166_CRC_CHECK_START_BIT;

sound/soc/codecs/aw88166.c

491

unsigned int reg_val;

sound/soc/codecs/aw88166.c

512

ret = regmap_read(aw_dev->regmap, AW88166_HAGCST_REG, &reg_val);

sound/soc/codecs/aw88166.c

516

check_val = (reg_val & (~AW88166_CRC_CHECK_BITS_MASK)) >> AW88166_CRC_CHECK_START_BIT;

sound/soc/codecs/aw88166.c

587

unsigned int reg_val;

sound/soc/codecs/aw88166.c

590

ret = regmap_read(aw_dev->regmap, AW88166_WDT_REG, &reg_val);

sound/soc/codecs/aw88166.c

593

if (!(reg_val & (~AW88166_WDT_CNT_MASK)))

sound/soc/codecs/aw88166.c

61

unsigned int reg_val;

sound/soc/codecs/aw88166.c

64

ret = regmap_read(aw_dev->regmap, AW88166_SYSINT_REG, &reg_val);

sound/soc/codecs/aw88166.c

68

*int_status = reg_val;

sound/soc/codecs/aw88166.c

87

unsigned int reg_val;

sound/soc/codecs/aw88166.c

882

unsigned int reg_val;

sound/soc/codecs/aw88166.c

885

aw_dev_dsp_read(aw_dev, AW88166_DSP_ROM_CHECK_ADDR, &reg_val, AW_DSP_16_DATA);

sound/soc/codecs/aw88166.c

886

if (reg_val != AW88166_DSP_ROM_CHECK_DATA) {

sound/soc/codecs/aw88166.c

888

reg_val, AW88166_DSP_ROM_CHECK_DATA);

sound/soc/codecs/aw88166.c

895

aw_dev_dsp_read(aw_dev, AW88166_DSP_CFG_ADDR, &reg_val, AW_DSP_16_DATA);

sound/soc/codecs/aw88166.c

896

if (reg_val != AW88166_DSP_ODD_NUM_BIT_TEST) {

sound/soc/codecs/aw88166.c

898

reg_val, AW88166_DSP_ODD_NUM_BIT_TEST);

sound/soc/codecs/aw88166.c

90

ret = regmap_read(aw_dev->regmap, AW88166_SYSST_REG, &reg_val);

sound/soc/codecs/aw88166.c

93

if ((reg_val & AW88166_BIT_PLL_CHECK) != AW88166_BIT_PLL_CHECK) {

sound/soc/codecs/aw88166.c

935

u16 read_vol, reg_val;

sound/soc/codecs/aw88166.c

94

dev_err(aw_dev->dev, "check pll lock fail, reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88166.c

950

reg_val = reg_data[i + 1];

sound/soc/codecs/aw88166.c

953

aw88166->vcalb_init_val = reg_val;

sound/soc/codecs/aw88166.c

958

if (reg_val & (~AW88166_DSPBY_MASK))

sound/soc/codecs/aw88166.c

963

reg_val &= (AW88166_HMUTE_MASK | AW88166_PWDN_MASK |

sound/soc/codecs/aw88166.c

965

reg_val |= (AW88166_HMUTE_ENABLE_VALUE | AW88166_PWDN_POWER_DOWN_VALUE |

sound/soc/codecs/aw88166.c

970

reg_val &= AW88166_I2STXEN_MASK;

sound/soc/codecs/aw88166.c

971

reg_val |= AW88166_I2STXEN_DISABLE_VALUE;

sound/soc/codecs/aw88166.c

975

read_vol = (reg_val & (~AW88166_VOL_MASK)) >>

sound/soc/codecs/aw88166.c

981

if ((reg_val & (~AW88166_EF_DBMD_MASK)) == AW88166_EF_DBMD_OR_VALUE)

sound/soc/codecs/aw88166.c

986

aw88166->dither_st = reg_val & (~AW88166_DITHER_EN_MASK);

sound/soc/codecs/aw88166.c

990

aw88166->re_init_val |= (uint32_t)reg_val << 16;

sound/soc/codecs/aw88166.c

995

aw88166->re_init_val |= (uint32_t)reg_val;

sound/soc/codecs/aw88261.c

1015

unsigned int reg_val;

sound/soc/codecs/aw88261.c

1019

ret = regmap_read(aw88261->regmap, AW88261_EFRH3_REG, &reg_val);

sound/soc/codecs/aw88261.c

1022

temh = ((u16)reg_val & (~AW88261_TEMH_MASK));

sound/soc/codecs/aw88261.c

1024

ret = regmap_read(aw88261->regmap, AW88261_EFRL3_REG, &reg_val);

sound/soc/codecs/aw88261.c

1027

teml = ((u16)reg_val & (~AW88261_TEML_MASK));

sound/soc/codecs/aw88261.c

147

unsigned int reg_val;

sound/soc/codecs/aw88261.c

150

ret = regmap_read(aw_dev->regmap, AW88261_SYSST_REG, &reg_val);

sound/soc/codecs/aw88261.c

153

if ((reg_val & AW88261_BIT_PLL_CHECK) != AW88261_BIT_PLL_CHECK) {

sound/soc/codecs/aw88261.c

154

dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88261.c

180

unsigned int reg_val;

sound/soc/codecs/aw88261.c

183

ret = regmap_read(aw_dev->regmap, AW88261_PLLCTRL1_REG, &reg_val);

sound/soc/codecs/aw88261.c

187

reg_val &= (~AW88261_CCO_MUX_MASK);

sound/soc/codecs/aw88261.c

188

if (reg_val == AW88261_CCO_MUX_DIVIDED_VALUE) {

sound/soc/codecs/aw88261.c

248

unsigned int reg_val;

sound/soc/codecs/aw88261.c

252

ret = regmap_read(aw_dev->regmap, AW88261_SYSST_REG, &reg_val);

sound/soc/codecs/aw88261.c

256

check_val = reg_val & (~AW88261_BIT_SYSST_CHECK_MASK)

sound/soc/codecs/aw88261.c

260

reg_val, AW88261_BIT_SYSST_CHECK);

sound/soc/codecs/aw88261.c

311

unsigned int reg_val;

sound/soc/codecs/aw88261.c

314

ret = regmap_read(aw_dev->regmap, AW88261_EFRH4_REG, &reg_val);

sound/soc/codecs/aw88261.c

318

reg_icalk = reg_val & (~AW88261_EF_ISN_GESLP_H_MASK);

sound/soc/codecs/aw88261.c

320

ret = regmap_read(aw_dev->regmap, AW88261_EFRL4_REG, &reg_val);

sound/soc/codecs/aw88261.c

324

reg_icalkl = reg_val & (~AW88261_EF_ISN_GESLP_L_MASK);

sound/soc/codecs/aw88261.c

339

unsigned int reg_val;

sound/soc/codecs/aw88261.c

342

ret = regmap_read(aw_dev->regmap, AW88261_EFRH3_REG, &reg_val);

sound/soc/codecs/aw88261.c

346

reg_vcalk = (u16)reg_val & (~AW88261_EF_VSN_GESLP_H_MASK);

sound/soc/codecs/aw88261.c

348

ret = regmap_read(aw_dev->regmap, AW88261_EFRL3_REG, &reg_val);

sound/soc/codecs/aw88261.c

352

reg_vcalkl = (u16)reg_val & (~AW88261_EF_VSN_GESLP_L_MASK);

sound/soc/codecs/aw88261.c

367

u32 reg_val;

sound/soc/codecs/aw88261.c

384

reg_val = (unsigned int)vcalb;

sound/soc/codecs/aw88261.c

387

icalk, vcalk, vcalb, reg_val);

sound/soc/codecs/aw88261.c

388

ret = regmap_write(aw_dev->regmap, AW88261_VSNTM1_REG, reg_val);

sound/soc/codecs/aw88261.c

401

u16 reg_val;

sound/soc/codecs/aw88261.c

419

reg_val = reg_data[i + 1];

sound/soc/codecs/aw88261.c

422

aw88261->amppd_st = reg_val & (~AW88261_AMPPD_MASK);

sound/soc/codecs/aw88261.c

430

reg_val &= (AW88261_AMPPD_MASK & AW88261_PWDN_MASK & AW88261_HMUTE_MASK);

sound/soc/codecs/aw88261.c

431

reg_val |= read_val;

sound/soc/codecs/aw88261.c

434

reg_val &= AW88261_ULS_HMUTE_MASK;

sound/soc/codecs/aw88261.c

435

reg_val |= AW88261_ULS_HMUTE_ENABLE_VALUE;

sound/soc/codecs/aw88261.c

439

efcheck_val = reg_val & (~AW88261_EF_DBMD_MASK);

sound/soc/codecs/aw88261.c

449

reg_val &= AW88261_I2STXEN_MASK;

sound/soc/codecs/aw88261.c

450

reg_val |= AW88261_I2STXEN_DISABLE_VALUE;

sound/soc/codecs/aw88261.c

454

read_vol = (reg_val & (~AW88261_VOL_MASK)) >>

sound/soc/codecs/aw88261.c

463

ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1006

u16 reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

1020

reg_val = reg_data[i + 1];

sound/soc/codecs/aw88395/aw88395_device.c

1027

reg_val &= AW88395_HMUTE_MASK;

sound/soc/codecs/aw88395/aw88395_device.c

1028

reg_val |= read_val;

sound/soc/codecs/aw88395/aw88395_device.c

1031

reg_val &= AW88395_AGC_DSP_CTL_MASK;

sound/soc/codecs/aw88395/aw88395_device.c

1035

reg_val &= AW88395_I2STXEN_MASK;

sound/soc/codecs/aw88395/aw88395_device.c

1036

reg_val |= AW88395_I2STXEN_DISABLE_VALUE;

sound/soc/codecs/aw88395/aw88395_device.c

1040

read_vol = (reg_val & (~AW88395_VOL_MASK)) >>

sound/soc/codecs/aw88395/aw88395_device.c

1045

ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1127

__be16 reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

1135

reg_val = cpu_to_be16p((u16 *)(data + i));

sound/soc/codecs/aw88395/aw88395_device.c

1137

(u16)reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1232

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

1237

regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1238

if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {

sound/soc/codecs/aw88395/aw88395_device.c

1240

reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);

sound/soc/codecs/aw88395/aw88395_device.c

1246

regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1247

if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {

sound/soc/codecs/aw88395/aw88395_device.c

1249

reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);

sound/soc/codecs/aw88395/aw88395_device.c

1255

aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_FW_ADDR, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1256

if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {

sound/soc/codecs/aw88395/aw88395_device.c

1258

reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);

sound/soc/codecs/aw88395/aw88395_device.c

1264

aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_CFG_ADDR, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

1265

if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {

sound/soc/codecs/aw88395/aw88395_device.c

1267

reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);

sound/soc/codecs/aw88395/aw88395_device.c

190

int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

193

ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

199

dev_info(aw_dev->dev, "chip id = %x\n", reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

200

*chip_id = reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

452

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

457

ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

463

if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) {

sound/soc/codecs/aw88395/aw88395_device.c

464

dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

468

dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

576

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

580

ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

584

reg_icalk = reg_val & (~AW88395_EF_ISN_GESLP_MASK);

sound/soc/codecs/aw88395/aw88395_device.c

596

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

600

ret = regmap_read(aw_dev->regmap, AW88395_EFRH_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

604

reg_val = reg_val >> AW88395_EF_VSENSE_GAIN_SHIFT;

sound/soc/codecs/aw88395/aw88395_device.c

606

reg_vcalk = (u16)reg_val & (~AW88395_EF_VSN_GESLP_MASK);

sound/soc/codecs/aw88395/aw88395_device.c

618

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

622

ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

626

reg_vcalk = reg_val >> AW88395_EF_DAC_GESLP_SHIFT;

sound/soc/codecs/aw88395/aw88395_device.c

663

u32 vcalb_adj, reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

719

reg_val = (u32)vcalb;

sound/soc/codecs/aw88395/aw88395_device.c

722

vcalb, reg_val, vcalb_adj);

sound/soc/codecs/aw88395/aw88395_device.c

724

ret = aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_VCALB, reg_val, AW_DSP_16_DATA);

sound/soc/codecs/aw88395/aw88395_device.c

731

(u32)reg_val, AW_DSP_16_DATA);

sound/soc/codecs/aw88395/aw88395_device.c

758

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

761

ret = regmap_read(aw_dev->regmap, AW88395_SYSINT_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

765

*int_status = reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

784

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

787

ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

790

if ((reg_val & AW88395_BIT_PLL_CHECK) != AW88395_BIT_PLL_CHECK) {

sound/soc/codecs/aw88395/aw88395_device.c

791

dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

817

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

820

ret = regmap_read(aw_dev->regmap, AW88395_PLLCTRL1_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

824

reg_val &= (~AW88395_CCO_MUX_MASK);

sound/soc/codecs/aw88395/aw88395_device.c

825

if (reg_val == AW88395_CCO_MUX_DIVIDED_VALUE) {

sound/soc/codecs/aw88395/aw88395_device.c

885

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

889

ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

893

check_val = reg_val & (~AW88395_BIT_SYSST_CHECK_MASK)

sound/soc/codecs/aw88395/aw88395_device.c

897

i, reg_val, AW88395_BIT_SYSST_CHECK);

sound/soc/codecs/aw88395/aw88395_device.c

909

u16 reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

911

aw_dev_get_int_status(aw_dev, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

913

if (reg_val & AW88395_BIT_SYSINT_CHECK) {

sound/soc/codecs/aw88395/aw88395_device.c

914

dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

924

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

927

ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

932

if ((reg_val & (~AW88395_RCV_MODE_MASK)) == AW88395_RCV_MODE_RECEIVER_VALUE)

sound/soc/codecs/aw88395/aw88395_device.c

940

unsigned int reg_val = 0;

sound/soc/codecs/aw88395/aw88395_device.c

943

ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

948

if (reg_val & (~AW88395_DSPBY_MASK))

sound/soc/codecs/aw88395/aw88395_device.c

981

unsigned int reg_val;

sound/soc/codecs/aw88395/aw88395_device.c

984

ret = regmap_read(aw_dev->regmap, AW88395_WDT_REG, &reg_val);

sound/soc/codecs/aw88395/aw88395_device.c

987

if (!(reg_val & (~AW88395_WDT_CNT_MASK)))

sound/soc/codecs/aw88399.c

105

unsigned int reg_val;

sound/soc/codecs/aw88399.c

108

ret = regmap_read(aw_dev->regmap, AW88399_PLLCTRL2_REG, &reg_val);

sound/soc/codecs/aw88399.c

112

reg_val &= (~AW88399_CCO_MUX_MASK);

sound/soc/codecs/aw88399.c

113

if (reg_val == AW88399_CCO_MUX_DIVIDED_VALUE) {

sound/soc/codecs/aw88399.c

1174

u16 reg_val;

sound/soc/codecs/aw88399.c

1176

aw_dev_get_int_status(aw_dev, &reg_val);

sound/soc/codecs/aw88399.c

1177

if (reg_val & AW88399_BIT_SYSINT_CHECK) {

sound/soc/codecs/aw88399.c

1178

dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val);

sound/soc/codecs/aw88399.c

1346

unsigned int reg_val;

sound/soc/codecs/aw88399.c

1350

ret = regmap_read(aw_dev->regmap, AW88399_DSPCFG_REG, &reg_val);

sound/soc/codecs/aw88399.c

1356

aw_dev->cali_desc.store_vol = reg_val & (~AW88399_DSP_VOL_MASK);

sound/soc/codecs/aw88399.c

1370

unsigned int reg_val, dsp_val;

sound/soc/codecs/aw88399.c

1372

regmap_read(aw_dev->regmap, AW88399_DBGCTRL_REG, &reg_val);

sound/soc/codecs/aw88399.c

1373

backup_desc->dsp_ng_cfg = reg_val & (~AW883XX_DSP_NG_EN_MASK);

sound/soc/codecs/aw88399.c

173

unsigned int reg_val;

sound/soc/codecs/aw88399.c

176

ret = regmap_read(aw_dev->regmap, AW88399_PWMCTRL3_REG, &reg_val);

sound/soc/codecs/aw88399.c

180

if (reg_val & (~AW88399_NOISE_GATE_EN_MASK))

sound/soc/codecs/aw88399.c

186

ret = regmap_read(aw_dev->regmap, AW88399_SYSST_REG, &reg_val);

sound/soc/codecs/aw88399.c

190

if ((reg_val & (~AW88399_BIT_SYSST_CHECK_MASK) & check_val) != check_val) {

sound/soc/codecs/aw88399.c

192

i, reg_val, AW88399_BIT_SYSST_NOSWS_CHECK);

sound/soc/codecs/aw88399.c

236

unsigned int reg_val;

sound/soc/codecs/aw88399.c

239

ret = regmap_read(aw_dev->regmap, AW88399_EFRH4_REG, &reg_val);

sound/soc/codecs/aw88399.c

242

icalkh_val = reg_val & (~AW88399_EF_ISN_GESLP_H_MASK);

sound/soc/codecs/aw88399.c

244

ret = regmap_read(aw_dev->regmap, AW88399_EFRL4_REG, &reg_val);

sound/soc/codecs/aw88399.c

247

icalkl_val = reg_val & (~AW88399_EF_ISN_GESLP_L_MASK);

sound/soc/codecs/aw88399.c

265

unsigned int reg_val;

sound/soc/codecs/aw88399.c

268

ret = regmap_read(aw_dev->regmap, AW88399_EFRH3_REG, &reg_val);

sound/soc/codecs/aw88399.c

272

vcalkh_val = reg_val & (~AW88399_EF_VSN_GESLP_H_MASK);

sound/soc/codecs/aw88399.c

274

ret = regmap_read(aw_dev->regmap, AW88399_EFRL3_REG, &reg_val);

sound/soc/codecs/aw88399.c

278

vcalkl_val = reg_val & (~AW88399_EF_VSN_GESLP_L_MASK);

sound/soc/codecs/aw88399.c

296

unsigned int reg_val;

sound/soc/codecs/aw88399.c

299

ret = regmap_read(aw_dev->regmap, AW88399_EFRH2_REG, &reg_val);

sound/soc/codecs/aw88399.c

302

vcalkh_val = reg_val & (~AW88399_INTERNAL_VSN_TRIM_H_MASK);

sound/soc/codecs/aw88399.c

304

ret = regmap_read(aw_dev->regmap, AW88399_EFRL2_REG, &reg_val);

sound/soc/codecs/aw88399.c

307

vcalkl_val = reg_val & (~AW88399_INTERNAL_VSN_TRIM_L_MASK);

sound/soc/codecs/aw88399.c

330

uint16_t reg_val;

sound/soc/codecs/aw88399.c

370

reg_val = (uint32_t)vcalb;

sound/soc/codecs/aw88399.c

372

regmap_write(aw_dev->regmap, AW88399_DSPVCALB_REG, reg_val);

sound/soc/codecs/aw88399.c

411

unsigned int reg_val;

sound/soc/codecs/aw88399.c

429

regmap_read(aw_dev->regmap, AW88399_HAGCST_REG, &reg_val);

sound/soc/codecs/aw88399.c

433

check_val = (reg_val & (~AW88399_CRC_CHECK_BITS_MASK)) >> AW88399_CRC_CHECK_START_BIT;

sound/soc/codecs/aw88399.c

453

unsigned int reg_val;

sound/soc/codecs/aw88399.c

46

unsigned int reg_val;

sound/soc/codecs/aw88399.c

474

ret = regmap_read(aw_dev->regmap, AW88399_HAGCST_REG, &reg_val);

sound/soc/codecs/aw88399.c

478

check_val = (reg_val & (~AW88399_CRC_CHECK_BITS_MASK)) >> AW88399_CRC_CHECK_START_BIT;

sound/soc/codecs/aw88399.c

49

ret = regmap_read(aw_dev->regmap, AW88399_SYSINT_REG, &reg_val);

sound/soc/codecs/aw88399.c

53

*int_status = reg_val;

sound/soc/codecs/aw88399.c

549

unsigned int reg_val;

sound/soc/codecs/aw88399.c

552

ret = regmap_read(aw_dev->regmap, AW88399_WDT_REG, &reg_val);

sound/soc/codecs/aw88399.c

555

if (!(reg_val & (~AW88399_WDT_CNT_MASK)))

sound/soc/codecs/aw88399.c

72

unsigned int reg_val;

sound/soc/codecs/aw88399.c

75

ret = regmap_read(aw_dev->regmap, AW88399_SYSST_REG, &reg_val);

sound/soc/codecs/aw88399.c

78

if ((reg_val & AW88399_BIT_PLL_CHECK) != AW88399_BIT_PLL_CHECK) {

sound/soc/codecs/aw88399.c

79

dev_err(aw_dev->dev, "check pll lock fail, reg_val:0x%04x", reg_val);

sound/soc/codecs/aw88399.c

844

unsigned int reg_val;

sound/soc/codecs/aw88399.c

847

aw_dev_dsp_read(aw_dev, AW88399_DSP_ROM_CHECK_ADDR, &reg_val, AW_DSP_16_DATA);

sound/soc/codecs/aw88399.c

848

if (reg_val != AW88399_DSP_ROM_CHECK_DATA) {

sound/soc/codecs/aw88399.c

850

reg_val, AW88399_DSP_ROM_CHECK_DATA);

sound/soc/codecs/aw88399.c

857

aw_dev_dsp_read(aw_dev, AW88399_DSP_CFG_ADDR, &reg_val, AW_DSP_16_DATA);

sound/soc/codecs/aw88399.c

858

if (reg_val != AW88399_DSP_ODD_NUM_BIT_TEST) {

sound/soc/codecs/aw88399.c

860

reg_val, AW88399_DSP_ODD_NUM_BIT_TEST);

sound/soc/codecs/aw88399.c

895

unsigned int reg_val;

sound/soc/codecs/aw88399.c

898

ret = regmap_read(aw_dev->regmap, AW88399_SYSCTRL_REG, &reg_val);

sound/soc/codecs/aw88399.c

903

if ((reg_val & (~AW88399_RCV_MODE_MASK)) == AW88399_RCV_MODE_RECEIVER_VALUE)

sound/soc/codecs/aw88399.c

914

u16 read_vol, reg_val;

sound/soc/codecs/aw88399.c

929

reg_val = reg_data[i + 1];

sound/soc/codecs/aw88399.c

932

aw88399->vcalb_init_val = reg_val;

sound/soc/codecs/aw88399.c

937

if (reg_val & (~AW88399_DSPBY_MASK))

sound/soc/codecs/aw88399.c

942

reg_val &= (AW88399_HMUTE_MASK | AW88399_PWDN_MASK |

sound/soc/codecs/aw88399.c

944

reg_val |= (AW88399_HMUTE_ENABLE_VALUE | AW88399_PWDN_POWER_DOWN_VALUE |

sound/soc/codecs/aw88399.c

949

reg_val &= AW88399_I2STXEN_MASK;

sound/soc/codecs/aw88399.c

950

reg_val |= AW88399_I2STXEN_DISABLE_VALUE;

sound/soc/codecs/aw88399.c

954

read_vol = (reg_val & (~AW88399_VOL_MASK)) >>

sound/soc/codecs/aw88399.c

960

if ((reg_val & (~AW88399_EF_DBMD_MASK)) == AW88399_EF_DBMD_OR_VALUE)

sound/soc/codecs/aw88399.c

965

aw88399->dither_st = reg_val & (~AW88399_DITHER_EN_MASK);

sound/soc/codecs/aw88399.c

969

aw88399->crc_init_val = reg_val;

sound/soc/codecs/aw88399.c

971

ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);

sound/soc/codecs/cs35l56.c

418

static unsigned int cs35l56_make_tdm_config_word(unsigned int reg_val, unsigned long mask)

sound/soc/codecs/cs35l56.c

426

reg_val &= ~(0x3f << channel_shift);

sound/soc/codecs/cs35l56.c

427

reg_val |= bit_num << channel_shift;

sound/soc/codecs/cs35l56.c

431

return reg_val;

sound/soc/codecs/da7213.c

271

static int da7213_get_alc_data(struct snd_soc_component *component, u8 reg_val)

sound/soc/codecs/da7213.c

280

snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL, reg_val);

sound/soc/codecs/da7213.c

284

reg_val | DA7213_ALC_DATA_MIDDLE);

sound/soc/codecs/da7213.c

289

reg_val | DA7213_ALC_DATA_TOP);

sound/soc/codecs/da7213.c

300

u8 reg_val;

sound/soc/codecs/da7213.c

315

reg_val = (offset_l & DA7213_ALC_OFFSET_15_8) >> 8;

sound/soc/codecs/da7213.c

316

snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_L, reg_val);

sound/soc/codecs/da7213.c

317

reg_val = (offset_l & DA7213_ALC_OFFSET_19_16) >> 16;

sound/soc/codecs/da7213.c

318

snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_L, reg_val);

sound/soc/codecs/da7213.c

320

reg_val = (offset_r & DA7213_ALC_OFFSET_15_8) >> 8;

sound/soc/codecs/da7213.c

321

snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_R, reg_val);

sound/soc/codecs/da7213.c

322

reg_val = (offset_r & DA7213_ALC_OFFSET_19_16) >> 16;

sound/soc/codecs/da7213.c

323

snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_R, reg_val);

sound/soc/codecs/da9055.c

449

static int da9055_get_alc_data(struct snd_soc_component *component, u8 reg_val)

sound/soc/codecs/da9055.c

458

snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);

sound/soc/codecs/da9055.c

462

reg_val | DA9055_ALC_DATA_MIDDLE);

sound/soc/codecs/da9055.c

467

reg_val | DA9055_ALC_DATA_TOP);

sound/soc/codecs/da9055.c

480

u8 reg_val, adc_left, adc_right, mic_left, mic_right;

sound/soc/codecs/da9055.c

521

reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;

sound/soc/codecs/da9055.c

522

snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_L, reg_val);

sound/soc/codecs/da9055.c

523

reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;

sound/soc/codecs/da9055.c

524

snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_L, reg_val);

sound/soc/codecs/da9055.c

526

reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;

sound/soc/codecs/da9055.c

527

snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_R, reg_val);

sound/soc/codecs/da9055.c

528

reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;

sound/soc/codecs/da9055.c

529

snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_R, reg_val);

sound/soc/codecs/msm8916-wcd-analog.c

434

u32 coarse, fine, reg_val, reg_addr;

sound/soc/codecs/msm8916-wcd-analog.c

466

reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |

sound/soc/codecs/msm8916-wcd-analog.c

470

reg_val);

sound/soc/codecs/nau8810.c

170

int i, reg, reg_val;

sound/soc/codecs/nau8810.c

177

regmap_read(nau8810->regmap, reg + i, &reg_val);

sound/soc/codecs/nau8810.c

181

tmp = cpu_to_be16(reg_val);

sound/soc/codecs/nau8822.c

186

u16 reg_val, *val;

sound/soc/codecs/nau8822.c

192

reg_val = snd_soc_component_read(component, reg + i);

sound/soc/codecs/nau8822.c

196

tmp = cpu_to_be16(reg_val);

sound/soc/codecs/rt1011.c

1665

unsigned int reg_val = 0, reg_bclk_inv = 0;

sound/soc/codecs/rt1011.c

1671

reg_val |= RT1011_I2S_TDM_MS_S;

sound/soc/codecs/rt1011.c

1693

reg_val |= RT1011_I2S_TDM_DF_LEFT;

sound/soc/codecs/rt1011.c

1696

reg_val |= RT1011_I2S_TDM_DF_PCM_A;

sound/soc/codecs/rt1011.c

1699

reg_val |= RT1011_I2S_TDM_DF_PCM_B;

sound/soc/codecs/rt1011.c

1710

reg_val);

sound/soc/codecs/rt1011.c

1730

unsigned int reg_val = 0;

sound/soc/codecs/rt1011.c

1741

reg_val |= RT1011_FS_SYS_PRE_MCLK;

sound/soc/codecs/rt1011.c

1746

reg_val |= RT1011_FS_SYS_PRE_BCLK;

sound/soc/codecs/rt1011.c

1749

reg_val |= RT1011_FS_SYS_PRE_PLL1;

sound/soc/codecs/rt1011.c

1752

reg_val |= RT1011_FS_SYS_PRE_RCCLK;

sound/soc/codecs/rt1011.c

1759

RT1011_FS_SYS_PRE_MASK, reg_val);

sound/soc/codecs/rt1015.c

750

unsigned int reg_val = 0, reg_val2 = 0;

sound/soc/codecs/rt1015.c

754

reg_val |= RT1015_TCON_TDM_MS_M;

sound/soc/codecs/rt1015.c

757

reg_val |= RT1015_TCON_TDM_MS_S;

sound/soc/codecs/rt1015.c

778

reg_val |= RT1015_I2S_M_DF_LEFT;

sound/soc/codecs/rt1015.c

782

reg_val |= RT1015_I2S_M_DF_PCM_A;

sound/soc/codecs/rt1015.c

786

reg_val |= RT1015_I2S_M_DF_PCM_B;

sound/soc/codecs/rt1015.c

795

reg_val);

sound/soc/codecs/rt1015.c

806

unsigned int reg_val = 0;

sound/soc/codecs/rt1015.c

813

reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;

sound/soc/codecs/rt1015.c

817

reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;

sound/soc/codecs/rt1015.c

832

RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);

sound/soc/codecs/rt1016.c

367

unsigned int reg_val = 0;

sound/soc/codecs/rt1016.c

371

reg_val |= RT1016_I2S_MS_M;

sound/soc/codecs/rt1016.c

375

reg_val |= RT1016_I2S_MS_S;

sound/soc/codecs/rt1016.c

385

reg_val |= RT1016_I2S_BCLK_POL_INV;

sound/soc/codecs/rt1016.c

396

reg_val |= RT1016_I2S_DF_LEFT;

sound/soc/codecs/rt1016.c

400

reg_val |= RT1016_I2S_DF_PCM_A;

sound/soc/codecs/rt1016.c

404

reg_val |= RT1016_I2S_DF_PCM_B;

sound/soc/codecs/rt1016.c

413

RT1016_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt1016.c

422

unsigned int reg_val = 0;

sound/soc/codecs/rt1016.c

429

reg_val |= RT1016_CLK_SYS_SEL_MCLK;

sound/soc/codecs/rt1016.c

433

reg_val |= RT1016_CLK_SYS_SEL_PLL;

sound/soc/codecs/rt1016.c

448

RT1016_CLK_SYS_SEL_MASK, reg_val);

sound/soc/codecs/rt1019.c

249

unsigned int reg_val = 0, reg_val2 = 0;

sound/soc/codecs/rt1019.c

266

reg_val |= RT1019_I2S_DF_LEFT;

sound/soc/codecs/rt1019.c

270

reg_val |= RT1019_I2S_DF_PCM_A_R;

sound/soc/codecs/rt1019.c

274

reg_val |= RT1019_I2S_DF_PCM_B_R;

sound/soc/codecs/rt1019.c

282

RT1019_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt1019.c

294

unsigned int reg_val = 0;

sound/soc/codecs/rt1019.c

301

reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK;

sound/soc/codecs/rt1019.c

305

reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL;

sound/soc/codecs/rt1019.c

319

RT1019_CLK_SYS_PRE_SEL_MASK, reg_val);

sound/soc/codecs/rt1305.c

697

unsigned int reg_val = 0, reg1_val = 0;

sound/soc/codecs/rt1305.c

701

reg_val |= RT1305_SEL_I2S_OUT_MODE_M;

sound/soc/codecs/rt1305.c

705

reg_val |= RT1305_SEL_I2S_OUT_MODE_S;

sound/soc/codecs/rt1305.c

741

RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);

sound/soc/codecs/rt1305.c

757

unsigned int reg_val = 0;

sound/soc/codecs/rt1305.c

764

reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;

sound/soc/codecs/rt1305.c

770

reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;

sound/soc/codecs/rt1305.c

773

reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;

sound/soc/codecs/rt1305.c

780

RT1305_SEL_FS_SYS_PRE_MASK, reg_val);

sound/soc/codecs/rt1308.c

523

unsigned int reg_val = 0, reg1_val = 0;

sound/soc/codecs/rt1308.c

537

reg_val |= RT1308_I2S_DF_SEL_LEFT;

sound/soc/codecs/rt1308.c

540

reg_val |= RT1308_I2S_DF_SEL_PCM_A;

sound/soc/codecs/rt1308.c

543

reg_val |= RT1308_I2S_DF_SEL_PCM_B;

sound/soc/codecs/rt1308.c

563

reg_val);

sound/soc/codecs/rt1308.c

579

unsigned int reg_val = 0;

sound/soc/codecs/rt1308.c

586

reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;

sound/soc/codecs/rt1308.c

592

reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;

sound/soc/codecs/rt1308.c

595

reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;

sound/soc/codecs/rt1308.c

598

reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;

sound/soc/codecs/rt1308.c

605

RT1308_SEL_FS_SYS_MASK, reg_val);

sound/soc/codecs/rt1318.c

684

unsigned int reg_val = 0, reg_val2 = 0;

sound/soc/codecs/rt1318.c

701

reg_val |= RT1318_FMT_LEFT_J;

sound/soc/codecs/rt1318.c

705

reg_val |= RT1318_FMT_PCM_A_R;

sound/soc/codecs/rt1318.c

709

reg_val |= RT1318_FMT_PCM_B_R;

sound/soc/codecs/rt1318.c

717

RT1318_I2S_FMT_MASK, reg_val);

sound/soc/codecs/rt1318.c

729

int reg_val = 0;

sound/soc/codecs/rt1318.c

736

reg_val |= RT1318_SYSCLK_BCLK;

sound/soc/codecs/rt1318.c

739

reg_val |= RT1318_SYSCLK_SDW;

sound/soc/codecs/rt1318.c

742

reg_val |= RT1318_SYSCLK_PLL2F;

sound/soc/codecs/rt1318.c

745

reg_val |= RT1318_SYSCLK_PLL2B;

sound/soc/codecs/rt1318.c

748

reg_val |= RT1318_SYSCLK_MCLK;

sound/soc/codecs/rt1318.c

751

reg_val |= RT1318_SYSCLK_RC1;

sound/soc/codecs/rt1318.c

754

reg_val |= RT1318_SYSCLK_RC2;

sound/soc/codecs/rt1318.c

757

reg_val |= RT1318_SYSCLK_RC3;

sound/soc/codecs/rt1318.c

768

RT1318_SYSCLK_SEL_MASK, reg_val);

sound/soc/codecs/rt5514.c

813

unsigned int reg_val = 0;

sound/soc/codecs/rt5514.c

820

reg_val |= RT5514_I2S_LR_INV;

sound/soc/codecs/rt5514.c

824

reg_val |= RT5514_I2S_BP_INV;

sound/soc/codecs/rt5514.c

828

reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;

sound/soc/codecs/rt5514.c

840

reg_val |= RT5514_I2S_DF_LEFT;

sound/soc/codecs/rt5514.c

844

reg_val |= RT5514_I2S_DF_PCM_A;

sound/soc/codecs/rt5514.c

848

reg_val |= RT5514_I2S_DF_PCM_B;

sound/soc/codecs/rt5514.c

857

reg_val);

sound/soc/codecs/rt5514.c

867

unsigned int reg_val = 0;

sound/soc/codecs/rt5514.c

874

reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;

sound/soc/codecs/rt5514.c

878

reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;

sound/soc/codecs/rt5514.c

887

RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);

sound/soc/codecs/rt5616.c

1015

unsigned int reg_val = 0;

sound/soc/codecs/rt5616.c

1022

reg_val |= RT5616_I2S_MS_S;

sound/soc/codecs/rt5616.c

1033

reg_val |= RT5616_I2S_BP_INV;

sound/soc/codecs/rt5616.c

1043

reg_val |= RT5616_I2S_DF_LEFT;

sound/soc/codecs/rt5616.c

1046

reg_val |= RT5616_I2S_DF_PCM_A;

sound/soc/codecs/rt5616.c

1049

reg_val |= RT5616_I2S_DF_PCM_B;

sound/soc/codecs/rt5616.c

1057

RT5616_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5616.c

1067

unsigned int reg_val = 0;

sound/soc/codecs/rt5616.c

1074

reg_val |= RT5616_SCLK_SRC_MCLK;

sound/soc/codecs/rt5616.c

1077

reg_val |= RT5616_SCLK_SRC_PLL1;

sound/soc/codecs/rt5616.c

1085

RT5616_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5631.c

1213

u16 reg_val;

sound/soc/codecs/rt5631.c

1220

u16 reg_val;

sound/soc/codecs/rt5631.c

1399

coeff_div[coeff].reg_val);

sound/soc/codecs/rt5631.c

1498

codec_master_pll_div[i].reg_val);

sound/soc/codecs/rt5631.c

1517

codec_slave_pll_div[i].reg_val);

sound/soc/codecs/rt5640.c

1772

unsigned int reg_val = 0;

sound/soc/codecs/rt5640.c

1780

reg_val |= RT5640_I2S_MS_S;

sound/soc/codecs/rt5640.c

1791

reg_val |= RT5640_I2S_BP_INV;

sound/soc/codecs/rt5640.c

1801

reg_val |= RT5640_I2S_DF_LEFT;

sound/soc/codecs/rt5640.c

1804

reg_val |= RT5640_I2S_DF_PCM_A;

sound/soc/codecs/rt5640.c

1807

reg_val |= RT5640_I2S_DF_PCM_B;

sound/soc/codecs/rt5640.c

1821

RT5640_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5640.c

1826

RT5640_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5640.c

1837

unsigned int reg_val = 0;

sound/soc/codecs/rt5640.c

1847

reg_val |= RT5640_SCLK_SRC_MCLK;

sound/soc/codecs/rt5640.c

1850

reg_val |= RT5640_SCLK_SRC_PLL1;

sound/soc/codecs/rt5640.c

1854

reg_val |= RT5640_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5640.c

1863

RT5640_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5645.c

2833

unsigned int reg_val = 0, pol_sft;

sound/soc/codecs/rt5645.c

2849

reg_val |= RT5645_I2S_MS_S;

sound/soc/codecs/rt5645.c

2860

reg_val |= (1 << pol_sft);

sound/soc/codecs/rt5645.c

2870

reg_val |= RT5645_I2S_DF_LEFT;

sound/soc/codecs/rt5645.c

2873

reg_val |= RT5645_I2S_DF_PCM_A;

sound/soc/codecs/rt5645.c

2876

reg_val |= RT5645_I2S_DF_PCM_B;

sound/soc/codecs/rt5645.c

2885

RT5645_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5645.c

2890

RT5645_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5645.c

2904

unsigned int reg_val = 0;

sound/soc/codecs/rt5645.c

2911

reg_val |= RT5645_SCLK_SRC_MCLK;

sound/soc/codecs/rt5645.c

2914

reg_val |= RT5645_SCLK_SRC_PLL1;

sound/soc/codecs/rt5645.c

2917

reg_val |= RT5645_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5645.c

2924

RT5645_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5651.c

1352

unsigned int reg_val = 0;

sound/soc/codecs/rt5651.c

1359

reg_val |= RT5651_I2S_MS_S;

sound/soc/codecs/rt5651.c

1370

reg_val |= RT5651_I2S_BP_INV;

sound/soc/codecs/rt5651.c

1380

reg_val |= RT5651_I2S_DF_LEFT;

sound/soc/codecs/rt5651.c

1383

reg_val |= RT5651_I2S_DF_PCM_A;

sound/soc/codecs/rt5651.c

1386

reg_val |= RT5651_I2S_DF_PCM_B;

sound/soc/codecs/rt5651.c

1396

RT5651_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5651.c

1401

RT5651_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5651.c

1415

unsigned int reg_val = 0;

sound/soc/codecs/rt5651.c

1423

reg_val |= RT5651_SCLK_SRC_MCLK;

sound/soc/codecs/rt5651.c

1426

reg_val |= RT5651_SCLK_SRC_PLL1;

sound/soc/codecs/rt5651.c

1430

reg_val |= RT5651_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5651.c

1439

RT5651_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5659.c

3363

unsigned int reg_val = 0;

sound/soc/codecs/rt5659.c

3370

reg_val |= RT5659_I2S_MS_S;

sound/soc/codecs/rt5659.c

3381

reg_val |= RT5659_I2S_BP_INV;

sound/soc/codecs/rt5659.c

3391

reg_val |= RT5659_I2S_DF_LEFT;

sound/soc/codecs/rt5659.c

3394

reg_val |= RT5659_I2S_DF_PCM_A;

sound/soc/codecs/rt5659.c

3397

reg_val |= RT5659_I2S_DF_PCM_B;

sound/soc/codecs/rt5659.c

3407

RT5659_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5659.c

3412

RT5659_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5659.c

3417

RT5659_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5659.c

3430

unsigned int reg_val = 0;

sound/soc/codecs/rt5659.c

3442

reg_val |= RT5659_SCLK_SRC_MCLK;

sound/soc/codecs/rt5659.c

3445

reg_val |= RT5659_SCLK_SRC_PLL1;

sound/soc/codecs/rt5659.c

3448

reg_val |= RT5659_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5659.c

3455

RT5659_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5660.c

905

unsigned int reg_val = 0;

sound/soc/codecs/rt5660.c

913

reg_val |= RT5660_I2S_MS_S;

sound/soc/codecs/rt5660.c

926

reg_val |= RT5660_I2S_BP_INV;

sound/soc/codecs/rt5660.c

938

reg_val |= RT5660_I2S_DF_LEFT;

sound/soc/codecs/rt5660.c

942

reg_val |= RT5660_I2S_DF_PCM_A;

sound/soc/codecs/rt5660.c

946

reg_val |= RT5660_I2S_DF_PCM_B;

sound/soc/codecs/rt5660.c

957

RT5660_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5660.c

973

unsigned int reg_val = 0;

sound/soc/codecs/rt5660.c

980

reg_val |= RT5660_SCLK_SRC_MCLK;

sound/soc/codecs/rt5660.c

984

reg_val |= RT5660_SCLK_SRC_PLL1;

sound/soc/codecs/rt5660.c

988

reg_val |= RT5660_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5660.c

997

reg_val);

sound/soc/codecs/rt5663.c

2814

unsigned int reg_val = 0;

sound/soc/codecs/rt5663.c

2820

reg_val |= RT5663_I2S_MS_S;

sound/soc/codecs/rt5663.c

2830

reg_val |= RT5663_I2S_BP_INV;

sound/soc/codecs/rt5663.c

2840

reg_val |= RT5663_I2S_DF_LEFT;

sound/soc/codecs/rt5663.c

2843

reg_val |= RT5663_I2S_DF_PCM_A;

sound/soc/codecs/rt5663.c

2846

reg_val |= RT5663_I2S_DF_PCM_B;

sound/soc/codecs/rt5663.c

2853

RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5663.c

2863

unsigned int reg_val = 0;

sound/soc/codecs/rt5663.c

2870

reg_val |= RT5663_SCLK_SRC_MCLK;

sound/soc/codecs/rt5663.c

2873

reg_val |= RT5663_SCLK_SRC_PLL1;

sound/soc/codecs/rt5663.c

2876

reg_val |= RT5663_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5663.c

2883

reg_val);

sound/soc/codecs/rt5665.c

4120

unsigned int reg_val = 0;

sound/soc/codecs/rt5665.c

4127

reg_val |= RT5665_I2S_MS_S;

sound/soc/codecs/rt5665.c

4138

reg_val |= RT5665_I2S_BP_INV;

sound/soc/codecs/rt5665.c

4148

reg_val |= RT5665_I2S_DF_LEFT;

sound/soc/codecs/rt5665.c

4151

reg_val |= RT5665_I2S_DF_PCM_A;

sound/soc/codecs/rt5665.c

4154

reg_val |= RT5665_I2S_DF_PCM_B;

sound/soc/codecs/rt5665.c

4165

RT5665_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5665.c

4171

RT5665_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5665.c

4176

RT5665_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5665.c

4189

unsigned int reg_val = 0, src = 0;

sound/soc/codecs/rt5665.c

4196

reg_val |= RT5665_SCLK_SRC_MCLK;

sound/soc/codecs/rt5665.c

4200

reg_val |= RT5665_SCLK_SRC_PLL1;

sound/soc/codecs/rt5665.c

4204

reg_val |= RT5665_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5665.c

4212

RT5665_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5668.c

1966

unsigned int reg_val = 0, tdm_ctrl = 0;

sound/soc/codecs/rt5668.c

1983

reg_val |= RT5668_I2S_BP_INV;

sound/soc/codecs/rt5668.c

2007

reg_val |= RT5668_I2S_DF_LEFT;

sound/soc/codecs/rt5668.c

2011

reg_val |= RT5668_I2S_DF_PCM_A;

sound/soc/codecs/rt5668.c

2015

reg_val |= RT5668_I2S_DF_PCM_B;

sound/soc/codecs/rt5668.c

2025

RT5668_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5668.c

2034

reg_val |= RT5668_I2S2_MS_S;

sound/soc/codecs/rt5668.c

2037

RT5668_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5668.c

2050

unsigned int reg_val = 0, src = 0;

sound/soc/codecs/rt5668.c

2057

reg_val |= RT5668_SCLK_SRC_MCLK;

sound/soc/codecs/rt5668.c

2061

reg_val |= RT5668_SCLK_SRC_PLL1;

sound/soc/codecs/rt5668.c

2065

reg_val |= RT5668_SCLK_SRC_PLL2;

sound/soc/codecs/rt5668.c

2069

reg_val |= RT5668_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5668.c

2077

RT5668_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5670.c

2443

unsigned int reg_val = 0;

sound/soc/codecs/rt5670.c

2450

reg_val |= RT5670_I2S_MS_S;

sound/soc/codecs/rt5670.c

2461

reg_val |= RT5670_I2S_BP_INV;

sound/soc/codecs/rt5670.c

2471

reg_val |= RT5670_I2S_DF_LEFT;

sound/soc/codecs/rt5670.c

2474

reg_val |= RT5670_I2S_DF_PCM_A;

sound/soc/codecs/rt5670.c

2477

reg_val |= RT5670_I2S_DF_PCM_B;

sound/soc/codecs/rt5670.c

2487

RT5670_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5670.c

2492

RT5670_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5670.c

2505

unsigned int reg_val = 0;

sound/soc/codecs/rt5670.c

2509

reg_val |= RT5670_SCLK_SRC_MCLK;

sound/soc/codecs/rt5670.c

2512

reg_val |= RT5670_SCLK_SRC_PLL1;

sound/soc/codecs/rt5670.c

2515

reg_val |= RT5670_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5670.c

2522

RT5670_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5677.c

4377

unsigned int reg_val = 0;

sound/soc/codecs/rt5677.c

4384

reg_val |= RT5677_I2S_MS_S;

sound/soc/codecs/rt5677.c

4395

reg_val |= RT5677_I2S_BP_INV;

sound/soc/codecs/rt5677.c

4405

reg_val |= RT5677_I2S_DF_LEFT;

sound/soc/codecs/rt5677.c

4408

reg_val |= RT5677_I2S_DF_PCM_A;

sound/soc/codecs/rt5677.c

4411

reg_val |= RT5677_I2S_DF_PCM_B;

sound/soc/codecs/rt5677.c

4421

RT5677_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5677.c

4426

RT5677_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5677.c

4431

RT5677_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5677.c

4436

RT5677_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5677.c

4451

unsigned int reg_val = 0;

sound/soc/codecs/rt5677.c

4458

reg_val |= RT5677_SCLK_SRC_MCLK;

sound/soc/codecs/rt5677.c

4461

reg_val |= RT5677_SCLK_SRC_PLL1;

sound/soc/codecs/rt5677.c

4464

reg_val |= RT5677_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5677.c

4471

RT5677_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5682.c

2225

unsigned int reg_val = 0, tdm_ctrl = 0;

sound/soc/codecs/rt5682.c

2242

reg_val |= RT5682_I2S_BP_INV;

sound/soc/codecs/rt5682.c

2266

reg_val |= RT5682_I2S_DF_LEFT;

sound/soc/codecs/rt5682.c

2270

reg_val |= RT5682_I2S_DF_PCM_A;

sound/soc/codecs/rt5682.c

2274

reg_val |= RT5682_I2S_DF_PCM_B;

sound/soc/codecs/rt5682.c

2284

RT5682_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5682.c

2293

reg_val |= RT5682_I2S2_MS_S;

sound/soc/codecs/rt5682.c

2296

RT5682_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5682.c

2309

unsigned int reg_val = 0, src = 0;

sound/soc/codecs/rt5682.c

2316

reg_val |= RT5682_SCLK_SRC_MCLK;

sound/soc/codecs/rt5682.c

2320

reg_val |= RT5682_SCLK_SRC_PLL1;

sound/soc/codecs/rt5682.c

2324

reg_val |= RT5682_SCLK_SRC_PLL2;

sound/soc/codecs/rt5682.c

2328

reg_val |= RT5682_SCLK_SRC_RCCLK;

sound/soc/codecs/rt5682.c

2336

RT5682_SCLK_SRC_MASK, reg_val);

sound/soc/codecs/rt5682s.c

2133

unsigned int reg_val = 0, tdm_ctrl = 0;

sound/soc/codecs/rt5682s.c

2150

reg_val |= RT5682S_I2S_BP_INV;

sound/soc/codecs/rt5682s.c

2174

reg_val |= RT5682S_I2S_DF_LEFT;

sound/soc/codecs/rt5682s.c

2178

reg_val |= RT5682S_I2S_DF_PCM_A;

sound/soc/codecs/rt5682s.c

2182

reg_val |= RT5682S_I2S_DF_PCM_B;

sound/soc/codecs/rt5682s.c

2192

RT5682S_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt5682s.c

2201

reg_val |= RT5682S_I2S2_MS_S;

sound/soc/codecs/rt5682s.c

2204

RT5682S_I2S_DF_MASK, reg_val);

sound/soc/codecs/rt715-sdca.c

111

static inline unsigned int rt715_sdca_get_gain(unsigned int reg_val,

sound/soc/codecs/rt715-sdca.c

116

if (reg_val & BIT(15)) {

sound/soc/codecs/rt715-sdca.c

117

reg_val = ~(reg_val - 1) & 0xffff;

sound/soc/codecs/rt715-sdca.c

120

reg_val *= 1000;

sound/soc/codecs/rt715-sdca.c

121

reg_val >>= 8;

sound/soc/codecs/rt715-sdca.c

123

reg_val = gain_sft - reg_val / RT715_SDCA_DB_STEP;

sound/soc/codecs/rt715-sdca.c

125

reg_val = gain_sft + reg_val / RT715_SDCA_DB_STEP;

sound/soc/codecs/rt715-sdca.c

127

return reg_val;

sound/soc/codecs/tas2562.c

475

u32 reg_val;

sound/soc/codecs/tas2562.c

477

reg_val = float_vol_db_lookup[ucontrol->value.integer.value[0]/2];

sound/soc/codecs/tas2562.c

479

(reg_val & 0xff));

sound/soc/codecs/tas2562.c

483

((reg_val >> 8) & 0xff));

sound/soc/codecs/tas2562.c

487

((reg_val >> 16) & 0xff));

sound/soc/codecs/tas2562.c

491

((reg_val >> 24) & 0xff));

sound/soc/codecs/tas6424.c

303

unsigned int reg_val;

sound/soc/codecs/tas6424.c

305

if (!regmap_read(tas6424->regmap, TAS6424_DC_DIAG_CTRL1, &reg_val))

sound/soc/codecs/tas6424.c

306

no_auto_diags = reg_val & TAS6424_LDGBYPASS_MASK;

sound/soc/codecs/wcd-mbhc-v2.c

105

u32 reg_val = ((mbhc->cfg->v_hs_max - HS_VREF_MIN_VAL) / 100);

sound/soc/codecs/wcd-mbhc-v2.c

107

wcd_mbhc_write_field(mbhc, WCD_MBHC_HS_VREF, reg_val);

sound/soc/fsl/fsl_audmix.c

118

unsigned int reg_val, val, mix_clk;

sound/soc/fsl/fsl_audmix.c

121

reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);

sound/soc/fsl/fsl_audmix.c

122

mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)

sound/soc/fsl/fsl_audmix.c

157

unsigned int reg_val, val, mask = 0, ctr = 0;

sound/soc/fsl/fsl_audmix.c

161

reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);

sound/soc/fsl/fsl_audmix.c

164

out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK)

sound/soc/fsl/fsl_audmix.c

166

mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)

sound/soc/fsl/fsl_micfil.c

341

u32 reg_val = 0;

sound/soc/fsl/fsl_micfil.c

350

reg_val |= val << MICFIL_DC_CHX_SHIFT(i);

sound/soc/fsl/fsl_micfil.c

354

MICFIL_DC_CTRL_CONFIG, reg_val);

sound/soc/fsl/fsl_ssi.c

1251

u32 reg_val;

sound/soc/fsl/fsl_ssi.c

1270

regmap_read(regs, REG_SSI_SACDAT, &reg_val);

sound/soc/fsl/fsl_ssi.c

1271

val = (reg_val >> 4) & 0xffff;

sound/soc/kirkwood/kirkwood-i2s.c

121

reg_val = readl(base + A38X_PLL_CONF_REG0);

sound/soc/kirkwood/kirkwood-i2s.c

122

reg_val &= ~A38X_PLL_FB_CLK_DIV_MASK;

sound/soc/kirkwood/kirkwood-i2s.c

123

reg_val |= (fb_clk_div << A38X_PLL_FB_CLK_DIV_OFFSET);

sound/soc/kirkwood/kirkwood-i2s.c

124

writel(reg_val, base + A38X_PLL_CONF_REG0);

sound/soc/kirkwood/kirkwood-i2s.c

126

reg_val = readl(base + A38X_PLL_CONF_REG2);

sound/soc/kirkwood/kirkwood-i2s.c

127

reg_val &= ~A38X_PLL_AUDIO_POSTDIV_MASK;

sound/soc/kirkwood/kirkwood-i2s.c

128

reg_val |= audio_postdiv;

sound/soc/kirkwood/kirkwood-i2s.c

129

writel(reg_val, base + A38X_PLL_CONF_REG2);

sound/soc/kirkwood/kirkwood-i2s.c

131

reg_val = readl(base + A38X_PLL_CONF_REG1);

sound/soc/kirkwood/kirkwood-i2s.c

132

reg_val &= ~A38X_PLL_FREQ_OFFSET_MASK;

sound/soc/kirkwood/kirkwood-i2s.c

133

reg_val |= freq_offset;

sound/soc/kirkwood/kirkwood-i2s.c

134

writel(reg_val, base + A38X_PLL_CONF_REG1);

sound/soc/kirkwood/kirkwood-i2s.c

139

reg_val |= A38X_PLL_SW_RESET;

sound/soc/kirkwood/kirkwood-i2s.c

140

writel(reg_val, base + A38X_PLL_CONF_REG1);

sound/soc/kirkwood/kirkwood-i2s.c

146

reg_val |= A38X_PLL_FREQ_OFFSET_VALID;

sound/soc/kirkwood/kirkwood-i2s.c

147

writel(reg_val, base + A38X_PLL_CONF_REG1);

sound/soc/kirkwood/kirkwood-i2s.c

57

u32 reg_val;

sound/soc/kirkwood/kirkwood-i2s.c

69

reg_val = readl(priv->soc_control);

sound/soc/kirkwood/kirkwood-i2s.c

71

reg_val |= A38X_SPDIF_MODE_ENABLE;

sound/soc/kirkwood/kirkwood-i2s.c

74

reg_val &= ~A38X_SPDIF_MODE_ENABLE;

sound/soc/kirkwood/kirkwood-i2s.c

77

writel(reg_val, priv->soc_control);

sound/soc/kirkwood/kirkwood-i2s.c

90

u32 reg_val;

sound/soc/kirkwood/kirkwood-i2s.c

95

reg_val = readl(base + A38X_PLL_CONF_REG1);

sound/soc/kirkwood/kirkwood-i2s.c

96

reg_val &= ~A38X_PLL_FREQ_OFFSET_VALID;

sound/soc/kirkwood/kirkwood-i2s.c

97

reg_val &= ~A38X_PLL_SW_RESET;

sound/soc/kirkwood/kirkwood-i2s.c

98

writel(reg_val, base + A38X_PLL_CONF_REG1);

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

107

unsigned int reg_val;

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

111

{ .rate = 8000, .reg_val = MT8365_FS_8K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

112

{ .rate = 11025, .reg_val = MT8365_FS_11D025K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

113

{ .rate = 12000, .reg_val = MT8365_FS_12K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

114

{ .rate = 16000, .reg_val = MT8365_FS_16K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

115

{ .rate = 22050, .reg_val = MT8365_FS_22D05K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

116

{ .rate = 24000, .reg_val = MT8365_FS_24K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

117

{ .rate = 32000, .reg_val = MT8365_FS_32K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

118

{ .rate = 44100, .reg_val = MT8365_FS_44D1K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

119

{ .rate = 48000, .reg_val = MT8365_FS_48K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

120

{ .rate = 88200, .reg_val = MT8365_FS_88D2K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

121

{ .rate = 96000, .reg_val = MT8365_FS_96K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

122

{ .rate = 176400, .reg_val = MT8365_FS_176D4K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

123

{ .rate = 192000, .reg_val = MT8365_FS_192K },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

132

return mt8365_afe_fs_rates[i].reg_val;

sound/soc/soc-dapm.c

3407

unsigned int reg_val, val, rval = 0;

sound/soc/soc-dapm.c

3411

reg_val = dapm_read(dapm, reg);

sound/soc/soc-dapm.c

3412

val = (reg_val >> shift) & mask;

sound/soc/soc-dapm.c

3415

reg_val = dapm_read(dapm, mc->rreg);

sound/soc/soc-dapm.c

3418

rval = (reg_val >> mc->rshift) & mask;

sound/soc/soc-dapm.c

3420

reg_val = snd_soc_dapm_kcontrol_get_value(kcontrol);

sound/soc/soc-dapm.c

3421

val = reg_val & mask;

sound/soc/soc-dapm.c

3424

rval = (reg_val >> width) & mask;

sound/soc/soc-dapm.c

3547

unsigned int reg_val, val;

sound/soc/soc-dapm.c

3551

reg_val = dapm_read(dapm, e->reg);

sound/soc/soc-dapm.c

3553

reg_val = snd_soc_dapm_kcontrol_get_value(kcontrol);

sound/soc/soc-dapm.c

3557

val = (reg_val >> e->shift_l) & e->mask;

sound/soc/soc-dapm.c

3560

val = (reg_val >> e->shift_r) & e->mask;

sound/soc/soc-ops.c

113

static int sdca_soc_q78_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val,

sound/soc/soc-ops.c

117

int val = reg_val;

sound/soc/soc-ops.c

133

int reg_val;

sound/soc/soc-ops.c

138

reg_val = val + mc->min;

sound/soc/soc-ops.c

139

ret_val = (int)((reg_val * mc->shift) << 8) / 100;

sound/soc/soc-ops.c

144

static int soc_mixer_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val,

sound/soc/soc-ops.c

148

int val = (reg_val >> shift) & mask;

sound/soc/soc-ops.c

171

unsigned int reg_val;

sound/soc/soc-ops.c

176

reg_val = val + mc->min;

sound/soc/soc-ops.c

178

return (reg_val & mask) << shift;

sound/soc/soc-ops.c

295

unsigned int reg_val;

sound/soc/soc-ops.c

303

reg_val = snd_soc_component_read(component, mc->reg);

sound/soc/soc-ops.c

304

val = reg_to_ctl(mc, reg_val, mask, mc->shift, max, sx);

sound/soc/soc-ops.c

310

val = reg_to_ctl(mc, reg_val, mask, mc->rshift, max, sx);

sound/soc/soc-ops.c

312

reg_val = snd_soc_component_read(component, mc->rreg);

sound/soc/soc-ops.c

313

val = reg_to_ctl(mc, reg_val, mask, mc->shift, max, sx);

sound/soc/soc-ops.c

64

unsigned int reg_val;

sound/soc/soc-ops.c

66

reg_val = snd_soc_component_read(component, e->reg);

sound/soc/soc-ops.c

67

val = (reg_val >> e->shift_l) & e->mask;

sound/soc/soc-ops.c

71

val = (reg_val >> e->shift_r) & e->mask;

sound/soc/sof/amd/acp-stream.c

102

reg_val = desc->sram_pte_offset + offset;

sound/soc/sof/amd/acp-stream.c

103

snd_sof_dsp_write(sdev, ACP_DSP_BAR, pte_reg, reg_val | BIT(31));

sound/soc/sof/amd/acp-stream.c

32

u32 low, high, offset, reg_val;

sound/soc/sunxi/sun4i-spdif.c

276

u32 reg_val;

sound/soc/sunxi/sun4i-spdif.c

361

reg_val = 0;

sound/soc/sunxi/sun4i-spdif.c

362

reg_val |= SUN4I_SPDIF_TXCFG_ASS;

sound/soc/sunxi/sun4i-spdif.c

363

reg_val |= fmt; /* set non audio and bit depth */

sound/soc/sunxi/sun4i-spdif.c

364

reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;

sound/soc/sunxi/sun4i-spdif.c

365

reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);

sound/soc/sunxi/sun4i-spdif.c

366

regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);

sound/soc/tegra/tegra210_ahub.c

30

unsigned int reg_val;

sound/soc/tegra/tegra210_ahub.c

33

reg_val = snd_soc_component_read(cmpnt, reg);

sound/soc/tegra/tegra210_ahub.c

34

reg_val &= ahub->soc_data->mask[i];

sound/soc/tegra/tegra210_ahub.c

36

if (reg_val) {

sound/soc/tegra/tegra210_ahub.c

37

bit_pos = ffs(reg_val) +

sound/soc/tegra/tegra210_ahub.c

64

unsigned int i, bit_pos, reg_idx = 0, reg_val = 0;

sound/soc/tegra/tegra210_ahub.c

74

reg_val = BIT(bit_pos);

sound/soc/tegra/tegra210_ahub.c

84

update[i].val = (i == reg_idx) ? reg_val : 0;

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

538

uint64_t set_reg_id, clr_reg_id, reg_val;

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

555

reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

556

TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

558

KVM_ARM64_SYS_REG(set_reg_id), reg_val);

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

560

reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

561

TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

563

KVM_ARM64_SYS_REG(clr_reg_id), reg_val);

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

572

reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

573

TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

575

KVM_ARM64_SYS_REG(set_reg_id), reg_val);

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

577

reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

578

TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

580

KVM_ARM64_SYS_REG(clr_reg_id), reg_val);

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

139

void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val)

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

143

writel(reg_val, base + offset);

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

152

uint32_t mask, uint32_t reg_val)

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

156

tmp |= (reg_val & mask);