arch/alpha/include/asm/core_marvel.h

30

volatile unsigned long csr __attribute__((aligned(16)));

arch/alpha/include/asm/core_marvel.h

65

#define EV7_CSR_OFFSET(name) ((unsigned long)&((ev7_csrs *)NULL)->name.csr)

arch/alpha/include/asm/core_marvel.h

71

volatile unsigned long csr __attribute__((aligned(64)));

arch/alpha/include/asm/core_titan.h

32

volatile unsigned long csr __attribute__((aligned(64)));

arch/alpha/include/asm/core_tsunami.h

31

volatile unsigned long csr __attribute__((aligned(64)));

arch/alpha/include/asm/core_wildfire.h

37

volatile unsigned long csr __attribute__((aligned(64)));

arch/alpha/include/asm/core_wildfire.h

41

volatile unsigned long csr __attribute__((aligned(256)));

arch/alpha/include/asm/core_wildfire.h

45

volatile unsigned long csr __attribute__((aligned(2048)));

arch/alpha/kernel/core_marvel.c

1087

agp->capability.lw = csrs->AGP_STAT.csr;

arch/alpha/kernel/core_marvel.c

1093

agp->mode.lw = csrs->AGP_CMD.csr;

arch/alpha/kernel/core_marvel.c

181

csrs->POx_ERR_SUM.csr = -1UL;

arch/alpha/kernel/core_marvel.c

182

csrs->POx_TLB_ERR.csr = -1UL;

arch/alpha/kernel/core_marvel.c

183

csrs->POx_SPL_COMPLT.csr = -1UL;

arch/alpha/kernel/core_marvel.c

184

csrs->POx_TRANS_SUM.csr = -1UL;

arch/alpha/kernel/core_marvel.c

192

p7csrs->PO7_ERROR_SUM.csr = -1UL;

arch/alpha/kernel/core_marvel.c

193

p7csrs->PO7_UNCRR_SYM.csr = -1UL;

arch/alpha/kernel/core_marvel.c

194

p7csrs->PO7_CRRCT_SYM.csr = -1UL;

arch/alpha/kernel/core_marvel.c

265

io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;

arch/alpha/kernel/core_marvel.c

266

io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;

arch/alpha/kernel/core_marvel.c

267

io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;

arch/alpha/kernel/core_marvel.c

289

csrs->POx_WBASE[0].csr =

arch/alpha/kernel/core_marvel.c

291

csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;

arch/alpha/kernel/core_marvel.c

292

csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);

arch/alpha/kernel/core_marvel.c

297

csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;

arch/alpha/kernel/core_marvel.c

298

csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;

arch/alpha/kernel/core_marvel.c

299

csrs->POx_TBASE[1].csr = 0;

arch/alpha/kernel/core_marvel.c

306

csrs->POx_WBASE[2].csr =

arch/alpha/kernel/core_marvel.c

308

csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;

arch/alpha/kernel/core_marvel.c

309

csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);

arch/alpha/kernel/core_marvel.c

314

csrs->POx_WBASE[3].csr = 0;

arch/alpha/kernel/core_marvel.c

319

csrs->POx_CTRL.csr &= ~(1UL << 61);

arch/alpha/kernel/core_marvel.c

323

csrs->POx_MSK_HEI.csr &= ~(3UL << 14);

arch/alpha/kernel/core_marvel.c

348

if (csrs->POx_CACHE_CTL.csr == 8) {

arch/alpha/kernel/core_marvel.c

609

csrs->POx_SG_TBIA.csr = 0;

arch/alpha/kernel/core_marvel.c

611

csrs->POx_SG_TBIA.csr;

arch/alpha/kernel/core_marvel.c

62

q = ev7csr->csr;

arch/alpha/kernel/core_marvel.c

74

ev7csr->csr = q;

arch/alpha/kernel/core_marvel.c

920

agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;

arch/alpha/kernel/core_marvel.c

966

csrs->AGP_CMD.csr = agp->mode.lw;

arch/alpha/kernel/core_titan.c

207

volatile unsigned long *csr;

arch/alpha/kernel/core_titan.c

220

csr = &port->port_specific.g.gtlbia.csr;

arch/alpha/kernel/core_titan.c

222

csr = &port->port_specific.g.gtlbiv.csr;

arch/alpha/kernel/core_titan.c

229

*csr = value;

arch/alpha/kernel/core_titan.c

231

*csr;

arch/alpha/kernel/core_titan.c

240

pctl.pctl_q_whole = port->pctl.csr;

arch/alpha/kernel/core_titan.c

293

saved_config[index].wsba[0] = port->wsba[0].csr;

arch/alpha/kernel/core_titan.c

294

saved_config[index].wsm[0] = port->wsm[0].csr;

arch/alpha/kernel/core_titan.c

295

saved_config[index].tba[0] = port->tba[0].csr;

arch/alpha/kernel/core_titan.c

297

saved_config[index].wsba[1] = port->wsba[1].csr;

arch/alpha/kernel/core_titan.c

298

saved_config[index].wsm[1] = port->wsm[1].csr;

arch/alpha/kernel/core_titan.c

299

saved_config[index].tba[1] = port->tba[1].csr;

arch/alpha/kernel/core_titan.c

301

saved_config[index].wsba[2] = port->wsba[2].csr;

arch/alpha/kernel/core_titan.c

302

saved_config[index].wsm[2] = port->wsm[2].csr;

arch/alpha/kernel/core_titan.c

303

saved_config[index].tba[2] = port->tba[2].csr;

arch/alpha/kernel/core_titan.c

305

saved_config[index].wsba[3] = port->wsba[3].csr;

arch/alpha/kernel/core_titan.c

306

saved_config[index].wsm[3] = port->wsm[3].csr;

arch/alpha/kernel/core_titan.c

307

saved_config[index].tba[3] = port->tba[3].csr;

arch/alpha/kernel/core_titan.c

326

port->wsba[0].csr = hose->sg_isa->dma_base | 3;

arch/alpha/kernel/core_titan.c

327

port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;

arch/alpha/kernel/core_titan.c

328

port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);

arch/alpha/kernel/core_titan.c

330

port->wsba[1].csr = __direct_map_base | 1;

arch/alpha/kernel/core_titan.c

331

port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000;

arch/alpha/kernel/core_titan.c

332

port->tba[1].csr = 0;

arch/alpha/kernel/core_titan.c

334

port->wsba[2].csr = hose->sg_pci->dma_base | 3;

arch/alpha/kernel/core_titan.c

335

port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000;

arch/alpha/kernel/core_titan.c

336

port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes);

arch/alpha/kernel/core_titan.c

338

port->wsba[3].csr = 0;

arch/alpha/kernel/core_titan.c

341

port->pctl.csr |= pctl_m_mwin;

arch/alpha/kernel/core_titan.c

347

port->port_specific.a.agplastwr.csr = __direct_map_base;

arch/alpha/kernel/core_titan.c

355

titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;

arch/alpha/kernel/core_titan.c

372

printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr);

arch/alpha/kernel/core_titan.c

373

printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr);

arch/alpha/kernel/core_titan.c

374

printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr);

arch/alpha/kernel/core_titan.c

375

printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);

arch/alpha/kernel/core_titan.c

376

printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);

arch/alpha/kernel/core_titan.c

377

printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);

arch/alpha/kernel/core_titan.c

378

printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr);

arch/alpha/kernel/core_titan.c

379

printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr);

arch/alpha/kernel/core_titan.c

382

printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);

arch/alpha/kernel/core_titan.c

383

printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr);

arch/alpha/kernel/core_titan.c

384

printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr);

arch/alpha/kernel/core_titan.c

407

port->wsba[0].csr = saved_config[index].wsba[0];

arch/alpha/kernel/core_titan.c

408

port->wsm[0].csr = saved_config[index].wsm[0];

arch/alpha/kernel/core_titan.c

409

port->tba[0].csr = saved_config[index].tba[0];

arch/alpha/kernel/core_titan.c

411

port->wsba[1].csr = saved_config[index].wsba[1];

arch/alpha/kernel/core_titan.c

412

port->wsm[1].csr = saved_config[index].wsm[1];

arch/alpha/kernel/core_titan.c

413

port->tba[1].csr = saved_config[index].tba[1];

arch/alpha/kernel/core_titan.c

415

port->wsba[2].csr = saved_config[index].wsba[2];

arch/alpha/kernel/core_titan.c

416

port->wsm[2].csr = saved_config[index].wsm[2];

arch/alpha/kernel/core_titan.c

417

port->tba[2].csr = saved_config[index].tba[2];

arch/alpha/kernel/core_titan.c

419

port->wsba[3].csr = saved_config[index].wsba[3];

arch/alpha/kernel/core_titan.c

420

port->wsm[3].csr = saved_config[index].wsm[3];

arch/alpha/kernel/core_titan.c

421

port->tba[3].csr = saved_config[index].tba[3];

arch/alpha/kernel/core_titan.c

645

pctl.pctl_q_whole = port->pctl.csr;

arch/alpha/kernel/core_titan.c

674

port->pctl.csr = pctl.pctl_q_whole;

arch/alpha/kernel/core_titan.c

794

pctl.pctl_q_whole = port->pctl.csr;

arch/alpha/kernel/core_tsunami.c

181

volatile unsigned long *csr;

arch/alpha/kernel/core_tsunami.c

186

csr = &pchip->tlbia.csr;

arch/alpha/kernel/core_tsunami.c

188

csr = &pchip->tlbiv.csr;

arch/alpha/kernel/core_tsunami.c

194

*csr = value;

arch/alpha/kernel/core_tsunami.c

196

*csr;

arch/alpha/kernel/core_tsunami.c

227

TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */

arch/alpha/kernel/core_tsunami.c

231

if (TSUNAMI_cchip->misc.csr & (1L << 28)) {

arch/alpha/kernel/core_tsunami.c

232

int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;

arch/alpha/kernel/core_tsunami.c

233

TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */

arch/alpha/kernel/core_tsunami.c

251

if (tsunami_probe_read(&pchip->pctl.csr) == 0)

arch/alpha/kernel/core_tsunami.c

294

saved_config[index].wsba[0] = pchip->wsba[0].csr;

arch/alpha/kernel/core_tsunami.c

295

saved_config[index].wsm[0] = pchip->wsm[0].csr;

arch/alpha/kernel/core_tsunami.c

296

saved_config[index].tba[0] = pchip->tba[0].csr;

arch/alpha/kernel/core_tsunami.c

298

saved_config[index].wsba[1] = pchip->wsba[1].csr;

arch/alpha/kernel/core_tsunami.c

299

saved_config[index].wsm[1] = pchip->wsm[1].csr;

arch/alpha/kernel/core_tsunami.c

300

saved_config[index].tba[1] = pchip->tba[1].csr;

arch/alpha/kernel/core_tsunami.c

302

saved_config[index].wsba[2] = pchip->wsba[2].csr;

arch/alpha/kernel/core_tsunami.c

303

saved_config[index].wsm[2] = pchip->wsm[2].csr;

arch/alpha/kernel/core_tsunami.c

304

saved_config[index].tba[2] = pchip->tba[2].csr;

arch/alpha/kernel/core_tsunami.c

306

saved_config[index].wsba[3] = pchip->wsba[3].csr;

arch/alpha/kernel/core_tsunami.c

307

saved_config[index].wsm[3] = pchip->wsm[3].csr;

arch/alpha/kernel/core_tsunami.c

308

saved_config[index].tba[3] = pchip->tba[3].csr;

arch/alpha/kernel/core_tsunami.c

335

pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;

arch/alpha/kernel/core_tsunami.c

336

pchip->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;

arch/alpha/kernel/core_tsunami.c

337

pchip->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);

arch/alpha/kernel/core_tsunami.c

339

pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;

arch/alpha/kernel/core_tsunami.c

340

pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000;

arch/alpha/kernel/core_tsunami.c

341

pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes);

arch/alpha/kernel/core_tsunami.c

343

pchip->wsba[2].csr = 0x80000000 | 1;

arch/alpha/kernel/core_tsunami.c

344

pchip->wsm[2].csr = (0x80000000 - 1) & 0xfff00000;

arch/alpha/kernel/core_tsunami.c

345

pchip->tba[2].csr = 0;

arch/alpha/kernel/core_tsunami.c

347

pchip->wsba[3].csr = 0;

arch/alpha/kernel/core_tsunami.c

350

pchip->pctl.csr |= pctl_m_mwin;

arch/alpha/kernel/core_tsunami.c

396

printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);

arch/alpha/kernel/core_tsunami.c

397

printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);

arch/alpha/kernel/core_tsunami.c

398

printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);

arch/alpha/kernel/core_tsunami.c

399

printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);

arch/alpha/kernel/core_tsunami.c

400

printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);

arch/alpha/kernel/core_tsunami.c

401

printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);

arch/alpha/kernel/core_tsunami.c

402

printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);

arch/alpha/kernel/core_tsunami.c

403

printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);

arch/alpha/kernel/core_tsunami.c

406

printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);

arch/alpha/kernel/core_tsunami.c

407

printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);

arch/alpha/kernel/core_tsunami.c

408

printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);

arch/alpha/kernel/core_tsunami.c

417

if (TSUNAMI_cchip->csc.csr & 1L<<14)

arch/alpha/kernel/core_tsunami.c

427

pchip->wsba[0].csr = saved_config[index].wsba[0];

arch/alpha/kernel/core_tsunami.c

428

pchip->wsm[0].csr = saved_config[index].wsm[0];

arch/alpha/kernel/core_tsunami.c

429

pchip->tba[0].csr = saved_config[index].tba[0];

arch/alpha/kernel/core_tsunami.c

431

pchip->wsba[1].csr = saved_config[index].wsba[1];

arch/alpha/kernel/core_tsunami.c

432

pchip->wsm[1].csr = saved_config[index].wsm[1];

arch/alpha/kernel/core_tsunami.c

433

pchip->tba[1].csr = saved_config[index].tba[1];

arch/alpha/kernel/core_tsunami.c

435

pchip->wsba[2].csr = saved_config[index].wsba[2];

arch/alpha/kernel/core_tsunami.c

436

pchip->wsm[2].csr = saved_config[index].wsm[2];

arch/alpha/kernel/core_tsunami.c

437

pchip->tba[2].csr = saved_config[index].tba[2];

arch/alpha/kernel/core_tsunami.c

439

pchip->wsba[3].csr = saved_config[index].wsba[3];

arch/alpha/kernel/core_tsunami.c

440

pchip->wsm[3].csr = saved_config[index].wsm[3];

arch/alpha/kernel/core_tsunami.c

441

pchip->tba[3].csr = saved_config[index].tba[3];

arch/alpha/kernel/core_tsunami.c

448

if (TSUNAMI_cchip->csc.csr & 1L<<14)

arch/alpha/kernel/core_tsunami.c

455

pchip->perror.csr;

arch/alpha/kernel/core_tsunami.c

456

pchip->perror.csr = 0x040;

arch/alpha/kernel/core_tsunami.c

458

pchip->perror.csr;

arch/alpha/kernel/core_tsunami.c

467

if (TSUNAMI_cchip->csc.csr & 1L<<14)

arch/alpha/kernel/core_wildfire.c

121

pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3;

arch/alpha/kernel/core_wildfire.c

122

pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000;

arch/alpha/kernel/core_wildfire.c

123

pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes);

arch/alpha/kernel/core_wildfire.c

125

pci->pci_window[1].wbase.csr = 0x40000000 | 1;

arch/alpha/kernel/core_wildfire.c

126

pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000;

arch/alpha/kernel/core_wildfire.c

127

pci->pci_window[1].tbase.csr = 0;

arch/alpha/kernel/core_wildfire.c

129

pci->pci_window[2].wbase.csr = 0x80000000 | 1;

arch/alpha/kernel/core_wildfire.c

130

pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000;

arch/alpha/kernel/core_wildfire.c

131

pci->pci_window[2].tbase.csr = 0x40000000;

arch/alpha/kernel/core_wildfire.c

133

pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3;

arch/alpha/kernel/core_wildfire.c

134

pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000;

arch/alpha/kernel/core_wildfire.c

135

pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes);

arch/alpha/kernel/core_wildfire.c

193

temp = fast->qsd_whami.csr;

arch/alpha/kernel/core_wildfire.c

220

temp = qsa->qsa_qbb_id.csr;

arch/alpha/kernel/core_wildfire.c

232

temp |= gp->gpa_qbb_map[i].csr << (i * 8);

arch/alpha/kernel/core_wildfire.c

254

temp = qsd->qsd_whami.csr;

arch/alpha/kernel/core_wildfire.c

263

temp = qsa->qsa_qbb_pop[0].csr;

arch/alpha/kernel/core_wildfire.c

270

temp = qsa->qsa_qbb_pop[1].csr;

arch/alpha/kernel/core_wildfire.c

277

temp = qsa->qsa_qbb_id.csr;

arch/alpha/kernel/core_wildfire.c

290

if ((iop->iop_hose[i].init.csr & 1) == 1 &&

arch/alpha/kernel/core_wildfire.c

291

((ne->ne_what_am_i.csr & 0xf00000300UL) == 0x100000300UL) &&

arch/alpha/kernel/core_wildfire.c

292

((fe->fe_what_am_i.csr & 0xf00000300UL) == 0x100000200UL))

arch/alpha/kernel/core_wildfire.c

354

pci->pci_flush_tlb.csr; /* reading does the trick */

arch/alpha/kernel/core_wildfire.c

455

pci->pci_io_addr_ext.csr);

arch/alpha/kernel/core_wildfire.c

456

printk(KERN_ERR " PCI_CTRL: 0x%16lx\n", pci->pci_ctrl.csr);

arch/alpha/kernel/core_wildfire.c

457

printk(KERN_ERR " PCI_ERR_SUM: 0x%16lx\n", pci->pci_err_sum.csr);

arch/alpha/kernel/core_wildfire.c

458

printk(KERN_ERR " PCI_ERR_ADDR: 0x%16lx\n", pci->pci_err_addr.csr);

arch/alpha/kernel/core_wildfire.c

459

printk(KERN_ERR " PCI_STALL_CNT: 0x%16lx\n", pci->pci_stall_cnt.csr);

arch/alpha/kernel/core_wildfire.c

460

printk(KERN_ERR " PCI_PEND_INT: 0x%16lx\n", pci->pci_pend_int.csr);

arch/alpha/kernel/core_wildfire.c

461

printk(KERN_ERR " PCI_SENT_INT: 0x%16lx\n", pci->pci_sent_int.csr);

arch/alpha/kernel/core_wildfire.c

467

pci->pci_window[i].wbase.csr,

arch/alpha/kernel/core_wildfire.c

468

pci->pci_window[i].wmask.csr,

arch/alpha/kernel/core_wildfire.c

469

pci->pci_window[i].tbase.csr);

arch/alpha/kernel/core_wildfire.c

483

printk(KERN_ERR " PCA_WHAT_AM_I: 0x%16lx\n", pca->pca_what_am_i.csr);

arch/alpha/kernel/core_wildfire.c

484

printk(KERN_ERR " PCA_ERR_SUM: 0x%16lx\n", pca->pca_err_sum.csr);

arch/alpha/kernel/core_wildfire.c

485

printk(KERN_ERR " PCA_PEND_INT: 0x%16lx\n", pca->pca_pend_int.csr);

arch/alpha/kernel/core_wildfire.c

486

printk(KERN_ERR " PCA_SENT_INT: 0x%16lx\n", pca->pca_sent_int.csr);

arch/alpha/kernel/core_wildfire.c

488

pca->pca_stdio_edge_level.csr);

arch/alpha/kernel/core_wildfire.c

494

pca->pca_int[i].target.csr,

arch/alpha/kernel/core_wildfire.c

495

pca->pca_int[i].enable.csr);

arch/alpha/kernel/core_wildfire.c

509

printk(KERN_ERR " QSA_QBB_ID: 0x%16lx\n", qsa->qsa_qbb_id.csr);

arch/alpha/kernel/core_wildfire.c

510

printk(KERN_ERR " QSA_PORT_ENA: 0x%16lx\n", qsa->qsa_port_ena.csr);

arch/alpha/kernel/core_wildfire.c

511

printk(KERN_ERR " QSA_REF_INT: 0x%16lx\n", qsa->qsa_ref_int.csr);

arch/alpha/kernel/core_wildfire.c

515

i, qsa->qsa_config[i].csr);

arch/alpha/kernel/core_wildfire.c

519

i, qsa->qsa_qbb_pop[0].csr);

arch/alpha/kernel/core_wildfire.c

531

printk(KERN_ERR " QSD_WHAMI: 0x%16lx\n", qsd->qsd_whami.csr);

arch/alpha/kernel/core_wildfire.c

532

printk(KERN_ERR " QSD_REV: 0x%16lx\n", qsd->qsd_rev.csr);

arch/alpha/kernel/core_wildfire.c

534

qsd->qsd_port_present.csr);

arch/alpha/kernel/core_wildfire.c

536

qsd->qsd_port_active.csr);

arch/alpha/kernel/core_wildfire.c

538

qsd->qsd_fault_ena.csr);

arch/alpha/kernel/core_wildfire.c

540

qsd->qsd_cpu_int_ena.csr);

arch/alpha/kernel/core_wildfire.c

542

qsd->qsd_mem_config.csr);

arch/alpha/kernel/core_wildfire.c

544

qsd->qsd_err_sum.csr);

arch/alpha/kernel/core_wildfire.c

557

printk(KERN_ERR " IOA_CONFIG: 0x%16lx\n", iop->ioa_config.csr);

arch/alpha/kernel/core_wildfire.c

558

printk(KERN_ERR " IOD_CONFIG: 0x%16lx\n", iop->iod_config.csr);

arch/alpha/kernel/core_wildfire.c

560

iop->iop_switch_credits.csr);

arch/alpha/kernel/core_wildfire.c

562

iop->iop_hose_credits.csr);

arch/alpha/kernel/core_wildfire.c

566

i, iop->iop_hose[i].init.csr);

arch/alpha/kernel/core_wildfire.c

569

i, iop->iop_dev_int[i].target.csr);

arch/alpha/kernel/core_wildfire.c

583

i, gp->gpa_qbb_map[i].csr);

arch/alpha/kernel/core_wildfire.c

586

gp->gpa_mem_pop_map.csr);

arch/alpha/kernel/core_wildfire.c

587

printk(KERN_ERR " GPA_SCRATCH: 0x%16lx\n", gp->gpa_scratch.csr);

arch/alpha/kernel/core_wildfire.c

588

printk(KERN_ERR " GPA_DIAG: 0x%16lx\n", gp->gpa_diag.csr);

arch/alpha/kernel/core_wildfire.c

589

printk(KERN_ERR " GPA_CONFIG_0: 0x%16lx\n", gp->gpa_config_0.csr);

arch/alpha/kernel/core_wildfire.c

590

printk(KERN_ERR " GPA_INIT_ID: 0x%16lx\n", gp->gpa_init_id.csr);

arch/alpha/kernel/core_wildfire.c

591

printk(KERN_ERR " GPA_CONFIG_2: 0x%16lx\n", gp->gpa_config_2.csr);

arch/alpha/kernel/err_marvel.c

818

err_sum |= io7->csrs->PO7_ERROR_SUM.csr;

arch/alpha/kernel/err_marvel.c

822

err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr;

arch/alpha/kernel/err_marvel.c

843

io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr;

arch/alpha/kernel/err_marvel.c

844

io->io_sys_rev = io7->csrs->IO_SYS_REV.csr;

arch/alpha/kernel/err_marvel.c

845

io->io7_uph = io7->csrs->IO7_UPH.csr;

arch/alpha/kernel/err_marvel.c

846

io->hpi_ctl = io7->csrs->HPI_CTL.csr;

arch/alpha/kernel/err_marvel.c

847

io->crd_ctl = io7->csrs->CRD_CTL.csr;

arch/alpha/kernel/err_marvel.c

848

io->hei_ctl = io7->csrs->HEI_CTL.csr;

arch/alpha/kernel/err_marvel.c

849

io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr;

arch/alpha/kernel/err_marvel.c

850

io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr;

arch/alpha/kernel/err_marvel.c

851

io->po7_crrct_sym = io7->csrs->PO7_CRRCT_SYM.csr;

arch/alpha/kernel/err_marvel.c

852

io->po7_ugbge_sym = io7->csrs->PO7_UGBGE_SYM.csr;

arch/alpha/kernel/err_marvel.c

853

io->po7_err_pkt0 = io7->csrs->PO7_ERR_PKT[0].csr;

arch/alpha/kernel/err_marvel.c

854

io->po7_err_pkt1 = io7->csrs->PO7_ERR_PKT[1].csr;

arch/alpha/kernel/err_marvel.c

862

io->ports[i].pox_err_sum = csrs->POx_ERR_SUM.csr;

arch/alpha/kernel/err_marvel.c

863

io->ports[i].pox_tlb_err = csrs->POx_TLB_ERR.csr;

arch/alpha/kernel/err_marvel.c

864

io->ports[i].pox_spl_cmplt = csrs->POx_SPL_COMPLT.csr;

arch/alpha/kernel/err_marvel.c

865

io->ports[i].pox_trans_sum = csrs->POx_TRANS_SUM.csr;

arch/alpha/kernel/err_marvel.c

866

io->ports[i].pox_first_err = csrs->POx_FIRST_ERR.csr;

arch/alpha/kernel/err_marvel.c

867

io->ports[i].pox_mult_err = csrs->POx_MULT_ERR.csr;

arch/alpha/kernel/err_marvel.c

868

io->ports[i].pox_dm_source = csrs->POx_DM_SOURCE.csr;

arch/alpha/kernel/err_marvel.c

869

io->ports[i].pox_dm_dest = csrs->POx_DM_DEST.csr;

arch/alpha/kernel/err_marvel.c

870

io->ports[i].pox_dm_size = csrs->POx_DM_SIZE.csr;

arch/alpha/kernel/err_marvel.c

871

io->ports[i].pox_dm_ctrl = csrs->POx_DM_CTRL.csr;

arch/alpha/kernel/err_marvel.c

881

csrs->POx_TLB_ERR.csr = io->ports[i].pox_tlb_err;

arch/alpha/kernel/err_marvel.c

882

csrs->POx_ERR_SUM.csr = io->ports[i].pox_err_sum;

arch/alpha/kernel/err_marvel.c

884

csrs->POx_ERR_SUM.csr;

arch/alpha/kernel/err_marvel.c

890

io7->csrs->PO7_ERROR_SUM.csr = io->po7_error_sum;

arch/alpha/kernel/err_marvel.c

892

io7->csrs->PO7_ERROR_SUM.csr;

arch/alpha/kernel/sys_dp264.c

197

pld = TSUNAMI_cchip->dir0.csr;

arch/alpha/kernel/sys_dp264.c

68

dim0 = &cchip->dim0.csr;

arch/alpha/kernel/sys_dp264.c

69

dim1 = &cchip->dim1.csr;

arch/alpha/kernel/sys_dp264.c

70

dim2 = &cchip->dim2.csr;

arch/alpha/kernel/sys_dp264.c

71

dim3 = &cchip->dim3.csr;

arch/alpha/kernel/sys_dp264.c

88

if (bcpu == 0) dimB = &cchip->dim0.csr;

arch/alpha/kernel/sys_dp264.c

89

else if (bcpu == 1) dimB = &cchip->dim1.csr;

arch/alpha/kernel/sys_dp264.c

90

else if (bcpu == 2) dimB = &cchip->dim2.csr;

arch/alpha/kernel/sys_dp264.c

91

else dimB = &cchip->dim3.csr;

arch/alpha/kernel/sys_marvel.c

174

volatile unsigned long *csr,

arch/alpha/kernel/sys_marvel.c

179

val = *csr;

arch/alpha/kernel/sys_marvel.c

183

*csr = val;

arch/alpha/kernel/sys_marvel.c

185

*csr;

arch/alpha/kernel/sys_marvel.c

196

val = io7->csrs->PO7_LSI_CTL[which].csr;

arch/alpha/kernel/sys_marvel.c

200

io7->csrs->PO7_LSI_CTL[which].csr = val;

arch/alpha/kernel/sys_marvel.c

202

io7->csrs->PO7_LSI_CTL[which].csr;

arch/alpha/kernel/sys_marvel.c

213

val = io7->csrs->PO7_MSI_CTL[which].csr;

arch/alpha/kernel/sys_marvel.c

217

io7->csrs->PO7_MSI_CTL[which].csr = val;

arch/alpha/kernel/sys_marvel.c

219

io7->csrs->PO7_MSI_CTL[which].csr;

arch/alpha/kernel/sys_marvel.c

228

io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14);

arch/alpha/kernel/sys_marvel.c

230

io7->csrs->PO7_LSI_CTL[which].csr;

arch/alpha/kernel/sys_marvel.c

239

io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14);

arch/alpha/kernel/sys_marvel.c

241

io7->csrs->PO7_MSI_CTL[which].csr;

arch/alpha/kernel/sys_marvel.c

269

io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid);

arch/alpha/kernel/sys_marvel.c

270

io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid);

arch/alpha/kernel/sys_marvel.c

271

io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid);

arch/alpha/kernel/sys_marvel.c

272

io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid);

arch/alpha/kernel/sys_marvel.c

273

io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid);

arch/alpha/kernel/sys_marvel.c

418

io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid);

arch/alpha/kernel/sys_marvel.c

419

io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid);

arch/alpha/kernel/sys_marvel.c

420

io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid);

arch/alpha/kernel/sys_marvel.c

421

io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid);

arch/alpha/kernel/sys_marvel.c

422

io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid);

arch/alpha/kernel/sys_marvel.c

96

ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */

arch/alpha/kernel/sys_marvel.c

98

ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr;

arch/alpha/kernel/sys_titan.c

103

dimB = &cchip->dim0.csr;

arch/alpha/kernel/sys_titan.c

104

if (bcpu == 1) dimB = &cchip->dim1.csr;

arch/alpha/kernel/sys_titan.c

105

else if (bcpu == 2) dimB = &cchip->dim2.csr;

arch/alpha/kernel/sys_titan.c

106

else if (bcpu == 3) dimB = &cchip->dim3.csr;

arch/alpha/kernel/sys_titan.c

83

dim0 = &cchip->dim0.csr;

arch/alpha/kernel/sys_titan.c

84

dim1 = &cchip->dim1.csr;

arch/alpha/kernel/sys_titan.c

85

dim2 = &cchip->dim2.csr;

arch/alpha/kernel/sys_titan.c

86

dim3 = &cchip->dim3.csr;

arch/arm/mach-omap1/omap-dma.c

692

u32 csr;

arch/arm/mach-omap1/omap-dma.c

695

csr = dma_chan[ch].saved_csr;

arch/arm/mach-omap1/omap-dma.c

698

csr = p->dma_read(CSR, ch);

arch/arm/mach-omap1/omap-dma.c

699

if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {

arch/arm/mach-omap1/omap-dma.c

700

dma_chan[ch + 6].saved_csr = csr >> 7;

arch/arm/mach-omap1/omap-dma.c

701

csr &= 0x7f;

arch/arm/mach-omap1/omap-dma.c

703

if ((csr & 0x3f) == 0)

arch/arm/mach-omap1/omap-dma.c

707

ch, csr);

arch/arm/mach-omap1/omap-dma.c

710

if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))

arch/arm/mach-omap1/omap-dma.c

712

if (unlikely(csr & OMAP_DMA_DROP_IRQ))

arch/arm/mach-omap1/omap-dma.c

715

if (likely(csr & OMAP_DMA_BLOCK_IRQ))

arch/arm/mach-omap1/omap-dma.c

718

dma_chan[ch].callback(ch, csr, dma_chan[ch].data);

arch/loongarch/include/asm/fpu.h

32

asmlinkage int _save_fp_context(void __user *fpregs, void __user *fcc, void __user *csr);

arch/loongarch/include/asm/fpu.h

33

asmlinkage int _restore_fp_context(void __user *fpregs, void __user *fcc, void __user *csr);

arch/loongarch/include/asm/inst.h

341

unsigned int csr : 14;

arch/loongarch/include/asm/kvm_csr.h

14

#define gcsr_read(csr) \

arch/loongarch/include/asm/kvm_csr.h

182

#define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid))

arch/loongarch/include/asm/kvm_csr.h

183

#define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid))

arch/loongarch/include/asm/kvm_csr.h

185

#define kvm_read_clear_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_write(0, gid))

arch/loongarch/include/asm/kvm_csr.h

189

static __always_inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid)

arch/loongarch/include/asm/kvm_csr.h

191

return csr->csrs[gid];

arch/loongarch/include/asm/kvm_csr.h

194

static __always_inline void kvm_write_sw_gcsr(struct loongarch_csrs *csr, int gid, unsigned long val)

arch/loongarch/include/asm/kvm_csr.h

196

csr->csrs[gid] = val;

arch/loongarch/include/asm/kvm_csr.h

199

static __always_inline void kvm_set_sw_gcsr(struct loongarch_csrs *csr,

arch/loongarch/include/asm/kvm_csr.h

20

: [reg] "i" (csr) \

arch/loongarch/include/asm/kvm_csr.h

202

csr->csrs[gid] |= val;

arch/loongarch/include/asm/kvm_csr.h

205

static __always_inline void kvm_change_sw_gcsr(struct loongarch_csrs *csr,

arch/loongarch/include/asm/kvm_csr.h

210

csr->csrs[gid] &= ~_mask;

arch/loongarch/include/asm/kvm_csr.h

211

csr->csrs[gid] |= val & _mask;

arch/loongarch/include/asm/kvm_csr.h

25

#define gcsr_write(v, csr) \

arch/loongarch/include/asm/kvm_csr.h

31

: [reg] "i" (csr) \

arch/loongarch/include/asm/kvm_csr.h

36

#define gcsr_xchg(v, m, csr) \

arch/loongarch/include/asm/kvm_csr.h

42

: [mask] "r" (m), [reg] "i" (csr) \

arch/loongarch/include/asm/kvm_host.h

212

struct loongarch_csrs *csr;

arch/loongarch/include/asm/kvm_host.h

262

static inline unsigned long readl_sw_gcsr(struct loongarch_csrs *csr, int reg)

arch/loongarch/include/asm/kvm_host.h

264

return csr->csrs[reg];

arch/loongarch/include/asm/kvm_host.h

267

static inline void writel_sw_gcsr(struct loongarch_csrs *csr, int reg, unsigned long val)

arch/loongarch/include/asm/kvm_host.h

269

csr->csrs[reg] = val;

arch/loongarch/include/asm/kvm_host.h

367

int get_gcsr_flag(int csr);

arch/loongarch/kernel/signal.c

348

unsigned int csr, enabled;

arch/loongarch/kernel/signal.c

350

err = __get_user(csr, fcsr);

arch/loongarch/kernel/signal.c

351

enabled = ((csr & FPU_CSR_ALL_E) << 24);

arch/loongarch/kernel/signal.c

356

if (csr & enabled) {

arch/loongarch/kernel/signal.c

357

csr &= ~enabled;

arch/loongarch/kernel/signal.c

358

err |= __put_user(csr, fcsr);

arch/loongarch/kvm/exit.c

100

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/exit.c

103

old = kvm_read_sw_gcsr(csr, csrid);

arch/loongarch/kvm/exit.c

105

kvm_write_sw_gcsr(csr, csrid, val);

arch/loongarch/kvm/exit.c

126

csrid = inst.reg2csr_format.csr;

arch/loongarch/kvm/exit.c

68

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/exit.c

75

val = kvm_read_sw_gcsr(csr, csrid);

arch/loongarch/kvm/exit.c

85

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/exit.c

88

old = kvm_read_sw_gcsr(csr, csrid);

arch/loongarch/kvm/exit.c

89

kvm_write_sw_gcsr(csr, csrid, val);

arch/loongarch/kvm/main.c

21

int get_gcsr_flag(int csr)

arch/loongarch/kvm/main.c

23

if (csr < CSR_MAX_NUMS)

arch/loongarch/kvm/main.c

24

return gcsr_flag[csr];

arch/loongarch/kvm/main.c

29

static inline void set_gcsr_sw_flag(int csr)

arch/loongarch/kvm/main.c

31

if (csr < CSR_MAX_NUMS)

arch/loongarch/kvm/main.c

32

gcsr_flag[csr] |= SW_GCSR;

arch/loongarch/kvm/main.c

35

static inline void set_gcsr_hw_flag(int csr)

arch/loongarch/kvm/main.c

37

if (csr < CSR_MAX_NUMS)

arch/loongarch/kvm/main.c

38

gcsr_flag[csr] |= HW_GCSR;

arch/loongarch/kvm/timer.c

144

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/timer.c

146

cfg = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TCFG);

arch/loongarch/kvm/timer.c

147

ticks = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TVAL);

arch/loongarch/kvm/timer.c

180

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/timer.c

185

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TCFG);

arch/loongarch/kvm/timer.c

186

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TVAL);

arch/loongarch/kvm/timer.c

187

if (kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TCFG) & CSR_TCFG_EN)

arch/loongarch/kvm/timer.c

191

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ESTAT);

arch/loongarch/kvm/timer.c

47

kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_TVAL, 0);

arch/loongarch/kvm/timer.c

58

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/timer.c

65

cfg = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TCFG);

arch/loongarch/kvm/timer.c

68

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ESTAT);

arch/loongarch/kvm/timer.c

69

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TCFG);

arch/loongarch/kvm/timer.c

72

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TVAL);

arch/loongarch/kvm/timer.c

91

ticks = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TVAL);

arch/loongarch/kvm/timer.c

92

estat = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT);

arch/loongarch/kvm/vcpu.c

122

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

140

val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0);

arch/loongarch/kvm/vcpu.c

141

val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1);

arch/loongarch/kvm/vcpu.c

142

val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2);

arch/loongarch/kvm/vcpu.c

143

val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3);

arch/loongarch/kvm/vcpu.c

1534

struct loongarch_csrs *csr;

arch/loongarch/kvm/vcpu.c

1553

vcpu->arch.csr = kzalloc_obj(struct loongarch_csrs);

arch/loongarch/kvm/vcpu.c

1554

if (!vcpu->arch.csr)

arch/loongarch/kvm/vcpu.c

1576

csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

1577

kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CRMD, CSR_CRMD_DA);

arch/loongarch/kvm/vcpu.c

1580

kvm_write_sw_gcsr(csr, LOONGARCH_CSR_TMID, vcpu->vcpu_id);

arch/loongarch/kvm/vcpu.c

1581

kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CPUID, KVM_MAX_PHYID);

arch/loongarch/kvm/vcpu.c

1584

csr->csrs[LOONGARCH_CSR_GINTC] = 0;

arch/loongarch/kvm/vcpu.c

1601

kfree(vcpu->arch.csr);

arch/loongarch/kvm/vcpu.c

1618

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

1646

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CRMD);

arch/loongarch/kvm/vcpu.c

1647

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PRMD);

arch/loongarch/kvm/vcpu.c

1648

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_EUEN);

arch/loongarch/kvm/vcpu.c

1649

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_MISC);

arch/loongarch/kvm/vcpu.c

1650

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ECFG);

arch/loongarch/kvm/vcpu.c

1651

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ERA);

arch/loongarch/kvm/vcpu.c

1652

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_BADV);

arch/loongarch/kvm/vcpu.c

1653

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_BADI);

arch/loongarch/kvm/vcpu.c

1654

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_EENTRY);

arch/loongarch/kvm/vcpu.c

1655

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBIDX);

arch/loongarch/kvm/vcpu.c

1656

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBEHI);

arch/loongarch/kvm/vcpu.c

1657

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBELO0);

arch/loongarch/kvm/vcpu.c

1658

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBELO1);

arch/loongarch/kvm/vcpu.c

1659

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ASID);

arch/loongarch/kvm/vcpu.c

1660

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PGDL);

arch/loongarch/kvm/vcpu.c

1661

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PGDH);

arch/loongarch/kvm/vcpu.c

1662

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PWCTL0);

arch/loongarch/kvm/vcpu.c

1663

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PWCTL1);

arch/loongarch/kvm/vcpu.c

1664

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_STLBPGSIZE);

arch/loongarch/kvm/vcpu.c

1665

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_RVACFG);

arch/loongarch/kvm/vcpu.c

1666

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CPUID);

arch/loongarch/kvm/vcpu.c

1667

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS0);

arch/loongarch/kvm/vcpu.c

1668

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS1);

arch/loongarch/kvm/vcpu.c

1669

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS2);

arch/loongarch/kvm/vcpu.c

1670

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS3);

arch/loongarch/kvm/vcpu.c

1671

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS4);

arch/loongarch/kvm/vcpu.c

1672

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS5);

arch/loongarch/kvm/vcpu.c

1673

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS6);

arch/loongarch/kvm/vcpu.c

1674

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS7);

arch/loongarch/kvm/vcpu.c

1675

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TMID);

arch/loongarch/kvm/vcpu.c

1676

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CNTC);

arch/loongarch/kvm/vcpu.c

1677

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRENTRY);

arch/loongarch/kvm/vcpu.c

1678

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRBADV);

arch/loongarch/kvm/vcpu.c

1679

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRERA);

arch/loongarch/kvm/vcpu.c

1680

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRSAVE);

arch/loongarch/kvm/vcpu.c

1681

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO0);

arch/loongarch/kvm/vcpu.c

1682

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO1);

arch/loongarch/kvm/vcpu.c

1683

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBREHI);

arch/loongarch/kvm/vcpu.c

1684

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRPRMD);

arch/loongarch/kvm/vcpu.c

1685

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN0);

arch/loongarch/kvm/vcpu.c

1686

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1);

arch/loongarch/kvm/vcpu.c

1687

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2);

arch/loongarch/kvm/vcpu.c

1688

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3);

arch/loongarch/kvm/vcpu.c

1689

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL);

arch/loongarch/kvm/vcpu.c

1692

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_IPR);

arch/loongarch/kvm/vcpu.c

1693

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR0);

arch/loongarch/kvm/vcpu.c

1694

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR1);

arch/loongarch/kvm/vcpu.c

1695

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR2);

arch/loongarch/kvm/vcpu.c

1696

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR3);

arch/loongarch/kvm/vcpu.c

1700

write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]);

arch/loongarch/kvm/vcpu.c

1727

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

1740

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CRMD);

arch/loongarch/kvm/vcpu.c

1741

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRMD);

arch/loongarch/kvm/vcpu.c

1742

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_EUEN);

arch/loongarch/kvm/vcpu.c

1743

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_MISC);

arch/loongarch/kvm/vcpu.c

1744

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ECFG);

arch/loongarch/kvm/vcpu.c

1745

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ERA);

arch/loongarch/kvm/vcpu.c

1746

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_BADV);

arch/loongarch/kvm/vcpu.c

1747

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_BADI);

arch/loongarch/kvm/vcpu.c

1748

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_EENTRY);

arch/loongarch/kvm/vcpu.c

1749

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBIDX);

arch/loongarch/kvm/vcpu.c

1750

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBEHI);

arch/loongarch/kvm/vcpu.c

1751

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBELO0);

arch/loongarch/kvm/vcpu.c

1752

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBELO1);

arch/loongarch/kvm/vcpu.c

1753

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ASID);

arch/loongarch/kvm/vcpu.c

1754

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PGDL);

arch/loongarch/kvm/vcpu.c

1755

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PGDH);

arch/loongarch/kvm/vcpu.c

1756

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PWCTL0);

arch/loongarch/kvm/vcpu.c

1757

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PWCTL1);

arch/loongarch/kvm/vcpu.c

1758

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_STLBPGSIZE);

arch/loongarch/kvm/vcpu.c

1759

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_RVACFG);

arch/loongarch/kvm/vcpu.c

1760

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CPUID);

arch/loongarch/kvm/vcpu.c

1761

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG1);

arch/loongarch/kvm/vcpu.c

1762

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG2);

arch/loongarch/kvm/vcpu.c

1763

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG3);

arch/loongarch/kvm/vcpu.c

1764

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS0);

arch/loongarch/kvm/vcpu.c

1765

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS1);

arch/loongarch/kvm/vcpu.c

1766

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS2);

arch/loongarch/kvm/vcpu.c

1767

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS3);

arch/loongarch/kvm/vcpu.c

1768

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS4);

arch/loongarch/kvm/vcpu.c

1769

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS5);

arch/loongarch/kvm/vcpu.c

1770

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS6);

arch/loongarch/kvm/vcpu.c

1771

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS7);

arch/loongarch/kvm/vcpu.c

1772

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TMID);

arch/loongarch/kvm/vcpu.c

1773

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CNTC);

arch/loongarch/kvm/vcpu.c

1774

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL);

arch/loongarch/kvm/vcpu.c

1775

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRENTRY);

arch/loongarch/kvm/vcpu.c

1776

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRBADV);

arch/loongarch/kvm/vcpu.c

1777

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRERA);

arch/loongarch/kvm/vcpu.c

1778

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRSAVE);

arch/loongarch/kvm/vcpu.c

1779

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO0);

arch/loongarch/kvm/vcpu.c

1780

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO1);

arch/loongarch/kvm/vcpu.c

1781

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBREHI);

arch/loongarch/kvm/vcpu.c

1782

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRPRMD);

arch/loongarch/kvm/vcpu.c

1783

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN0);

arch/loongarch/kvm/vcpu.c

1784

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1);

arch/loongarch/kvm/vcpu.c

1785

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2);

arch/loongarch/kvm/vcpu.c

1786

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3);

arch/loongarch/kvm/vcpu.c

1789

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_IPR);

arch/loongarch/kvm/vcpu.c

1790

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR0);

arch/loongarch/kvm/vcpu.c

1791

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR1);

arch/loongarch/kvm/vcpu.c

1792

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR2);

arch/loongarch/kvm/vcpu.c

1793

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR3);

arch/loongarch/kvm/vcpu.c

1801

csr->csrs[LOONGARCH_CSR_GINTC] = read_csr_gintc();

arch/loongarch/kvm/vcpu.c

519

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

525

cpuid = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_CPUID);

arch/loongarch/kvm/vcpu.c

558

kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CPUID, val);

arch/loongarch/kvm/vcpu.c

570

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

573

cpuid = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_CPUID);

arch/loongarch/kvm/vcpu.c

582

kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CPUID, KVM_MAX_PHYID);

arch/loongarch/kvm/vcpu.c

607

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

625

gintc = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff;

arch/loongarch/kvm/vcpu.c

626

*val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2);

arch/loongarch/kvm/vcpu.c

634

*val = kvm_read_sw_gcsr(csr, id);

arch/loongarch/kvm/vcpu.c

642

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

653

kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc);

arch/loongarch/kvm/vcpu.c

656

kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc);

arch/loongarch/kvm/vcpu.c

661

kvm_write_sw_gcsr(csr, id, val);

arch/loongarch/kvm/vcpu.c

670

val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0) |

arch/loongarch/kvm/vcpu.c

671

kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1) |

arch/loongarch/kvm/vcpu.c

672

kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2) |

arch/loongarch/kvm/vcpu.c

673

kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3);

arch/loongarch/kvm/vcpu.c

74

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

76

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR0);

arch/loongarch/kvm/vcpu.c

77

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR1);

arch/loongarch/kvm/vcpu.c

78

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR2);

arch/loongarch/kvm/vcpu.c

79

kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR3);

arch/loongarch/kvm/vcpu.c

80

kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0);

arch/loongarch/kvm/vcpu.c

81

kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1);

arch/loongarch/kvm/vcpu.c

82

kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2);

arch/loongarch/kvm/vcpu.c

83

kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3);

arch/loongarch/kvm/vcpu.c

88

struct loongarch_csrs *csr = vcpu->arch.csr;

arch/loongarch/kvm/vcpu.c

90

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR0);

arch/loongarch/kvm/vcpu.c

91

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR1);

arch/loongarch/kvm/vcpu.c

92

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR2);

arch/loongarch/kvm/vcpu.c

93

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR3);

arch/loongarch/kvm/vcpu.c

94

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0);

arch/loongarch/kvm/vcpu.c

95

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1);

arch/loongarch/kvm/vcpu.c

96

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2);

arch/loongarch/kvm/vcpu.c

97

kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3);

arch/loongarch/kvm/vcpu.c

971

kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_GINTC, 0);

arch/loongarch/kvm/vcpu.c

972

kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_ESTAT, 0);

arch/m68k/sun3x/time.c

49

h->csr |= C_WRITE;

arch/m68k/sun3x/time.c

57

h->csr &= ~C_WRITE;

arch/m68k/sun3x/time.c

59

h->csr |= C_READ;

arch/m68k/sun3x/time.c

67

h->csr &= ~C_READ;

arch/m68k/sun3x/time.h

9

volatile unsigned char csr;

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

53

union cvmx_asxx_int_en csr;

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

65

csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

66

csr.s.txpsh = mask;

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

67

csr.s.txpop = mask;

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

68

csr.s.ovrflw = mask;

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

69

cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);

arch/mips/dec/ecc-berr.c

227

volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);

arch/mips/dec/ecc-berr.c

233

cached_kn02_csr = *csr | KN02_CSR_LEDS;

arch/mips/dec/ecc-berr.c

239

*csr = cached_kn02_csr;

arch/mips/dec/kn01-berr.c

150

volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);

arch/mips/dec/kn01-berr.c

154

if (!(*csr & KN01_CSR_MEMERR))

arch/mips/dec/kn01-berr.c

177

volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);

arch/mips/dec/kn01-berr.c

183

cached_kn01_csr = *csr;

arch/mips/dec/kn01-berr.c

189

*csr = cached_kn01_csr;

arch/mips/dec/kn01-berr.c

49

volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);

arch/mips/dec/kn01-berr.c

54

*csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */

arch/mips/dec/kn02-irq.c

30

volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

arch/mips/dec/kn02-irq.c

34

*csr = cached_kn02_csr;

arch/mips/dec/kn02-irq.c

39

volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

arch/mips/dec/kn02-irq.c

43

*csr = cached_kn02_csr;

arch/mips/dec/kn02-irq.c

62

volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

arch/mips/dec/kn02-irq.c

68

*csr = cached_kn02_csr;

arch/mips/include/asm/msa.h

213

__BUILD_MSA_CTL_REG(csr, 1)

arch/mips/include/asm/octeon/cvmx-npei-defs.h

3791

uint64_t csr:39;

arch/mips/include/asm/octeon/cvmx-npei-defs.h

3793

uint64_t csr:39;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1295

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1323

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1330

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1360

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1368

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1404

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1412

uint64_t csr:1;

arch/mips/include/asm/octeon/cvmx-pko-defs.h

1448

uint64_t csr:1;

arch/mips/include/asm/sibyte/sb1250_defs.h

242

#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)

arch/mips/include/asm/sibyte/sb1250_defs.h

243

#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))

arch/mips/include/uapi/asm/ucontext.h

40

unsigned int csr;

arch/mips/kernel/irq_txx9.c

173

u32 csr = __raw_readl(&txx9_ircptr->csr);

arch/mips/kernel/irq_txx9.c

175

if (likely(!(csr & TXx9_IRCSR_IF)))

arch/mips/kernel/irq_txx9.c

176

return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));

arch/mips/kernel/irq_txx9.c

34

u32 csr;

arch/mips/kernel/mips-r2-to-r6-emul.c

201

u32 csr;

arch/mips/kernel/mips-r2-to-r6-emul.c

204

csr = current->thread.fpu.fcr31;

arch/mips/kernel/mips-r2-to-r6-emul.c

207

if (((csr & cond) == 0) && MIPSInst_RD(ir))

arch/mips/kernel/mips-r2-to-r6-emul.c

224

u32 csr;

arch/mips/kernel/mips-r2-to-r6-emul.c

227

csr = current->thread.fpu.fcr31;

arch/mips/kernel/mips-r2-to-r6-emul.c

230

if (((csr & cond) != 0) && MIPSInst_RD(ir))

arch/mips/kernel/signal-common.h

36

_save_fp_context(void __user *fpregs, void __user *csr);

arch/mips/kernel/signal-common.h

38

_restore_fp_context(void __user *fpregs, void __user *csr);

arch/mips/kernel/signal.c

104

err |= __get_user(current->thread.fpu.fcr31, csr);

arch/mips/kernel/signal.c

130

uint32_t __user *csr = sc + abi->off_sc_fpc_csr;

arch/mips/kernel/signal.c

132

return _save_fp_context(fpregs, csr);

arch/mips/kernel/signal.c

139

uint32_t __user *csr = sc + abi->off_sc_fpc_csr;

arch/mips/kernel/signal.c

141

return _restore_fp_context(fpregs, csr);

arch/mips/kernel/signal.c

188

err = __put_user(read_msa_csr(), &msa->csr);

arch/mips/kernel/signal.c

195

err = __put_user(current->thread.fpu.msacsr, &msa->csr);

arch/mips/kernel/signal.c

213

unsigned int csr;

arch/mips/kernel/signal.c

219

err = get_user(csr, &msa->csr);

arch/mips/kernel/signal.c

235

write_msa_csr(csr);

arch/mips/kernel/signal.c

241

current->thread.fpu.msacsr = csr;

arch/mips/kernel/signal.c

329

uint32_t __user *csr = sc + abi->off_sc_fpc_csr;

arch/mips/kernel/signal.c

364

__put_user(0, csr);

arch/mips/kernel/signal.c

382

uint32_t __user *csr = sc + abi->off_sc_fpc_csr;

arch/mips/kernel/signal.c

401

err = sig = fpcsr_pending(csr);

arch/mips/kernel/signal.c

427

__get_user(tmp, csr);

arch/mips/kernel/signal.c

500

unsigned int csr, enabled;

arch/mips/kernel/signal.c

502

err = __get_user(csr, fpcsr);

arch/mips/kernel/signal.c

503

enabled = FPU_CSR_UNI_X | ((csr & FPU_CSR_ALL_E) << 5);

arch/mips/kernel/signal.c

508

if (csr & enabled) {

arch/mips/kernel/signal.c

509

csr &= ~enabled;

arch/mips/kernel/signal.c

510

err |= __put_user(csr, fpcsr);

arch/mips/kernel/signal.c

75

uint32_t __user *csr = sc + abi->off_sc_fpc_csr;

arch/mips/kernel/signal.c

85

err |= __put_user(current->thread.fpu.fcr31, csr);

arch/mips/kernel/signal.c

94

uint32_t __user *csr = sc + abi->off_sc_fpc_csr;

arch/powerpc/boot/ugecon.c

43

u32 csr, data, cr;

arch/powerpc/boot/ugecon.c

46

csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;

arch/powerpc/boot/ugecon.c

47

out_be32(csr_reg, csr);

arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c

51

u32 csr, data, cr;

arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c

54

csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;

arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c

55

out_be32(csr_reg, csr);

arch/riscv/include/asm/csr.h

549

#define csr_swap(csr, val) \

arch/riscv/include/asm/csr.h

552

__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\

arch/riscv/include/asm/csr.h

558

#define csr_read(csr) \

arch/riscv/include/asm/csr.h

561

__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

arch/riscv/include/asm/csr.h

567

#define csr_write(csr, val) \

arch/riscv/include/asm/csr.h

570

__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \

arch/riscv/include/asm/csr.h

575

#define csr_read_set(csr, val) \

arch/riscv/include/asm/csr.h

578

__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\

arch/riscv/include/asm/csr.h

584

#define csr_set(csr, val) \

arch/riscv/include/asm/csr.h

587

__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \

arch/riscv/include/asm/csr.h

592

#define csr_read_clear(csr, val) \

arch/riscv/include/asm/csr.h

595

__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\

arch/riscv/include/asm/csr.h

601

#define csr_clear(csr, val) \

arch/riscv/include/asm/csr.h

604

__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \

arch/riscv/include/asm/sbi.h

147

unsigned long csr:12;

arch/riscv/kernel/vector.c

105

csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);

arch/riscv/kernel/vector.c

106

if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||

arch/riscv/kernel/vector.c

107

(csr >= CSR_VL && csr <= CSR_VLENB))

arch/riscv/kernel/vector.c

84

u32 width, csr;

arch/riscv/kvm/aia.c

100

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/aia.c

108

ncsr_write(CSR_HVICTL, aia_hvictl_value(!!(csr->hvip & BIT(IRQ_VS_EXT))));

arch/riscv/kvm/aia.c

113

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia.c

121

nacl_csr_write(nsh, CSR_VSISELECT, csr->vsiselect);

arch/riscv/kvm/aia.c

122

nacl_csr_write(nsh, CSR_HVIPRIO1, csr->hviprio1);

arch/riscv/kvm/aia.c

123

nacl_csr_write(nsh, CSR_HVIPRIO2, csr->hviprio2);

arch/riscv/kvm/aia.c

125

nacl_csr_write(nsh, CSR_VSIEH, csr->vsieh);

arch/riscv/kvm/aia.c

126

nacl_csr_write(nsh, CSR_HVIPH, csr->hviph);

arch/riscv/kvm/aia.c

127

nacl_csr_write(nsh, CSR_HVIPRIO1H, csr->hviprio1h);

arch/riscv/kvm/aia.c

128

nacl_csr_write(nsh, CSR_HVIPRIO2H, csr->hviprio2h);

arch/riscv/kvm/aia.c

131

csr_write(CSR_VSISELECT, csr->vsiselect);

arch/riscv/kvm/aia.c

132

csr_write(CSR_HVIPRIO1, csr->hviprio1);

arch/riscv/kvm/aia.c

133

csr_write(CSR_HVIPRIO2, csr->hviprio2);

arch/riscv/kvm/aia.c

135

csr_write(CSR_VSIEH, csr->vsieh);

arch/riscv/kvm/aia.c

136

csr_write(CSR_HVIPH, csr->hviph);

arch/riscv/kvm/aia.c

137

csr_write(CSR_HVIPRIO1H, csr->hviprio1h);

arch/riscv/kvm/aia.c

138

csr_write(CSR_HVIPRIO2H, csr->hviprio2h);

arch/riscv/kvm/aia.c

148

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia.c

159

csr->vsiselect = nacl_csr_read(nsh, CSR_VSISELECT);

arch/riscv/kvm/aia.c

160

csr->hviprio1 = nacl_csr_read(nsh, CSR_HVIPRIO1);

arch/riscv/kvm/aia.c

161

csr->hviprio2 = nacl_csr_read(nsh, CSR_HVIPRIO2);

arch/riscv/kvm/aia.c

163

csr->vsieh = nacl_csr_read(nsh, CSR_VSIEH);

arch/riscv/kvm/aia.c

164

csr->hviph = nacl_csr_read(nsh, CSR_HVIPH);

arch/riscv/kvm/aia.c

165

csr->hviprio1h = nacl_csr_read(nsh, CSR_HVIPRIO1H);

arch/riscv/kvm/aia.c

166

csr->hviprio2h = nacl_csr_read(nsh, CSR_HVIPRIO2H);

arch/riscv/kvm/aia.c

169

csr->vsiselect = csr_read(CSR_VSISELECT);

arch/riscv/kvm/aia.c

170

csr->hviprio1 = csr_read(CSR_HVIPRIO1);

arch/riscv/kvm/aia.c

171

csr->hviprio2 = csr_read(CSR_HVIPRIO2);

arch/riscv/kvm/aia.c

173

csr->vsieh = csr_read(CSR_VSIEH);

arch/riscv/kvm/aia.c

174

csr->hviph = csr_read(CSR_HVIPH);

arch/riscv/kvm/aia.c

175

csr->hviprio1h = csr_read(CSR_HVIPRIO1H);

arch/riscv/kvm/aia.c

176

csr->hviprio2h = csr_read(CSR_HVIPRIO2H);

arch/riscv/kvm/aia.c

185

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia.c

197

*out_val = ((unsigned long *)csr)[reg_num];

arch/riscv/kvm/aia.c

206

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia.c

217

((unsigned long *)csr)[reg_num] = val;

arch/riscv/kvm/aia.c

51

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia.c

61

csr->hviph &= ~mask;

arch/riscv/kvm/aia.c

62

csr->hviph |= val;

arch/riscv/kvm/aia.c

68

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia.c

71

csr->vsieh = ncsr_read(CSR_VSIEH);

arch/riscv/kvm/aia_device.c

508

struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;

arch/riscv/kvm/aia_device.c

512

memset(csr, 0, sizeof(*csr));

arch/riscv/kvm/vcpu.c

349

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

356

csr->hvip &= ~mask;

arch/riscv/kvm/vcpu.c

357

csr->hvip |= val;

arch/riscv/kvm/vcpu.c

368

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

371

csr->vsie = ncsr_read(CSR_VSIE);

arch/riscv/kvm/vcpu.c

375

if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {

arch/riscv/kvm/vcpu.c

388

if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) {

arch/riscv/kvm/vcpu.c

57

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

581

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

586

nacl_csr_write(nsh, CSR_VSSTATUS, csr->vsstatus);

arch/riscv/kvm/vcpu.c

587

nacl_csr_write(nsh, CSR_VSIE, csr->vsie);

arch/riscv/kvm/vcpu.c

588

nacl_csr_write(nsh, CSR_VSTVEC, csr->vstvec);

arch/riscv/kvm/vcpu.c

589

nacl_csr_write(nsh, CSR_VSSCRATCH, csr->vsscratch);

arch/riscv/kvm/vcpu.c

590

nacl_csr_write(nsh, CSR_VSEPC, csr->vsepc);

arch/riscv/kvm/vcpu.c

591

nacl_csr_write(nsh, CSR_VSCAUSE, csr->vscause);

arch/riscv/kvm/vcpu.c

592

nacl_csr_write(nsh, CSR_VSTVAL, csr->vstval);

arch/riscv/kvm/vcpu.c

594

nacl_csr_write(nsh, CSR_HVIP, csr->hvip);

arch/riscv/kvm/vcpu.c

595

nacl_csr_write(nsh, CSR_VSATP, csr->vsatp);

arch/riscv/kvm/vcpu.c

605

csr_write(CSR_VSSTATUS, csr->vsstatus);

arch/riscv/kvm/vcpu.c

606

csr_write(CSR_VSIE, csr->vsie);

arch/riscv/kvm/vcpu.c

607

csr_write(CSR_VSTVEC, csr->vstvec);

arch/riscv/kvm/vcpu.c

608

csr_write(CSR_VSSCRATCH, csr->vsscratch);

arch/riscv/kvm/vcpu.c

609

csr_write(CSR_VSEPC, csr->vsepc);

arch/riscv/kvm/vcpu.c

610

csr_write(CSR_VSCAUSE, csr->vscause);

arch/riscv/kvm/vcpu.c

611

csr_write(CSR_VSTVAL, csr->vstval);

arch/riscv/kvm/vcpu.c

613

csr_write(CSR_HVIP, csr->hvip);

arch/riscv/kvm/vcpu.c

614

csr_write(CSR_VSATP, csr->vsatp);

arch/riscv/kvm/vcpu.c

62

memset(csr, 0, sizeof(*csr));

arch/riscv/kvm/vcpu.c

646

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

663

csr->vsstatus = nacl_csr_read(nsh, CSR_VSSTATUS);

arch/riscv/kvm/vcpu.c

664

csr->vsie = nacl_csr_read(nsh, CSR_VSIE);

arch/riscv/kvm/vcpu.c

665

csr->vstvec = nacl_csr_read(nsh, CSR_VSTVEC);

arch/riscv/kvm/vcpu.c

666

csr->vsscratch = nacl_csr_read(nsh, CSR_VSSCRATCH);

arch/riscv/kvm/vcpu.c

667

csr->vsepc = nacl_csr_read(nsh, CSR_VSEPC);

arch/riscv/kvm/vcpu.c

668

csr->vscause = nacl_csr_read(nsh, CSR_VSCAUSE);

arch/riscv/kvm/vcpu.c

669

csr->vstval = nacl_csr_read(nsh, CSR_VSTVAL);

arch/riscv/kvm/vcpu.c

670

csr->hvip = nacl_csr_read(nsh, CSR_HVIP);

arch/riscv/kvm/vcpu.c

671

csr->vsatp = nacl_csr_read(nsh, CSR_VSATP);

arch/riscv/kvm/vcpu.c

673

csr->vsstatus = csr_read(CSR_VSSTATUS);

arch/riscv/kvm/vcpu.c

674

csr->vsie = csr_read(CSR_VSIE);

arch/riscv/kvm/vcpu.c

675

csr->vstvec = csr_read(CSR_VSTVEC);

arch/riscv/kvm/vcpu.c

676

csr->vsscratch = csr_read(CSR_VSSCRATCH);

arch/riscv/kvm/vcpu.c

677

csr->vsepc = csr_read(CSR_VSEPC);

arch/riscv/kvm/vcpu.c

678

csr->vscause = csr_read(CSR_VSCAUSE);

arch/riscv/kvm/vcpu.c

679

csr->vstval = csr_read(CSR_VSTVAL);

arch/riscv/kvm/vcpu.c

680

csr->hvip = csr_read(CSR_HVIP);

arch/riscv/kvm/vcpu.c

681

csr->vsatp = csr_read(CSR_VSATP);

arch/riscv/kvm/vcpu.c

743

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

745

ncsr_write(CSR_HVIP, csr->hvip);

arch/riscv/kvm/vcpu.c

752

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

755

vcpu->arch.host_scounteren = csr_swap(CSR_SCOUNTEREN, csr->scounteren);

arch/riscv/kvm/vcpu.c

756

vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg);

arch/riscv/kvm/vcpu.c

766

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu.c

769

csr->scounteren = csr_swap(CSR_SCOUNTEREN, vcpu->arch.host_scounteren);

arch/riscv/kvm/vcpu.c

770

csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg);

arch/riscv/kvm/vcpu_onereg.c

517

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu_onereg.c

527

*out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;

arch/riscv/kvm/vcpu_onereg.c

528

*out_val |= csr->hvip & ~IRQ_LOCAL_MASK;

arch/riscv/kvm/vcpu_onereg.c

530

*out_val = ((unsigned long *)csr)[reg_num];

arch/riscv/kvm/vcpu_onereg.c

539

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu_onereg.c

552

((unsigned long *)csr)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

564

struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr;

arch/riscv/kvm/vcpu_onereg.c

575

((unsigned long *)csr)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

583

struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr;

arch/riscv/kvm/vcpu_onereg.c

594

*out_val = ((unsigned long *)csr)[reg_num];

arch/riscv/kvm/vcpu_pmu.c

877

pmc->cinfo.csr = CSR_CYCLE + i;

arch/riscv/kvm/vcpu_sbi.c

184

struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

arch/riscv/kvm/vcpu_sbi.c

196

csr->vsatp = 0;

arch/sh/boards/mach-hp6xx/pm.c

40

u8 stbcr, csr;

arch/sh/boards/mach-hp6xx/pm.c

47

csr = sh_wdt_read_csr();

arch/sh/boards/mach-hp6xx/pm.c

48

csr &= ~WTCSR_TME;

arch/sh/boards/mach-hp6xx/pm.c

49

csr |= WTCSR_CKS_4096;

arch/sh/boards/mach-hp6xx/pm.c

50

sh_wdt_write_csr(csr);

arch/sh/boards/mach-hp6xx/pm.c

51

csr = sh_wdt_read_csr();

arch/sh/kernel/cpu/adc.c

16

unsigned char csr;

arch/sh/kernel/cpu/adc.c

22

csr = __raw_readb(ADCSR);

arch/sh/kernel/cpu/adc.c

23

csr = channel | ADCSR_ADST | ADCSR_CKS;

arch/sh/kernel/cpu/adc.c

24

__raw_writeb(csr, ADCSR);

arch/sh/kernel/cpu/adc.c

27

csr = __raw_readb(ADCSR);

arch/sh/kernel/cpu/adc.c

28

} while ((csr & ADCSR_ADF) == 0);

arch/sh/kernel/cpu/adc.c

30

csr &= ~(ADCSR_ADF | ADCSR_ADST);

arch/sh/kernel/cpu/adc.c

31

__raw_writeb(csr, ADCSR);

arch/sparc/kernel/ebus.c

113

csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT;

arch/sparc/kernel/ebus.c

116

csr |= EBDMA_CSR_TCI_DIS;

arch/sparc/kernel/ebus.c

118

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

127

u32 csr;

arch/sparc/kernel/ebus.c

136

csr = readl(p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

137

csr |= EBDMA_CSR_INT_EN;

arch/sparc/kernel/ebus.c

138

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

142

csr = readl(p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

143

csr &= ~EBDMA_CSR_INT_EN;

arch/sparc/kernel/ebus.c

144

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

159

u32 csr;

arch/sparc/kernel/ebus.c

163

csr = readl(p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

164

if (csr & EBDMA_CSR_INT_EN) {

arch/sparc/kernel/ebus.c

165

csr &= ~EBDMA_CSR_INT_EN;

arch/sparc/kernel/ebus.c

166

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

179

u32 csr;

arch/sparc/kernel/ebus.c

186

csr = readl(p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

188

if (!(csr & EBDMA_CSR_EN_DMA))

arch/sparc/kernel/ebus.c

191

if (csr & EBDMA_CSR_NA_LOADED)

arch/sparc/kernel/ebus.c

208

u32 csr;

arch/sparc/kernel/ebus.c

213

csr = (EBDMA_CSR_INT_EN |

arch/sparc/kernel/ebus.c

219

csr |= EBDMA_CSR_WRITE;

arch/sparc/kernel/ebus.c

221

csr |= EBDMA_CSR_TCI_DIS;

arch/sparc/kernel/ebus.c

223

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

244

u32 orig_csr, csr;

arch/sparc/kernel/ebus.c

247

orig_csr = csr = readl(p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

249

csr |= EBDMA_CSR_EN_DMA;

arch/sparc/kernel/ebus.c

251

csr &= ~EBDMA_CSR_EN_DMA;

arch/sparc/kernel/ebus.c

253

(csr & EBDMA_CSR_EN_DMA))

arch/sparc/kernel/ebus.c

254

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

74

u32 csr = 0;

arch/sparc/kernel/ebus.c

77

csr = readl(p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

78

writel(csr, p->regs + EBDMA_CSR);

arch/sparc/kernel/ebus.c

81

if (csr & EBDMA_CSR_ERR_PEND) {

arch/sparc/kernel/ebus.c

85

} else if (csr & EBDMA_CSR_INT_PEND) {

arch/sparc/kernel/ebus.c

87

(csr & EBDMA_CSR_TC) ?

arch/sparc/kernel/ebus.c

99

u32 csr;

arch/sparc/kernel/pci_schizo.c

587

unsigned long csr_reg, csr, csr_error_bits;

arch/sparc/kernel/pci_schizo.c

592

csr = upa_readq(csr_reg);

arch/sparc/kernel/pci_schizo.c

594

csr & (SCHIZO_PCICTRL_BUS_UNUS |

arch/sparc/kernel/pci_schizo.c

602

upa_writeq(csr, csr_reg);

arch/sparc/kernel/psycho_common.c

257

u64 csr, csr_error_bits;

arch/sparc/kernel/psycho_common.c

260

csr = upa_readq(pbm->pci_csr);

arch/sparc/kernel/psycho_common.c

261

csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);

arch/sparc/kernel/psycho_common.c

264

upa_writeq(csr, pbm->pci_csr);

drivers/ata/ahci_xgene.c

768

void __iomem *csr = devm_ioremap_resource(dev, res);

drivers/ata/ahci_xgene.c

769

if (IS_ERR(csr))

drivers/ata/ahci_xgene.c

770

return PTR_ERR(csr);

drivers/ata/ahci_xgene.c

772

ctx->csr_mux = csr;

drivers/clk/clk-xgene.c

32

static inline u32 xgene_clk_read(void __iomem *csr)

drivers/clk/clk-xgene.c

34

return readl_relaxed(csr);

drivers/clk/clk-xgene.c

37

static inline void xgene_clk_write(u32 data, void __iomem *csr)

drivers/clk/clk-xgene.c

39

writel_relaxed(data, csr);

drivers/clk/imx/clk-pllv4.c

62

u32 csr;

drivers/clk/imx/clk-pllv4.c

65

csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);

drivers/cpuidle/cpuidle-tegra.c

53

unsigned long cpu, lcpu, csr;

drivers/cpuidle/cpuidle-tegra.c

57

csr = flowctrl_read_cpu_csr(cpu);

drivers/cpuidle/cpuidle-tegra.c

60

cpu, cpu_online(lcpu), csr);

drivers/crypto/cavium/nitrox/nitrox_mbx.c

124

DECLARE_BITMAP(csr, BITS_PER_TYPE(u64));

drivers/crypto/cavium/nitrox/nitrox_mbx.c

134

bitmap_from_u64(csr, value);

drivers/crypto/cavium/nitrox/nitrox_mbx.c

135

for_each_set_bit(i, csr, BITS_PER_TYPE(csr)) {

drivers/crypto/cavium/nitrox/nitrox_mbx.c

157

bitmap_from_u64(csr, value);

drivers/crypto/cavium/nitrox/nitrox_mbx.c

158

for_each_set_bit(i, csr, BITS_PER_TYPE(csr)) {

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

357

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

363

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, ADF_GEN6_VFLNOTIFY);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

407

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

411

ADF_CSR_WR(csr, ADF_GEN6_MSIX_RTTABLE_OFFSET(i), i);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

414

static int reset_ring_pair(void __iomem *csr, u32 bank_number)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

424

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

432

csr, ADF_WQM_CSR_RPRESETSTS(bank_number));

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

437

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number), ADF_WQM_CSR_RPRESETSTS_STATUS);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

445

void __iomem *csr = adf_get_etr_base(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

453

ret = reset_ring_pair(csr, bank_number);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

576

static void set_vc_csr_for_bank(void __iomem *csr, u32 bank_number)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

584

value = ADF_CSR_RD(csr, ADF_GEN6_CSR_RINGMODECTL(bank_number));

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

587

ADF_CSR_WR(csr, ADF_GEN6_CSR_RINGMODECTL(bank_number), value);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

623

void __iomem *csr = adf_get_etr_base(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

628

set_vc_csr_for_bank(csr, i);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

782

u32 csr;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

786

csr = ADF_CSR_RD(addr, ADF_GEN6_ERRMSK2);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

787

csr |= ADF_GEN6_PM_SOU;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

788

ADF_CSR_WR(addr, ADF_GEN6_ERRMSK2, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

117

u32 csr;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

123

csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

124

csr |= ADF_GEN4_PM_SOU;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

125

ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

171

void __iomem *csr;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

174

csr = (&GET_BARS(accel_dev)[ADF_GEN4_PMISC_BAR])->virt_addr;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

176

ADF_CSR_WR(csr, ADF_GEN4_MSIX_RTTABLE_OFFSET(i), i);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

186

static int reset_ring_pair(void __iomem *csr, u32 bank_number)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

195

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

203

csr, ADF_WQM_CSR_RPRESETSTS(bank_number));

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

206

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

216

void __iomem *csr = adf_get_etr_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

225

ret = reset_ring_pair(csr, bank_number);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

455

static int drain_bank(void __iomem *csr, u32 bank_number, int timeout_us)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

459

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

465

csr, ADF_WQM_CSR_RPRESETSTS(bank_number));

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

471

void __iomem *csr = adf_get_etr_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

473

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

480

void __iomem *csr = adf_get_etr_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

485

ret = drain_bank(csr, bank_number, timeout_us);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

91

void __iomem *csr = misc_bar->virt_addr;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

94

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_VFLNOTIFY);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

10

static void enable_errsou_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1000

reset_required |= adf_handle_spp_pulldata_err(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1001

reset_required |= adf_handle_spp_pushcmd_err(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1002

reset_required |= adf_handle_spp_pushdata_err(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1008

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1018

reg = ADF_CSR_RD(csr, ADF_GEN4_SSMCPPERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

102

ADF_CSR_WR(csr, ADF_GEN4_RI_MEM_PAR_ERR_EN0,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1041

ADF_CSR_WR(csr, ADF_GEN4_SSMCPPERR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1047

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1059

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

107

ADF_CSR_WR(csr, ADF_GEN4_RIMISCCTL, ADF_GEN4_RIMISCSTS_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1070

reg = ADF_CSR_RD(csr, ADF_GEN4_SER_ERR_SSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

110

ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1106

ADF_CSR_WR(csr, ADF_GEN4_SER_ERR_SSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

111

ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1112

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1114

u32 iastatssm = ADF_CSR_RD(csr, ADF_GEN4_IAINTSTATSSM);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

112

ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1121

reset_required = adf_handle_uerrssmsh(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1122

reset_required |= adf_handle_cerrssmsh(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1123

reset_required |= adf_handle_pperr_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1124

reset_required |= adf_handle_slice_hang_error(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1125

reset_required |= adf_handle_spppar_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1126

reset_required |= adf_handle_ssmcpppar_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1127

reset_required |= adf_handle_ser_err_ssmsh(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1128

adf_handle_rf_parr_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

113

ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1130

ADF_CSR_WR(csr, ADF_GEN4_IAINTSTATSSM, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1136

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1138

u32 reg = ADF_CSR_RD(csr, ADF_GEN4_EXPRPSSMCPR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

114

ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1149

ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMCPR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1155

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1157

u32 reg = ADF_CSR_RD(csr, ADF_GEN4_EXPRPSSMXLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

117

ADF_CSR_WR(csr, ADF_GEN4_RICPPINTCTL, ADF_GEN4_RICPPINTCTL_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1178

ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMXLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1184

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

119

ADF_CSR_WR(csr, ADF_GEN4_TICPPINTCTL, ADF_GEN4_TICPPINTCTL_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1190

reg = ADF_CSR_RD(csr, ADF_GEN4_EXPRPSSMDCPR(i));

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1210

ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMDCPR(i), reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1216

static bool adf_handle_ssm(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1224

reset_required = adf_handle_iaintstatssm(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1225

reset_required |= adf_handle_exprpssmcmpr(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1226

reset_required |= adf_handle_exprpssmxlt(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1227

reset_required |= adf_handle_exprpssmdcpr(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1233

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1241

reg = ADF_CSR_RD(csr, ADF_GEN4_CPP_CFC_ERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

125

reg = ADF_CSR_RD(csr, ADF_GEN4_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1264

ADF_CSR_WR(csr, ADF_GEN4_CPP_CFC_ERR_STATUS_CLR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1271

void __iomem *csr, u32 errsou,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1274

*reset_required |= adf_handle_ssm(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1275

*reset_required |= adf_handle_cpp_cfc_err(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1279

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

128

ADF_CSR_WR(csr, ADF_GEN4_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1286

timiscsts = ADF_CSR_RD(csr, ADF_GEN4_TIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1297

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

13

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1304

ricppintsts = ADF_CSR_RD(csr, ADF_GEN4_RICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

131

static void disable_ti_ri_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1312

ADF_CSR_WR(csr, ADF_GEN4_RICPPINTSTS, ricppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1318

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1325

ticppintsts = ADF_CSR_RD(csr, ADF_GEN4_TICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1333

ADF_CSR_WR(csr, ADF_GEN4_TICPPINTSTS, ticppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1339

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1346

aram_cerr = ADF_CSR_RD(csr, ADF_GEN4_REG_ARAMCERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1356

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR, aram_cerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

136

ADF_CSR_WR(csr, ADF_GEN4_RI_MEM_PAR_ERR_EN0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1362

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1370

aramuerr = ADF_CSR_RD(csr, ADF_GEN4_REG_ARAMUERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

139

ADF_CSR_WR(csr, ADF_GEN4_RIMISCCTL, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1393

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR, aramuerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1399

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1407

cppmemtgterr = ADF_CSR_RD(csr, ADF_GEN4_REG_CPPMEMTGTERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

142

ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1429

ADF_CSR_WR(csr, ADF_GEN4_REG_CPPMEMTGTERR, cppmemtgterr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1435

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

144

ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1444

u32 atufaultstatus = ADF_CSR_RD(csr, ADF_GEN4_ATUFAULTSTATUS(i));

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1455

ADF_CSR_WR(csr, ADF_GEN4_ATUFAULTSTATUS(i), atufaultstatus);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

146

ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1463

void __iomem *csr, void __iomem *aram_csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1466

*reset_required |= adf_handle_timiscsts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1467

*reset_required |= adf_handle_ricppintsts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1468

*reset_required |= adf_handle_ticppintsts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1472

*reset_required |= adf_handle_atufaultstatus(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1479

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

148

ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1480

u32 errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1486

adf_gen4_process_errsou0(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1490

errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU1);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1492

adf_gen4_process_errsou1(accel_dev, csr, errsou, reset_required);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1496

errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1498

adf_gen4_process_errsou2(accel_dev, csr, errsou, reset_required);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

150

ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1502

errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1504

adf_gen4_process_errsou3(accel_dev, csr, aram_csr, errsou, reset_required);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

154

ADF_CSR_WR(csr, ADF_GEN4_RICPPINTCTL, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

156

ADF_CSR_WR(csr, ADF_GEN4_TICPPINTCTL, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

16

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

162

reg = ADF_CSR_RD(csr, ADF_GEN4_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

164

ADF_CSR_WR(csr, ADF_GEN4_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

168

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

173

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_SRC, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

174

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_ATH_CPH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

175

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_CPR_XLT, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

176

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_DCPR_UCS, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

177

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_PKE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

180

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_WAT_WCP, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

184

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

189

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_SRC,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

192

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_ATH_CPH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

195

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_CPR_XLT,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

198

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_DCPR_UCS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

201

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_PKE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

205

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

210

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

216

ADF_CSR_WR(csr, ADF_GEN4_INTMASKSSM, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

219

val = ADF_CSR_RD(csr, ADF_GEN4_SSMFEATREN);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

22

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

221

ADF_CSR_WR(csr, ADF_GEN4_SSMFEATREN, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

224

ADF_CSR_WR(csr, ADF_GEN4_SER_EN_SSMSH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

228

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_ATH_CPH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

229

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_CPR_XLT, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

230

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_DCPR_UCS, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

231

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_PKE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

234

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_WAT_WCP, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

237

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_ATH_CPH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

238

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_CPR_XLT, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

239

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_DCPR_UCS, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

240

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_PKE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

243

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_WAT_WCP, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

247

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

253

ADF_CSR_WR(csr, ADF_GEN4_INTMASKSSM,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

257

val = ADF_CSR_RD(csr, ADF_GEN4_SSMFEATREN);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

259

ADF_CSR_WR(csr, ADF_GEN4_SSMFEATREN, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

262

ADF_CSR_WR(csr, ADF_GEN4_SER_EN_SSMSH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

265

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_ATH_CPH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

268

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_CPR_XLT,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

271

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_DCPR_UCS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

274

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_PKE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

278

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

282

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_ATH_CPH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

285

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_CPR_XLT,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

288

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_DCPR_UCS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

291

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_PKE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

295

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

299

static void enable_aram_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

30

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

301

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERRUERR_EN,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

304

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

307

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

310

ADF_CSR_WR(csr, ADF_GEN4_REG_CPPMEMTGTERR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

314

static void disable_aram_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

316

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERRUERR_EN, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

317

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

318

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

319

ADF_CSR_WR(csr, ADF_GEN4_REG_CPPMEMTGTERR, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

325

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

327

enable_errsou_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

328

enable_ae_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

329

enable_cpp_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

330

enable_ti_ri_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

331

enable_rf_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

332

enable_ssm_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

339

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

341

disable_errsou_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

342

disable_ae_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

343

disable_cpp_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

344

disable_ti_ri_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

345

disable_rf_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

346

disable_ssm_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

35

static void disable_errsou_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

351

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

353

u32 aecorrerr = ADF_CSR_RD(csr, ADF_GEN4_HIAECORERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

364

ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOG_CPP0, aecorrerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

368

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

375

aeuncorerr = ADF_CSR_RD(csr, ADF_GEN4_HIAEUNCERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

384

ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOG_CPP0, aeuncorerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

390

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

398

cmdparerr = ADF_CSR_RD(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOG);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

40

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, ADF_GEN4_ERRSOU0_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

407

ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOG, cmdparerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

413

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

421

rimem_parerr_sts = ADF_CSR_RD(csr, ADF_GEN4_RIMEM_PARERR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

43

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, ADF_GEN4_ERRSOU1_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

440

ADF_CSR_WR(csr, ADF_GEN4_RIMEM_PARERR_STS, rimem_parerr_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

446

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

453

ti_ci_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_CI_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

459

ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_STS, ti_ci_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

46

val = ADF_CSR_RD(csr, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

467

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

474

ti_pullfub_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_PULL0FUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

48

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

481

ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_STS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

491

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

498

ti_pushfub_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_PUSHFUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

507

ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_STS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

51

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_ERRSOU3_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

515

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

522

ti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_CD_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

531

ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_STS, ti_cd_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

538

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

545

ti_trnsb_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_TRNSB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

55

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

554

ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_STS, ti_trnsb_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

561

void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

568

rimiscsts = ADF_CSR_RD(csr, ADF_GEN4_RIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

577

ADF_CSR_WR(csr, ADF_GEN4_RIMISCSTS, rimiscsts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

583

void __iomem *csr, u32 errsou,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

586

*reset_required |= adf_handle_cpp_aeunc(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

587

*reset_required |= adf_handle_cppcmdparerr(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

588

*reset_required |= adf_handle_ri_mem_par_err(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

589

*reset_required |= adf_handle_ti_ci_par_sts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

590

*reset_required |= adf_handle_ti_pullfub_par_sts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

591

*reset_required |= adf_handle_ti_pushfub_par_sts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

592

*reset_required |= adf_handle_ti_cd_par_sts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

593

*reset_required |= adf_handle_ti_trnsb_par_sts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

594

*reset_required |= adf_handle_iosfp_cmd_parerr(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

598

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

60

ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

605

reg = ADF_CSR_RD(csr, ADF_GEN4_UERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

614

ADF_CSR_WR(csr, ADF_GEN4_UERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

620

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

627

reg = ADF_CSR_RD(csr, ADF_GEN4_CERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

63

ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

636

ADF_CSR_WR(csr, ADF_GEN4_CERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

642

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

649

reg = ADF_CSR_RD(csr, ADF_GEN4_PPERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

658

ADF_CSR_WR(csr, ADF_GEN4_PPERR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

66

static void disable_ae_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

664

void __iomem *csr, u32 slice_hang_offset,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

667

u32 slice_hang_reg = ADF_CSR_RD(csr, slice_hang_offset);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

679

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

686

adf_poll_slicehang_csr(accel_dev, csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

688

adf_poll_slicehang_csr(accel_dev, csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

69

ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

690

adf_poll_slicehang_csr(accel_dev, csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

692

adf_poll_slicehang_csr(accel_dev, csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

696

adf_poll_slicehang_csr(accel_dev, csr,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

704

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

710

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

718

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

72

ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

723

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

731

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

736

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

744

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

749

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

757

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

76

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

763

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

771

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_WAT_WCP, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

781

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

786

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

794

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

797

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

805

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

808

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

81

ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOGENABLE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

816

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

819

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

827

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

831

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

839

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_WAT_WCP, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

84

ADF_CSR_WR(csr, ADF_GEN4_CPP_CFC_ERR_CTRL,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

847

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

853

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

861

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

866

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

874

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

879

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

88

static void disable_cpp_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

887

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

892

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

901

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

907

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

91

ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOGENABLE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

915

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_WAT_WCP, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

925

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

93

ADF_CSR_WR(csr, ADF_GEN4_CPP_CFC_ERR_CTRL,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

930

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

938

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

941

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

949

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

952

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

960

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

963

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

97

static void enable_ti_ri_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

971

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

975

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

983

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

992

void __iomem *csr, u32 iastatssm)

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

999

reset_required = adf_handle_spp_pullcmd_err(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

438

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

477

ADF_CSR_WR(csr, misc_states[i].ofs, regv);

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

671

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

711

regv = ADF_CSR_RD(csr, misc_states[i].offset);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

10

static void enable_errsou_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

103

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

105

enable_errsou_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

106

enable_ae_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

107

enable_cpp_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

108

enable_ti_ri_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

109

enable_ssm_error_reporting(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

112

static void disable_errsou_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

117

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, ADF_GEN6_ERRSOU0_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

120

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, ADF_GEN6_ERRMSK1_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

123

val = ADF_CSR_RD(csr, ADF_GEN6_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

125

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

128

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, ADF_GEN6_ERRSOU3_DIS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

13

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

131

static void disable_ae_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

134

ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

137

ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

140

static void disable_cpp_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

143

ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

145

ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_CTRL, ADF_GEN6_CPP_CFC_ERR_CTRL_DIS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

148

static void disable_ti_ri_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

153

ADF_CSR_WR(csr, ADF_GEN6_RI_MEM_PAR_ERR_EN0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

156

reg = ADF_CSR_RD(csr, ADF_GEN6_RIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

158

ADF_CSR_WR(csr, ADF_GEN6_RIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

16

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

161

ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK, ADF_GEN6_TI_CI_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

162

ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK, ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

163

ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK, ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

164

ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK, ADF_GEN6_TI_CD_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

165

ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK, ADF_GEN6_TI_TRNSB_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

168

reg = ADF_CSR_RD(csr, ADF_GEN6_RICPPINTCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

170

ADF_CSR_WR(csr, ADF_GEN6_RICPPINTCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

172

reg = ADF_CSR_RD(csr, ADF_GEN6_TICPPINTCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

174

ADF_CSR_WR(csr, ADF_GEN6_TICPPINTCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

180

reg = ADF_CSR_RD(csr, ADF_GEN6_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

182

ADF_CSR_WR(csr, ADF_GEN6_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

185

static void disable_ssm_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

188

ADF_CSR_WR(csr, ADF_GEN6_INTMASKSSM, ADF_GEN6_INTMASKSSM_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

193

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

195

disable_errsou_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

196

disable_ae_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

197

disable_cpp_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

198

disable_ti_ri_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

199

disable_ssm_error_reporting(csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

202

static void adf_gen6_process_errsou0(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

206

ae = ADF_CSR_RD(csr, ADF_GEN6_HIAECORERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

214

ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOG_CPP0, ae);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

216

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

22

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK2, ADF_GEN6_ERRSOU2_PM_INT_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

221

static void adf_handle_cpp_ae_unc(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

229

ae = ADF_CSR_RD(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

234

ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0, ae);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

238

static void adf_handle_cpp_cmd_par_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

246

cmd_par_err = ADF_CSR_RD(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOG);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

25

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

252

ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOG, cmd_par_err);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

256

static void adf_handle_ri_mem_par_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

264

rimem_parerr_sts = ADF_CSR_RD(csr, ADF_GEN6_RIMEM_PARERR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

279

ADF_CSR_WR(csr, ADF_GEN6_RIMEM_PARERR_STS, rimem_parerr_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

28

static void enable_ae_error_reporting(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

282

static void adf_handle_ti_ci_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

286

ti_ci_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CI_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

290

ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_STS, ti_ci_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

295

static void adf_handle_ti_pullfub_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

299

ti_pullfub_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_PULL0FUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

303

ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_STS, ti_pullfub_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

308

static void adf_handle_ti_pushfub_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

312

ti_pushfub_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_PUSHFUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

317

ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_STS, ti_pushfub_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

321

static void adf_handle_ti_cd_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

325

ti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

33

ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

330

ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_cd_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

334

static void adf_handle_ti_trnsb_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

338

ti_trnsb_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_TRNSB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

343

ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_STS, ti_trnsb_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

347

static void adf_handle_iosfp_cmd_parerr(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

351

rimiscsts = ADF_CSR_RD(csr, ADF_GEN6_RIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

357

ADF_CSR_WR(csr, ADF_GEN6_RIMISCSTS, rimiscsts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

36

ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

361

static void adf_handle_ti_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

367

adf_handle_ti_ci_par_sts(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

368

adf_handle_ti_pullfub_par_sts(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

369

adf_handle_ti_pushfub_par_sts(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

370

adf_handle_ti_cd_par_sts(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

371

adf_handle_ti_trnsb_par_sts(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

372

adf_handle_iosfp_cmd_parerr(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

375

static void adf_handle_sfi_cmd_parerr(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

387

static void adf_gen6_process_errsou1(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

39

static void enable_cpp_error_reporting(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

390

adf_handle_cpp_ae_unc(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

391

adf_handle_cpp_cmd_par_err(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

392

adf_handle_ri_mem_par_err(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

393

adf_handle_ti_err(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

394

adf_handle_sfi_cmd_parerr(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

396

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU1);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

401

static void adf_handle_cerrssmsh(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

405

reg = ADF_CSR_RD(csr, ADF_GEN6_CERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

411

ADF_CSR_WR(csr, ADF_GEN6_CERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

415

static void adf_handle_uerrssmsh(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

42

ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

423

reg = ADF_CSR_RD(csr, ADF_GEN6_UERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

429

ADF_CSR_WR(csr, ADF_GEN6_UERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

433

static void adf_handle_pperr_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

441

reg = ADF_CSR_RD(csr, ADF_GEN6_PPERR);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

447

ADF_CSR_WR(csr, ADF_GEN6_PPERR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

45

ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_CTRL, ADF_GEN6_CPP_CFC_ERR_CTRL_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

451

static void adf_handle_scmpar_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

459

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

464

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

468

static void adf_handle_cpppar_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

476

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

48

static void enable_ti_ri_error_reporting(void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

481

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

485

static void adf_handle_rfpar_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

493

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

498

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

502

static void adf_handle_unexp_cpl_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

510

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

516

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

520

static void adf_handle_iaintstatssm(struct adf_accel_dev *accel_dev, void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

522

u32 iastatssm = ADF_CSR_RD(csr, ADF_GEN6_IAINTSTATSSM);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

528

adf_handle_uerrssmsh(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

529

adf_handle_pperr_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

530

adf_handle_scmpar_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

531

adf_handle_cpppar_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

532

adf_handle_rfpar_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

533

adf_handle_unexp_cpl_err(accel_dev, csr, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

535

ADF_CSR_WR(csr, ADF_GEN6_IAINTSTATSSM, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

538

static void adf_handle_ssm(struct adf_accel_dev *accel_dev, void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

54

ADF_CSR_WR(csr, ADF_GEN6_RI_MEM_PAR_ERR_EN0, mask);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

543

adf_handle_cerrssmsh(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

544

adf_handle_iaintstatssm(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

547

static void adf_handle_cpp_cfc_err(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

555

reg = ADF_CSR_RD(csr, ADF_GEN6_CPP_CFC_ERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

57

ADF_CSR_WR(csr, ADF_GEN6_RIMISCCTL, ADF_GEN6_RIMISCSTS_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

571

ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_STATUS_CLR,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

575

static void adf_gen6_process_errsou2(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

578

adf_handle_ssm(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

579

adf_handle_cpp_cfc_err(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

581

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

586

static void adf_handle_timiscsts(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

594

timiscsts = ADF_CSR_RD(csr, ADF_GEN6_TIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

60

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

602

static void adf_handle_ricppintsts(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

610

ricppintsts = ADF_CSR_RD(csr, ADF_GEN6_RICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

615

ADF_CSR_WR(csr, ADF_GEN6_RICPPINTSTS, ricppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

619

static void adf_handle_ticppintsts(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

62

ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

627

ticppintsts = ADF_CSR_RD(csr, ADF_GEN6_TICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

632

ADF_CSR_WR(csr, ADF_GEN6_TICPPINTSTS, ticppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

636

static void adf_handle_atufaultstatus(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

64

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

647

atufaultstatus = ADF_CSR_RD(csr, ADF_GEN6_ATUFAULTSTATUS(i));

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

654

ADF_CSR_WR(csr, ADF_GEN6_ATUFAULTSTATUS(i), atufaultstatus);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

659

static void adf_handle_rlterror(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

66

ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

667

rlterror = ADF_CSR_RD(csr, ADF_GEN6_RLT_ERRLOG);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

672

ADF_CSR_WR(csr, ADF_GEN6_RLT_ERRLOG, rlterror);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

676

static void adf_handle_vflr(struct adf_accel_dev *accel_dev, void __iomem *csr, u32 errsou)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

68

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

685

static void adf_handle_tc_vc_map_error(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

695

static void adf_handle_pcie_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

70

ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

706

static void adf_handle_pg_req_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

717

static void adf_handle_xlt_cpl_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

72

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

727

static void adf_handle_ti_int_err_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

737

static void adf_gen6_process_errsou3(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

74

ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

740

adf_handle_timiscsts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

741

adf_handle_ricppintsts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

742

adf_handle_ticppintsts(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

743

adf_handle_atufaultstatus(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

744

adf_handle_rlterror(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

745

adf_handle_vflr(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

746

adf_handle_tc_vc_map_error(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

747

adf_handle_pcie_devhalt(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

748

adf_handle_pg_req_devhalt(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

749

adf_handle_xlt_cpl_devhalt(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

750

adf_handle_ti_int_err_devhalt(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

752

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

757

static void adf_gen6_is_reset_required(struct adf_accel_dev *accel_dev, void __iomem *csr,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

76

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

763

gensts = ADF_CSR_RD(csr, ADF_GEN6_GENSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

779

void __iomem *csr = adf_get_pmisc_base(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

78

ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

783

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

785

adf_gen6_process_errsou0(accel_dev, csr);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

789

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU1);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

791

adf_gen6_process_errsou1(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

795

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

797

adf_gen6_process_errsou2(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

801

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

803

adf_gen6_process_errsou3(accel_dev, csr, errsou);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

807

adf_gen6_is_reset_required(accel_dev, csr, reset_required);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

81

ADF_CSR_WR(csr, ADF_GEN6_RICPPINTCTL, ADF_GEN6_RICPPINTCTL_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

82

ADF_CSR_WR(csr, ADF_GEN6_TICPPINTCTL, ADF_GEN6_TICPPINTCTL_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

88

reg = ADF_CSR_RD(csr, ADF_GEN6_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

91

ADF_CSR_WR(csr, ADF_GEN6_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

95

void __iomem *csr)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

98

ADF_CSR_WR(csr, ADF_GEN6_INTMASKSSM, 0);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

105

void __iomem *csr = accel_dev->transport->banks[0].csr_addr;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

123

WRITE_CSR_ARB_WT2SAM(csr, info.arb_offset, info.wt2sam_offset, ae,

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

21

void __iomem *csr = accel_dev->transport->banks[0].csr_addr;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

36

WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

42

WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

79

void __iomem *csr;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

89

csr = accel_dev->transport->banks[0].csr_addr;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

95

WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, 0);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

99

csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

163

void __iomem *csr = bank->csr_addr;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

169

head = csr_ops->read_csr_ring_head(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

171

tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

173

empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

53

void __iomem *csr = ring->bank->csr_addr;

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

58

head = csr_ops->read_csr_ring_head(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

60

tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number,

drivers/crypto/intel/qat/qat_common/adf_transport_debug.c

62

empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

125

#define SET_CAP_CSR(handle, csr, val) \

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

126

ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

127

#define GET_CAP_CSR(handle, csr) \

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

128

ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

131

#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

132

#define SET_AE_CSR(handle, ae, csr, val) \

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

133

ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

134

#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

102

QAT_FIELD_SET(val32, csr.lazy,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

105

QAT_FIELD_SET(val32, csr.nice,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

121

ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_20_config_csr_lower csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

125

QAT_FIELD_SET(val32, csr.hbs,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

128

QAT_FIELD_SET(val32, csr.lbms,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

131

QAT_FIELD_SET(val32, csr.algo,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

134

QAT_FIELD_SET(val32, csr.mmctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

137

QAT_FIELD_SET(val32, csr.lbc,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

150

ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_20_config_csr_upper csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

154

QAT_FIELD_SET(val32, csr.sdc,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

157

QAT_FIELD_SET(val32, csr.mcc,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

23

ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

27

QAT_FIELD_SET(val32, csr.algo,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

30

QAT_FIELD_SET(val32, csr.sd,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

33

QAT_FIELD_SET(val32, csr.edmm,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

36

QAT_FIELD_SET(val32, csr.hbs,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

39

QAT_FIELD_SET(val32, csr.lllbd,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

42

QAT_FIELD_SET(val32, csr.mmctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

45

QAT_FIELD_SET(val32, csr.hash_col,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

48

QAT_FIELD_SET(val32, csr.hash_update,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

51

QAT_FIELD_SET(val32, csr.skip_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

54

QAT_FIELD_SET(val32, csr.abd, ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

74

ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

78

QAT_FIELD_SET(val32, csr.scb_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

81

QAT_FIELD_SET(val32, csr.rmb_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

84

QAT_FIELD_SET(val32, csr.som_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

87

QAT_FIELD_SET(val32, csr.skip_hash_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

90

QAT_FIELD_SET(val32, csr.scb_unload_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

93

QAT_FIELD_SET(val32, csr.disable_token_fusion_ctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

96

QAT_FIELD_SET(val32, csr.lbms,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

99

QAT_FIELD_SET(val32, csr.scb_mode_reset,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

20

ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_51_config_csr_lower csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

24

QAT_FIELD_SET(val32, csr.abd,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

27

QAT_FIELD_SET(val32, csr.lllbd,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

30

QAT_FIELD_SET(val32, csr.sd,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

33

QAT_FIELD_SET(val32, csr.mmctrl,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

36

QAT_FIELD_SET(val32, csr.lbc,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

50

ICP_QAT_FW_COMP_51_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_51_config_csr_upper csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

54

QAT_FIELD_SET(val32, csr.edmm,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

57

QAT_FIELD_SET(val32, csr.bms,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

60

QAT_FIELD_SET(val32, csr.scb_mode_reset,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

72

ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_51_config_csr_lower csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

76

QAT_FIELD_SET(val32, csr.lbc,

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

88

ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_51_config_csr_upper csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h

92

QAT_FIELD_SET(val32, csr.bms,

drivers/crypto/intel/qat/qat_common/qat_hal.c

125

unsigned int csr = (1 << ACS_ABO_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

133

csr = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

143

if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS)))

drivers/crypto/intel/qat/qat_common/qat_hal.c

159

unsigned int csr, new_csr;

drivers/crypto/intel/qat/qat_common/qat_hal.c

167

csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);

drivers/crypto/intel/qat/qat_common/qat_hal.c

168

csr = IGNORE_W1C_MASK & csr;

drivers/crypto/intel/qat/qat_common/qat_hal.c

170

SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

171

CLR_BIT(csr, CE_INUSE_CONTEXTS_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

179

unsigned int csr, new_csr;

drivers/crypto/intel/qat/qat_common/qat_hal.c

181

csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);

drivers/crypto/intel/qat/qat_common/qat_hal.c

182

csr &= IGNORE_W1C_MASK;

drivers/crypto/intel/qat/qat_common/qat_hal.c

185

SET_BIT(csr, CE_NN_MODE_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

186

CLR_BIT(csr, CE_NN_MODE_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

188

if (new_csr != csr)

drivers/crypto/intel/qat/qat_common/qat_hal.c

198

unsigned int csr, new_csr;

drivers/crypto/intel/qat/qat_common/qat_hal.c

200

csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);

drivers/crypto/intel/qat/qat_common/qat_hal.c

201

csr &= IGNORE_W1C_MASK;

drivers/crypto/intel/qat/qat_common/qat_hal.c

205

SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

206

CLR_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

210

SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

211

CLR_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

215

SET_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

216

CLR_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

220

SET_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

221

CLR_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

228

if (new_csr != csr)

drivers/crypto/intel/qat/qat_common/qat_hal.c

236

unsigned int csr, new_csr;

drivers/crypto/intel/qat/qat_common/qat_hal.c

238

csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);

drivers/crypto/intel/qat/qat_common/qat_hal.c

239

csr &= IGNORE_W1C_MASK;

drivers/crypto/intel/qat/qat_common/qat_hal.c

241

SET_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS) :

drivers/crypto/intel/qat/qat_common/qat_hal.c

242

CLR_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS);

drivers/crypto/intel/qat/qat_common/qat_hal.c

243

if (new_csr != csr)

drivers/crypto/intel/qat/qat_common/qat_hal.c

77

unsigned char ae, unsigned int csr)

drivers/crypto/intel/qat/qat_common/qat_hal.c

83

value = GET_AE_CSR(handle, ae, csr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

93

unsigned char ae, unsigned int csr,

drivers/crypto/intel/qat/qat_common/qat_hal.c

99

SET_AE_CSR(handle, ae, csr, value);

drivers/crypto/starfive/jh7110-aes.c

231

rctx->csr.aes.v = 0;

drivers/crypto/starfive/jh7110-aes.c

232

rctx->csr.aes.aesrst = 1;

drivers/crypto/starfive/jh7110-aes.c

233

writel(rctx->csr.aes.v, cryp->base + STARFIVE_AES_CSR);

drivers/crypto/starfive/jh7110-aes.c

238

rctx->csr.aes.v = 0;

drivers/crypto/starfive/jh7110-aes.c

242

rctx->csr.aes.keymode = STARFIVE_AES_KEYMODE_128;

drivers/crypto/starfive/jh7110-aes.c

245

rctx->csr.aes.keymode = STARFIVE_AES_KEYMODE_192;

drivers/crypto/starfive/jh7110-aes.c

248

rctx->csr.aes.keymode = STARFIVE_AES_KEYMODE_256;

drivers/crypto/starfive/jh7110-aes.c

252

rctx->csr.aes.mode = hw_mode;

drivers/crypto/starfive/jh7110-aes.c

253

rctx->csr.aes.cmode = !is_encrypt(cryp);

drivers/crypto/starfive/jh7110-aes.c

254

rctx->csr.aes.stmode = STARFIVE_AES_MODE_XFB_1;

drivers/crypto/starfive/jh7110-aes.c

257

rctx->csr.aes.delay_aes = 1;

drivers/crypto/starfive/jh7110-aes.c

258

rctx->csr.aes.vaes_start = 1;

drivers/crypto/starfive/jh7110-aes.c

261

writel(rctx->csr.aes.v, cryp->base + STARFIVE_AES_CSR);

drivers/crypto/starfive/jh7110-cryp.h

215

} csr;

drivers/crypto/starfive/jh7110-hash.c

100

csr.final = 1;

drivers/crypto/starfive/jh7110-hash.c

101

writel(csr.v, cryp->base + STARFIVE_HASH_SHACSR);

drivers/crypto/starfive/jh7110-hash.c

210

rctx->csr.hash.v = 0;

drivers/crypto/starfive/jh7110-hash.c

211

rctx->csr.hash.mode = ctx->hash_mode;

drivers/crypto/starfive/jh7110-hash.c

218

rctx->csr.hash.start = 1;

drivers/crypto/starfive/jh7110-hash.c

219

rctx->csr.hash.firstb = 1;

drivers/crypto/starfive/jh7110-hash.c

220

writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR);

drivers/crypto/starfive/jh7110-hash.c

74

rctx->csr.hash.hmac = 1;

drivers/crypto/starfive/jh7110-hash.c

75

rctx->csr.hash.key_flag = 1;

drivers/crypto/starfive/jh7110-hash.c

77

writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR);

drivers/crypto/starfive/jh7110-hash.c

96

union starfive_hash_csr csr;

drivers/crypto/starfive/jh7110-hash.c

98

csr.v = readl(cryp->base + STARFIVE_HASH_SHACSR);

drivers/crypto/starfive/jh7110-hash.c

99

csr.firstb = 0;

drivers/crypto/starfive/jh7110-rsa.c

112

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

113

rctx->csr.pka.cln_done = 1;

drivers/crypto/starfive/jh7110-rsa.c

114

rctx->csr.pka.opsize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

115

rctx->csr.pka.exposize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

116

rctx->csr.pka.cmd = CRYPTO_CMD_AERN;

drivers/crypto/starfive/jh7110-rsa.c

117

rctx->csr.pka.start = 1;

drivers/crypto/starfive/jh7110-rsa.c

118

rctx->csr.pka.ie = 1;

drivers/crypto/starfive/jh7110-rsa.c

120

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/crypto/starfive/jh7110-rsa.c

125

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

126

rctx->csr.pka.cln_done = 1;

drivers/crypto/starfive/jh7110-rsa.c

127

rctx->csr.pka.opsize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

128

rctx->csr.pka.exposize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

129

rctx->csr.pka.cmd = CRYPTO_CMD_PRE;

drivers/crypto/starfive/jh7110-rsa.c

130

rctx->csr.pka.start = 1;

drivers/crypto/starfive/jh7110-rsa.c

131

rctx->csr.pka.pre_expf = 1;

drivers/crypto/starfive/jh7110-rsa.c

132

rctx->csr.pka.ie = 1;

drivers/crypto/starfive/jh7110-rsa.c

134

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/crypto/starfive/jh7110-rsa.c

146

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

147

rctx->csr.pka.cln_done = 1;

drivers/crypto/starfive/jh7110-rsa.c

148

rctx->csr.pka.opsize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

149

rctx->csr.pka.exposize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

150

rctx->csr.pka.cmd = CRYPTO_CMD_ARN;

drivers/crypto/starfive/jh7110-rsa.c

151

rctx->csr.pka.start = 1;

drivers/crypto/starfive/jh7110-rsa.c

152

rctx->csr.pka.ie = 1;

drivers/crypto/starfive/jh7110-rsa.c

154

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/crypto/starfive/jh7110-rsa.c

199

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

200

rctx->csr.pka.cln_done = 1;

drivers/crypto/starfive/jh7110-rsa.c

201

rctx->csr.pka.opsize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

202

rctx->csr.pka.exposize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

203

rctx->csr.pka.cmd = CRYPTO_CMD_AARN;

drivers/crypto/starfive/jh7110-rsa.c

204

rctx->csr.pka.start = 1;

drivers/crypto/starfive/jh7110-rsa.c

205

rctx->csr.pka.ie = 1;

drivers/crypto/starfive/jh7110-rsa.c

207

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/crypto/starfive/jh7110-rsa.c

214

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

215

rctx->csr.pka.cln_done = 1;

drivers/crypto/starfive/jh7110-rsa.c

216

rctx->csr.pka.opsize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

217

rctx->csr.pka.exposize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

218

rctx->csr.pka.cmd = CRYPTO_CMD_AERN;

drivers/crypto/starfive/jh7110-rsa.c

219

rctx->csr.pka.start = 1;

drivers/crypto/starfive/jh7110-rsa.c

220

rctx->csr.pka.ie = 1;

drivers/crypto/starfive/jh7110-rsa.c

222

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/crypto/starfive/jh7110-rsa.c

82

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

84

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/crypto/starfive/jh7110-rsa.c

90

rctx->csr.pka.v = 0;

drivers/crypto/starfive/jh7110-rsa.c

91

rctx->csr.pka.cln_done = 1;

drivers/crypto/starfive/jh7110-rsa.c

92

rctx->csr.pka.opsize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

93

rctx->csr.pka.exposize = opsize;

drivers/crypto/starfive/jh7110-rsa.c

94

rctx->csr.pka.cmd = CRYPTO_CMD_PRE;

drivers/crypto/starfive/jh7110-rsa.c

95

rctx->csr.pka.start = 1;

drivers/crypto/starfive/jh7110-rsa.c

96

rctx->csr.pka.not_r2 = 1;

drivers/crypto/starfive/jh7110-rsa.c

97

rctx->csr.pka.ie = 1;

drivers/crypto/starfive/jh7110-rsa.c

99

writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);

drivers/dma/altera-msgdma.c

192

void __iomem *csr;

drivers/dma/altera-msgdma.c

475

iowrite32(MSGDMA_CSR_STAT_MASK, mdev->csr + MSGDMA_CSR_STATUS);

drivers/dma/altera-msgdma.c

476

iowrite32(MSGDMA_CSR_CTL_RESET, mdev->csr + MSGDMA_CSR_CONTROL);

drivers/dma/altera-msgdma.c

478

ret = readl_poll_timeout(mdev->csr + MSGDMA_CSR_STATUS, val,

drivers/dma/altera-msgdma.c

485

iowrite32(MSGDMA_CSR_STAT_MASK, mdev->csr + MSGDMA_CSR_STATUS);

drivers/dma/altera-msgdma.c

489

MSGDMA_CSR_CTL_GLOBAL_INTR, mdev->csr + MSGDMA_CSR_CONTROL);

drivers/dma/altera-msgdma.c

503

while (ioread32(mdev->csr + MSGDMA_CSR_STATUS) &

drivers/dma/altera-msgdma.c

695

count = ioread32(mdev->csr + MSGDMA_CSR_RESP_FILL_LEVEL);

drivers/dma/altera-msgdma.c

736

status = ioread32(mdev->csr + MSGDMA_CSR_STATUS);

drivers/dma/altera-msgdma.c

748

iowrite32(MSGDMA_CSR_STAT_IRQ, mdev->csr + MSGDMA_CSR_STATUS);

drivers/dma/altera-msgdma.c

823

ret = request_and_map(pdev, "csr", &dma_res, &mdev->csr, false);

drivers/dma/fsl-edma-common.c

432

u16 csr = 0;

drivers/dma/fsl-edma-common.c

440

edma_write_tcdreg(fsl_chan, 0, csr);

drivers/dma/fsl-edma-common.c

457

csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr);

drivers/dma/fsl-edma-common.c

460

csr |= EDMA_TCD_CSR_START;

drivers/dma/fsl-edma-common.c

461

fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);

drivers/dma/fsl-edma-common.c

470

(csr & EDMA_TCD_CSR_E_SG)) ||

drivers/dma/fsl-edma-common.c

472

(csr & EDMA_TCD_CSR_E_LINK)))

drivers/dma/fsl-edma-common.c

476

edma_cp_tcd_to_reg(fsl_chan, tcd, csr);

drivers/dma/fsl-edma-common.c

488

u16 csr = 0;

drivers/dma/fsl-edma-common.c

543

csr |= EDMA_TCD_CSR_INT_MAJOR;

drivers/dma/fsl-edma-common.c

546

csr |= EDMA_TCD_CSR_D_REQ;

drivers/dma/fsl-edma-common.c

549

csr |= EDMA_TCD_CSR_E_SG;

drivers/dma/fsl-edma-common.c

552

csr |= EDMA_TCD_CSR_ACTIVE;

drivers/dma/fsl-edma-common.c

555

csr |= EDMA_TCD_CSR_START;

drivers/dma/fsl-edma-common.c

557

fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);

drivers/dma/fsl-edma-common.h

101

__le16 csr;

drivers/dma/fsl-edma-common.h

115

__le16 csr;

drivers/dma/fsl-edma-main.c

826

edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr);

drivers/dma/fsl-edma-main.c

954

edma_write_tcdreg(fsl_chan, 0, csr);

drivers/dma/fsl-edma-trace.h

113

__entry->csr,

drivers/dma/fsl-edma-trace.h

75

__field(u16, csr)

drivers/dma/fsl-edma-trace.h

89

__entry->csr = fsl_edma_get_tcd_to_cpu(chan, tcd, csr),

drivers/dma/mcf-edma-main.c

203

edma_write_tcdreg(mcf_chan, cpu_to_le32(0), csr);

drivers/dma/stm32/stm32-dma3.c

1016

u32 misr, csr, ccr;

drivers/dma/stm32/stm32-dma3.c

1026

csr = readl_relaxed(ddata->base + STM32_DMA3_CSR(chan->id));

drivers/dma/stm32/stm32-dma3.c

1029

if (csr & CSR_TCF && ccr & CCR_TCIE) {

drivers/dma/stm32/stm32-dma3.c

1036

if (csr & CSR_USEF && ccr & CCR_USEIE) {

drivers/dma/stm32/stm32-dma3.c

1044

if (csr & CSR_ULEF && ccr & CCR_ULEIE) {

drivers/dma/stm32/stm32-dma3.c

1051

if (csr & CSR_DTEF && ccr & CCR_DTEIE) {

drivers/dma/stm32/stm32-dma3.c

1062

csr &= (ccr | CCR_HTIE);

drivers/dma/stm32/stm32-dma3.c

1064

if (csr)

drivers/dma/stm32/stm32-dma3.c

1065

writel_relaxed(csr, ddata->base + STM32_DMA3_CFCR(chan->id));

drivers/dma/stm32/stm32-dma3.c

776

u32 csr, ccr;

drivers/dma/stm32/stm32-dma3.c

799

csr = readl_relaxed(ddata->base + STM32_DMA3_CSR(id));

drivers/dma/stm32/stm32-dma3.c

800

if (csr & CSR_ALL_F)

drivers/dma/stm32/stm32-dma3.c

801

writel_relaxed(csr, ddata->base + STM32_DMA3_CFCR(id));

drivers/dma/stm32/stm32-dma3.c

816

u32 csr, ccr = readl_relaxed(ddata->base + STM32_DMA3_CCR(chan->id)) & ~CCR_EN;

drivers/dma/stm32/stm32-dma3.c

827

ret = readl_relaxed_poll_timeout_atomic(ddata->base + STM32_DMA3_CSR(chan->id), csr,

drivers/dma/stm32/stm32-dma3.c

828

csr & CSR_SUSPF, 1, 10);

drivers/dma/stm32/stm32-dma3.c

876

u32 residue, curr_lli, csr, cdar, cbr1, cllr, bndt, fifol;

drivers/dma/stm32/stm32-dma3.c

880

csr = readl_relaxed(ddata->base + STM32_DMA3_CSR(chan->id));

drivers/dma/stm32/stm32-dma3.c

881

if (!(csr & CSR_IDLEF) && chan->dma_status != DMA_PAUSED) {

drivers/dma/stm32/stm32-dma3.c

884

ret = readl_relaxed_poll_timeout_atomic(ddata->base + STM32_DMA3_CSR(chan->id), csr,

drivers/dma/stm32/stm32-dma3.c

885

csr & (CSR_SUSPF | CSR_IDLEF), 1, 10);

drivers/dma/stm32/stm32-dma3.c

887

if (ret || ((csr & CSR_TCF) && (csr & CSR_IDLEF))) {

drivers/dma/stm32/stm32-dma3.c

891

dev_err(dev, "Channel suspension timeout, csr=%08x\n", csr);

drivers/dma/stm32/stm32-dma3.c

896

if (!(csr & CSR_IDLEF))

drivers/dma/stm32/stm32-dma3.c

897

dev_warn(dev, "Can't get residue: channel still active, csr=%08x\n", csr);

drivers/dma/stm32/stm32-dma3.c

903

if (!(csr & CSR_SUSPF) && (csr & CSR_TCF) && (csr & CSR_IDLEF))

drivers/dma/stm32/stm32-dma3.c

912

if (csr & CSR_SUSPF) {

drivers/dma/stm32/stm32-dma3.c

931

fifol = FIELD_GET(CSR_FIFOL, csr) * (1 << FIELD_GET(CTR1_DDW_LOG2, hwdesc->ctr1));

drivers/dma/tegra186-gpc-dma.c

1013

u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0;

drivers/dma/tegra186-gpc-dma.c

1034

ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,

drivers/dma/tegra186-gpc-dma.c

1040

csr |= TEGRA_GPCDMA_CSR_ONCE;

drivers/dma/tegra186-gpc-dma.c

1042

csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);

drivers/dma/tegra186-gpc-dma.c

1044

csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;

drivers/dma/tegra186-gpc-dma.c

1046

csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);

drivers/dma/tegra186-gpc-dma.c

1050

csr |= TEGRA_GPCDMA_CSR_IE_EOC;

drivers/dma/tegra186-gpc-dma.c

1115

sg_req[i].ch_regs.csr = csr;

drivers/dma/tegra186-gpc-dma.c

1131

u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size;

drivers/dma/tegra186-gpc-dma.c

1169

ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,

drivers/dma/tegra186-gpc-dma.c

1175

csr &= ~TEGRA_GPCDMA_CSR_ONCE;

drivers/dma/tegra186-gpc-dma.c

1177

csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);

drivers/dma/tegra186-gpc-dma.c

1179

csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;

drivers/dma/tegra186-gpc-dma.c

1181

csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);

drivers/dma/tegra186-gpc-dma.c

1185

csr |= TEGRA_GPCDMA_CSR_IE_EOC;

drivers/dma/tegra186-gpc-dma.c

1235

sg_req[i].ch_regs.csr = csr;

drivers/dma/tegra186-gpc-dma.c

189

u32 csr;

drivers/dma/tegra186-gpc-dma.c

457

u32 csr, status;

drivers/dma/tegra186-gpc-dma.c

459

csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);

drivers/dma/tegra186-gpc-dma.c

462

csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;

drivers/dma/tegra186-gpc-dma.c

465

csr &= ~TEGRA_GPCDMA_CSR_ENB;

drivers/dma/tegra186-gpc-dma.c

466

tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);

drivers/dma/tegra186-gpc-dma.c

507

ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);

drivers/dma/tegra186-gpc-dma.c

539

tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);

drivers/dma/tegra186-gpc-dma.c

543

ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);

drivers/dma/tegra186-gpc-dma.c

669

u32 status, csr;

drivers/dma/tegra186-gpc-dma.c

676

csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);

drivers/dma/tegra186-gpc-dma.c

677

csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);

drivers/dma/tegra186-gpc-dma.c

678

csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;

drivers/dma/tegra186-gpc-dma.c

679

tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);

drivers/dma/tegra186-gpc-dma.c

842

u32 *csr,

drivers/dma/tegra186-gpc-dma.c

852

*csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;

drivers/dma/tegra186-gpc-dma.c

859

*csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;

drivers/dma/tegra186-gpc-dma.c

876

u32 csr, mc_seq;

drivers/dma/tegra186-gpc-dma.c

885

csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;

drivers/dma/tegra186-gpc-dma.c

887

csr |= TEGRA_GPCDMA_CSR_ONCE;

drivers/dma/tegra186-gpc-dma.c

889

csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;

drivers/dma/tegra186-gpc-dma.c

892

csr |= TEGRA_GPCDMA_CSR_IE_EOC;

drivers/dma/tegra186-gpc-dma.c

894

csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);

drivers/dma/tegra186-gpc-dma.c

926

sg_req[0].ch_regs.csr = csr;

drivers/dma/tegra186-gpc-dma.c

943

u32 csr, mc_seq;

drivers/dma/tegra186-gpc-dma.c

953

csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;

drivers/dma/tegra186-gpc-dma.c

955

csr |= TEGRA_GPCDMA_CSR_ONCE;

drivers/dma/tegra186-gpc-dma.c

957

csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;

drivers/dma/tegra186-gpc-dma.c

960

csr |= TEGRA_GPCDMA_CSR_IE_EOC;

drivers/dma/tegra186-gpc-dma.c

962

csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);

drivers/dma/tegra186-gpc-dma.c

996

sg_req[0].ch_regs.csr = csr;

drivers/dma/tegra20-apb-dma.c

1003

*csr = TEGRA_APBDMA_CSR_DIR;

drivers/dma/tegra20-apb-dma.c

1011

*csr = 0;

drivers/dma/tegra20-apb-dma.c

1031

ch_regs->csr |= len_field;

drivers/dma/tegra20-apb-dma.c

1044

u32 csr, ahb_seq, apb_ptr, apb_seq;

drivers/dma/tegra20-apb-dma.c

1061

if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,

drivers/dma/tegra20-apb-dma.c

1072

csr |= TEGRA_APBDMA_CSR_ONCE;

drivers/dma/tegra20-apb-dma.c

1075

csr |= TEGRA_APBDMA_CSR_FLOW;

drivers/dma/tegra20-apb-dma.c

1076

csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;

drivers/dma/tegra20-apb-dma.c

1080

csr |= TEGRA_APBDMA_CSR_IE_EOC;

drivers/dma/tegra20-apb-dma.c

1127

sg_req->ch_regs.csr = csr;

drivers/dma/tegra20-apb-dma.c

1169

u32 csr, ahb_seq, apb_ptr, apb_seq;

drivers/dma/tegra20-apb-dma.c

1213

if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,

drivers/dma/tegra20-apb-dma.c

1223

csr |= TEGRA_APBDMA_CSR_FLOW;

drivers/dma/tegra20-apb-dma.c

1224

csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;

drivers/dma/tegra20-apb-dma.c

1228

csr |= TEGRA_APBDMA_CSR_IE_EOC;

drivers/dma/tegra20-apb-dma.c

1262

sg_req->ch_regs.csr = csr;

drivers/dma/tegra20-apb-dma.c

132

u32 csr;

drivers/dma/tegra20-apb-dma.c

407

u32 csr, status;

drivers/dma/tegra20-apb-dma.c

410

csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);

drivers/dma/tegra20-apb-dma.c

411

csr &= ~TEGRA_APBDMA_CSR_IE_EOC;

drivers/dma/tegra20-apb-dma.c

412

tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);

drivers/dma/tegra20-apb-dma.c

415

csr &= ~TEGRA_APBDMA_CSR_ENB;

drivers/dma/tegra20-apb-dma.c

416

tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);

drivers/dma/tegra20-apb-dma.c

432

tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);

drivers/dma/tegra20-apb-dma.c

442

ch_regs->csr | TEGRA_APBDMA_CSR_ENB);

drivers/dma/tegra20-apb-dma.c

482

nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);

drivers/dma/tegra20-apb-dma.c

993

u32 *csr,

drivers/dma/ti/omap-dma.c

646

unsigned mask, csr;

drivers/dma/ti/omap-dma.c

660

csr = omap_dma_get_csr(c);

drivers/dma/ti/omap-dma.c

663

omap_dma_callback(channel, csr, c);

drivers/dma/txx9dmac.c

498

static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)

drivers/dma/txx9dmac.c

516

errors = csr & (TXX9_DMA_CSR_ABCHC |

drivers/dma/txx9dmac.c

541

u32 csr;

drivers/dma/txx9dmac.c

545

csr = channel64_readl(dc, CSR);

drivers/dma/txx9dmac.c

546

channel64_writel(dc, CSR, csr);

drivers/dma/txx9dmac.c

549

csr = channel32_readl(dc, CSR);

drivers/dma/txx9dmac.c

550

channel32_writel(dc, CSR, csr);

drivers/dma/txx9dmac.c

553

if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {

drivers/dma/txx9dmac.c

558

if (!(csr & TXX9_DMA_CSR_CHNEN))

drivers/dma/txx9dmac.c

567

if (csr & TXX9_DMA_CSR_ABCHC)

drivers/dma/txx9dmac.c

575

if (csr & TXX9_DMA_CSR_ABCHC)

drivers/dma/txx9dmac.c

587

if (csr & TXX9_DMA_CSR_ABCHC) {

drivers/dma/txx9dmac.c

588

txx9dmac_handle_error(dc, csr);

drivers/dma/txx9dmac.c

607

u32 csr;

drivers/dma/txx9dmac.c

611

csr = channel_readl(dc, CSR);

drivers/dma/txx9dmac.c

612

dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);

drivers/dma/txx9dmac.c

615

if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |

drivers/dma/txx9dmac.c

644

u32 csr;

drivers/dma/txx9dmac.c

656

csr = channel_readl(dc, CSR);

drivers/dma/txx9dmac.c

658

csr);

drivers/dma/txx9dmac.c

660

if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |

drivers/edac/edac_mc.c

181

struct csrow_info *csr;

drivers/edac/edac_mc.c

192

csr = mci->csrows[row];

drivers/edac/edac_mc.c

193

if (!csr)

drivers/edac/edac_mc.c

196

if (csr->channels) {

drivers/edac/edac_mc.c

198

kfree(csr->channels[chn]);

drivers/edac/edac_mc.c

199

kfree(csr->channels);

drivers/edac/edac_mc.c

201

kfree(csr);

drivers/edac/edac_mc.c

224

struct csrow_info *csr;

drivers/edac/edac_mc.c

226

csr = kzalloc_obj(**mci->csrows);

drivers/edac/edac_mc.c

227

if (!csr)

drivers/edac/edac_mc.c

230

mci->csrows[row] = csr;

drivers/edac/edac_mc.c

231

csr->csrow_idx = row;

drivers/edac/edac_mc.c

232

csr->mci = mci;

drivers/edac/edac_mc.c

233

csr->nr_channels = tot_channels;

drivers/edac/edac_mc.c

234

csr->channels = kzalloc_objs(*csr->channels, tot_channels);

drivers/edac/edac_mc.c

235

if (!csr->channels)

drivers/edac/edac_mc.c

241

chan = kzalloc_obj(**csr->channels);

drivers/edac/edac_mc.c

245

csr->channels[chn] = chan;

drivers/edac/edac_mc.c

247

chan->csrow = csr;

drivers/firewire/ohci.c

1458

struct fw_packet *packet, u32 csr)

drivers/firewire/ohci.c

1469

i = csr - CSR_CONFIG_ROM;

drivers/firewire/ohci.c

1487

struct fw_packet *packet, u32 csr)

drivers/firewire/ohci.c

1512

sel = (csr - CSR_BUS_MANAGER_ID) / 4;

drivers/firewire/ohci.c

1539

u64 offset, csr;

drivers/firewire/ohci.c

1547

csr = offset - CSR_REGISTER_BASE;

drivers/firewire/ohci.c

1550

if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)

drivers/firewire/ohci.c

1551

handle_local_rom(ohci, packet, csr);

drivers/firewire/ohci.c

1552

else switch (csr) {

drivers/firewire/ohci.c

1557

handle_local_lock(ohci, packet, csr);

drivers/hid/intel-ish-hid/ipc/ipc.c

767

uint16_t csr;

drivers/hid/intel-ish-hid/ipc/ipc.c

788

pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &csr);

drivers/hid/intel-ish-hid/ipc/ipc.c

790

csr &= ~PCI_PM_CTRL_STATE_MASK;

drivers/hid/intel-ish-hid/ipc/ipc.c

791

csr |= PCI_D3hot;

drivers/hid/intel-ish-hid/ipc/ipc.c

792

pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);

drivers/hid/intel-ish-hid/ipc/ipc.c

796

csr &= ~PCI_PM_CTRL_STATE_MASK;

drivers/hid/intel-ish-hid/ipc/ipc.c

797

csr |= PCI_D0;

drivers/hid/intel-ish-hid/ipc/ipc.c

798

pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);

drivers/hsi/controllers/omap_ssi_core.c

167

u32 csr;

drivers/hsi/controllers/omap_ssi_core.c

186

csr = readw(omap_ssi->gdd + SSI_GDD_CSR_REG(lch));

drivers/hsi/controllers/omap_ssi_core.c

191

if (csr & SSI_CSR_TOUR) { /* Timeout error */

drivers/iio/adc/stm32-adc-core.c

311

.csr = STM32F4_ADC_CSR,

drivers/iio/adc/stm32-adc-core.c

321

.csr = STM32H7_ADC_CSR,

drivers/iio/adc/stm32-adc-core.c

331

.csr = STM32H7_ADC_CSR,

drivers/iio/adc/stm32-adc-core.c

362

status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);

drivers/iio/adc/stm32-adc-core.c

55

u32 csr;

drivers/iio/proximity/rfd77402.c

266

static int rfd77402_config_irq(struct i2c_client *client, u8 csr, u8 ier)

drivers/iio/proximity/rfd77402.c

270

ret = i2c_smbus_write_byte_data(client, RFD77402_ICSR, csr);

drivers/infiniband/hw/hfi1/chip.c

11174

static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,

drivers/infiniband/hw/hfi1/chip.c

11177

u64 reg = read_csr(dd, csr);

drivers/infiniband/hw/hfi1/chip.c

1163

u64 csr;

drivers/infiniband/hw/hfi1/chip.c

1185

#define CNTR_ELEM(name, csr, offset, flags, accessor) \

drivers/infiniband/hw/hfi1/chip.c

1188

csr, \

drivers/infiniband/hw/hfi1/chip.c

1350

static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,

drivers/infiniband/hw/hfi1/chip.c

1356

ret = read_csr(dd, csr);

drivers/infiniband/hw/hfi1/chip.c

1358

write_csr(dd, csr, value);

drivers/infiniband/hw/hfi1/chip.c

1365

hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);

drivers/infiniband/hw/hfi1/chip.c

1374

u64 csr = entry->csr;

drivers/infiniband/hw/hfi1/chip.c

1379

csr += 0x100 * vl;

drivers/infiniband/hw/hfi1/chip.c

1384

return read_write_csr(dd, csr, mode, data);

drivers/infiniband/hw/hfi1/chip.c

1434

u64 csr = entry->csr;

drivers/infiniband/hw/hfi1/chip.c

1439

csr += 8 * vl;

drivers/infiniband/hw/hfi1/chip.c

1445

val = read_write_csr(dd, csr, mode, data);

drivers/infiniband/hw/hfi1/chip.c

1453

u32 csr = entry->csr;

drivers/infiniband/hw/hfi1/chip.c

1459

ret = read_lcb_csr(dd, csr, &data);

drivers/infiniband/hw/hfi1/chip.c

1461

ret = write_lcb_csr(dd, csr, data);

drivers/infiniband/hw/hfi1/chip.c

1465

dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);

drivers/infiniband/hw/hfi1/chip.c

1469

hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);

drivers/infiniband/hw/hfi1/chip.c

1481

return read_write_csr(ppd->dd, entry->csr, mode, data);

drivers/infiniband/hw/hfi1/chip.c

1489

u64 csr = entry->csr;

drivers/infiniband/hw/hfi1/chip.c

1494

csr += 8 * vl;

drivers/infiniband/hw/hfi1/chip.c

1499

val = read_write_csr(ppd->dd, csr, mode, data);

drivers/infiniband/hw/hfi1/chip.c

4036

u64 csr = entry->csr;

drivers/infiniband/hw/hfi1/chip.c

4038

val = read_write_csr(dd, csr, mode, data);

drivers/infiniband/hw/hfi1/sdma.c

2027

csr = read_csr(sde->dd, reg); \

drivers/infiniband/hw/hfi1/sdma.c

2028

dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \

drivers/infiniband/hw/hfi1/sdma.c

2032

csr = read_sde_csr(sde, reg); \

drivers/infiniband/hw/hfi1/sdma.c

2034

#reg, sde->this_idx, csr); \

drivers/infiniband/hw/hfi1/sdma.c

2038

csr = read_csr(sde->dd, reg + (8 * i)); \

drivers/infiniband/hw/hfi1/sdma.c

2040

#reg, i, csr); \

drivers/infiniband/hw/hfi1/sdma.c

2045

u64 csr;

drivers/iommu/riscv/iommu.c

225

u32 csr;

drivers/iommu/riscv/iommu.c

262

csr, !(csr & RISCV_IOMMU_QUEUE_BUSY),

drivers/iommu/riscv/iommu.c

265

if (RISCV_IOMMU_QUEUE_ACTIVE != (csr & (RISCV_IOMMU_QUEUE_ACTIVE |

drivers/iommu/riscv/iommu.c

289

u32 csr;

drivers/iommu/riscv/iommu.c

297

csr, !(csr & RISCV_IOMMU_QUEUE_BUSY),

drivers/iommu/riscv/iommu.c

300

if (csr & (RISCV_IOMMU_QUEUE_ACTIVE | RISCV_IOMMU_QUEUE_BUSY))

drivers/iommu/riscv/iommu.c

302

queue->qid, csr);

drivers/ipack/devices/ipoctal.c

342

iowrite8(TX_CLK_9600 | RX_CLK_9600, &channel->regs->w.csr);

drivers/ipack/devices/ipoctal.c

502

unsigned char csr = 0;

drivers/ipack/devices/ipoctal.c

574

csr |= TX_CLK_75 | RX_CLK_75;

drivers/ipack/devices/ipoctal.c

577

csr |= TX_CLK_110 | RX_CLK_110;

drivers/ipack/devices/ipoctal.c

580

csr |= TX_CLK_150 | RX_CLK_150;

drivers/ipack/devices/ipoctal.c

583

csr |= TX_CLK_300 | RX_CLK_300;

drivers/ipack/devices/ipoctal.c

586

csr |= TX_CLK_600 | RX_CLK_600;

drivers/ipack/devices/ipoctal.c

589

csr |= TX_CLK_1200 | RX_CLK_1200;

drivers/ipack/devices/ipoctal.c

592

csr |= TX_CLK_1800 | RX_CLK_1800;

drivers/ipack/devices/ipoctal.c

595

csr |= TX_CLK_2000 | RX_CLK_2000;

drivers/ipack/devices/ipoctal.c

598

csr |= TX_CLK_2400 | RX_CLK_2400;

drivers/ipack/devices/ipoctal.c

601

csr |= TX_CLK_4800 | RX_CLK_4800;

drivers/ipack/devices/ipoctal.c

604

csr |= TX_CLK_9600 | RX_CLK_9600;

drivers/ipack/devices/ipoctal.c

607

csr |= TX_CLK_19200 | RX_CLK_19200;

drivers/ipack/devices/ipoctal.c

611

csr |= TX_CLK_38400 | RX_CLK_38400;

drivers/ipack/devices/ipoctal.c

623

iowrite8(csr, &channel->regs->w.csr);

drivers/ipack/devices/scc2698.h

31

u8 d1, csr; /* Clock select register */

drivers/media/cec/i2c/tda9950.c

142

u8 csr, cconr, buf[19];

drivers/media/cec/i2c/tda9950.c

148

csr = tda9950_read(priv->client, REG_CSR);

drivers/media/cec/i2c/tda9950.c

149

if (!(csr & CSR_INT))

drivers/media/cec/i2c/tda9950.c

303

u8 csr;

drivers/media/cec/i2c/tda9950.c

310

csr = tda9950_read(client, REG_CSR);

drivers/media/cec/i2c/tda9950.c

311

if (!(csr & CSR_BUSY) || !--timeout)

drivers/media/cec/i2c/tda9950.c

317

if (csr & CSR_BUSY)

drivers/media/cec/i2c/tda9950.c

319

client->irq, csr);

drivers/misc/eeprom/idt_89hpesx.c

1148

pdev->csr = CSR_DEF;

drivers/misc/eeprom/idt_89hpesx.c

93

u16 csr;

drivers/misc/eeprom/idt_89hpesx.c

950

pdev->csr = (csraddr >> 2);

drivers/misc/eeprom/idt_89hpesx.c

958

ret = idt_csr_write(pdev, pdev->csr, csrval);

drivers/misc/eeprom/idt_89hpesx.c

994

ret = idt_csr_read(pdev, pdev->csr, &csrval);

drivers/misc/eeprom/idt_89hpesx.c

999

csraddr = ((u32)pdev->csr << 2);

drivers/mmc/host/wbsd.c

1003

csr = inb(host->base + WBSD_CSR);

drivers/mmc/host/wbsd.c

1004

WARN_ON(csr == 0xff);

drivers/mmc/host/wbsd.c

1006

if (csr & WBSD_CARDPRESENT) {

drivers/mmc/host/wbsd.c

913

u8 csr;

drivers/mmc/host/wbsd.c

917

csr = inb(host->base + WBSD_CSR);

drivers/mmc/host/wbsd.c

918

csr |= WBSD_MSLED;

drivers/mmc/host/wbsd.c

919

outb(csr, host->base + WBSD_CSR);

drivers/mmc/host/wbsd.c

923

csr = inb(host->base + WBSD_CSR);

drivers/mmc/host/wbsd.c

924

csr &= ~WBSD_MSLED;

drivers/mmc/host/wbsd.c

925

outb(csr, host->base + WBSD_CSR);

drivers/mmc/host/wbsd.c

929

return !!(csr & WBSD_WRPT);

drivers/mmc/host/wbsd.c

993

u8 csr;

drivers/mtd/devices/ms02-nv.c

188

mp->resource.csr = csr_res;

drivers/mtd/devices/ms02-nv.c

255

release_resource(mp->resource.csr);

drivers/mtd/devices/ms02-nv.c

256

kfree(mp->resource.csr);

drivers/mtd/devices/ms02-nv.c

270

volatile u32 *csr;

drivers/mtd/devices/ms02-nv.c

277

csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);

drivers/mtd/devices/ms02-nv.c

278

if (*csr & KN02_CSR_BNK32M)

drivers/mtd/devices/ms02-nv.c

283

csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);

drivers/mtd/devices/ms02-nv.c

284

if (*csr & KN03_MCR_BNK32M)

drivers/mtd/devices/ms02-nv.h

96

struct resource *csr;

drivers/net/can/esd/esd_402_pci-core.c

115

u16 csr = 0;

drivers/net/can/esd/esd_402_pci-core.c

121

err = pci_read_config_word(pdev, PCI402_PCICFG_MSICAP + PCI_MSI_FLAGS, &csr);

drivers/net/can/esd/esd_402_pci-core.c

145

if (!(csr & PCI_MSI_FLAGS_ENABLE)) {

drivers/net/can/esd/esd_402_pci-core.c

160

csr, addr_hi, addr_lo, addr_lo_offs, data);

drivers/net/ethernet/agere/et131x.c

1721

&adapter->regs->txdma.csr);

drivers/net/ethernet/agere/et131x.c

2927

regs_buff[num++] = readl(&aregs->txdma.csr);

drivers/net/ethernet/agere/et131x.c

2955

regs_buff[num++] = readl(&aregs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

739

u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;

drivers/net/ethernet/agere/et131x.c

743

csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;

drivers/net/ethernet/agere/et131x.c

745

csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;

drivers/net/ethernet/agere/et131x.c

747

csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;

drivers/net/ethernet/agere/et131x.c

749

csr |= ET_RXDMA_CSR_FBR0_ENABLE;

drivers/net/ethernet/agere/et131x.c

751

csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;

drivers/net/ethernet/agere/et131x.c

753

csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;

drivers/net/ethernet/agere/et131x.c

755

csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;

drivers/net/ethernet/agere/et131x.c

756

writel(csr, &adapter->regs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

758

csr = readl(&adapter->regs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

759

if (csr & ET_RXDMA_CSR_HALT_STATUS) {

drivers/net/ethernet/agere/et131x.c

761

csr = readl(&adapter->regs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

762

if (csr & ET_RXDMA_CSR_HALT_STATUS) {

drivers/net/ethernet/agere/et131x.c

765

csr);

drivers/net/ethernet/agere/et131x.c

772

u32 csr;

drivers/net/ethernet/agere/et131x.c

775

&adapter->regs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

776

csr = readl(&adapter->regs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

777

if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {

drivers/net/ethernet/agere/et131x.c

779

csr = readl(&adapter->regs->rxdma.csr);

drivers/net/ethernet/agere/et131x.c

780

if (!(csr & ET_RXDMA_CSR_HALT_STATUS))

drivers/net/ethernet/agere/et131x.c

783

csr);

drivers/net/ethernet/agere/et131x.c

793

&adapter->regs->txdma.csr);

drivers/net/ethernet/agere/et131x.h

240

u32 csr; /* 0x1000 */

drivers/net/ethernet/agere/et131x.h

462

u32 csr; /* 0x2000 */

drivers/net/ethernet/amd/sunlance.c

1385

u32 csr;

drivers/net/ethernet/amd/sunlance.c

1434

csr = sbus_readl(lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

1435

sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

1437

sbus_writel(csr & ~DMA_RST_ENET, lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

436

u32 csr = sbus_readl(lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

438

if (!(csr & DMA_HNDL_ERROR)) {

drivers/net/ethernet/amd/sunlance.c

444

csr = sbus_readl(lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

445

csr &= ~DMA_E_BURSTS;

drivers/net/ethernet/amd/sunlance.c

447

csr |= DMA_E_BURST32;

drivers/net/ethernet/amd/sunlance.c

449

csr |= DMA_E_BURST16;

drivers/net/ethernet/amd/sunlance.c

451

csr |= (DMA_DSBL_RD_DRN | DMA_DSBL_WR_INV | DMA_FIFO_INV);

drivers/net/ethernet/amd/sunlance.c

454

csr |= DMA_EN_ENETAUI;

drivers/net/ethernet/amd/sunlance.c

456

csr &= ~DMA_EN_ENETAUI;

drivers/net/ethernet/amd/sunlance.c

458

sbus_writel(csr, lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

494

u32 csr = sbus_readl(lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

496

csr |= DMA_INT_ENAB;

drivers/net/ethernet/amd/sunlance.c

497

sbus_writel(csr, lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

983

u32 csr, addr;

drivers/net/ethernet/amd/sunlance.c

986

csr = sbus_readl(lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

987

sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR);

drivers/net/ethernet/amd/sunlance.c

989

sbus_writel(csr & ~DMA_RST_ENET, lp->dregs + DMA_CSR);

drivers/net/ethernet/emulex/benet/be.h

554

u8 __iomem *csr; /* CSR BAR used only for BE2/3 */

drivers/net/ethernet/emulex/benet/be_cmds.c

716

sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);

drivers/net/ethernet/emulex/benet/be_main.c

5534

if (adapter->csr)

drivers/net/ethernet/emulex/benet/be_main.c

5535

pci_iounmap(adapter->pdev, adapter->csr);

drivers/net/ethernet/emulex/benet/be_main.c

5574

adapter->csr = pci_iomap(pdev, 2, 0);

drivers/net/ethernet/emulex/benet/be_main.c

5575

if (!adapter->csr)

drivers/net/ethernet/intel/e100.c

1365

iowrite8(~0, &nic->csr->scb.stat_ack);

drivers/net/ethernet/intel/e100.c

1713

iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);

drivers/net/ethernet/intel/e100.c

1979

if (ioread8(&nic->csr->scb.status) & rus_no_res)

drivers/net/ethernet/intel/e100.c

2007

if (ioread8(&nic->csr->scb.status) & rus_no_res)

drivers/net/ethernet/intel/e100.c

2120

iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);

drivers/net/ethernet/intel/e100.c

2194

u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);

drivers/net/ethernet/intel/e100.c

2204

iowrite8(stat_ack, &nic->csr->scb.stat_ack);

drivers/net/ethernet/intel/e100.c

2332

"scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));

drivers/net/ethernet/intel/e100.c

2454

buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |

drivers/net/ethernet/intel/e100.c

2455

ioread8(&nic->csr->scb.cmd_lo) << 16 |

drivers/net/ethernet/intel/e100.c

2456

ioread16(&nic->csr->scb.status);

drivers/net/ethernet/intel/e100.c

2879

nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));

drivers/net/ethernet/intel/e100.c

2880

if (!nic->csr) {

drivers/net/ethernet/intel/e100.c

2971

pci_iounmap(pdev, nic->csr);

drivers/net/ethernet/intel/e100.c

2989

pci_iounmap(pdev, nic->csr);

drivers/net/ethernet/intel/e100.c

551

struct csr __iomem *csr;

drivers/net/ethernet/intel/e100.c

609

(void)ioread8(&nic->csr->scb.status);

drivers/net/ethernet/intel/e100.c

617

iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);

drivers/net/ethernet/intel/e100.c

627

iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);

drivers/net/ethernet/intel/e100.c

636

iowrite32(selective_reset, &nic->csr->port);

drivers/net/ethernet/intel/e100.c

640

iowrite32(software_reset, &nic->csr->port);

drivers/net/ethernet/intel/e100.c

657

iowrite32(selftest | dma_addr, &nic->csr->port);

drivers/net/ethernet/intel/e100.c

696

iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

702

iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

705

iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

712

iowrite8(0, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

728

iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

734

iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

737

iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

742

ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

752

iowrite8(0, &nic->csr->eeprom_ctrl_lo);

drivers/net/ethernet/intel/e100.c

822

if (likely(!ioread8(&nic->csr->scb.cmd_lo)))

drivers/net/ethernet/intel/e100.c

834

iowrite32(dma_addr, &nic->csr->scb.gen_ptr);

drivers/net/ethernet/intel/e100.c

835

iowrite8(cmd, &nic->csr->scb.cmd_lo);

drivers/net/ethernet/intel/e100.c

930

if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)

drivers/net/ethernet/intel/e100.c

939

iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);

drivers/net/ethernet/intel/e100.c

943

if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)

drivers/net/ethernet/meta/fbnic/fbnic.h

121

u32 __iomem *csr = READ_ONCE(fbd->uc_addr0);

drivers/net/ethernet/meta/fbnic/fbnic.h

123

if (csr)

drivers/net/ethernet/meta/fbnic/fbnic.h

124

writel(val, csr + reg);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

39

u32 __iomem *csr = READ_ONCE(fbd->uc_addr0);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

42

if (!csr)

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

45

value = readl(csr + reg);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

52

if (reg != FBNIC_MASTER_SPARE_0 && ~readl(csr + FBNIC_MASTER_SPARE_0))

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

77

u32 __iomem *csr = READ_ONCE(fbd->uc_addr4);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

79

if (csr)

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

80

writel(val, csr + reg);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

85

u32 __iomem *csr = READ_ONCE(fbd->uc_addr4);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

88

if (!csr)

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

91

value = readl(csr + reg);

drivers/net/ethernet/meta/fbnic/fbnic_pci.c

98

if (reg != FBNIC_FW_ZERO_REG && ~readl(csr + FBNIC_FW_ZERO_REG))

drivers/net/ethernet/meta/fbnic/fbnic_txrx.c

51

static u32 fbnic_ring_rd32(struct fbnic_ring *ring, unsigned int csr)

drivers/net/ethernet/meta/fbnic/fbnic_txrx.c

55

return readl(csr_base + csr);

drivers/net/ethernet/meta/fbnic/fbnic_txrx.c

58

static void fbnic_ring_wr32(struct fbnic_ring *ring, unsigned int csr, u32 val)

drivers/net/ethernet/meta/fbnic/fbnic_txrx.c

62

writel(val, csr_base + csr);

drivers/net/ethernet/microchip/lan743x_main.c

127

return ioread32(&adapter->csr.csr_address[offset]);

drivers/net/ethernet/microchip/lan743x_main.c

133

iowrite32(data, &adapter->csr.csr_address[offset]);

drivers/net/ethernet/microchip/lan743x_main.c

1355

id_rev = adapter->csr.id_rev & ID_REV_ID_MASK_;

drivers/net/ethernet/microchip/lan743x_main.c

1491

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))

drivers/net/ethernet/microchip/lan743x_main.c

176

struct lan743x_csr *csr = &adapter->csr;

drivers/net/ethernet/microchip/lan743x_main.c

181

csr->csr_address = devm_ioremap(&adapter->pdev->dev,

drivers/net/ethernet/microchip/lan743x_main.c

183

if (!csr->csr_address)

drivers/net/ethernet/microchip/lan743x_main.c

186

csr->id_rev = lan743x_csr_read(adapter, ID_REV);

drivers/net/ethernet/microchip/lan743x_main.c

187

csr->fpga_rev = lan743x_csr_read(adapter, FPGA_REV);

drivers/net/ethernet/microchip/lan743x_main.c

190

csr->id_rev, FPGA_REV_GET_MAJOR_(csr->fpga_rev),

drivers/net/ethernet/microchip/lan743x_main.c

191

FPGA_REV_GET_MINOR_(csr->fpga_rev));

drivers/net/ethernet/microchip/lan743x_main.c

192

if (!ID_REV_IS_VALID_CHIP_ID_(csr->id_rev))

drivers/net/ethernet/microchip/lan743x_main.c

195

csr->flags = LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR;

drivers/net/ethernet/microchip/lan743x_main.c

196

switch (csr->id_rev & ID_REV_CHIP_REV_MASK_) {

drivers/net/ethernet/microchip/lan743x_main.c

198

csr->flags |= LAN743X_CSR_FLAG_IS_A0;

drivers/net/ethernet/microchip/lan743x_main.c

199

csr->flags &= ~LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR;

drivers/net/ethernet/microchip/lan743x_main.c

202

csr->flags |= LAN743X_CSR_FLAG_IS_B0;

drivers/net/ethernet/microchip/lan743x_main.c

2244

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))

drivers/net/ethernet/microchip/lan743x_main.c

2250

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {

drivers/net/ethernet/microchip/lan743x_main.c

2787

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {

drivers/net/ethernet/microchip/lan743x_main.c

2807

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))

drivers/net/ethernet/microchip/lan743x_main.c

3191

} else if (((adapter->csr.id_rev & ID_REV_ID_MASK_) ==

drivers/net/ethernet/microchip/lan743x_main.c

3480

u16 rev = adapter->csr.id_rev & ID_REV_CHIP_REV_MASK_;

drivers/net/ethernet/microchip/lan743x_main.c

3606

if ((adapter->csr.id_rev & ID_REV_ID_MASK_) == ID_REV_ID_LAN7430_)

drivers/net/ethernet/microchip/lan743x_main.c

556

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {

drivers/net/ethernet/microchip/lan743x_main.c

600

if (adapter->csr.flags & LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {

drivers/net/ethernet/microchip/lan743x_main.c

623

if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {

drivers/net/ethernet/microchip/lan743x_main.c

662

if (adapter->csr.flags &

drivers/net/ethernet/microchip/lan743x_main.c

706

if (adapter->csr.flags &

drivers/net/ethernet/microchip/lan743x_main.c

75

struct lan743x_csr *csr = &adapter->csr;

drivers/net/ethernet/microchip/lan743x_main.c

76

u32 id_rev = csr->id_rev;

drivers/net/ethernet/microchip/lan743x_main.h

1060

struct lan743x_csr csr;

drivers/net/ethernet/microchip/lan743x_ptp.c

1498

switch (adapter->csr.id_rev & ID_REV_ID_MASK_) {

drivers/net/ethernet/microchip/lan743x_ptp.c

1510

adapter->csr.id_rev);

drivers/net/ethernet/microchip/lan743x_ptp.c

220

u32 id_rev = adapter->csr.id_rev & ID_REV_ID_MASK_;

drivers/net/ethernet/microchip/lan743x_ptp.c

239

u32 id_rev = adapter->csr.id_rev & ID_REV_ID_MASK_;

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1130

u32 csr[3];

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1155

csr[0] = NFP_PCIE_BAR_EXPLICIT_BAR0_SignalType(sigmask) |

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1160

csr[1] = NFP_PCIE_BAR_EXPLICIT_BAR1_SignalRef(signal_ref) |

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1164

csr[2] = NFP_PCIE_BAR_EXPLICIT_BAR2_Target(

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1172

if (nfp->iomem.csr) {

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1173

writel(csr[0], nfp->iomem.csr +

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1176

writel(csr[1], nfp->iomem.csr +

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1179

writel(csr[2], nfp->iomem.csr +

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1183

readl(nfp->iomem.csr +

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1186

readl(nfp->iomem.csr +

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1189

readl(nfp->iomem.csr +

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1196

csr[0]);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1201

csr[1]);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

1206

csr[2]);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

155

void __iomem *csr;

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

274

if (nfp->iomem.csr) {

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

275

writel(newcfg, nfp->iomem.csr + xbar);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

277

readl(nfp->iomem.csr + xbar);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

628

nfp->iomem.csr = bar->iomem + NFP_PCIE_BAR(pf);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c

633

nfp->iomem.csr = bar->iomem + NFP_PCIE_BAR(0);

drivers/net/ethernet/qualcomm/emac/emac-mac.c

494

csr1 = readl(adpt->csr + EMAC_EMAC_WRAPPER_CSR1);

drivers/net/ethernet/qualcomm/emac/emac-mac.c

558

writel_relaxed(csr1, adpt->csr + EMAC_EMAC_WRAPPER_CSR1);

drivers/net/ethernet/qualcomm/emac/emac.c

565

adpt->csr = devm_platform_ioremap_resource(pdev, 1);

drivers/net/ethernet/qualcomm/emac/emac.c

566

if (IS_ERR(adpt->csr))

drivers/net/ethernet/qualcomm/emac/emac.c

567

return PTR_ERR(adpt->csr);

drivers/net/ethernet/qualcomm/emac/emac.h

331

void __iomem *csr;

drivers/net/ethernet/sun/sungem.c

2080

u32 csr;

drivers/net/ethernet/sun/sungem.c

2090

csr = WOL_WAKECSR_ENABLE;

drivers/net/ethernet/sun/sungem.c

2092

csr |= WOL_WAKECSR_MII;

drivers/net/ethernet/sun/sungem.c

2093

writel(csr, gp->regs + WOL_WAKECSR);

drivers/net/pcs/pcs-xpcs-plat.c

116

ptrdiff_t csr;

drivers/net/pcs/pcs-xpcs-plat.c

119

csr = xpcs_mmio_addr_format(dev, reg);

drivers/net/pcs/pcs-xpcs-plat.c

127

ret = readl(pxpcs->reg_base + (csr << 2)) & 0xffff;

drivers/net/pcs/pcs-xpcs-plat.c

130

ret = readw(pxpcs->reg_base + (csr << 1));

drivers/net/pcs/pcs-xpcs-plat.c

142

ptrdiff_t csr;

drivers/net/pcs/pcs-xpcs-plat.c

145

csr = xpcs_mmio_addr_format(dev, reg);

drivers/net/pcs/pcs-xpcs-plat.c

153

writel(val, pxpcs->reg_base + (csr << 2));

drivers/net/pcs/pcs-xpcs-plat.c

156

writew(val, pxpcs->reg_base + (csr << 1));

drivers/net/pcs/pcs-xpcs-plat.c

41

static u16 xpcs_mmio_addr_page(ptrdiff_t csr)

drivers/net/pcs/pcs-xpcs-plat.c

43

return FIELD_GET(0x1fff00, csr);

drivers/net/pcs/pcs-xpcs-plat.c

46

static ptrdiff_t xpcs_mmio_addr_offset(ptrdiff_t csr)

drivers/net/pcs/pcs-xpcs-plat.c

48

return FIELD_GET(0xff, csr);

drivers/net/pcs/pcs-xpcs-plat.c

54

ptrdiff_t csr, ofs;

drivers/net/pcs/pcs-xpcs-plat.c

58

csr = xpcs_mmio_addr_format(dev, reg);

drivers/net/pcs/pcs-xpcs-plat.c

59

page = xpcs_mmio_addr_page(csr);

drivers/net/pcs/pcs-xpcs-plat.c

60

ofs = xpcs_mmio_addr_offset(csr);

drivers/net/pcs/pcs-xpcs-plat.c

85

ptrdiff_t csr, ofs;

drivers/net/pcs/pcs-xpcs-plat.c

89

csr = xpcs_mmio_addr_format(dev, reg);

drivers/net/pcs/pcs-xpcs-plat.c

90

page = xpcs_mmio_addr_page(csr);

drivers/net/pcs/pcs-xpcs-plat.c

91

ofs = xpcs_mmio_addr_offset(csr);

drivers/net/wireless/ath/wil6210/debugfs.c

2312

blob->data = (void * __force)wil->csr + HOSTADDR(map->host);

drivers/net/wireless/ath/wil6210/debugfs.c

2460

wil6210_debugfs_init_offset(wil, dbg, (void * __force)wil->csr,

drivers/net/wireless/ath/wil6210/debugfs.c

317

void __iomem *x = wil->csr + HOSTADDR(r.base) + delta;

drivers/net/wireless/ath/wil6210/debugfs.c

363

wil_print_mbox_ring(s, "tx", wil->csr + HOST_MBOX +

drivers/net/wireless/ath/wil6210/debugfs.c

365

wil_print_mbox_ring(s, "rx", wil->csr + HOST_MBOX +

drivers/net/wireless/ath/wil6210/debugfs.c

504

wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr + off,

drivers/net/wireless/ath/wil6210/debugfs.c

520

wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr,

drivers/net/wireless/ath/wil6210/debugfs.c

573

wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr,

drivers/net/wireless/ath/wil6210/debugfs.c

576

wil6210_debugfs_init_offset(wil, dtx, (void * __force)wil->csr,

drivers/net/wireless/ath/wil6210/debugfs.c

579

wil6210_debugfs_init_offset(wil, drx, (void * __force)wil->csr,

drivers/net/wireless/ath/wil6210/interrupt.c

297

isr = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

359

isr = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

410

isr = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

456

isr = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

512

wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,

drivers/net/wireless/ath/wil6210/interrupt.c

544

isr = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

687

icm_rx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

690

icr_rx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

695

icm_tx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

698

icr_tx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

704

icm_rx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

707

icr_rx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

712

icm_tx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

715

icr_tx = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

721

icm_misc = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

724

icr_misc = wil_ioread32_and_clear(wil->csr +

drivers/net/wireless/ath/wil6210/interrupt.c

848

wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +

drivers/net/wireless/ath/wil6210/interrupt.c

850

wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +

drivers/net/wireless/ath/wil6210/interrupt.c

853

wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) +

drivers/net/wireless/ath/wil6210/interrupt.c

855

wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) +

drivers/net/wireless/ath/wil6210/interrupt.c

858

wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +

drivers/net/wireless/ath/wil6210/main.c

1323

wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL),

drivers/net/wireless/ath/wil6210/main.c

1412

wil_memcpy_fromio_32(mac, wil->csr + HOSTADDR(mac_addr), sizeof(mac));

drivers/net/wireless/ath/wil6210/main.c

1422

wil_memcpy_fromio_32(mac, wil->csr + HOSTADDR(mac_addr),

drivers/net/wireless/ath/wil6210/pcie_bus.c

366

wil->csr = pci_ioremap_bar(pdev, 0);

drivers/net/wireless/ath/wil6210/pcie_bus.c

367

if (!wil->csr) {

drivers/net/wireless/ath/wil6210/pcie_bus.c

373

wil_info(wil, "CSR at %pR -> 0x%p\n", &pdev->resource[0], wil->csr);

drivers/net/wireless/ath/wil6210/pcie_bus.c

450

pci_iounmap(pdev, wil->csr);

drivers/net/wireless/ath/wil6210/pcie_bus.c

466

void __iomem *csr = wil->csr;

drivers/net/wireless/ath/wil6210/pcie_bus.c

483

pci_iounmap(pdev, csr);

drivers/net/wireless/ath/wil6210/wil6210.h

1127

return readl(wil->csr + HOSTADDR(reg));

drivers/net/wireless/ath/wil6210/wil6210.h

1133

writel(val, wil->csr + HOSTADDR(reg));

drivers/net/wireless/ath/wil6210/wil6210.h

926

void __iomem *csr;

drivers/net/wireless/ath/wil6210/wil_crash_dump.c

82

data = (void * __force)wil->csr + HOSTADDR(map->host);

drivers/net/wireless/ath/wil6210/wmi.c

1940

wil_memcpy_fromio_32(&d_tail, wil->csr + HOSTADDR(r->tail),

drivers/net/wireless/ath/wil6210/wmi.c

292

return wil->csr + off;

drivers/net/wireless/ath/wil6210/wmi.c

315

return wil->csr + off;

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c

3217

DEBUGFS_WRITE_FILE_OPS(csr);

drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c

3244

DEBUGFS_ADD_FILE(csr, dir, 0200);

drivers/net/wireless/ralink/rt2x00/rt2400pci.c

161

.csr = {

drivers/net/wireless/ralink/rt2x00/rt2500pci.c

161

.csr = {

drivers/net/wireless/ralink/rt2x00/rt2500usb.c

224

.csr = {

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

1540

.csr = {

drivers/net/wireless/ralink/rt2x00/rt2800soc.c

309

rt2x00dev->csr.base = mem;

drivers/net/wireless/ralink/rt2x00/rt2x00.h

821

} csr;

drivers/net/wireless/ralink/rt2x00/rt2x00debug.c

495

RT2X00DEBUGFS_OPS(csr, "0x%.8x\n", u32);

drivers/net/wireless/ralink/rt2x00/rt2x00debug.c

623

RT2X00DEBUGFS_SPRINTF_REGISTER(csr);

drivers/net/wireless/ralink/rt2x00/rt2x00debug.c

680

RT2X00DEBUGFS_CREATE_REGISTER_ENTRY(intf, csr);

drivers/net/wireless/ralink/rt2x00/rt2x00debug.h

51

RT2X00DEBUGFS_REGISTER_ENTRY(csr, u32);

drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h

24

return readl(rt2x00dev->csr.base + offset);

drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h

31

memcpy_fromio(value, rt2x00dev->csr.base + offset, length);

drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h

38

writel(value, rt2x00dev->csr.base + offset);

drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h

46

__iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);

drivers/net/wireless/ralink/rt2x00/rt2x00pci.c

33

if (rt2x00dev->csr.base) {

drivers/net/wireless/ralink/rt2x00/rt2x00pci.c

34

iounmap(rt2x00dev->csr.base);

drivers/net/wireless/ralink/rt2x00/rt2x00pci.c

35

rt2x00dev->csr.base = NULL;

drivers/net/wireless/ralink/rt2x00/rt2x00pci.c

43

rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0);

drivers/net/wireless/ralink/rt2x00/rt2x00pci.c

44

if (!rt2x00dev->csr.base)

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

101

memcpy(rt2x00dev->csr.cache, buffer, buffer_length);

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

104

offset, 0, rt2x00dev->csr.cache,

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

108

memcpy(buffer, rt2x00dev->csr.cache, buffer_length);

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

769

kfree(rt2x00dev->csr.cache);

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

770

rt2x00dev->csr.cache = NULL;

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

775

rt2x00dev->csr.cache = kzalloc(CSR_CACHE_SIZE, GFP_KERNEL);

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

776

if (!rt2x00dev->csr.cache)

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c

95

if (unlikely(!rt2x00dev->csr.cache || buffer_length > CSR_CACHE_SIZE)) {

drivers/net/wireless/ralink/rt2x00/rt61pci.c

199

.csr = {

drivers/net/wireless/ralink/rt2x00/rt73usb.c

144

.csr = {

drivers/pci/controller/pci-xgene.c

228

struct resource csr;

drivers/pci/controller/pci-xgene.c

235

ret = xgene_get_csr_resource(adev, &csr);

drivers/pci/controller/pci-xgene.c

240

port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);

drivers/pci/pci.c

4460

u16 csr;

drivers/pci/pci.c

4466

pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);

drivers/pci/pci.c

4467

if (csr & PCI_PM_CTRL_NO_SOFT_RESET)

drivers/pci/pci.c

4482

csr &= ~PCI_PM_CTRL_STATE_MASK;

drivers/pci/pci.c

4483

csr |= PCI_D3hot;

drivers/pci/pci.c

4484

pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);

drivers/pci/pci.c

4487

csr &= ~PCI_PM_CTRL_STATE_MASK;

drivers/pci/pci.c

4488

csr |= PCI_D0;

drivers/pci/pci.c

4489

pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);

drivers/pci/quirks.c

2439

u8 __iomem *csr;

drivers/pci/quirks.c

2485

csr = ioremap(pci_resource_start(dev, 0), 8);

drivers/pci/quirks.c

2486

if (!csr) {

drivers/pci/quirks.c

2491

cmd_hi = readb(csr + 3);

drivers/pci/quirks.c

2494

writeb(1, csr + 3);

drivers/pci/quirks.c

2497

iounmap(csr);

drivers/pcmcia/pxa2xx_sharpsl.c

57

unsigned short cpr, csr;

drivers/pcmcia/pxa2xx_sharpsl.c

65

csr = read_scoop_reg(scoop, SCOOP_CSR);

drivers/pcmcia/pxa2xx_sharpsl.c

66

if (csr & 0x0004) {

drivers/pcmcia/pxa2xx_sharpsl.c

74

csr |= SCOOP_DEV[skt->nr].keep_vs;

drivers/pcmcia/pxa2xx_sharpsl.c

79

SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0);

drivers/pcmcia/pxa2xx_sharpsl.c

90

state->detect = (csr & 0x0004) ? 0 : 1;

drivers/pcmcia/pxa2xx_sharpsl.c

91

state->ready = (csr & 0x0002) ? 1 : 0;

drivers/pcmcia/pxa2xx_sharpsl.c

92

state->bvd1 = (csr & 0x0010) ? 1 : 0;

drivers/pcmcia/pxa2xx_sharpsl.c

93

state->bvd2 = (csr & 0x0020) ? 1 : 0;

drivers/pcmcia/pxa2xx_sharpsl.c

94

state->wrprot = (csr & 0x0008) ? 1 : 0;

drivers/pcmcia/pxa2xx_sharpsl.c

95

state->vs_3v = (csr & 0x0040) ? 0 : 1;

drivers/pcmcia/pxa2xx_sharpsl.c

96

state->vs_Xv = (csr & 0x0080) ? 0 : 1;

drivers/perf/riscv_pmu.c

134

unsigned long riscv_pmu_ctr_read_csr(unsigned long csr)

drivers/perf/riscv_pmu.c

136

if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H ||

drivers/perf/riscv_pmu.c

137

(csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) {

drivers/perf/riscv_pmu.c

138

pr_err("Invalid performance counter csr %lx\n", csr);

drivers/perf/riscv_pmu.c

142

return csr_read_num(csr);

drivers/perf/riscv_pmu_sbi.c

1110

hidx = info->csr - CSR_CYCLE;

drivers/perf/riscv_pmu_sbi.c

499

if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET)

drivers/perf/riscv_pmu_sbi.c

514

return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE;

drivers/perf/riscv_pmu_sbi.c

773

val = riscv_pmu_ctr_read_csr(info.csr);

drivers/perf/riscv_pmu_sbi.c

775

val |= ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32;

drivers/perf/xgene_pmu.c

1182

void __iomem *csr = pmu_dev->inf->csr;

drivers/perf/xgene_pmu.c

1189

pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;

drivers/perf/xgene_pmu.c

1191

pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;

drivers/perf/xgene_pmu.c

1198

writel(0x0, csr + PMU_PMOVSR);

drivers/perf/xgene_pmu.c

1200

writel(pmovsr, csr + PMU_PMOVSR);

drivers/perf/xgene_pmu.c

1202

writel(pmovsr, csr + PMU_PMOVSCLR);

drivers/perf/xgene_pmu.c

1503

inf->csr = dev_csr;

drivers/perf/xgene_pmu.c

1650

inf->csr = dev_csr;

drivers/perf/xgene_pmu.c

723

return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));

drivers/perf/xgene_pmu.c

748

writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));

drivers/perf/xgene_pmu.c

767

writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));

drivers/perf/xgene_pmu.c

773

writel(val, pmu_dev->inf->csr + PMU_PMAMR0);

drivers/perf/xgene_pmu.c

782

writel(val, pmu_dev->inf->csr + PMU_PMAMR1);

drivers/perf/xgene_pmu.c

793

val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);

drivers/perf/xgene_pmu.c

795

writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);

drivers/perf/xgene_pmu.c

803

val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);

drivers/perf/xgene_pmu.c

805

writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);

drivers/perf/xgene_pmu.c

813

val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);

drivers/perf/xgene_pmu.c

815

writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);

drivers/perf/xgene_pmu.c

823

val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);

drivers/perf/xgene_pmu.c

825

writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);

drivers/perf/xgene_pmu.c

832

val = readl(pmu_dev->inf->csr + PMU_PMCR);

drivers/perf/xgene_pmu.c

834

writel(val, pmu_dev->inf->csr + PMU_PMCR);

drivers/perf/xgene_pmu.c

841

val = readl(pmu_dev->inf->csr + PMU_PMCR);

drivers/perf/xgene_pmu.c

843

writel(val, pmu_dev->inf->csr + PMU_PMCR);

drivers/perf/xgene_pmu.c

850

val = readl(pmu_dev->inf->csr + PMU_PMCR);

drivers/perf/xgene_pmu.c

852

writel(val, pmu_dev->inf->csr + PMU_PMCR);

drivers/perf/xgene_pmu.c

87

void __iomem *csr;

drivers/power/reset/xgene-reboot.c

25

void __iomem *csr;

drivers/power/reset/xgene-reboot.c

34

writel(ctx->mask, ctx->csr);

drivers/power/reset/xgene-reboot.c

53

ctx->csr = devm_platform_ioremap_resource(pdev, 0);

drivers/power/reset/xgene-reboot.c

54

if (IS_ERR(ctx->csr)) {

drivers/power/reset/xgene-reboot.c

56

return PTR_ERR(ctx->csr);

drivers/regulator/bcm590xx-regulator.c

373

BCM59056_SR_DESC(CSR, csr, dcdc_csr_ranges),

drivers/regulator/bcm590xx-regulator.c

750

BCM59054_SR_DESC(CSR, csr, dcdc_csr_ranges),

drivers/regulator/bcm590xx-regulator.c

984

BCM59054_SR_DESC(CSR, csr, dcdc_csr_ranges),

drivers/scsi/NCR5380.c

1215

dregs->csr |= CSR_INTR;

drivers/scsi/NCR5380.c

1536

dregs->csr |= CSR_DMA_ENABLE;

drivers/scsi/NCR5380.c

1672

dregs->csr |= CSR_INTR;

drivers/scsi/NCR5380.c

1705

dregs->csr |= CSR_INTR;

drivers/scsi/NCR5380.c

1870

dregs->csr |= CSR_DMA_ENABLE;

drivers/scsi/NCR5380.c

922

dregs->csr |= CSR_DMA_ENABLE;

drivers/scsi/NCR5380.c

929

dregs->csr |= CSR_DMA_ENABLE;

drivers/scsi/be2iscsi/be.h

112

u8 __iomem *csr;

drivers/scsi/be2iscsi/be_main.c

478

phba->ctrl.csr = addr;

drivers/scsi/be2iscsi/be_main.c

760

isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +

drivers/scsi/sun3_scsi.c

196

unsigned short csr = dregs->csr;

drivers/scsi/sun3_scsi.c

200

dregs->csr &= ~CSR_DMA_ENABLE;

drivers/scsi/sun3_scsi.c

203

if(csr & ~CSR_GOOD) {

drivers/scsi/sun3_scsi.c

204

if (csr & CSR_DMA_BUSERR)

drivers/scsi/sun3_scsi.c

206

if (csr & CSR_DMA_CONFLICT)

drivers/scsi/sun3_scsi.c

211

if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {

drivers/scsi/sun3_scsi.c

242

dregs->csr &= ~CSR_FIFO;

drivers/scsi/sun3_scsi.c

243

dregs->csr |= CSR_FIFO;

drivers/scsi/sun3_scsi.c

248

dregs->csr |= CSR_SEND;

drivers/scsi/sun3_scsi.c

250

dregs->csr &= ~CSR_SEND;

drivers/scsi/sun3_scsi.c

253

dregs->csr |= CSR_PACK_ENABLE;

drivers/scsi/sun3_scsi.c

269

dregs->csr &= ~CSR_FIFO;

drivers/scsi/sun3_scsi.c

270

dregs->csr |= CSR_FIFO;

drivers/scsi/sun3_scsi.c

348

unsigned short csr;

drivers/scsi/sun3_scsi.c

350

csr = dregs->csr;

drivers/scsi/sun3_scsi.c

379

dregs->csr &= ~CSR_DMA_ENABLE;

drivers/scsi/sun3_scsi.c

389

if ((!write_flag) && (dregs->csr & CSR_LEFT)) {

drivers/scsi/sun3_scsi.c

397

switch (dregs->csr & CSR_LEFT) {

drivers/scsi/sun3_scsi.c

419

if(dregs->csr & CSR_FIFO_EMPTY)

drivers/scsi/sun3_scsi.c

465

dregs->csr &= ~CSR_SEND;

drivers/scsi/sun3_scsi.c

470

dregs->csr &= ~CSR_SEND;

drivers/scsi/sun3_scsi.c

473

dregs->csr &= ~CSR_FIFO;

drivers/scsi/sun3_scsi.c

474

dregs->csr |= CSR_FIFO;

drivers/scsi/sun3_scsi.c

549

oldcsr = dregs->csr;

drivers/scsi/sun3_scsi.c

550

dregs->csr = 0;

drivers/scsi/sun3_scsi.c

552

if (dregs->csr == 0x1400)

drivers/scsi/sun3_scsi.c

555

dregs->csr = oldcsr;

drivers/scsi/sun3_scsi.c

605

dregs->csr = 0;

drivers/scsi/sun3_scsi.c

607

dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;

drivers/scsi/sun3_scsi.c

73

unsigned short csr; /* control/status reg */

drivers/scsi/sun3x_esp.c

131

u32 csr;

drivers/scsi/sun3x_esp.c

137

csr = dma_read32(DMA_CSR);

drivers/scsi/sun3x_esp.c

138

csr |= DMA_ENABLE;

drivers/scsi/sun3x_esp.c

140

csr |= DMA_ST_WRITE;

drivers/scsi/sun3x_esp.c

142

csr &= ~DMA_ST_WRITE;

drivers/scsi/sun3x_esp.c

143

dma_write32(csr, DMA_CSR);

drivers/scsi/sun3x_esp.c

151

u32 csr = dma_read32(DMA_CSR);

drivers/scsi/sun3x_esp.c

153

if (csr & DMA_HNDL_ERROR)

drivers/scsi/sun3x_esp.c

86

u32 csr;

drivers/scsi/sun3x_esp.c

89

csr = dma_read32(DMA_CSR);

drivers/scsi/sun3x_esp.c

90

if (!(csr & DMA_FIFO_ISDRAIN))

drivers/scsi/sun3x_esp.c

93

dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

drivers/scsi/sun_esp.c

323

u32 csr;

drivers/scsi/sun_esp.c

329

csr = dma_read32(DMA_CSR);

drivers/scsi/sun_esp.c

330

if (!(csr & DMA_FIFO_ISDRAIN))

drivers/scsi/sun_esp.c

334

dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

drivers/scsi/sun_esp.c

389

u32 csr;

drivers/scsi/sun_esp.c

401

csr = esp->prev_hme_dmacsr;

drivers/scsi/sun_esp.c

402

csr |= DMA_SCSI_DISAB | DMA_ENABLE;

drivers/scsi/sun_esp.c

404

csr |= DMA_ST_WRITE;

drivers/scsi/sun_esp.c

406

csr &= ~DMA_ST_WRITE;

drivers/scsi/sun_esp.c

407

esp->prev_hme_dmacsr = csr;

drivers/scsi/sun_esp.c

411

dma_write32(csr, DMA_CSR);

drivers/scsi/sun_esp.c

413

csr = dma_read32(DMA_CSR);

drivers/scsi/sun_esp.c

414

csr |= DMA_ENABLE;

drivers/scsi/sun_esp.c

416

csr |= DMA_ST_WRITE;

drivers/scsi/sun_esp.c

418

csr &= ~DMA_ST_WRITE;

drivers/scsi/sun_esp.c

419

dma_write32(csr, DMA_CSR);

drivers/scsi/sun_esp.c

433

u32 csr = dma_read32(DMA_CSR);

drivers/scsi/sun_esp.c

435

if (csr & DMA_HNDL_ERROR)

drivers/spi/spi-atmel.c

1251

u32 csr;

drivers/spi/spi-atmel.c

1282

csr = SPI_BF(BITS, bits - 8);

drivers/spi/spi-atmel.c

1284

csr |= SPI_BIT(CPOL);

drivers/spi/spi-atmel.c

1286

csr |= SPI_BIT(NCPHA);

drivers/spi/spi-atmel.c

1289

csr |= SPI_BIT(CSAAT);

drivers/spi/spi-atmel.c

1290

csr |= SPI_BF(DLYBS, 0);

drivers/spi/spi-atmel.c

1299

csr |= SPI_BF(DLYBCT, word_delay_csr);

drivers/spi/spi-atmel.c

1310

asd->csr = csr;

drivers/spi/spi-atmel.c

1314

bits, spi->mode, spi_get_chipselect(spi, 0), csr);

drivers/spi/spi-atmel.c

1317

spi_writel(as, CSR0 + 4 * chip_select, csr);

drivers/spi/spi-atmel.c

1355

bits = (asd->csr >> 4) & 0xf;

drivers/spi/spi-atmel.c

288

u32 csr;

drivers/spi/spi-atmel.c

332

u32 csr;

drivers/spi/spi-atmel.c

339

csr = spi_readl(as, CSR0 + 4 * chip_select);

drivers/spi/spi-atmel.c

340

csr = SPI_BFINS(SCBR, DUMMY_MSG_FREQUENCY, csr);

drivers/spi/spi-atmel.c

341

spi_writel(as, CSR0 + 4 * chip_select, csr);

drivers/spi/spi-atmel.c

396

spi_writel(as, CSR0 + 4 * chip_select, asd->csr);

drivers/spi/spi-atmel.c

400

spi_writel(as, CSR0, asd->csr);

drivers/spi/spi-atmel.c

412

new_polarity = (asd->csr & SPI_BIT(CPOL)) != 0;

drivers/spi/spi-atmel.c

427

u32 csr;

drivers/spi/spi-atmel.c

431

csr = spi_readl(as, CSR0 + 4 * i);

drivers/spi/spi-atmel.c

432

if ((csr ^ cpol) & SPI_BIT(CPOL))

drivers/spi/spi-atmel.c

434

csr ^ SPI_BIT(CPOL));

drivers/spi/spi-atmel.c

868

u32 scbr, csr;

drivers/spi/spi-atmel.c

904

csr = spi_readl(as, CSR0 + 4 * chip_select);

drivers/spi/spi-atmel.c

905

csr = SPI_BFINS(SCBR, scbr, csr);

drivers/spi/spi-atmel.c

906

spi_writel(as, CSR0 + 4 * chip_select, csr);

drivers/tty/ipwireless/hardware.c

1096

unsigned short csr = readw(&hw->memregs_CCR->reg_config_and_status);

drivers/tty/ipwireless/hardware.c

1098

csr &= 0xfffd;

drivers/tty/ipwireless/hardware.c

1099

writew(csr, &hw->memregs_CCR->reg_config_and_status);

drivers/tty/ipwireless/hardware.c

539

unsigned short csr = readw(&hw->memregs_CCR->reg_config_and_status);

drivers/tty/ipwireless/hardware.c

541

csr |= 1;

drivers/tty/ipwireless/hardware.c

542

writew(csr, &hw->memregs_CCR->reg_config_and_status);

drivers/tty/serial/dz.c

810

unsigned short csr, tcr, trdy, mask;

drivers/tty/serial/dz.c

814

csr = dz_in(dport, DZ_CSR);

drivers/tty/serial/dz.c

815

dz_out(dport, DZ_CSR, csr & ~DZ_TIE);

drivers/tty/serial/dz.c

840

dz_out(dport, DZ_CSR, csr);

drivers/tty/serial/sb1250-duart.c

118

void __iomem *csr = sport->port.membase + reg;

drivers/tty/serial/sb1250-duart.c

120

return __raw_readq(csr);

drivers/tty/serial/sb1250-duart.c

125

void __iomem *csr = sport->memctrl + reg;

drivers/tty/serial/sb1250-duart.c

127

return __raw_readq(csr);

drivers/tty/serial/sb1250-duart.c

132

void __iomem *csr = sport->port.membase + reg;

drivers/tty/serial/sb1250-duart.c

134

__raw_writeq(value, csr);

drivers/tty/serial/sb1250-duart.c

139

void __iomem *csr = sport->memctrl + reg;

drivers/tty/serial/sb1250-duart.c

141

__raw_writeq(value, csr);

drivers/tty/serial/sccnxp.c

267

u8 csr;

drivers/tty/serial/sccnxp.c

308

u8 i, acr = 0, csr = 0, mr0 = 0;

drivers/tty/serial/sccnxp.c

315

csr = CSR_TIMER_MODE;

drivers/tty/serial/sccnxp.c

330

csr = baud_std[i].csr;

drivers/tty/serial/sccnxp.c

345

sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);

drivers/usb/gadget/udc/amd5536udc.h

548

struct udc_csrs __iomem *csr;

drivers/usb/gadget/udc/amd5536udc_pci.c

133

dev->csr = dev->virt_addr + UDC_CSR_ADDR;

drivers/usb/gadget/udc/at91_udc.c

1010

u32 csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

1019

if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) {

drivers/usb/gadget/udc/at91_udc.c

1020

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1021

csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP);

drivers/usb/gadget/udc/at91_udc.c

1022

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

1028

if (csr & AT91_UDP_STALLSENT) {

drivers/usb/gadget/udc/at91_udc.c

1032

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1033

csr &= ~(SET_FX | AT91_UDP_STALLSENT);

drivers/usb/gadget/udc/at91_udc.c

1034

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

1035

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

1037

if (req && (csr & RX_DATA_READY))

drivers/usb/gadget/udc/at91_udc.c

1048

static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)

drivers/usb/gadget/udc/at91_udc.c

1058

rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16;

drivers/usb/gadget/udc/at91_udc.c

1063

csr |= AT91_UDP_DIR;

drivers/usb/gadget/udc/at91_udc.c

1066

csr &= ~AT91_UDP_DIR;

drivers/usb/gadget/udc/at91_udc.c

1071

ERR("SETUP len %d, csr %08x\n", rxcount, csr);

drivers/usb/gadget/udc/at91_udc.c

1074

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1075

csr &= ~(SET_FX | AT91_UDP_RXSETUP);

drivers/usb/gadget/udc/at91_udc.c

1076

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

1096

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

1097

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1098

csr &= ~SET_FX;

drivers/usb/gadget/udc/at91_udc.c

1103

__raw_writel(csr | AT91_UDP_TXPKTRDY, creg);

drivers/usb/gadget/udc/at91_udc.c

112

u32 csr;

drivers/usb/gadget/udc/at91_udc.c

119

csr = __raw_readl(ep->creg);

drivers/usb/gadget/udc/at91_udc.c

1259

csr |= AT91_UDP_FORCESTALL;

drivers/usb/gadget/udc/at91_udc.c

1260

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

1269

csr |= AT91_UDP_TXPKTRDY;

drivers/usb/gadget/udc/at91_udc.c

1270

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

1278

u32 csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

1281

if (unlikely(csr & AT91_UDP_STALLSENT)) {

drivers/usb/gadget/udc/at91_udc.c

1284

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1285

csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL);

drivers/usb/gadget/udc/at91_udc.c

1286

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

1288

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

1290

if (csr & AT91_UDP_RXSETUP) {

drivers/usb/gadget/udc/at91_udc.c

1293

handle_setup(udc, ep0, csr);

drivers/usb/gadget/udc/at91_udc.c

1303

if (csr & AT91_UDP_TXCOMP) {

drivers/usb/gadget/udc/at91_udc.c

1304

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1305

csr &= ~(SET_FX | AT91_UDP_TXCOMP);

drivers/usb/gadget/udc/at91_udc.c

1322

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

133

csr,

drivers/usb/gadget/udc/at91_udc.c

134

(csr & 0x07ff0000) >> 16,

drivers/usb/gadget/udc/at91_udc.c

1346

else if (csr & AT91_UDP_RX_DATA_BK0) {

drivers/usb/gadget/udc/at91_udc.c

1347

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

1348

csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);

drivers/usb/gadget/udc/at91_udc.c

135

str_enabled_disabled(csr & (1 << 15)),

drivers/usb/gadget/udc/at91_udc.c

1356

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

1357

csr &= ~SET_FX;

drivers/usb/gadget/udc/at91_udc.c

1358

csr |= CLR_FX | AT91_UDP_TXPKTRDY;

drivers/usb/gadget/udc/at91_udc.c

1359

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

136

(csr & (1 << 11)) ? "DATA1" : "DATA0",

drivers/usb/gadget/udc/at91_udc.c

137

types[(csr & 0x700) >> 8],

drivers/usb/gadget/udc/at91_udc.c

1381

__raw_writel(csr | AT91_UDP_FORCESTALL, creg);

drivers/usb/gadget/udc/at91_udc.c

1388

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

140

(!(csr & 0x700))

drivers/usb/gadget/udc/at91_udc.c

141

? ((csr & (1 << 7)) ? " IN" : " OUT")

drivers/usb/gadget/udc/at91_udc.c

143

(csr & (1 << 6)) ? " rxdatabk1" : "",

drivers/usb/gadget/udc/at91_udc.c

144

(csr & (1 << 5)) ? " forcestall" : "",

drivers/usb/gadget/udc/at91_udc.c

145

(csr & (1 << 4)) ? " txpktrdy" : "",

drivers/usb/gadget/udc/at91_udc.c

147

(csr & (1 << 3)) ? " stallsent" : "",

drivers/usb/gadget/udc/at91_udc.c

148

(csr & (1 << 2)) ? " rxsetup" : "",

drivers/usb/gadget/udc/at91_udc.c

149

(csr & (1 << 1)) ? " rxdatabk0" : "",

drivers/usb/gadget/udc/at91_udc.c

150

(csr & (1 << 0)) ? " txcomp" : "");

drivers/usb/gadget/udc/at91_udc.c

315

u32 csr;

drivers/usb/gadget/udc/at91_udc.c

327

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

328

if ((csr & RX_DATA_READY) == 0)

drivers/usb/gadget/udc/at91_udc.c

331

count = (csr & AT91_UDP_RXBYTECNT) >> 16;

drivers/usb/gadget/udc/at91_udc.c

342

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

345

csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);

drivers/usb/gadget/udc/at91_udc.c

348

csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1);

drivers/usb/gadget/udc/at91_udc.c

352

csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);

drivers/usb/gadget/udc/at91_udc.c

353

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

375

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

389

u32 csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

406

if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) {

drivers/usb/gadget/udc/at91_udc.c

407

if (csr & AT91_UDP_TXCOMP) {

drivers/usb/gadget/udc/at91_udc.c

408

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

409

csr &= ~(SET_FX | AT91_UDP_TXCOMP);

drivers/usb/gadget/udc/at91_udc.c

410

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

411

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

413

if (csr & AT91_UDP_TXPKTRDY)

drivers/usb/gadget/udc/at91_udc.c

442

csr &= ~SET_FX;

drivers/usb/gadget/udc/at91_udc.c

443

csr |= CLR_FX | AT91_UDP_TXPKTRDY;

drivers/usb/gadget/udc/at91_udc.c

444

__raw_writel(csr, creg);

drivers/usb/gadget/udc/at91_udc.c

742

u32 csr;

drivers/usb/gadget/udc/at91_udc.c

752

csr = __raw_readl(creg);

drivers/usb/gadget/udc/at91_udc.c

759

if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0))

drivers/usb/gadget/udc/at91_udc.c

762

csr |= CLR_FX;

drivers/usb/gadget/udc/at91_udc.c

763

csr &= ~SET_FX;

drivers/usb/gadget/udc/at91_udc.c

765

csr |= AT91_UDP_FORCESTALL;

drivers/usb/gadget/udc/at91_udc.c

770

csr &= ~AT91_UDP_FORCESTALL;

drivers/usb/gadget/udc/at91_udc.c

772

__raw_writel(csr, creg);

drivers/usb/gadget/udc/snps_udc_core.c

1865

tmp = readl(&dev->csr->ne[0]);

drivers/usb/gadget/udc/snps_udc_core.c

1872

writel(tmp, &dev->csr->ne[0]);

drivers/usb/gadget/udc/snps_udc_core.c

2781

tmp = readl(&dev->csr->ne[udc_csr_epix]);

drivers/usb/gadget/udc/snps_udc_core.c

2786

writel(tmp, &dev->csr->ne[udc_csr_epix]);

drivers/usb/gadget/udc/snps_udc_core.c

2836

tmp = readl(&dev->csr->ne[udc_csr_epix]);

drivers/usb/gadget/udc/snps_udc_core.c

2845

writel(tmp, &dev->csr->ne[udc_csr_epix]);

drivers/usb/gadget/udc/snps_udc_core.c

389

tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);

drivers/usb/gadget/udc/snps_udc_core.c

392

writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);

drivers/usb/gadget/udc/snps_udc_core.c

405

tmp = readl(&dev->csr->ne[udc_csr_epix]);

drivers/usb/gadget/udc/snps_udc_core.c

421

writel(tmp, &dev->csr->ne[udc_csr_epix]);

drivers/usb/gadget/udc/snps_udc_plat.c

119

udc->csr = udc->virt_addr + UDC_CSR_ADDR;

drivers/usb/mtu3/mtu3_core.c

313

u32 csr;

drivers/usb/mtu3/mtu3_core.c

316

csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;

drivers/usb/mtu3/mtu3_core.c

318

csr |= TX_SENDSTALL;

drivers/usb/mtu3/mtu3_core.c

320

csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;

drivers/usb/mtu3/mtu3_core.c

321

mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);

drivers/usb/mtu3/mtu3_core.c

323

csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;

drivers/usb/mtu3/mtu3_core.c

325

csr |= RX_SENDSTALL;

drivers/usb/mtu3/mtu3_core.c

327

csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;

drivers/usb/mtu3/mtu3_core.c

328

mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);

drivers/usb/mtu3/mtu3_core.c

583

u32 csr;

drivers/usb/mtu3/mtu3_core.c

587

csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);

drivers/usb/mtu3/mtu3_core.c

588

csr &= ~EP0_MAXPKTSZ_MSK;

drivers/usb/mtu3/mtu3_core.c

589

csr |= EP0_MAXPKTSZ(maxpacket);

drivers/usb/mtu3/mtu3_core.c

590

csr &= EP0_W1C_BITS;

drivers/usb/mtu3/mtu3_core.c

591

mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);

drivers/usb/mtu3/mtu3_gadget_ep0.c

139

u32 csr;

drivers/usb/mtu3/mtu3_gadget_ep0.c

142

csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;

drivers/usb/mtu3/mtu3_gadget_ep0.c

144

csr |= EP0_SENDSTALL | pktrdy;

drivers/usb/mtu3/mtu3_gadget_ep0.c

146

csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL;

drivers/usb/mtu3/mtu3_gadget_ep0.c

147

mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);

drivers/usb/mtu3/mtu3_gadget_ep0.c

515

u32 csr;

drivers/usb/mtu3/mtu3_gadget_ep0.c

520

csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;

drivers/usb/mtu3/mtu3_gadget_ep0.c

537

csr |= EP0_RXPKTRDY;

drivers/usb/mtu3/mtu3_gadget_ep0.c

545

csr |= EP0_DATAEND;

drivers/usb/mtu3/mtu3_gadget_ep0.c

550

csr |= EP0_RXPKTRDY | EP0_SENDSTALL;

drivers/usb/mtu3/mtu3_gadget_ep0.c

554

mtu3_writel(mbase, U3D_EP0CSR, csr);

drivers/usb/mtu3/mtu3_gadget_ep0.c

567

u32 csr;

drivers/usb/mtu3/mtu3_gadget_ep0.c

596

csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS;

drivers/usb/mtu3/mtu3_gadget_ep0.c

597

mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr | EP0_TXPKTRDY);

drivers/usb/mtu3/mtu3_gadget_ep0.c

607

u32 csr;

drivers/usb/mtu3/mtu3_gadget_ep0.c

609

csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS;

drivers/usb/mtu3/mtu3_gadget_ep0.c

628

csr | EP0_SETUPPKTRDY | EP0_DPHTX);

drivers/usb/mtu3/mtu3_gadget_ep0.c

632

(csr | EP0_SETUPPKTRDY) & (~EP0_DPHTX));

drivers/usb/mtu3/mtu3_gadget_ep0.c

702

u32 csr;

drivers/usb/mtu3/mtu3_gadget_ep0.c

717

csr = mtu3_readl(mbase, U3D_EP0CSR);

drivers/usb/mtu3/mtu3_gadget_ep0.c

719

dev_dbg(mtu->dev, "%s csr=0x%x\n", __func__, csr);

drivers/usb/mtu3/mtu3_gadget_ep0.c

722

if (csr & EP0_SENTSTALL) {

drivers/usb/mtu3/mtu3_gadget_ep0.c

724

csr = mtu3_readl(mbase, U3D_EP0CSR);

drivers/usb/mtu3/mtu3_gadget_ep0.c

733

if ((csr & EP0_FIFOFULL) == 0) {

drivers/usb/mtu3/mtu3_gadget_ep0.c

740

if (csr & EP0_RXPKTRDY) {

drivers/usb/mtu3/mtu3_gadget_ep0.c

747

(csr & EP0_W1C_BITS) | EP0_DATAEND);

drivers/usb/mtu3/mtu3_gadget_ep0.c

758

if (!(csr & EP0_SETUPPKTRDY))

drivers/usb/musb/musb_core.c

282

u16 csr;

drivers/usb/musb/musb_core.c

285

csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;

drivers/usb/musb/musb_core.c

287

csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;

drivers/usb/musb/musb_core.c

289

return csr;

drivers/usb/musb/musb_core.c

295

u16 csr;

drivers/usb/musb/musb_core.c

301

csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE

drivers/usb/musb/musb_core.c

305

csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE

drivers/usb/musb/musb_core.c

308

return csr;

drivers/usb/musb/musb_cppi41.c

105

u16 csr;

drivers/usb/musb/musb_cppi41.c

108

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_cppi41.c

109

if (csr & MUSB_TXCSR_TXPKTRDY)

drivers/usb/musb/musb_cppi41.c

122

u16 csr;

drivers/usb/musb/musb_cppi41.c

140

csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;

drivers/usb/musb/musb_cppi41.c

141

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_cppi41.c

178

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_cppi41.c

179

csr |= MUSB_RXCSR_H_REQPKT;

drivers/usb/musb/musb_cppi41.c

180

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_cppi41.c

56

u16 csr;

drivers/usb/musb/musb_cppi41.c

582

u16 csr;

drivers/usb/musb/musb_cppi41.c

592

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_cppi41.c

593

csr &= ~MUSB_TXCSR_DMAENAB;

drivers/usb/musb/musb_cppi41.c

594

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_cppi41.c

601

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_cppi41.c

602

csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);

drivers/usb/musb/musb_cppi41.c

603

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_cppi41.c

608

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_cppi41.c

609

if (csr & MUSB_RXCSR_RXPKTRDY) {

drivers/usb/musb/musb_cppi41.c

610

csr |= MUSB_RXCSR_FLUSHFIFO;

drivers/usb/musb/musb_cppi41.c

611

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_cppi41.c

612

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_cppi41.c

634

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_cppi41.c

635

if (csr & MUSB_TXCSR_TXPKTRDY) {

drivers/usb/musb/musb_cppi41.c

636

csr |= MUSB_TXCSR_FLUSHFIFO;

drivers/usb/musb/musb_cppi41.c

637

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_cppi41.c

64

csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);

drivers/usb/musb/musb_cppi41.c

65

toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;

drivers/usb/musb/musb_cppi41.c

74

u16 csr;

drivers/usb/musb/musb_cppi41.c

83

csr = musb_readw(hw_ep->regs, MUSB_RXCSR);

drivers/usb/musb/musb_cppi41.c

84

toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;

drivers/usb/musb/musb_cppi41.c

92

csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;

drivers/usb/musb/musb_cppi41.c

93

musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1001

csr |= MUSB_TXCSR_FLUSHFIFO;

drivers/usb/musb/musb_gadget.c

1003

csr |= MUSB_TXCSR_P_ISO;

drivers/usb/musb/musb_gadget.c

1006

musb_writew(regs, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

1008

musb_writew(regs, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

1036

csr = musb_readw(regs, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

1037

csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);

drivers/usb/musb/musb_gadget.c

1038

musb_writew(regs, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

1041

csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;

drivers/usb/musb/musb_gadget.c

1043

csr |= MUSB_RXCSR_P_ISO;

drivers/usb/musb/musb_gadget.c

1045

csr |= MUSB_RXCSR_DISNYET;

drivers/usb/musb/musb_gadget.c

1048

musb_writew(regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1049

musb_writew(regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1165

u16 csr;

drivers/usb/musb/musb_gadget.c

1173

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_gadget.c

1174

csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

1175

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1176

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1334

u16 csr;

drivers/usb/musb/musb_gadget.c

1361

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

1362

if (csr & MUSB_TXCSR_FIFONOTEMPTY) {

drivers/usb/musb/musb_gadget.c

1375

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

1376

csr |= MUSB_TXCSR_P_WZC_BITS

drivers/usb/musb/musb_gadget.c

1379

csr |= MUSB_TXCSR_P_SENDSTALL;

drivers/usb/musb/musb_gadget.c

1381

csr &= ~(MUSB_TXCSR_P_SENDSTALL

drivers/usb/musb/musb_gadget.c

1383

csr &= ~MUSB_TXCSR_TXPKTRDY;

drivers/usb/musb/musb_gadget.c

1384

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

1386

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_gadget.c

1387

csr |= MUSB_RXCSR_P_WZC_BITS

drivers/usb/musb/musb_gadget.c

1391

csr |= MUSB_RXCSR_P_SENDSTALL;

drivers/usb/musb/musb_gadget.c

1393

csr &= ~(MUSB_RXCSR_P_SENDSTALL

drivers/usb/musb/musb_gadget.c

1395

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1455

u16 csr;

drivers/usb/musb/musb_gadget.c

1466

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

1467

if (csr & MUSB_TXCSR_FIFONOTEMPTY) {

drivers/usb/musb/musb_gadget.c

1468

csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

1474

csr &= ~MUSB_TXCSR_TXPKTRDY;

drivers/usb/musb/musb_gadget.c

1475

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

1477

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

1480

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_gadget.c

1481

csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

1482

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

1483

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

230

u16 fifo_count = 0, csr;

drivers/usb/musb/musb_gadget.c

249

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

255

if (csr & MUSB_TXCSR_TXPKTRDY) {

drivers/usb/musb/musb_gadget.c

257

musb_ep->end_point.name, csr);

drivers/usb/musb/musb_gadget.c

261

if (csr & MUSB_TXCSR_P_SENDSTALL) {

drivers/usb/musb/musb_gadget.c

263

musb_ep->end_point.name, csr);

drivers/usb/musb/musb_gadget.c

269

csr);

drivers/usb/musb/musb_gadget.c

302

csr &= ~(MUSB_TXCSR_AUTOSET

drivers/usb/musb/musb_gadget.c

304

musb_writew(epio, MUSB_TXCSR, csr

drivers/usb/musb/musb_gadget.c

306

csr &= ~MUSB_TXCSR_DMAMODE;

drivers/usb/musb/musb_gadget.c

307

csr |= (MUSB_TXCSR_DMAENAB |

drivers/usb/musb/musb_gadget.c

311

csr |= (MUSB_TXCSR_DMAENAB

drivers/usb/musb/musb_gadget.c

326

csr |= MUSB_TXCSR_AUTOSET;

drivers/usb/musb/musb_gadget.c

328

csr &= ~MUSB_TXCSR_P_UNDERRUN;

drivers/usb/musb/musb_gadget.c

330

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

336

csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);

drivers/usb/musb/musb_gadget.c

337

csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |

drivers/usb/musb/musb_gadget.c

340

~MUSB_TXCSR_P_UNDERRUN) | csr);

drivers/usb/musb/musb_gadget.c

343

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

366

csr &= ~MUSB_TXCSR_DMAENAB;

drivers/usb/musb/musb_gadget.c

367

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

389

csr |= MUSB_TXCSR_TXPKTRDY;

drivers/usb/musb/musb_gadget.c

390

csr &= ~MUSB_TXCSR_P_UNDERRUN;

drivers/usb/musb/musb_gadget.c

391

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

409

u16 csr;

drivers/usb/musb/musb_gadget.c

421

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

422

musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);

drivers/usb/musb/musb_gadget.c

430

if (csr & MUSB_TXCSR_P_SENTSTALL) {

drivers/usb/musb/musb_gadget.c

431

csr |= MUSB_TXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

432

csr &= ~MUSB_TXCSR_P_SENTSTALL;

drivers/usb/musb/musb_gadget.c

433

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

437

if (csr & MUSB_TXCSR_P_UNDERRUN) {

drivers/usb/musb/musb_gadget.c

439

csr |= MUSB_TXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

440

csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);

drivers/usb/musb/musb_gadget.c

441

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

459

if (dma && (csr & MUSB_TXCSR_DMAENAB)) {

drivers/usb/musb/musb_gadget.c

460

csr |= MUSB_TXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

461

csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |

drivers/usb/musb/musb_gadget.c

463

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget.c

465

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_gadget.c

468

epnum, csr, musb_ep->dma->actual_len, request);

drivers/usb/musb/musb_gadget.c

483

if (csr & MUSB_TXCSR_TXPKTRDY)

drivers/usb/musb/musb_gadget.c

527

u16 csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_gadget.c

551

if (csr & MUSB_RXCSR_P_SENDSTALL) {

drivers/usb/musb/musb_gadget.c

553

musb_ep->end_point.name, csr);

drivers/usb/musb/musb_gadget.c

576

csr &= ~(MUSB_RXCSR_AUTOCLEAR

drivers/usb/musb/musb_gadget.c

578

csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

579

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

584

if (csr & MUSB_RXCSR_RXPKTRDY) {

drivers/usb/musb/musb_gadget.c

634

csr |= MUSB_RXCSR_AUTOCLEAR;

drivers/usb/musb/musb_gadget.c

635

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

636

csr |= MUSB_RXCSR_DMAENAB;

drivers/usb/musb/musb_gadget.c

637

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

645

csr | MUSB_RXCSR_DMAMODE);

drivers/usb/musb/musb_gadget.c

646

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

656

csr |= MUSB_RXCSR_AUTOCLEAR;

drivers/usb/musb/musb_gadget.c

657

csr |= MUSB_RXCSR_DMAENAB;

drivers/usb/musb/musb_gadget.c

658

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

701

csr &= ~MUSB_RXCSR_DMAMODE;

drivers/usb/musb/musb_gadget.c

702

csr |= (MUSB_RXCSR_DMAENAB |

drivers/usb/musb/musb_gadget.c

705

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

712

csr |= MUSB_RXCSR_DMAMODE;

drivers/usb/musb/musb_gadget.c

713

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

760

csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);

drivers/usb/musb/musb_gadget.c

761

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

776

csr |= MUSB_RXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

777

csr &= ~MUSB_RXCSR_RXPKTRDY;

drivers/usb/musb/musb_gadget.c

778

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

793

u16 csr;

drivers/usb/musb/musb_gadget.c

816

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_gadget.c

820

csr, dma ? " (dma)" : "", request);

drivers/usb/musb/musb_gadget.c

822

if (csr & MUSB_RXCSR_P_SENTSTALL) {

drivers/usb/musb/musb_gadget.c

823

csr |= MUSB_RXCSR_P_WZC_BITS;

drivers/usb/musb/musb_gadget.c

824

csr &= ~MUSB_RXCSR_P_SENTSTALL;

drivers/usb/musb/musb_gadget.c

825

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

829

if (csr & MUSB_RXCSR_P_OVERRUN) {

drivers/usb/musb/musb_gadget.c

831

csr &= ~MUSB_RXCSR_P_OVERRUN;

drivers/usb/musb/musb_gadget.c

832

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

838

if (csr & MUSB_RXCSR_INCOMPRX) {

drivers/usb/musb/musb_gadget.c

846

musb_ep->end_point.name, csr);

drivers/usb/musb/musb_gadget.c

850

if (dma && (csr & MUSB_RXCSR_DMAENAB)) {

drivers/usb/musb/musb_gadget.c

851

csr &= ~(MUSB_RXCSR_AUTOCLEAR

drivers/usb/musb/musb_gadget.c

855

MUSB_RXCSR_P_WZC_BITS | csr);

drivers/usb/musb/musb_gadget.c

866

csr &= ~MUSB_RXCSR_RXPKTRDY;

drivers/usb/musb/musb_gadget.c

867

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget.c

877

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_gadget.c

878

if ((csr & MUSB_RXCSR_RXPKTRDY) &&

drivers/usb/musb/musb_gadget.c

919

u16 csr;

drivers/usb/musb/musb_gadget.c

998

csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;

drivers/usb/musb/musb_gadget_ep0.c

1016

csr = musb->ackpend;

drivers/usb/musb/musb_gadget_ep0.c

1026

csr = musb_readw(regs, MUSB_CSR0);

drivers/usb/musb/musb_gadget_ep0.c

1035

csr |= MUSB_CSR0_P_SENDSTALL;

drivers/usb/musb/musb_gadget_ep0.c

1036

musb_writew(regs, MUSB_CSR0, csr);

drivers/usb/musb/musb_gadget_ep0.c

243

u16 csr;

drivers/usb/musb/musb_gadget_ep0.c

266

csr = musb_readw(regs, MUSB_TXCSR);

drivers/usb/musb/musb_gadget_ep0.c

267

csr |= MUSB_TXCSR_CLRDATATOG |

drivers/usb/musb/musb_gadget_ep0.c

269

csr &= ~(MUSB_TXCSR_P_SENDSTALL |

drivers/usb/musb/musb_gadget_ep0.c

272

musb_writew(regs, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget_ep0.c

274

csr = musb_readw(regs, MUSB_RXCSR);

drivers/usb/musb/musb_gadget_ep0.c

275

csr |= MUSB_RXCSR_CLRDATATOG |

drivers/usb/musb/musb_gadget_ep0.c

277

csr &= ~(MUSB_RXCSR_P_SENDSTALL |

drivers/usb/musb/musb_gadget_ep0.c

279

musb_writew(regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget_ep0.c

403

u16 csr;

drivers/usb/musb/musb_gadget_ep0.c

421

csr = musb_readw(regs, MUSB_TXCSR);

drivers/usb/musb/musb_gadget_ep0.c

422

if (csr & MUSB_TXCSR_FIFONOTEMPTY)

drivers/usb/musb/musb_gadget_ep0.c

423

csr |= MUSB_TXCSR_FLUSHFIFO;

drivers/usb/musb/musb_gadget_ep0.c

424

csr |= MUSB_TXCSR_P_SENDSTALL

drivers/usb/musb/musb_gadget_ep0.c

427

musb_writew(regs, MUSB_TXCSR, csr);

drivers/usb/musb/musb_gadget_ep0.c

429

csr = musb_readw(regs, MUSB_RXCSR);

drivers/usb/musb/musb_gadget_ep0.c

430

csr |= MUSB_RXCSR_P_SENDSTALL

drivers/usb/musb/musb_gadget_ep0.c

434

musb_writew(regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_gadget_ep0.c

465

u16 count, csr;

drivers/usb/musb/musb_gadget_ep0.c

487

csr = MUSB_CSR0_P_SVDRXPKTRDY;

drivers/usb/musb/musb_gadget_ep0.c

490

csr |= MUSB_CSR0_P_DATAEND;

drivers/usb/musb/musb_gadget_ep0.c

494

csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;

drivers/usb/musb/musb_gadget_ep0.c

501

musb->ackpend = csr;

drivers/usb/musb/musb_gadget_ep0.c

508

musb_writew(regs, MUSB_CSR0, csr);

drivers/usb/musb/musb_gadget_ep0.c

522

u16 csr = MUSB_CSR0_TXPKTRDY;

drivers/usb/musb/musb_gadget_ep0.c

546

csr |= MUSB_CSR0_P_DATAEND;

drivers/usb/musb/musb_gadget_ep0.c

556

musb->ackpend = csr;

drivers/usb/musb/musb_gadget_ep0.c

565

musb_writew(regs, MUSB_CSR0, csr);

drivers/usb/musb/musb_gadget_ep0.c

643

u16 csr;

drivers/usb/musb/musb_gadget_ep0.c

650

csr = musb_readw(regs, MUSB_CSR0);

drivers/usb/musb/musb_gadget_ep0.c

654

csr, len, decode_ep0stage(musb->ep0_state));

drivers/usb/musb/musb_gadget_ep0.c

656

if (csr & MUSB_CSR0_P_DATAEND) {

drivers/usb/musb/musb_gadget_ep0.c

665

if (csr & MUSB_CSR0_P_SENTSTALL) {

drivers/usb/musb/musb_gadget_ep0.c

667

csr & ~MUSB_CSR0_P_SENTSTALL);

drivers/usb/musb/musb_gadget_ep0.c

670

csr = musb_readw(regs, MUSB_CSR0);

drivers/usb/musb/musb_gadget_ep0.c

674

if (csr & MUSB_CSR0_P_SETUPEND) {

drivers/usb/musb/musb_gadget_ep0.c

689

csr = musb_readw(regs, MUSB_CSR0);

drivers/usb/musb/musb_gadget_ep0.c

701

if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {

drivers/usb/musb/musb_gadget_ep0.c

709

if (csr & MUSB_CSR0_RXPKTRDY) {

drivers/usb/musb/musb_gadget_ep0.c

754

if (csr & MUSB_CSR0_RXPKTRDY)

drivers/usb/musb/musb_gadget_ep0.c

774

if (csr & MUSB_CSR0_RXPKTRDY) {

drivers/usb/musb/musb_gadget_ep0.c

843

handled, csr,

drivers/usb/musb/musb_gadget_ep0.c

997

u16 csr;

drivers/usb/musb/musb_host.c

1057

u16 csr, len;

drivers/usb/musb/musb_host.c

1070

csr = musb_readw(epio, MUSB_CSR0);

drivers/usb/musb/musb_host.c

1071

len = (csr & MUSB_CSR0_RXPKTRDY)

drivers/usb/musb/musb_host.c

1076

csr, qh, len, urb, musb->ep0_stage);

drivers/usb/musb/musb_host.c

1085

if (csr & MUSB_CSR0_H_RXSTALL) {

drivers/usb/musb/musb_host.c

1089

} else if (csr & MUSB_CSR0_H_ERROR) {

drivers/usb/musb/musb_host.c

1090

musb_dbg(musb, "no response, csr0 %04x", csr);

drivers/usb/musb/musb_host.c

1093

} else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {

drivers/usb/musb/musb_host.c

1116

if (csr & MUSB_CSR0_H_REQPKT) {

drivers/usb/musb/musb_host.c

1117

csr &= ~MUSB_CSR0_H_REQPKT;

drivers/usb/musb/musb_host.c

1118

musb_writew(epio, MUSB_CSR0, csr);

drivers/usb/musb/musb_host.c

1119

csr &= ~MUSB_CSR0_H_NAKTIMEOUT;

drivers/usb/musb/musb_host.c

1120

musb_writew(epio, MUSB_CSR0, csr);

drivers/usb/musb/musb_host.c

1144

csr = (MUSB_EP0_IN == musb->ep0_stage)

drivers/usb/musb/musb_host.c

1150

csr = MUSB_CSR0_H_STATUSPKT

drivers/usb/musb/musb_host.c

1153

csr = MUSB_CSR0_H_STATUSPKT

drivers/usb/musb/musb_host.c

1157

csr |= MUSB_CSR0_H_DIS_PING;

drivers/usb/musb/musb_host.c

116

ep->epnum, csr))

drivers/usb/musb/musb_host.c

1162

musb_dbg(musb, "ep0 STATUS, csr %04x", csr);

drivers/usb/musb/musb_host.c

1165

musb_writew(epio, MUSB_CSR0, csr);

drivers/usb/musb/musb_host.c

125

u16 csr;

drivers/usb/musb/musb_host.c

130

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

131

if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))

drivers/usb/musb/musb_host.c

134

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

139

ep->epnum, csr);

drivers/usb/musb/musb_host.c

2317

u16 csr;

drivers/usb/musb/musb_host.c

2336

csr = musb_h_flush_rxfifo(ep, 0);

drivers/usb/musb/musb_host.c

2343

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

2344

csr &= ~(MUSB_TXCSR_AUTOSET

drivers/usb/musb/musb_host.c

2350

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

2352

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

2354

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

391

static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)

drivers/usb/musb/musb_host.c

397

csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;

drivers/usb/musb/musb_host.c

398

csr &= ~(MUSB_RXCSR_H_REQPKT

drivers/usb/musb/musb_host.c

403

musb_writew(hw_ep->regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_host.c

404

musb_writew(hw_ep->regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_host.c

418

u16 csr;

drivers/usb/musb/musb_host.c

491

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/musb_host.c

492

csr |= MUSB_RXCSR_H_WZC_BITS;

drivers/usb/musb/musb_host.c

494

musb_h_flush_rxfifo(hw_ep, csr);

drivers/usb/musb/musb_host.c

497

csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);

drivers/usb/musb/musb_host.c

499

csr |= MUSB_RXCSR_H_REQPKT;

drivers/usb/musb/musb_host.c

500

musb_writew(epio, MUSB_RXCSR, csr);

drivers/usb/musb/musb_host.c

518

u16 csr;

drivers/usb/musb/musb_host.c

527

csr = musb_readw(ep->regs, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

528

if (csr & MUSB_TXCSR_MODE) {

drivers/usb/musb/musb_host.c

530

csr = musb_readw(ep->regs, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

532

csr | MUSB_TXCSR_FRCDATATOG);

drivers/usb/musb/musb_host.c

539

if (csr & MUSB_TXCSR_DMAMODE)

drivers/usb/musb/musb_host.c

545

csr = musb_readw(ep->regs, MUSB_RXCSR);

drivers/usb/musb/musb_host.c

546

if (csr & MUSB_RXCSR_RXPKTRDY)

drivers/usb/musb/musb_host.c

580

u16 csr;

drivers/usb/musb/musb_host.c

585

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

588

csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;

drivers/usb/musb/musb_host.c

601

csr |= MUSB_TXCSR_AUTOSET;

drivers/usb/musb/musb_host.c

604

csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);

drivers/usb/musb/musb_host.c

605

csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */

drivers/usb/musb/musb_host.c

608

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

653

u16 csr;

drivers/usb/musb/musb_host.c

658

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

659

csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);

drivers/usb/musb/musb_host.c

660

musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);

drivers/usb/musb/musb_host.c

683

u16 csr;

drivers/usb/musb/musb_host.c

697

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

698

csr &= ~MUSB_TXCSR_DMAENAB;

drivers/usb/musb/musb_host.c

699

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

722

u16 csr;

drivers/usb/musb/musb_host.c

726

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

748

csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT

drivers/usb/musb/musb_host.c

756

csr |= MUSB_TXCSR_MODE;

drivers/usb/musb/musb_host.c

759

csr |= musb->io.set_toggle(qh, is_out, urb);

drivers/usb/musb/musb_host.c

761

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

763

csr &= ~MUSB_TXCSR_DMAMODE;

drivers/usb/musb/musb_host.c

764

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

765

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

840

u16 csr = 0;

drivers/usb/musb/musb_host.c

844

csr |= musb->io.set_toggle(qh, is_out, urb);

drivers/usb/musb/musb_host.c

847

csr |= MUSB_RXCSR_DISNYET;

drivers/usb/musb/musb_host.c

850

csr = musb_readw(hw_ep->regs, MUSB_RXCSR);

drivers/usb/musb/musb_host.c

852

if (csr & (MUSB_RXCSR_RXPKTRDY

drivers/usb/musb/musb_host.c

856

hw_ep->epnum, csr);

drivers/usb/musb/musb_host.c

859

csr &= MUSB_RXCSR_DISNYET;

drivers/usb/musb/musb_host.c

870

musb_writew(hw_ep->regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_host.c

871

csr = musb_readw(hw_ep->regs, MUSB_RXCSR);

drivers/usb/musb/musb_host.c

886

csr |= MUSB_RXCSR_DMAENAB;

drivers/usb/musb/musb_host.c

889

csr |= MUSB_RXCSR_H_REQPKT;

drivers/usb/musb/musb_host.c

890

musb_dbg(musb, "RXCSR%d := %04x", epnum, csr);

drivers/usb/musb/musb_host.c

891

musb_writew(hw_ep->regs, MUSB_RXCSR, csr);

drivers/usb/musb/musb_host.c

892

csr = musb_readw(hw_ep->regs, MUSB_RXCSR);

drivers/usb/musb/musb_host.c

91

u16 csr;

drivers/usb/musb/musb_host.c

94

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musb_host.c

95

while (csr & MUSB_TXCSR_FIFONOTEMPTY) {

drivers/usb/musb/musb_host.c

96

csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;

drivers/usb/musb/musb_host.c

97

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/musb_host.c

98

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/musbhsdma.c

152

u16 csr = 0;

drivers/usb/musb/musbhsdma.c

158

csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;

drivers/usb/musb/musbhsdma.c

161

csr |= MUSB_HSDMA_BURSTMODE_INCR16

drivers/usb/musb/musbhsdma.c

164

csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)

drivers/usb/musb/musbhsdma.c

178

csr);

drivers/usb/musb/musbhsdma.c

228

u16 csr;

drivers/usb/musb/musbhsdma.c

239

csr = musb_readw(mbase, offset);

drivers/usb/musb/musbhsdma.c

240

csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);

drivers/usb/musb/musbhsdma.c

241

musb_writew(mbase, offset, csr);

drivers/usb/musb/musbhsdma.c

242

csr &= ~MUSB_TXCSR_DMAMODE;

drivers/usb/musb/musbhsdma.c

243

musb_writew(mbase, offset, csr);

drivers/usb/musb/musbhsdma.c

248

csr = musb_readw(mbase, offset);

drivers/usb/musb/musbhsdma.c

249

csr &= ~(MUSB_RXCSR_AUTOCLEAR |

drivers/usb/musb/musbhsdma.c

252

musb_writew(mbase, offset, csr);

drivers/usb/musb/musbhsdma.c

283

u16 csr;

drivers/usb/musb/musbhsdma.c

316

csr = musb_readw(mbase,

drivers/usb/musb/musbhsdma.c

320

if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {

drivers/usb/musb/tusb6010_omap.c

166

u16 csr;

drivers/usb/musb/tusb6010_omap.c

171

csr = musb_readw(hw_ep->regs, MUSB_TXCSR);

drivers/usb/musb/tusb6010_omap.c

172

csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY

drivers/usb/musb/tusb6010_omap.c

174

musb_writew(hw_ep->regs, MUSB_TXCSR, csr);

drivers/usb/musb/tusb6010_omap.c

193

u16 csr;

drivers/usb/musb/tusb6010_omap.c

328

csr = musb_readw(hw_ep->regs, MUSB_TXCSR);

drivers/usb/musb/tusb6010_omap.c

329

csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB

drivers/usb/musb/tusb6010_omap.c

331

csr &= ~MUSB_TXCSR_P_UNDERRUN;

drivers/usb/musb/tusb6010_omap.c

332

musb_writew(hw_ep->regs, MUSB_TXCSR, csr);

drivers/usb/musb/tusb6010_omap.c

334

csr = musb_readw(hw_ep->regs, MUSB_RXCSR);

drivers/usb/musb/tusb6010_omap.c

335

csr |= MUSB_RXCSR_DMAENAB;

drivers/usb/musb/tusb6010_omap.c

336

csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);

drivers/usb/musb/tusb6010_omap.c

338

csr | MUSB_RXCSR_P_WZC_BITS);

drivers/usb/musb/ux500_dma.c

213

u16 csr;

drivers/usb/musb/ux500_dma.c

220

csr = musb_readw(epio, MUSB_TXCSR);

drivers/usb/musb/ux500_dma.c

221

csr &= ~(MUSB_TXCSR_AUTOSET |

drivers/usb/musb/ux500_dma.c

224

musb_writew(epio, MUSB_TXCSR, csr);

drivers/usb/musb/ux500_dma.c

226

csr = musb_readw(epio, MUSB_RXCSR);

drivers/usb/musb/ux500_dma.c

227

csr &= ~(MUSB_RXCSR_AUTOCLEAR |

drivers/usb/musb/ux500_dma.c

230

musb_writew(epio, MUSB_RXCSR, csr);

drivers/video/fbdev/leo.c

107

u32 csr;

drivers/video/fbdev/leo.c

128

u32 csr;

drivers/video/fbdev/leo.c

230

val = sbus_readl(&par->lc_ss0_usr->csr);

drivers/video/fbdev/via/via-core.c

169

int csr;

drivers/video/fbdev/via/via-core.c

173

csr = viafb_mmio_read(VDMA_CSR0);

drivers/video/fbdev/via/via-core.c

174

if (csr & VDMA_C_DONE) {

drivers/watchdog/shwdt.c

109

csr = sh_wdt_read_csr();

drivers/watchdog/shwdt.c

110

csr |= WTCSR_TME;

drivers/watchdog/shwdt.c

111

csr &= ~WTCSR_RSTS;

drivers/watchdog/shwdt.c

112

sh_wdt_write_csr(csr);

drivers/watchdog/shwdt.c

115

csr = sh_wdt_read_rstcsr();

drivers/watchdog/shwdt.c

116

csr &= ~RSTCSR_RSTS;

drivers/watchdog/shwdt.c

117

sh_wdt_write_rstcsr(csr);

drivers/watchdog/shwdt.c

128

u8 csr;

drivers/watchdog/shwdt.c

134

csr = sh_wdt_read_csr();

drivers/watchdog/shwdt.c

135

csr &= ~WTCSR_TME;

drivers/watchdog/shwdt.c

136

sh_wdt_write_csr(csr);

drivers/watchdog/shwdt.c

181

u8 csr;

drivers/watchdog/shwdt.c

183

csr = sh_wdt_read_csr();

drivers/watchdog/shwdt.c

184

csr &= ~WTCSR_IOVF;

drivers/watchdog/shwdt.c

185

sh_wdt_write_csr(csr);

drivers/watchdog/shwdt.c

85

u8 csr;

drivers/watchdog/shwdt.c

95

csr = sh_wdt_read_csr();

drivers/watchdog/shwdt.c

96

csr |= WTCSR_WT | clock_division_ratio;

drivers/watchdog/shwdt.c

97

sh_wdt_write_csr(csr);

include/linux/perf/riscv_pmu.h

80

unsigned long riscv_pmu_ctr_read_csr(unsigned long csr);

mm/filemap.c

4718

struct cachestat_range csr;

mm/filemap.c

4725

if (copy_from_user(&csr, cstat_range,

mm/filemap.c

4739

first_index = csr.off >> PAGE_SHIFT;

mm/filemap.c

4741

csr.len == 0 ? ULONG_MAX : (csr.off + csr.len - 1) >> PAGE_SHIFT;

sound/soc/intel/atom/sst/sst_loader.c

101

csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);

sound/soc/intel/atom/sst/sst_loader.c

103

csr.full);

sound/soc/intel/atom/sst/sst_loader.c

56

union config_status_reg_mrfld csr;

sound/soc/intel/atom/sst/sst_loader.c

59

csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);

sound/soc/intel/atom/sst/sst_loader.c

61

dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);

sound/soc/intel/atom/sst/sst_loader.c

63

csr.full |= 0x7;

sound/soc/intel/atom/sst/sst_loader.c

64

sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);

sound/soc/intel/atom/sst/sst_loader.c

65

csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);

sound/soc/intel/atom/sst/sst_loader.c

67

dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);

sound/soc/intel/atom/sst/sst_loader.c

69

csr.full &= ~(0x1);

sound/soc/intel/atom/sst/sst_loader.c

70

sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);

sound/soc/intel/atom/sst/sst_loader.c

72

csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);

sound/soc/intel/atom/sst/sst_loader.c

73

dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);

sound/soc/intel/atom/sst/sst_loader.c

85

union config_status_reg_mrfld csr;

sound/soc/intel/atom/sst/sst_loader.c

88

csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);

sound/soc/intel/atom/sst/sst_loader.c

89

dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);

sound/soc/intel/atom/sst/sst_loader.c

91

csr.full |= 0x7;

sound/soc/intel/atom/sst/sst_loader.c

92

sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);

sound/soc/intel/atom/sst/sst_loader.c

94

csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);

sound/soc/intel/atom/sst/sst_loader.c

95

dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);

sound/soc/intel/atom/sst/sst_loader.c

97

csr.part.xt_snoop = 1;

sound/soc/intel/atom/sst/sst_loader.c

98

csr.full &= ~(0x5);

sound/soc/intel/atom/sst/sst_loader.c

99

sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);

sound/sparc/cs4231.c

1551

u32 csr;

sound/sparc/cs4231.c

1559

csr = sbus_readl(chip->port + APCCSR);

sound/sparc/cs4231.c

1561

sbus_writel(csr, chip->port + APCCSR);

sound/sparc/cs4231.c

1563

if ((csr & APC_PDMA_READY) &&

sound/sparc/cs4231.c

1564

(csr & APC_PLAY_INT) &&

sound/sparc/cs4231.c

1565

(csr & APC_XINT_PNVA) &&

sound/sparc/cs4231.c

1566

!(csr & APC_XINT_EMPT))

sound/sparc/cs4231.c

1569

if ((csr & APC_CDMA_READY) &&

sound/sparc/cs4231.c

1570

(csr & APC_CAPT_INT) &&

sound/sparc/cs4231.c

1571

(csr & APC_XINT_CNVA) &&

sound/sparc/cs4231.c

1572

!(csr & APC_XINT_EMPT))

sound/sparc/cs4231.c

1582

if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))

sound/sparc/cs4231.c

1599

u32 test, csr;

sound/sparc/cs4231.c

1605

csr = sbus_readl(base->regs + APCCSR);

sound/sparc/cs4231.c

1609

if (!(csr & test))

sound/sparc/cs4231.c

1614

if (!(csr & test))

sound/sparc/cs4231.c

1623

u32 csr, test;

sound/sparc/cs4231.c

1627

csr = sbus_readl(base->regs + APCCSR);

sound/sparc/cs4231.c

1634

csr |= test;

sound/sparc/cs4231.c

1635

sbus_writel(csr, base->regs + APCCSR);

sound/sparc/cs4231.c

1640

u32 csr, shift;

sound/sparc/cs4231.c

1654

csr = sbus_readl(base->regs + APCCSR);

sound/sparc/cs4231.c

1659

csr &= ~(APC_CPAUSE << shift);

sound/sparc/cs4231.c

1661

csr |= (APC_CPAUSE << shift);

sound/sparc/cs4231.c

1662

sbus_writel(csr, base->regs + APCCSR);

sound/sparc/cs4231.c

1664

csr |= (APC_CDMA_READY << shift);

sound/sparc/cs4231.c

1666

csr &= ~(APC_CDMA_READY << shift);

sound/sparc/cs4231.c

1667

sbus_writel(csr, base->regs + APCCSR);

tools/arch/riscv/include/asm/csr.h

480

#define csr_swap(csr, val) \

tools/arch/riscv/include/asm/csr.h

483

__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\

tools/arch/riscv/include/asm/csr.h

489

#define csr_read(csr) \

tools/arch/riscv/include/asm/csr.h

492

__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

tools/arch/riscv/include/asm/csr.h

498

#define csr_write(csr, val) \

tools/arch/riscv/include/asm/csr.h

501

__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \

tools/arch/riscv/include/asm/csr.h

506

#define csr_read_set(csr, val) \

tools/arch/riscv/include/asm/csr.h

509

__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\

tools/arch/riscv/include/asm/csr.h

515

#define csr_set(csr, val) \

tools/arch/riscv/include/asm/csr.h

518

__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \

tools/arch/riscv/include/asm/csr.h

523

#define csr_read_clear(csr, val) \

tools/arch/riscv/include/asm/csr.h

526

__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\

tools/arch/riscv/include/asm/csr.h

532

#define csr_clear(csr, val) \

tools/arch/riscv/include/asm/csr.h

535

__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \

tools/lib/perf/mmap.c

417

#define csr_read(csr) \

tools/lib/perf/mmap.c

422

: "i" (csr) : ); \

tools/testing/selftests/kvm/include/loongarch/processor.h

131

#define csr_read(csr) \

tools/testing/selftests/kvm/include/loongarch/processor.h

137

: [reg] "i" (csr) \

tools/testing/selftests/kvm/include/loongarch/processor.h

142

#define csr_write(v, csr) \

tools/testing/selftests/kvm/include/loongarch/processor.h

148

: [reg] "i" (csr) \

tools/testing/selftests/kvm/include/riscv/sbi.h

61

unsigned long csr:12;

tools/testing/selftests/kvm/riscv/get-reg-list.c

322

#define RISCV_CSR_GENERAL(csr) \

tools/testing/selftests/kvm/riscv/get-reg-list.c

323

"KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"

tools/testing/selftests/kvm/riscv/get-reg-list.c

324

#define RISCV_CSR_AIA(csr) \

tools/testing/selftests/kvm/riscv/get-reg-list.c

325

"KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"

tools/testing/selftests/kvm/riscv/get-reg-list.c

326

#define RISCV_CSR_SMSTATEEN(csr) \

tools/testing/selftests/kvm/riscv/get-reg-list.c

327

"KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"

tools/testing/selftests/kvm/riscv/sbi_pmu_test.c

243

counter_val = pmu_csr_read_num(ctrinfo.csr);

tools/testing/selftests/kvm/riscv/sbi_pmu_test.c

461

pmu_csr_read_num(ctrinfo.csr);

tools/testing/selftests/riscv/cfi/cfi_rv_test.h

65

#define csr_read(csr) \

tools/testing/selftests/riscv/cfi/cfi_rv_test.h

68

__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

tools/testing/selftests/riscv/cfi/cfi_rv_test.h

74

#define csr_write(csr, val) \

tools/testing/selftests/riscv/cfi/cfi_rv_test.h

77

__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \