#ifndef _ASM_RISCV_SBI_H
#define _ASM_RISCV_SBI_H
#include <linux/types.h>
#include <linux/cpumask.h>
#include <linux/jump_label.h>
#ifdef CONFIG_RISCV_SBI
enum sbi_ext_id {
#ifdef CONFIG_RISCV_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
SBI_EXT_0_1_CLEAR_IPI = 0x3,
SBI_EXT_0_1_SEND_IPI = 0x4,
SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_SUSP = 0x53555350,
SBI_EXT_PMU = 0x504D55,
SBI_EXT_DBCN = 0x4442434E,
SBI_EXT_STA = 0x535441,
SBI_EXT_NACL = 0x4E41434C,
SBI_EXT_FWFT = 0x46574654,
SBI_EXT_MPXY = 0x4D505859,
SBI_EXT_DBTR = 0x44425452,
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
SBI_EXT_VENDOR_START = 0x09000000,
SBI_EXT_VENDOR_END = 0x09FFFFFF,
};
enum sbi_ext_base_fid {
SBI_EXT_BASE_GET_SPEC_VERSION = 0,
SBI_EXT_BASE_GET_IMP_ID,
SBI_EXT_BASE_GET_IMP_VERSION,
SBI_EXT_BASE_PROBE_EXT,
SBI_EXT_BASE_GET_MVENDORID,
SBI_EXT_BASE_GET_MARCHID,
SBI_EXT_BASE_GET_MIMPID,
};
enum sbi_ext_time_fid {
SBI_EXT_TIME_SET_TIMER = 0,
};
enum sbi_ext_ipi_fid {
SBI_EXT_IPI_SEND_IPI = 0,
};
enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
};
enum sbi_ext_hsm_fid {
SBI_EXT_HSM_HART_START = 0,
SBI_EXT_HSM_HART_STOP,
SBI_EXT_HSM_HART_STATUS,
SBI_EXT_HSM_HART_SUSPEND,
};
enum sbi_hsm_hart_state {
SBI_HSM_STATE_STARTED = 0,
SBI_HSM_STATE_STOPPED,
SBI_HSM_STATE_START_PENDING,
SBI_HSM_STATE_STOP_PENDING,
SBI_HSM_STATE_SUSPENDED,
SBI_HSM_STATE_SUSPEND_PENDING,
SBI_HSM_STATE_RESUME_PENDING,
};
#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
SBI_HSM_SUSP_PLAT_BASE)
#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
SBI_HSM_SUSP_BASE_MASK)
enum sbi_ext_srst_fid {
SBI_EXT_SRST_RESET = 0,
};
enum sbi_srst_reset_type {
SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
SBI_SRST_RESET_TYPE_COLD_REBOOT,
SBI_SRST_RESET_TYPE_WARM_REBOOT,
};
enum sbi_srst_reset_reason {
SBI_SRST_RESET_REASON_NONE = 0,
SBI_SRST_RESET_REASON_SYS_FAILURE,
};
enum sbi_ext_susp_fid {
SBI_EXT_SUSP_SYSTEM_SUSPEND = 0,
};
enum sbi_ext_susp_sleep_type {
SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,
};
enum sbi_ext_pmu_fid {
SBI_EXT_PMU_NUM_COUNTERS = 0,
SBI_EXT_PMU_COUNTER_GET_INFO,
SBI_EXT_PMU_COUNTER_CFG_MATCH,
SBI_EXT_PMU_COUNTER_START,
SBI_EXT_PMU_COUNTER_STOP,
SBI_EXT_PMU_COUNTER_FW_READ,
SBI_EXT_PMU_COUNTER_FW_READ_HI,
SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
SBI_EXT_PMU_EVENT_GET_INFO,
};
union sbi_pmu_ctr_info {
unsigned long value;
struct {
unsigned long csr:12;
unsigned long width:6;
#if __riscv_xlen == 32
unsigned long reserved:13;
#else
unsigned long reserved:45;
#endif
unsigned long type:1;
};
};
struct riscv_pmu_snapshot_data {
u64 ctr_overflow_mask;
u64 ctr_values[64];
u64 reserved[447];
};
struct riscv_pmu_event_info {
u32 event_idx;
u32 output;
u64 event_data;
};
#define RISCV_PMU_EVENT_INFO_OUTPUT_MASK 0x01
#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)
#define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0)
#define RISCV_PMU_RAW_EVENT_IDX 0x20000
#define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000
#define RISCV_PLAT_FW_EVENT 0xFFFF
enum sbi_pmu_hw_generic_events_t {
SBI_PMU_HW_NO_EVENT = 0,
SBI_PMU_HW_CPU_CYCLES = 1,
SBI_PMU_HW_INSTRUCTIONS = 2,
SBI_PMU_HW_CACHE_REFERENCES = 3,
SBI_PMU_HW_CACHE_MISSES = 4,
SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
SBI_PMU_HW_BRANCH_MISSES = 6,
SBI_PMU_HW_BUS_CYCLES = 7,
SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
SBI_PMU_HW_REF_CPU_CYCLES = 10,
SBI_PMU_HW_GENERAL_MAX,
};
enum sbi_pmu_fw_generic_events_t {
SBI_PMU_FW_MISALIGNED_LOAD = 0,
SBI_PMU_FW_MISALIGNED_STORE = 1,
SBI_PMU_FW_ACCESS_LOAD = 2,
SBI_PMU_FW_ACCESS_STORE = 3,
SBI_PMU_FW_ILLEGAL_INSN = 4,
SBI_PMU_FW_SET_TIMER = 5,
SBI_PMU_FW_IPI_SENT = 6,
SBI_PMU_FW_IPI_RCVD = 7,
SBI_PMU_FW_FENCE_I_SENT = 8,
SBI_PMU_FW_FENCE_I_RCVD = 9,
SBI_PMU_FW_SFENCE_VMA_SENT = 10,
SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
SBI_PMU_FW_MAX,
};
enum sbi_pmu_event_type {
SBI_PMU_EVENT_TYPE_HW = 0x0,
SBI_PMU_EVENT_TYPE_CACHE = 0x1,
SBI_PMU_EVENT_TYPE_RAW = 0x2,
SBI_PMU_EVENT_TYPE_RAW_V2 = 0x3,
SBI_PMU_EVENT_TYPE_FW = 0xf,
};
enum sbi_pmu_ctr_type {
SBI_PMU_CTR_TYPE_HW = 0x0,
SBI_PMU_CTR_TYPE_FW,
};
#define SBI_PMU_EVENT_IDX_OFFSET 20
#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
#define SBI_PMU_EVENT_RAW_IDX 0x20000
#define SBI_PMU_FIXED_CTR_MASK 0x07
#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8
#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
#define SBI_PMU_STOP_FLAG_RESET BIT(0)
#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
enum sbi_ext_dbcn_fid {
SBI_EXT_DBCN_CONSOLE_WRITE = 0,
SBI_EXT_DBCN_CONSOLE_READ = 1,
SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
};
enum sbi_ext_sta_fid {
SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0,
};
struct sbi_sta_struct {
__le32 sequence;
__le32 flags;
__le64 steal;
u8 preempted;
u8 pad[47];
} __packed;
#define SBI_SHMEM_DISABLE -1
enum sbi_ext_nacl_fid {
SBI_EXT_NACL_PROBE_FEATURE = 0x0,
SBI_EXT_NACL_SET_SHMEM = 0x1,
SBI_EXT_NACL_SYNC_CSR = 0x2,
SBI_EXT_NACL_SYNC_HFENCE = 0x3,
SBI_EXT_NACL_SYNC_SRET = 0x4,
};
enum sbi_ext_nacl_feature {
SBI_NACL_FEAT_SYNC_CSR = 0x0,
SBI_NACL_FEAT_SYNC_HFENCE = 0x1,
SBI_NACL_FEAT_SYNC_SRET = 0x2,
SBI_NACL_FEAT_AUTOSWAP_CSR = 0x3,
};
#define SBI_NACL_SHMEM_ADDR_SHIFT 12
#define SBI_NACL_SHMEM_SCRATCH_OFFSET 0x0000
#define SBI_NACL_SHMEM_SCRATCH_SIZE 0x1000
#define SBI_NACL_SHMEM_SRET_OFFSET 0x0000
#define SBI_NACL_SHMEM_SRET_SIZE 0x0200
#define SBI_NACL_SHMEM_AUTOSWAP_OFFSET (SBI_NACL_SHMEM_SRET_OFFSET + \
SBI_NACL_SHMEM_SRET_SIZE)
#define SBI_NACL_SHMEM_AUTOSWAP_SIZE 0x0080
#define SBI_NACL_SHMEM_UNUSED_OFFSET (SBI_NACL_SHMEM_AUTOSWAP_OFFSET + \
SBI_NACL_SHMEM_AUTOSWAP_SIZE)
#define SBI_NACL_SHMEM_UNUSED_SIZE 0x0580
#define SBI_NACL_SHMEM_HFENCE_OFFSET (SBI_NACL_SHMEM_UNUSED_OFFSET + \
SBI_NACL_SHMEM_UNUSED_SIZE)
#define SBI_NACL_SHMEM_HFENCE_SIZE 0x0780
#define SBI_NACL_SHMEM_DBITMAP_OFFSET (SBI_NACL_SHMEM_HFENCE_OFFSET + \
SBI_NACL_SHMEM_HFENCE_SIZE)
#define SBI_NACL_SHMEM_DBITMAP_SIZE 0x0080
#define SBI_NACL_SHMEM_CSR_OFFSET (SBI_NACL_SHMEM_DBITMAP_OFFSET + \
SBI_NACL_SHMEM_DBITMAP_SIZE)
#define SBI_NACL_SHMEM_CSR_SIZE ((__riscv_xlen / 8) * 1024)
#define SBI_NACL_SHMEM_SIZE (SBI_NACL_SHMEM_CSR_OFFSET + \
SBI_NACL_SHMEM_CSR_SIZE)
#define SBI_NACL_SHMEM_CSR_INDEX(__csr_num) \
((((__csr_num) & 0xc00) >> 2) | ((__csr_num) & 0xff))
#define SBI_NACL_SHMEM_HFENCE_ENTRY_SZ ((__riscv_xlen / 8) * 4)
#define SBI_NACL_SHMEM_HFENCE_ENTRY_MAX \
(SBI_NACL_SHMEM_HFENCE_SIZE / \
SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
#define SBI_NACL_SHMEM_HFENCE_ENTRY(__num) \
(SBI_NACL_SHMEM_HFENCE_OFFSET + \
(__num) * SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
#define SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(__num) \
SBI_NACL_SHMEM_HFENCE_ENTRY(__num)
#define SBI_NACL_SHMEM_HFENCE_ENTRY_PNUM(__num)\
(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + (__riscv_xlen / 8))
#define SBI_NACL_SHMEM_HFENCE_ENTRY_PCOUNT(__num)\
(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + \
((__riscv_xlen / 8) * 3))
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS 1
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT \
(__riscv_xlen - SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND \
(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK << \
SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS 3
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS 4
#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA 0x0
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_ALL 0x1
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID 0x2
#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID_ALL 0x3
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA 0x4
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ALL 0x5
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID 0x6
#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID_ALL 0x7
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS 1
#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS 7
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_SHIFT \
(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT - \
SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_ORDER_BASE 12
#if __riscv_xlen == 32
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 9
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 7
#else
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 16
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 14
#endif
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_SHIFT \
SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS
#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS) - 1)
#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_MASK \
((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS) - 1)
#define SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS BIT(0)
#define SBI_NACL_SHMEM_AUTOSWAP_HSTATUS ((__riscv_xlen / 8) * 1)
#define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
#define SBI_NACL_SHMEM_SRET_X_LAST 31
#define SBI_EXT_FWFT_SET 0x0
#define SBI_EXT_FWFT_GET 0x1
enum sbi_fwft_feature_t {
SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0,
SBI_FWFT_LANDING_PAD = 0x1,
SBI_FWFT_SHADOW_STACK = 0x2,
SBI_FWFT_DOUBLE_TRAP = 0x3,
SBI_FWFT_PTE_AD_HW_UPDATING = 0x4,
SBI_FWFT_POINTER_MASKING_PMLEN = 0x5,
SBI_FWFT_LOCAL_RESERVED_START = 0x6,
SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff,
SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000,
SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff,
SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000,
SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff,
SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000,
SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff,
};
#define SBI_FWFT_PLATFORM_FEATURE_BIT BIT(30)
#define SBI_FWFT_GLOBAL_FEATURE_BIT BIT(31)
#define SBI_FWFT_SET_FLAG_LOCK BIT(0)
enum sbi_ext_mpxy_fid {
SBI_EXT_MPXY_GET_SHMEM_SIZE,
SBI_EXT_MPXY_SET_SHMEM,
SBI_EXT_MPXY_GET_CHANNEL_IDS,
SBI_EXT_MPXY_READ_ATTRS,
SBI_EXT_MPXY_WRITE_ATTRS,
SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS,
};
enum sbi_mpxy_attribute_id {
SBI_MPXY_ATTR_MSG_PROT_ID = 0x00000000,
SBI_MPXY_ATTR_MSG_PROT_VER = 0x00000001,
SBI_MPXY_ATTR_MSG_MAX_LEN = 0x00000002,
SBI_MPXY_ATTR_MSG_SEND_TIMEOUT = 0x00000003,
SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT = 0x00000004,
SBI_MPXY_ATTR_CHANNEL_CAPABILITY = 0x00000005,
SBI_MPXY_ATTR_SSE_EVENT_ID = 0x00000006,
SBI_MPXY_ATTR_MSI_CONTROL = 0x00000007,
SBI_MPXY_ATTR_MSI_ADDR_LO = 0x00000008,
SBI_MPXY_ATTR_MSI_ADDR_HI = 0x00000009,
SBI_MPXY_ATTR_MSI_DATA = 0x0000000A,
SBI_MPXY_ATTR_EVENTS_STATE_CONTROL = 0x0000000B,
SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
SBI_MPXY_ATTR_MSGPROTO_ATTR_START = 0x80000000,
SBI_MPXY_ATTR_MSGPROTO_ATTR_END = 0xffffffff
};
enum sbi_mpxy_msgproto_id {
SBI_MPXY_MSGPROTO_RPMI_ID = 0x0,
};
enum sbi_mpxy_rpmi_attribute_id {
SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
SBI_MPXY_RPMI_ATTR_IMPL_ID,
SBI_MPXY_RPMI_ATTR_IMPL_VERSION,
SBI_MPXY_RPMI_ATTR_MAX_ID
};
#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver) upper_16_bits(__ver)
#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver) lower_16_bits(__ver)
#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min) (((u32)(__maj) << 16) | (u16)(__min))
#define SBI_MPXY_CHAN_CAP_MSI BIT(0)
#define SBI_MPXY_CHAN_CAP_SSE BIT(1)
#define SBI_MPXY_CHAN_CAP_EVENTS_STATE BIT(2)
#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP BIT(3)
#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP BIT(4)
#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS BIT(5)
enum sbi_ext_dbtr_fid {
SBI_EXT_DBTR_NUM_TRIGGERS = 0,
SBI_EXT_DBTR_SETUP_SHMEM,
SBI_EXT_DBTR_TRIG_READ,
SBI_EXT_DBTR_TRIG_INSTALL,
SBI_EXT_DBTR_TRIG_UPDATE,
SBI_EXT_DBTR_TRIG_UNINSTALL,
SBI_EXT_DBTR_TRIG_ENABLE,
SBI_EXT_DBTR_TRIG_DISABLE,
};
struct sbi_dbtr_data_msg {
unsigned long tstate;
unsigned long tdata1;
unsigned long tdata2;
unsigned long tdata3;
};
struct sbi_dbtr_id_msg {
unsigned long idx;
};
union sbi_dbtr_shmem_entry {
struct sbi_dbtr_data_msg data;
struct sbi_dbtr_id_msg id;
};
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
#define SBI_SUCCESS 0
#define SBI_ERR_FAILURE -1
#define SBI_ERR_NOT_SUPPORTED -2
#define SBI_ERR_INVALID_PARAM -3
#define SBI_ERR_DENIED -4
#define SBI_ERR_INVALID_ADDRESS -5
#define SBI_ERR_ALREADY_AVAILABLE -6
#define SBI_ERR_ALREADY_STARTED -7
#define SBI_ERR_ALREADY_STOPPED -8
#define SBI_ERR_NO_SHMEM -9
#define SBI_ERR_INVALID_STATE -10
#define SBI_ERR_BAD_RANGE -11
#define SBI_ERR_TIMEOUT -12
#define SBI_ERR_IO -13
#define SBI_ERR_DENIED_LOCKED -14
extern unsigned long sbi_spec_version;
struct sbiret {
long error;
long value;
};
void sbi_init(void);
long __sbi_base_ecall(int fid);
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
unsigned long arg2, unsigned long arg3,
unsigned long arg4, unsigned long arg5,
int fid, int ext);
#define sbi_ecall(e, f, a0, a1, a2, a3, a4, a5) \
__sbi_ecall(a0, a1, a2, a3, a4, a5, f, e)
#ifdef CONFIG_RISCV_SBI_V01
void sbi_console_putchar(int ch);
int sbi_console_getchar(void);
#else
static inline void sbi_console_putchar(int ch) { }
static inline int sbi_console_getchar(void) { return -ENOENT; }
#endif
long sbi_get_mvendorid(void);
long sbi_get_marchid(void);
long sbi_get_mimpid(void);
void sbi_set_timer(uint64_t stime_value);
void sbi_shutdown(void);
void sbi_send_ipi(unsigned int cpu);
int sbi_remote_fence_i(const struct cpumask *cpu_mask);
int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
unsigned long start,
unsigned long size,
unsigned long asid);
int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
unsigned long start,
unsigned long size);
int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
unsigned long start,
unsigned long size,
unsigned long vmid);
int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
unsigned long start,
unsigned long size);
int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
unsigned long start,
unsigned long size,
unsigned long asid);
long sbi_probe_extension(int ext);
int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags);
int sbi_fwft_set_cpumask(const cpumask_t *mask, u32 feature,
unsigned long value, unsigned long flags);
static inline int sbi_fwft_set_online_cpus(u32 feature, unsigned long value,
unsigned long flags)
{
return sbi_fwft_set_cpumask(cpu_online_mask, feature, value, flags);
}
static inline int sbi_spec_is_0_1(void)
{
return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
}
static inline unsigned long sbi_major_version(void)
{
return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
SBI_SPEC_VERSION_MAJOR_MASK;
}
static inline unsigned long sbi_minor_version(void)
{
return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
}
static inline unsigned long sbi_mk_version(unsigned long major,
unsigned long minor)
{
return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
| (minor & SBI_SPEC_VERSION_MINOR_MASK);
}
static inline int sbi_err_map_linux_errno(int err)
{
switch (err) {
case SBI_SUCCESS:
return 0;
case SBI_ERR_DENIED:
case SBI_ERR_DENIED_LOCKED:
return -EPERM;
case SBI_ERR_INVALID_PARAM:
case SBI_ERR_INVALID_STATE:
return -EINVAL;
case SBI_ERR_BAD_RANGE:
return -ERANGE;
case SBI_ERR_INVALID_ADDRESS:
return -EFAULT;
case SBI_ERR_NO_SHMEM:
return -ENOMEM;
case SBI_ERR_TIMEOUT:
return -ETIMEDOUT;
case SBI_ERR_IO:
return -EIO;
case SBI_ERR_NOT_SUPPORTED:
case SBI_ERR_FAILURE:
default:
return -ENOTSUPP;
};
}
extern bool sbi_debug_console_available;
int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
int sbi_debug_console_read(char *bytes, unsigned int num_bytes);
#else
static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
static inline void sbi_init(void) {}
#endif
unsigned long riscv_get_mvendorid(void);
unsigned long riscv_get_marchid(void);
unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
unsigned long riscv_cached_marchid(unsigned int cpu_id);
unsigned long riscv_cached_mimpid(unsigned int cpu_id);
#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence);
#define riscv_use_sbi_for_rfence() \
static_branch_unlikely(&riscv_sbi_for_rfence)
void sbi_ipi_init(void);
#else
static inline bool riscv_use_sbi_for_rfence(void) { return false; }
static inline void sbi_ipi_init(void) { }
#endif
#endif
