intr_isrc_dispatch
if (intr_isrc_dispatch(&sc->isrcs[irq].isrc,
if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
if (intr_isrc_dispatch(&sc->intr.isrc, curthread->td_intr_frame) != 0) {
if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
if (intr_isrc_dispatch(&bgi->bgi_isrc,
if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc,
if (intr_isrc_dispatch(&bli->bli_isrc, tf) != 0)
if (intr_isrc_dispatch(&irqsrc->isrc, tf))
if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
intr_isrc_dispatch(&isrc, NULL);
if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc,
if (intr_isrc_dispatch(&sirq->isrc, tf) != 0) {
if (intr_isrc_dispatch(&mgi->isrc, tf) != 0) {
if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc,
if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {
if (intr_isrc_dispatch(&aisrc->ai_isrc, tf) != 0) {
intr_isrc_dispatch(&isrcs[AIC_TMR_GUEST_VIRT].ai_isrc, tf);
intr_isrc_dispatch(&isrcs[AIC_TMR_GUEST_PHYS].ai_isrc,
intr_isrc_dispatch(&isrcs[AIC_TMR_HV_PHYS].ai_isrc, tf);
intr_isrc_dispatch(&isrcs[AIC_TMR_HV_VIRT].ai_isrc, tf);
if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
intr_isrc_dispatch(&girq->gi_isrc, tf);
if (intr_isrc_dispatch(&sc->isrcs[pin].isrc, tf) != 0) {
if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) {
if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, pin), tf) != 0)
if (intr_isrc_dispatch(&xi->isrc, tf) != 0) {
if (intr_isrc_dispatch(&src->isrc, tf) != 0)
if (intr_isrc_dispatch(&src->isrc, frame) != 0) {
if (intr_isrc_dispatch(&src->isrc, tf) != 0)
err = intr_isrc_dispatch(&irq->isrc, tf);
int intr_isrc_dispatch(struct intr_irqsrc *, struct trapframe *);