bus_write_2
bus_write_2(sc->base.base.res, offset, htole16(val));
bus_write_2(sc->sc_res[MEMRES], offs, val);
bus_write_2(sc->mem_res, off, val);
bus_write_2((_sc)->sc_mem_res, reg, value);
bus_write_2((_sc)->sc_mem_res, reg, value)
bus_write_2(sc->mem_res, slot->bd_offset + 14, val)
bus_write_2(sc->sc_mem_res, off, val);
bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
bus_write_2((sc)->mem[0], (reg), (val))
bus_write_2((_sc)->age_res[0], (reg), (val))
bus_write_2((res), (offset), (value))
bus_write_2((_sc)->alc_res[0], (reg), (val))
bus_write_2((_sc)->ale_res[0], (reg), (val))
(bus_write_2(amdpm->res, register, value))
bus_write_2((res), (offset), (value))
bus_write_2((_pdata)->xpcs_res, (_off), _val)
bus_write_2((_pdata)->sir0_res, _reg, (_val))
bus_write_2((_pdata)->sir1_res, _reg, (_val))
bus_write_2((_pdata)->rxtx_res, _reg, (_val))
bus_write_2((r)->res, (o), (v)) : \
return (bus_write_2(r, res_offset, value));
bus_write_2(r, r_offset, value);
(bus_write_2((mac)->mac_sc->sc_mem_res, (o), (v)))
bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value)
bus_write_2(sc->mem_res, off, val);
#define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val)
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
bus_write_2(sc->res, WDT_RELOAD_REG, WDT_RELOAD);
bus_write_2(sc->res, WDT_RELOAD_REG, WDT_RELOAD);
bus_write_2(sc->res, WDT_RELOAD_REG, WDT_RELOAD | WDT_TIMEOUT);
bus_write_2(sc->res, WDT_RELOAD_REG, WDT_UNLOCK_SEQ_1_VAL);
bus_write_2(sc->res, WDT_RELOAD_REG, WDT_UNLOCK_SEQ_2_VAL);
bus_write_2((sc)->tco_res, (off), (val))
bus_write_2((ida)->regs, port, val)
#define WR2(sc, off, val) (bus_write_2((sc)->mem_res, (off), (val)))
#define ips_write_2(sc,offset,value) bus_write_2(sc->iores, offset, value)
#define BXW2(isp, off, v) bus_write_2((isp)->isp_regs, (off), (v))
bus_write_2((sc)->msk_res[0], (reg), (val))
bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
bus_write_2((res), (offset), (value))
bus_write_2(res, UHCI_INTR, 0);
bus_write_2(sc->dbi_res, reg, val);
bus_write_2(res, reg, val);
bus_write_2(sc->res, offset, htole16(val));
bus_write_2(res, offset, pbi->pbi_value);
bus_write_2(r->r_d.res, ofs, buf.x2[0]);
bus_write_2(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
bus_write_2(sc->mem_res, off, val);
bus_write_2(sc->mem_res[slot->num], off, val);
bus_write_2(sc->mem_res[slot->num], off, val);
bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);
bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);
bus_write_2(sc->mem_res, off, val);
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)
bus_write_2((res), (offset), (value))
bus_write_2((sc)->sk_res[0], (reg), (val))
bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
bus_write_2(sc->smc_reg, offset, val);
bus_write_2(reg, BSR, 0);
bus_write_2(reg, BSR, 1);
bus_write_2(reg, BSR, 3);
bus_write_2((sc)->ste_res, reg, val)
bus_write_2((_sc)->sc_res[0], (reg), (val))
#define OUTW_OFF(o, v) bus_write_2(np->io_res, (o), (v))
#define OUTW_OFF(o, v) bus_write_2(np->mmio_res, (o), (v))
bus_write_2(sc->vge_res, reg, val)
bus_write_2((sc)->res[0], (o), (v))
bus_write_2((sc)->vtpci_res, (o), (htole16(v)))
bus_write_2((sc)->vtpci_res, (o), (v))
bus_write_2(&sc->vtpci_common_res_map.vtrm_map,
bus_write_2(&sc->vtpci_notify_res_map.vtrm_map, off, val);
bus_write_2(&sc->vtpci_device_res_map.vtrm_map, off, val);
return (bus_write_2(sc->vmd_regs_res[0], offset, val));
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val)
bus_write_2((_sc)->vte_res, (reg), (val))
bus_write_2(sc->sc_mem, CPLD_MEM_ADDR, addr);
bus_write_2(sc->sc_mem, CPLD_MEM_DATA, data);
bus_write_2(sc->sc_mem, CPLD_MEM_ADDR, addr);
bus_write_2(sc->cfg_mem_res, offset, htole16(val));
int bus_write_2(int rid, long ofs, uint16_t val);
{ "write_2", bus_write_2, METH_VARARGS, "Write a 2-byte data item." },