sys/arm/allwinner/aw_sid.c
371
WR4(sc, SID_PRCTL, val);
sys/arm/allwinner/aw_thermal.c
402
WR4(sc, THS_CALIB0, calib[0]);
sys/arm/allwinner/aw_thermal.c
404
WR4(sc, THS_CALIB1, calib[1]);
sys/arm/allwinner/aw_thermal.c
407
WR4(sc, THS_CTRL1, ADC_CALI_EN);
sys/arm/allwinner/aw_thermal.c
408
WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time);
sys/arm/allwinner/aw_thermal.c
409
WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT);
sys/arm/allwinner/aw_thermal.c
412
WR4(sc, THS_INTC, sc->conf->thermal_per << THS_THERMAL_PER_SHIFT);
sys/arm/allwinner/aw_thermal.c
415
WR4(sc, THS_FILTER, sc->conf->filter);
sys/arm/allwinner/aw_thermal.c
418
WR4(sc, THS_INTS, RD4(sc, THS_INTS));
sys/arm/allwinner/aw_thermal.c
419
WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL);
sys/arm/allwinner/aw_thermal.c
422
WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);
sys/arm/allwinner/aw_thermal.c
456
WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val);
sys/arm/allwinner/aw_thermal.c
489
WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val);
sys/arm/allwinner/aw_thermal.c
576
WR4(sc, THS_INTS, ints);
sys/arm/allwinner/aw_usb3phy.c
129
WR4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL, val);
sys/arm/allwinner/aw_usb3phy.c
135
WR4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL, val);
sys/arm/allwinner/aw_usb3phy.c
141
WR4(sc->res, USB3PHY_APP, val);
sys/arm/allwinner/aw_usb3phy.c
143
WR4(sc->res, USB3PHY_PHY_TUNE_LOW, PTL_MAGIC);
sys/arm/allwinner/aw_usb3phy.c
156
WR4(sc->res, USB3PHY_PHY_TUNE_HIGH, val);
sys/arm/allwinner/aw_usbphy.c
182
#define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
sys/arm/allwinner/aw_usbphy.c
183
#define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
sys/arm/allwinner/if_awg.c
1328
WR4(sc, EMAC_INT_STA, val);
sys/arm/allwinner/if_awg.c
1370
WR4(sc, EMAC_INT_STA, val);
sys/arm/allwinner/if_awg.c
1856
WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
sys/arm/allwinner/if_awg.c
243
WR4(sc, EMAC_MII_CMD,
sys/arm/allwinner/if_awg.c
271
WR4(sc, EMAC_MII_DATA, val);
sys/arm/allwinner/if_awg.c
272
WR4(sc, EMAC_MII_CMD,
sys/arm/allwinner/if_awg.c
338
WR4(sc, EMAC_BASIC_CTL_0, val);
sys/arm/allwinner/if_awg.c
344
WR4(sc, EMAC_RX_CTL_0, val);
sys/arm/allwinner/if_awg.c
352
WR4(sc, EMAC_TX_FLOW_CTL, val);
sys/arm/allwinner/if_awg.c
448
WR4(sc, EMAC_ADDR_HIGH(0), machi);
sys/arm/allwinner/if_awg.c
449
WR4(sc, EMAC_ADDR_LOW(0), maclo);
sys/arm/allwinner/if_awg.c
452
WR4(sc, EMAC_RX_HASH_0, hash[1]);
sys/arm/allwinner/if_awg.c
453
WR4(sc, EMAC_RX_HASH_1, hash[0]);
sys/arm/allwinner/if_awg.c
456
WR4(sc, EMAC_RX_FRM_FLT, val);
sys/arm/allwinner/if_awg.c
469
WR4(sc, EMAC_BASIC_CTL_1, val);
sys/arm/allwinner/if_awg.c
490
WR4(sc, EMAC_TX_CTL_0, tx);
sys/arm/allwinner/if_awg.c
491
WR4(sc, EMAC_RX_CTL_0, rx);
sys/arm/allwinner/if_awg.c
542
WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
sys/arm/allwinner/if_awg.c
549
WR4(sc, EMAC_INT_EN, 0);
sys/arm/allwinner/if_awg.c
571
WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
sys/arm/allwinner/if_awg.c
575
WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
sys/arm/allwinner/if_awg.c
589
WR4(sc, EMAC_TX_CTL_1, val);
sys/arm/allwinner/if_awg.c
596
WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
sys/arm/allwinner/if_awg.c
600
WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
sys/arm/allwinner/if_awg.c
937
WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
sys/arm/allwinner/if_awg.c
938
WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
sys/arm/allwinner/if_awg.c
952
WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
507
WR4(sc, off & ~3, val32);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
546
WR4(sc, SDHCI_BLOCK_SIZE, sc->blksz_and_count);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
552
WR4(sc, off & ~3, val32);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
561
WR4(sc, off, val);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1050
WR4(sc, HC_HOSTCONFIG, val2);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1122
WR4(sc, HC_CLOCKDIVISOR, val2);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1163
WR4(sc, HC_ARGUMENT, val2);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1185
WR4(sc, HC_HOSTCONFIG, hstcfg);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
279
WR4(sc, off & ~3, val32);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
290
WR4(sc, off & ~3, val32);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
346
WR4(sc, HC_POWER, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
348
WR4(sc, HC_COMMAND, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
349
WR4(sc, HC_ARGUMENT, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
350
WR4(sc, HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
351
WR4(sc, HC_CLOCKDIVISOR, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
352
WR4(sc, HC_HOSTSTATUS, HC_HSTST_RESET);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
353
WR4(sc, HC_HOSTCONFIG, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
354
WR4(sc, HC_BLOCKSIZE, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
355
WR4(sc, HC_BLOCKCOUNT, 0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
362
WR4(sc, HC_DEBUG, dbg);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
366
WR4(sc, HC_POWER, 1);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
373
WR4(sc, HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_MAXVAL);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
374
WR4(sc, HC_HOSTCONFIG, HC_HSTCF_INT_BUSY);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
533
WR4(sc, HC_ARGUMENT, sc->sdcard_rca << 16);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
534
WR4(sc, HC_COMMAND,
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
615
WR4(sc, HC_ARGUMENT, 0x00000000);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
616
WR4(sc, HC_COMMAND,
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
639
WR4(sc, HC_HOSTSTATUS,
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
722
WR4(sc, HC_ARGUMENT, sc->sdhci_blockcount);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
723
WR4(sc, HC_COMMAND, MMC_SET_BLOCK_COUNT | HC_CMD_ENABLE);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
733
WR4(sc, HC_ARGUMENT, save_sdarg);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
740
WR4(sc, HC_COMMAND, val2);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
747
WR4(sc, HC_HOSTCONFIG, hstcfg);
sys/arm/freescale/imx/imx6_ccm.c
100
WR4(sc, CCM_CCGR1, reg);
sys/arm/freescale/imx/imx6_ccm.c
107
WR4(sc, CCM_CCGR2, reg);
sys/arm/freescale/imx/imx6_ccm.c
112
WR4(sc, CCM_CCGR3, reg);
sys/arm/freescale/imx/imx6_ccm.c
117
WR4(sc, CCM_CCGR4, reg);
sys/arm/freescale/imx/imx6_ccm.c
122
WR4(sc, CCM_CCGR5, reg);
sys/arm/freescale/imx/imx6_ccm.c
127
WR4(sc, CCM_CCGR6, reg);
sys/arm/freescale/imx/imx6_ccm.c
179
WR4(sc, CCM_CGPR, reg);
sys/arm/freescale/imx/imx6_ccm.c
182
WR4(sc, CCM_CLPCR, reg);
sys/arm/freescale/imx/imx6_ccm.c
231
WR4(sc, CCM_CSCMR1, reg);
sys/arm/freescale/imx/imx6_ccm.c
250
WR4(sc, CCM_CS1CDR, reg);
sys/arm/freescale/imx/imx6_ccm.c
260
WR4(sc, CCM_CS2CDR, reg);
sys/arm/freescale/imx/imx6_ccm.c
271
WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
sys/arm/freescale/imx/imx6_ccm.c
325
WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
sys/arm/freescale/imx/imx6_ccm.c
330
WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
sys/arm/freescale/imx/imx6_ccm.c
345
WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
sys/arm/freescale/imx/imx6_ccm.c
348
WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
sys/arm/freescale/imx/imx6_ccm.c
403
WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);
sys/arm/freescale/imx/imx6_ccm.c
413
WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);
sys/arm/freescale/imx/imx6_ccm.c
415
WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO_NUM, 11);
sys/arm/freescale/imx/imx6_ccm.c
416
WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO_DENOM, 12);
sys/arm/freescale/imx/imx6_ccm.c
421
WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);
sys/arm/freescale/imx/imx6_ccm.c
436
WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);
sys/arm/freescale/imx/imx6_ccm.c
453
WR4(sc, CCM_CCGR3, reg);
sys/arm/freescale/imx/imx6_ccm.c
461
WR4(sc, CCM_CHSCCDR, reg);
sys/arm/freescale/imx/imx6_ccm.c
464
WR4(sc, CCM_CHSCCDR, reg);
sys/arm/freescale/imx/imx6_ccm.c
483
WR4(sc, CCM_CCGR2, reg);
sys/arm/freescale/imx/imx6_ccm.c
497
WR4(ccm_sc, CCM_CACCR, divisor);
sys/arm/freescale/imx/imx6_ccm.c
95
WR4(sc, CCM_CCGR0, reg);
sys/arm/freescale/imx/imx6_snvs.c
102
WR4(sc, SNVS_LPCR, sc->lpcr);
sys/arm/freescale/imx/imx6_snvs.c
161
WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32)));
sys/arm/freescale/imx/imx6_snvs.c
162
WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB)));
sys/arm/freescale/imx/imx6_src.c
81
WR4(src_sc, SRC_SCR, reg);
sys/arm/freescale/imx/imx_epit.c
201
WR4(sc, EPIT_LR, 0xffffffff);
sys/arm/freescale/imx/imx_epit.c
202
WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
sys/arm/freescale/imx/imx_epit.c
232
WR4(sc, EPIT_CR, sc->ctlreg);
sys/arm/freescale/imx/imx_epit.c
233
WR4(sc, EPIT_SR, EPIT_SR_OCIF);
sys/arm/freescale/imx/imx_epit.c
245
WR4(sc, EPIT_LR, ticks);
sys/arm/freescale/imx/imx_epit.c
259
WR4(sc, EPIT_CR, sc->ctlreg);
sys/arm/freescale/imx/imx_epit.c
284
WR4(sc, EPIT_CR, sc->ctlreg);
sys/arm/freescale/imx/imx_epit.c
448
WR4(sc, EPIT_CR, 0);
sys/arm/freescale/imx/imx_iomux.c
141
WR4(sc, reg, val);
sys/arm/freescale/imx/imx_iomux.c
163
WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
sys/arm/freescale/imx/imx_iomux.c
166
WR4(sc, cfg->padconf_reg, cfg->padconf_val);
sys/arm/freescale/imx/imx_iomux.c
287
WR4(iomux_sc, regaddr, val);
sys/arm/freescale/imx/imx_iomux.c
304
WR4(iomux_sc, regaddr, val);
sys/arm/freescale/imx/imx_spi.c
240
WR4(sc, ECSPI_CTLREG, sc->ctlreg);
sys/arm/freescale/imx/imx_spi.c
256
WR4(sc, ECSPI_CFGREG, reg);
sys/arm/freescale/imx/imx_spi.c
263
WR4(sc, ECSPI_DMAREG, reg);
sys/arm/freescale/imx/imx_spi.c
287
WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]);
sys/arm/freescale/imx/imx_spi.c
310
WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */
sys/arm/freescale/imx/imx_spi.c
358
WR4(sc, ECSPI_INTREG, sc->intreg);
sys/arm/freescale/imx/imx_spi.c
395
WR4(sc, ECSPI_INTREG, sc->intreg);
sys/arm/freescale/imx/imx_spi.c
448
WR4(sc, ECSPI_CTLREG, 0);
sys/arm/freescale/imx/imx_spi.c
555
WR4(sc, ECSPI_CTLREG, CTLREG_CMODES_MASTER);
sys/arm/mv/clk/armada38x_gateclk.c
241
WR4(sc, addr, val);
sys/arm/mv/clk/armada38x_gateclk.c
270
WR4(sc, addr, reg);
sys/arm/mv/mv_ap806_sei.c
123
WR4(sc, GICP_SEMR(sisrc->irq), tmp);
sys/arm/mv/mv_ap806_sei.c
132
WR4(sc, GICP_SECR(sisrc->irq), GICP_SECR_BIT(sisrc->irq));
sys/arm/mv/mv_ap806_sei.c
353
WR4(sc, GICP_SEMR0, 0xFFFFFFFF);
sys/arm/mv/mv_ap806_sei.c
354
WR4(sc, GICP_SEMR1, 0xFFFFFFFF);
sys/arm/mv/mv_cp110_clock.c
291
WR4(sc, addr, val);
sys/arm/mv/mv_cp110_clock.c
317
WR4(sc, addr, reg);
sys/arm/mv/mv_cp110_icu.c
161
WR4(sc, ICU_INT_CFG(i), 0);
sys/arm/mv/mv_cp110_icu.c
249
WR4(sc, ICU_SETSPI_NSR_AL, addr & UINT32_MAX);
sys/arm/mv/mv_cp110_icu.c
250
WR4(sc, ICU_SETSPI_NSR_AH, (addr >> 32) & UINT32_MAX);
sys/arm/mv/mv_cp110_icu.c
252
WR4(sc, ICU_CLRSPI_NSR_AL, addr & UINT32_MAX);
sys/arm/mv/mv_cp110_icu.c
253
WR4(sc, ICU_CLRSPI_NSR_AH, (addr >> 32) & UINT32_MAX);
sys/arm/mv/mv_cp110_icu.c
256
WR4(sc, ICU_SETSPI_SEI_AL, addr & UINT32_MAX);
sys/arm/mv/mv_cp110_icu.c
257
WR4(sc, ICU_SETSPI_SEI_AH, (addr >> 32) & UINT32_MAX);
sys/arm/mv/mv_cp110_icu.c
319
WR4(sc, ICU_INT_CFG(irq_no), vector);
sys/arm/mv/mv_cp110_icu.c
329
WR4(sc, ICU_INT_CFG(ICU_INT_SATA1), vector);
sys/arm/mv/mv_cp110_icu.c
331
WR4(sc, ICU_INT_CFG(ICU_INT_SATA0), vector);
sys/arm/mv/mv_cp110_icu.c
365
WR4(sc, ICU_INT_CFG(irq_no), 0);
sys/arm/mv/mv_thermal.c
165
WR4(sc, CONTROL0, reg);
sys/arm/mv/mv_thermal.c
181
WR4(sc, CONTROL0, reg);
sys/arm/mv/mv_thermal.c
187
WR4(sc, CONTROL0, reg);
sys/arm/mv/mv_thermal.c
228
WR4(sc, CONTROL0, reg);
sys/arm/mv/mv_thermal.c
244
WR4(sc, CONTROL1, reg);
sys/arm/mv/mv_thermal.c
249
WR4(sc, CONTROL0, reg);
sys/arm/mv/mvebu_pinctrl.c
120
WR4(sc, offset, reg);
sys/arm/nvidia/drm2/tegra_dc.c
1030
WR4(sc, DC_DISP_CURSOR_START_ADDR, val);
sys/arm/nvidia/drm2/tegra_dc.c
1039
WR4(sc, DC_DISP_BLEND_CURSOR_CONTROL, val);
sys/arm/nvidia/drm2/tegra_dc.c
1043
WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val);
sys/arm/nvidia/drm2/tegra_dc.c
1047
WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val);
sys/arm/nvidia/drm2/tegra_dc.c
1051
WR4(sc, DC_DISP_CURSOR_UNDERFLOW_CTRL, CURSOR_UFLOW_CYA);
sys/arm/nvidia/drm2/tegra_dc.c
1053
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | CURSOR_UPDATE );
sys/arm/nvidia/drm2/tegra_dc.c
1054
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | CURSOR_ACT_REQ);
sys/arm/nvidia/drm2/tegra_dc.c
1066
WR4(sc, DC_DISP_CURSOR_POSITION, CURSOR_POSITION(x, y));
sys/arm/nvidia/drm2/tegra_dc.c
1068
WR4(sc, DC_CMD_STATE_CONTROL, CURSOR_UPDATE);
sys/arm/nvidia/drm2/tegra_dc.c
1069
WR4(sc, DC_CMD_STATE_CONTROL, CURSOR_ACT_REQ);
sys/arm/nvidia/drm2/tegra_dc.c
1126
WR4(sc, DC_CMD_DISPLAY_COMMAND, DISPLAY_CTRL_MODE(val));
sys/arm/nvidia/drm2/tegra_dc.c
1129
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE);
sys/arm/nvidia/drm2/tegra_dc.c
1130
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ);
sys/arm/nvidia/drm2/tegra_dc.c
1146
WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val);
sys/arm/nvidia/drm2/tegra_dc.c
1158
WR4(sc, DC_DISP_DISP_TIMING_OPTIONS, VSYNC_H_POSITION(1));
sys/arm/nvidia/drm2/tegra_dc.c
1159
WR4(sc, DC_DISP_DISP_COLOR_CONTROL,
sys/arm/nvidia/drm2/tegra_dc.c
1162
WR4(sc, DC_DISP_DISP_SIGNAL_OPTIONS0, H_PULSE2_ENABLE);
sys/arm/nvidia/drm2/tegra_dc.c
1163
WR4(sc, DC_DISP_H_PULSE2_CONTROL,
sys/arm/nvidia/drm2/tegra_dc.c
1166
WR4(sc, DC_DISP_H_PULSE2_POSITION_A,
sys/arm/nvidia/drm2/tegra_dc.c
1180
WR4(sc, DC_CMD_INT_STATUS, status);
sys/arm/nvidia/drm2/tegra_dc.c
1209
WR4(sc, DC_CMD_INT_TYPE,
sys/arm/nvidia/drm2/tegra_dc.c
1213
WR4(sc, DC_CMD_INT_POLARITY,
sys/arm/nvidia/drm2/tegra_dc.c
1217
WR4(sc, DC_CMD_INT_ENABLE, 0);
sys/arm/nvidia/drm2/tegra_dc.c
1218
WR4(sc, DC_CMD_INT_MASK, 0);
sys/arm/nvidia/drm2/tegra_dc.c
423
WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val);
sys/arm/nvidia/drm2/tegra_dc.c
426
WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y));
sys/arm/nvidia/drm2/tegra_dc.c
427
WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h));
sys/arm/nvidia/drm2/tegra_dc.c
428
WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size));
sys/arm/nvidia/drm2/tegra_dc.c
431
WR4(sc, DC_WIN_DDA_INCREMENT,
sys/arm/nvidia/drm2/tegra_dc.c
433
WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda);
sys/arm/nvidia/drm2/tegra_dc.c
434
WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda);
sys/arm/nvidia/drm2/tegra_dc.c
437
WR4(sc, DC_WINBUF_START_ADDR, win->base[0]);
sys/arm/nvidia/drm2/tegra_dc.c
439
WR4(sc, DC_WINBUF_START_ADDR_U, win->base[1]);
sys/arm/nvidia/drm2/tegra_dc.c
440
WR4(sc, DC_WINBUF_START_ADDR_V, win->base[2]);
sys/arm/nvidia/drm2/tegra_dc.c
441
WR4(sc, DC_WIN_LINE_STRIDE,
sys/arm/nvidia/drm2/tegra_dc.c
444
WR4(sc, DC_WIN_LINE_STRIDE, win->stride[0]);
sys/arm/nvidia/drm2/tegra_dc.c
448
WR4(sc, DC_WINBUF_ADDR_H_OFFSET, h_offset);
sys/arm/nvidia/drm2/tegra_dc.c
449
WR4(sc, DC_WINBUF_ADDR_V_OFFSET, v_offset);
sys/arm/nvidia/drm2/tegra_dc.c
452
WR4(sc, DC_WIN_COLOR_DEPTH, win->color_mode);
sys/arm/nvidia/drm2/tegra_dc.c
453
WR4(sc, DC_WIN_BYTE_SWAP, win->swap);
sys/arm/nvidia/drm2/tegra_dc.c
459
WR4(sc, DC_WINBUF_SURFACE_KIND, val);
sys/arm/nvidia/drm2/tegra_dc.c
463
WR4(sc, DC_WINC_CSC_YOF, 0x00f0);
sys/arm/nvidia/drm2/tegra_dc.c
464
WR4(sc, DC_WINC_CSC_KYRGB, 0x012a);
sys/arm/nvidia/drm2/tegra_dc.c
465
WR4(sc, DC_WINC_CSC_KUR, 0x0000);
sys/arm/nvidia/drm2/tegra_dc.c
466
WR4(sc, DC_WINC_CSC_KVR, 0x0198);
sys/arm/nvidia/drm2/tegra_dc.c
467
WR4(sc, DC_WINC_CSC_KUG, 0x039b);
sys/arm/nvidia/drm2/tegra_dc.c
468
WR4(sc, DC_WINC_CSC_KVG, 0x032f);
sys/arm/nvidia/drm2/tegra_dc.c
469
WR4(sc, DC_WINC_CSC_KUB, 0x0204);
sys/arm/nvidia/drm2/tegra_dc.c
470
WR4(sc, DC_WINC_CSC_KVB, 0x0000);
sys/arm/nvidia/drm2/tegra_dc.c
484
WR4(sc, DC_WINC_WIN_OPTIONS, val);
sys/arm/nvidia/drm2/tegra_dc.c
488
WR4(sc, DC_WINBUF_UFLOW_CTRL, UFLOW_CTR_ENABLE);
sys/arm/nvidia/drm2/tegra_dc.c
489
WR4(sc, DC_WINBUF_UFLOW_DBG_PIXEL, 0xFFFF0000);
sys/arm/nvidia/drm2/tegra_dc.c
537
WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_UPDATE << plane->index);
sys/arm/nvidia/drm2/tegra_dc.c
538
WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_ACT_REQ << plane->index);
sys/arm/nvidia/drm2/tegra_dc.c
561
WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT << idx);
sys/arm/nvidia/drm2/tegra_dc.c
565
WR4(sc, DC_WINC_WIN_OPTIONS, val);
sys/arm/nvidia/drm2/tegra_dc.c
569
WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_UPDATE << idx);
sys/arm/nvidia/drm2/tegra_dc.c
570
WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_ACT_REQ << idx);
sys/arm/nvidia/drm2/tegra_dc.c
662
WR4(sc, DC_DISP_DISP_TIMING_OPTIONS, 0);
sys/arm/nvidia/drm2/tegra_dc.c
664
WR4(sc, DC_DISP_REF_TO_SYNC,
sys/arm/nvidia/drm2/tegra_dc.c
668
WR4(sc, DC_DISP_SYNC_WIDTH,
sys/arm/nvidia/drm2/tegra_dc.c
672
WR4(sc, DC_DISP_BACK_PORCH,
sys/arm/nvidia/drm2/tegra_dc.c
676
WR4(sc, DC_DISP_FRONT_PORCH,
sys/arm/nvidia/drm2/tegra_dc.c
680
WR4(sc, DC_DISP_DISP_ACTIVE,
sys/arm/nvidia/drm2/tegra_dc.c
683
WR4(sc, DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT(DF1P1C));
sys/arm/nvidia/drm2/tegra_dc.c
685
WR4(sc,DC_DISP_DISP_CLOCK_CONTROL,
sys/arm/nvidia/drm2/tegra_dc.c
727
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE);
sys/arm/nvidia/drm2/tegra_dc.c
728
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ);
sys/arm/nvidia/drm2/tegra_dc.c
743
WR4(sc, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL);
sys/arm/nvidia/drm2/tegra_dc.c
745
WR4(sc, DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE |
sys/arm/nvidia/drm2/tegra_dc.c
748
WR4(sc, DC_CMD_DISPLAY_POWER_CONTROL,
sys/arm/nvidia/drm2/tegra_dc.c
754
WR4(sc, DC_CMD_DISPLAY_COMMAND, val);
sys/arm/nvidia/drm2/tegra_dc.c
756
WR4(sc, DC_CMD_INT_MASK,
sys/arm/nvidia/drm2/tegra_dc.c
760
WR4(sc, DC_CMD_INT_ENABLE,
sys/arm/nvidia/drm2/tegra_dc.c
775
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE);
sys/arm/nvidia/drm2/tegra_dc.c
779
WR4(sc, DC_CMD_INT_MASK, val);
sys/arm/nvidia/drm2/tegra_dc.c
783
WR4(sc, DC_CMD_INT_ENABLE, val);
sys/arm/nvidia/drm2/tegra_dc.c
785
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ);
sys/arm/nvidia/drm2/tegra_dc.c
848
WR4(sc, DC_CMD_INT_MASK, val);
sys/arm/nvidia/drm2/tegra_dc.c
865
WR4(sc, DC_CMD_INT_MASK, val);
sys/arm/nvidia/drm2/tegra_dc.c
892
WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT);
sys/arm/nvidia/drm2/tegra_dc.c
893
WR4(sc, DC_CMD_STATE_ACCESS, READ_MUX);
sys/arm/nvidia/drm2/tegra_dc.c
895
WR4(sc, DC_CMD_STATE_ACCESS, 0);
sys/arm/nvidia/drm2/tegra_dc.c
962
WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE);
sys/arm/nvidia/drm2/tegra_hdmi.c
1165
WR4(sc, HDMI_NV_PDISP_INT_STATUS, status);
sys/arm/nvidia/drm2/tegra_hdmi.c
354
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
sys/arm/nvidia/drm2/tegra_hdmi.c
356
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW,
sys/arm/nvidia/drm2/tegra_hdmi.c
358
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH,
sys/arm/nvidia/drm2/tegra_hdmi.c
360
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW,
sys/arm/nvidia/drm2/tegra_hdmi.c
362
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH,
sys/arm/nvidia/drm2/tegra_hdmi.c
365
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL,
sys/arm/nvidia/drm2/tegra_hdmi.c
385
WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
sys/arm/nvidia/drm2/tegra_hdmi.c
387
WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW,
sys/arm/nvidia/drm2/tegra_hdmi.c
389
WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH,
sys/arm/nvidia/drm2/tegra_hdmi.c
392
WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL,
sys/arm/nvidia/drm2/tegra_hdmi.c
413
WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
415
WR4(sc,HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE,
sys/arm/nvidia/drm2/tegra_hdmi.c
543
WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0,
sys/arm/nvidia/drm2/tegra_hdmi.c
549
WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_SPARE0, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
551
WR4(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL, 0);
sys/arm/nvidia/drm2/tegra_hdmi.c
553
WR4(sc, HDMI_NV_PDISP_AUDIO_N,
sys/arm/nvidia/drm2/tegra_hdmi.c
558
WR4(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH,
sys/arm/nvidia/drm2/tegra_hdmi.c
561
WR4(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW,
sys/arm/nvidia/drm2/tegra_hdmi.c
564
WR4(sc, HDMI_NV_PDISP_HDMI_SPARE,
sys/arm/nvidia/drm2/tegra_hdmi.c
569
WR4(sc, HDMI_NV_PDISP_AUDIO_N, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
571
WR4(sc, aval_reg, audio_aval);
sys/arm/nvidia/drm2/tegra_hdmi.c
583
WR4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
588
WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
601
WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
606
WR4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
650
WR4(sc, HDMI_NV_PDISP_SOR_PLL0, tmds->pll0);
sys/arm/nvidia/drm2/tegra_hdmi.c
651
WR4(sc, HDMI_NV_PDISP_SOR_PLL1, tmds->pll1);
sys/arm/nvidia/drm2/tegra_hdmi.c
652
WR4(sc, HDMI_NV_PDISP_PE_CURRENT, tmds->pe_c);
sys/arm/nvidia/drm2/tegra_hdmi.c
653
WR4(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, tmds->drive_c);
sys/arm/nvidia/drm2/tegra_hdmi.c
654
WR4(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT, tmds->peak_c);
sys/arm/nvidia/drm2/tegra_hdmi.c
655
WR4(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0, tmds->pad_ctls);
sys/arm/nvidia/drm2/tegra_hdmi.c
669
WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
674
WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
676
WR4(sc, HDMI_NV_PDISP_SOR_PWR, SOR_PWR_SETTING_NEW);
sys/arm/nvidia/drm2/tegra_hdmi.c
677
WR4(sc, HDMI_NV_PDISP_SOR_PWR, 0);
sys/arm/nvidia/drm2/tegra_hdmi.c
699
WR4(sc, HDMI_NV_PDISP_SOR_STATE2, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
701
WR4(sc, HDMI_NV_PDISP_SOR_STATE1, SOR_STATE1_ASY_ORMODE_NORMAL |
sys/arm/nvidia/drm2/tegra_hdmi.c
704
WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0);
sys/arm/nvidia/drm2/tegra_hdmi.c
705
WR4(sc, HDMI_NV_PDISP_SOR_STATE0, SOR_STATE0_UPDATE);
sys/arm/nvidia/drm2/tegra_hdmi.c
709
WR4(sc, HDMI_NV_PDISP_SOR_STATE1, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
711
WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0);
sys/arm/nvidia/drm2/tegra_hdmi.c
737
WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
740
WR4(sc, HDMI_NV_PDISP_INT_ENABLE, 0);
sys/arm/nvidia/drm2/tegra_hdmi.c
741
WR4(sc, HDMI_NV_PDISP_INT_MASK, 0);
sys/arm/nvidia/drm2/tegra_hdmi.c
791
WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
796
WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
800
WR4(sc, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW,
sys/arm/nvidia/drm2/tegra_hdmi.c
810
WR4(sc, HDMI_NV_PDISP_INPUT_CONTROL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
815
WR4(sc, HDMI_NV_PDISP_SOR_REFCLK, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
830
WR4(sc, HDMI_NV_PDISP_HDMI_CTRL, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
841
WR4(sc, HDMI_NV_PDISP_SOR_SEQ_CTL,
sys/arm/nvidia/drm2/tegra_hdmi.c
849
WR4(sc, HDMI_NV_PDISP_SOR_SEQ_INST(0), val);
sys/arm/nvidia/drm2/tegra_hdmi.c
850
WR4(sc, HDMI_NV_PDISP_SOR_SEQ_INST(8), val);
sys/arm/nvidia/drm2/tegra_hdmi.c
859
WR4(sc, HDMI_NV_PDISP_SOR_CSTM, val);
sys/arm/nvidia/drm2/tegra_hdmi.c
871
WR4(sc, HDMI_NV_PDISP_INT_MASK, INT_CODEC_SCRATCH0);
sys/arm/nvidia/drm2/tegra_hdmi.c
872
WR4(sc, HDMI_NV_PDISP_INT_ENABLE, INT_CODEC_SCRATCH0);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
611
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1009
WR4(sc, sc->misc_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1014
WR4(sc, sc->misc_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
421
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
434
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
568
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
573
WR4(sc, PLLE_AUX, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
583
WR4(sc, sc->misc_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
588
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
594
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
607
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
610
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
614
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
620
WR4(sc, sc->misc_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
627
WR4(sc, PLLE_AUX, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
631
WR4(sc, PLLE_AUX, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
638
WR4(sc, XUSBIO_PLL_CFG0, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
642
WR4(sc, XUSBIO_PLL_CFG0, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
655
WR4(sc, SATA_PLL_CFG0, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
658
WR4(sc, SATA_PLL_CFG0, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
663
WR4(sc, PCIE_PLL_CFG0, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
696
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
737
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
742
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
747
WR4(sc, sc->misc_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
754
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
916
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
924
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
931
WR4(sc, sc->misc_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
936
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
943
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
210
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
214
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
221
WR4(sc, sc->base_reg, reg);
sys/arm/nvidia/tegra124/tegra124_pmc.c
207
WR4(sc, PMC_PWRGATE_TOGGLE,
sys/arm/nvidia/tegra124/tegra124_pmc.c
234
WR4(sc, PMC_GPU_RG_CNTRL, 0);
sys/arm/nvidia/tegra124/tegra124_pmc.c
248
WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
sys/arm/nvidia/tegra124/tegra124_pmc.c
514
WR4(sc, PMC_CNTRL, reg);
sys/arm/nvidia/tegra124/tegra124_pmc.c
522
WR4(sc, PMC_CNTRL, reg);
sys/arm/nvidia/tegra124/tegra124_pmc.c
527
WR4(sc, PMC_CNTRL, reg);
sys/arm/nvidia/tegra124/tegra124_pmc.c
535
WR4(sc, PMC_IO_DPD_STATUS, reg);
sys/arm/nvidia/tegra124/tegra124_pmc.c
539
WR4(sc, PMC_IO_DPD2_STATUS, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
375
WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
384
WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
386
WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
391
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
396
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
401
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
415
WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
422
WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
427
WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
442
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
454
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
458
WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
474
WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
479
WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
483
WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
487
WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
501
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
505
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
517
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
521
WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
526
WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
532
WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
538
WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
561
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
566
WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
584
WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
595
WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
607
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
626
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
646
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
651
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
656
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
669
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
674
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
679
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
852
WR4(sc, lane->reg, reg);
sys/arm/nvidia/tegra_i2c.c
244
WR4(sc, I2C_FIFO_CONTROL, reg);
sys/arm/nvidia/tegra_i2c.c
272
WR4(sc, I2C_CLK_DIVISOR,
sys/arm/nvidia/tegra_i2c.c
283
WR4(sc, I2C_BUS_CLEAR_CONFIG,
sys/arm/nvidia/tegra_i2c.c
288
WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
sys/arm/nvidia/tegra_i2c.c
298
WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
sys/arm/nvidia/tegra_i2c.c
332
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
sys/arm/nvidia/tegra_i2c.c
333
WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
sys/arm/nvidia/tegra_i2c.c
334
WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
sys/arm/nvidia/tegra_i2c.c
339
WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) |
sys/arm/nvidia/tegra_i2c.c
342
WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
sys/arm/nvidia/tegra_i2c.c
374
WR4(sc, I2C_TX_PACKET_FIFO, reg);
sys/arm/nvidia/tegra_i2c.c
423
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
sys/arm/nvidia/tegra_i2c.c
424
WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
sys/arm/nvidia/tegra_i2c.c
444
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
sys/arm/nvidia/tegra_i2c.c
452
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
sys/arm/nvidia/tegra_i2c.c
461
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
sys/arm/nvidia/tegra_i2c.c
465
WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
sys/arm/nvidia/tegra_i2c.c
467
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
sys/arm/nvidia/tegra_i2c.c
484
WR4(sc, I2C_TX_PACKET_FIFO, tmp);
sys/arm/nvidia/tegra_i2c.c
487
WR4(sc, I2C_TX_PACKET_FIFO, msg->len - 1);
sys/arm/nvidia/tegra_i2c.c
502
WR4(sc, I2C_TX_PACKET_FIFO, tmp);
sys/arm/nvidia/tegra_i2c.c
510
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, mask);
sys/arm/nvidia/tegra_i2c.c
578
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
sys/arm/nvidia/tegra_i2c.c
579
WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
sys/arm/nvidia/tegra_lic.c
229
WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF);
sys/arm/nvidia/tegra_lic.c
230
WR4(sc, i, LIC_CPU_IEP_CLASS, 0);
sys/arm/nvidia/tegra_mc.c
148
WR4(sc, MC_INTSTATUS, stat);
sys/arm/nvidia/tegra_mc.c
182
WR4(sc, MC_INTSTATUS, stat);
sys/arm/nvidia/tegra_mc.c
190
WR4(sc, MC_INTMASK, 0);
sys/arm/nvidia/tegra_mc.c
191
WR4(sc, MC_INTSTATUS, MC_INT_INT_MASK);
sys/arm/nvidia/tegra_mc.c
261
WR4(sc, MC_INTMASK, MC_INT_INT_MASK);
sys/arm/nvidia/tegra_rtc.c
154
WR4(sc, RTC_SECONDS, tv.tv_sec);
sys/arm/nvidia/tegra_rtc.c
169
WR4(sc, RTC_INTR_STATUS, status);
sys/arm/nvidia/tegra_rtc.c
229
WR4(sc, RTC_SECONDS_ALARM0, 0);
sys/arm/nvidia/tegra_rtc.c
230
WR4(sc, RTC_SECONDS_ALARM1, 0);
sys/arm/nvidia/tegra_rtc.c
231
WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF);
sys/arm/nvidia/tegra_rtc.c
232
WR4(sc, RTC_INTR_MASK, 0);
sys/arm/nvidia/tegra_soctherm.c
524
WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val);
sys/arm/nvidia/tegra_soctherm.c
528
WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val);
sys/arm/nvidia/tegra_soctherm.c
534
WR4(sc, sensor->sensor_base + TSENSOR_CONFIG1, val);
sys/arm/nvidia/tegra_soctherm.c
538
WR4(sc, sensor->sensor_base + TSENSOR_CONFIG2, val);
sys/arm/nvidia/tegra_soctherm.c
542
WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val);
sys/arm/nvidia/tegra_soctherm.c
770
WR4(sc, TSENSOR_PDIV, sc->soc->tsensor_pdiv);
sys/arm/nvidia/tegra_soctherm.c
771
WR4(sc, TSENSOR_HOTSPOT_OFF, sc->soc->tsensor_hotspot_off);
sys/arm/nvidia/tegra_usbphy.c
336
WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
sys/arm/nvidia/tegra_usbphy.c
356
WR4(sc, IF_USB_SUSP_CTRL, val);
sys/arm/nvidia/tegra_usbphy.c
360
WR4(sc, UTMIP_TX_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
367
WR4(sc, UTMIP_HSRX_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
372
WR4(sc, UTMIP_HSRX_CFG1, val);
sys/arm/nvidia/tegra_usbphy.c
377
WR4(sc, UTMIP_DEBOUNCE_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
381
WR4(sc, UTMIP_MISC_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
387
WR4(sc, IF_USB_SUSP_CTRL, val);
sys/arm/nvidia/tegra_usbphy.c
391
WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
395
WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
451
WR4(sc, UTMIP_XCVR_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
459
WR4(sc, UTMIP_XCVR_CFG1, val);
sys/arm/nvidia/tegra_usbphy.c
464
WR4(sc, UTMIP_BIAS_CFG1, val);
sys/arm/nvidia/tegra_usbphy.c
471
WR4(sc, UTMIP_SPARE_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
475
WR4(sc, IF_USB_SUSP_CTRL, val);
sys/arm/nvidia/tegra_usbphy.c
479
WR4(sc, IF_USB_SUSP_CTRL, val);
sys/arm/nvidia/tegra_usbphy.c
489
WR4(sc, CTRL_USB_USBMODE, val);
sys/arm/nvidia/tegra_usbphy.c
494
WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
sys/arm/nvidia/tegra_usbphy.c
512
WR4(sc, IF_USB_SUSP_CTRL, val);
sys/arm/nvidia/tegra_usbphy.c
517
WR4(sc, IF_USB_SUSP_CTRL, val);
sys/arm/nvidia/tegra_usbphy.c
521
WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
527
WR4(sc, UTMIP_XCVR_CFG0, val);
sys/arm/nvidia/tegra_usbphy.c
533
WR4(sc, UTMIP_XCVR_CFG1, val);
sys/arm/ti/ti_sdhci.c
271
WR4(sc, off & ~3, val32);
sys/arm/ti/ti_sdhci.c
299
WR4(sc, SDHCI_CLOCK_CONTROL, val32);
sys/arm/ti/ti_sdhci.c
313
WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
sys/arm/ti/ti_sdhci.c
320
WR4(sc, off & ~3, val32);
sys/arm/ti/ti_sdhci.c
329
WR4(sc, off, val);
sys/arm/xilinx/uart_dev_cdnc.c
208
WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv);
sys/arm/xilinx/uart_dev_cdnc.c
209
WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen);
sys/arm/xilinx/uart_dev_cdnc.c
256
WR4(bas, CDNC_UART_MODE_REG, mode_reg_value);
sys/arm/xilinx/uart_dev_cdnc.c
269
WR4(bas, CDNC_UART_CTRL_REG,
sys/arm/xilinx/uart_dev_cdnc.c
273
WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL);
sys/arm/xilinx/uart_dev_cdnc.c
274
WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL);
sys/arm/xilinx/uart_dev_cdnc.c
277
WR4(bas, CDNC_UART_MODEM_STAT_REG,
sys/arm/xilinx/uart_dev_cdnc.c
282
WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2);
sys/arm/xilinx/uart_dev_cdnc.c
283
WR4(bas, CDNC_UART_RX_TIMEO_REG, 10);
sys/arm/xilinx/uart_dev_cdnc.c
286
WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2);
sys/arm/xilinx/uart_dev_cdnc.c
289
WR4(bas, CDNC_UART_CTRL_REG,
sys/arm/xilinx/uart_dev_cdnc.c
294
WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR |
sys/arm/xilinx/uart_dev_cdnc.c
337
WR4(bas, CDNC_UART_FIFO, c);
sys/arm/xilinx/uart_dev_cdnc.c
445
WR4(bas, CDNC_UART_IEN_REG,
sys/arm/xilinx/uart_dev_cdnc.c
462
WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY);
sys/arm/xilinx/uart_dev_cdnc.c
465
WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]);
sys/arm/xilinx/uart_dev_cdnc.c
468
WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY);
sys/arm/xilinx/uart_dev_cdnc.c
499
WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
sys/arm/xilinx/uart_dev_cdnc.c
517
WR4(bas, CDNC_UART_ISTAT_REG,
sys/arm/xilinx/uart_dev_cdnc.c
534
WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING);
sys/arm/xilinx/uart_dev_cdnc.c
566
WR4(bas, CDNC_UART_ISTAT_REG, istatus &
sys/arm/xilinx/uart_dev_cdnc.c
578
WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY);
sys/arm/xilinx/uart_dev_cdnc.c
592
WR4(bas, CDNC_UART_MODEM_STAT_REG,
sys/arm/xilinx/uart_dev_cdnc.c
656
WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl);
sys/arm/xilinx/uart_dev_cdnc.c
664
WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
sys/arm/xilinx/uart_dev_cdnc.c
681
WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
sys/arm/xilinx/uart_dev_cdnc.c
691
WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
sys/arm/xilinx/zy7_devcfg.c
402
WR4(sc, ZY7_DEVCFG_CTRL,
sys/arm/xilinx/zy7_devcfg.c
415
WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
sys/arm/xilinx/zy7_devcfg.c
431
WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
sys/arm/xilinx/zy7_devcfg.c
432
WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
sys/arm/xilinx/zy7_devcfg.c
436
WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
sys/arm/xilinx/zy7_devcfg.c
445
WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
sys/arm/xilinx/zy7_devcfg.c
456
WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
sys/arm/xilinx/zy7_devcfg.c
468
WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
sys/arm/xilinx/zy7_devcfg.c
469
WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
sys/arm/xilinx/zy7_devcfg.c
473
WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
sys/arm/xilinx/zy7_devcfg.c
484
WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
sys/arm/xilinx/zy7_devcfg.c
591
WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
sys/arm/xilinx/zy7_devcfg.c
594
WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
sys/arm/xilinx/zy7_devcfg.c
597
WR4(sc, ZY7_DEVCFG_DMA_DST_ADDR, ZY7_DEVCFG_DMA_ADDR_ILLEGAL);
sys/arm/xilinx/zy7_devcfg.c
598
WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4);
sys/arm/xilinx/zy7_devcfg.c
599
WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0);
sys/arm/xilinx/zy7_devcfg.c
602
WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
sys/arm/xilinx/zy7_devcfg.c
603
WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_DMA_DONE);
sys/arm/xilinx/zy7_devcfg.c
653
WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
sys/arm/xilinx/zy7_devcfg.c
683
WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_PCFG_DONE);
sys/arm/xilinx/zy7_devcfg.c
765
WR4(sc, ZY7_DEVCFG_UNLOCK, ZY7_DEVCFG_UNLOCK_MAGIC);
sys/arm/xilinx/zy7_devcfg.c
768
WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
sys/arm/xilinx/zy7_devcfg.c
769
WR4(sc, ZY7_DEVCFG_INT_MASK, 0xffffffff);
sys/arm/xilinx/zy7_gpio.c
326
WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
330
WR4(sc, ZY7_GPIO_OEN(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
334
WR4(sc, ZY7_GPIO_OEN(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
339
WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
341
WR4(sc, ZY7_GPIO_OEN(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
361
WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
365
WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
sys/arm/xilinx/zy7_gpio.c
397
WR4(sc, ZY7_GPIO_DATA(pin >> 5),
sys/arm/xilinx/zy7_qspi.c
251
WR4(sc, ZY7_QSPI_TXD1_REG, data);
sys/arm/xilinx/zy7_qspi.c
254
WR4(sc, ZY7_QSPI_TXD2_REG, data);
sys/arm/xilinx/zy7_qspi.c
257
WR4(sc, ZY7_QSPI_TXD3_REG, data);
sys/arm/xilinx/zy7_qspi.c
260
WR4(sc, ZY7_QSPI_TXD0_REG, data);
sys/arm/xilinx/zy7_qspi.c
321
WR4(sc, ZY7_QSPI_INTR_DIS_REG,
sys/arm/xilinx/zy7_qspi.c
351
WR4(sc, ZY7_QSPI_INTR_STAT_REG,
sys/arm/xilinx/zy7_qspi.c
361
WR4(sc, ZY7_QSPI_INTR_DIS_REG,
sys/arm/xilinx/zy7_qspi.c
375
WR4(sc, ZY7_QSPI_INTR_STAT_REG,
sys/arm/xilinx/zy7_qspi.c
390
WR4(sc, ZY7_QSPI_INTR_DIS_REG,
sys/arm/xilinx/zy7_qspi.c
392
WR4(sc, ZY7_QSPI_INTR_EN_REG,
sys/arm/xilinx/zy7_qspi.c
402
WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow);
sys/arm/xilinx/zy7_qspi.c
432
WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow);
sys/arm/xilinx/zy7_qspi.c
451
WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG,
sys/arm/xilinx/zy7_qspi.c
456
WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG, 0);
sys/arm/xilinx/zy7_qspi.c
468
WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow);
sys/arm/xilinx/zy7_qspi.c
475
WR4(sc, ZY7_QSPI_TX_THRESH_REG, 1);
sys/arm/xilinx/zy7_qspi.c
476
WR4(sc, ZY7_QSPI_RX_THRESH_REG, 1);
sys/arm/xilinx/zy7_qspi.c
479
WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0);
sys/arm/xilinx/zy7_qspi.c
480
WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0);
sys/arm/xilinx/zy7_qspi.c
483
WR4(sc, ZY7_QSPI_EN_REG, ZY7_SPI_ENABLE);
sys/arm/xilinx/zy7_qspi.c
624
WR4(sc, ZY7_QSPI_EN_REG, 0);
sys/arm/xilinx/zy7_qspi.c
627
WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0);
sys/arm/xilinx/zy7_qspi.c
628
WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0);
sys/arm/xilinx/zy7_qspi.c
693
WR4(sc, ZY7_QSPI_INTR_EN_REG,
sys/arm/xilinx/zy7_qspi.c
703
WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow);
sys/arm/xilinx/zy7_qspi.c
709
WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow);
sys/arm/xilinx/zy7_slcr.c
114
WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
sys/arm/xilinx/zy7_slcr.c
122
WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
sys/arm/xilinx/zy7_slcr.c
136
WR4(sc, ZY7_SLCR_REBOOT_STAT,
sys/arm/xilinx/zy7_slcr.c
140
WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
sys/arm/xilinx/zy7_slcr.c
163
WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
sys/arm/xilinx/zy7_slcr.c
166
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
sys/arm/xilinx/zy7_slcr.c
194
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
sys/arm/xilinx/zy7_slcr.c
197
WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
sys/arm/xilinx/zy7_slcr.c
239
WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
sys/arm/xilinx/zy7_slcr.c
274
WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
sys/arm/xilinx/zy7_slcr.c
366
WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
sys/arm/xilinx/zy7_slcr.c
445
WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
sys/arm/xilinx/zy7_slcr.c
446
WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
sys/arm/xilinx/zy7_slcr.c
469
WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
sys/arm/xilinx/zy7_slcr.c
470
WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
sys/arm/xilinx/zy7_slcr.c
523
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
sys/arm/xilinx/zy7_slcr.c
538
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
sys/arm/xilinx/zy7_spi.c
163
WR4(sc, ZY7_SPI_TX_DATA_REG, (uint32_t)byte);
sys/arm/xilinx/zy7_spi.c
206
WR4(sc, ZY7_SPI_INTR_DIS_REG,
sys/arm/xilinx/zy7_spi.c
236
WR4(sc, ZY7_SPI_INTR_STAT_REG,
sys/arm/xilinx/zy7_spi.c
246
WR4(sc, ZY7_SPI_INTR_DIS_REG,
sys/arm/xilinx/zy7_spi.c
256
WR4(sc, ZY7_SPI_INTR_STAT_REG,
sys/arm/xilinx/zy7_spi.c
270
WR4(sc, ZY7_SPI_INTR_DIS_REG,
sys/arm/xilinx/zy7_spi.c
272
WR4(sc, ZY7_SPI_INTR_EN_REG,
sys/arm/xilinx/zy7_spi.c
284
WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow);
sys/arm/xilinx/zy7_spi.c
316
WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow);
sys/arm/xilinx/zy7_spi.c
319
WR4(sc, ZY7_SPI_TX_THRESH_REG, 32);
sys/arm/xilinx/zy7_spi.c
320
WR4(sc, ZY7_SPI_RX_THRESH_REG, 1);
sys/arm/xilinx/zy7_spi.c
323
WR4(sc, ZY7_SPI_INTR_STAT_REG, ~0);
sys/arm/xilinx/zy7_spi.c
324
WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0);
sys/arm/xilinx/zy7_spi.c
327
WR4(sc, ZY7_SPI_EN_REG, ZY7_SPI_ENABLE);
sys/arm/xilinx/zy7_spi.c
460
WR4(sc, ZY7_SPI_EN_REG, 0);
sys/arm/xilinx/zy7_spi.c
463
WR4(sc, ZY7_SPI_INTR_STAT_REG, ~0);
sys/arm/xilinx/zy7_spi.c
464
WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0);
sys/arm/xilinx/zy7_spi.c
535
WR4(sc, ZY7_SPI_INTR_EN_REG,
sys/arm/xilinx/zy7_spi.c
548
WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow);
sys/arm64/arm64/cmn600.c
209
WR4(nd->sc, nd->nd_offset + reg, val);
sys/arm64/broadcom/genet/if_genet.c
1011
WR4(sc, GENET_UMAC_CMD, cmd);
sys/arm64/broadcom/genet/if_genet.c
1012
WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl);
sys/arm64/broadcom/genet/if_genet.c
1031
WR4(sc, GENET_UMAC_MAC0, val);
sys/arm64/broadcom/genet/if_genet.c
1033
WR4(sc, GENET_UMAC_MAC1, val);
sys/arm64/broadcom/genet/if_genet.c
1213
WR4(sc, GENET_TX_DESC_ADDRESS_LO(index),
sys/arm64/broadcom/genet/if_genet.c
1215
WR4(sc, GENET_TX_DESC_ADDRESS_HI(index),
sys/arm64/broadcom/genet/if_genet.c
1217
WR4(sc, GENET_TX_DESC_STATUS(index), length_status);
sys/arm64/broadcom/genet/if_genet.c
1228
WR4(sc, GENET_TX_DMA_PROD_INDEX(q->hwindex), q->prod_idx);
sys/arm64/broadcom/genet/if_genet.c
1356
WR4(sc, GENET_INTRL2_CPU_CLEAR, val);
sys/arm64/broadcom/genet/if_genet.c
1462
WR4(sc, GENET_RX_DMA_CONS_INDEX(q->hwindex), q->cons_idx);
sys/arm64/broadcom/genet/if_genet.c
1566
WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)seg.ds_addr);
sys/arm64/broadcom/genet/if_genet.c
1567
WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(seg.ds_addr >> 32));
sys/arm64/broadcom/genet/if_genet.c
1680
WR4(sc, GENET_MDIO_CMD, GENET_MDIO_READ |
sys/arm64/broadcom/genet/if_genet.c
1683
WR4(sc, GENET_MDIO_CMD, val | GENET_MDIO_START_BUSY);
sys/arm64/broadcom/genet/if_genet.c
1710
WR4(sc, GENET_MDIO_CMD, GENET_MDIO_WRITE |
sys/arm64/broadcom/genet/if_genet.c
1714
WR4(sc, GENET_MDIO_CMD, val | GENET_MDIO_START_BUSY);
sys/arm64/broadcom/genet/if_genet.c
1775
WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
1780
WR4(sc, GENET_UMAC_CMD, val);
sys/arm64/broadcom/genet/if_genet.c
494
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
498
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
501
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
sys/arm64/broadcom/genet/if_genet.c
504
WR4(sc, GENET_UMAC_CMD, 0);
sys/arm64/broadcom/genet/if_genet.c
505
WR4(sc, GENET_UMAC_CMD,
sys/arm64/broadcom/genet/if_genet.c
508
WR4(sc, GENET_UMAC_CMD, 0);
sys/arm64/broadcom/genet/if_genet.c
510
WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
sys/arm64/broadcom/genet/if_genet.c
512
WR4(sc, GENET_UMAC_MIB_CTRL, 0);
sys/arm64/broadcom/genet/if_genet.c
520
WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536);
sys/arm64/broadcom/genet/if_genet.c
524
WR4(sc, GENET_RBUF_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
526
WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1);
sys/arm64/broadcom/genet/if_genet.c
532
WR4(sc, GENET_UMAC_CMD, val);
sys/arm64/broadcom/genet/if_genet.c
536
WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
sys/arm64/broadcom/genet/if_genet.c
544
WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff);
sys/arm64/broadcom/genet/if_genet.c
545
WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK, 0xffffffff);
sys/arm64/broadcom/genet/if_genet.c
556
WR4(sc, GENET_UMAC_CMD, val);
sys/arm64/broadcom/genet/if_genet.c
561
WR4(sc, GENET_UMAC_CMD, val);
sys/arm64/broadcom/genet/if_genet.c
581
WR4(sc, GENET_RBUF_CHECK_CTRL, check_ctrl);
sys/arm64/broadcom/genet/if_genet.c
582
WR4(sc, GENET_RBUF_CTRL, buf_ctrl);
sys/arm64/broadcom/genet/if_genet.c
590
WR4(sc, GENET_TBUF_CTRL, buf_ctrl);
sys/arm64/broadcom/genet/if_genet.c
601
WR4(sc, GENET_TX_DMA_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
606
WR4(sc, GENET_RX_DMA_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
713
WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
sys/arm64/broadcom/genet/if_genet.c
738
WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08);
sys/arm64/broadcom/genet/if_genet.c
740
WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
741
WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
742
WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
743
WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
744
WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
sys/arm64/broadcom/genet/if_genet.c
747
WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
748
WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
749
WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
sys/arm64/broadcom/genet/if_genet.c
751
WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
752
WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), 1);
sys/arm64/broadcom/genet/if_genet.c
753
WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
754
WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
755
WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
757
WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
sys/arm64/broadcom/genet/if_genet.c
763
WR4(sc, GENET_TX_DMA_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
784
WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08);
sys/arm64/broadcom/genet/if_genet.c
786
WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
787
WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
788
WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
789
WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
790
WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
sys/arm64/broadcom/genet/if_genet.c
793
WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
794
WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
795
WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
sys/arm64/broadcom/genet/if_genet.c
797
WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
798
WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
sys/arm64/broadcom/genet/if_genet.c
800
WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
801
WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
sys/arm64/broadcom/genet/if_genet.c
803
WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
sys/arm64/broadcom/genet/if_genet.c
813
WR4(sc, GENET_RX_DMA_CTRL, val);
sys/arm64/broadcom/genet/if_genet.c
921
WR4(sc, GENET_SYS_PORT_CTRL, GENET_SYS_PORT_MODE_EXT_GPHY);
sys/arm64/broadcom/genet/if_genet.c
924
WR4(sc, GENET_SYS_PORT_CTRL, 0);
sys/arm64/broadcom/genet/if_genet.c
962
WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0);
sys/arm64/broadcom/genet/if_genet.c
963
WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
725
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1156
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1164
WR4(sc, PLLX_MISC_2, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1170
WR4(sc, PLLX_MISC_2, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1175
WR4(sc, PLLX_MISC_2, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1193
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1198
WR4(sc, PLLX_MISC_2, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1211
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1228
WR4(sc, PLLX_MISC, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1234
WR4(sc, PLLX_MISC_2, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1238
WR4(sc, PLLX_MISC_4, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1239
WR4(sc, PLLX_MISC_5, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1320
WR4(sc, sc->misc_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1325
WR4(sc, sc->misc_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
607
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
620
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
760
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
766
WR4(sc, PLLE_AUX, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
776
WR4(sc, sc->misc_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
781
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
785
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
802
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
805
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
809
WR4(sc, PLLE_SS_CNTL, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
815
WR4(sc, sc->misc_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
822
WR4(sc, PLLE_AUX, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
826
WR4(sc, PLLE_AUX, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
835
WR4(sc, XUSBIO_PLL_CFG0, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
839
WR4(sc, XUSBIO_PLL_CFG0, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
853
WR4(sc, SATA_PLL_CFG0, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
856
WR4(sc, SATA_PLL_CFG0, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
861
WR4(sc, PCIE_PLL_CFG, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
894
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
935
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
940
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
945
WR4(sc, sc->misc_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
952
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_clk_super.c
190
WR4(sc, sc->base_reg, reg);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
243
WR4(sc, PMC_PWRGATE_TOGGLE,
sys/arm64/nvidia/tegra210/tegra210_pmc.c
270
WR4(sc, PMC_GPU_RG_CNTRL, 0);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
284
WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
sys/arm64/nvidia/tegra210/tegra210_pmc.c
506
WR4(sc, PMC_SCRATCH0, 0xDEADBEEF);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
511
WR4(sc, PMC_SCRATCH0, 0xBADC0DE);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
516
WR4(sc, PMC_SCRATCH0, orig);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
579
WR4(sc, PMC_CNTRL, reg);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
587
WR4(sc, PMC_CNTRL, reg);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
592
WR4(sc, PMC_CNTRL, reg);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
600
WR4(sc, PMC_IO_DPD_STATUS, reg);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
604
WR4(sc, PMC_IO_DPD2_STATUS, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1014
WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1028
WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1033
WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1035
WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1040
WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1042
WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1053
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1058
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1063
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1081
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1093
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1113
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1125
WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1156
WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1161
WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1170
WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1188
WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1204
WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1210
WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1240
WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1273
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1278
WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1289
WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1299
WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1304
WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1327
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1331
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1352
WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1381
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1386
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1391
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1404
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1409
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1414
WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1589
WR4(sc, lane->reg, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
573
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
578
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
582
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
586
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
590
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
601
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
607
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
611
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
615
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
623
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
628
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
644
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
661
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
679
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
696
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
714
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
721
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
725
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
729
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
796
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
801
WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
805
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
809
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
813
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
842
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
846
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
850
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
858
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
863
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
879
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
896
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
914
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
930
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
946
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
953
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
957
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
961
WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
sys/arm64/qoriq/qoriq_gpio_pic.c
253
WR4(sc, GPIO_GPICR, reg);
sys/arm64/qoriq/qoriq_gpio_pic.c
382
WR4(sc, GPIO_GPIER, 0xffffffff);
sys/arm64/qoriq/qoriq_gpio_pic.c
383
WR4(sc, GPIO_GPIMR, 0);
sys/arm64/qoriq/qoriq_gpio_pic.c
84
WR4(sc, GPIO_GPIMR, reg);
sys/arm64/qoriq/qoriq_gpio_pic.c
93
WR4(sc, GPIO_GPIER, reg);
sys/arm64/qoriq/qoriq_therm.c
315
WR4(sc, TMU_TTRCR(i), ranges[i]);
sys/arm64/qoriq/qoriq_therm.c
326
WR4(sc, TMU_TTCFGR, calibs[i]);
sys/arm64/qoriq/qoriq_therm.c
327
WR4(sc, TMU_TSCFGR, calibs[i + 1]);
sys/arm64/qoriq/qoriq_therm.c
423
WR4(sc, TMU_TMR, 0);
sys/arm64/qoriq/qoriq_therm.c
427
WR4(sc, TMU_TIER, 0);
sys/arm64/qoriq/qoriq_therm.c
431
WR4(sc, TMUV1_TMTMIR, 0x0F);
sys/arm64/qoriq/qoriq_therm.c
433
WR4(sc, TMUV2_TMTMIR, 0x0F); /* disable */
sys/arm64/qoriq/qoriq_therm.c
435
WR4(sc, TMUV2_TEUMR(0), 0x51009c00);
sys/arm64/qoriq/qoriq_therm.c
437
WR4(sc, TMUV2_TMSAR(sc->tsensors[i].site_id), 0xE);
sys/arm64/qoriq/qoriq_therm.c
452
WR4(sc, TMU_TMR, 0x8C000000 | sites);
sys/arm64/qoriq/qoriq_therm.c
456
WR4(sc, TMUV2_TMSR, sites);
sys/arm64/qoriq/qoriq_therm.c
457
WR4(sc, TMU_TMR, 0x83000000);
sys/arm64/rockchip/rk_pcie_phy.c
107
WR4(sc, GRF_SOC_CON8, 0x7FF,
sys/arm64/rockchip/rk_pcie_phy.c
113
WR4(sc, GRF_SOC_CON8, 1, 1);
sys/arm64/rockchip/rk_pcie_phy.c
116
WR4(sc, GRF_SOC_CON8, 1, 0);
sys/arm64/rockchip/rk_pcie_phy.c
126
WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1);
sys/arm64/rockchip/rk_pcie_phy.c
155
WR4(sc, GRF_SOC_CON_5_PCIE, CON_5_PCIE_IDLE_OFF(i), 0);
sys/arm64/rockchip/rk_pcie_phy.c
218
WR4(sc, GRF_SOC_CON_5_PCIE,
sys/arm64/rockchip/rk_tsadc.c
484
WR4(sc, TSADC_INT_EN, val);
sys/arm64/rockchip/rk_tsadc.c
488
WR4(sc, TSADC_COMP_SHUT(sensor->channel), val);
sys/arm64/rockchip/rk_tsadc.c
491
WR4(sc, TSADC_AUTO_CON, val);
sys/arm64/rockchip/rk_tsadc.c
495
WR4(sc, TSADC_COMP_INT(sensor->channel), val);
sys/arm64/rockchip/rk_tsadc.c
498
WR4(sc, TSADC_INT_EN, val);
sys/arm64/rockchip/rk_tsadc.c
514
WR4(sc, TSADC_AUTO_CON, val);
sys/arm64/rockchip/rk_tsadc.c
519
WR4(sc, TSADC_AUTO_PERIOD, 250); /* 250 ms */
sys/arm64/rockchip/rk_tsadc.c
520
WR4(sc, TSADC_AUTO_PERIOD_HT, 50); /* 50 ms */
sys/arm64/rockchip/rk_tsadc.c
521
WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4);
sys/arm64/rockchip/rk_tsadc.c
522
WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4);
sys/arm64/rockchip/rk_tsadc.c
528
WR4(sc, TSADC_USER_CON, 13 << 6); /* 13 clks */
sys/arm64/rockchip/rk_tsadc.c
542
WR4(sc, TSADC_AUTO_PERIOD, 1875); /* 2.5 ms */
sys/arm64/rockchip/rk_tsadc.c
543
WR4(sc, TSADC_AUTO_PERIOD_HT, 1875); /* 2.5 ms */
sys/arm64/rockchip/rk_tsadc.c
544
WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4);
sys/arm64/rockchip/rk_tsadc.c
545
WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4);
sys/arm64/rockchip/rk_tsadc.c
549
WR4(sc, TSADC_USER_CON, 0xfc0); /* 97us, at least 90us */
sys/arm64/rockchip/rk_tsadc.c
550
WR4(sc, TSADC_AUTO_PERIOD, 1622); /* 2.5ms */
sys/arm64/rockchip/rk_tsadc.c
551
WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4);
sys/arm64/rockchip/rk_tsadc.c
552
WR4(sc, TSADC_AUTO_PERIOD_HT, 1622); /* 2.5ms */
sys/arm64/rockchip/rk_tsadc.c
553
WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4);
sys/arm64/rockchip/rk_tsadc.c
672
WR4(sc, TSADC_INT_PD, val);
sys/arm64/rockchip/rk_tsadc.c
812
WR4(sc, TSADC_AUTO_CON, val);
sys/dev/cadence/if_cgem.c
1005
WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK);
sys/dev/cadence/if_cgem.c
1011
WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN);
sys/dev/cadence/if_cgem.c
1017
WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
sys/dev/cadence/if_cgem.c
1050
WR4(sc, CGEM_NET_CTRL, 0);
sys/dev/cadence/if_cgem.c
1051
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
1052
WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);
sys/dev/cadence/if_cgem.c
1053
WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);
sys/dev/cadence/if_cgem.c
1054
WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);
sys/dev/cadence/if_cgem.c
1055
WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL);
sys/dev/cadence/if_cgem.c
1056
WR4(sc, CGEM_HASH_BOT, 0);
sys/dev/cadence/if_cgem.c
1057
WR4(sc, CGEM_HASH_TOP, 0);
sys/dev/cadence/if_cgem.c
1058
WR4(sc, CGEM_TX_QBAR, 0); /* manual says do this. */
sys/dev/cadence/if_cgem.c
1059
WR4(sc, CGEM_RX_QBAR, 0);
sys/dev/cadence/if_cgem.c
1063
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
1066
WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
sys/dev/cadence/if_cgem.c
1097
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
1113
WR4(sc, CGEM_DMA_CFG, dma_cfg);
sys/dev/cadence/if_cgem.c
1116
WR4(sc, CGEM_RX_QBAR, (uint32_t)sc->rxring_physaddr);
sys/dev/cadence/if_cgem.c
1117
WR4(sc, CGEM_TX_QBAR, (uint32_t)sc->txring_physaddr);
sys/dev/cadence/if_cgem.c
1119
WR4(sc, CGEM_RX_QBAR_HI, (uint32_t)(sc->rxring_physaddr >> 32));
sys/dev/cadence/if_cgem.c
1120
WR4(sc, CGEM_TX_QBAR_HI, (uint32_t)(sc->txring_physaddr >> 32));
sys/dev/cadence/if_cgem.c
1125
WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
sys/dev/cadence/if_cgem.c
1128
WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
sys/dev/cadence/if_cgem.c
1130
WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
sys/dev/cadence/if_cgem.c
1133
WR4(sc, CGEM_INTR_EN, CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN |
sys/dev/cadence/if_cgem.c
1289
WR4(sc, CGEM_DMA_CFG,
sys/dev/cadence/if_cgem.c
1298
WR4(sc, CGEM_DMA_CFG,
sys/dev/cadence/if_cgem.c
1310
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
1317
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
1378
WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 |
sys/dev/cadence/if_cgem.c
1411
WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 |
sys/dev/cadence/if_cgem.c
1499
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
281
WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
sys/dev/cadence/if_cgem.c
283
WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
sys/dev/cadence/if_cgem.c
286
WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
sys/dev/cadence/if_cgem.c
287
WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
sys/dev/cadence/if_cgem.c
359
WR4(sc, CGEM_HASH_TOP, hashes[0]);
sys/dev/cadence/if_cgem.c
360
WR4(sc, CGEM_HASH_BOT, hashes[1]);
sys/dev/cadence/if_cgem.c
361
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
sys/dev/cadence/if_cgem.c
399
WR4(sc, CGEM_RX_QN_BAR(n), sc->null_qs_physaddr);
sys/dev/cadence/if_cgem.c
400
WR4(sc, CGEM_TX_QN_BAR(n), sc->null_qs_physaddr +
sys/dev/cadence/if_cgem.c
856
WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
sys/dev/cadence/if_cgem.c
963
WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow &
sys/dev/cadence/if_cgem.c
966
WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
sys/dev/cadence/if_cgem.c
991
WR4(sc, CGEM_INTR_STAT, istatus);
sys/dev/clk/rockchip/rk_clk_fract.c
175
WR4(clk, sc->gate_offset, val);
sys/dev/clk/rockchip/rk_clk_fract.c
251
WR4(clk, sc->offset, sc->numerator << 16 | sc->denominator);
sys/dev/eqos/if_eqos.c
122
WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);
sys/dev/eqos/if_eqos.c
149
WR4(sc, GMAC_MAC_MDIO_DATA, val);
sys/dev/eqos/if_eqos.c
156
WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);
sys/dev/eqos/if_eqos.c
219
WR4(sc, GMAC_MAC_CONFIGURATION, reg);
sys/dev/eqos/if_eqos.c
223
WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1);
sys/dev/eqos/if_eqos.c
374
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE,
sys/dev/eqos/if_eqos.c
386
WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0);
sys/dev/eqos/if_eqos.c
443
WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val);
sys/dev/eqos/if_eqos.c
445
WR4(sc, GMAC_MAC_ADDRESS0_LOW, val);
sys/dev/eqos/if_eqos.c
448
WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]);
sys/dev/eqos/if_eqos.c
449
WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]);
sys/dev/eqos/if_eqos.c
452
WR4(sc, GMAC_MAC_PACKET_FILTER, pfil);
sys/dev/eqos/if_eqos.c
461
WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR);
sys/dev/eqos/if_eqos.c
475
WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI,
sys/dev/eqos/if_eqos.c
477
WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR,
sys/dev/eqos/if_eqos.c
479
WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1);
sys/dev/eqos/if_eqos.c
481
WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI,
sys/dev/eqos/if_eqos.c
483
WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR,
sys/dev/eqos/if_eqos.c
485
WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1);
sys/dev/eqos/if_eqos.c
487
WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,
sys/dev/eqos/if_eqos.c
508
WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1);
sys/dev/eqos/if_eqos.c
516
WR4(sc, GMAC_DMA_CHAN0_CONTROL, val);
sys/dev/eqos/if_eqos.c
522
WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
sys/dev/eqos/if_eqos.c
529
WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
sys/dev/eqos/if_eqos.c
532
WR4(sc, GMAC_MMC_CONTROL,
sys/dev/eqos/if_eqos.c
546
WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE,
sys/dev/eqos/if_eqos.c
549
WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE,
sys/dev/eqos/if_eqos.c
558
WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, val);
sys/dev/eqos/if_eqos.c
561
WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val);
sys/dev/eqos/if_eqos.c
564
WR4(sc, GMAC_RXQ_CTRL0, (GMAC_RXQ_CTRL0_EN_MASK << 16) |
sys/dev/eqos/if_eqos.c
575
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/eqos/if_eqos.c
625
WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR,
sys/dev/eqos/if_eqos.c
657
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/eqos/if_eqos.c
662
WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
sys/dev/eqos/if_eqos.c
667
WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
sys/dev/eqos/if_eqos.c
672
WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);
sys/dev/eqos/if_eqos.c
685
WR4(sc, GMAC_MAC_CONFIGURATION, val);
sys/dev/eqos/if_eqos.c
737
WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,
sys/dev/eqos/if_eqos.c
807
WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, mtl_clear);
sys/dev/eqos/if_eqos.c
859
WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status);
sys/dev/eqos/if_eqos.c
993
WR4(sc, GMAC_DMA_SYSBUS_MODE, val);
sys/dev/eqos/if_eqos_fdt.c
267
WR4(sc, GMAC_MAC_ADDRESS0_LOW,
sys/dev/eqos/if_eqos_fdt.c
271
WR4(sc, GMAC_MAC_ADDRESS0_HIGH,
sys/dev/ffec/if_ffec.c
1010
WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
sys/dev/ffec/if_ffec.c
1011
WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
sys/dev/ffec/if_ffec.c
1025
WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
sys/dev/ffec/if_ffec.c
1026
WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
sys/dev/ffec/if_ffec.c
1032
WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
sys/dev/ffec/if_ffec.c
1034
WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
sys/dev/ffec/if_ffec.c
1055
WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
sys/dev/ffec/if_ffec.c
1056
WR4(sc, FEC_IEM_REG, 0x00000000);
sys/dev/ffec/if_ffec.c
1057
WR4(sc, FEC_IER_REG, 0xffffffff);
sys/dev/ffec/if_ffec.c
1132
WR4(sc, FEC_IEM_REG, 0x00000000);
sys/dev/ffec/if_ffec.c
1133
WR4(sc, FEC_IER_REG, 0xffffffff);
sys/dev/ffec/if_ffec.c
1150
WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
sys/dev/ffec/if_ffec.c
1156
WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
sys/dev/ffec/if_ffec.c
1164
WR4(sc, FEC_TCR_REG, 0);
sys/dev/ffec/if_ffec.c
1171
WR4(sc, FEC_OPD_REG, 0x00010020);
sys/dev/ffec/if_ffec.c
1195
WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
sys/dev/ffec/if_ffec.c
1202
WR4(sc, FEC_FTRL_REG, maxfl);
sys/dev/ffec/if_ffec.c
1214
WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
sys/dev/ffec/if_ffec.c
1215
WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
sys/dev/ffec/if_ffec.c
1224
WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
sys/dev/ffec/if_ffec.c
1231
WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
sys/dev/ffec/if_ffec.c
1233
WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
sys/dev/ffec/if_ffec.c
1240
WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16);
sys/dev/ffec/if_ffec.c
1257
WR4(sc, FEC_ECR_REG, regval);
sys/dev/ffec/if_ffec.c
1272
WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
sys/dev/ffec/if_ffec.c
1298
WR4(sc, FEC_IER_REG, FEC_IER_TXF);
sys/dev/ffec/if_ffec.c
1303
WR4(sc, FEC_IER_REG, FEC_IER_RXF);
sys/dev/ffec/if_ffec.c
1316
WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
sys/dev/ffec/if_ffec.c
1687
WR4(sc, FEC_ECR_REG, 0);
sys/dev/ffec/if_ffec.c
1689
WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
sys/dev/ffec/if_ffec.c
1736
WR4(sc, FEC_MSCR_REG, mscr);
sys/dev/ffec/if_ffec.c
325
WR4(sc, FEC_IER_REG, FEC_IER_MII);
sys/dev/ffec/if_ffec.c
327
WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
sys/dev/ffec/if_ffec.c
349
WR4(sc, FEC_IER_REG, FEC_IER_MII);
sys/dev/ffec/if_ffec.c
351
WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
sys/dev/ffec/if_ffec.c
437
WR4(sc, FEC_RCR_REG, rcr);
sys/dev/ffec/if_ffec.c
438
WR4(sc, FEC_TCR_REG, tcr);
sys/dev/ffec/if_ffec.c
439
WR4(sc, FEC_ECR_REG, ecr);
sys/dev/ffec/if_ffec.c
491
WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
sys/dev/ffec/if_ffec.c
492
WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR);
sys/dev/ffec/if_ffec.c
494
WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS);
sys/dev/ffec/if_ffec.c
496
WR4(sc, FEC_IEEE_R_DROP, 0);
sys/dev/ffec/if_ffec.c
497
WR4(sc, FEC_IEEE_R_MACERR, 0);
sys/dev/ffec/if_ffec.c
498
WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
sys/dev/ffec/if_ffec.c
499
WR4(sc, FEC_RMON_R_FRAG, 0);
sys/dev/ffec/if_ffec.c
500
WR4(sc, FEC_RMON_R_JAB, 0);
sys/dev/ffec/if_ffec.c
501
WR4(sc, FEC_RMON_R_MC_PKT, 0);
sys/dev/ffec/if_ffec.c
502
WR4(sc, FEC_RMON_R_OVERSIZE, 0);
sys/dev/ffec/if_ffec.c
503
WR4(sc, FEC_RMON_R_PACKETS, 0);
sys/dev/ffec/if_ffec.c
504
WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
sys/dev/ffec/if_ffec.c
505
WR4(sc, FEC_RMON_T_COL, 0);
sys/dev/ffec/if_ffec.c
506
WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
sys/dev/ffec/if_ffec.c
507
WR4(sc, FEC_RMON_T_FRAG, 0);
sys/dev/ffec/if_ffec.c
508
WR4(sc, FEC_RMON_T_JAB, 0);
sys/dev/ffec/if_ffec.c
509
WR4(sc, FEC_RMON_T_MC_PKT, 0);
sys/dev/ffec/if_ffec.c
510
WR4(sc, FEC_RMON_T_OVERSIZE , 0);
sys/dev/ffec/if_ffec.c
511
WR4(sc, FEC_RMON_T_PACKETS, 0);
sys/dev/ffec/if_ffec.c
512
WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
sys/dev/ffec/if_ffec.c
514
WR4(sc, FEC_MIBC_REG, mibc);
sys/dev/ffec/if_ffec.c
686
WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
sys/dev/ffec/if_ffec.c
931
WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
sys/dev/hwpmc/pmu_dmc620.c
155
WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0);
sys/dev/hwpmc/pmu_dmc620.c
156
WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0);
sys/dev/hwpmc/pmu_dmc620.c
224
WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
sys/dev/hwpmc/pmu_dmc620.c
234
WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0);
sys/dev/hwpmc/pmu_dmc620.c
242
WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0);
sys/dev/hwpmc/pmu_dmc620.c
247
WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
sys/dev/hwpmc/pmu_dmc620.c
71
#define MD4(sc, r, c, s) WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s))
sys/dev/hwpmc/pmu_dmc620.c
99
WR4(sc, DMC620_REG(cntr, reg), val);
sys/dev/mwl/if_mwl.c
970
WR4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead);
sys/dev/mwl/if_mwl.c
971
WR4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead);
sys/dev/mwl/if_mwl.c
976
WR4(sc, sc->sc_hwspecs.wcbBase[i], sc->sc_hwdma.wcbBase[i]);
sys/dev/mwl/mwlhal.c
2174
WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
sys/dev/mwl/mwlhal.c
2350
WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
sys/dev/mwl/mwlhal.c
2353
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
sys/dev/mwl/mwlhal.c
2439
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
sys/dev/mwl/mwlhal.c
2449
WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
sys/dev/mwl/mwlhal.c
2452
WR4(mh, MACREG_REG_INT_CODE, 0x00);
sys/dev/mwl/mwlhal.c
2455
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
sys/dev/mwl/mwlhal.c
2484
WR4(mh, MACREG_REG_INT_CODE, 0);
sys/dev/mwl/mwlhal.c
2502
WR4(mh, MACREG_REG_INT_CODE, 0);
sys/dev/mwl/mwlhal.c
2515
WR4(mh, 0x00006014, 0x33);
sys/dev/mwl/mwlhal.c
2516
WR4(mh, 0x00006018, 0xa3a2632);
sys/dev/mwl/mwlhal.c
2517
WR4(mh, 0x00006010, SDRAMSIZE_Addr);
sys/dev/mwl/mwlhal.c
2567
WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
sys/dev/mwl/mwlhal.c
2568
WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
sys/dev/mwl/mwlhal.c
2569
WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
sys/dev/mwl/mwlhal.c
2570
WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
sys/dev/mwl/mwlhal.c
2600
WR4(mh, MACREG_REG_INT_CODE, 0);
sys/dev/mwl/mwlhal.c
2662
WR4(mh, MACREG_REG_GEN_PTR, OpMode);
sys/dev/mwl/mwlhal.c
2665
WR4(mh, MACREG_REG_INT_CODE, 0x00);
sys/dev/mwl/mwlhal.c
491
WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
sys/dev/mwl/mwlhal.c
507
WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
sys/dev/mwl/mwlhal.c
511
WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
sys/dev/mwl/mwlhal.c
528
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
sys/dev/sdhci/fsl_sdhci.c
398
WR4(sc, SDHC_PROT_CTRL, val32);
sys/dev/sdhci/fsl_sdhci.c
416
WR4(sc, off & ~3, val32);
sys/dev/sdhci/fsl_sdhci.c
456
WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
sys/dev/sdhci/fsl_sdhci.c
457
WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
sys/dev/sdhci/fsl_sdhci.c
476
WR4(sc, USDHC_MIX_CONTROL, val32);
sys/dev/sdhci/fsl_sdhci.c
487
WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
sys/dev/sdhci/fsl_sdhci.c
495
WR4(sc, off & ~3, val32);
sys/dev/sdhci/fsl_sdhci.c
508
WR4(sc, off, val);
sys/dev/sdhci/fsl_sdhci.c
592
WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);
sys/dev/sdhci/fsl_sdhci.c
645
WR4(sc, SDHCI_CLOCK_CONTROL, val32);
sys/dev/sdhci/fsl_sdhci.c
742
WR4(sc, SDHCI_INT_STATUS, intmask);
sys/dev/sdhci/fsl_sdhci.c
892
WR4(sc, SDHC_WTMK_LVL, 0x10801080);
sys/dev/sdhci/fsl_sdhci.c
894
WR4(sc, SDHC_WTMK_LVL, 0x08800880);
sys/dev/sdhci/fsl_sdhci.c
922
WR4(sc, SDHC_PROT_CTRL, protctl);
sys/dev/sdhci/sdhci.c
1373
WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
sys/dev/sdhci/sdhci.c
1524
WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
1525
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
1593
WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
sys/dev/sdhci/sdhci.c
1594
WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
sys/dev/sdhci/sdhci.c
1633
WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
sys/dev/sdhci/sdhci.c
1635
WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
sys/dev/sdhci/sdhci.c
1850
WR4(slot, SDHCI_SIGNAL_ENABLE,
sys/dev/sdhci/sdhci.c
1854
WR4(slot, SDHCI_ARGUMENT, cmd->arg);
sys/dev/sdhci/sdhci.c
1886
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
sys/dev/sdhci/sdhci.c
1985
WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
sys/dev/sdhci/sdhci.c
1994
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
2031
WR4(slot, SDHCI_SIGNAL_ENABLE,
sys/dev/sdhci/sdhci.c
2332
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
2335
WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
sys/dev/sdhci/sdhci.c
2387
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
sys/dev/sdhci/sdhci.c
2405
WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
2406
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
2407
WR4(slot, SDHCI_INT_STATUS, intmask &
sys/dev/sdhci/sdhci.c
2413
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
sys/dev/sdhci/sdhci.c
2418
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
sys/dev/sdhci/sdhci.c
2427
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
sys/dev/sdhci/sdhci.c
2432
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
sys/dev/sdhci/sdhci.c
2440
WR4(slot, SDHCI_INT_STATUS, intmask);
sys/dev/sdhci/sdhci.c
2846
WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
sys/dev/sdhci/sdhci.c
403
WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
404
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
640
WR4(slot, SDHCI_BUFFER, data);
sys/dev/sdhci/sdhci.c
654
WR4(slot, SDHCI_BUFFER, data);
sys/dev/sdhci/sdhci.c
731
WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci.c
732
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
sys/dev/sdhci/sdhci_fsl_fdt.c
1107
WR4(sc, SDHCI_FSL_TBCTL, val);
sys/dev/sdhci/sdhci_fsl_fdt.c
1117
WR4(sc, SDHCI_FSL_DLLCFG1, val);
sys/dev/sdhci/sdhci_fsl_fdt.c
1138
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1162
WR4(sc, SDHCI_FSL_TBPTR, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1170
WR4(sc, SDHCI_FSL_AUTOCERR, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1173
WR4(sc, SDHCI_FSL_AUTOCERR, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1178
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1231
WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1250
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1299
WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1348
WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1352
WR4(sc, SDHCI_FSL_SDCLKCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1363
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1377
WR4(sc, SDHCI_FSL_DLLCFG0, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1381
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1404
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1407
WR4(sc, SDHCI_FSL_SDCLKCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1420
WR4(sc, SDHCI_FSL_DLLCFG0, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1428
WR4(sc, SDHCI_FSL_DLLCFG0, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1438
WR4(sc, SDHCI_FSL_TBCTL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1450
WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
1513
WR4(sc, SDHCI_FSL_AUTOCERR, reg);
sys/dev/sdhci/sdhci_fsl_fdt.c
325
WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN);
sys/dev/sdhci/sdhci_fsl_fdt.c
372
WR4(sc, SDHCI_CLOCK_CONTROL, val32);
sys/dev/sdhci/sdhci_fsl_fdt.c
492
WR4(sc, SDHCI_FSL_PROT_CTRL, val32);
sys/dev/sdhci/sdhci_fsl_fdt.c
500
WR4(sc, off & ~3, val32);
sys/dev/sdhci/sdhci_fsl_fdt.c
529
WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
sys/dev/sdhci/sdhci_fsl_fdt.c
543
WR4(sc, off & ~3, val32);
sys/dev/sdhci/sdhci_fsl_fdt.c
572
WR4(sc, off, val);
sys/dev/sdhci/sdhci_fsl_fdt.c
723
WR4(sc, SDHCI_FSL_PROT_CTRL, val);
sys/dev/sdhci/sdhci_fsl_fdt.c
747
WR4(sc, SDHCI_FSL_PROT_CTRL, val_old);
sys/dev/sdhci/sdhci_fsl_fdt.c
962
WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order);
sys/dev/sdhci/sdhci_fsl_fdt.c
970
WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN);
sys/dev/sdhci/sdhci_fsl_fdt.c
972
WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2);
sys/dev/sdhci/sdhci_fsl_fdt.c
989
WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B |
sys/riscv/riscv/plic.c
199
WR4(sc, PLIC_PRIORITY(src->irq), 0);
sys/riscv/riscv/plic.c
211
WR4(sc, PLIC_PRIORITY(src->irq), 1);
sys/riscv/riscv/plic.c
345
WR4(sc, PLIC_PRIORITY(irq), 0);
sys/riscv/riscv/plic.c
436
WR4(sc, PLIC_THRESHOLD(sc, cpu), 0);
sys/riscv/riscv/plic.c
467
WR4(sc, PLIC_CLAIM(sc, cpu), src->irq);
sys/riscv/riscv/plic.c
496
WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
sys/riscv/riscv/plic.c
513
WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
sys/riscv/starfive/jh7110_pcie.c
241
WR4(sc, IRQ_LOCAL_STATUS, MSI_MASK);
sys/riscv/starfive/jh7110_pcie.c
258
WR4(sc, IRQ_LOCAL_STATUS, irqbits);
sys/riscv/starfive/jh7110_pcie.c
276
WR4(sc, IRQ_LOCAL_STATUS, irqbits);
sys/riscv/starfive/jh7110_pcie.c
506
WR4(sc, IRQ_MSI_STATUS, (1U << irq));
sys/riscv/starfive/jh7110_pcie.c
565
WR4(sc, ATR0_AXI4_SLV0_TRSL_PARAM + win_idx * ATR_ENTRY_SIZE, val);
sys/riscv/starfive/jh7110_pcie.c
571
WR4(sc, ATR0_AXI4_SLV0_SRCADDR_PARAM + win_idx * ATR_ENTRY_SIZE, val);
sys/riscv/starfive/jh7110_pcie.c
574
WR4(sc, ATR0_AXI4_SLV0_SRC_ADDR + win_idx * ATR_ENTRY_SIZE, val);
sys/riscv/starfive/jh7110_pcie.c
577
WR4(sc, ATR0_AXI4_SLV0_TRSL_ADDR_LSB + win_idx * ATR_ENTRY_SIZE, val);
sys/riscv/starfive/jh7110_pcie.c
580
WR4(sc, ATR0_AXI4_SLV0_TRSL_ADDR_UDW + win_idx * ATR_ENTRY_SIZE, val);
sys/riscv/starfive/jh7110_pcie.c
585
WR4(sc, ATR0_PCIE_WIN0_SRCADDR_PARAM, val);
sys/riscv/starfive/jh7110_pcie.c
586
WR4(sc, ATR0_PCIE_WIN0_SRC_ADDR, 0);
sys/riscv/starfive/jh7110_pcie.c
790
WR4(sc, IRQ_LOCAL_STATUS, 0xffffffff);
sys/riscv/starfive/jh7110_pcie.c
791
WR4(sc, IRQ_LOCAL_MASK, INTX_MASK | ERROR_MASK | MSI_MASK);
sys/riscv/starfive/jh7110_pcie.c
866
WR4(sc, PCI_MISC_REG, val | PHY_FUNC_DIS);
sys/riscv/starfive/jh7110_pcie.c
876
WR4(sc, PCI_GENERAL_SETUP_REG, val | ROOTPORT_ENABLE);
sys/riscv/starfive/jh7110_pcie.c
879
WR4(sc, PCI_CONF_SPACE_REGS + PCIR_BAR(0), 0);
sys/riscv/starfive/jh7110_pcie.c
880
WR4(sc, PCI_CONF_SPACE_REGS + PCIR_BAR(1), 0);
sys/riscv/starfive/jh7110_pcie.c
886
WR4(sc, PCIE_PCI_IDS_REG, val);
sys/riscv/starfive/jh7110_pcie.c
890
WR4(sc, PMSG_RX_SUPPORT_REG, val & ~PMSG_LTR_SUPPORT);
sys/riscv/starfive/jh7110_pcie.c
894
WR4(sc, PCIE_WINCONF, val | PREF_MEM_WIN_64_SUPPORT);
