sys/arm/allwinner/aw_sid.c
373
while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ)
sys/arm/allwinner/aw_sid.c
375
val = RD4(sc, SID_RDKEY);
sys/arm/allwinner/aw_sid.c
377
val = RD4(sc, sc->sid_conf->efuses[i].base +
sys/arm/allwinner/aw_thermal.c
418
WR4(sc, THS_INTS, RD4(sc, THS_INTS));
sys/arm/allwinner/aw_thermal.c
419
WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL);
sys/arm/allwinner/aw_thermal.c
422
WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);
sys/arm/allwinner/aw_thermal.c
432
val = RD4(sc, THS_DATA0 + (sensor * 4));
sys/arm/allwinner/aw_thermal.c
442
val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
sys/arm/allwinner/aw_thermal.c
453
val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
sys/arm/allwinner/aw_thermal.c
464
val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
sys/arm/allwinner/aw_thermal.c
475
val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
sys/arm/allwinner/aw_thermal.c
486
val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
sys/arm/allwinner/aw_thermal.c
575
ints = RD4(sc, THS_INTS);
sys/arm/allwinner/aw_usb3phy.c
123
val = RD4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL);
sys/arm/allwinner/aw_usb3phy.c
131
val = RD4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL);
sys/arm/allwinner/aw_usb3phy.c
137
val = RD4(sc->res, USB3PHY_APP);
sys/arm/allwinner/aw_usb3phy.c
145
val = RD4(sc->res, USB3PHY_PHY_TUNE_HIGH);
sys/arm/allwinner/aw_usbphy.c
182
#define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
sys/arm/allwinner/aw_usbphy.c
183
#define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
sys/arm/allwinner/if_awg.c
1327
val = RD4(sc, EMAC_INT_STA);
sys/arm/allwinner/if_awg.c
1368
val = RD4(sc, EMAC_INT_STA);
sys/arm/allwinner/if_awg.c
1791
RD4(sc, regs[n].reg));
sys/arm/allwinner/if_awg.c
1860
if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
sys/arm/allwinner/if_awg.c
249
if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {
sys/arm/allwinner/if_awg.c
250
val = RD4(sc, EMAC_MII_DATA);
sys/arm/allwinner/if_awg.c
278
if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)
sys/arm/allwinner/if_awg.c
324
val = RD4(sc, EMAC_BASIC_CTL_0);
sys/arm/allwinner/if_awg.c
340
val = RD4(sc, EMAC_RX_CTL_0);
sys/arm/allwinner/if_awg.c
346
val = RD4(sc, EMAC_TX_FLOW_CTL);
sys/arm/allwinner/if_awg.c
480
tx = RD4(sc, EMAC_TX_CTL_0);
sys/arm/allwinner/if_awg.c
481
rx = RD4(sc, EMAC_RX_CTL_0);
sys/arm/allwinner/if_awg.c
504
machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
sys/arm/allwinner/if_awg.c
505
maclo = RD4(sc, EMAC_ADDR_LOW(0));
sys/arm/allwinner/if_awg.c
570
val = RD4(sc, EMAC_TX_CTL_1);
sys/arm/allwinner/if_awg.c
574
val = RD4(sc, EMAC_RX_CTL_1);
sys/arm/allwinner/if_awg.c
586
val = RD4(sc, EMAC_TX_CTL_1);
sys/arm/allwinner/if_awg.c
595
val = RD4(sc, EMAC_TX_CTL_1);
sys/arm/allwinner/if_awg.c
599
val = RD4(sc, EMAC_RX_CTL_1);
sys/arm/allwinner/if_awg.c
951
val = RD4(sc, EMAC_TX_CTL_1);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
456
uint32_t val = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
477
val32 = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
487
return RD4(sc, off);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
504
uint32_t val32 = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
532
val32 = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1018
edm = RD4(sc, HC_DEBUG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1043
val2 = RD4(sc, HC_HOSTCONFIG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1176
hstcfg = RD4(sc, HC_HOSTCONFIG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1226
edm = RD4(sc, HC_DEBUG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
1238
while (((RD4(sc, HC_DEBUG) >> 4) & 0x1f) > 0)
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
255
val = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
266
val = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
276
val32 = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
287
val32 = RD4(sc, off & ~3);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
302
RD4(sc, HC_COMMAND));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
304
RD4(sc, HC_ARGUMENT));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
306
RD4(sc, HC_TIMEOUTCOUNTER));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
308
RD4(sc, HC_CLOCKDIVISOR));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
310
RD4(sc, HC_RESPONSE_0));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
312
RD4(sc, HC_RESPONSE_1));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
314
RD4(sc, HC_RESPONSE_2));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
316
RD4(sc, HC_RESPONSE_3));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
318
RD4(sc, HC_HOSTSTATUS));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
320
RD4(sc, HC_POWER));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
322
RD4(sc, HC_DEBUG));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
324
RD4(sc, HC_HOSTCONFIG));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
326
RD4(sc, HC_BLOCKSIZE));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
328
RD4(sc, HC_BLOCKCOUNT));
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
357
dbg = RD4(sc, HC_DEBUG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
513
while ((RD4(sc, HC_COMMAND) & HC_CMD_ENABLE) && --timeout > 0) {
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
537
cdst = RD4(sc, HC_RESPONSE_0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
563
hstst = RD4(sc, HC_HOSTSTATUS);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
564
cmd = RD4(sc, HC_COMMAND);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
674
if (RD4(sc, HC_COMMAND) & HC_CMD_ENABLE) {
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
721
save_sdarg = RD4(sc, HC_ARGUMENT);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
736
sc->sdcard_rca = (RD4(sc, HC_ARGUMENT) >> 16);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
745
hstcfg = RD4(sc, HC_HOSTCONFIG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
776
if (RD4(sc, HC_HOSTSTATUS) & HC_HSTST_TIMEOUT_CMD)
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
778
else if (RD4(sc, HC_COMMAND) & HC_CMD_FAILED)
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
790
if (RD4(sc, HC_COMMAND) & HC_CMD_ENABLE) {
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
819
val1 = RD4(sc, HC_HOSTCONFIG);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
887
val = RD4(sc, HC_CLOCKDIVISOR);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
936
val2 = (RD4(sc, HC_COMMAND) << 16) |
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
937
(RD4(sc, HC_ARGUMENT) & 0x0000ffff);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
940
val2 = RD4(sc, HC_RESPONSE_0);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
944
val2 = RD4(sc, HC_RESPONSE_1);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
948
val2 = RD4(sc, HC_RESPONSE_2);
sys/arm/broadcom/bcm2835/bcm2835_sdhost.c
952
val2 = RD4(sc, HC_RESPONSE_3);
sys/arm/freescale/fsl_ocotp.c
171
return (RD4(ocotp_sc, off));
sys/arm/freescale/imx/imx6_ccm.c
177
reg = RD4(sc, CCM_CGPR);
sys/arm/freescale/imx/imx6_ccm.c
180
reg = RD4(sc, CCM_CLPCR);
sys/arm/freescale/imx/imx6_ccm.c
224
reg = RD4(sc, CCM_CSCMR1);
sys/arm/freescale/imx/imx6_ccm.c
239
reg = RD4(sc, CCM_CS1CDR);
sys/arm/freescale/imx/imx6_ccm.c
253
reg = RD4(sc, CCM_CS2CDR);
sys/arm/freescale/imx/imx6_ccm.c
271
WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
sys/arm/freescale/imx/imx6_ccm.c
325
WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
sys/arm/freescale/imx/imx6_ccm.c
328
v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
sys/arm/freescale/imx/imx6_ccm.c
333
if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) &
sys/arm/freescale/imx/imx6_ccm.c
401
reg = RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO);
sys/arm/freescale/imx/imx6_ccm.c
419
reg = RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO);
sys/arm/freescale/imx/imx6_ccm.c
424
if (RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO) &
sys/arm/freescale/imx/imx6_ccm.c
448
reg = RD4(sc, CCM_CCGR3);
sys/arm/freescale/imx/imx6_ccm.c
456
reg = RD4(sc, CCM_CHSCCDR);
sys/arm/freescale/imx/imx6_ccm.c
481
reg = RD4(sc, CCM_CCGR2);
sys/arm/freescale/imx/imx6_ccm.c
490
return (RD4(ccm_sc, CCM_CACCR));
sys/arm/freescale/imx/imx6_snvs.c
106
while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit)
sys/arm/freescale/imx/imx6_snvs.c
119
if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) {
sys/arm/freescale/imx/imx6_snvs.c
131
counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
sys/arm/freescale/imx/imx6_snvs.c
132
counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
sys/arm/freescale/imx/imx6_snvs.c
133
counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
sys/arm/freescale/imx/imx6_snvs.c
134
counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
sys/arm/freescale/imx/imx6_src.c
79
reg = RD4(src_sc, SRC_SCR);
sys/arm/freescale/imx/imx6_src.c
84
reg = RD4(src_sc, SRC_SCR);
sys/arm/freescale/imx/imx_epit.c
162
return (0xffffffff - RD4(sc, EPIT_CNR));
sys/arm/freescale/imx/imx_epit.c
286
status = RD4(sc, EPIT_SR);
sys/arm/freescale/imx/imx_epit.c
459
while (RD4(sc, EPIT_CR) & EPIT_CR_SWR)
sys/arm/freescale/imx/imx_iomux.c
139
val = (RD4(sc, reg) & ~mask) | (select << shift);
sys/arm/freescale/imx/imx_iomux.c
273
return (RD4(iomux_sc, regaddr));
sys/arm/freescale/imx/imx_iomux.c
302
val = RD4(iomux_sc, regaddr * 4);
sys/arm/freescale/imx/imx_spi.c
269
(void)RD4(sc, ECSPI_CFGREG);
sys/arm/freescale/imx/imx_spi.c
276
while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) {
sys/arm/freescale/imx/imx_spi.c
277
sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA);
sys/arm/freescale/imx/imx_spi.c
309
status = RD4(sc, ECSPI_STATREG);
sys/arm/freescale/imx/imx_spi.c
359
(void)RD4(sc, ECSPI_INTREG);
sys/arm/mv/clk/a37x0_tbg_pll.c
61
RD4(clk, sc->tbg_bypass.offset, &val);
sys/arm/mv/clk/a37x0_tbg_pll.c
65
RD4(clk, sc->vcodiv.offset, &val);
sys/arm/mv/clk/a37x0_tbg_pll.c
68
RD4(clk, sc->refdiv.offset, &val);
sys/arm/mv/clk/a37x0_tbg_pll.c
71
RD4(clk, sc->fbdiv.offset, &val);
sys/arm/mv/clk/armada38x_gateclk.c
253
*val = RD4(sc, addr);
sys/arm/mv/clk/armada38x_gateclk.c
267
reg = RD4(sc, addr);
sys/arm/mv/clk/armada38x_gen.c
60
RD4(clk, 0, ®);
sys/arm/mv/mv_ap806_clock.c
134
reg = RD4(sc, 0x400);
sys/arm/mv/mv_ap806_sei.c
118
tmp = RD4(sc, GICP_SEMR(sisrc->irq));
sys/arm/mv/mv_ap806_sei.c
287
cause = RD4(sc, GICP_SECR1);
sys/arm/mv/mv_ap806_sei.c
289
cause |= RD4(sc, GICP_SECR0);
sys/arm/mv/mv_cp110_clock.c
302
*val = RD4(sc, addr);
sys/arm/mv/mv_cp110_clock.c
314
reg = RD4(sc, addr);
sys/arm/mv/mv_cp110_icu.c
157
reg = RD4(sc, ICU_INT_CFG(i));
sys/arm/mv/mv_cp110_icu.c
191
reg = RD4(sc, ICU_INT_CFG(irq_no));
sys/arm/mv/mv_thermal.c
142
reg = RD4(sc, STATUS);
sys/arm/mv/mv_thermal.c
163
reg = RD4(sc, CONTROL0);
sys/arm/mv/mv_thermal.c
185
reg = RD4(sc, CONTROL0);
sys/arm/mv/mv_thermal.c
202
reg = RD4(sc, STATUS) & STATUS_TEMP_MASK;
sys/arm/mv/mv_thermal.c
221
reg = RD4(sc, CONTROL0);
sys/arm/mv/mv_thermal.c
241
reg = RD4(sc, CONTROL1);
sys/arm/mv/mv_thermal.c
247
reg = RD4(sc, CONTROL0);
sys/arm/mv/mvebu_pinctrl.c
117
reg = RD4(sc, offset);
sys/arm/nvidia/drm2/tegra_dc.c
1032
val = RD4(sc, DC_DISP_BLEND_CURSOR_CONTROL);
sys/arm/nvidia/drm2/tegra_dc.c
1041
val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS);
sys/arm/nvidia/drm2/tegra_dc.c
1045
val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS);
sys/arm/nvidia/drm2/tegra_dc.c
1141
val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS);
sys/arm/nvidia/drm2/tegra_dc.c
1179
status = RD4(sc, DC_CMD_INT_STATUS);
sys/arm/nvidia/drm2/tegra_dc.c
563
val = RD4(sc, DC_WINC_WIN_OPTIONS);
sys/arm/nvidia/drm2/tegra_dc.c
752
val = RD4(sc, DC_CMD_DISPLAY_COMMAND);
sys/arm/nvidia/drm2/tegra_dc.c
777
val = RD4(sc, DC_CMD_INT_MASK);
sys/arm/nvidia/drm2/tegra_dc.c
781
val = RD4(sc, DC_CMD_INT_ENABLE);
sys/arm/nvidia/drm2/tegra_dc.c
846
val = RD4(sc, DC_CMD_INT_MASK);
sys/arm/nvidia/drm2/tegra_dc.c
863
val = RD4(sc, DC_CMD_INT_MASK);
sys/arm/nvidia/drm2/tegra_dc.c
894
base = RD4(sc, DC_WINBUF_START_ADDR);
sys/arm/nvidia/drm2/tegra_hdmi.c
1164
status = RD4(sc, HDMI_NV_PDISP_INT_STATUS);
sys/arm/nvidia/drm2/tegra_hdmi.c
547
val = RD4(sc, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
sys/arm/nvidia/drm2/tegra_hdmi.c
567
val = RD4(sc, HDMI_NV_PDISP_AUDIO_N);
sys/arm/nvidia/drm2/tegra_hdmi.c
581
val = RD4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
sys/arm/nvidia/drm2/tegra_hdmi.c
586
val = RD4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
sys/arm/nvidia/drm2/tegra_hdmi.c
599
val = RD4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
sys/arm/nvidia/drm2/tegra_hdmi.c
604
val = RD4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
sys/arm/nvidia/drm2/tegra_hdmi.c
624
val = RD4(sc, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
sys/arm/nvidia/drm2/tegra_hdmi.c
665
val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0);
sys/arm/nvidia/drm2/tegra_hdmi.c
672
val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0);
sys/arm/nvidia/drm2/tegra_hdmi.c
681
val = RD4(sc, HDMI_NV_PDISP_SOR_PWR);
sys/arm/nvidia/drm2/tegra_hdmi.c
707
val = RD4(sc, HDMI_NV_PDISP_SOR_STATE1);
sys/arm/nvidia/drm2/tegra_hdmi.c
735
val = RD4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
sys/arm/nvidia/drm2/tegra_hdmi.c
789
val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0);
sys/arm/nvidia/drm2/tegra_hdmi.c
794
val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0);
sys/arm/nvidia/drm2/tegra_hdmi.c
852
val = RD4(sc,HDMI_NV_PDISP_SOR_CSTM);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
556
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
596
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
627
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
743
RD4(sc, get_enable_reg(sc->idx), &ena_reg);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
744
RD4(sc, get_reset_reg(sc->idx), &rst_reg);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
766
RD4(sc, base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_per.c
784
RD4(sc, base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1005
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1007
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1012
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1030
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1031
RD4(sc, sc->misc_reg, &misc_reg);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
417
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
430
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
495
RD4(sc, sc->base_reg, &val);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
521
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
526
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
531
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
566
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
570
RD4(sc, PLLE_AUX, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
576
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
586
RD4(sc, PLLE_SS_CNTL, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
590
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
602
RD4(sc, PLLE_SS_CNTL, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
618
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
622
RD4(sc, PLLE_AUX, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
633
RD4(sc, XUSBIO_PLL_CFG0, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
645
RD4(sc, SATA_PLL_CFG0, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
661
RD4(sc, PCIE_PLL_CFG0, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
694
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
732
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
740
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
745
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
752
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
757
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
914
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
919
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
925
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
929
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
934
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
941
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
946
RD4(sc, sc->misc_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
159
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
197
RD4(sc, sc->base_reg, ®);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
211
RD4(sc, sc->base_reg, &dummy);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
215
RD4(sc, sc->base_reg, &dummy);
sys/arm/nvidia/tegra124/tegra124_clk_super.c
222
RD4(sc, sc->base_reg, &dummy);
sys/arm/nvidia/tegra124/tegra124_pmc.c
191
reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
sys/arm/nvidia/tegra124/tegra124_pmc.c
198
reg = RD4(sc, PMC_PWRGATE_TOGGLE);
sys/arm/nvidia/tegra124/tegra124_pmc.c
211
reg = RD4(sc, PMC_PWRGATE_TOGGLE);
sys/arm/nvidia/tegra124/tegra124_pmc.c
238
reg = RD4(sc, PMC_PWRGATE_STATUS);
sys/arm/nvidia/tegra124/tegra124_pmc.c
251
reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
sys/arm/nvidia/tegra124/tegra124_pmc.c
259
reg = RD4(sc, PMC_CLAMP_STATUS);
sys/arm/nvidia/tegra124/tegra124_pmc.c
274
reg = RD4(sc, PMC_PWRGATE_STATUS);
sys/arm/nvidia/tegra124/tegra124_pmc.c
512
reg = RD4(sc, PMC_CNTRL);
sys/arm/nvidia/tegra124/tegra124_pmc.c
517
reg = RD4(sc, PMC_CNTRL);
sys/arm/nvidia/tegra124/tegra124_pmc.c
525
reg = RD4(sc, PMC_CNTRL);
sys/arm/nvidia/tegra124/tegra124_pmc.c
533
reg = RD4(sc, PMC_IO_DPD_STATUS);
sys/arm/nvidia/tegra124/tegra124_pmc.c
537
reg = RD4(sc, PMC_IO_DPD2_STATUS);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
368
reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
377
reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
389
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
394
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
399
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
413
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
418
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
425
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
431
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
440
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
452
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
456
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
471
reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
476
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
481
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
485
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
490
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
499
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
503
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
515
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
519
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
524
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
529
reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
535
reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
556
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
563
reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
568
reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
586
reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
605
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
624
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
644
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
649
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
654
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
667
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
672
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
677
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
849
reg = RD4(sc, lane->reg);
sys/arm/nvidia/tegra_efuse.c
194
sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO);
sys/arm/nvidia/tegra_efuse.c
195
sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ);
sys/arm/nvidia/tegra_efuse.c
196
sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ);
sys/arm/nvidia/tegra_efuse.c
197
sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ);
sys/arm/nvidia/tegra_efuse.c
198
sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0);
sys/arm/nvidia/tegra_efuse.c
199
sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0);
sys/arm/nvidia/tegra_efuse.c
200
sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2);
sys/arm/nvidia/tegra_efuse.c
284
reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4);
sys/arm/nvidia/tegra_efuse.c
286
reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4);
sys/arm/nvidia/tegra_efuse.c
288
reg = RD4(sc, TEGRA210_FUSE_SPARE + 4 * 4);
sys/arm/nvidia/tegra_efuse.c
335
cpu_speedo[0] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_0);
sys/arm/nvidia/tegra_efuse.c
336
cpu_speedo[1] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_1);
sys/arm/nvidia/tegra_efuse.c
337
cpu_speedo[2] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_2);
sys/arm/nvidia/tegra_efuse.c
338
soc_speedo[0] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_0);
sys/arm/nvidia/tegra_efuse.c
339
soc_speedo[1] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_1);
sys/arm/nvidia/tegra_efuse.c
340
soc_speedo[2] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_2);
sys/arm/nvidia/tegra_efuse.c
343
sku->cpu_iddq_value = RD4(sc, TEGRA210_FUSE_CPU_IDDQ);
sys/arm/nvidia/tegra_efuse.c
344
sku->soc_iddq_value = RD4(sc, TEGRA210_FUSE_SOC_IDDQ);
sys/arm/nvidia/tegra_efuse.c
345
sku->gpu_iddq_value = RD4(sc, TEGRA210_FUSE_GPU_IDDQ);
sys/arm/nvidia/tegra_efuse.c
399
return (RD4(dev_sc, addr));
sys/arm/nvidia/tegra_i2c.c
242
reg = RD4(sc, I2C_FIFO_CONTROL);
sys/arm/nvidia/tegra_i2c.c
248
reg = RD4(sc, I2C_FIFO_CONTROL);
sys/arm/nvidia/tegra_i2c.c
290
if (RD4(sc, I2C_CONFIG_LOAD) == 0)
sys/arm/nvidia/tegra_i2c.c
296
reg = RD4(sc, I2C_BUS_CLEAR_CONFIG);
sys/arm/nvidia/tegra_i2c.c
301
if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) &
sys/arm/nvidia/tegra_i2c.c
309
status = RD4(sc, I2C_BUS_CLEAR_STATUS);
sys/arm/nvidia/tegra_i2c.c
344
if (RD4(sc, I2C_CONFIG_LOAD) == 0)
sys/arm/nvidia/tegra_i2c.c
365
reg = RD4(sc, I2C_FIFO_STATUS);
sys/arm/nvidia/tegra_i2c.c
391
reg = RD4(sc, I2C_FIFO_STATUS);
sys/arm/nvidia/tegra_i2c.c
395
reg = RD4(sc, I2C_RX_FIFO);
sys/arm/nvidia/tegra_i2c.c
417
status = RD4(sc, I2C_INTERRUPT_SOURCE_REGISTER);
sys/arm/nvidia/tegra_i2c.c
420
reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
sys/arm/nvidia/tegra_i2c.c
442
reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
sys/arm/nvidia/tegra_i2c.c
450
reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
sys/arm/nvidia/tegra_i2c.c
458
reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
sys/arm/nvidia/tegra_mc.c
146
stat = RD4(sc, MC_INTSTATUS);
sys/arm/nvidia/tegra_mc.c
172
err = RD4(sc, MC_ERR_STATUS);
sys/arm/nvidia/tegra_mc.c
173
addr = RD4(sc, MC_ERR_STATUS);
sys/arm/nvidia/tegra_rtc.c
111
if ((RD4(sc, RTC_BUSY) & RTC_BUSY_STATUS) == 0)
sys/arm/nvidia/tegra_rtc.c
134
msec = RD4(sc, RTC_MILLI_SECONDS);
sys/arm/nvidia/tegra_rtc.c
135
sec = RD4(sc, RTC_SHADOW_SECONDS);
sys/arm/nvidia/tegra_rtc.c
168
status = RD4(sc, RTC_INTR_STATUS);
sys/arm/nvidia/tegra_sdhci.c
213
RD4(sc, SDHCI_INT_STATUS);
sys/arm/nvidia/tegra_sdhci.c
347
sc->caps = RD4(sc, SDHCI_CAPABILITIES);
sys/arm/nvidia/tegra_soctherm.c
521
val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0);
sys/arm/nvidia/tegra_soctherm.c
540
val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0);
sys/arm/nvidia/tegra_soctherm.c
546
RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0),
sys/arm/nvidia/tegra_soctherm.c
547
RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1),
sys/arm/nvidia/tegra_soctherm.c
548
RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2),
sys/arm/nvidia/tegra_soctherm.c
549
RD4(sc, sensor->sensor_base + TSENSOR_STATUS0),
sys/arm/nvidia/tegra_soctherm.c
550
RD4(sc, sensor->sensor_base + TSENSOR_STATUS1),
sys/arm/nvidia/tegra_soctherm.c
551
RD4(sc, sensor->sensor_base + TSENSOR_STATUS2)
sys/arm/nvidia/tegra_soctherm.c
578
val = RD4(sc, sensor->sensor_base + TSENSOR_STATUS1);
sys/arm/nvidia/tegra_soctherm.c
590
RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0),
sys/arm/nvidia/tegra_soctherm.c
591
RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1),
sys/arm/nvidia/tegra_soctherm.c
592
RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2),
sys/arm/nvidia/tegra_soctherm.c
593
RD4(sc, sensor->sensor_base + TSENSOR_STATUS0),
sys/arm/nvidia/tegra_soctherm.c
594
RD4(sc, sensor->sensor_base + TSENSOR_STATUS1),
sys/arm/nvidia/tegra_soctherm.c
595
RD4(sc, sensor->sensor_base + TSENSOR_STATUS2)
sys/arm/nvidia/tegra_usbphy.c
318
if ((RD4(sc, reg) & mask) == val)
sys/arm/nvidia/tegra_usbphy.c
331
val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
sys/arm/nvidia/tegra_usbphy.c
354
val = RD4(sc, IF_USB_SUSP_CTRL);
sys/arm/nvidia/tegra_usbphy.c
358
val = RD4(sc, UTMIP_TX_CFG0);
sys/arm/nvidia/tegra_usbphy.c
362
val = RD4(sc, UTMIP_HSRX_CFG0);
sys/arm/nvidia/tegra_usbphy.c
369
val = RD4(sc, UTMIP_HSRX_CFG1);
sys/arm/nvidia/tegra_usbphy.c
374
val = RD4(sc, UTMIP_DEBOUNCE_CFG0);
sys/arm/nvidia/tegra_usbphy.c
379
val = RD4(sc, UTMIP_MISC_CFG0);
sys/arm/nvidia/tegra_usbphy.c
384
val = RD4(sc,IF_USB_SUSP_CTRL);
sys/arm/nvidia/tegra_usbphy.c
389
val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
sys/arm/nvidia/tegra_usbphy.c
393
val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
sys/arm/nvidia/tegra_usbphy.c
432
val = RD4(sc, UTMIP_XCVR_CFG0);
sys/arm/nvidia/tegra_usbphy.c
453
val = RD4(sc, UTMIP_XCVR_CFG1);
sys/arm/nvidia/tegra_usbphy.c
461
val = RD4(sc, UTMIP_BIAS_CFG1);
sys/arm/nvidia/tegra_usbphy.c
466
val = RD4(sc, UTMIP_SPARE_CFG0);
sys/arm/nvidia/tegra_usbphy.c
473
val = RD4(sc, IF_USB_SUSP_CTRL);
sys/arm/nvidia/tegra_usbphy.c
477
val = RD4(sc, IF_USB_SUSP_CTRL);
sys/arm/nvidia/tegra_usbphy.c
483
val = RD4(sc, CTRL_USB_USBMODE);
sys/arm/nvidia/tegra_usbphy.c
491
val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
sys/arm/nvidia/tegra_usbphy.c
508
val = RD4(sc, IF_USB_SUSP_CTRL);
sys/arm/nvidia/tegra_usbphy.c
515
val = RD4(sc, IF_USB_SUSP_CTRL);
sys/arm/nvidia/tegra_usbphy.c
519
val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
sys/arm/nvidia/tegra_usbphy.c
523
val = RD4(sc, UTMIP_XCVR_CFG0);
sys/arm/nvidia/tegra_usbphy.c
529
val = RD4(sc, UTMIP_XCVR_CFG1);
sys/arm/ti/ti_sdhci.c
165
return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
sys/arm/ti/ti_sdhci.c
188
val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
sys/arm/ti/ti_sdhci.c
208
return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
sys/arm/ti/ti_sdhci.c
217
val32 = RD4(sc, off);
sys/arm/ti/ti_sdhci.c
267
val32 = RD4(sc, off & ~3);
sys/arm/ti/ti_sdhci.c
294
val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
sys/arm/ti/ti_sdhci.c
317
val32 = RD4(sc, off & ~3);
sys/arm/xilinx/uart_dev_cdnc.c
333
while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
sys/arm/xilinx/uart_dev_cdnc.c
339
while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
sys/arm/xilinx/uart_dev_cdnc.c
351
return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
sys/arm/xilinx/uart_dev_cdnc.c
365
while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
sys/arm/xilinx/uart_dev_cdnc.c
372
c = RD4(bas, CDNC_UART_FIFO);
sys/arm/xilinx/uart_dev_cdnc.c
493
modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) &
sys/arm/xilinx/uart_dev_cdnc.c
515
status = RD4(bas, CDNC_UART_ISTAT_REG);
sys/arm/xilinx/uart_dev_cdnc.c
525
while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
sys/arm/xilinx/uart_dev_cdnc.c
527
c = RD4(bas, CDNC_UART_FIFO) & 0xff;
sys/arm/xilinx/uart_dev_cdnc.c
563
istatus = RD4(bas, CDNC_UART_ISTAT_REG);
sys/arm/xilinx/uart_dev_cdnc.c
622
modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG);
sys/arm/xilinx/uart_dev_cdnc.c
648
uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG);
sys/arm/xilinx/uart_dev_cdnc.c
659
modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG);
sys/arm/xilinx/zy7_devcfg.c
415
WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
sys/arm/xilinx/zy7_devcfg.c
428
devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL);
sys/arm/xilinx/zy7_devcfg.c
442
if ((RD4(sc, ZY7_DEVCFG_STATUS) &
sys/arm/xilinx/zy7_devcfg.c
460
while ((RD4(sc, ZY7_DEVCFG_STATUS) &
sys/arm/xilinx/zy7_devcfg.c
569
if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
sys/arm/xilinx/zy7_devcfg.c
615
if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
sys/arm/xilinx/zy7_devcfg.c
649
istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS);
sys/arm/xilinx/zy7_devcfg.c
650
imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK);
sys/arm/xilinx/zy7_devcfg.c
684
pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
sys/arm/xilinx/zy7_devcfg.c
772
zy7_ps_vers = (RD4(sc, ZY7_DEVCFG_MCTRL) &
sys/arm/xilinx/zy7_gpio.c
298
if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
sys/arm/xilinx/zy7_gpio.c
300
if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
sys/arm/xilinx/zy7_gpio.c
327
RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
sys/arm/xilinx/zy7_gpio.c
331
RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
sys/arm/xilinx/zy7_gpio.c
335
RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
sys/arm/xilinx/zy7_gpio.c
340
RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
sys/arm/xilinx/zy7_gpio.c
342
RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
sys/arm/xilinx/zy7_gpio.c
381
*value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
sys/arm/xilinx/zy7_gpio.c
398
RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
sys/arm/xilinx/zy7_qspi.c
228
if (nvalid < 4 && (RD4(sc, ZY7_QSPI_INTR_STAT_REG) &
sys/arm/xilinx/zy7_qspi.c
277
data = RD4(sc, ZY7_QSPI_RX_DATA_REG);
sys/arm/xilinx/zy7_qspi.c
307
(RD4(sc, ZY7_QSPI_INTR_STAT_REG) &
sys/arm/xilinx/zy7_qspi.c
316
while ((RD4(sc, ZY7_QSPI_INTR_STAT_REG) &
sys/arm/xilinx/zy7_qspi.c
318
(void)RD4(sc, ZY7_QSPI_RX_DATA_REG);
sys/arm/xilinx/zy7_qspi.c
337
istatus = RD4(sc, ZY7_QSPI_INTR_STAT_REG);
sys/arm/xilinx/zy7_qspi.c
417
sc->lqspi_cfg_shadow = RD4(sc, ZY7_QSPI_LQSPI_CFG_REG);
sys/arm/xilinx/zy7_slcr.c
137
RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
sys/arm/xilinx/zy7_slcr.c
271
reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
sys/arm/xilinx/zy7_slcr.c
297
reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
sys/arm/xilinx/zy7_slcr.c
361
reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
sys/arm/xilinx/zy7_slcr.c
410
reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
sys/arm/xilinx/zy7_slcr.c
490
reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
sys/arm/xilinx/zy7_slcr.c
507
reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
sys/arm/xilinx/zy7_slcr.c
596
bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
sys/arm/xilinx/zy7_slcr.c
601
pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
sys/arm/xilinx/zy7_slcr.c
617
zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
sys/arm/xilinx/zy7_slcr.c
626
arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
sys/arm/xilinx/zy7_slcr.c
627
ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
sys/arm/xilinx/zy7_slcr.c
628
io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
sys/arm/xilinx/zy7_spi.c
177
byte = RD4(sc, ZY7_SPI_RX_DATA_REG) & 0xff;
sys/arm/xilinx/zy7_spi.c
192
(RD4(sc, ZY7_SPI_INTR_STAT_REG) &
sys/arm/xilinx/zy7_spi.c
201
while ((RD4(sc, ZY7_SPI_INTR_STAT_REG) &
sys/arm/xilinx/zy7_spi.c
203
(void)RD4(sc, ZY7_SPI_RX_DATA_REG);
sys/arm/xilinx/zy7_spi.c
222
istatus = RD4(sc, ZY7_SPI_INTR_STAT_REG);
sys/arm64/arm64/cmn600.c
202
return (RD4(nd->sc, nd->nd_offset + reg));
sys/arm64/broadcom/genet/if_genet.c
1354
val = RD4(sc, GENET_INTRL2_CPU_STAT);
sys/arm64/broadcom/genet/if_genet.c
1355
val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);
sys/arm64/broadcom/genet/if_genet.c
1384
prod_idx = RD4(sc, GENET_RX_DMA_PROD_INDEX(q->hwindex)) &
sys/arm64/broadcom/genet/if_genet.c
1400
status = RD4(sc, GENET_RX_DESC_STATUS(index));
sys/arm64/broadcom/genet/if_genet.c
1494
cons_idx = RD4(sc, GENET_TX_DMA_CONS_INDEX(q->hwindex)) &
sys/arm64/broadcom/genet/if_genet.c
1682
val = RD4(sc, GENET_MDIO_CMD);
sys/arm64/broadcom/genet/if_genet.c
1685
if (((val = RD4(sc, GENET_MDIO_CMD)) &
sys/arm64/broadcom/genet/if_genet.c
1713
val = RD4(sc, GENET_MDIO_CMD);
sys/arm64/broadcom/genet/if_genet.c
1716
val = RD4(sc, GENET_MDIO_CMD);
sys/arm64/broadcom/genet/if_genet.c
1767
val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);
sys/arm64/broadcom/genet/if_genet.c
1777
val = RD4(sc, GENET_UMAC_CMD);
sys/arm64/broadcom/genet/if_genet.c
264
major = (RD4(sc, GENET_SYS_REV_CTRL) & REV_MAJOR) >> REV_MAJOR_SHIFT;
sys/arm64/broadcom/genet/if_genet.c
270
minor = (RD4(sc, GENET_SYS_REV_CTRL) & REV_MINOR) >> REV_MINOR_SHIFT;
sys/arm64/broadcom/genet/if_genet.c
272
RD4(sc, GENET_SYS_REV_CTRL) & REV_PHY);
sys/arm64/broadcom/genet/if_genet.c
465
val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
sys/arm64/broadcom/genet/if_genet.c
467
maclo = htobe32(RD4(sc, GENET_UMAC_MAC0));
sys/arm64/broadcom/genet/if_genet.c
468
machi = htobe16(RD4(sc, GENET_UMAC_MAC1) & 0xffff);
sys/arm64/broadcom/genet/if_genet.c
492
val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
sys/arm64/broadcom/genet/if_genet.c
522
val = RD4(sc, GENET_RBUF_CTRL);
sys/arm64/broadcom/genet/if_genet.c
529
val = RD4(sc, GENET_UMAC_CMD);
sys/arm64/broadcom/genet/if_genet.c
554
val = RD4(sc, GENET_UMAC_CMD);
sys/arm64/broadcom/genet/if_genet.c
559
val = RD4(sc, GENET_UMAC_CMD);
sys/arm64/broadcom/genet/if_genet.c
572
check_ctrl = RD4(sc, GENET_RBUF_CHECK_CTRL);
sys/arm64/broadcom/genet/if_genet.c
573
buf_ctrl = RD4(sc, GENET_RBUF_CTRL);
sys/arm64/broadcom/genet/if_genet.c
584
buf_ctrl = RD4(sc, GENET_TBUF_CTRL);
sys/arm64/broadcom/genet/if_genet.c
598
val = RD4(sc, GENET_TX_DMA_CTRL);
sys/arm64/broadcom/genet/if_genet.c
603
val = RD4(sc, GENET_RX_DMA_CTRL);
sys/arm64/broadcom/genet/if_genet.c
760
val = RD4(sc, GENET_TX_DMA_CTRL);
sys/arm64/broadcom/genet/if_genet.c
810
val = RD4(sc, GENET_RX_DMA_CTRL);
sys/arm64/broadcom/genet/if_genet.c
985
cmd = RD4(sc, GENET_UMAC_CMD);
sys/arm64/freescale/imx/clk/imx_clk_gate.c
91
RD4(clk, sc->offset, ®);
sys/arm64/freescale/imx/clk/imx_clk_mux.c
109
RD4(clk, sc->offset, ®);
sys/arm64/freescale/imx/clk/imx_clk_mux.c
83
rv = RD4(clk, sc->offset, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
669
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
710
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
741
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
857
RD4(sc, get_enable_reg(sc->idx), &ena_reg);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
858
RD4(sc, get_reset_reg(sc->idx), &rst_reg);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
880
RD4(sc, base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_per.c
898
RD4(sc, base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1153
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1162
RD4(sc, PLLX_MISC_2, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1167
RD4(sc, PLLX_MISC_2, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1173
RD4(sc, PLLX_MISC_2, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1179
RD4(sc, PLLX_MISC_2, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1190
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1196
RD4(sc, PLLX_MISC_2, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1208
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1226
RD4(sc, PLLX_MISC, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1316
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1318
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1323
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1341
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1342
RD4(sc, sc->misc_reg, &misc_reg);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
603
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
616
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
688
RD4(sc, sc->base_reg, &val);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
714
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
719
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
724
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
758
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
763
RD4(sc, PLLE_AUX, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
769
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
779
RD4(sc, PLLE_SS_CNTL, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
783
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
793
RD4(sc, PLLE_SS_CNTL, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
813
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
817
RD4(sc, PLLE_AUX, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
829
RD4(sc, XUSBIO_PLL_CFG0, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
843
RD4(sc, SATA_PLL_CFG0, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
859
RD4(sc, PCIE_PLL_CFG, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
892
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
930
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
938
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
943
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
950
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
955
RD4(sc, sc->misc_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_super.c
149
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_super.c
177
RD4(sc, sc->base_reg, ®);
sys/arm64/nvidia/tegra210/tegra210_clk_super.c
191
RD4(sc, sc->base_reg, &dummy);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
227
reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
234
reg = RD4(sc, PMC_PWRGATE_TOGGLE);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
247
reg = RD4(sc, PMC_PWRGATE_TOGGLE);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
274
reg = RD4(sc, PMC_PWRGATE_STATUS);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
287
reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
295
reg = RD4(sc, PMC_CLAMP_STATUS);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
310
reg = RD4(sc, PMC_PWRGATE_STATUS);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
505
orig = RD4(sc, PMC_SCRATCH0);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
507
if (RD4(sc, PMC_SCRATCH0) == 0) {
sys/arm64/nvidia/tegra210/tegra210_pmc.c
512
if (RD4(sc, PMC_SCRATCH0) == 0) {
sys/arm64/nvidia/tegra210/tegra210_pmc.c
577
reg = RD4(sc, PMC_CNTRL);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
582
reg = RD4(sc, PMC_CNTRL);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
590
reg = RD4(sc, PMC_CNTRL);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
598
reg = RD4(sc, PMC_IO_DPD_STATUS);
sys/arm64/nvidia/tegra210/tegra210_pmc.c
602
reg = RD4(sc, PMC_IO_DPD2_STATUS);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1007
reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1025
reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1030
reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1037
reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1051
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1056
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1061
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1079
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1091
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1111
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1123
reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1158
reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1163
reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1172
reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1199
reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1208
reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1230
reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1269
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1275
reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1280
reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1291
reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1301
reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx));
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1322
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1329
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1350
reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1379
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1384
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1389
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1402
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1407
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1412
reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
1586
reg = RD4(sc, lane->reg);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
570
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
575
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
580
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
584
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
588
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
596
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
603
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
609
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
613
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
621
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
626
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
630
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
642
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
646
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
659
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
663
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
676
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
682
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
694
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
699
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
712
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
719
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
723
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
727
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
793
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
798
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
803
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
807
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
811
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
819
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
835
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
844
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
848
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
856
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
861
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
865
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
877
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
881
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
894
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
898
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
911
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
916
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
928
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
932
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
944
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
951
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
955
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
959
reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
sys/arm64/qoriq/clk/qoriq_clk_pll.c
78
RD4(clk, sc->offset, &mul);
sys/arm64/qoriq/qoriq_gpio_pic.c
107
status = RD4(sc, GPIO_GPIER);
sys/arm64/qoriq/qoriq_gpio_pic.c
108
status &= RD4(sc, GPIO_GPIMR);
sys/arm64/qoriq/qoriq_gpio_pic.c
248
reg = RD4(sc, GPIO_GPICR);
sys/arm64/qoriq/qoriq_gpio_pic.c
79
reg = RD4(sc, GPIO_GPIMR);
sys/arm64/qoriq/qoriq_therm.c
221
val = RD4(sc, TMU_TRITSR(sensor->site_id));
sys/arm64/qoriq/qoriq_therm.c
399
sc->ver = (RD4(sc, TMU_VERSION) >> 8) & 0xFF;
sys/arm64/qoriq/qoriq_therm.c
424
RD4(sc, TMU_TMR);
sys/arm64/rockchip/rk_pcie_phy.c
110
RD4(sc, GRF_SOC_CON8);
sys/arm64/rockchip/rk_pcie_phy.c
114
RD4(sc, GRF_SOC_CON8);
sys/arm64/rockchip/rk_pcie_phy.c
117
RD4(sc, GRF_SOC_CON8);
sys/arm64/rockchip/rk_pcie_phy.c
127
RD4(sc, GRF_SOC_CON8);
sys/arm64/rockchip/rk_pcie_phy.c
129
val = RD4(sc, GRF_SOC_STATUS1);
sys/arm64/rockchip/rk_tsadc.c
475
val = RD4(sc, TSADC_INT_EN);
sys/arm64/rockchip/rk_tsadc.c
489
val = RD4(sc, TSADC_AUTO_CON);
sys/arm64/rockchip/rk_tsadc.c
496
val = RD4(sc, TSADC_INT_EN);
sys/arm64/rockchip/rk_tsadc.c
574
val = RD4(sc, TSADC_DATA(sensor->channel));
sys/arm64/rockchip/rk_tsadc.c
582
__func__, RD4(sc, TSADC_USER_CON), RD4(sc, TSADC_AUTO_CON),
sys/arm64/rockchip/rk_tsadc.c
583
RD4(sc, TSADC_COMP_INT(sensor->channel)),
sys/arm64/rockchip/rk_tsadc.c
584
RD4(sc, TSADC_COMP_SHUT(sensor->channel)));
sys/arm64/rockchip/rk_tsadc.c
671
val = RD4(sc, TSADC_INT_PD);
sys/arm64/rockchip/rk_tsadc.c
810
val = RD4(sc, TSADC_AUTO_CON);
sys/dev/cadence/if_cgem.c
1004
RD4(sc, CGEM_RX_STAT));
sys/dev/cadence/if_cgem.c
1038
switch (RD4(sc, CGEM_DESIGN_CFG1) &
sys/dev/cadence/if_cgem.c
1290
RD4(sc, CGEM_DMA_CFG) |
sys/dev/cadence/if_cgem.c
1299
RD4(sc, CGEM_DMA_CFG) &
sys/dev/cadence/if_cgem.c
1385
while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
sys/dev/cadence/if_cgem.c
1393
val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK;
sys/dev/cadence/if_cgem.c
1419
while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
sys/dev/cadence/if_cgem.c
251
uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
sys/dev/cadence/if_cgem.c
252
uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
sys/dev/cadence/if_cgem.c
384
queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) &
sys/dev/cadence/if_cgem.c
881
sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT);
sys/dev/cadence/if_cgem.c
882
sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32;
sys/dev/cadence/if_cgem.c
884
sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX);
sys/dev/cadence/if_cgem.c
885
sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX);
sys/dev/cadence/if_cgem.c
886
sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX);
sys/dev/cadence/if_cgem.c
887
sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX);
sys/dev/cadence/if_cgem.c
888
sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX);
sys/dev/cadence/if_cgem.c
889
sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX);
sys/dev/cadence/if_cgem.c
890
sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX);
sys/dev/cadence/if_cgem.c
891
sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX);
sys/dev/cadence/if_cgem.c
892
sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX);
sys/dev/cadence/if_cgem.c
893
sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX);
sys/dev/cadence/if_cgem.c
894
sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS);
sys/dev/cadence/if_cgem.c
896
n = RD4(sc, CGEM_SINGLE_COLL_FRAMES);
sys/dev/cadence/if_cgem.c
899
n = RD4(sc, CGEM_MULTI_COLL_FRAMES);
sys/dev/cadence/if_cgem.c
902
n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES);
sys/dev/cadence/if_cgem.c
905
n = RD4(sc, CGEM_LATE_COLL);
sys/dev/cadence/if_cgem.c
909
sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES);
sys/dev/cadence/if_cgem.c
910
sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS);
sys/dev/cadence/if_cgem.c
912
sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT);
sys/dev/cadence/if_cgem.c
913
sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32;
sys/dev/cadence/if_cgem.c
915
sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX);
sys/dev/cadence/if_cgem.c
916
sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX);
sys/dev/cadence/if_cgem.c
917
sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX);
sys/dev/cadence/if_cgem.c
918
sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX);
sys/dev/cadence/if_cgem.c
919
sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX);
sys/dev/cadence/if_cgem.c
920
sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX);
sys/dev/cadence/if_cgem.c
921
sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX);
sys/dev/cadence/if_cgem.c
922
sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX);
sys/dev/cadence/if_cgem.c
923
sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX);
sys/dev/cadence/if_cgem.c
924
sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX);
sys/dev/cadence/if_cgem.c
925
sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX);
sys/dev/cadence/if_cgem.c
926
sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX);
sys/dev/cadence/if_cgem.c
927
sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX);
sys/dev/cadence/if_cgem.c
928
sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS);
sys/dev/cadence/if_cgem.c
929
sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS);
sys/dev/cadence/if_cgem.c
930
sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS);
sys/dev/cadence/if_cgem.c
931
sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS);
sys/dev/cadence/if_cgem.c
932
sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS);
sys/dev/cadence/if_cgem.c
933
sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS);
sys/dev/cadence/if_cgem.c
934
sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS);
sys/dev/cadence/if_cgem.c
935
sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS);
sys/dev/cadence/if_cgem.c
936
sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS);
sys/dev/cadence/if_cgem.c
990
istatus = RD4(sc, CGEM_INTR_STAT);
sys/dev/clk/clk_div.c
124
rv = RD4(clk, sc->offset, ®);
sys/dev/clk/clk_div.c
229
RD4(clk, sc->offset, ®);
sys/dev/clk/clk_gate.c
109
rv = RD4(clk, sc->offset, ®);
sys/dev/clk/clk_gate.c
95
RD4(clk, sc->offset, ®);
sys/dev/clk/clk_mux.c
106
RD4(clk, sc->offset, ®);
sys/dev/clk/clk_mux.c
80
rv = RD4(clk, sc->offset, ®);
sys/dev/clk/rockchip/rk_clk_fract.c
145
RD4(clk, sc->offset, ®);
sys/dev/clk/rockchip/rk_clk_fract.c
168
RD4(clk, sc->gate_offset, &val);
sys/dev/clk/rockchip/rk_clk_gate.c
107
RD4(clk, sc->offset, ®);
sys/dev/clk/rockchip/rk_clk_gate.c
80
rv = RD4(clk, sc->offset, ®);
sys/dev/clk/rockchip/rk_clk_mux.c
127
rv = RD4(clk, sc->offset, ®);
sys/dev/clk/rockchip/rk_clk_mux.c
158
RD4(clk, sc->offset, ®);
sys/dev/eqos/if_eqos.c
1178
ver = RD4(sc, GMAC_MAC_VERSION);
sys/dev/eqos/if_eqos.c
1190
sc->hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n));
sys/dev/eqos/if_eqos.c
127
addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
sys/dev/eqos/if_eqos.c
129
val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF;
sys/dev/eqos/if_eqos.c
161
addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
sys/dev/eqos/if_eqos.c
188
reg = RD4(sc, GMAC_MAC_CONFIGURATION);
sys/dev/eqos/if_eqos.c
422
pfil = RD4(sc, GMAC_MAC_PACKET_FILTER);
sys/dev/eqos/if_eqos.c
464
val = RD4(sc, GMAC_DMA_MODE);
sys/dev/eqos/if_eqos.c
511
val = RD4(sc, GMAC_DMA_CHAN0_CONTROL);
sys/dev/eqos/if_eqos.c
517
val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
sys/dev/eqos/if_eqos.c
523
val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);
sys/dev/eqos/if_eqos.c
555
val = RD4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL);
sys/dev/eqos/if_eqos.c
559
val = RD4(sc, GMAC_MAC_RX_FLOW_CTRL);
sys/dev/eqos/if_eqos.c
568
val = RD4(sc, GMAC_MAC_CONFIGURATION);
sys/dev/eqos/if_eqos.c
655
val = RD4(sc, GMAC_MAC_CONFIGURATION);
sys/dev/eqos/if_eqos.c
660
val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);
sys/dev/eqos/if_eqos.c
665
val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
sys/dev/eqos/if_eqos.c
670
val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);
sys/dev/eqos/if_eqos.c
674
val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);
sys/dev/eqos/if_eqos.c
683
val = RD4(sc, GMAC_MAC_CONFIGURATION);
sys/dev/eqos/if_eqos.c
796
mtl_istat = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS);
sys/dev/eqos/if_eqos.c
846
mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS);
sys/dev/eqos/if_eqos.c
847
mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE);
sys/dev/eqos/if_eqos.c
852
if ((mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS)))
sys/dev/eqos/if_eqos.c
855
dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS);
sys/dev/eqos/if_eqos.c
856
dma_status &= RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE);
sys/dev/eqos/if_eqos.c
874
RD4(sc, GMAC_MAC_INTERRUPT_STATUS),
sys/dev/eqos/if_eqos.c
875
RD4(sc, GMAC_MTL_INTERRUPT_STATUS),
sys/dev/eqos/if_eqos.c
876
RD4(sc, GMAC_DMA_CHAN0_STATUS));
sys/dev/eqos/if_eqos.c
878
if ((rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS)))
sys/dev/eqos/if_eqos.c
954
maclo = htobe32(RD4(sc, GMAC_MAC_ADDRESS0_LOW));
sys/dev/eqos/if_eqos.c
955
machi = htobe16(RD4(sc, GMAC_MAC_ADDRESS0_HIGH) & 0xFFFF);
sys/dev/eqos/if_eqos.c
975
val = RD4(sc, GMAC_DMA_SYSBUS_MODE);
sys/dev/ffec/if_ffec.c
1055
WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
sys/dev/ffec/if_ffec.c
1230
regval = RD4(sc, FEC_MIBC_REG);
sys/dev/ffec/if_ffec.c
1239
regval = RD4(sc, FEC_RACC_REG);
sys/dev/ffec/if_ffec.c
1252
regval = RD4(sc, FEC_ECR_REG);
sys/dev/ffec/if_ffec.c
1295
ier = RD4(sc, FEC_IER_REG);
sys/dev/ffec/if_ffec.c
311
if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
sys/dev/ffec/if_ffec.c
337
val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
sys/dev/ffec/if_ffec.c
388
ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
sys/dev/ffec/if_ffec.c
389
rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
sys/dev/ffec/if_ffec.c
391
tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
sys/dev/ffec/if_ffec.c
483
mibc = RD4(sc, FEC_MIBC_REG);
sys/dev/ffec/if_ffec.c
530
if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
sys/dev/ffec/if_ffec.c
531
if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
sys/dev/ffec/if_ffec.c
533
RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
sys/dev/ffec/if_ffec.c
534
RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
sys/dev/ffec/if_ffec.c
535
RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP));
sys/dev/ffec/if_ffec.c
537
if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR));
sys/dev/ffec/if_ffec.c
539
if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
sys/dev/ffec/if_ffec.c
540
if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
sys/dev/ffec/if_ffec.c
542
RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
sys/dev/ffec/if_ffec.c
543
RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
sys/dev/ffec/if_ffec.c
544
RD4(sc, FEC_RMON_T_JAB));
sys/dev/ffec/if_ffec.c
546
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
sys/dev/ffec/if_ffec.c
950
palr = RD4(sc, FEC_PALR_REG);
sys/dev/ffec/if_ffec.c
951
paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
sys/dev/hwpmc/pmu_dmc620.c
215
clkdiv2_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2);
sys/dev/hwpmc/pmu_dmc620.c
216
clk_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLK);
sys/dev/hwpmc/pmu_dmc620.c
222
sc->sc_saved_control[i] = RD4(sc, DMC620_REG(i,
sys/dev/hwpmc/pmu_dmc620.c
71
#define MD4(sc, r, c, s) WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s))
sys/dev/hwpmc/pmu_dmc620.c
87
val = RD4(sc, DMC620_REG(cntr, reg));
sys/dev/mwl/if_mwl.c
2628
__func__, npending, RD4(sc, sc->sc_hwspecs.rxDescRead),
sys/dev/mwl/if_mwl.c
2629
RD4(sc, sc->sc_hwspecs.rxDescWrite));
sys/dev/mwl/mwlhal.c
2173
v = RD4(mh, MACREG_REG_PROMISCUOUS);
sys/dev/mwl/mwlhal.c
2186
v = RD4(mh, MACREG_REG_PROMISCUOUS);
sys/dev/mwl/mwlhal.c
2284
*dp = RD4(mh, r);
sys/dev/mwl/mwlhal.c
2292
*dp = RD4(mh, r);
sys/dev/mwl/mwlhal.c
2351
RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
2388
if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
sys/dev/mwl/mwlhal.c
2434
if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
sys/dev/mwl/mwlhal.c
2450
RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
2453
RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
2456
RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
2466
if (RD4(mh, MACREG_REG_INT_CODE) == val)
sys/dev/mwl/mwlhal.c
2489
__func__, RD4(mh, MACREG_REG_INT_CODE));
sys/dev/mwl/mwlhal.c
2507
__func__, RD4(mh, MACREG_REG_INT_CODE));
sys/dev/mwl/mwlhal.c
2601
blocksize = RD4(mh, MACREG_REG_SCRATCH);
sys/dev/mwl/mwlhal.c
2664
if (RD4(mh, MACREG_REG_INT_CODE) == FwReadySignature) {
sys/dev/mwl/mwlhal.c
485
cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE);
sys/dev/mwl/mwlhal.c
493
RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */
sys/dev/mwl/mwlhal.c
508
RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
512
RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
529
dummy = RD4(mh, MACREG_REG_INT_CODE);
sys/dev/mwl/mwlhal.c
671
mh->mh_RTSSuccesses += RD4(mh, 0xa834);
sys/dev/mwl/mwlhal.c
672
mh->mh_RTSFailures += RD4(mh, 0xa830);
sys/dev/mwl/mwlhal.c
673
mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c);
sys/dev/mwl/mwlhal.c
674
mh->mh_FCSErrorCount += RD4(mh, 0xa840);
sys/dev/sdhci/fsl_sdhci.c
215
wrk32 = RD4(sc, SDHC_PROT_CTRL);
sys/dev/sdhci/fsl_sdhci.c
254
return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
sys/dev/sdhci/fsl_sdhci.c
276
return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
sys/dev/sdhci/fsl_sdhci.c
298
val32 = RD4(sc, SDHCI_INT_STATUS);
sys/dev/sdhci/fsl_sdhci.c
299
val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
sys/dev/sdhci/fsl_sdhci.c
311
return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
sys/dev/sdhci/fsl_sdhci.c
320
val32 = RD4(sc, off);
sys/dev/sdhci/fsl_sdhci.c
388
val32 = RD4(sc, SDHC_PROT_CTRL);
sys/dev/sdhci/fsl_sdhci.c
412
val32 = RD4(sc, off & ~3);
sys/dev/sdhci/fsl_sdhci.c
451
val32 = RD4(sc, USDHC_MIX_CONTROL);
sys/dev/sdhci/fsl_sdhci.c
472
val32 = RD4(sc, USDHC_MIX_CONTROL);
sys/dev/sdhci/fsl_sdhci.c
492
val32 = RD4(sc, off & ~3);
sys/dev/sdhci/fsl_sdhci.c
541
if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB)
sys/dev/sdhci/fsl_sdhci.c
557
if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN)
sys/dev/sdhci/fsl_sdhci.c
572
val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
sys/dev/sdhci/fsl_sdhci.c
662
inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB);
sys/dev/sdhci/fsl_sdhci.c
730
intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
sys/dev/sdhci/fsl_sdhci.c
733
intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
sys/dev/sdhci/fsl_sdhci.c
916
protctl = RD4(sc, SDHC_PROT_CTRL);
sys/dev/sdhci/sdhci.c
1326
return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
sys/dev/sdhci/sdhci.c
1812
while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
sys/dev/sdhci/sdhci.c
1903
val = RD4(slot, SDHCI_RESPONSE + i * 4);
sys/dev/sdhci/sdhci.c
1914
slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
sys/dev/sdhci/sdhci.c
2174
val = RD4(slot, SDHCI_PRESENT_STATE);
sys/dev/sdhci/sdhci.c
231
RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
sys/dev/sdhci/sdhci.c
235
RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
sys/dev/sdhci/sdhci.c
237
RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
sys/dev/sdhci/sdhci.c
2377
intmask = RD4(slot, SDHCI_INT_STATUS);
sys/dev/sdhci/sdhci.c
243
RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
sys/dev/sdhci/sdhci.c
245
RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
sys/dev/sdhci/sdhci.c
249
RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
sys/dev/sdhci/sdhci.c
251
RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
sys/dev/sdhci/sdhci.c
253
RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
sys/dev/sdhci/sdhci.c
588
data = RD4(slot, SDHCI_BUFFER);
sys/dev/sdhci/sdhci.c
603
data = RD4(slot, SDHCI_BUFFER);
sys/dev/sdhci/sdhci.c
664
while (RD4(slot, SDHCI_PRESENT_STATE) &
sys/dev/sdhci/sdhci.c
671
while (RD4(slot, SDHCI_PRESENT_STATE) &
sys/dev/sdhci/sdhci.c
890
caps = RD4(slot, SDHCI_CAPABILITIES);
sys/dev/sdhci/sdhci.c
892
caps2 = RD4(slot, SDHCI_CAPABILITIES2);
sys/dev/sdhci/sdhci_fsl_fdt.c
1105
val = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1115
val = RD4(sc, SDHCI_FSL_DLLCFG1);
sys/dev/sdhci/sdhci_fsl_fdt.c
1131
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1157
reg = RD4(sc, SDHCI_FSL_TBPTR);
sys/dev/sdhci/sdhci_fsl_fdt.c
1168
reg = RD4(sc, SDHCI_FSL_AUTOCERR);
sys/dev/sdhci/sdhci_fsl_fdt.c
1175
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1229
reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1247
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1265
reg = RD4(sc, SDHCI_FSL_TBPTR);
sys/dev/sdhci/sdhci_fsl_fdt.c
1297
reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1342
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1346
reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1350
reg = RD4(sc, SDHCI_FSL_SDCLKCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1361
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1374
reg = RD4(sc, SDHCI_FSL_DLLCFG0);
sys/dev/sdhci/sdhci_fsl_fdt.c
1379
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1402
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1405
reg = RD4(sc, SDHCI_FSL_SDCLKCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1417
reg = RD4(sc, SDHCI_FSL_DLLCFG0);
sys/dev/sdhci/sdhci_fsl_fdt.c
1436
reg = RD4(sc, SDHCI_FSL_TBCTL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1448
reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
sys/dev/sdhci/sdhci_fsl_fdt.c
1497
reg = RD4(sc, SDHCI_FSL_AUTOCERR);
sys/dev/sdhci/sdhci_fsl_fdt.c
292
if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)
sys/dev/sdhci/sdhci_fsl_fdt.c
294
if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)
sys/dev/sdhci/sdhci_fsl_fdt.c
322
val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
sys/dev/sdhci/sdhci_fsl_fdt.c
385
wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
sys/dev/sdhci/sdhci_fsl_fdt.c
399
return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);
sys/dev/sdhci/sdhci_fsl_fdt.c
414
return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);
sys/dev/sdhci/sdhci_fsl_fdt.c
424
val32 = RD4(sc, SDHCI_INT_STATUS);
sys/dev/sdhci/sdhci_fsl_fdt.c
425
val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
sys/dev/sdhci/sdhci_fsl_fdt.c
428
return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX);
sys/dev/sdhci/sdhci_fsl_fdt.c
445
val32 = RD4(sc, off);
sys/dev/sdhci/sdhci_fsl_fdt.c
478
val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
sys/dev/sdhci/sdhci_fsl_fdt.c
497
val32 = RD4(sc, off & ~3);
sys/dev/sdhci/sdhci_fsl_fdt.c
540
val32 = RD4(sc, off & ~3);
sys/dev/sdhci/sdhci_fsl_fdt.c
705
val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL);
sys/dev/sdhci/sdhci_fsl_fdt.c
852
while ((RD4(sc, reg) & mask) != value) {
sys/dev/sdhci/sdhci_fsl_fdt.c
946
sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) &
sys/dev/sdhci/sdhci_fsl_fdt.c
960
val = RD4(sc, SDHCI_FSL_PROT_CTRL);
sys/dev/sdhci/sdhci_fsl_fdt.c
969
val = RD4(sc, SDHCI_CLOCK_CONTROL);
sys/dev/sdhci/sdhci_fsl_fdt.c
971
val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
sys/riscv/riscv/plic.c
182
while ((pending = RD4(sc, PLIC_CLAIM(sc, cpu))) != 0) {
sys/riscv/riscv/plic.c
494
reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu));
sys/riscv/riscv/plic.c
511
reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu));
sys/riscv/starfive/jh7110_pcie.c
236
reg = RD4(sc, IRQ_LOCAL_STATUS);
sys/riscv/starfive/jh7110_pcie.c
243
irqbits = RD4(sc, IRQ_MSI_STATUS);
sys/riscv/starfive/jh7110_pcie.c
582
val = RD4(sc, ATR0_PCIE_WIN0_SRCADDR_PARAM);
sys/riscv/starfive/jh7110_pcie.c
865
val = RD4(sc, PCI_MISC_REG);
sys/riscv/starfive/jh7110_pcie.c
875
val = RD4(sc, PCI_GENERAL_SETUP_REG);
sys/riscv/starfive/jh7110_pcie.c
883
val = RD4(sc, PCIE_PCI_IDS_REG);
sys/riscv/starfive/jh7110_pcie.c
889
val = RD4(sc, PMSG_RX_SUPPORT_REG);
sys/riscv/starfive/jh7110_pcie.c
893
val = RD4(sc, PCIE_WINCONF);
