lib/libc/net/nsdispatch.c

450

#define NSS_BACKEND(name, reg) \

lib/libc/net/nsdispatch.c

451

ns_mtab *reg(unsigned int *, nss_module_unregister_fn *);

lib/libc/net/nsdispatch.c

458

#define NSS_BACKEND(name, reg) nss_load_module(#name, reg);

lib/libexecinfo/unwind_arm_ehabi_stub.c

57

_Unwind_SetGR(struct _Unwind_Context *context, int reg, _Unwind_Ptr val)

lib/libexecinfo/unwind_arm_ehabi_stub.c

59

_Unwind_VRS_Set(context, 0 /*_UVRSC_CORE*/, reg, 0 /*_UVRSD_UINT32*/,

lib/libnvmm/libnvmm_x86.c

1000

uint8_t reg:3;

lib/libnvmm/libnvmm_x86.c

1026

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

1879

instr->src.u.reg = &gpr_map__special[1][2][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1884

instr->dst.u.reg = &gpr_map__special[1][3][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1916

streg->u.reg = &gpr_map[0][0][regsize-1]; /* ?AX */

lib/libnvmm/libnvmm_x86.c

1921

stlo->u.reg = &gpr_map__special[1][3][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1925

stlo->u.reg = &gpr_map__special[1][2][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1953

streg->u.reg = &gpr_map[0][0][regsize-1]; /* ?AX */

lib/libnvmm/libnvmm_x86.c

2094

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2098

reg = &gpr_map[instr->rexpref.x][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2100

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2101

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2104

return reg;

lib/libnvmm/libnvmm_x86.c

2111

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2115

reg = &gpr_map[instr->rexpref.b][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2116

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2117

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2120

return reg;

lib/libnvmm/libnvmm_x86.c

2179

uint8_t enc = instr->regmodrm.reg;

lib/libnvmm/libnvmm_x86.c

2180

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2185

reg = &gpr_map[instr->rexpref.r][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2186

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2187

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2190

return reg;

lib/libnvmm/libnvmm_x86.c

2197

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2207

reg = &gpr_map[instr->rexpref.b][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2208

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2209

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2212

return reg;

lib/libnvmm/libnvmm_x86.c

2281

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2291

instr->regmodrm.reg = ((byte & 0b00111000) >> 3);

lib/libnvmm/libnvmm_x86.c

2310

if (group1[instr->regmodrm.reg].emul == NULL) {

lib/libnvmm/libnvmm_x86.c

2313

instr->emul = group1[instr->regmodrm.reg].emul;

lib/libnvmm/libnvmm_x86.c

2315

if (group3[instr->regmodrm.reg].emul == NULL) {

lib/libnvmm/libnvmm_x86.c

2318

instr->emul = group3[instr->regmodrm.reg].emul;

lib/libnvmm/libnvmm_x86.c

2320

if (group11[instr->regmodrm.reg].emul == NULL) {

lib/libnvmm/libnvmm_x86.c

2323

instr->emul = group11[instr->regmodrm.reg].emul;

lib/libnvmm/libnvmm_x86.c

2327

reg = get_register_reg(instr);

lib/libnvmm/libnvmm_x86.c

2328

if (reg == NULL) {

lib/libnvmm/libnvmm_x86.c

2332

strg->u.reg = reg;

lib/libnvmm/libnvmm_x86.c

2347

strm->u.reg = &gpr_map__rip;

lib/libnvmm/libnvmm_x86.c

2356

strm->u.reg = NULL;

lib/libnvmm/libnvmm_x86.c

2365

strm->u.reg = NULL;

lib/libnvmm/libnvmm_x86.c

2377

reg = get_register_rm(instr);

lib/libnvmm/libnvmm_x86.c

2378

if (reg == NULL) {

lib/libnvmm/libnvmm_x86.c

2382

strm->u.reg = reg;

lib/libnvmm/libnvmm_x86.c

3018

uint64_t reg;

lib/libnvmm/libnvmm_x86.c

3026

reg = gpr_read_address(instr, state, sib->idx->num);

lib/libnvmm/libnvmm_x86.c

3027

gva += sib->scale * reg;

lib/libnvmm/libnvmm_x86.c

3030

if (store->u.reg == NULL) {

lib/libnvmm/libnvmm_x86.c

3034

gva = gpr_read_address(instr, state, store->u.reg->num);

lib/libnvmm/libnvmm_x86.c

3035

if (store->u.reg == &gpr_map__rip) {

lib/libnvmm/libnvmm_x86.c

3266

val = state->gprs[instr->src.u.reg->num];

lib/libnvmm/libnvmm_x86.c

3267

val = __SHIFTOUT(val, instr->src.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3287

val = state->gprs[instr->dst.u.reg->num];

lib/libnvmm/libnvmm_x86.c

3288

val = __SHIFTOUT(val, instr->dst.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3310

val = __SHIFTIN(val, instr->dst.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3311

state->gprs[instr->dst.u.reg->num] &= ~instr->dst.u.reg->mask;

lib/libnvmm/libnvmm_x86.c

3312

state->gprs[instr->dst.u.reg->num] |= val;

lib/libnvmm/libnvmm_x86.c

3313

state->gprs[instr->dst.u.reg->num] &= ~instr->zeroextend_mask;

lib/libnvmm/libnvmm_x86.c

3325

val = __SHIFTIN(val, instr->src.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3326

state->gprs[instr->src.u.reg->num] &= ~instr->src.u.reg->mask;

lib/libnvmm/libnvmm_x86.c

3327

state->gprs[instr->src.u.reg->num] |= val;

lib/libnvmm/libnvmm_x86.c

3328

state->gprs[instr->src.u.reg->num] &= ~instr->zeroextend_mask;

lib/libnvmm/libnvmm_x86.c

745

int reg = 0; /* GCC */

lib/libnvmm/libnvmm_x86.c

784

reg = NVMM_X64_GPR_RDI;

lib/libnvmm/libnvmm_x86.c

786

reg = NVMM_X64_GPR_RSI;

lib/libnvmm/libnvmm_x86.c

789

gva = state->gprs[reg];

lib/libnvmm/libnvmm_x86.c

854

state->gprs[reg] -= iocnt * io.size;

lib/libnvmm/libnvmm_x86.c

856

state->gprs[reg] += iocnt * io.size;

sbin/ifconfig/ifieee80211.c

2081

const struct ieee80211_regdomain *reg,

sbin/ifconfig/ifieee80211.c

2163

if ((flags & REQ_ECM) && !reg->ecm) {

sbin/ifconfig/ifieee80211.c

2168

if ((flags & REQ_INDOOR) && reg->location == 'O') {

sbin/ifconfig/ifieee80211.c

2174

if ((flags & REQ_OUTDOOR) && reg->location == 'I') {

sbin/ifconfig/ifieee80211.c

2221

const struct ieee80211_regdomain *reg = &req->rd;

sbin/ifconfig/ifieee80211.c

2233

if (reg->regdomain == 0) {

sbin/ifconfig/ifieee80211.c

2234

cc = lib80211_country_findbycc(rdp, reg->country);

sbin/ifconfig/ifieee80211.c

2237

reg->country);

sbin/ifconfig/ifieee80211.c

2240

rd = lib80211_regdomain_findbysku(rdp, reg->regdomain);

sbin/ifconfig/ifieee80211.c

2243

reg->regdomain);

sbin/ifconfig/ifieee80211.c

2254

regdomain_addchans(ci, &rd->bands_11b, reg,

sbin/ifconfig/ifieee80211.c

2257

regdomain_addchans(ci, &rd->bands_11g, reg,

sbin/ifconfig/ifieee80211.c

2260

regdomain_addchans(ci, &rd->bands_11a, reg,

sbin/ifconfig/ifieee80211.c

2263

regdomain_addchans(ci, &rd->bands_11na, reg,

sbin/ifconfig/ifieee80211.c

2267

regdomain_addchans(ci, &rd->bands_11na, reg,

sbin/ifconfig/ifieee80211.c

2270

regdomain_addchans(ci, &rd->bands_11na, reg,

sbin/ifconfig/ifieee80211.c

2276

regdomain_addchans(ci, &rd->bands_11ng, reg,

sbin/ifconfig/ifieee80211.c

2280

regdomain_addchans(ci, &rd->bands_11ng, reg,

sbin/ifconfig/ifieee80211.c

2283

regdomain_addchans(ci, &rd->bands_11ng, reg,

sbin/ifconfig/ifieee80211.c

4205

print_regdomain(const struct ieee80211_regdomain *reg, int verb)

sbin/ifconfig/ifieee80211.c

4207

if ((reg->regdomain != 0 &&

sbin/ifconfig/ifieee80211.c

4208

reg->regdomain != reg->country) || verb) {

sbin/ifconfig/ifieee80211.c

4210

lib80211_regdomain_findbysku(getregdata(), reg->regdomain);

sbin/ifconfig/ifieee80211.c

4212

LINE_CHECK("regdomain %d", reg->regdomain);

sbin/ifconfig/ifieee80211.c

4216

if (reg->country != 0 || verb) {

sbin/ifconfig/ifieee80211.c

4218

lib80211_country_findbycc(getregdata(), reg->country);

sbin/ifconfig/ifieee80211.c

4220

LINE_CHECK("country %d", reg->country);

sbin/ifconfig/ifieee80211.c

4224

if (reg->location == 'I')

sbin/ifconfig/ifieee80211.c

4226

else if (reg->location == 'O')

sbin/ifconfig/ifieee80211.c

4230

if (reg->ecm)

sys/bus/firewire/fwcrom.c

109

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

113

reg = crom_get(cc);

sys/bus/firewire/fwcrom.c

114

if ((reg->key & CSRTYPE_MASK) == CSRTYPE_D) {

sys/bus/firewire/fwcrom.c

122

ptr->dir = (struct csrdirectory *) (reg + reg->val);

sys/bus/firewire/fwcrom.c

149

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

152

reg = crom_get(cc);

sys/bus/firewire/fwcrom.c

153

if (reg->key == key)

sys/bus/firewire/fwcrom.c

154

return reg;

sys/bus/firewire/fwcrom.c

163

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

170

reg = crom_get(cc);

sys/bus/firewire/fwcrom.c

172

if (reg->key == CSRKEY_SPEC && reg->val == spec)

sys/bus/firewire/fwcrom.c

177

if (reg->key == CSRKEY_VER && reg->val == ver)

sys/bus/firewire/fwcrom.c

190

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

199

reg = crom_get(cc);

sys/bus/firewire/fwcrom.c

200

if (reg->key != CROM_TEXTLEAF ||

sys/bus/firewire/fwcrom.c

201

(vm_offset_t)(reg + reg->val) > CROM_END(cc)) {

sys/bus/firewire/fwcrom.c

205

textleaf = (struct csrtext *)(reg + reg->val);

sys/bus/firewire/fwcrom.c

301

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

306

reg = crom_get(cc);

sys/bus/firewire/fwcrom.c

307

switch (reg->key & CSRTYPE_MASK) {

sys/bus/firewire/fwcrom.c

310

len -= ksnprintf(buf, len, "%d", reg->val);

sys/bus/firewire/fwcrom.c

318

reg->val, reg->val);

sys/bus/firewire/fwcrom.c

324

dir = (struct csrdirectory *) (reg + reg->val);

sys/bus/firewire/fwcrom.c

331

switch (reg->key) {

sys/bus/firewire/fwcrom.c

346

crom_desc_specver(0, reg->val, buf, len);

sys/bus/firewire/fwcrom.c

412

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

415

reg = (struct csrreg *)(void *)&i;

sys/bus/firewire/fwcrom.c

416

reg->key = key;

sys/bus/firewire/fwcrom.c

417

reg->val = val;

sys/bus/firewire/fwcrom.c

502

struct csrreg *reg;

sys/bus/firewire/fwcrom.c

503

reg = (struct csrreg *)

sys/bus/firewire/fwcrom.c

505

reg->val = offset -

sys/bus/firewire/fwohci.c

341

struct fw_reg_req_t *reg = (struct fw_reg_req_t *) ap->a_data;

sys/bus/firewire/fwohci.c

356

if(reg->addr <= OHCI_MAX_REG){

sys/bus/firewire/fwohci.c

357

OWRITE(fc, reg->addr, reg->data);

sys/bus/firewire/fwohci.c

358

reg->data = OREAD(fc, reg->addr);

sys/bus/firewire/fwohci.c

364

if(reg->addr <= OHCI_MAX_REG){

sys/bus/firewire/fwohci.c

365

reg->data = OREAD(fc, reg->addr);

sys/bus/firewire/fwohci.c

382

if (reg->addr <= OHCI_MAX_PHY_REG)

sys/bus/firewire/fwohci.c

383

reg->data = fwphy_rddata(fc, reg->addr);

sys/bus/firewire/fwohci.c

388

if (reg->addr <= OHCI_MAX_PHY_REG)

sys/bus/firewire/fwohci.c

389

reg->data = fwphy_wrdata(fc, reg->addr, reg->data);

sys/bus/firewire/fwohci.c

403

u_int32_t reg, reg2;

sys/bus/firewire/fwohci.c

415

reg = fwphy_rddata(sc, FW_PHY_SPD_REG);

sys/bus/firewire/fwohci.c

417

if((reg >> 5) != 7 ){

sys/bus/firewire/fwohci.c

419

sc->fc.nport = reg & FW_PHY_NP;

sys/bus/firewire/fwohci.c

420

sc->fc.speed = reg & FW_PHY_SPD >> 6;

sys/bus/firewire/fwohci.c

432

sc->fc.nport = reg & FW_PHY_NP;

sys/bus/firewire/fwohci.c

465

reg = fwphy_rddata(sc, FW_PHY_SPD_REG);

sys/bus/firewire/fwohci.c

466

if((reg >> 5) == 7 ){

sys/bus/firewire/fwohci.c

467

reg = fwphy_rddata(sc, 4);

sys/bus/firewire/fwohci.c

468

reg |= 1 << 6;

sys/bus/firewire/fwohci.c

469

fwphy_wrdata(sc, 4, reg);

sys/bus/firewire/fwohci.c

470

reg = fwphy_rddata(sc, 4);

sys/bus/firewire/fwohci.c

480

u_int32_t reg, reg2;

sys/bus/firewire/fwohci.c

514

reg = OREAD(sc, OHCI_BUS_OPT);

sys/bus/firewire/fwohci.c

515

reg2 = reg | OHCI_BUSFNC;

sys/bus/firewire/fwohci.c

516

max_rec = (reg & 0x0000f000) >> 12;

sys/bus/firewire/fwohci.c

517

speed = (reg & 0x00000007);

sys/bus/firewire/fwohci.c

528

device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);

sys/bus/firewire/fwohci.c

586

u_int32_t reg;

sys/bus/firewire/fwohci.c

594

reg = OREAD(sc, OHCI_VERSION);

sys/bus/firewire/fwohci.c

595

mver = (reg >> 16) & 0xff;

sys/bus/firewire/fwohci.c

597

mver, reg & 0xff, (reg>>24) & 1);

sys/bus/firewire/fwohci.c

606

reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);

sys/bus/firewire/fwohci.c

610

if ((reg & (1 << i)) == 0)

sys/bus/gpio/gpio_intel/gpio_cherryview.c

243

uint32_t reg, reg1, reg2;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

353

reg = reg2 & ~CHV_GPIO_CTL1_INTCFG_MASK;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

354

reg |= (new_intcfg & CHV_GPIO_CTL1_INTCFG_MASK) << 0;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

355

chvgpio_write(sc, PIN_CTL1(pin), reg);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

362

reg = reg1 & ~CHV_GPIO_CTL0_GPIOCFG_MASK;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

363

reg |= (new_gpiocfg & CHV_GPIO_CTL0_GPIOCFG_MASK) << 0;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

364

chvgpio_write(sc, PIN_CTL0(pin), reg);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

384

uint32_t reg, intcfg, gpiocfg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

400

reg = chvgpio_read(sc, PIN_CTL1(pin));

sys/bus/gpio/gpio_intel/gpio_cherryview.c

401

if ((reg & CHV_GPIO_CTL1_INTCFG_MASK) != intcfg) {

sys/bus/gpio/gpio_intel/gpio_cherryview.c

402

reg &= ~CHV_GPIO_CTL1_INTCFG_MASK;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

403

reg |= intcfg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

404

chvgpio_write(sc, PIN_CTL1(pin), reg);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

408

reg = chvgpio_read(sc, PIN_CTL0(pin));

sys/bus/gpio/gpio_intel/gpio_cherryview.c

409

if ((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) != gpiocfg) {

sys/bus/gpio/gpio_intel/gpio_cherryview.c

410

reg &= ~CHV_GPIO_CTL0_GPIOCFG_MASK;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

411

reg |= gpiocfg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

412

chvgpio_write(sc, PIN_CTL0(pin), reg);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

420

uint32_t reg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

428

reg = chvgpio_read(sc, CHV_GPIO_REG_MASK);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

429

reg |= (1U << map->intidx);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

430

chvgpio_write(sc, CHV_GPIO_REG_MASK, reg);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

437

uint32_t reg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

442

reg = chvgpio_read(sc, CHV_GPIO_REG_MASK);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

443

reg &= ~(1U << map->intidx);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

444

chvgpio_write(sc, CHV_GPIO_REG_MASK, reg);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

479

uint32_t reg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

482

reg = chvgpio_read(sc, PIN_CTL0(pin));

sys/bus/gpio/gpio_intel/gpio_cherryview.c

484

KKASSERT((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x0 ||

sys/bus/gpio/gpio_intel/gpio_cherryview.c

485

(reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x200);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

487

if (reg & CHV_GPIO_CTL0_RXSTATE)

sys/bus/gpio/gpio_intel/gpio_cherryview.c

498

uint32_t reg;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

500

reg = chvgpio_read(sc, PIN_CTL0(pin));

sys/bus/gpio/gpio_intel/gpio_cherryview.c

502

KKASSERT((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0 ||

sys/bus/gpio/gpio_intel/gpio_cherryview.c

503

(reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x100);

sys/bus/gpio/gpio_intel/gpio_cherryview.c

506

reg |= CHV_GPIO_CTL0_TXSTATE;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

508

reg &= ~CHV_GPIO_CTL0_TXSTATE;

sys/bus/gpio/gpio_intel/gpio_cherryview.c

509

chvgpio_write(sc, PIN_CTL0(pin), reg);

sys/bus/pccard/pccard.c

1203

int reg;

sys/bus/pccard/pccard.c

1223

reg = pccard_ccr_read(pf, PCCARD_CCR_STATUS);

sys/bus/pccard/pccard.c

1224

if (reg & PCCARD_CCR_STATUS_INTR)

sys/bus/pccard/pccard.c

1226

reg & ~PCCARD_CCR_STATUS_INTR);

sys/bus/pccard/pccard.c

581

int reg;

sys/bus/pccard/pccard.c

645

reg = (pf->cfe->number & PCCARD_CCR_OPTION_CFINDEX);

sys/bus/pccard/pccard.c

646

reg |= PCCARD_CCR_OPTION_LEVIREQ;

sys/bus/pccard/pccard.c

648

reg |= (PCCARD_CCR_OPTION_FUNC_ENABLE |

sys/bus/pccard/pccard.c

652

pccard_ccr_write(pf, PCCARD_CCR_OPTION, reg);

sys/bus/pccard/pccard.c

654

reg = 0;

sys/bus/pccard/pccard.c

656

reg |= PCCARD_CCR_STATUS_IOIS8;

sys/bus/pccard/pccard.c

658

reg |= PCCARD_CCR_STATUS_AUDIO;

sys/bus/pccard/pccard.c

659

pccard_ccr_write(pf, PCCARD_CCR_STATUS, reg);

sys/bus/pccard/pccard_cis.c

1010

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

1013

if ((reg & PCCARD_TPCE_TD_RESERVED_MASK) !=

sys/bus/pccard/pccard_cis.c

1016

if ((reg & PCCARD_TPCE_TD_RDYBSY_MASK) !=

sys/bus/pccard/pccard_cis.c

1019

if ((reg & PCCARD_TPCE_TD_WAIT_MASK) !=

sys/bus/pccard/pccard_cis.c

1029

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

1033

if (reg & PCCARD_TPCE_IO_BUSWIDTH_8BIT)

sys/bus/pccard/pccard_cis.c

1035

if (reg & PCCARD_TPCE_IO_BUSWIDTH_16BIT)

sys/bus/pccard/pccard_cis.c

1038

reg & PCCARD_TPCE_IO_IOADDRLINES_MASK;

sys/bus/pccard/pccard_cis.c

1040

if (reg & PCCARD_TPCE_IO_HASRANGE) {

sys/bus/pccard/pccard_cis.c

1041

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

1044

cfe->num_iospace = 1 + (reg &

sys/bus/pccard/pccard_cis.c

1057

switch (reg & PCCARD_TPCE_IO_RANGE_ADDRSIZE_MASK) {

sys/bus/pccard/pccard_cis.c

1074

switch (reg &

sys/bus/pccard/pccard_cis.c

1107

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

1112

if (reg & PCCARD_TPCE_IR_SHARE)

sys/bus/pccard/pccard_cis.c

1114

if (reg & PCCARD_TPCE_IR_PULSE)

sys/bus/pccard/pccard_cis.c

1116

if (reg & PCCARD_TPCE_IR_LEVEL)

sys/bus/pccard/pccard_cis.c

1119

if (reg & PCCARD_TPCE_IR_HASMASK) {

sys/bus/pccard/pccard_cis.c

1130

(1 << (reg & PCCARD_TPCE_IR_IRQ));

sys/bus/pccard/pccard_cis.c

1161

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

1164

cfe->num_memspace = (reg &

sys/bus/pccard/pccard_cis.c

1177

((reg & PCCARD_TPCE_MS_LENGTH_SIZE_MASK) >>

sys/bus/pccard/pccard_cis.c

1180

((reg & PCCARD_TPCE_MS_CARDADDR_SIZE_MASK) >>

sys/bus/pccard/pccard_cis.c

1183

(reg & PCCARD_TPCE_MS_HOSTADDR) ? cardaddrsize : 0;

sys/bus/pccard/pccard_cis.c

1230

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

1235

if (reg & PCCARD_TPCE_MI_PWRDOWN)

sys/bus/pccard/pccard_cis.c

1237

if (reg & PCCARD_TPCE_MI_READONLY)

sys/bus/pccard/pccard_cis.c

1239

if (reg & PCCARD_TPCE_MI_AUDIO)

sys/bus/pccard/pccard_cis.c

1241

cfe->maxtwins = reg & PCCARD_TPCE_MI_MAXTWINS;

sys/bus/pccard/pccard_cis.c

1243

while (reg & PCCARD_TPCE_MI_EXT) {

sys/bus/pccard/pccard_cis.c

1244

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

664

u_int reg, dtype, dspeed;

sys/bus/pccard/pccard_cis.c

666

reg = pccard_tuple_read_1(tuple, 0);

sys/bus/pccard/pccard_cis.c

667

dtype = reg & PCCARD_DTYPE_MASK;

sys/bus/pccard/pccard_cis.c

668

dspeed = reg & PCCARD_DSPEED_MASK;

sys/bus/pccard/pccard_cis.c

819

u_int reg, rasz, rmsz, rfsz;

sys/bus/pccard/pccard_cis.c

822

reg = pccard_tuple_read_1(tuple, 0);

sys/bus/pccard/pccard_cis.c

823

rasz = 1 + ((reg & PCCARD_TPCC_RASZ_MASK) >>

sys/bus/pccard/pccard_cis.c

825

rmsz = 1 + ((reg & PCCARD_TPCC_RMSZ_MASK) >>

sys/bus/pccard/pccard_cis.c

827

rfsz = ((reg & PCCARD_TPCC_RFSZ_MASK) >>

sys/bus/pccard/pccard_cis.c

874

u_int reg, reg2;

sys/bus/pccard/pccard_cis.c

881

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

883

intface = reg & PCCARD_TPCE_INDX_INTFACE;

sys/bus/pccard/pccard_cis.c

884

def = reg & PCCARD_TPCE_INDX_DEFAULT;

sys/bus/pccard/pccard_cis.c

885

num = reg & PCCARD_TPCE_INDX_NUM_MASK;

sys/bus/pccard/pccard_cis.c

958

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

964

if (reg & PCCARD_TPCE_IF_MWAIT)

sys/bus/pccard/pccard_cis.c

966

if (reg & PCCARD_TPCE_IF_RDYBSY)

sys/bus/pccard/pccard_cis.c

968

if (reg & PCCARD_TPCE_IF_WP)

sys/bus/pccard/pccard_cis.c

970

if (reg & PCCARD_TPCE_IF_BVD)

sys/bus/pccard/pccard_cis.c

972

cfe->iftype = reg & PCCARD_TPCE_IF_IFTYPE;

sys/bus/pccard/pccard_cis.c

974

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

977

power = reg & PCCARD_TPCE_FS_POWER_MASK;

sys/bus/pccard/pccard_cis.c

978

timing = reg & PCCARD_TPCE_FS_TIMING;

sys/bus/pccard/pccard_cis.c

979

iospace = reg & PCCARD_TPCE_FS_IOSPACE;

sys/bus/pccard/pccard_cis.c

980

irq = reg & PCCARD_TPCE_FS_IRQ;

sys/bus/pccard/pccard_cis.c

981

memspace = reg & PCCARD_TPCE_FS_MEMSPACE_MASK;

sys/bus/pccard/pccard_cis.c

982

misc = reg & PCCARD_TPCE_FS_MISC;

sys/bus/pccard/pccard_cis.c

988

reg = pccard_tuple_read_1(tuple, idx);

sys/bus/pccard/pccard_cis.c

993

if ((reg >> j) & 0x01) {

sys/bus/pci/hostb_pci.c

123

pci_hostb_read_config(device_t dev, device_t child, int reg, int width)

sys/bus/pci/hostb_pci.c

126

return (pci_read_config(dev, reg, width));

sys/bus/pci/hostb_pci.c

130

pci_hostb_write_config(device_t dev, device_t child, int reg,

sys/bus/pci/hostb_pci.c

134

pci_write_config(dev, reg, val, width);

sys/bus/pci/pci.c

102

int reg, uint32_t data);

sys/bus/pci/pci.c

2526

int b, int s, int f, int reg, struct resource_list *rl, int force,

sys/bus/pci/pci.c

2541

map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);

sys/bus/pci/pci.c

2551

PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);

sys/bus/pci/pci.c

2552

testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);

sys/bus/pci/pci.c

2553

PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);

sys/bus/pci/pci.c

2586

base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;

sys/bus/pci/pci.c

2589

reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);

sys/bus/pci/pci.c

2614

pci_get_domain(dev), b, s, f, reg);

sys/bus/pci/pci.c

2652

resource_list_add(rl, type, reg, start, end, count, -1);

sys/bus/pci/pci.c

2660

res = resource_list_alloc(rl, bus, dev, type, &reg, start, end, count,

sys/bus/pci/pci.c

2668

resource_list_delete(rl, type, reg);

sys/bus/pci/pci.c

2688

pci_write_config(dev, reg, start, 4);

sys/bus/pci/pci.c

2690

pci_write_config(dev, reg + 4, start >> 32, 4);

sys/bus/pci/pci.c

4139

pci_read_config_method(device_t dev, device_t child, int reg, int width)

sys/bus/pci/pci.c

4145

cfg->bus, cfg->slot, cfg->func, reg, width));

sys/bus/pci/pci.c

4149

pci_write_config_method(device_t dev, device_t child, int reg,

sys/bus/pci/pci.c

4156

cfg->bus, cfg->slot, cfg->func, reg, val, width);

sys/bus/pci/pci.c

85

int b, int s, int f, int reg,

sys/bus/pci/pci.c

921

pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)

sys/bus/pci/pci.c

925

KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));

sys/bus/pci/pci.c

927

WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);

sys/bus/pci/pci.c

941

pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)

sys/bus/pci/pci.c

945

KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));

sys/bus/pci/pci.c

948

WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);

sys/bus/pci/pci.c

973

uint32_t reg;

sys/bus/pci/pci.c

977

if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))

sys/bus/pci/pci.c

979

vrs->val = le32toh(reg);

sys/bus/pci/pci.c

99

int reg, uint32_t *data);

sys/bus/pci/pci_pci.c

555

pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)

sys/bus/pci/pci_pci.c

557

return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));

sys/bus/pci/pci_pci.c

561

pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)

sys/bus/pci/pci_pci.c

563

PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);

sys/bus/pci/pci_private.h

67

int reg, int width);

sys/bus/pci/pci_private.h

69

int reg, uint32_t val, int width);

sys/bus/pci/pcib_private.h

66

typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);

sys/bus/pci/pcib_private.h

77

uint32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);

sys/bus/pci/pcib_private.h

78

void pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width);

sys/bus/pci/pcivar.h

300

pci_read_config(device_t dev, int reg, int width)

sys/bus/pci/pcivar.h

302

return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);

sys/bus/pci/pcivar.h

306

pci_write_config(device_t dev, int reg, uint32_t val, int width)

sys/bus/pci/pcivar.h

308

PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);

sys/bus/pci/vga_pci.c

497

vga_pci_read_config(device_t dev, device_t child, int reg, int width)

sys/bus/pci/vga_pci.c

500

return (pci_read_config(dev, reg, width));

sys/bus/pci/vga_pci.c

504

vga_pci_write_config(device_t dev, device_t child, int reg,

sys/bus/pci/vga_pci.c

508

pci_write_config(dev, reg, val, width);

sys/bus/pci/x86_64/legacyvar.h

47

int reg, int bytes);

sys/bus/pci/x86_64/legacyvar.h

51

int reg, u_int32_t data, int bytes);

sys/bus/pci/x86_64/pci_bus.c

63

int reg, int bytes)

sys/bus/pci/x86_64/pci_bus.c

65

return(pci_cfgregread(bus, slot, func, reg, bytes));

sys/bus/pci/x86_64/pci_bus.c

72

int reg, u_int32_t data, int bytes)

sys/bus/pci/x86_64/pci_bus.c

74

pci_cfgregwrite(bus, slot, func, reg, data, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

129

pci_docfgregread(int bus, int slot, int func, int reg, int bytes)

sys/bus/pci/x86_64/pci_cfgreg.c

134

return pciereg_cfgread(bus, slot, func, reg, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

136

return pcireg_cfgread(bus, slot, func, reg, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

143

pci_cfgregread(int bus, int slot, int func, int reg, int bytes)

sys/bus/pci/x86_64/pci_cfgreg.c

152

if (reg == PCIR_INTLINE && bytes == 1) {

sys/bus/pci/x86_64/pci_cfgreg.c

160

return pci_docfgregread(bus, slot, func, reg, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

167

pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)

sys/bus/pci/x86_64/pci_cfgreg.c

172

pciereg_cfgwrite(bus, slot, func, reg, data, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

174

pcireg_cfgwrite(bus, slot, func, reg, data, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

183

pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)

sys/bus/pci/x86_64/pci_cfgreg.c

190

(unsigned)reg <= PCI_REGMAX &&

sys/bus/pci/x86_64/pci_cfgreg.c

193

(reg & (bytes - 1)) == 0) {

sys/bus/pci/x86_64/pci_cfgreg.c

195

(func << 8) | (reg & ~0x03));

sys/bus/pci/x86_64/pci_cfgreg.c

196

dataport = CONF1_DATA_PORT + (reg & 0x03);

sys/bus/pci/x86_64/pci_cfgreg.c

212

pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)

sys/bus/pci/x86_64/pci_cfgreg.c

218

port = pci_cfgenable(bus, slot, func, reg, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

238

pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)

sys/bus/pci/x86_64/pci_cfgreg.c

243

port = pci_cfgenable(bus, slot, func, reg, bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

308

#define PCIE_VADDR(base, reg, bus, slot, func) \

sys/bus/pci/x86_64/pci_cfgreg.c

313

((reg) & 0xfff)))

sys/bus/pci/x86_64/pci_cfgreg.c

316

pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,

sys/bus/pci/x86_64/pci_cfgreg.c

323

func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/bus/pci/x86_64/pci_cfgreg.c

326

va = PCIE_VADDR(pcie_base, reg, bus, slot, func);

sys/bus/pci/x86_64/pci_cfgreg.c

343

pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,

sys/bus/pci/x86_64/pci_cfgreg.c

349

func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/bus/pci/x86_64/pci_cfgreg.c

352

va = PCIE_VADDR(pcie_base, reg, bus, slot, func);

sys/bus/pci/x86_64/pci_cfgreg.c

68

static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, int bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

70

static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

71

static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data,

sys/bus/pci/x86_64/pci_cfgreg.c

75

unsigned reg, unsigned bytes);

sys/bus/pci/x86_64/pci_cfgreg.c

77

unsigned reg, int data, unsigned bytes);

sys/bus/pci/x86_64/pci_cfgreg.h

51

u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);

sys/bus/pci/x86_64/pci_cfgreg.h

52

void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);

sys/bus/ppbus/ppb_msq.h

110

#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ reg }, { assert }, { clear }}}

sys/bus/ppbus/ppb_msq.h

111

#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { reg }, { byte }}}

sys/bus/ppbus/ppb_msq.h

112

#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ reg }, { MS_ASSERT_NONE }, { clear }}}

sys/bus/ppbus/ppb_msq.h

114

#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ reg }, { mask }, { ptr }}}

sys/bus/ppbus/ppb_msq.h

117

#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ reg }, { len }, { array }}}

sys/bus/ppbus/ppb_msq.h

120

#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ n }, { reg }}}

sys/bus/ppbus/ppb_msq.h

121

#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ n }, { reg }, { mask }}}

sys/bus/smbus/ichiic/ig4_iic.c

1002

#define REGDUMP(sc, reg) \

sys/bus/smbus/ichiic/ig4_iic.c

1003

device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))

sys/bus/smbus/ichiic/ig4_iic.c

77

reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)

sys/bus/smbus/ichiic/ig4_iic.c

79

bus_space_write_4(sc->regs_t, sc->regs_h, reg, value);

sys/bus/smbus/ichiic/ig4_iic.c

80

bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4,

sys/bus/smbus/ichiic/ig4_iic.c

86

reg_read(ig4iic_softc_t *sc, uint32_t reg)

sys/bus/smbus/ichiic/ig4_iic.c

90

bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4,

sys/bus/smbus/ichiic/ig4_iic.c

92

value = bus_space_read_4(sc->regs_t, sc->regs_h, reg);

sys/bus/u4b/controller/ohci_pci.c

102

reg = pci_read_config(self, PCI_CBMEM, 4);

sys/bus/u4b/controller/ohci_pci.c

105

pci_write_config(self, PCI_CBMEM, reg, 4);

sys/bus/u4b/controller/ohci_pci.c

95

uint32_t reg;

sys/bus/u4b/net/if_aue.c

292

#define AUE_SETBIT(sc, reg, x) \

sys/bus/u4b/net/if_aue.c

293

aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x))

sys/bus/u4b/net/if_aue.c

295

#define AUE_CLRBIT(sc, reg, x) \

sys/bus/u4b/net/if_aue.c

296

aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x))

sys/bus/u4b/net/if_aue.c

299

aue_csr_read_1(struct aue_softc *sc, uint16_t reg)

sys/bus/u4b/net/if_aue.c

308

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_aue.c

318

aue_csr_read_2(struct aue_softc *sc, uint16_t reg)

sys/bus/u4b/net/if_aue.c

327

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_aue.c

337

aue_csr_write_1(struct aue_softc *sc, uint16_t reg, uint8_t val)

sys/bus/u4b/net/if_aue.c

345

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_aue.c

354

aue_csr_write_2(struct aue_softc *sc, uint16_t reg, uint16_t val)

sys/bus/u4b/net/if_aue.c

361

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_aue.c

412

aue_miibus_readreg(device_t dev, int phy, int reg)

sys/bus/u4b/net/if_aue.c

438

aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ);

sys/bus/u4b/net/if_aue.c

459

aue_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/bus/u4b/net/if_aue.c

474

aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE);

sys/bus/u4b/net/if_axe.c

312

axe_miibus_readreg(device_t dev, int phy, int reg)

sys/bus/u4b/net/if_axe.c

329

axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);

sys/bus/u4b/net/if_axe.c

333

if (AXE_IS_772(sc) && reg == MII_BMSR) {

sys/bus/u4b/net/if_axe.c

349

axe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/bus/u4b/net/if_axe.c

360

axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);

sys/bus/u4b/net/if_axge.c

243

axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)

sys/bus/u4b/net/if_axge.c

247

axge_read_mem(sc, cmd, 1, reg, &val, 1);

sys/bus/u4b/net/if_axge.c

253

uint16_t reg)

sys/bus/u4b/net/if_axge.c

257

axge_read_mem(sc, cmd, index, reg, &val, 2);

sys/bus/u4b/net/if_axge.c

262

axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)

sys/bus/u4b/net/if_axge.c

264

axge_write_mem(sc, cmd, 1, reg, &val, 1);

sys/bus/u4b/net/if_axge.c

269

uint16_t reg, uint16_t val)

sys/bus/u4b/net/if_axge.c

274

axge_write_mem(sc, cmd, index, reg, &temp, 2);

sys/bus/u4b/net/if_axge.c

278

axge_miibus_readreg(device_t dev, int phy, int reg)

sys/bus/u4b/net/if_axge.c

289

val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);

sys/bus/u4b/net/if_axge.c

298

axge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/bus/u4b/net/if_axge.c

310

axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);

sys/bus/u4b/net/if_cue.c

188

#define CUE_SETBIT(sc, reg, x) \

sys/bus/u4b/net/if_cue.c

189

cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) | (x))

sys/bus/u4b/net/if_cue.c

191

#define CUE_CLRBIT(sc, reg, x) \

sys/bus/u4b/net/if_cue.c

192

cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) & ~(x))

sys/bus/u4b/net/if_cue.c

195

cue_csr_read_1(struct cue_softc *sc, uint16_t reg)

sys/bus/u4b/net/if_cue.c

203

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_cue.c

213

cue_csr_read_2(struct cue_softc *sc, uint8_t reg)

sys/bus/u4b/net/if_cue.c

221

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_cue.c

229

cue_csr_write_1(struct cue_softc *sc, uint16_t reg, uint16_t val)

sys/bus/u4b/net/if_cue.c

236

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_mos.c

262

mos_reg_read_1(struct mos_softc *sc, int reg)

sys/bus/u4b/net/if_mos.c

271

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_mos.c

277

MOS_DPRINTFN("mos_reg_read_1 error, reg: %d\n", reg);

sys/bus/u4b/net/if_mos.c

284

mos_reg_read_2(struct mos_softc *sc, int reg)

sys/bus/u4b/net/if_mos.c

295

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_mos.c

301

MOS_DPRINTFN("mos_reg_read_2 error, reg: %d", reg);

sys/bus/u4b/net/if_mos.c

308

mos_reg_write_1(struct mos_softc *sc, int reg, int aval)

sys/bus/u4b/net/if_mos.c

318

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_mos.c

324

MOS_DPRINTFN("mos_reg_write_1 error, reg: %d", reg);

sys/bus/u4b/net/if_mos.c

331

mos_reg_write_2(struct mos_softc *sc, int reg, int aval)

sys/bus/u4b/net/if_mos.c

342

USETW(req.wIndex, reg);

sys/bus/u4b/net/if_mos.c

348

MOS_DPRINTFN("mos_reg_write_2 error, reg: %d", reg);

sys/bus/u4b/net/if_mos.c

417

mos_miibus_readreg(device_t dev, int phy, int reg)

sys/bus/u4b/net/if_mos.c

432

mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |

sys/bus/u4b/net/if_mos.c

450

mos_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/bus/u4b/net/if_mos.c

462

mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |

sys/bus/u4b/net/if_udav.c

199

#define UDAV_SETBIT(sc, reg, x) \

sys/bus/u4b/net/if_udav.c

200

udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) | (x))

sys/bus/u4b/net/if_udav.c

202

#define UDAV_CLRBIT(sc, reg, x) \

sys/bus/u4b/net/if_udav.c

203

udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) & ~(x))

sys/bus/u4b/net/if_udav.c

797

udav_miibus_readreg(device_t dev, int phy, int reg)

sys/bus/u4b/net/if_udav.c

814

UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));

sys/bus/u4b/net/if_udav.c

830

phy, reg, data16);

sys/bus/u4b/net/if_udav.c

838

udav_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/bus/u4b/net/if_udav.c

854

UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));

sys/bus/u4b/net/ruephy.c

119

int reg;

sys/bus/u4b/net/ruephy.c

153

reg = PHY_READ(sc, RUEPHY_MII_MSR) |

sys/bus/u4b/net/ruephy.c

155

if (reg & RUEPHY_MSR_LINK)

sys/bus/u4b/serial/umcs.c

915

umcs7840_get_reg_sync(struct umcs7840_softc *sc, uint8_t reg, uint8_t *data)

sys/bus/u4b/serial/umcs.c

924

USETW(req.wIndex, reg);

sys/bus/u4b/serial/umcs.c

929

device_printf(sc->sc_dev, "Reading register %d failed: invalid length %d\n", reg, len);

sys/bus/u4b/serial/umcs.c

932

device_printf(sc->sc_dev, "Reading register %d failed: %s\n", reg, usbd_errstr(err));

sys/bus/u4b/serial/umcs.c

937

umcs7840_set_reg_sync(struct umcs7840_softc *sc, uint8_t reg, uint8_t data)

sys/bus/u4b/serial/umcs.c

945

USETW(req.wIndex, reg);

sys/bus/u4b/serial/umcs.c

950

device_printf(sc->sc_dev, "Writing register %d failed: %s\n", reg, usbd_errstr(err));

sys/bus/u4b/serial/umcs.c

956

umcs7840_get_UART_reg_sync(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t *data)

sys/bus/u4b/serial/umcs.c

969

USETW(req.wIndex, reg);

sys/bus/u4b/serial/umcs.c

974

device_printf(sc->sc_dev, "Reading UART%d register %d failed: invalid length %d\n", portno, reg, len);

sys/bus/u4b/serial/umcs.c

977

device_printf(sc->sc_dev, "Reading UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err));

sys/bus/u4b/serial/umcs.c

982

umcs7840_set_UART_reg_sync(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t data)

sys/bus/u4b/serial/umcs.c

994

USETW(req.wIndex, reg);

sys/bus/u4b/serial/umcs.c

999

device_printf(sc->sc_dev, "Writing UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err));

sys/bus/u4b/serial/umoscom.c

525

umoscom_cfg_write(struct umoscom_softc *sc, uint16_t reg, uint16_t val)

sys/bus/u4b/serial/umoscom.c

532

USETW(req.wIndex, reg);

sys/bus/u4b/serial/umoscom.c

540

umoscom_cfg_read(struct umoscom_softc *sc, uint16_t reg)

sys/bus/u4b/serial/umoscom.c

548

USETW(req.wIndex, reg);

sys/bus/u4b/serial/umoscom.c

554

DPRINTF("reg=0x%04x, val=0x%02x\n", reg, val);

sys/bus/u4b/wlan/if_mtw.c

1009

mtw_write_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t val)

sys/bus/u4b/wlan/if_mtw.c

1017

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_mtw.c

1276

mtw_read(struct mtw_softc *sc, uint16_t reg, uint32_t *val)

sys/bus/u4b/wlan/if_mtw.c

1281

error = mtw_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);

sys/bus/u4b/wlan/if_mtw.c

1290

mtw_read_region_1(struct mtw_softc *sc, uint16_t reg, uint8_t *buf, int len)

sys/bus/u4b/wlan/if_mtw.c

1297

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_mtw.c

1304

mtw_write_2(struct mtw_softc *sc, uint16_t reg, uint16_t val)

sys/bus/u4b/wlan/if_mtw.c

1311

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_mtw.c

1317

mtw_write(struct mtw_softc *sc, uint16_t reg, uint32_t val)

sys/bus/u4b/wlan/if_mtw.c

1322

if ((error = mtw_write_2(sc, reg, val & 0xffff)) == 0) {

sys/bus/u4b/wlan/if_mtw.c

1324

error = mtw_write_2(sc, reg + 2, val >> 16);

sys/bus/u4b/wlan/if_mtw.c

1331

mtw_write_region_1(struct mtw_softc *sc, uint16_t reg, uint8_t *buf, int len)

sys/bus/u4b/wlan/if_mtw.c

1338

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_mtw.c

1344

mtw_set_region_4(struct mtw_softc *sc, uint16_t reg, uint32_t val, int count)

sys/bus/u4b/wlan/if_mtw.c

1350

error = mtw_write(sc, reg + i, val);

sys/bus/u4b/wlan/if_mtw.c

1359

uint16_t reg;

sys/bus/u4b/wlan/if_mtw.c

1391

reg = MTW_EFUSE_DATA0 + (addr & 0xc);

sys/bus/u4b/wlan/if_mtw.c

1392

if ((error = mtw_read(sc, reg, &tmp)) != 0)

sys/bus/u4b/wlan/if_mtw.c

1407

mtw_bbp_read(struct mtw_softc *sc, uint8_t reg, uint8_t *val)

sys/bus/u4b/wlan/if_mtw.c

1421

tmp = MTW_BBP_CSR_READ | MTW_BBP_CSR_KICK | reg << 8;

sys/bus/u4b/wlan/if_mtw.c

1439

mtw_bbp_write(struct mtw_softc *sc, uint8_t reg, uint8_t val)

sys/bus/u4b/wlan/if_mtw.c

1453

tmp = MTW_BBP_CSR_KICK | reg << 8 | val;

sys/bus/u4b/wlan/if_mtw.c

1625

uint32_t reg;

sys/bus/u4b/wlan/if_mtw.c

1628

reg = val;

sys/bus/u4b/wlan/if_mtw.c

1630

reg |= (uint32_t)val << 16;

sys/bus/u4b/wlan/if_mtw.c

1632

sc->txpow20mhz[ridx] = reg;

sys/bus/u4b/wlan/if_mtw.c

1633

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/bus/u4b/wlan/if_mtw.c

1634

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/bus/u4b/wlan/if_mtw.c

267

uint8_t reg;

sys/bus/u4b/wlan/if_mtw.c

273

uint32_t reg;

sys/bus/u4b/wlan/if_mtw.c

277

uint8_t reg;

sys/bus/u4b/wlan/if_mtw.c

3595

mtw_rf_write(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t val)

sys/bus/u4b/wlan/if_mtw.c

3615

reg << 8 | val;

sys/bus/u4b/wlan/if_mtw.c

3657

mtw_rf_read(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t *val)

sys/bus/u4b/wlan/if_mtw.c

3676

tmp = MTW_RF_CSR_KICK | (bank & 0xf) << shift | reg << 8;

sys/bus/u4b/wlan/if_mtw.c

4198

if ((error = mtw_bbp_write(sc, mt7601_def_bbp[i].reg,

sys/bus/u4b/wlan/if_mtw.c

4215

error = mtw_rf_write(sc, 0, mt7601_rf_bank0[i].reg,

sys/bus/u4b/wlan/if_mtw.c

4222

error = mtw_rf_write(sc, 4, mt7601_rf_bank4[i].reg,

sys/bus/u4b/wlan/if_mtw.c

4229

error = mtw_rf_write(sc, 5, mt7601_rf_bank5[i].reg,

sys/bus/u4b/wlan/if_mtw.c

4493

mtw_write(sc, mt7601_def_mac[i].reg,

sys/bus/u4b/wlan/if_mtw.c

482

mtw_read_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t *val)

sys/bus/u4b/wlan/if_mtw.c

492

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_rum.c

1788

rum_read(struct rum_softc *sc, uint16_t reg)

sys/bus/u4b/wlan/if_rum.c

1792

rum_read_multi(sc, reg, &val, sizeof val);

sys/bus/u4b/wlan/if_rum.c

1798

rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)

sys/bus/u4b/wlan/if_rum.c

1806

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_rum.c

1818

rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)

sys/bus/u4b/wlan/if_rum.c

1822

return (rum_write_multi(sc, reg, &tmp, sizeof tmp));

sys/bus/u4b/wlan/if_rum.c

1826

rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len)

sys/bus/u4b/wlan/if_rum.c

1838

USETW(req.wIndex, reg + offset);

sys/bus/u4b/wlan/if_rum.c

1854

rum_setbits(struct rum_softc *sc, uint16_t reg, uint32_t mask)

sys/bus/u4b/wlan/if_rum.c

1856

return (rum_write(sc, reg, rum_read(sc, reg) | mask));

sys/bus/u4b/wlan/if_rum.c

1860

rum_clrbits(struct rum_softc *sc, uint16_t reg, uint32_t mask)

sys/bus/u4b/wlan/if_rum.c

1862

return (rum_write(sc, reg, rum_read(sc, reg) & ~mask));

sys/bus/u4b/wlan/if_rum.c

1866

rum_modbits(struct rum_softc *sc, uint16_t reg, uint32_t set, uint32_t unset)

sys/bus/u4b/wlan/if_rum.c

1868

return (rum_write(sc, reg, (rum_read(sc, reg) & ~unset) | set));

sys/bus/u4b/wlan/if_rum.c

1889

rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)

sys/bus/u4b/wlan/if_rum.c

1893

DPRINTFN(2, "reg=0x%08x\n", reg);

sys/bus/u4b/wlan/if_rum.c

1900

tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;

sys/bus/u4b/wlan/if_rum.c

1905

rum_bbp_read(struct rum_softc *sc, uint8_t reg)

sys/bus/u4b/wlan/if_rum.c

1910

DPRINTFN(2, "reg=0x%08x\n", reg);

sys/bus/u4b/wlan/if_rum.c

1917

val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;

sys/bus/u4b/wlan/if_rum.c

1933

rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)

sys/bus/u4b/wlan/if_rum.c

1950

(reg & 3);

sys/bus/u4b/wlan/if_rum.c

1954

sc->rf_regs[reg] = val;

sys/bus/u4b/wlan/if_rum.c

1956

DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff);

sys/bus/u4b/wlan/if_rum.c

2452

if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)

sys/bus/u4b/wlan/if_rum.c

2454

DPRINTF("BBP R%d=%02x\n", sc->bbp_prom[i].reg,

sys/bus/u4b/wlan/if_rum.c

2501

rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);

sys/bus/u4b/wlan/if_rum.c

2505

if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)

sys/bus/u4b/wlan/if_rum.c

2507

rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/bus/u4b/wlan/if_rum.c

2537

rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);

sys/bus/u4b/wlan/if_rum.c

2638

uint16_t reg = RT2573_MCU_CODE_BASE;

sys/bus/u4b/wlan/if_rum.c

2642

for (; size >= 4; reg += 4, ucode += 4, size -= 4) {

sys/bus/u4b/wlan/if_rum.c

2643

err = rum_write(sc, reg, UGETDW(ucode));

sys/bus/u4b/wlan/if_rum.c

267

uint32_t reg;

sys/bus/u4b/wlan/if_rum.c

295

uint8_t reg;

sys/bus/u4b/wlan/if_rumvar.h

158

uint8_t reg;

sys/bus/u4b/wlan/if_run.c

1245

run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)

sys/bus/u4b/wlan/if_run.c

1250

error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);

sys/bus/u4b/wlan/if_run.c

1259

run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len)

sys/bus/u4b/wlan/if_run.c

1266

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_run.c

1273

run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val)

sys/bus/u4b/wlan/if_run.c

1280

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_run.c

1287

run_write(struct run_softc *sc, uint16_t reg, uint32_t val)

sys/bus/u4b/wlan/if_run.c

1291

if ((error = run_write_2(sc, reg, val & 0xffff)) == 0)

sys/bus/u4b/wlan/if_run.c

1292

error = run_write_2(sc, reg + 2, val >> 16);

sys/bus/u4b/wlan/if_run.c

1297

run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf,

sys/bus/u4b/wlan/if_run.c

1308

error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8);

sys/bus/u4b/wlan/if_run.c

1328

USETW(req.wIndex, reg);

sys/bus/u4b/wlan/if_run.c

1333

reg += delta;

sys/bus/u4b/wlan/if_run.c

1342

run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int len)

sys/bus/u4b/wlan/if_run.c

1348

error = run_write(sc, reg + i, val);

sys/bus/u4b/wlan/if_run.c

1356

uint16_t reg;

sys/bus/u4b/wlan/if_run.c

1389

reg = RT3070_EFUSE_DATA3 - (addr & 0xc);

sys/bus/u4b/wlan/if_run.c

1390

if ((error = run_read(sc, reg, &tmp)) != 0)

sys/bus/u4b/wlan/if_run.c

1454

run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val)

sys/bus/u4b/wlan/if_run.c

1469

tmp = RT3070_RF_KICK | reg << 8;

sys/bus/u4b/wlan/if_run.c

1487

run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val)

sys/bus/u4b/wlan/if_run.c

1501

tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;

sys/bus/u4b/wlan/if_run.c

1506

run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val)

sys/bus/u4b/wlan/if_run.c

1520

tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8;

sys/bus/u4b/wlan/if_run.c

1538

run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val)

sys/bus/u4b/wlan/if_run.c

1552

tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;

sys/bus/u4b/wlan/if_run.c

1779

sc->bbp[i].reg = val >> 8;

sys/bus/u4b/wlan/if_run.c

1780

DPRINTF("BBP%d=0x%02x\n", sc->bbp[i].reg,

sys/bus/u4b/wlan/if_run.c

1789

sc->rf[i].reg = val >> 8;

sys/bus/u4b/wlan/if_run.c

1790

DPRINTF("RF%d=0x%02x\n", sc->rf[i].reg,

sys/bus/u4b/wlan/if_run.c

1900

uint32_t reg;

sys/bus/u4b/wlan/if_run.c

1903

reg = val;

sys/bus/u4b/wlan/if_run.c

1905

reg |= (uint32_t)val << 16;

sys/bus/u4b/wlan/if_run.c

1907

sc->txpow20mhz[ridx] = reg;

sys/bus/u4b/wlan/if_run.c

1908

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/bus/u4b/wlan/if_run.c

1909

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/bus/u4b/wlan/if_run.c

4606

uint8_t reg, rf, txpow_bound;

sys/bus/u4b/wlan/if_run.c

4659

run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

4673

reg = 2;

sys/bus/u4b/wlan/if_run.c

4678

run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

4684

run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg,

sys/bus/u4b/wlan/if_run.c

4693

reg = 3;

sys/bus/u4b/wlan/if_run.c

4700

rf |= (reg << 6);

sys/bus/u4b/wlan/if_run.c

4709

rf |= (reg << 6);

sys/bus/u4b/wlan/if_run.c

485

uint16_t reg;

sys/bus/u4b/wlan/if_run.c

492

uint8_t reg;

sys/bus/u4b/wlan/if_run.c

5275

run_bbp_write(sc, rt5592_def_bbp[i].reg,

sys/bus/u4b/wlan/if_run.c

5284

run_bbp_write(sc, rt5390_def_bbp[i].reg,

sys/bus/u4b/wlan/if_run.c

5337

run_bbp_write(sc, rt2860_def_bbp[i].reg,

sys/bus/u4b/wlan/if_run.c

5382

run_rt3070_rf_write(sc, rt3572_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

5387

run_rt3070_rf_write(sc, rt3070_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

540

uint8_t reg;

sys/bus/u4b/wlan/if_run.c

5524

run_rt3070_rf_write(sc, rt3593_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

5580

run_rt3070_rf_write(sc, rt5592_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

5587

run_rt3070_rf_write(sc, rt5392_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

5600

run_rt3070_rf_write(sc, rt5390_def_rf[i].reg,

sys/bus/u4b/wlan/if_run.c

563

uint8_t reg;

sys/bus/u4b/wlan/if_run.c

5760

if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)

sys/bus/u4b/wlan/if_run.c

5762

run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);

sys/bus/u4b/wlan/if_run.c

6018

run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val);

sys/bus/u4b/wlan/if_run.c

6098

if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)

sys/bus/u4b/wlan/if_run.c

6100

run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);

sys/bus/u4b/wlan/if_runvar.h

208

uint8_t reg;

sys/bus/u4b/wlan/if_urtwn.c

1670

uint32_t reg[R92C_MAX_CHAINS], val;

sys/bus/u4b/wlan/if_urtwn.c

1672

reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));

sys/bus/u4b/wlan/if_urtwn.c

1674

reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));

sys/bus/u4b/wlan/if_urtwn.c

1677

reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);

sys/bus/u4b/wlan/if_urtwn.c

1681

RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |

sys/bus/u4b/wlan/if_urtwn.c

1686

reg[0] | R92C_HSSI_PARAM2_READ_EDGE);

sys/bus/u4b/wlan/if_urtwn.c

1721

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

1728

reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

1729

reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr);

sys/bus/u4b/wlan/if_urtwn.c

1730

reg &= ~R92C_EFUSE_CTRL_VALID;

sys/bus/u4b/wlan/if_urtwn.c

1732

error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

1737

reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

1738

if (reg & R92C_EFUSE_CTRL_VALID)

sys/bus/u4b/wlan/if_urtwn.c

1749

*val = MS(reg, R92C_EFUSE_CTRL_DATA);

sys/bus/u4b/wlan/if_urtwn.c

1759

uint8_t reg;

sys/bus/u4b/wlan/if_urtwn.c

1765

error = urtwn_efuse_read_next(sc, &reg);

sys/bus/u4b/wlan/if_urtwn.c

1769

off * 8 + i * 2, reg);

sys/bus/u4b/wlan/if_urtwn.c

1770

rom[off * 8 + i * 2 + 0] = reg;

sys/bus/u4b/wlan/if_urtwn.c

1772

error = urtwn_efuse_read_next(sc, &reg);

sys/bus/u4b/wlan/if_urtwn.c

1776

off * 8 + i * 2 + 1, reg);

sys/bus/u4b/wlan/if_urtwn.c

1777

rom[off * 8 + i * 2 + 1] = reg;

sys/bus/u4b/wlan/if_urtwn.c

1810

uint8_t msk, off, reg;

sys/bus/u4b/wlan/if_urtwn.c

1819

URTWN_CHK(urtwn_efuse_read_next(sc, &reg));

sys/bus/u4b/wlan/if_urtwn.c

1820

while (reg != 0xff) {

sys/bus/u4b/wlan/if_urtwn.c

1822

if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) {

sys/bus/u4b/wlan/if_urtwn.c

1823

off = reg >> 5;

sys/bus/u4b/wlan/if_urtwn.c

1824

URTWN_CHK(urtwn_efuse_read_next(sc, &reg));

sys/bus/u4b/wlan/if_urtwn.c

1826

if ((reg & 0x0f) != 0x0f)

sys/bus/u4b/wlan/if_urtwn.c

1827

off = ((reg & 0xf0) >> 1) | off;

sys/bus/u4b/wlan/if_urtwn.c

1831

off = reg >> 4;

sys/bus/u4b/wlan/if_urtwn.c

1832

msk = reg & 0xf;

sys/bus/u4b/wlan/if_urtwn.c

1835

URTWN_CHK(urtwn_efuse_read_next(sc, &reg));

sys/bus/u4b/wlan/if_urtwn.c

1860

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

1866

reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

1867

if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {

sys/bus/u4b/wlan/if_urtwn.c

1869

reg | R92C_SYS_ISO_CTRL_PWC_EV12V);

sys/bus/u4b/wlan/if_urtwn.c

1873

reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/bus/u4b/wlan/if_urtwn.c

1874

if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {

sys/bus/u4b/wlan/if_urtwn.c

1876

reg | R92C_SYS_FUNC_EN_ELDR);

sys/bus/u4b/wlan/if_urtwn.c

1880

reg = urtwn_read_2(sc, R92C_SYS_CLKR);

sys/bus/u4b/wlan/if_urtwn.c

1881

if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=

sys/bus/u4b/wlan/if_urtwn.c

1884

reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);

sys/bus/u4b/wlan/if_urtwn.c

1895

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

1900

reg = urtwn_read_4(sc, R92C_SYS_CFG);

sys/bus/u4b/wlan/if_urtwn.c

1901

if (reg & R92C_SYS_CFG_TRP_VAUX_EN)

sys/bus/u4b/wlan/if_urtwn.c

1904

if (reg & R92C_SYS_CFG_TYPE_92C) {

sys/bus/u4b/wlan/if_urtwn.c

1912

if (reg & R92C_SYS_CFG_VENDOR_UMC) {

sys/bus/u4b/wlan/if_urtwn.c

1914

if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)

sys/bus/u4b/wlan/if_urtwn.c

2400

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

2404

reg = urtwn_read_1(sc, R92C_BCN_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

2410

reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0;

sys/bus/u4b/wlan/if_urtwn.c

2411

urtwn_write_1(sc, R92C_BCN_CTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

2417

reg |= R92C_BCN_CTRL_DIS_TSF_UDT0;

sys/bus/u4b/wlan/if_urtwn.c

2418

urtwn_write_1(sc, R92C_BCN_CTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

2426

reg |= R92C_BCN_CTRL_EN_BCN;

sys/bus/u4b/wlan/if_urtwn.c

2428

urtwn_write_1(sc, R92C_BCN_CTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

2475

uint8_t reg;

sys/bus/u4b/wlan/if_urtwn.c

2479

reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;

sys/bus/u4b/wlan/if_urtwn.c

2480

urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);

sys/bus/u4b/wlan/if_urtwn.c

2482

reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;

sys/bus/u4b/wlan/if_urtwn.c

2484

reg | R92C_LEDCFG0_DIS);

sys/bus/u4b/wlan/if_urtwn.c

2490

reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;

sys/bus/u4b/wlan/if_urtwn.c

2492

reg |= R92C_LEDCFG0_DIS;

sys/bus/u4b/wlan/if_urtwn.c

2493

urtwn_write_1(sc, R92C_LEDCFG0, reg);

sys/bus/u4b/wlan/if_urtwn.c

2502

uint8_t reg;

sys/bus/u4b/wlan/if_urtwn.c

2504

reg = urtwn_read_1(sc, R92C_MSR);

sys/bus/u4b/wlan/if_urtwn.c

2505

reg = (reg & ~R92C_MSR_MASK) | mode;

sys/bus/u4b/wlan/if_urtwn.c

2506

urtwn_write_1(sc, R92C_MSR, reg);

sys/bus/u4b/wlan/if_urtwn.c

2543

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

2657

reg = urtwn_read_4(sc, R92C_RCR);

sys/bus/u4b/wlan/if_urtwn.c

2660

reg |= R92C_RCR_CBSSID_DATA;

sys/bus/u4b/wlan/if_urtwn.c

2662

reg |= R92C_RCR_CBSSID_BCN;

sys/bus/u4b/wlan/if_urtwn.c

2664

urtwn_write_4(sc, R92C_RCR, reg);

sys/bus/u4b/wlan/if_urtwn.c

3324

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3350

reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

3351

if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {

sys/bus/u4b/wlan/if_urtwn.c

3353

reg | R92C_LDOV12D_CTRL_LDV12_EN);

sys/bus/u4b/wlan/if_urtwn.c

3412

reg = urtwn_read_2(sc, R92C_CR);

sys/bus/u4b/wlan/if_urtwn.c

3413

reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/bus/u4b/wlan/if_urtwn.c

3417

error = urtwn_write_2(sc, R92C_CR, reg);

sys/bus/u4b/wlan/if_urtwn.c

3430

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3494

reg = urtwn_read_2(sc, R92C_CR);

sys/bus/u4b/wlan/if_urtwn.c

3495

reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/bus/u4b/wlan/if_urtwn.c

3498

error = urtwn_write_2(sc, R92C_CR, reg);

sys/bus/u4b/wlan/if_urtwn.c

3515

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3585

reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;

sys/bus/u4b/wlan/if_urtwn.c

3586

reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;

sys/bus/u4b/wlan/if_urtwn.c

3587

urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

3592

reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;

sys/bus/u4b/wlan/if_urtwn.c

3593

reg |= (((reg & 0x000f) << 4) | 0x0780);

sys/bus/u4b/wlan/if_urtwn.c

3594

urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);

sys/bus/u4b/wlan/if_urtwn.c

3643

uint8_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3751

reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1);

sys/bus/u4b/wlan/if_urtwn.c

3752

urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);

sys/bus/u4b/wlan/if_urtwn.c

3753

urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);

sys/bus/u4b/wlan/if_urtwn.c

3803

uint16_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3811

reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/bus/u4b/wlan/if_urtwn.c

3812

if (!(reg & R92C_SYS_FUNC_EN_CPUEN))

sys/bus/u4b/wlan/if_urtwn.c

3817

urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);

sys/bus/u4b/wlan/if_urtwn.c

3823

uint16_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3825

reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/bus/u4b/wlan/if_urtwn.c

3826

urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);

sys/bus/u4b/wlan/if_urtwn.c

3827

urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);

sys/bus/u4b/wlan/if_urtwn.c

3833

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3837

reg = urtwn_read_4(sc, R92C_MCUFWDL);

sys/bus/u4b/wlan/if_urtwn.c

3838

reg = RW(reg, R92C_MCUFWDL_PAGE, page);

sys/bus/u4b/wlan/if_urtwn.c

3839

urtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/bus/u4b/wlan/if_urtwn.c

3869

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

3961

reg = urtwn_read_4(sc, R92C_MCUFWDL);

sys/bus/u4b/wlan/if_urtwn.c

3962

reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;

sys/bus/u4b/wlan/if_urtwn.c

3963

urtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/bus/u4b/wlan/if_urtwn.c

3989

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4084

reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

4085

reg &= ~R92C_TRXDMA_CTRL_QMAP_M;

sys/bus/u4b/wlan/if_urtwn.c

4088

reg |= R92C_TRXDMA_CTRL_QMAP_HQ;

sys/bus/u4b/wlan/if_urtwn.c

4090

reg |= R92C_TRXDMA_CTRL_QMAP_NQ;

sys/bus/u4b/wlan/if_urtwn.c

4092

reg |= R92C_TRXDMA_CTRL_QMAP_LQ;

sys/bus/u4b/wlan/if_urtwn.c

4098

reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;

sys/bus/u4b/wlan/if_urtwn.c

4100

reg |= R92C_TRXDMA_CTRL_QMAP_3EP;

sys/bus/u4b/wlan/if_urtwn.c

4101

usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

4130

error = urtwn_write_1(sc, rtl8188eu_mac[i].reg,

sys/bus/u4b/wlan/if_urtwn.c

4138

error = urtwn_write_1(sc, rtl8192cu_mac[i].reg,

sys/bus/u4b/wlan/if_urtwn.c

4152

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4201

reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);

sys/bus/u4b/wlan/if_urtwn.c

4202

reg = (reg & ~0x00000003) | 0x2;

sys/bus/u4b/wlan/if_urtwn.c

4203

urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);

sys/bus/u4b/wlan/if_urtwn.c

4205

reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);

sys/bus/u4b/wlan/if_urtwn.c

4206

reg = (reg & ~0x00300033) | 0x00200022;

sys/bus/u4b/wlan/if_urtwn.c

4207

urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);

sys/bus/u4b/wlan/if_urtwn.c

4209

reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);

sys/bus/u4b/wlan/if_urtwn.c

4210

reg = (reg & ~0xff000000) | 0x45 << 24;

sys/bus/u4b/wlan/if_urtwn.c

4211

urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);

sys/bus/u4b/wlan/if_urtwn.c

4213

reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);

sys/bus/u4b/wlan/if_urtwn.c

4214

reg = (reg & ~0x000000ff) | 0x23;

sys/bus/u4b/wlan/if_urtwn.c

4215

urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);

sys/bus/u4b/wlan/if_urtwn.c

4217

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);

sys/bus/u4b/wlan/if_urtwn.c

4218

reg = (reg & ~0x00000030) | 1 << 4;

sys/bus/u4b/wlan/if_urtwn.c

4219

urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);

sys/bus/u4b/wlan/if_urtwn.c

4221

reg = urtwn_bb_read(sc, 0xe74);

sys/bus/u4b/wlan/if_urtwn.c

4222

reg = (reg & ~0x0c000000) | 2 << 26;

sys/bus/u4b/wlan/if_urtwn.c

4223

urtwn_bb_write(sc, 0xe74, reg);

sys/bus/u4b/wlan/if_urtwn.c

4224

reg = urtwn_bb_read(sc, 0xe78);

sys/bus/u4b/wlan/if_urtwn.c

4225

reg = (reg & ~0x0c000000) | 2 << 26;

sys/bus/u4b/wlan/if_urtwn.c

4226

urtwn_bb_write(sc, 0xe78, reg);

sys/bus/u4b/wlan/if_urtwn.c

4227

reg = urtwn_bb_read(sc, 0xe7c);

sys/bus/u4b/wlan/if_urtwn.c

4228

reg = (reg & ~0x0c000000) | 2 << 26;

sys/bus/u4b/wlan/if_urtwn.c

4229

urtwn_bb_write(sc, 0xe7c, reg);

sys/bus/u4b/wlan/if_urtwn.c

4230

reg = urtwn_bb_read(sc, 0xe80);

sys/bus/u4b/wlan/if_urtwn.c

4231

reg = (reg & ~0x0c000000) | 2 << 26;

sys/bus/u4b/wlan/if_urtwn.c

4232

urtwn_bb_write(sc, 0xe80, reg);

sys/bus/u4b/wlan/if_urtwn.c

4233

reg = urtwn_bb_read(sc, 0xe88);

sys/bus/u4b/wlan/if_urtwn.c

4234

reg = (reg & ~0x0c000000) | 2 << 26;

sys/bus/u4b/wlan/if_urtwn.c

4235

urtwn_bb_write(sc, 0xe88, reg);

sys/bus/u4b/wlan/if_urtwn.c

4255

reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);

sys/bus/u4b/wlan/if_urtwn.c

4257

RW(reg, R92C_AFE_XTAL_CTRL_ADDR,

sys/bus/u4b/wlan/if_urtwn.c

4270

uint32_t reg, type;

sys/bus/u4b/wlan/if_urtwn.c

4290

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/bus/u4b/wlan/if_urtwn.c

4291

type = (reg >> off) & 0x10;

sys/bus/u4b/wlan/if_urtwn.c

4294

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/bus/u4b/wlan/if_urtwn.c

4295

reg |= 0x100000;

sys/bus/u4b/wlan/if_urtwn.c

4296

urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);

sys/bus/u4b/wlan/if_urtwn.c

4299

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/bus/u4b/wlan/if_urtwn.c

4300

reg |= 0x10;

sys/bus/u4b/wlan/if_urtwn.c

4301

urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);

sys/bus/u4b/wlan/if_urtwn.c

4304

reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/bus/u4b/wlan/if_urtwn.c

4305

reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;

sys/bus/u4b/wlan/if_urtwn.c

4306

urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);

sys/bus/u4b/wlan/if_urtwn.c

4308

reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/bus/u4b/wlan/if_urtwn.c

4309

reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;

sys/bus/u4b/wlan/if_urtwn.c

4310

urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);

sys/bus/u4b/wlan/if_urtwn.c

4330

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/bus/u4b/wlan/if_urtwn.c

4331

reg &= ~(0x10 << off) | (type << off);

sys/bus/u4b/wlan/if_urtwn.c

4332

urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);

sys/bus/u4b/wlan/if_urtwn.c

4373

uint8_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4385

reg = urtwn_read_1(sc, 0x16);

sys/bus/u4b/wlan/if_urtwn.c

4386

reg = (reg & ~0xf0) | 0x90;

sys/bus/u4b/wlan/if_urtwn.c

4387

urtwn_write_1(sc, 0x16, reg);

sys/bus/u4b/wlan/if_urtwn.c

4470

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4474

reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);

sys/bus/u4b/wlan/if_urtwn.c

4475

reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);

sys/bus/u4b/wlan/if_urtwn.c

4476

urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);

sys/bus/u4b/wlan/if_urtwn.c

4477

reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/bus/u4b/wlan/if_urtwn.c

4478

reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);

sys/bus/u4b/wlan/if_urtwn.c

4479

reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);

sys/bus/u4b/wlan/if_urtwn.c

4480

reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);

sys/bus/u4b/wlan/if_urtwn.c

4481

urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/bus/u4b/wlan/if_urtwn.c

4483

reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);

sys/bus/u4b/wlan/if_urtwn.c

4484

reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);

sys/bus/u4b/wlan/if_urtwn.c

4485

reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);

sys/bus/u4b/wlan/if_urtwn.c

4486

reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);

sys/bus/u4b/wlan/if_urtwn.c

4487

urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);

sys/bus/u4b/wlan/if_urtwn.c

4488

reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/bus/u4b/wlan/if_urtwn.c

4489

reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);

sys/bus/u4b/wlan/if_urtwn.c

4490

urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/bus/u4b/wlan/if_urtwn.c

460

uint16_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4716

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4718

reg = urtwn_read_4(sc, R92C_RCR);

sys/bus/u4b/wlan/if_urtwn.c

4720

reg &= ~R92C_RCR_CBSSID_BCN;

sys/bus/u4b/wlan/if_urtwn.c

4722

reg |= R92C_RCR_CBSSID_BCN;

sys/bus/u4b/wlan/if_urtwn.c

4723

urtwn_write_4(sc, R92C_RCR, reg);

sys/bus/u4b/wlan/if_urtwn.c

4729

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

4731

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/bus/u4b/wlan/if_urtwn.c

4732

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);

sys/bus/u4b/wlan/if_urtwn.c

4733

urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);

sys/bus/u4b/wlan/if_urtwn.c

4736

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/bus/u4b/wlan/if_urtwn.c

4737

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);

sys/bus/u4b/wlan/if_urtwn.c

4738

urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);

sys/bus/u4b/wlan/if_urtwn.c

4808

urtwn_write_4(sc, wme2queue[ac].reg,

sys/bus/u4b/wlan/if_urtwn.c

4859

urtwn_write_1(sc, wme2queue[ac].reg, aifs);

sys/bus/u4b/wlan/if_urtwn.c

5061

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

5087

reg = urtwn_read_1(sc, R92C_RRSR + 2);

sys/bus/u4b/wlan/if_urtwn.c

5088

reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;

sys/bus/u4b/wlan/if_urtwn.c

5089

urtwn_write_1(sc, R92C_RRSR + 2, reg);

sys/bus/u4b/wlan/if_urtwn.c

5097

reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);

sys/bus/u4b/wlan/if_urtwn.c

5098

reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;

sys/bus/u4b/wlan/if_urtwn.c

5099

urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);

sys/bus/u4b/wlan/if_urtwn.c

5101

reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);

sys/bus/u4b/wlan/if_urtwn.c

5102

reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;

sys/bus/u4b/wlan/if_urtwn.c

5103

urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);

sys/bus/u4b/wlan/if_urtwn.c

5109

reg = urtwn_bb_read(sc, 0x818);

sys/bus/u4b/wlan/if_urtwn.c

5110

reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;

sys/bus/u4b/wlan/if_urtwn.c

5111

urtwn_bb_write(sc, 0x818, reg);

sys/bus/u4b/wlan/if_urtwn.c

5254

uint32_t reg;

sys/bus/u4b/wlan/if_urtwn.c

5329

reg = urtwn_read_4(sc, R92C_RRSR);

sys/bus/u4b/wlan/if_urtwn.c

5330

reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);

sys/bus/u4b/wlan/if_urtwn.c

5331

urtwn_write_4(sc, R92C_RRSR, reg);

sys/bus/u4b/wlan/if_urtwn.c

5355

reg = urtwn_read_4(sc, R92C_TDECTRL);

sys/bus/u4b/wlan/if_urtwn.c

5356

reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);

sys/bus/u4b/wlan/if_urtwn.c

5357

urtwn_write_4(sc, R92C_TDECTRL, reg);

sys/bus/u4b/wlan/if_urtwn.c

5416

reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/bus/u4b/wlan/if_urtwn.c

5417

reg |= R92C_RFMOD_CCK_EN;

sys/bus/u4b/wlan/if_urtwn.c

5418

usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);

sys/bus/u4b/wlan/if_urtwn.c

5421

reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/bus/u4b/wlan/if_urtwn.c

5422

reg |= R92C_RFMOD_OFDM_EN;

sys/bus/u4b/wlan/if_urtwn.c

5423

usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);

sys/bus/u4b/wlan/if_urtwnreg.h

1252

uint16_t reg;

sys/cpu/x86_64/include/asmacros.h

459

#define PCPU_ADDR(member, reg) \

sys/cpu/x86_64/include/asmacros.h

460

movq %gs:PC_PRVSPACE, reg ; \

sys/cpu/x86_64/include/asmacros.h

461

addq $PC_ ## member, reg

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

305

int reg;

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

308

reg = (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) ?

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

316

*val = acpi_panasonic_sinf(h, reg);

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

326

int reg;

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

329

reg = (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) ?

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

337

*val = acpi_panasonic_sinf(h, reg);

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

347

int reg;

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

350

reg = (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) ?

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

360

acpi_panasonic_sset(h, reg, *val);

sys/dev/acpica/acpi_panasonic/acpi_panasonic.c

363

*val = acpi_panasonic_sinf(h, reg);

sys/dev/acpica/acpi_pcib_acpi.c

311

acpi_pcib_read_config(device_t dev, int bus, int slot, int func, int reg,

sys/dev/acpica/acpi_pcib_acpi.c

314

return (pci_cfgregread(bus, slot, func, reg, bytes));

sys/dev/acpica/acpi_pcib_acpi.c

318

acpi_pcib_write_config(device_t dev, int bus, int slot, int func, int reg,

sys/dev/acpica/acpi_pcib_acpi.c

321

pci_cfgregwrite(bus, slot, func, reg, data, bytes);

sys/dev/acpica/acpi_pcib_acpi.c

72

int func, int reg, int bytes);

sys/dev/acpica/acpi_pcib_acpi.c

74

int func, int reg, uint32_t data, int bytes);

sys/dev/crypto/tpm/tpm.c

290

u_int8_t save, reg;

sys/dev/crypto/tpm/tpm.c

309

reg = bus_space_read_1(bt, bh, TPM_ACCESS);

sys/dev/crypto/tpm/tpm.c

310

if ((reg & TPM_ACCESS_VALID) && (reg & TPM_ACCESS_ACTIVE_LOCALITY) &&

sys/dev/crypto/tpm/tpm.c

951

tpm_legacy_in(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)

sys/dev/crypto/tpm/tpm.c

953

bus_space_write_1(iot, ioh, 0, reg);

sys/dev/crypto/tpm/tpm.c

960

tpm_legacy_out(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, u_int8_t v)

sys/dev/crypto/tpm/tpm.c

962

bus_space_write_1(iot, ioh, 0, reg);

sys/dev/disk/ahci/ahci_attach.c

225

u_int32_t pi, reg;

sys/dev/disk/ahci/ahci_attach.c

451

reg = ahci_read(sc, AHCI_REG_VS);

sys/dev/disk/ahci/ahci_attach.c

453

if (reg & 0x0000FF) {

sys/dev/disk/ahci/ahci_attach.c

455

(reg >> 16), (uint8_t)(reg >> 8), (uint8_t)reg);

sys/dev/disk/ahci/ahci_attach.c

458

(reg >> 16), (uint8_t)(reg >> 8));

sys/dev/disk/ahci/ahci_attach.c

460

sc->sc_vers = reg;

sys/dev/disk/ahci/ahci_attach.c

462

if (reg >= AHCI_REG_VS_1_3) {

sys/dev/disk/buslogic/btreg.h

661

#define bt_inb(bt, reg) \

sys/dev/disk/buslogic/btreg.h

662

bus_read_1((bt)->port, reg)

sys/dev/disk/buslogic/btreg.h

664

#define bt_outb(bt, reg, value) \

sys/dev/disk/buslogic/btreg.h

665

bus_write_1((bt)->port, reg, value)

sys/dev/disk/isp/ispvar.h

101

#define ISP_SETBITS(isp, reg, val) \

sys/dev/disk/isp/ispvar.h

102

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))

sys/dev/disk/isp/ispvar.h

104

#define ISP_CLRBITS(isp, reg, val) \

sys/dev/disk/isp/ispvar.h

105

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))

sys/dev/disk/isp/ispvar.h

78

#define ISP_READ(isp, reg) \

sys/dev/disk/isp/ispvar.h

79

(*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))

sys/dev/disk/isp/ispvar.h

81

#define ISP_WRITE(isp, reg, val) \

sys/dev/disk/isp/ispvar.h

82

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))

sys/dev/disk/mpt/mpt_pci.c

803

#define MPT_CHECK(reg, offset, size) \

sys/dev/disk/mpt/mpt_pci.c

805

if (mpt->pci_cfg.reg != val) { \

sys/dev/disk/mpt/mpt_pci.c

807

"Restoring " #reg " to 0x%X from 0x%X\n", \

sys/dev/disk/mpt/mpt_pci.c

808

mpt->pci_cfg.reg, val); \

sys/dev/disk/nata/chipsets/ata-amd.c

113

pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);

sys/dev/disk/nata/chipsets/ata-amd.c

115

pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1);

sys/dev/disk/nata/chipsets/ata-amd.c

117

pci_write_config(gparent, reg, 0x8b, 1);

sys/dev/disk/nata/chipsets/ata-amd.c

92

int reg = 0x53 - devno;

sys/dev/disk/nata/chipsets/ata-highpoint.c

184

u_int8_t reg, val, res;

sys/dev/disk/nata/chipsets/ata-highpoint.c

187

reg = ch->unit ? 0x57 : 0x53;

sys/dev/disk/nata/chipsets/ata-highpoint.c

188

val = pci_read_config(gparent, reg, 1);

sys/dev/disk/nata/chipsets/ata-highpoint.c

189

pci_write_config(gparent, reg, val | 0x80, 1);

sys/dev/disk/nata/chipsets/ata-highpoint.c

192

reg = 0x5b;

sys/dev/disk/nata/chipsets/ata-highpoint.c

193

val = pci_read_config(gparent, reg, 1);

sys/dev/disk/nata/chipsets/ata-highpoint.c

194

pci_write_config(gparent, reg, val & 0xfe, 1);

sys/dev/disk/nata/chipsets/ata-highpoint.c

197

pci_write_config(gparent, reg, val, 1);

sys/dev/disk/nata/chipsets/ata-nvidia.c

292

int reg = 0x63 - devno;

sys/dev/disk/nata/chipsets/ata-nvidia.c

303

pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);

sys/dev/disk/nata/chipsets/ata-nvidia.c

305

pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1);

sys/dev/disk/nata/chipsets/ata-nvidia.c

307

pci_write_config(gparent, reg, 0x8b, 1);

sys/dev/disk/nata/chipsets/ata-sis.c

250

u_int32_t reg;

sys/dev/disk/nata/chipsets/ata-sis.c

252

reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);

sys/dev/disk/nata/chipsets/ata-sis.c

253

pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);

sys/dev/disk/nata/chipsets/ata-sis.c

261

u_int16_t reg = 0x40 + (devno << 1);

sys/dev/disk/nata/chipsets/ata-sis.c

263

pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);

sys/dev/disk/nata/chipsets/ata-sis.c

270

u_int16_t reg = 0x40 + (devno << 1);

sys/dev/disk/nata/chipsets/ata-sis.c

272

pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);

sys/dev/disk/nata/chipsets/ata-sis.c

281

u_int16_t reg = 0x40 + (devno << 1);

sys/dev/disk/nata/chipsets/ata-sis.c

283

pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);

sys/dev/disk/nata/chipsets/ata-via.c

266

int reg = 0x53 - devno;

sys/dev/disk/nata/chipsets/ata-via.c

287

pci_write_config(gparent, reg - 0x08,timings[ata_mode2idx(mode)],1);

sys/dev/disk/nata/chipsets/ata-via.c

289

pci_write_config(gparent, reg,

sys/dev/disk/nata/chipsets/ata-via.c

292

pci_write_config(gparent, reg, 0x8b, 1);

sys/dev/disk/ncr/ncr.c

3723

int reg;

sys/dev/disk/ncr/ncr.c

3724

for (reg=0; reg<256; reg+=4) {

sys/dev/disk/ncr/ncr.c

3725

if (reg%16==0) kprintf ("reg[%2x]", reg);

sys/dev/disk/ncr/ncr.c

3726

kprintf (" %08x", (int)pci_conf_read (config_id, reg));

sys/dev/disk/ncr/ncr.c

3727

if (reg%16==12) kprintf ("\n");

sys/dev/disk/ncr/ncr.c

7091

read_tekram_eeprom_reg (ncb_p np, int reg)

sys/dev/disk/ncr/ncr.c

7095

int cmd = 0x80 | reg;

sys/dev/disk/ncr/ncrreg.h

425

#define SCR_SFBR_REG(reg,op,data) \

sys/dev/disk/ncr/ncrreg.h

426

(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))

sys/dev/disk/ncr/ncrreg.h

428

#define SCR_REG_SFBR(reg,op,data) \

sys/dev/disk/ncr/ncrreg.h

429

(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))

sys/dev/disk/ncr/ncrreg.h

431

#define SCR_REG_REG(reg,op,data) \

sys/dev/disk/ncr/ncrreg.h

432

(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))

sys/dev/disk/ncr/ncrreg.h

461

#define SCR_FROM_REG(reg) \

sys/dev/disk/ncr/ncrreg.h

462

SCR_REG_SFBR(reg,SCR_OR,0)

sys/dev/disk/ncr/ncrreg.h

464

#define SCR_TO_REG(reg) \

sys/dev/disk/ncr/ncrreg.h

465

SCR_SFBR_REG(reg,SCR_OR,0)

sys/dev/disk/ncr/ncrreg.h

467

#define SCR_LOAD_REG(reg,data) \

sys/dev/disk/ncr/ncrreg.h

468

SCR_REG_REG(reg,SCR_LOAD,data)

sys/dev/disk/nvme/nvme.c

62

uint32_t reg;

sys/dev/disk/nvme/nvme.c

66

reg = nvme_read(sc, NVME_REG_CONFIG);

sys/dev/disk/nvme/nvme.c

67

if (enable == 0 && (reg & NVME_CONFIG_EN)) {

sys/dev/disk/nvme/nvme.c

71

reg &= ~NVME_CONFIG_EN;

sys/dev/disk/nvme/nvme.c

72

nvme_write(sc, NVME_REG_CONFIG, reg);

sys/dev/disk/nvme/nvme.c

73

} else if (enable && (reg & NVME_CONFIG_EN) == 0) {

sys/dev/disk/nvme/nvme.c

77

reg |= NVME_CONFIG_EN;

sys/dev/disk/nvme/nvme.c

78

nvme_write(sc, NVME_REG_CONFIG, reg);

sys/dev/disk/nvme/nvme.c

83

reg = nvme_read(sc, NVME_REG_STATUS);

sys/dev/disk/nvme/nvme.c

84

if (enable == 0 && (reg & NVME_STATUS_RDY) == 0) {

sys/dev/disk/nvme/nvme.c

88

if (enable && (reg & NVME_STATUS_RDY)) {

sys/dev/disk/nvme/nvme.c

925

uint32_t reg;

sys/dev/disk/nvme/nvme.c

932

reg = nvme_read(sc, NVME_REG_CONFIG);

sys/dev/disk/nvme/nvme.c

933

reg &= ~NVME_CONFIG_SHUT_MASK;

sys/dev/disk/nvme/nvme.c

934

reg |= NVME_CONFIG_SHUT_NORM;

sys/dev/disk/nvme/nvme.c

935

nvme_write(sc, NVME_REG_CONFIG, reg);

sys/dev/disk/nvme/nvme.c

943

reg = nvme_read(sc, NVME_REG_STATUS);

sys/dev/disk/nvme/nvme.c

944

if ((reg & NVME_STATUS_SHUT_MASK) & NVME_STATUS_SHUT_DONE) {

sys/dev/disk/nvme/nvme_attach.c

100

uint32_t reg;

sys/dev/disk/nvme/nvme_attach.c

306

for (reg = 2; reg <= sc->maxqe; reg <<= 1)

sys/dev/disk/nvme/nvme_attach.c

308

sc->maxqe = reg >> 1;

sys/dev/disk/nvme/nvme_attach.c

417

reg = NVME_ATTR_COM_SET(sc->maxqe) | NVME_ATTR_SUB_SET(sc->maxqe);

sys/dev/disk/nvme/nvme_attach.c

418

nvme_write(sc, NVME_REG_ADM_ATTR, reg);

sys/dev/disk/nvme/nvme_attach.c

431

reg = NVME_CONFIG_IOSUB_ES_SET(6) | /* 64 byte sub entry */

sys/dev/disk/nvme/nvme_attach.c

435

nvme_write(sc, NVME_REG_CONFIG, reg);

sys/dev/disk/nvme/nvme_attach.c

437

reg = nvme_read(sc, NVME_REG_MEMSIZE);

sys/dev/disk/sbp/sbp.c

406

struct csrreg *reg;

sys/dev/disk/sbp/sbp.c

416

reg = crom_search_key(&cc, CROM_LUN);

sys/dev/disk/sbp/sbp.c

417

if (reg == NULL)

sys/dev/disk/sbp/sbp.c

419

lun = reg->val & 0xffff;

sys/dev/disk/sbp/sbp.c

472

reg = crom_search_key(&cc, CROM_LUN);

sys/dev/disk/sbp/sbp.c

473

if (reg == NULL)

sys/dev/disk/sbp/sbp.c

475

lun = reg->val & 0xffff;

sys/dev/disk/sbp/sbp.c

494

sdev->type = (reg->val & 0xff0000) >> 16;

sys/dev/disk/sbp/sbp.c

550

struct csrreg *reg;

sys/dev/disk/sbp/sbp.c

568

reg = crom_search_key(&cc, CROM_MGM);

sys/dev/disk/sbp/sbp.c

569

if (reg == NULL || reg->val == 0) {

sys/dev/disk/sbp/sbp.c

575

target->mgm_lo = 0xf0000000 | (reg->val << 2);

sys/dev/disk/sbp/sbp.c

596

struct csrreg *reg;

sys/dev/disk/sbp/sbp.c

608

while ((reg = crom_search_key(cc, CSRKEY_VER)) != NULL) {

sys/dev/disk/sbp/sbp.c

609

if (reg->val == CSRVAL_T10SBP2)

sys/dev/disk/sbp/sbp.c

614

reg = crom_search_key(cc, CSRKEY_FIRM_VER);

sys/dev/disk/sbp/sbp.c

615

if (reg != NULL)

sys/dev/disk/sbp/sbp.c

617

"%06x", reg->val);

sys/dev/disk/sili/sili_attach.c

124

u_int32_t nports, reg;

sys/dev/disk/sili/sili_attach.c

291

reg = sili_read(sc, SILI_REG_GCTL);

sys/dev/disk/sili/sili_attach.c

293

reg |= SILI_REG_GCTL_PORTEN(i);

sys/dev/disk/sili/sili_attach.c

294

sili_write(sc, SILI_REG_GCTL, reg);

sys/dev/disk/sym/sym_defs.h

728

#define SCR_SFBR_REG(reg,op,data) \

sys/dev/disk/sym/sym_defs.h

729

(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/disk/sym/sym_defs.h

731

#define SCR_REG_SFBR(reg,op,data) \

sys/dev/disk/sym/sym_defs.h

732

(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/disk/sym/sym_defs.h

734

#define SCR_REG_REG(reg,op,data) \

sys/dev/disk/sym/sym_defs.h

735

(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/disk/sym/sym_defs.h

766

#define SCR_FROM_REG(reg) \

sys/dev/disk/sym/sym_defs.h

767

SCR_REG_SFBR(reg,SCR_OR,0)

sys/dev/disk/sym/sym_defs.h

769

#define SCR_TO_REG(reg) \

sys/dev/disk/sym/sym_defs.h

770

SCR_SFBR_REG(reg,SCR_OR,0)

sys/dev/disk/sym/sym_defs.h

772

#define SCR_LOAD_REG(reg,data) \

sys/dev/disk/sym/sym_defs.h

773

SCR_REG_REG(reg,SCR_LOAD,data)

sys/dev/disk/sym/sym_defs.h

800

#define SCR_LOAD_R(reg, how, n) \

sys/dev/disk/sym/sym_defs.h

801

(0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/disk/sym/sym_defs.h

803

#define SCR_STORE_R(reg, how, n) \

sys/dev/disk/sym/sym_defs.h

804

(0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/disk/sym/sym_defs.h

806

#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)

sys/dev/disk/sym/sym_defs.h

807

#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)

sys/dev/disk/sym/sym_defs.h

808

#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)

sys/dev/disk/sym/sym_defs.h

809

#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)

sys/dev/disk/sym/sym_defs.h

811

#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)

sys/dev/disk/sym/sym_defs.h

812

#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)

sys/dev/disk/sym/sym_defs.h

813

#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)

sys/dev/disk/sym/sym_defs.h

814

#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)

sys/dev/disk/trm/trm.c

100

#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg)

sys/dev/disk/trm/trm.c

101

#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\

sys/dev/disk/trm/trm.c

102

reg, value)

sys/dev/disk/trm/trm.c

103

#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\

sys/dev/disk/trm/trm.c

104

reg, value)

sys/dev/disk/trm/trm.c

105

#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\

sys/dev/disk/trm/trm.c

106

reg, value)

sys/dev/disk/trm/trm.c

98

#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg)

sys/dev/disk/trm/trm.c

99

#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg)

sys/dev/drm/amd/amdgpu/amdgpu.h

1066

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

sys/dev/drm/amd/amdgpu/amdgpu.h

1068

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

sys/dev/drm/amd/amdgpu/amdgpu.h

1073

u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);

sys/dev/drm/amd/amdgpu/amdgpu.h

1074

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);

sys/dev/drm/amd/amdgpu/amdgpu.h

1093

#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

sys/dev/drm/amd/amdgpu/amdgpu.h

1094

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)

sys/dev/drm/amd/amdgpu/amdgpu.h

1096

#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1097

#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1099

#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)

sys/dev/drm/amd/amdgpu/amdgpu.h

1100

#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)

sys/dev/drm/amd/amdgpu/amdgpu.h

1101

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))

sys/dev/drm/amd/amdgpu/amdgpu.h

1102

#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)

sys/dev/drm/amd/amdgpu/amdgpu.h

1103

#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)

sys/dev/drm/amd/amdgpu/amdgpu.h

1106

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1107

#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1108

#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1109

#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1110

#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1111

#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1112

#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1113

#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1114

#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1115

#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1116

#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1117

#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1118

#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1119

#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1120

#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1121

#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1122

#define WREG32_P(reg, val, mask) \

sys/dev/drm/amd/amdgpu/amdgpu.h

1124

uint32_t tmp_ = RREG32(reg); \

sys/dev/drm/amd/amdgpu/amdgpu.h

1127

WREG32(reg, tmp_); \

sys/dev/drm/amd/amdgpu/amdgpu.h

1129

#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)

sys/dev/drm/amd/amdgpu/amdgpu.h

1130

#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))

sys/dev/drm/amd/amdgpu/amdgpu.h

1131

#define WREG32_PLL_P(reg, val, mask) \

sys/dev/drm/amd/amdgpu/amdgpu.h

1133

uint32_t tmp_ = RREG32_PLL(reg); \

sys/dev/drm/amd/amdgpu/amdgpu.h

1136

WREG32_PLL(reg, tmp_); \

sys/dev/drm/amd/amdgpu/amdgpu.h

1138

#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))

sys/dev/drm/amd/amdgpu/amdgpu.h

1139

#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))

sys/dev/drm/amd/amdgpu/amdgpu.h

1140

#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))

sys/dev/drm/amd/amdgpu/amdgpu.h

1147

#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT

sys/dev/drm/amd/amdgpu/amdgpu.h

1148

#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK

sys/dev/drm/amd/amdgpu/amdgpu.h

1150

#define REG_SET_FIELD(orig_val, reg, field, field_val) \

sys/dev/drm/amd/amdgpu/amdgpu.h

1151

(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \

sys/dev/drm/amd/amdgpu/amdgpu.h

1152

(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))

sys/dev/drm/amd/amdgpu/amdgpu.h

1154

#define REG_GET_FIELD(value, reg, field) \

sys/dev/drm/amd/amdgpu/amdgpu.h

1155

(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu.h

1157

#define WREG32_FIELD(reg, field, val) \

sys/dev/drm/amd/amdgpu/amdgpu.h

1158

WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu.h

1160

#define WREG32_FIELD_OFFSET(reg, offset, field, val) \

sys/dev/drm/amd/amdgpu/amdgpu.h

1161

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

320

uint32_t reg, wptr_val, data;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

345

for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

346

WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

359

for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

360

WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

392

uint32_t i = 0, reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

412

for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

413

DUMP_REG(reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

493

uint32_t i = 0, reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

501

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

502

DUMP_REG(sdma_offset + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

503

for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

504

reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

505

DUMP_REG(sdma_offset + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

506

for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

507

reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

508

DUMP_REG(sdma_offset + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

509

for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

510

reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

511

DUMP_REG(sdma_offset + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

512

for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

513

reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

514

DUMP_REG(sdma_offset + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

705

uint32_t reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

708

reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

709

return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

715

uint32_t reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

718

reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

719

return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

410

uint32_t reg, hqd_base, data;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

435

for (reg = hqd_base;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

436

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

437

WREG32(reg, mqd_hqd[reg - hqd_base]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

502

uint32_t i = 0, reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

517

for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

518

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

519

DUMP_REG(reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

609

uint32_t i = 0, reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

617

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

618

DUMP_REG(sdma_base_addr + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

619

for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

620

DUMP_REG(sdma_base_addr + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

621

for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

622

reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

623

DUMP_REG(sdma_base_addr + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

624

for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

625

reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

626

DUMP_REG(sdma_base_addr + reg);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

766

uint32_t reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

769

reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

771

return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

777

uint32_t reg;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

780

reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

782

return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

184

gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1843

static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1857

static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1871

static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1885

static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1899

static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1903

WREG32(reg, val);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1915

static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1920

r = RREG32(reg);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1933

static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1937

WREG32_IO(reg, val);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1949

static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1954

r = RREG32_IO(reg);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

203

u32 reg;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

207

reg = amdgpu_display_hpd_get_gpio_reg(adev);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

210

if (gpio->reg == reg) {

sys/dev/drm/amd/amdgpu/amdgpu_device.c

127

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

sys/dev/drm/amd/amdgpu/amdgpu_device.c

133

return amdgpu_virt_kiq_rreg(adev, reg);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

135

if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))

sys/dev/drm/amd/amdgpu/amdgpu_device.c

136

ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

141

writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

145

trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

201

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

sys/dev/drm/amd/amdgpu/amdgpu_device.c

204

trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

206

if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {

sys/dev/drm/amd/amdgpu/amdgpu_device.c

211

return amdgpu_virt_kiq_wreg(adev, reg, v);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

213

if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))

sys/dev/drm/amd/amdgpu/amdgpu_device.c

214

writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

219

writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

224

if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {

sys/dev/drm/amd/amdgpu/amdgpu_device.c

237

u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

239

if ((reg * 4) < adev->rio_mem_size)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

240

return bus_read_4(adev->rio_mem, (reg * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

242

bus_write_4(adev->rio_mem, (mmMM_INDEX * 4), (reg * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

256

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

258

if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {

sys/dev/drm/amd/amdgpu/amdgpu_device.c

262

if ((reg * 4) < adev->rio_mem_size)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

263

bus_write_4(adev->rio_mem, (reg * 4), v);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

265

bus_write_4(adev->rio_mem, (mmMM_INDEX * 4), (reg * 4));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

269

if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {

sys/dev/drm/amd/amdgpu/amdgpu_device.c

360

static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

362

DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

377

static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

380

reg, v);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

396

uint32_t block, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

399

reg, block);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

417

uint32_t reg, uint32_t v)

sys/dev/drm/amd/amdgpu/amdgpu_device.c

420

reg, block, v);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

467

u32 tmp, reg, and_mask, or_mask;

sys/dev/drm/amd/amdgpu/amdgpu_device.c

474

reg = registers[i + 0];

sys/dev/drm/amd/amdgpu/amdgpu_device.c

481

tmp = RREG32(reg);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

485

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

743

uint32_t reg;

sys/dev/drm/amd/amdgpu/amdgpu_device.c

778

reg = amdgpu_asic_get_config_memsize(adev);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

780

if ((reg != 0) && (reg != 0xffffffff))

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

100

adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

76

int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

84

*reg = adev->gfx.scratch.reg_base + i;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

98

void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

331

int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

332

void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

493

u32 reg;

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

160

void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

161

void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

162

void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/amdgpu_trace.h

56

#define trace_amdgpu_mm_rreg(device, reg, ret)

sys/dev/drm/amd/amdgpu/amdgpu_trace.h

57

#define trace_amdgpu_mm_wreg(device, reg, v)

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

89

unsigned reg, count;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

896

unsigned reg = ctx->reg + i;

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

903

switch (reg) {

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

919

DRM_ERROR("Invalid reg 0x%X!\n", reg);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

946

ctx->reg = CP_PACKET0_GET_REG(cmd);

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

135

uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

147

amdgpu_ring_emit_rreg(ring, reg);

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

185

pr_err("failed to read reg:%x\n", reg);

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

189

void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

201

amdgpu_ring_emit_wreg(ring, reg, v);

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

239

pr_err("failed to write reg:%x\n", reg);

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

289

uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

290

void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);

sys/dev/drm/amd/amdgpu/cik.c

100

static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

106

WREG32(mmSMC_IND_INDEX_0, (reg));

sys/dev/drm/amd/amdgpu/cik.c

112

static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

117

WREG32(mmSMC_IND_INDEX_0, (reg));

sys/dev/drm/amd/amdgpu/cik.c

122

static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

128

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/cik.c

134

static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

139

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/cik.c

144

static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

150

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/cik.c

156

static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

161

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/cik.c

75

static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/cik.c

81

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/cik.c

88

static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/cik.c

93

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/cik_sdma.c

890

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/cik_sdma.c

893

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/cikd.h

216

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

sys/dev/drm/amd/amdgpu/cikd.h

217

((reg) & 0xFFFF) | \

sys/dev/drm/amd/amdgpu/dce_v10_0.c

103

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

108

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

113

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

172

u32 block_offset, u32 reg)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

178

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

186

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

191

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3086

u32 reg;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3093

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3096

reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3099

reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3207

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3253

disp_int = RREG32(interrupt_status_offsets[hpd].reg);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

82

uint32_t reg;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

88

.reg = mmDISP_INTERRUPT_STATUS,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

93

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

98

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

100

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

105

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

110

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

115

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

190

u32 block_offset, u32 reg)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

196

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

204

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

209

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3212

u32 reg;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3219

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3222

reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3225

reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3333

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3380

disp_int = RREG32(interrupt_status_offsets[hpd].reg);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

84

uint32_t reg;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

90

.reg = mmDISP_INTERRUPT_STATUS,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

95

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

103

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

108

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

113

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

120

u32 block_offset, u32 reg)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

126

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

134

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

139

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3018

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3055

u32 reg;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3062

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3065

reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3068

reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3139

disp_int = RREG32(interrupt_status_offsets[hpd].reg);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

82

uint32_t reg;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

88

.reg = mmDISP_INTERRUPT_STATUS,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

93

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

98

.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3255

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3262

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6263

int pipe_num, tmp, reg;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6272

reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6273

tmp = RREG32(reg);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6275

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6469

static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6477

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6485

static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6504

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

357

bool wc, uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

363

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4203

int pipe_num, tmp, reg;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4212

reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4213

tmp = RREG32(reg);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4215

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4450

static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4458

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4466

static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4484

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4489

static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4492

gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

442

uint32_t reg;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

445

reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

447

reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

448

amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

645

uint32_t reg;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

648

reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

650

reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

651

amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

208

u32 tmp, reg, bits, i, j;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

223

reg = hub->vm_context0_cntl + i;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

224

tmp = RREG32(reg);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

226

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

234

reg = hub->vm_context0_cntl + i;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

235

tmp = RREG32(reg);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

237

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

454

uint32_t reg;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

457

reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

459

reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

461

amdgpu_ring_emit_wreg(ring, reg, pasid);

sys/dev/drm/amd/amdgpu/mmsch_v1_0.h

120

#define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

sys/dev/drm/amd/amdgpu/mmsch_v1_0.h

122

init_table, (reg), \

sys/dev/drm/amd/amdgpu/mmsch_v1_0.h

128

#define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \

sys/dev/drm/amd/amdgpu/mmsch_v1_0.h

130

init_table, (reg), \

sys/dev/drm/amd/amdgpu/mmsch_v1_0.h

136

#define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \

sys/dev/drm/amd/amdgpu/mmsch_v1_0.h

138

init_table, (reg), \

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

118

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

137

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

139

reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

142

reg);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

63

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

65

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

67

if (reg != event)

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

82

u8 reg;

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

85

reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

86

if (reg & 2)

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

320

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

324

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

325

reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

326

WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

329

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

330

while (reg & mask) {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

338

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

344

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

346

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

347

reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

349

WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

355

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

357

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

358

reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

360

WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

368

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

373

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

374

if (!(reg & mask))

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

378

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

379

if (reg != event)

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

392

u32 reg;

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

394

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

395

while (!(reg & mask)) {

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

404

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

248

uint32_t reg;

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

250

reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

251

if (reg & 1)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

254

if (reg & 0x80000000)

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

257

if (!reg) {

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

76

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

79

u32 doorbell_range = RREG32(reg);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

87

WREG32(reg, doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

74

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

77

u32 doorbell_range = RREG32(reg);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

85

WREG32(reg, doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

221

uint32_t reg;

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

223

reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

224

if (reg & 1)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

227

if (reg & 0x80000000)

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

230

if (!reg) {

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

72

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

75

u32 doorbell_range = RREG32(reg);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

83

WREG32(reg, doorbell_range);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

572

uint32_t reg;

sys/dev/drm/amd/amdgpu/psp_v3_1.c

574

reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;

sys/dev/drm/amd/amdgpu/psp_v3_1.c

575

WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

576

reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

577

return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

830

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

834

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1101

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1105

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1262

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1266

amdgpu_ring_write(ring, reg);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1270

static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1273

sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);

sys/dev/drm/amd/amdgpu/si_dpm.c

2756

u32 load_line_slope, reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

2767

reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;

sys/dev/drm/amd/amdgpu/si_dpm.c

2768

reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);

sys/dev/drm/amd/amdgpu/si_dpm.c

2769

WREG32(CG_CAC_CTRL, reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4837

u32 reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

4915

reg = CG_R(0xffff) | CG_L(0);

sys/dev/drm/amd/amdgpu/si_dpm.c

4916

table->initialState.levels[0].aT = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4941

reg = MIN_POWER_MASK | MAX_POWER_MASK;

sys/dev/drm/amd/amdgpu/si_dpm.c

4942

table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4944

reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;

sys/dev/drm/amd/amdgpu/si_dpm.c

4945

table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

4967

u32 reg;

sys/dev/drm/amd/amdgpu/si_dpm.c

5083

reg = MIN_POWER_MASK | MAX_POWER_MASK;

sys/dev/drm/amd/amdgpu/si_dpm.c

5084

table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

5086

reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;

sys/dev/drm/amd/amdgpu/si_dpm.c

5087

table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/amd/amdgpu/soc15.c

101

WREG32(address, reg);

sys/dev/drm/amd/amdgpu/soc15.c

108

static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

117

WREG32(address, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/soc15.c

123

static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

131

WREG32(address, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/soc15.c

136

static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

145

WREG32(address, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

151

static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

159

WREG32(address, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

164

static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

170

WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

176

static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

181

WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

186

static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

192

WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

198

static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.c

203

WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

369

u32 tmp, reg;

sys/dev/drm/amd/amdgpu/soc15.c

374

reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;

sys/dev/drm/amd/amdgpu/soc15.c

379

tmp = RREG32(reg);

sys/dev/drm/amd/amdgpu/soc15.c

383

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/soc15.c

78

static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/soc15.c

86

WREG32(address, reg);

sys/dev/drm/amd/amdgpu/soc15.c

93

static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/soc15.h

40

u32 reg;

sys/dev/drm/amd/amdgpu/soc15.h

45

#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg

sys/dev/drm/amd/amdgpu/soc15.h

47

#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \

sys/dev/drm/amd/amdgpu/soc15.h

48

{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }

sys/dev/drm/amd/amdgpu/soc15_common.h

28

#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

sys/dev/drm/amd/amdgpu/soc15_common.h

30

#define WREG32_FIELD15(ip, idx, reg, field, val) \

sys/dev/drm/amd/amdgpu/soc15_common.h

31

WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \

sys/dev/drm/amd/amdgpu/soc15_common.h

32

(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \

sys/dev/drm/amd/amdgpu/soc15_common.h

33

& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/soc15_common.h

35

#define RREG32_SOC15(ip, inst, reg) \

sys/dev/drm/amd/amdgpu/soc15_common.h

36

RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

sys/dev/drm/amd/amdgpu/soc15_common.h

38

#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \

sys/dev/drm/amd/amdgpu/soc15_common.h

39

RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)

sys/dev/drm/amd/amdgpu/soc15_common.h

41

#define WREG32_SOC15(ip, inst, reg, value) \

sys/dev/drm/amd/amdgpu/soc15_common.h

42

WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)

sys/dev/drm/amd/amdgpu/soc15_common.h

44

#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \

sys/dev/drm/amd/amdgpu/soc15_common.h

45

WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)

sys/dev/drm/amd/amdgpu/soc15_common.h

47

#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \

sys/dev/drm/amd/amdgpu/soc15_common.h

48

WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)

sys/dev/drm/amd/amdgpu/soc15_common.h

50

#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \

sys/dev/drm/amd/amdgpu/soc15_common.h

53

uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \

sys/dev/drm/amd/amdgpu/soc15_common.h

62

tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \

sys/dev/drm/amd/amdgpu/soc15_common.h

66

inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \

sys/dev/drm/amd/amdgpu/soc15_common.h

73

#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \

sys/dev/drm/amd/amdgpu/soc15_common.h

77

((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \

sys/dev/drm/amd/amdgpu/soc15_common.h

82

#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \

sys/dev/drm/amd/amdgpu/soc15_common.h

88

((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \

sys/dev/drm/amd/amdgpu/soc15d.h

41

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

sys/dev/drm/amd/amdgpu/soc15d.h

42

((reg) & 0xFFFF) | \

sys/dev/drm/amd/amdgpu/soc15d.h

74

#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1040

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1043

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1284

uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1286

reg -= p->adev->reg_offset[UVD_HWIP][0][1];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1287

reg += p->adev->reg_offset[UVD_HWIP][1][1];

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1289

amdgpu_set_ib_value(p, ib_idx, i, reg);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1342

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1348

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1357

static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1364

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1410

uint32_t reg, uint32_t val,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1414

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1432

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1435

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

1003

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/vce_v4_0.c

1006

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

981

static void vce_v4_0_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

985

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1392

uint32_t reg, uint32_t val,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1399

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1427

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1433

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1539

uint32_t reg, uint32_t val,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1543

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1561

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1564

amdgpu_ring_write(ring, reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1781

uint32_t reg, uint32_t val,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1785

uint32_t reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1826

uint32_t reg, uint32_t val)

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1829

uint32_t reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1877

uint32_t reg, reg_offset, val, mask, i;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1880

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1881

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1886

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1887

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1898

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1899

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1904

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1905

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1910

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1911

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1937

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1938

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1943

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1944

reg_offset = (reg << 2);

sys/dev/drm/amd/amdgpu/vi.c

102

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/vi.c

109

static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

115

WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));

sys/dev/drm/amd/amdgpu/vi.c

121

static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

126

WREG32(mmSMC_IND_INDEX_11, (reg));

sys/dev/drm/amd/amdgpu/vi.c

135

static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

141

WREG32(mmMP0PUB_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

147

static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

152

WREG32(mmMP0PUB_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

157

static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

163

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/vi.c

169

static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

174

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/vi.c

179

static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

185

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

191

static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

196

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

201

static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

207

WREG32(mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

213

static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vi.c

218

WREG32(mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

452

uint32_t reg = 0;

sys/dev/drm/amd/amdgpu/vi.c

456

reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);

sys/dev/drm/amd/amdgpu/vi.c

458

if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))

sys/dev/drm/amd/amdgpu/vi.c

461

if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))

sys/dev/drm/amd/amdgpu/vi.c

465

if (reg == 0) {

sys/dev/drm/amd/amdgpu/vi.c

84

static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)

sys/dev/drm/amd/amdgpu/vi.c

90

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/vi.c

97

static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

sys/dev/drm/amd/amdgpu/vid.h

98

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

sys/dev/drm/amd/amdgpu/vid.h

99

((reg) & 0xFFFF) | \

sys/dev/drm/amd/display/dc/bios/bios_parser_helper.c

50

#define REG(reg)\

sys/dev/drm/amd/display/dc/bios/bios_parser_helper.c

51

(bios->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_abm.c

38

#define REG(reg) \

sys/dev/drm/amd/display/dc/dce/dce_abm.c

39

(abm_dce->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_audio.c

39

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_audio.c

40

(aud->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_audio.c

46

#define IX_REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_audio.c

47

ix ## reg

sys/dev/drm/amd/display/dc/dce/dce_audio.c

937

const struct dce_audio_registers *reg,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

953

audio->regs = reg;

sys/dev/drm/amd/display/dc/dce/dce_audio.h

127

const struct dce_audio_registers *reg,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

39

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

40

(clk_src->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

43

#define REG(reg) \

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

44

(clk_dce->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

37

#define REG(reg) \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

38

(dmcu_dce->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

33

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

34

hws->regs->reg

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

32

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

33

dce_i2c_hw->regs->reg

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

30

#define REG(reg) \

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

31

(ipp_dce->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

62

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

63

(enc110->link_regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

65

#define AUX_REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

66

(enc110->aux_regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

68

#define HPD_REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

69

(enc110->hpd_regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

91

#define DIG_REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

92

(reg + enc110->offsets.dig)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

94

#define DP_REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

95

(reg + enc110->offsets.dp)

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

32

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

33

dce_mi->regs->reg

sys/dev/drm/amd/display/dc/dce/dce_opp.c

33

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_opp.c

34

(opp110->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

35

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

36

(enc110->regs->reg)

sys/dev/drm/amd/display/dc/dce/dce_transform.c

32

#define REG(reg) \

sys/dev/drm/amd/display/dc/dce/dce_transform.c

33

(xfm_dce->regs->reg)

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

64

#define HW_REG_CRTC(reg, id)\

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

65

(reg + reg_offsets[id].crtc)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

383

#define REG(reg) mm ## reg

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

39

#define DCP_REG(reg)\

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

40

(reg + cp110->offsets.dcp_offset)

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

41

#define DMIF_REG(reg)\

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

42

(reg + cp110->offsets.dmif_offset)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

100

#define HW_REG_BLND(reg, id)\

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

101

(reg + reg_offsets[id].blnd)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

103

#define HW_REG_CRTC(reg, id)\

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

104

(reg + reg_offsets[id].crtc)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

74

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

75

hws->regs->reg

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

394

#define REG(reg) mm ## reg

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

48

#define CRTC_REG(reg) (reg + tg110->offsets.crtc)

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

49

#define DCP_REG(reg) (reg + tg110->offsets.dcp)

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

38

#define DCP_REG(reg)\

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

39

(reg + cp110->offsets.dcp_offset)

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

40

#define DMIF_REG(reg)\

sys/dev/drm/amd/display/dc/dce112/dce112_compressor.c

41

(reg + cp110->offsets.dmif_offset)

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

62

#define HW_REG_CRTC(reg, id)\

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

63

(reg + reg_offsets[id].crtc)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

402

#define REG(reg) mm ## reg

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

42

#define REG(reg)\

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

43

hws->regs->reg

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

76

#define HW_REG_CRTC(reg, id)\

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

77

(reg + reg_offsets[id].crtc)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

48

#define CRTC_REG_UPDATE(reg, field, val) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

49

CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

51

#define CRTC_REG_UPDATE_2(reg, field1, val1, field2, val2) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

52

CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

54

#define CRTC_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

55

CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

57

#define CRTC_REG_UPDATE_4(reg, field1, val1, field2, val2, field3, val3, field4, val4) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

58

CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

60

#define CRTC_REG_UPDATE_5(reg, field1, val1, field2, val2, field3, val3, field4, val4, field5, val5) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

61

CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

63

#define CRTC_REG_SET(reg, field, val) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

64

CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

66

#define CRTC_REG_SET_2(reg, field1, val1, field2, val2) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

67

CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

69

#define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

70

CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

66

#define HW_REG_CRTC(reg, id)\

sys/dev/drm/amd/display/dc/dce80/dce80_hw_sequencer.c

67

(reg + reg_offsets[id].crtc)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

415

#define REG(reg) mm ## reg

sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c

83

#define CRTC_REG(reg) (reg + tg110->offsets.crtc)

sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c

84

#define DCP_REG(reg) (reg + tg110->offsets.dcp)

sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c

85

#define DMIF_REG(reg) (reg + tg110->offsets.dmif)

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

102

REG_SET(reg->start_end_cntl1_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

104

REG_SET_2(reg->start_end_cntl2_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

108

for (reg_region_cur = reg->region_start;

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

109

reg_region_cur <= reg->region_end;

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

32

#define REG(reg) reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

39

reg->shifts.field_name, reg->masks.field_name

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

44

const struct color_matrices_reg *reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

49

for (cur_csc_reg = reg->csc_c11_c12;

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

50

cur_csc_reg <= reg->csc_c33_c34;

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

68

const struct xfer_func_reg *reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

73

REG_SET_2(reg->start_cntl_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

76

REG_SET_2(reg->start_cntl_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

79

REG_SET_2(reg->start_cntl_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

83

REG_SET(reg->start_slope_cntl_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

85

REG_SET(reg->start_slope_cntl_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

87

REG_SET(reg->start_slope_cntl_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

90

REG_SET(reg->start_end_cntl1_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

92

REG_SET_2(reg->start_end_cntl2_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

96

REG_SET(reg->start_end_cntl1_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

98

REG_SET_2(reg->start_end_cntl2_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.h

92

const struct color_matrices_reg *reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.h

97

const struct xfer_func_reg *reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

41

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

42

dpp->tf_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

289

struct xfer_func_reg *reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

291

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

292

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

293

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

294

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

295

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

296

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

297

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

298

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

300

reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

301

reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

302

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

303

reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

304

reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

305

reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

306

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

307

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

308

reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

309

reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

310

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

311

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

316

struct xfer_func_reg *reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

318

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

319

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

320

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

321

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

322

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

323

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

324

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

325

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

327

reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

328

reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

329

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

330

reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

331

reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

332

reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

333

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

334

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

335

reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

336

reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

337

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

338

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

42

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

43

dpp->tf_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

42

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

43

dpp->tf_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

35

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

36

hubbub->regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

31

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

32

hubp1->hubp_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

53

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

54

hws->regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.c

30

#define REG(reg) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.c

31

(ippn10->regs->reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1286

#define HPD_REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1287

(enc10->hpd_regs->reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1319

#define AUX_REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1320

(enc10->aux_regs->reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1335

#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1336

AUX_REG_UPDATE_N(reg, 2,\

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1337

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1338

FN(reg, f2), v2)

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

42

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

43

(enc10->link_regs->reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

29

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

30

mpc10->mpc_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

30

#define REG(reg) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

31

(oppn10->regs->reg)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

31

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

32

optc1->tg_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

36

#define REG(reg)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

37

(enc1->regs->reg)

sys/dev/drm/amd/display/dc/dm_services.h

163

#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \

sys/dev/drm/amd/display/dc/dm_services.h

164

dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)

sys/dev/drm/amd/display/dc/dm_services.h

166

#define dm_read_reg_soc15(ctx, reg, inst_offset) \

sys/dev/drm/amd/display/dc/dm_services.h

167

dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

42

#define REG(reg)\

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

43

(ddc->regs->reg)

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

39

#define REG(reg)\

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

40

(gpio->regs->reg)

sys/dev/drm/amd/display/dc/gpio/hw_hpd.c

41

#define REG(reg)\

sys/dev/drm/amd/display/dc/gpio/hw_hpd.c

42

(hpd->regs->reg)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

100

FN(reg, f4), v4,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

101

FN(reg, f5), v5,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

102

FN(reg, f6), v6)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

104

#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

106

REG_SET_N(reg, 7, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

107

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

108

FN(reg, f2), v2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

109

FN(reg, f3), v3,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

110

FN(reg, f4), v4,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

111

FN(reg, f5), v5,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

112

FN(reg, f6), v6,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

113

FN(reg, f7), v7)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

115

#define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

117

REG_SET_N(reg, 8, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

118

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

119

FN(reg, f2), v2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

120

FN(reg, f3), v3,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

121

FN(reg, f4), v4,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

122

FN(reg, f5), v5,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

123

FN(reg, f6), v6,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

124

FN(reg, f7), v7,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

125

FN(reg, f8), v8)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

127

#define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

129

REG_SET_N(reg, 9, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

130

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

131

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

132

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

133

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

134

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

135

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

136

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

137

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

138

FN(reg, f9), v9)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

140

#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

142

REG_SET_N(reg, 10, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

143

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

144

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

145

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

146

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

147

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

148

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

149

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

150

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

151

FN(reg, f9), v9, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

152

FN(reg, f10), v10)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

235

#define REG_UPDATE_2(reg, f1, v1, f2, v2) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

236

REG_UPDATE_N(reg, 2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

237

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

238

FN(reg, f2), v2)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

240

#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

241

REG_UPDATE_N(reg, 3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

242

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

243

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

244

FN(reg, f3), v3)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

246

#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

247

REG_UPDATE_N(reg, 4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

248

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

249

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

250

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

251

FN(reg, f4), v4)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

253

#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

254

REG_UPDATE_N(reg, 5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

255

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

256

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

257

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

258

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

259

FN(reg, f5), v5)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

261

#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

262

REG_UPDATE_N(reg, 6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

263

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

264

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

265

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

266

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

267

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

268

FN(reg, f6), v6)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

270

#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

271

REG_UPDATE_N(reg, 7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

272

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

273

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

274

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

275

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

276

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

277

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

278

FN(reg, f7), v7)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

280

#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

281

REG_UPDATE_N(reg, 8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

282

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

283

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

284

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

285

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

286

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

287

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

288

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

289

FN(reg, f8), v8)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

291

#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

292

REG_UPDATE_N(reg, 9, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

293

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

294

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

295

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

296

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

297

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

298

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

299

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

300

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

301

FN(reg, f9), v9)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

303

#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

304

REG_UPDATE_N(reg, 10, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

305

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

306

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

307

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

308

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

309

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

310

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

311

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

312

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

313

FN(reg, f9), v9, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

314

FN(reg, f10), v10)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

316

#define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

318

REG_UPDATE_N(reg, 14, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

319

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

320

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

321

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

322

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

323

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

324

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

325

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

326

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

327

FN(reg, f9), v9, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

328

FN(reg, f10), v10, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

329

FN(reg, f11), v11, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

330

FN(reg, f12), v12, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

331

FN(reg, f13), v13, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

332

FN(reg, f14), v14)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

334

#define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

336

REG_UPDATE_N(reg, 19, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

337

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

338

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

339

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

340

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

341

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

342

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

343

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

344

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

345

FN(reg, f9), v9, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

346

FN(reg, f10), v10, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

347

FN(reg, f11), v11, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

348

FN(reg, f12), v12, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

349

FN(reg, f13), v13, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

350

FN(reg, f14), v14, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

351

FN(reg, f15), v15, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

352

FN(reg, f16), v16, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

353

FN(reg, f17), v17, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

354

FN(reg, f18), v18, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

355

FN(reg, f19), v19)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

357

#define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

359

REG_UPDATE_N(reg, 20, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

360

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

361

FN(reg, f2), v2, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

362

FN(reg, f3), v3, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

363

FN(reg, f4), v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

364

FN(reg, f5), v5, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

365

FN(reg, f6), v6, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

366

FN(reg, f7), v7, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

367

FN(reg, f8), v8, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

368

FN(reg, f9), v9, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

369

FN(reg, f10), v10, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

370

FN(reg, f11), v11, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

371

FN(reg, f12), v12, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

372

FN(reg, f13), v13, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

373

FN(reg, f14), v14, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

374

FN(reg, f15), v15, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

375

FN(reg, f16), v16, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

376

FN(reg, f17), v17, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

377

FN(reg, f18), v18, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

378

FN(reg, f19), v19, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

379

FN(reg, f20), v20)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

383

#define REG_UPDATE_SEQ(reg, field, value1, value2) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

384

{ uint32_t val = REG_UPDATE(reg, field, value1); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

385

REG_SET(reg, val, field, value2); }

sys/dev/drm/amd/display/dc/inc/reg_helper.h

388

#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

389

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

390

REG_SET(reg, val, f2, v2); }

sys/dev/drm/amd/display/dc/inc/reg_helper.h

392

#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

393

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

394

val = REG_SET(reg, val, f2, v2); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

395

REG_SET(reg, val, f3, v3); }

sys/dev/drm/amd/display/dc/inc/reg_helper.h

460

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

461

FN(reg, f2), v2)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

477

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

478

FN(reg, f2), v2)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

67

#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

68

REG_SET_N(reg, 2, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

69

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

70

FN(reg, f2), v2)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

72

#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

73

REG_SET_N(reg, 3, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

74

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

75

FN(reg, f2), v2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

76

FN(reg, f3), v3)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

78

#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

79

REG_SET_N(reg, 4, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

80

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

81

FN(reg, f2), v2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

82

FN(reg, f3), v3,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

83

FN(reg, f4), v4)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

85

#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

87

REG_SET_N(reg, 5, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

88

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

89

FN(reg, f2), v2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

90

FN(reg, f3), v3,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

91

FN(reg, f4), v4,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

92

FN(reg, f5), v5)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

94

#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

96

REG_SET_N(reg, 6, init_value, \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

97

FN(reg, f1), v1,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

98

FN(reg, f2), v2,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

99

FN(reg, f3), v3,\

sys/dev/drm/amd/include/cgs_common.h

121

#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT

sys/dev/drm/amd/include/cgs_common.h

122

#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK

sys/dev/drm/amd/include/cgs_common.h

124

#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \

sys/dev/drm/amd/include/cgs_common.h

125

(((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \

sys/dev/drm/amd/include/cgs_common.h

126

(CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))

sys/dev/drm/amd/include/cgs_common.h

128

#define CGS_REG_GET_FIELD(value, reg, field) \

sys/dev/drm/amd/include/cgs_common.h

129

(((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/include/cgs_common.h

131

#define CGS_WREG32_FIELD(device, reg, field, val) \

sys/dev/drm/amd/include/cgs_common.h

132

cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/include/cgs_common.h

134

#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \

sys/dev/drm/amd/include/cgs_common.h

135

cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

294

uint32_t reg;

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

297

reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

298

if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

124

#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

125

#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

127

#define PHM_SET_FIELD(origval, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

128

(((origval) & ~PHM_FIELD_MASK(reg, field)) | \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

129

(PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

131

#define PHM_GET_FIELD(value, reg, field) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

132

(((value) & PHM_FIELD_MASK(reg, field)) >> \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

133

PHM_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

138

#define PHM_READ_FIELD(device, reg, field) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

139

PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

141

#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

142

PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

143

reg, field)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

145

#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

146

PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

147

reg, field)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

149

#define PHM_WRITE_FIELD(device, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

150

cgs_write_register(device, mm##reg, PHM_SET_FIELD( \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

151

cgs_read_register(device, mm##reg), reg, field, fieldval))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

153

#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

154

cgs_write_ind_register(device, port, ix##reg, \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

155

PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

156

reg, field, fieldval))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

158

#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

159

cgs_write_ind_register(device, port, ix##reg, \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

160

PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

161

reg, field, fieldval))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

167

#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

168

PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

170

#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

171

PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

172

<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

178

#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

179

PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

181

#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

182

PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

183

(fieldval) << PHM_FIELD_SHIFT(reg, field), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

184

PHM_FIELD_MASK(reg, field) )

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

192

#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

193

PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

195

#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

196

PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

197

(fieldval) << PHM_FIELD_SHIFT(reg, field), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

198

PHM_FIELD_MASK(reg, field))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

206

#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

207

PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

209

#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

210

PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

211

(fieldval) << PHM_FIELD_SHIFT(reg, field), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

212

PHM_FIELD_MASK(reg, field))

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

219

#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

221

mm##reg, value, mask)

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

223

#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

224

PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

225

(fieldval) << PHM_FIELD_SHIFT(reg, field), \

sys/dev/drm/amd/powerplay/hwmgr/smu_helper.h

226

PHM_FIELD_MASK(reg, field))

sys/dev/drm/amd/powerplay/inc/polaris10_pwrvirus.h

34

uint32_t reg;

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

51

uint32_t reg;

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

53

reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

55

phm_wait_for_register_unequal(hwmgr, reg,

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

505

uint32_t reg, data;

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

508

reg = pvirus->reg;

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

510

if (reg != 0xffffffff)

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

511

cgs_write_register(hwmgr->device, reg, data);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

64

uint32_t reg;

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

67

reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

69

ret = phm_wait_for_register_unequal(hwmgr, reg,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

73

uint32_t reg;

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

75

reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

77

phm_wait_for_register_unequal(hwmgr, reg,

sys/dev/drm/drm_mipi_dsi.c

165

u32 reg;

sys/dev/drm/drm_mipi_dsi.c

172

ret = of_property_read_u32(node, "reg", &reg);

sys/dev/drm/drm_mipi_dsi.c

179

info.channel = reg;

sys/dev/drm/i915/dvo_ch7017.c

378

#define DUMP(reg) \

sys/dev/drm/i915/dvo_ch7017.c

380

ch7017_read(dvo, reg, &val); \

sys/dev/drm/i915/dvo_ch7017.c

381

DRM_DEBUG_KMS(#reg ": %02x\n", val); \

sys/dev/drm/i915/gvt/gvt.h

380

#define vgpu_vreg(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

381

(*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

382

#define vgpu_vreg8(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

383

(*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

384

#define vgpu_vreg16(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

385

(*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

386

#define vgpu_vreg64(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

387

(*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

388

#define vgpu_sreg(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

389

(*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

390

#define vgpu_sreg8(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

391

(*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

392

#define vgpu_sreg16(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

393

(*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

394

#define vgpu_sreg64(vgpu, reg) \

sys/dev/drm/i915/gvt/gvt.h

395

(*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/i915_cmd_parser.c

1037

const struct drm_i915_reg_descriptor *reg;

sys/dev/drm/i915/i915_cmd_parser.c

1039

reg = __find_reg(table->regs, table->num_regs, addr);

sys/dev/drm/i915/i915_cmd_parser.c

1040

if (reg != NULL)

sys/dev/drm/i915/i915_cmd_parser.c

1041

return reg;

sys/dev/drm/i915/i915_cmd_parser.c

1153

const u32 step = desc->reg.step ? desc->reg.step : length;

sys/dev/drm/i915/i915_cmd_parser.c

1156

for (offset = desc->reg.offset; offset < length;

sys/dev/drm/i915/i915_cmd_parser.c

1158

const u32 reg_addr = cmd[offset] & desc->reg.mask;

sys/dev/drm/i915/i915_cmd_parser.c

1159

const struct drm_i915_reg_descriptor *reg =

sys/dev/drm/i915/i915_cmd_parser.c

1162

if (!reg) {

sys/dev/drm/i915/i915_cmd_parser.c

1172

if (reg->mask) {

sys/dev/drm/i915/i915_cmd_parser.c

1187

(cmd[offset + 1] & reg->mask) != reg->value)) {

sys/dev/drm/i915/i915_cmd_parser.c

151

} reg;

sys/dev/drm/i915/i915_cmd_parser.c

224

.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),

sys/dev/drm/i915/i915_cmd_parser.c

226

.reg = { .offset = 1, .mask = 0x007FFFFC },

sys/dev/drm/i915/i915_cmd_parser.c

233

.reg = { .offset = 1, .mask = 0x007FFFFC },

sys/dev/drm/i915/i915_cmd_parser.c

317

.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),

sys/dev/drm/i915/i915_drv.c

492

int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

sys/dev/drm/i915/i915_drv.c

498

pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);

sys/dev/drm/i915/i915_drv.c

499

pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);

sys/dev/drm/i915/i915_drv.c

522

pci_write_config_dword(dev_priv->bridge_dev, reg + 4,

sys/dev/drm/i915/i915_drv.c

525

pci_write_config_dword(dev_priv->bridge_dev, reg,

sys/dev/drm/i915/i915_drv.h

1336

struct i915_wa_reg reg[I915_MAX_WA_REGS];

sys/dev/drm/i915/i915_drv.h

3536

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);

sys/dev/drm/i915/i915_drv.h

3537

void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3538

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3539

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3540

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3541

void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3542

u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3543

void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3544

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);

sys/dev/drm/i915/i915_drv.h

3545

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3546

u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,

sys/dev/drm/i915/i915_drv.h

3548

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

sys/dev/drm/i915/i915_drv.h

3550

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/i915_drv.h

3551

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

3597

const i915_reg_t reg);

sys/dev/drm/i915/i915_drv.h

3602

const i915_reg_t reg)

sys/dev/drm/i915/i915_drv.h

3604

return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);

sys/dev/drm/i915/i915_drv.h

3607

#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)

sys/dev/drm/i915/i915_drv.h

3608

#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

sys/dev/drm/i915/i915_drv.h

3610

#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)

sys/dev/drm/i915/i915_drv.h

3611

#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)

sys/dev/drm/i915/i915_drv.h

3612

#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)

sys/dev/drm/i915/i915_drv.h

3613

#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

sys/dev/drm/i915/i915_drv.h

3615

#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)

sys/dev/drm/i915/i915_drv.h

3616

#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)

sys/dev/drm/i915/i915_drv.h

3617

#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)

sys/dev/drm/i915/i915_drv.h

3618

#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

sys/dev/drm/i915/i915_drv.h

3634

#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)

sys/dev/drm/i915/i915_drv.h

3646

#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)

sys/dev/drm/i915/i915_drv.h

3647

#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)

sys/dev/drm/i915/i915_drv.h

3651

i915_reg_t reg) \

sys/dev/drm/i915/i915_drv.h

3653

return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \

sys/dev/drm/i915/i915_drv.h

3658

i915_reg_t reg, uint##x##_t val) \

sys/dev/drm/i915/i915_drv.h

3660

write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \

sys/dev/drm/i915/i915_gem.c

2577

struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];

sys/dev/drm/i915/i915_gem.c

2590

if (!reg->vma)

sys/dev/drm/i915/i915_gem.c

2593

GEM_BUG_ON(i915_vma_has_userfault(reg->vma));

sys/dev/drm/i915/i915_gem.c

2594

reg->dirty = true;

sys/dev/drm/i915/i915_gem_fence_reg.c

149

i915_reg_t reg = FENCE_REG(fence->id);

sys/dev/drm/i915/i915_gem_fence_reg.c

151

I915_WRITE(reg, val);

sys/dev/drm/i915/i915_gem_fence_reg.c

152

POSTING_READ(reg);

sys/dev/drm/i915/i915_gem_fence_reg.c

181

i915_reg_t reg = FENCE_REG(fence->id);

sys/dev/drm/i915/i915_gem_fence_reg.c

183

I915_WRITE(reg, val);

sys/dev/drm/i915/i915_gem_fence_reg.c

184

POSTING_READ(reg);

sys/dev/drm/i915/i915_gem_fence_reg.c

476

struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];

sys/dev/drm/i915/i915_gem_fence_reg.c

477

struct i915_vma *vma = reg->vma;

sys/dev/drm/i915/i915_gem_fence_reg.c

479

GEM_BUG_ON(vma && vma->fence != reg);

sys/dev/drm/i915/i915_gem_fence_reg.c

486

GEM_BUG_ON(!reg->dirty);

sys/dev/drm/i915/i915_gem_fence_reg.c

489

list_move(&reg->link, &dev_priv->mm.fence_list);

sys/dev/drm/i915/i915_gem_fence_reg.c

494

fence_write(reg, vma);

sys/dev/drm/i915/i915_gem_fence_reg.c

495

reg->vma = vma;

sys/dev/drm/i915/i915_irq.c

1397

i915_reg_t reg;

sys/dev/drm/i915/i915_irq.c

1405

reg = GEN7_L3CDERRST1(slice);

sys/dev/drm/i915/i915_irq.c

1407

error_status = I915_READ(reg);

sys/dev/drm/i915/i915_irq.c

1412

I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);

sys/dev/drm/i915/i915_irq.c

1413

POSTING_READ(reg);

sys/dev/drm/i915/i915_irq.c

169

i915_reg_t reg)

sys/dev/drm/i915/i915_irq.c

171

u32 val = I915_READ(reg);

sys/dev/drm/i915/i915_irq.c

177

i915_mmio_reg_offset(reg), val);

sys/dev/drm/i915/i915_irq.c

178

I915_WRITE(reg, 0xffffffff);

sys/dev/drm/i915/i915_irq.c

179

POSTING_READ(reg);

sys/dev/drm/i915/i915_irq.c

180

I915_WRITE(reg, 0xffffffff);

sys/dev/drm/i915/i915_irq.c

181

POSTING_READ(reg);

sys/dev/drm/i915/i915_irq.c

185

i915_reg_t reg)

sys/dev/drm/i915/i915_irq.c

187

u16 val = I915_READ16(reg);

sys/dev/drm/i915/i915_irq.c

1887

i915_reg_t reg;

sys/dev/drm/i915/i915_irq.c

1918

reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

1919

pipe_stats[pipe] = I915_READ(reg) & status_mask;

sys/dev/drm/i915/i915_irq.c

193

i915_mmio_reg_offset(reg), val);

sys/dev/drm/i915/i915_irq.c

1932

I915_WRITE(reg, pipe_stats[pipe]);

sys/dev/drm/i915/i915_irq.c

1933

I915_WRITE(reg, enable_mask);

sys/dev/drm/i915/i915_irq.c

194

I915_WRITE16(reg, 0xffff);

sys/dev/drm/i915/i915_irq.c

195

POSTING_READ16(reg);

sys/dev/drm/i915/i915_irq.c

196

I915_WRITE16(reg, 0xffff);

sys/dev/drm/i915/i915_irq.c

197

POSTING_READ16(reg);

sys/dev/drm/i915/i915_irq.c

437

i915_reg_t reg = gen6_pm_iir(dev_priv);

sys/dev/drm/i915/i915_irq.c

441

I915_WRITE(reg, reset_mask);

sys/dev/drm/i915/i915_irq.c

442

I915_WRITE(reg, reset_mask);

sys/dev/drm/i915/i915_irq.c

443

POSTING_READ(reg);

sys/dev/drm/i915/i915_irq.c

707

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

723

I915_WRITE(reg, enable_mask | status_mask);

sys/dev/drm/i915/i915_irq.c

724

POSTING_READ(reg);

sys/dev/drm/i915/i915_irq.c

730

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

746

I915_WRITE(reg, enable_mask | status_mask);

sys/dev/drm/i915/i915_irq.c

747

POSTING_READ(reg);

sys/dev/drm/i915/i915_perf.c

1563

const struct i915_oa_reg *reg = regs + i;

sys/dev/drm/i915/i915_perf.c

1565

I915_WRITE(reg->addr, reg->value);

sys/dev/drm/i915/i915_perf.c

3036

static uint32_t mask_reg_value(u32 reg, u32 val)

sys/dev/drm/i915/i915_perf.c

3042

if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg)

sys/dev/drm/i915/i915_perf.c

3049

if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg)

sys/dev/drm/i915/i915_reg.h

120

uint32_t reg;

sys/dev/drm/i915/i915_reg.h

123

#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })

sys/dev/drm/i915/i915_reg.h

127

static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)

sys/dev/drm/i915/i915_reg.h

129

return reg.reg;

sys/dev/drm/i915/i915_reg.h

137

static inline bool i915_mmio_reg_valid(i915_reg_t reg)

sys/dev/drm/i915/i915_reg.h

139

return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);

sys/dev/drm/i915/i915_reg.h

1530

#define _BXT_PHY(phy, reg) \

sys/dev/drm/i915/i915_reg.h

1531

_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

sys/dev/drm/i915/i915_reg.h

4074

#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \

sys/dev/drm/i915/i915_reg.h

4075

dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \

sys/dev/drm/i915/i915_reg.h

4613

#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \

sys/dev/drm/i915/i915_reg.h

4614

PPS_BASE + (reg) + \

sys/dev/drm/i915/i915_reg.h

5643

#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \

sys/dev/drm/i915/i915_reg.h

5644

dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \

sys/dev/drm/i915/i915_reg.h

6094

#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \

sys/dev/drm/i915/i915_reg.h

6095

dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \

sys/dev/drm/i915/i915_reg.h

6460

#define _MMIO_CHV_SPCSC(plane_id, reg) \

sys/dev/drm/i915/i915_reg.h

6461

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

sys/dev/drm/i915/i915_reg.h

8641

#define GEN7_PARITY_ERROR_ROW(reg) \

sys/dev/drm/i915/i915_reg.h

8642

(((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)

sys/dev/drm/i915/i915_reg.h

8643

#define GEN7_PARITY_ERROR_BANK(reg) \

sys/dev/drm/i915/i915_reg.h

8644

(((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)

sys/dev/drm/i915/i915_reg.h

8645

#define GEN7_PARITY_ERROR_SUBBANK(reg) \

sys/dev/drm/i915/i915_reg.h

8646

(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)

sys/dev/drm/i915/i915_sysfs.c

44

i915_reg_t reg)

sys/dev/drm/i915/i915_sysfs.c

49

res = intel_rc6_residency_us(dev_priv, reg);

sys/dev/drm/i915/intel_ddi.c

1030

i915_reg_t reg = DDI_BUF_CTL(port);

sys/dev/drm/i915/intel_ddi.c

1035

if (I915_READ(reg) & DDI_BUF_IS_IDLE)

sys/dev/drm/i915/intel_ddi.c

1273

i915_reg_t reg)

sys/dev/drm/i915/intel_ddi.c

1279

wrpll = I915_READ(reg);

sys/dev/drm/i915/intel_ddi.c

1897

i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);

sys/dev/drm/i915/intel_ddi.c

1898

uint32_t val = I915_READ(reg);

sys/dev/drm/i915/intel_ddi.c

1902

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_display.c

1048

i915_reg_t reg = PIPEDSL(pipe);

sys/dev/drm/i915/intel_display.c

1057

line1 = I915_READ(reg) & line_mask;

sys/dev/drm/i915/intel_display.c

1059

line2 = I915_READ(reg) & line_mask;

sys/dev/drm/i915/intel_display.c

1093

i915_reg_t reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1097

reg, I965_PIPECONF_ACTIVE, 0,

sys/dev/drm/i915/intel_display.c

1512

i915_reg_t reg = DPLL(crtc->pipe);

sys/dev/drm/i915/intel_display.c

1540

I915_WRITE(reg, 0);

sys/dev/drm/i915/intel_display.c

1542

I915_WRITE(reg, dpll);

sys/dev/drm/i915/intel_display.c

1545

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

1557

I915_WRITE(reg, dpll);

sys/dev/drm/i915/intel_display.c

1562

I915_WRITE(reg, dpll);

sys/dev/drm/i915/intel_display.c

1563

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

15636

i915_reg_t reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

15638

I915_WRITE(reg,

sys/dev/drm/i915/intel_display.c

15639

I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);

sys/dev/drm/i915/intel_display.c

16236

unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;

sys/dev/drm/i915/intel_display.c

16239

if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {

sys/dev/drm/i915/intel_display.c

16252

if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {

sys/dev/drm/i915/intel_display.c

1674

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1687

reg = TRANS_CHICKEN2(pipe);

sys/dev/drm/i915/intel_display.c

1688

val = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

1690

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_display.c

1693

reg = PCH_TRANSCONF(pipe);

sys/dev/drm/i915/intel_display.c

1694

val = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

1720

I915_WRITE(reg, val | TRANS_ENABLE);

sys/dev/drm/i915/intel_display.c

1722

reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,

sys/dev/drm/i915/intel_display.c

1762

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1772

reg = PCH_TRANSCONF(pipe);

sys/dev/drm/i915/intel_display.c

1773

val = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

1775

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_display.c

1778

reg, TRANS_STATE_ENABLE, 0,

sys/dev/drm/i915/intel_display.c

1784

reg = TRANS_CHICKEN2(pipe);

sys/dev/drm/i915/intel_display.c

1785

val = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

1787

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_display.c

1826

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1854

reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1855

val = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

1862

I915_WRITE(reg, val | PIPECONF_ENABLE);

sys/dev/drm/i915/intel_display.c

1863

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

1882

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1893

reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1894

val = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

1909

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_display.c

194

const char *name, u32 reg, int ref_freq)

sys/dev/drm/i915/intel_display.c

200

val = vlv_cck_read(dev_priv, reg);

sys/dev/drm/i915/intel_display.c

213

const char *name, u32 reg)

sys/dev/drm/i915/intel_display.c

218

return vlv_get_cck_clock(dev_priv, name, reg,

sys/dev/drm/i915/intel_display.c

3402

i915_reg_t reg = DSPCNTR(i9xx_plane);

sys/dev/drm/i915/intel_display.c

3433

I915_WRITE_FW(reg, dspcntr);

sys/dev/drm/i915/intel_display.c

3452

POSTING_READ_FW(reg);

sys/dev/drm/i915/intel_display.c

3953

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

3957

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

3958

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

3966

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

3968

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

3969

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

3977

I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

sys/dev/drm/i915/intel_display.c

3980

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

3985

I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |

sys/dev/drm/i915/intel_display.c

3996

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4004

reg = FDI_RX_IMR(pipe);

sys/dev/drm/i915/intel_display.c

4005

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4008

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4009

I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4013

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4014

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4019

I915_WRITE(reg, temp | FDI_TX_ENABLE);

sys/dev/drm/i915/intel_display.c

4021

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4022

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4025

I915_WRITE(reg, temp | FDI_RX_ENABLE);

sys/dev/drm/i915/intel_display.c

4027

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4035

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4037

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4042

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

sys/dev/drm/i915/intel_display.c

4050

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4051

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4054

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4056

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4057

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4060

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4062

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4065

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4067

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4071

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

sys/dev/drm/i915/intel_display.c

4097

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4102

reg = FDI_RX_IMR(pipe);

sys/dev/drm/i915/intel_display.c

4103

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4106

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4108

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4112

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4113

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4121

I915_WRITE(reg, temp | FDI_TX_ENABLE);

sys/dev/drm/i915/intel_display.c

4126

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4127

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4135

I915_WRITE(reg, temp | FDI_RX_ENABLE);

sys/dev/drm/i915/intel_display.c

4137

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4141

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4142

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4145

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4147

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4151

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4152

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4155

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

sys/dev/drm/i915/intel_display.c

4168

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4169

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4177

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4179

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4180

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4188

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4190

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4194

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4195

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4198

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4200

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4204

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4205

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4208

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

sys/dev/drm/i915/intel_display.c

4230

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4235

reg = FDI_RX_IMR(pipe);

sys/dev/drm/i915/intel_display.c

4236

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4239

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4241

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4250

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4251

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4254

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4256

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4257

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4261

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4264

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4265

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4272

I915_WRITE(reg, temp | FDI_TX_ENABLE);

sys/dev/drm/i915/intel_display.c

4277

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4278

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4281

I915_WRITE(reg, temp | FDI_RX_ENABLE);

sys/dev/drm/i915/intel_display.c

4283

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4287

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4288

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4292

(I915_READ(reg) & FDI_RX_BIT_LOCK)) {

sys/dev/drm/i915/intel_display.c

4293

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

sys/dev/drm/i915/intel_display.c

4306

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4307

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4310

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4312

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4313

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4316

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4318

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4322

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4323

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4327

(I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {

sys/dev/drm/i915/intel_display.c

4328

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

sys/dev/drm/i915/intel_display.c

4348

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4352

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4353

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4357

I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

sys/dev/drm/i915/intel_display.c

4359

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4363

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4364

I915_WRITE(reg, temp | FDI_PCDCLK);

sys/dev/drm/i915/intel_display.c

4366

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4370

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4371

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4373

I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

sys/dev/drm/i915/intel_display.c

4375

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4385

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4389

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4390

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4391

I915_WRITE(reg, temp & ~FDI_PCDCLK);

sys/dev/drm/i915/intel_display.c

4394

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4395

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4396

I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

sys/dev/drm/i915/intel_display.c

4398

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4401

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4402

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4403

I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

sys/dev/drm/i915/intel_display.c

4406

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4416

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4420

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4421

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4422

I915_WRITE(reg, temp & ~FDI_TX_ENABLE);

sys/dev/drm/i915/intel_display.c

4423

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4425

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4426

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4429

I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

sys/dev/drm/i915/intel_display.c

4431

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4439

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4440

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4443

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4445

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4446

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4457

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

4459

POSTING_READ(reg);

sys/dev/drm/i915/intel_display.c

4782

i915_reg_t reg = TRANS_DP_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4785

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

4801

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

5922

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

5926

reg = TRANS_DP_CTL(pipe);

sys/dev/drm/i915/intel_display.c

5927

temp = I915_READ(reg);

sys/dev/drm/i915/intel_display.c

5931

I915_WRITE(reg, temp);

sys/dev/drm/i915/intel_display.c

8352

uint32_t reg, tmp;

sys/dev/drm/i915/intel_display.c

8380

reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;

sys/dev/drm/i915/intel_display.c

8381

tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);

sys/dev/drm/i915/intel_display.c

8383

intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);

sys/dev/drm/i915/intel_display.c

8391

uint32_t reg, tmp;

sys/dev/drm/i915/intel_display.c

8395

reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;

sys/dev/drm/i915/intel_display.c

8396

tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);

sys/dev/drm/i915/intel_display.c

8398

intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);

sys/dev/drm/i915/intel_dp.c

6116

i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);

sys/dev/drm/i915/intel_dp.c

6119

val = I915_READ(reg);

sys/dev/drm/i915/intel_dp.c

6131

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_dpio_phy.c

489

i915_reg_t reg, u32 mask, u32 expected,

sys/dev/drm/i915/intel_dpio_phy.c

496

val = I915_READ(reg);

sys/dev/drm/i915/intel_dpio_phy.c

506

phy, &vaf, reg.reg, val, (val & ~mask) | expected,

sys/dev/drm/i915/intel_dpio_phy.c

523

#define _CHK(reg, mask, exp, fmt, ...) \

sys/dev/drm/i915/intel_dpio_phy.c

524

__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \

sys/dev/drm/i915/intel_drv.h

1509

const char *name, u32 reg, int ref_freq);

sys/dev/drm/i915/intel_drv.h

1511

const char *name, u32 reg);

sys/dev/drm/i915/intel_drv.h

2133

i915_reg_t reg, enum port port);

sys/dev/drm/i915/intel_engine_cs.c

786

int subslice, i915_reg_t reg)

sys/dev/drm/i915/intel_engine_cs.c

809

fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,

sys/dev/drm/i915/intel_engine_cs.c

827

ret = I915_READ_FW(reg);

sys/dev/drm/i915/intel_fifo_underrun.c

100

POSTING_READ(reg);

sys/dev/drm/i915/intel_fifo_underrun.c

111

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

118

I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

sys/dev/drm/i915/intel_fifo_underrun.c

119

POSTING_READ(reg);

sys/dev/drm/i915/intel_fifo_underrun.c

121

if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/drm/i915/intel_fifo_underrun.c

90

i915_reg_t reg = PIPESTAT(crtc->pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

95

if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

sys/dev/drm/i915/intel_fifo_underrun.c

99

I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

sys/dev/drm/i915/intel_hdcp.c

474

u32 reg[2];

sys/dev/drm/i915/intel_hdcp.c

478

u32 reg[2];

sys/dev/drm/i915/intel_hdcp.c

482

u32 reg;

sys/dev/drm/i915/intel_hdcp.c

520

an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));

sys/dev/drm/i915/intel_hdcp.c

521

an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));

sys/dev/drm/i915/intel_hdcp.c

543

I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);

sys/dev/drm/i915/intel_hdcp.c

544

I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);

sys/dev/drm/i915/intel_hdcp.c

584

ri.reg = 0;

sys/dev/drm/i915/intel_hdcp.c

588

I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);

sys/dev/drm/i915/intel_hdmi.c

1103

u32 reg;

sys/dev/drm/i915/intel_hdmi.c

1111

I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);

sys/dev/drm/i915/intel_hdmi.c

215

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

216

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

226

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

242

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

243

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

252

i915_reg_t reg = TVIDEO_DIP_CTL(pipe);

sys/dev/drm/i915/intel_hdmi.c

253

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

275

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

276

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

289

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

305

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

306

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

333

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

334

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

344

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

360

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

361

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

550

i915_reg_t reg = VIDEO_DIP_CTL;

sys/dev/drm/i915/intel_hdmi.c

551

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

577

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

578

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

596

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

597

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

666

i915_reg_t reg;

sys/dev/drm/i915/intel_hdmi.c

670

reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);

sys/dev/drm/i915/intel_hdmi.c

672

reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

674

reg = TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

687

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

701

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

702

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

716

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

717

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

737

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

738

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

753

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

754

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

767

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

768

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

780

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

781

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

797

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

798

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

812

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

813

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

833

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

834

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

847

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);

sys/dev/drm/i915/intel_hdmi.c

848

u32 val = I915_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

858

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

859

POSTING_READ(reg);

sys/dev/drm/i915/intel_hdmi.c

866

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_hdmi.c

867

POSTING_READ(reg);

sys/dev/drm/i915/intel_lrc.c

1535

i915_reg_t reg;

sys/dev/drm/i915/intel_lrc.c

1545

*batch++ = i915_mmio_reg_offset(lri->reg);

sys/dev/drm/i915/intel_lrc_reg.h

42

#define CTX_REG(reg_state, pos, reg, val) do { \

sys/dev/drm/i915/intel_lrc_reg.h

45

(reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_lvds.c

114

ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);

sys/dev/drm/i915/intel_lvds.c

130

tmp = I915_READ(lvds_encoder->reg);

sys/dev/drm/i915/intel_lvds.c

308

I915_WRITE(lvds_encoder->reg, temp);

sys/dev/drm/i915/intel_lvds.c

322

I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);

sys/dev/drm/i915/intel_lvds.c

325

POSTING_READ(lvds_encoder->reg);

sys/dev/drm/i915/intel_lvds.c

344

I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);

sys/dev/drm/i915/intel_lvds.c

345

POSTING_READ(lvds_encoder->reg);

sys/dev/drm/i915/intel_lvds.c

68

i915_reg_t reg;

sys/dev/drm/i915/intel_lvds.c

819

val = I915_READ(lvds_encoder->reg);

sys/dev/drm/i915/intel_lvds.c

970

lvds_encoder->reg = lvds_reg;

sys/dev/drm/i915/intel_pm.c

3940

struct skl_ddb_entry *entry, u32 reg)

sys/dev/drm/i915/intel_pm.c

3948

entry->start = reg & mask;

sys/dev/drm/i915/intel_pm.c

3949

entry->end = (reg >> DDB_ENTRY_END_SHIFT) & mask;

sys/dev/drm/i915/intel_pm.c

5013

i915_reg_t reg,

sys/dev/drm/i915/intel_pm.c

5017

I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);

sys/dev/drm/i915/intel_pm.c

5019

I915_WRITE(reg, 0);

sys/dev/drm/i915/intel_pm.c

5023

i915_reg_t reg,

sys/dev/drm/i915/intel_pm.c

5034

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_pm.c

845

u32 reg;

sys/dev/drm/i915/intel_pm.c

871

reg = I915_READ(DSPFW1);

sys/dev/drm/i915/intel_pm.c

8713

uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);

sys/dev/drm/i915/intel_pm.c

872

reg &= ~DSPFW_SR_MASK;

sys/dev/drm/i915/intel_pm.c

8721

reg &= ~GEN7_FF_SCHED_MASK;

sys/dev/drm/i915/intel_pm.c

8722

reg |= GEN7_FF_TS_SCHED_HW;

sys/dev/drm/i915/intel_pm.c

8723

reg |= GEN7_FF_VS_SCHED_HW;

sys/dev/drm/i915/intel_pm.c

8724

reg |= GEN7_FF_DS_SCHED_HW;

sys/dev/drm/i915/intel_pm.c

8726

I915_WRITE(GEN7_FF_THREAD_MODE, reg);

sys/dev/drm/i915/intel_pm.c

873

reg |= FW_WM(wm, SR);

sys/dev/drm/i915/intel_pm.c

874

I915_WRITE(DSPFW1, reg);

sys/dev/drm/i915/intel_pm.c

875

DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);

sys/dev/drm/i915/intel_pm.c

881

reg = I915_READ(DSPFW3);

sys/dev/drm/i915/intel_pm.c

882

reg &= ~DSPFW_CURSOR_SR_MASK;

sys/dev/drm/i915/intel_pm.c

883

reg |= FW_WM(wm, CURSOR_SR);

sys/dev/drm/i915/intel_pm.c

884

I915_WRITE(DSPFW3, reg);

sys/dev/drm/i915/intel_pm.c

890

reg = I915_READ(DSPFW3);

sys/dev/drm/i915/intel_pm.c

891

reg &= ~DSPFW_HPLL_SR_MASK;

sys/dev/drm/i915/intel_pm.c

892

reg |= FW_WM(wm, HPLL_SR);

sys/dev/drm/i915/intel_pm.c

893

I915_WRITE(DSPFW3, reg);

sys/dev/drm/i915/intel_pm.c

899

reg = I915_READ(DSPFW3);

sys/dev/drm/i915/intel_pm.c

900

reg &= ~DSPFW_HPLL_CURSOR_MASK;

sys/dev/drm/i915/intel_pm.c

901

reg |= FW_WM(wm, HPLL_CURSOR);

sys/dev/drm/i915/intel_pm.c

902

I915_WRITE(DSPFW3, reg);

sys/dev/drm/i915/intel_pm.c

903

DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);

sys/dev/drm/i915/intel_pm.c

9732

const i915_reg_t reg)

sys/dev/drm/i915/intel_pm.c

9755

upper = I915_READ_FW(reg);

sys/dev/drm/i915/intel_pm.c

9761

lower = I915_READ_FW(reg);

sys/dev/drm/i915/intel_pm.c

9765

upper = I915_READ_FW(reg);

sys/dev/drm/i915/intel_pm.c

9778

const i915_reg_t reg)

sys/dev/drm/i915/intel_pm.c

9796

i = (i915_mmio_reg_offset(reg) -

sys/dev/drm/i915/intel_pm.c

9801

fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);

sys/dev/drm/i915/intel_pm.c

9811

time_hw = vlv_residency_raw(dev_priv, reg);

sys/dev/drm/i915/intel_pm.c

9823

time_hw = I915_READ_FW(reg);

sys/dev/drm/i915/intel_psr.c

787

i915_reg_t reg;

sys/dev/drm/i915/intel_psr.c

795

reg = EDP_PSR2_STATUS;

sys/dev/drm/i915/intel_psr.c

798

reg = EDP_PSR_STATUS;

sys/dev/drm/i915/intel_psr.c

804

err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);

sys/dev/drm/i915/intel_ringbuffer.c

449

i915_reg_t reg = RING_INSTPM(engine->mmio_base);

sys/dev/drm/i915/intel_ringbuffer.c

454

I915_WRITE(reg,

sys/dev/drm/i915/intel_ringbuffer.c

458

reg, INSTPM_SYNC_FLUSH, 0,

sys/dev/drm/i915/intel_ringbuffer.h

745

intel_read_status_page(const struct intel_engine_cs *engine, int reg)

sys/dev/drm/i915/intel_ringbuffer.h

748

return READ_ONCE(engine->status_page.page_addr[reg]);

sys/dev/drm/i915/intel_ringbuffer.h

752

intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)

sys/dev/drm/i915/intel_ringbuffer.h

761

linux_clflush(&engine->status_page.page_addr[reg]);

sys/dev/drm/i915/intel_ringbuffer.h

762

engine->status_page.page_addr[reg] = value;

sys/dev/drm/i915/intel_ringbuffer.h

763

linux_clflush(&engine->status_page.page_addr[reg]);

sys/dev/drm/i915/intel_ringbuffer.h

766

WRITE_ONCE(engine->status_page.page_addr[reg], value);

sys/dev/drm/i915/intel_runtime_pm.c

1312

u32 reg, val, expected, actual;

sys/dev/drm/i915/intel_runtime_pm.c

1325

reg = _CHV_CMN_DW0_CH0;

sys/dev/drm/i915/intel_runtime_pm.c

1327

reg = _CHV_CMN_DW6_CH1;

sys/dev/drm/i915/intel_runtime_pm.c

1330

val = vlv_dpio_read(dev_priv, pipe, reg);

sys/dev/drm/i915/intel_runtime_pm.c

1367

reg, val);

sys/dev/drm/i915/intel_runtime_pm.c

3140

i915_reg_t reg, bool enable)

sys/dev/drm/i915/intel_runtime_pm.c

3144

val = I915_READ(reg);

sys/dev/drm/i915/intel_runtime_pm.c

3146

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_runtime_pm.c

3147

POSTING_READ(reg);

sys/dev/drm/i915/intel_runtime_pm.c

3150

status = I915_READ(reg) & DBUF_POWER_STATE;

sys/dev/drm/i915/intel_runtime_pm.c

318

if (regs->kvmr.reg)

sys/dev/drm/i915/intel_sideband.c

108

u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

113

SB_CRRDDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

118

void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

121

SB_CRWRDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

138

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)

sys/dev/drm/i915/intel_sideband.c

142

SB_CRRDDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

147

u8 port, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

150

SB_CRWRDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

153

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

157

SB_CRRDDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

161

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

164

SB_CRWRDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

167

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

171

SB_CRRDDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

175

void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

178

SB_CRWRDA_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

181

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg)

sys/dev/drm/i915/intel_sideband.c

186

SB_MRD_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

193

pipe_name(pipe), reg, val);

sys/dev/drm/i915/intel_sideband.c

198

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

201

SB_MWR_NP, reg, &val);

sys/dev/drm/i915/intel_sideband.c

205

u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,

sys/dev/drm/i915/intel_sideband.c

218

I915_WRITE(SBI_ADDR, (reg << 16));

sys/dev/drm/i915/intel_sideband.c

237

DRM_ERROR("error during SBI read of reg %x\n", reg);

sys/dev/drm/i915/intel_sideband.c

244

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

sys/dev/drm/i915/intel_sideband.c

258

I915_WRITE(SBI_ADDR, (reg << 16));

sys/dev/drm/i915/intel_sideband.c

278

value, reg);

sys/dev/drm/i915/intel_sideband.c

283

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)

sys/dev/drm/i915/intel_sideband.c

287

reg, &val);

sys/dev/drm/i915/intel_sideband.c

291

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

294

reg, &val);

sys/dev/drm/i915/intel_uncore.c

1086

const i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

1093

i915_mmio_reg_offset(reg)))

sys/dev/drm/i915/intel_uncore.c

1100

const i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

1107

__unclaimed_reg_debug(dev_priv, reg, read, before);

sys/dev/drm/i915/intel_uncore.c

1115

trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \

sys/dev/drm/i915/intel_uncore.c

1120

gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1122

val = __raw_i915_read##x(dev_priv, reg); \

sys/dev/drm/i915/intel_uncore.c

1128

gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1131

val = __raw_i915_read##x(dev_priv, reg); \

sys/dev/drm/i915/intel_uncore.c

1151

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_uncore.c

1156

unclaimed_reg_debug(dev_priv, reg, true, true)

sys/dev/drm/i915/intel_uncore.c

1159

unclaimed_reg_debug(dev_priv, reg, true, false); \

sys/dev/drm/i915/intel_uncore.c

1161

trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \

sys/dev/drm/i915/intel_uncore.c

1194

func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1200

val = __raw_i915_read##x(dev_priv, reg); \

sys/dev/drm/i915/intel_uncore.c

1227

trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \

sys/dev/drm/i915/intel_uncore.c

1234

gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1236

__raw_i915_write##x(dev_priv, reg, val); \

sys/dev/drm/i915/intel_uncore.c

1242

gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1245

__raw_i915_write##x(dev_priv, reg, val); \

sys/dev/drm/i915/intel_uncore.c

1263

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_uncore.c

1265

trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \

sys/dev/drm/i915/intel_uncore.c

1268

unclaimed_reg_debug(dev_priv, reg, false, true)

sys/dev/drm/i915/intel_uncore.c

1271

unclaimed_reg_debug(dev_priv, reg, false, false); \

sys/dev/drm/i915/intel_uncore.c

1276

gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1280

__raw_i915_write##x(dev_priv, reg, val); \

sys/dev/drm/i915/intel_uncore.c

1286

func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1292

__raw_i915_write##x(dev_priv, reg, val); \

sys/dev/drm/i915/intel_uncore.c

1671

struct drm_i915_reg_read *reg = data;

sys/dev/drm/i915/intel_uncore.c

1687

entry_offset == (reg->offset & -entry->size))

sys/dev/drm/i915/intel_uncore.c

1696

flags = reg->offset & (entry->size - 1);

sys/dev/drm/i915/intel_uncore.c

1700

reg->val = I915_READ64_2x32(entry->offset_ldw,

sys/dev/drm/i915/intel_uncore.c

1703

reg->val = I915_READ64(entry->offset_ldw);

sys/dev/drm/i915/intel_uncore.c

1705

reg->val = I915_READ(entry->offset_ldw);

sys/dev/drm/i915/intel_uncore.c

1707

reg->val = I915_READ16(entry->offset_ldw);

sys/dev/drm/i915/intel_uncore.c

1709

reg->val = I915_READ8(entry->offset_ldw);

sys/dev/drm/i915/intel_uncore.c

2005

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

2013

#define done (((reg_value = I915_READ_FW(reg)) & mask) == value)

sys/dev/drm/i915/intel_uncore.c

2053

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

2061

intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);

sys/dev/drm/i915/intel_uncore.c

2071

reg, mask, value,

sys/dev/drm/i915/intel_uncore.c

2078

ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),

sys/dev/drm/i915/intel_uncore.c

2312

i915_reg_t reg)

sys/dev/drm/i915/intel_uncore.c

2314

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_uncore.c

2335

i915_reg_t reg)

sys/dev/drm/i915/intel_uncore.c

2337

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_uncore.c

2374

i915_reg_t reg, unsigned int op)

sys/dev/drm/i915/intel_uncore.c

2384

fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);

sys/dev/drm/i915/intel_uncore.c

2387

fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);

sys/dev/drm/i915/intel_uncore.c

804

#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)

sys/dev/drm/i915/intel_uncore.c

806

#define GEN11_NEEDS_FORCE_WAKE(reg) \

sys/dev/drm/i915/intel_uncore.c

807

((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))

sys/dev/drm/i915/intel_uncore.c

936

static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)

sys/dev/drm/i915/intel_uncore.c

938

u32 offset = i915_mmio_reg_offset(*reg);

sys/dev/drm/i915/intel_uncore.h

160

i915_reg_t reg, unsigned int op);

sys/dev/drm/i915/intel_uncore.h

180

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

188

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

193

return __intel_wait_for_register(dev_priv, reg, mask, value, 2,

sys/dev/drm/i915/intel_uncore.h

197

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

205

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

210

return __intel_wait_for_register_fw(dev_priv, reg, mask, value,

sys/dev/drm/i915/intel_uncore.h

214

#define raw_reg_read(base, reg) \

sys/dev/drm/i915/intel_uncore.h

215

readl(base + i915_mmio_reg_offset(reg))

sys/dev/drm/i915/intel_uncore.h

216

#define raw_reg_write(base, reg, value) \

sys/dev/drm/i915/intel_uncore.h

217

writel(value, base + i915_mmio_reg_offset(reg))

sys/dev/drm/i915/intel_wopcm.c

220

i915_reg_t reg, u32 val, u32 mask,

sys/dev/drm/i915/intel_wopcm.c

227

I915_WRITE(reg, val);

sys/dev/drm/i915/intel_wopcm.c

229

reg_val = I915_READ(reg);

sys/dev/drm/i915/intel_workarounds.c

102

r = &wa->reg[wa->count++];

sys/dev/drm/i915/intel_workarounds.c

107

while (r-- > wa->reg) {

sys/dev/drm/i915/intel_workarounds.c

1113

i915_mmio_reg_offset(w->reg[i]));

sys/dev/drm/i915/intel_workarounds.c

583

*cs++ = w->reg[i].addr;

sys/dev/drm/i915/intel_workarounds.c

584

*cs++ = w->reg[i].value;

sys/dev/drm/i915/intel_workarounds.c

624

wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

627

.reg = reg,

sys/dev/drm/i915/intel_workarounds.c

636

wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,

sys/dev/drm/i915/intel_workarounds.c

640

.reg = reg,

sys/dev/drm/i915/intel_workarounds.c

649

wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

651

wa_write_masked_or(wal, reg, ~0, val);

sys/dev/drm/i915/intel_workarounds.c

655

wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

657

wa_write_masked_or(wal, reg, val, val);

sys/dev/drm/i915/intel_workarounds.c

66

i915_reg_t reg, const u32 mask, const u32 val)

sys/dev/drm/i915/intel_workarounds.c

70

unsigned int addr = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_workarounds.c

76

if (wa->reg[mid].addr < addr) {

sys/dev/drm/i915/intel_workarounds.c

78

} else if (wa->reg[mid].addr > addr) {

sys/dev/drm/i915/intel_workarounds.c

81

r = &wa->reg[mid];

sys/dev/drm/i915/intel_workarounds.c

942

wa->reg,

sys/dev/drm/i915/intel_workarounds.c

966

u32 val = I915_READ_FW(wa->reg);

sys/dev/drm/i915/intel_workarounds.c

971

I915_WRITE_FW(wa->reg, val);

sys/dev/drm/i915/intel_workarounds.c

986

i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];

sys/dev/drm/i915/intel_workarounds.c

991

static void whitelist_reg(struct whitelist *w, i915_reg_t reg)

sys/dev/drm/i915/intel_workarounds.c

996

w->reg[w->count++] = reg;

sys/dev/drm/i915/intel_workarounds.h

13

i915_reg_t reg;

sys/dev/drm/i915/vlv_dsi.c

100

I915_WRITE(reg, val);

sys/dev/drm/i915/vlv_dsi.c

105

i915_reg_t reg,

sys/dev/drm/i915/vlv_dsi.c

111

u32 val = I915_READ(reg);

sys/dev/drm/i915/vlv_dsi.c

89

i915_reg_t reg,

sys/dev/drm/include/linux/pci.h

413

int reg;

sys/dev/drm/include/linux/pci.h

415

if (pci_find_extcap(pdev->dev.bsddev, capid, &reg))

sys/dev/drm/include/linux/pci.h

417

return (reg);

sys/dev/drm/include/uapi/drm/radeon_drm.h

276

unsigned char cmd_type, reg, n_bufs, flags;

sys/dev/drm/radeon/atombios_encoders.c

1602

uint32_t temp, reg;

sys/dev/drm/radeon/atombios_encoders.c

1607

reg = R600_BIOS_3_SCRATCH;

sys/dev/drm/radeon/atombios_encoders.c

1609

reg = RADEON_BIOS_3_SCRATCH;

sys/dev/drm/radeon/atombios_encoders.c

1612

temp = RREG32(reg);

sys/dev/drm/radeon/atombios_encoders.c

1614

WREG32(reg, (ATOM_S3_TV1_ACTIVE |

sys/dev/drm/radeon/atombios_encoders.c

1617

WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));

sys/dev/drm/radeon/atombios_encoders.c

1619

WREG32(reg, 0);

sys/dev/drm/radeon/atombios_encoders.c

1627

WREG32(reg, temp);

sys/dev/drm/radeon/atombios_encoders.c

1687

u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);

sys/dev/drm/radeon/atombios_encoders.c

1688

WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);

sys/dev/drm/radeon/atombios_encoders.c

1690

WREG32(RADEON_BIOS_3_SCRATCH, reg);

sys/dev/drm/radeon/cik.c

145

u32 reg, u32 *val)

sys/dev/drm/radeon/cik.c

147

switch (reg) {

sys/dev/drm/radeon/cik.c

160

*val = RREG32(reg);

sys/dev/drm/radeon/cik.c

170

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/cik.c

176

WREG32(CIK_DIDT_IND_INDEX, (reg));

sys/dev/drm/radeon/cik.c

182

void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/cik.c

187

WREG32(CIK_DIDT_IND_INDEX, (reg));

sys/dev/drm/radeon/cik.c

232

u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/cik.c

238

WREG32(PCIE_INDEX, reg);

sys/dev/drm/radeon/cik.c

245

void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/cik.c

250

WREG32(PCIE_INDEX, reg);

sys/dev/drm/radeon/cik.c

3456

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

sys/dev/drm/radeon/cik.c

5567

uint32_t reg;

sys/dev/drm/radeon/cik.c

5569

reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);

sys/dev/drm/radeon/cik.c

5571

reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);

sys/dev/drm/radeon/cik.c

5572

rdev->vm_manager.saved_table_addr[i] = RREG32(reg);

sys/dev/drm/radeon/cik_sdma.c

112

u32 reg;

sys/dev/drm/radeon/cik_sdma.c

115

reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

117

reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

119

WREG32(reg, (ring->wptr << 2) & 0x3fffc);

sys/dev/drm/radeon/cik_sdma.c

120

(void)RREG32(reg);

sys/dev/drm/radeon/cik_sdma.c

64

u32 rptr, reg;

sys/dev/drm/radeon/cik_sdma.c

70

reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

72

reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

74

rptr = RREG32(reg);

sys/dev/drm/radeon/cik_sdma.c

91

u32 reg;

sys/dev/drm/radeon/cik_sdma.c

94

reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

96

reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

98

return (RREG32(reg) & 0x3fffc) >> 2;

sys/dev/drm/radeon/cikd.h

1682

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

sys/dev/drm/radeon/cikd.h

1683

(((reg) >> 2) & 0xFFFF) | \

sys/dev/drm/radeon/dce6_afmt.c

33

u32 block_offset, u32 reg);

sys/dev/drm/radeon/dce6_afmt.c

35

u32 block_offset, u32 reg, u32 v);

sys/dev/drm/radeon/dce6_afmt.c

45

u32 block_offset, u32 reg)

sys/dev/drm/radeon/dce6_afmt.c

50

WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/radeon/dce6_afmt.c

58

u32 block_offset, u32 reg, u32 v)

sys/dev/drm/radeon/dce6_afmt.c

62

WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/radeon/dce6_afmt.c

65

AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));

sys/dev/drm/radeon/evergreen.c

101

void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/evergreen.c

106

WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

1079

u32 reg, u32 *val)

sys/dev/drm/radeon/evergreen.c

1081

switch (reg) {

sys/dev/drm/radeon/evergreen.c

1089

*val = RREG32(reg);

sys/dev/drm/radeon/evergreen.c

45

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/evergreen.c

51

WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

57

void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/evergreen.c

62

WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

67

u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/evergreen.c

73

WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

79

void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/evergreen.c

84

WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

89

u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/evergreen.c

95

WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen_cs.c

1048

unsigned idx, unsigned reg)

sys/dev/drm/radeon/evergreen_cs.c

1052

switch (reg) {

sys/dev/drm/radeon/evergreen_cs.c

1057

idx, reg);

sys/dev/drm/radeon/evergreen_cs.c

1062

pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);

sys/dev/drm/radeon/evergreen_cs.c

1071

unsigned reg, i;

sys/dev/drm/radeon/evergreen_cs.c

1076

reg = pkt->reg;

sys/dev/drm/radeon/evergreen_cs.c

1077

for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {

sys/dev/drm/radeon/evergreen_cs.c

1078

r = evergreen_packet0_check(p, pkt, idx, reg);

sys/dev/drm/radeon/evergreen_cs.c

1092

static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/drm/radeon/evergreen_cs.c

1100

switch (reg) {

sys/dev/drm/radeon/evergreen_cs.c

1144

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1156

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1163

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1173

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1215

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1227

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1239

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1251

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1274

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1277

tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;

sys/dev/drm/radeon/evergreen_cs.c

1287

tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;

sys/dev/drm/radeon/evergreen_cs.c

1296

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1312

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1321

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1335

tmp = (reg - CB_COLOR0_VIEW) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1343

tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;

sys/dev/drm/radeon/evergreen_cs.c

1355

tmp = (reg - CB_COLOR0_INFO) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1361

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1373

tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;

sys/dev/drm/radeon/evergreen_cs.c

1379

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1395

tmp = (reg - CB_COLOR0_PITCH) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1403

tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;

sys/dev/drm/radeon/evergreen_cs.c

1415

tmp = (reg - CB_COLOR0_SLICE) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1424

tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;

sys/dev/drm/radeon/evergreen_cs.c

1440

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1457

tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);

sys/dev/drm/radeon/evergreen_cs.c

1468

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1485

tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;

sys/dev/drm/radeon/evergreen_cs.c

1497

tmp = (reg - CB_COLOR0_FMASK) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1500

dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1514

tmp = (reg - CB_COLOR0_CMASK) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1517

dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1531

tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1542

tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1556

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1559

tmp = (reg - CB_COLOR0_BASE) / 0x3c;

sys/dev/drm/radeon/evergreen_cs.c

1572

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1575

tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;

sys/dev/drm/radeon/evergreen_cs.c

1585

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1703

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1711

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1717

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1725

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1731

"0x%04X\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

1740

dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

sys/dev/drm/radeon/evergreen_cs.c

1754

static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg)

sys/dev/drm/radeon/evergreen_cs.c

1759

i = (reg >> 7);

sys/dev/drm/radeon/evergreen_cs.c

1763

m = 1 << ((reg >> 2) & 31);

sys/dev/drm/radeon/evergreen_cs.c

1778

unsigned start_reg, end_reg, reg;

sys/dev/drm/radeon/evergreen_cs.c

2307

for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {

sys/dev/drm/radeon/evergreen_cs.c

2308

if (evergreen_is_safe_reg(p, reg))

sys/dev/drm/radeon/evergreen_cs.c

2310

r = evergreen_cs_handle_reg(p, reg, idx);

sys/dev/drm/radeon/evergreen_cs.c

2324

for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {

sys/dev/drm/radeon/evergreen_cs.c

2325

if (evergreen_is_safe_reg(p, reg))

sys/dev/drm/radeon/evergreen_cs.c

2327

r = evergreen_cs_handle_reg(p, reg, idx);

sys/dev/drm/radeon/evergreen_cs.c

2581

reg = radeon_get_ib_value(p, idx+1) << 2;

sys/dev/drm/radeon/evergreen_cs.c

2582

if (!evergreen_is_safe_reg(p, reg)) {

sys/dev/drm/radeon/evergreen_cs.c

2584

reg, idx + 1);

sys/dev/drm/radeon/evergreen_cs.c

2608

reg = radeon_get_ib_value(p, idx+3) << 2;

sys/dev/drm/radeon/evergreen_cs.c

2609

if (!evergreen_is_safe_reg(p, reg)) {

sys/dev/drm/radeon/evergreen_cs.c

2611

reg, idx + 3);

sys/dev/drm/radeon/evergreen_cs.c

3224

static bool evergreen_vm_reg_valid(u32 reg)

sys/dev/drm/radeon/evergreen_cs.c

3227

if (reg >= 0x28000)

sys/dev/drm/radeon/evergreen_cs.c

3231

switch (reg) {

sys/dev/drm/radeon/evergreen_cs.c

3341

DRM_ERROR("Invalid register 0x%x in CS\n", reg);

sys/dev/drm/radeon/evergreen_cs.c

3351

u32 start_reg, end_reg, reg, i;

sys/dev/drm/radeon/evergreen_cs.c

3407

reg = ib[idx + 5] * 4;

sys/dev/drm/radeon/evergreen_cs.c

3408

if (!evergreen_vm_reg_valid(reg))

sys/dev/drm/radeon/evergreen_cs.c

3414

reg = ib[idx + 3] * 4;

sys/dev/drm/radeon/evergreen_cs.c

3415

if (!evergreen_vm_reg_valid(reg))

sys/dev/drm/radeon/evergreen_cs.c

3429

reg = start_reg + (4 * i);

sys/dev/drm/radeon/evergreen_cs.c

3430

if (!evergreen_vm_reg_valid(reg))

sys/dev/drm/radeon/evergreen_cs.c

3454

reg = start_reg;

sys/dev/drm/radeon/evergreen_cs.c

3455

if (!evergreen_vm_reg_valid(reg)) {

sys/dev/drm/radeon/evergreen_cs.c

3461

reg = start_reg + (4 * i);

sys/dev/drm/radeon/evergreen_cs.c

3462

if (!evergreen_vm_reg_valid(reg)) {

sys/dev/drm/radeon/evergreen_cs.c

3475

reg = start_reg;

sys/dev/drm/radeon/evergreen_cs.c

3476

if (!evergreen_vm_reg_valid(reg)) {

sys/dev/drm/radeon/evergreen_cs.c

3482

reg = start_reg + (4 * i);

sys/dev/drm/radeon/evergreen_cs.c

3483

if (!evergreen_vm_reg_valid(reg)) {

sys/dev/drm/radeon/evergreend.h

1534

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

sys/dev/drm/radeon/evergreend.h

1535

(((reg) >> 2) & 0xFFFF) | \

sys/dev/drm/radeon/ni.c

41

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/ni.c

46

WREG32(TN_SMC_IND_INDEX_0, (reg));

sys/dev/drm/radeon/ni.c

52

void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/ni.c

55

WREG32(TN_SMC_IND_INDEX_0, (reg));

sys/dev/drm/radeon/ni.c

872

u32 reg, u32 *val)

sys/dev/drm/radeon/ni.c

874

switch (reg) {

sys/dev/drm/radeon/ni.c

883

*val = RREG32(reg);

sys/dev/drm/radeon/ni_dma.c

102

u32 reg;

sys/dev/drm/radeon/ni_dma.c

105

reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

107

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

109

WREG32(reg, (ring->wptr << 2) & 0x3fffc);

sys/dev/drm/radeon/ni_dma.c

54

u32 rptr, reg;

sys/dev/drm/radeon/ni_dma.c

60

reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

62

reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

64

rptr = RREG32(reg);

sys/dev/drm/radeon/ni_dma.c

81

u32 reg;

sys/dev/drm/radeon/ni_dma.c

84

reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

86

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

88

return (RREG32(reg) & 0x3fffc) >> 2;

sys/dev/drm/radeon/ni_dpm.c

1687

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

1751

reg = CG_R(0xffff) | CG_L(0);

sys/dev/drm/radeon/ni_dpm.c

1752

table->initialState.levels[0].aT = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1781

reg = MIN_POWER_MASK | MAX_POWER_MASK;

sys/dev/drm/radeon/ni_dpm.c

1782

table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1784

reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;

sys/dev/drm/radeon/ni_dpm.c

1785

table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1806

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

1929

reg = MIN_POWER_MASK | MAX_POWER_MASK;

sys/dev/drm/radeon/ni_dpm.c

1930

table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

1932

reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;

sys/dev/drm/radeon/ni_dpm.c

1933

table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/ni_dpm.c

3145

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

3154

reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);

sys/dev/drm/radeon/ni_dpm.c

3155

reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) |

sys/dev/drm/radeon/ni_dpm.c

3157

WREG32(CG_CAC_CTRL, reg);

sys/dev/drm/radeon/ni_dpm.c

3211

u32 reg;

sys/dev/drm/radeon/ni_dpm.c

3220

reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3223

reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) |

sys/dev/drm/radeon/ni_dpm.c

3226

WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg);

sys/dev/drm/radeon/ni_dpm.c

3228

reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3231

reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) |

sys/dev/drm/radeon/ni_dpm.c

3234

WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg);

sys/dev/drm/radeon/ni_dpm.c

3236

reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3240

reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) |

sys/dev/drm/radeon/ni_dpm.c

3244

WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg);

sys/dev/drm/radeon/ni_dpm.c

3246

reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3250

reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) |

sys/dev/drm/radeon/ni_dpm.c

3254

WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg);

sys/dev/drm/radeon/ni_dpm.c

3256

reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3261

reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) |

sys/dev/drm/radeon/ni_dpm.c

3266

WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg);

sys/dev/drm/radeon/ni_dpm.c

3268

reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3272

reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) |

sys/dev/drm/radeon/ni_dpm.c

3276

WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg);

sys/dev/drm/radeon/ni_dpm.c

3278

reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK |

sys/dev/drm/radeon/ni_dpm.c

3283

reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) |

sys/dev/drm/radeon/ni_dpm.c

3288

WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg);

sys/dev/drm/radeon/ni_dpm.c

3290

reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3293

reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) |

sys/dev/drm/radeon/ni_dpm.c

3296

WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg);

sys/dev/drm/radeon/ni_dpm.c

3298

reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK |

sys/dev/drm/radeon/ni_dpm.c

3303

reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) |

sys/dev/drm/radeon/ni_dpm.c

3308

WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg);

sys/dev/drm/radeon/ni_dpm.c

3310

reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK |

sys/dev/drm/radeon/ni_dpm.c

3315

reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) |

sys/dev/drm/radeon/ni_dpm.c

3320

WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg);

sys/dev/drm/radeon/ni_dpm.c

3322

reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK |

sys/dev/drm/radeon/ni_dpm.c

3327

reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) |

sys/dev/drm/radeon/ni_dpm.c

3332

WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg);

sys/dev/drm/radeon/ni_dpm.c

3334

reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK |

sys/dev/drm/radeon/ni_dpm.c

3336

reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) |

sys/dev/drm/radeon/ni_dpm.c

3338

WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg);

sys/dev/drm/radeon/ni_dpm.c

3340

reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK);

sys/dev/drm/radeon/ni_dpm.c

3341

reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr);

sys/dev/drm/radeon/ni_dpm.c

3342

WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg);

sys/dev/drm/radeon/ni_dpm.c

3344

reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK |

sys/dev/drm/radeon/ni_dpm.c

3348

reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) |

sys/dev/drm/radeon/ni_dpm.c

3352

WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg);

sys/dev/drm/radeon/ni_dpm.c

3354

reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |

sys/dev/drm/radeon/ni_dpm.c

3357

reg |= (VSP(ni_pi->cac_weights->vsp) |

sys/dev/drm/radeon/ni_dpm.c

3360

WREG32(SQ_CAC_THRESHOLD, reg);

sys/dev/drm/radeon/ni_dpm.c

3362

reg = (MCDW_WR_ENABLE |

sys/dev/drm/radeon/ni_dpm.c

3367

WREG32(MC_CG_CONFIG, reg);

sys/dev/drm/radeon/ni_dpm.c

3369

reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) |

sys/dev/drm/radeon/ni_dpm.c

3372

WREG32(MC_CG_DATAPORT, reg);

sys/dev/drm/radeon/nid.h

1148

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

sys/dev/drm/radeon/nid.h

1149

(((reg) >> 2) & 0xFFFF) | \

sys/dev/drm/radeon/r100.c

1272

unsigned reg)

sys/dev/drm/radeon/r100.c

1283

idx, reg);

sys/dev/drm/radeon/r100.c

1296

if (reg == RADEON_SRC_PITCH_OFFSET) {

sys/dev/drm/radeon/r100.c

1380

unsigned reg;

sys/dev/drm/radeon/r100.c

1386

reg = pkt->reg;

sys/dev/drm/radeon/r100.c

1392

if ((reg >> 7) > n) {

sys/dev/drm/radeon/r100.c

1396

if (((reg + (pkt->count << 2)) >> 7) > n) {

sys/dev/drm/radeon/r100.c

1401

j = (reg >> 7);

sys/dev/drm/radeon/r100.c

1402

m = 1 << ((reg >> 2) & 31);

sys/dev/drm/radeon/r100.c

1404

r = check(p, pkt, idx, reg);

sys/dev/drm/radeon/r100.c

1414

reg += 4;

sys/dev/drm/radeon/r100.c

1441

uint32_t header, h_idx, reg;

sys/dev/drm/radeon/r100.c

1452

if (waitreloc.reg != RADEON_WAIT_UNTIL ||

sys/dev/drm/radeon/r100.c

1474

reg = R100_CP_PACKET0_GET_REG(header);

sys/dev/drm/radeon/r100.c

1488

switch (reg) {

sys/dev/drm/radeon/r100.c

1563

unsigned idx, unsigned reg)

sys/dev/drm/radeon/r100.c

1579

switch (reg) {

sys/dev/drm/radeon/r100.c

1584

idx, reg);

sys/dev/drm/radeon/r100.c

1593

r = r100_reloc_pitch_offset(p, pkt, idx, reg);

sys/dev/drm/radeon/r100.c

1601

idx, reg);

sys/dev/drm/radeon/r100.c

1614

idx, reg);

sys/dev/drm/radeon/r100.c

1626

i = (reg - RADEON_PP_TXOFFSET_0) / 24;

sys/dev/drm/radeon/r100.c

1630

idx, reg);

sys/dev/drm/radeon/r100.c

1653

i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;

sys/dev/drm/radeon/r100.c

1657

idx, reg);

sys/dev/drm/radeon/r100.c

1671

i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;

sys/dev/drm/radeon/r100.c

1675

idx, reg);

sys/dev/drm/radeon/r100.c

1689

i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;

sys/dev/drm/radeon/r100.c

1693

idx, reg);

sys/dev/drm/radeon/r100.c

1711

idx, reg);

sys/dev/drm/radeon/r100.c

1782

idx, reg);

sys/dev/drm/radeon/r100.c

1805

i = (reg - RADEON_PP_TEX_SIZE_0) / 8;

sys/dev/drm/radeon/r100.c

1813

i = (reg - RADEON_PP_TEX_PITCH_0) / 8;

sys/dev/drm/radeon/r100.c

1820

i = (reg - RADEON_PP_TXFILTER_0) / 24;

sys/dev/drm/radeon/r100.c

1834

i = (reg - RADEON_PP_TXFORMAT_0) / 24;

sys/dev/drm/radeon/r100.c

1888

i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;

sys/dev/drm/radeon/r100.c

1896

pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);

sys/dev/drm/radeon/r100.c

2890

uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/r100.c

2896

WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);

sys/dev/drm/radeon/r100.c

2904

void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/r100.c

2909

WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));

sys/dev/drm/radeon/r100.c

2938

uint32_t reg, value;

sys/dev/drm/radeon/r100.c

2946

reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;

sys/dev/drm/radeon/r100.c

2949

seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);

sys/dev/drm/radeon/r100.c

3103

int r100_set_surface_reg(struct radeon_device *rdev, int reg,

sys/dev/drm/radeon/r100.c

3107

int surf_index = reg * 16;

sys/dev/drm/radeon/r100.c

3144

DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);

sys/dev/drm/radeon/r100.c

3151

void r100_clear_surface_reg(struct radeon_device *rdev, int reg)

sys/dev/drm/radeon/r100.c

3153

int surf_index = reg * 16;

sys/dev/drm/radeon/r100.c

354

tmp = RREG32(voltage->gpio.reg);

sys/dev/drm/radeon/r100.c

359

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/r100.c

363

tmp = RREG32(voltage->gpio.reg);

sys/dev/drm/radeon/r100.c

368

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/r100.c

4125

uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/r100.c

4131

writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);

sys/dev/drm/radeon/r100.c

4137

void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/r100.c

4142

writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);

sys/dev/drm/radeon/r100.c

4147

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r100.c

4149

if (reg < rdev->rio_mem_size)

sys/dev/drm/radeon/r100.c

4150

return ioread32(rdev->rio_mem + reg);

sys/dev/drm/radeon/r100.c

4152

iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);

sys/dev/drm/radeon/r100.c

4157

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r100.c

4159

if (reg < rdev->rio_mem_size)

sys/dev/drm/radeon/r100.c

4160

iowrite32(v, rdev->rio_mem + reg);

sys/dev/drm/radeon/r100.c

4162

iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);

sys/dev/drm/radeon/r100_track.h

89

unsigned idx, unsigned reg);

sys/dev/drm/radeon/r100_track.h

94

unsigned reg);

sys/dev/drm/radeon/r100d.h

59

#define PACKET0(reg, n) (CP_PACKET0 | \

sys/dev/drm/radeon/r100d.h

60

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

sys/dev/drm/radeon/r200.c

147

unsigned idx, unsigned reg)

sys/dev/drm/radeon/r200.c

162

switch (reg) {

sys/dev/drm/radeon/r200.c

167

idx, reg);

sys/dev/drm/radeon/r200.c

176

r = r100_reloc_pitch_offset(p, pkt, idx, reg);

sys/dev/drm/radeon/r200.c

184

idx, reg);

sys/dev/drm/radeon/r200.c

197

idx, reg);

sys/dev/drm/radeon/r200.c

212

i = (reg - R200_PP_TXOFFSET_0) / 24;

sys/dev/drm/radeon/r200.c

216

idx, reg);

sys/dev/drm/radeon/r200.c

264

i = (reg - R200_PP_TXOFFSET_0) / 24;

sys/dev/drm/radeon/r200.c

265

face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;

sys/dev/drm/radeon/r200.c

269

idx, reg);

sys/dev/drm/radeon/r200.c

287

idx, reg);

sys/dev/drm/radeon/r200.c

364

idx, reg);

sys/dev/drm/radeon/r200.c

397

i = (reg - R200_PP_TXSIZE_0) / 32;

sys/dev/drm/radeon/r200.c

408

i = (reg - R200_PP_TXPITCH_0) / 32;

sys/dev/drm/radeon/r200.c

418

i = (reg - R200_PP_TXFILTER_0) / 32;

sys/dev/drm/radeon/r200.c

435

i = (reg - R200_PP_TXMULTI_CTL_0) / 32;

sys/dev/drm/radeon/r200.c

443

i = (reg - R200_PP_TXFORMAT_X_0) / 32;

sys/dev/drm/radeon/r200.c

474

i = (reg - R200_PP_TXFORMAT_0) / 32;

sys/dev/drm/radeon/r200.c

532

i = (reg - R200_PP_CUBIC_FACES_0) / 32;

sys/dev/drm/radeon/r200.c

540

pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);

sys/dev/drm/radeon/r300.c

1022

i = (reg - 0x4500) >> 2;

sys/dev/drm/radeon/r300.c

1060

i = (reg - 0x4480) >> 2;

sys/dev/drm/radeon/r300.c

1077

idx, reg);

sys/dev/drm/radeon/r300.c

1119

idx, reg);

sys/dev/drm/radeon/r300.c

1162

reg, idx, idx_value);

sys/dev/drm/radeon/r300.c

54

uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/r300.c

59

WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));

sys/dev/drm/radeon/r300.c

623

unsigned idx, unsigned reg)

sys/dev/drm/radeon/r300.c

637

switch(reg) {

sys/dev/drm/radeon/r300.c

643

idx, reg);

sys/dev/drm/radeon/r300.c

65

void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/r300.c

650

r = r100_reloc_pitch_offset(p, pkt, idx, reg);

sys/dev/drm/radeon/r300.c

658

i = (reg - R300_RB3D_COLOROFFSET0) >> 2;

sys/dev/drm/radeon/r300.c

662

idx, reg);

sys/dev/drm/radeon/r300.c

675

idx, reg);

sys/dev/drm/radeon/r300.c

68

WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));

sys/dev/drm/radeon/r300.c

700

i = (reg - R300_TX_OFFSET_0) >> 2;

sys/dev/drm/radeon/r300.c

704

idx, reg);

sys/dev/drm/radeon/r300.c

777

idx, reg);

sys/dev/drm/radeon/r300.c

793

i = (reg - 0x4E38) >> 2;

sys/dev/drm/radeon/r300.c

862

idx, reg);

sys/dev/drm/radeon/r300.c

908

i = (reg - 0x44C0) >> 2;

sys/dev/drm/radeon/r300.c

994

i = (reg - 0x4400) >> 2;

sys/dev/drm/radeon/r300d.h

60

#define PACKET0(reg, n) (CP_PACKET0 | \

sys/dev/drm/radeon/r300d.h

61

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

sys/dev/drm/radeon/r420.c

158

u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r420.c

164

WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));

sys/dev/drm/radeon/r420.c

170

void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r420.c

175

WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/r600.c

110

u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r600.c

116

WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));

sys/dev/drm/radeon/r600.c

122

void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r600.c

1268

uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/r600.c

127

WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));

sys/dev/drm/radeon/r600.c

1274

WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));

sys/dev/drm/radeon/r600.c

1281

void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/r600.c

1286

WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/r600.c

132

u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r600.c

138

WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/radeon/r600.c

144

void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r600.c

149

WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/radeon/r600.c

165

u32 reg, u32 *val)

sys/dev/drm/radeon/r600.c

167

switch (reg) {

sys/dev/drm/radeon/r600.c

173

*val = RREG32(reg);

sys/dev/drm/radeon/r600.c

2386

u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)

sys/dev/drm/radeon/r600.c

2392

WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));

sys/dev/drm/radeon/r600.c

2399

void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)

sys/dev/drm/radeon/r600.c

2404

WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));

sys/dev/drm/radeon/r600.c

2828

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

sys/dev/drm/radeon/r600.c

3037

int r600_set_surface_reg(struct radeon_device *rdev, int reg,

sys/dev/drm/radeon/r600.c

3045

void r600_clear_surface_reg(struct radeon_device *rdev, int reg)

sys/dev/drm/radeon/r600_cs.c

1020

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1038

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1080

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1083

tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;

sys/dev/drm/radeon/r600_cs.c

1094

tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;

sys/dev/drm/radeon/r600_cs.c

1103

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1138

dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1141

tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;

sys/dev/drm/radeon/r600_cs.c

1151

tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;

sys/dev/drm/radeon/r600_cs.c

1164

tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;

sys/dev/drm/radeon/r600_cs.c

1176

tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;

sys/dev/drm/radeon/r600_cs.c

1198

tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;

sys/dev/drm/radeon/r600_cs.c

1201

dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1210

dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1229

tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;

sys/dev/drm/radeon/r600_cs.c

1232

dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1241

dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1260

tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;

sys/dev/drm/radeon/r600_cs.c

1277

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1280

tmp = (reg - CB_COLOR0_BASE) / 4;

sys/dev/drm/radeon/r600_cs.c

1292

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1305

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1375

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1384

"0x%04X\n", reg);

sys/dev/drm/radeon/r600_cs.c

1393

dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

sys/dev/drm/radeon/r600_cs.c

1610

static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/drm/radeon/r600_cs.c

1614

i = (reg >> 7);

sys/dev/drm/radeon/r600_cs.c

1616

dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

sys/dev/drm/radeon/r600_cs.c

1619

m = 1 << ((reg >> 2) & 31);

sys/dev/drm/radeon/r600_cs.c

1622

dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

sys/dev/drm/radeon/r600_cs.c

1634

unsigned start_reg, end_reg, reg;

sys/dev/drm/radeon/r600_cs.c

1918

reg = start_reg + (4 * i);

sys/dev/drm/radeon/r600_cs.c

1919

r = r600_cs_check_reg(p, reg, idx+1+i);

sys/dev/drm/radeon/r600_cs.c

1934

reg = start_reg + (4 * i);

sys/dev/drm/radeon/r600_cs.c

1935

r = r600_cs_check_reg(p, reg, idx+1+i);

sys/dev/drm/radeon/r600_cs.c

2230

reg = radeon_get_ib_value(p, idx+1) << 2;

sys/dev/drm/radeon/r600_cs.c

2231

if (!r600_is_safe_reg(p, reg, idx+1))

sys/dev/drm/radeon/r600_cs.c

2254

reg = radeon_get_ib_value(p, idx+3) << 2;

sys/dev/drm/radeon/r600_cs.c

2255

if (!r600_is_safe_reg(p, reg, idx+3))

sys/dev/drm/radeon/r600_cs.c

834

uint32_t header, h_idx, reg, wait_reg_mem_info;

sys/dev/drm/radeon/r600_cs.c

888

reg = R600_CP_PACKET0_GET_REG(header);

sys/dev/drm/radeon/r600_cs.c

907

} else if (reg == vline_start_end[0]) {

sys/dev/drm/radeon/r600_cs.c

921

unsigned idx, unsigned reg)

sys/dev/drm/radeon/r600_cs.c

925

switch (reg) {

sys/dev/drm/radeon/r600_cs.c

930

idx, reg);

sys/dev/drm/radeon/r600_cs.c

935

pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);

sys/dev/drm/radeon/r600_cs.c

944

unsigned reg, i;

sys/dev/drm/radeon/r600_cs.c

949

reg = pkt->reg;

sys/dev/drm/radeon/r600_cs.c

950

for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {

sys/dev/drm/radeon/r600_cs.c

951

r = r600_packet0_check(p, pkt, idx, reg);

sys/dev/drm/radeon/r600_cs.c

969

static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

sys/dev/drm/radeon/r600_cs.c

976

i = (reg >> 7);

sys/dev/drm/radeon/r600_cs.c

978

dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

sys/dev/drm/radeon/r600_cs.c

981

m = 1 << ((reg >> 2) & 31);

sys/dev/drm/radeon/r600_cs.c

985

switch (reg) {

sys/dev/drm/radeon/r600d.h

1584

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

sys/dev/drm/radeon/r600d.h

1585

(((reg) >> 2) & 0xFFFF) | \

sys/dev/drm/radeon/radeon.h

1111

unsigned reg;

sys/dev/drm/radeon/radeon.h

1119

unsigned idx, unsigned reg);

sys/dev/drm/radeon/radeon.h

1870

int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);

sys/dev/drm/radeon/radeon.h

1945

int (*set_reg)(struct radeon_device *rdev, int reg,

sys/dev/drm/radeon/radeon.h

1948

void (*clear_reg)(struct radeon_device *rdev, int reg);

sys/dev/drm/radeon/radeon.h

2488

uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon.h

2489

void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon.h

2490

static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,

sys/dev/drm/radeon/radeon.h

2494

if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)

sys/dev/drm/radeon/radeon.h

2495

return readl(((void __iomem *)rdev->rmmio) + reg);

sys/dev/drm/radeon/radeon.h

2497

return r100_mm_rreg_slow(rdev, reg);

sys/dev/drm/radeon/radeon.h

2499

static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,

sys/dev/drm/radeon/radeon.h

2502

if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)

sys/dev/drm/radeon/radeon.h

2503

writel(v, ((void __iomem *)rdev->rmmio) + reg);

sys/dev/drm/radeon/radeon.h

2505

r100_mm_wreg_slow(rdev, reg, v);

sys/dev/drm/radeon/radeon.h

2508

u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2509

void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2532

#define RREG8(reg) readb((rdev->rmmio) + (reg))

sys/dev/drm/radeon/radeon.h

2533

#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))

sys/dev/drm/radeon/radeon.h

2534

#define RREG16(reg) readw((rdev->rmmio) + (reg))

sys/dev/drm/radeon/radeon.h

2535

#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))

sys/dev/drm/radeon/radeon.h

2536

#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

sys/dev/drm/radeon/radeon.h

2537

#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)

sys/dev/drm/radeon/radeon.h

2538

#define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))

sys/dev/drm/radeon/radeon.h

2539

#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)

sys/dev/drm/radeon/radeon.h

2540

#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)

sys/dev/drm/radeon/radeon.h

2543

#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2544

#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2545

#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2546

#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2547

#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2548

#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2549

#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2550

#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2551

#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2552

#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2553

#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2554

#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2555

#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2556

#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2557

#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2558

#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2559

#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2560

#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2561

#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2562

#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2563

#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2564

#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2565

#define WREG32_P(reg, val, mask) \

sys/dev/drm/radeon/radeon.h

2567

uint32_t tmp_ = RREG32(reg); \

sys/dev/drm/radeon/radeon.h

2570

WREG32(reg, tmp_); \

sys/dev/drm/radeon/radeon.h

2572

#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)

sys/dev/drm/radeon/radeon.h

2573

#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))

sys/dev/drm/radeon/radeon.h

2574

#define WREG32_PLL_P(reg, val, mask) \

sys/dev/drm/radeon/radeon.h

2576

uint32_t tmp_ = RREG32_PLL(reg); \

sys/dev/drm/radeon/radeon.h

2579

WREG32_PLL(reg, tmp_); \

sys/dev/drm/radeon/radeon.h

2581

#define WREG32_SMC_P(reg, val, mask) \

sys/dev/drm/radeon/radeon.h

2583

uint32_t tmp_ = RREG32_SMC(reg); \

sys/dev/drm/radeon/radeon.h

2586

WREG32_SMC(reg, tmp_); \

sys/dev/drm/radeon/radeon.h

2588

#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))

sys/dev/drm/radeon/radeon.h

2589

#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))

sys/dev/drm/radeon/radeon.h

2590

#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))

sys/dev/drm/radeon/radeon.h

2603

uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon.h

2604

void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon.h

2605

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2606

void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2607

u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2608

void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2609

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2610

void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2611

u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2612

void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2613

u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2614

void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2615

u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2616

void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

2617

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon.h

2618

void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon.h

3007

u32 reg, u32 mask,

sys/dev/drm/radeon/radeon.h

717

uint32_t reg[32];

sys/dev/drm/radeon/radeon.h

720

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);

sys/dev/drm/radeon/radeon.h

721

void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.c

141

u32 reg, u32 *val)

sys/dev/drm/radeon/radeon_asic.c

54

static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/radeon_asic.c

56

DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);

sys/dev/drm/radeon/radeon_asic.c

71

static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/radeon_asic.c

74

reg, v);

sys/dev/drm/radeon/radeon_asic.h

199

extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);

sys/dev/drm/radeon/radeon_asic.h

200

extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_asic.h

215

uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

216

void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

240

uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

241

void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

265

uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

266

void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

284

uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

285

void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

317

uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

318

void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

340

int r600_set_surface_reg(struct radeon_device *rdev, int reg,

sys/dev/drm/radeon/radeon_asic.h

343

void r600_clear_surface_reg(struct radeon_device *rdev, int reg);

sys/dev/drm/radeon/radeon_asic.h

367

extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

368

extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

390

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

570

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

676

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

786

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

827

uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

828

void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

83

void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/drm/radeon/radeon_asic.h

84

uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/drm/radeon/radeon_asic.h

90

int r100_set_surface_reg(struct radeon_device *rdev, int reg,

sys/dev/drm/radeon/radeon_asic.h

927

u32 reg, u32 *val);

sys/dev/drm/radeon/radeon_asic.h

93

void r100_clear_surface_reg(struct radeon_device *rdev, int reg);

sys/dev/drm/radeon/radeon_atombios.c

215

gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;

sys/dev/drm/radeon/radeon_atombios.c

233

u32 reg;

sys/dev/drm/radeon/radeon_atombios.c

238

reg = SI_DC_GPIO_HPD_A;

sys/dev/drm/radeon/radeon_atombios.c

240

reg = EVERGREEN_DC_GPIO_HPD_A;

sys/dev/drm/radeon/radeon_atombios.c

242

reg = AVIVO_DC_GPIO_HPD_A;

sys/dev/drm/radeon/radeon_atombios.c

245

if (gpio->reg == reg) {

sys/dev/drm/radeon/radeon_audio.c

123

static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)

sys/dev/drm/radeon/radeon_audio.c

125

return RREG32(reg);

sys/dev/drm/radeon/radeon_audio.c

129

u32 reg, u32 v)

sys/dev/drm/radeon/radeon_audio.c

131

WREG32(reg, v);

sys/dev/drm/radeon/radeon_audio.c

350

u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)

sys/dev/drm/radeon/radeon_audio.c

353

return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg);

sys/dev/drm/radeon/radeon_audio.c

359

u32 reg, u32 v)

sys/dev/drm/radeon/radeon_audio.c

362

rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);

sys/dev/drm/radeon/radeon_audio.c

42

u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);

sys/dev/drm/radeon/radeon_audio.c

44

u32 offset, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_audio.h

30

#define RREG32_ENDPOINT(block, reg) \

sys/dev/drm/radeon/radeon_audio.h

31

radeon_audio_endpoint_rreg(rdev, (block), (reg))

sys/dev/drm/radeon/radeon_audio.h

32

#define WREG32_ENDPOINT(block, reg, v) \

sys/dev/drm/radeon/radeon_audio.h

33

radeon_audio_endpoint_wreg(rdev, (block), (reg), (v))

sys/dev/drm/radeon/radeon_audio.h

37

u32 (*endpoint_rreg)(struct radeon_device *rdev, u32 offset, u32 reg);

sys/dev/drm/radeon/radeon_audio.h

39

u32 offset, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_audio.h

74

u32 offset, u32 reg);

sys/dev/drm/radeon/radeon_audio.h

76

u32 offset, u32 reg, u32 v);

sys/dev/drm/radeon/radeon_combios.c

2749

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =

sys/dev/drm/radeon/radeon_combios.c

2757

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =

sys/dev/drm/radeon/radeon_combios.c

2882

uint32_t reg, val, and_mask, or_mask;

sys/dev/drm/radeon/radeon_combios.c

2901

reg = (id & 0x1fff) * 4;

sys/dev/drm/radeon/radeon_combios.c

2904

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2907

reg = (id & 0x1fff) * 4;

sys/dev/drm/radeon/radeon_combios.c

2912

val = RREG32(reg);

sys/dev/drm/radeon/radeon_combios.c

2914

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2930

reg = RBIOS8(index);

sys/dev/drm/radeon/radeon_combios.c

2936

reg, val);

sys/dev/drm/radeon/radeon_combios.c

2956

reg = (id & 0x1fff) * 4;

sys/dev/drm/radeon/radeon_combios.c

2958

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2961

reg = (id & 0x1fff) * 4;

sys/dev/drm/radeon/radeon_combios.c

2966

val = RREG32(reg);

sys/dev/drm/radeon/radeon_combios.c

2968

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2976

reg = id & 0x1fff;

sys/dev/drm/radeon/radeon_combios.c

2981

val = RREG32_PLL(reg);

sys/dev/drm/radeon/radeon_combios.c

2983

WREG32_PLL(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2986

reg = id & 0x1fff;

sys/dev/drm/radeon/radeon_combios.c

2991

reg, val);

sys/dev/drm/radeon/radeon_cs.c

751

pkt->reg = R100_CP_PACKET0_GET_REG(header);

sys/dev/drm/radeon/radeon_cs.c

755

pkt->reg = R600_CP_PACKET0_GET_REG(header);

sys/dev/drm/radeon/radeon_cursor.c

73

u32 reg;

sys/dev/drm/radeon/radeon_cursor.c

76

reg = RADEON_CRTC_GEN_CNTL;

sys/dev/drm/radeon/radeon_cursor.c

79

reg = RADEON_CRTC2_GEN_CNTL;

sys/dev/drm/radeon/radeon_cursor.c

84

WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);

sys/dev/drm/radeon/radeon_device.c

198

u32 tmp, reg, and_mask, or_mask;

sys/dev/drm/radeon/radeon_device.c

205

reg = registers[i + 0];

sys/dev/drm/radeon/radeon_device.c

212

tmp = RREG32(reg);

sys/dev/drm/radeon/radeon_device.c

216

WREG32(reg, tmp);

sys/dev/drm/radeon/radeon_device.c

272

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

sys/dev/drm/radeon/radeon_device.c

285

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)

sys/dev/drm/radeon/radeon_device.c

292

*reg = rdev->scratch.reg[i];

sys/dev/drm/radeon/radeon_device.c

307

void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/radeon_device.c

312

if (rdev->scratch.reg[i] == reg) {

sys/dev/drm/radeon/radeon_device.c

653

uint32_t reg;

sys/dev/drm/radeon/radeon_device.c

673

reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_device.c

676

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_device.c

680

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

sys/dev/drm/radeon/radeon_device.c

683

if (reg & EVERGREEN_CRTC_MASTER_EN)

sys/dev/drm/radeon/radeon_device.c

686

reg = RREG32(AVIVO_D1CRTC_CONTROL) |

sys/dev/drm/radeon/radeon_device.c

688

if (reg & AVIVO_CRTC_EN) {

sys/dev/drm/radeon/radeon_device.c

692

reg = RREG32(RADEON_CRTC_GEN_CNTL) |

sys/dev/drm/radeon/radeon_device.c

694

if (reg & RADEON_CRTC_EN) {

sys/dev/drm/radeon/radeon_device.c

702

reg = RREG32(R600_CONFIG_MEMSIZE);

sys/dev/drm/radeon/radeon_device.c

704

reg = RREG32(RADEON_CONFIG_MEMSIZE);

sys/dev/drm/radeon/radeon_device.c

706

if (reg)

sys/dev/drm/radeon/radeon_device.c

824

static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)

sys/dev/drm/radeon/radeon_device.c

829

r = rdev->pll_rreg(rdev, reg);

sys/dev/drm/radeon/radeon_device.c

842

static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/radeon/radeon_device.c

846

rdev->pll_wreg(rdev, reg, val);

sys/dev/drm/radeon/radeon_device.c

858

static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)

sys/dev/drm/radeon/radeon_device.c

863

r = rdev->mc_rreg(rdev, reg);

sys/dev/drm/radeon/radeon_device.c

876

static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/radeon/radeon_device.c

880

rdev->mc_wreg(rdev, reg, val);

sys/dev/drm/radeon/radeon_device.c

892

static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/radeon/radeon_device.c

896

WREG32(reg*4, val);

sys/dev/drm/radeon/radeon_device.c

908

static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)

sys/dev/drm/radeon/radeon_device.c

913

r = RREG32(reg*4);

sys/dev/drm/radeon/radeon_device.c

926

static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/drm/radeon/radeon_device.c

930

WREG32_IO(reg*4, val);

sys/dev/drm/radeon/radeon_device.c

942

static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)

sys/dev/drm/radeon/radeon_device.c

947

r = RREG32_IO(reg*4);

sys/dev/drm/radeon/radeon_dp_mst.c

31

uint32_t reg;

sys/dev/drm/radeon/radeon_dp_mst.c

35

reg = RREG32(NI_DIG_BE_CNTL + primary->offset);

sys/dev/drm/radeon/radeon_dp_mst.c

38

reg &= ~NI_DIG_FE_DIG_MODE(7);

sys/dev/drm/radeon/radeon_dp_mst.c

39

reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);

sys/dev/drm/radeon/radeon_dp_mst.c

42

reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);

sys/dev/drm/radeon/radeon_dp_mst.c

44

reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);

sys/dev/drm/radeon/radeon_dp_mst.c

46

reg |= NI_DIG_HPD_SELECT(hpd);

sys/dev/drm/radeon/radeon_dp_mst.c

47

DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);

sys/dev/drm/radeon/radeon_dp_mst.c

48

WREG32(NI_DIG_BE_CNTL + primary->offset, reg);

sys/dev/drm/radeon/radeon_i2c.c

105

u32 reg;

sys/dev/drm/radeon/radeon_i2c.c

108

reg = RADEON_GPIO_MONID;

sys/dev/drm/radeon/radeon_i2c.c

111

reg = RADEON_GPIO_DVI_DDC;

sys/dev/drm/radeon/radeon_i2c.c

113

reg = RADEON_GPIO_CRT2_DDC;

sys/dev/drm/radeon/radeon_i2c.c

116

if (rec->a_clk_reg == reg) {

sys/dev/drm/radeon/radeon_i2c.c

336

u32 tmp, reg;

sys/dev/drm/radeon/radeon_i2c.c

344

reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |

sys/dev/drm/radeon/radeon_i2c.c

385

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

sys/dev/drm/radeon/radeon_i2c.c

388

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

sys/dev/drm/radeon/radeon_i2c.c

401

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

sys/dev/drm/radeon/radeon_i2c.c

404

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);

sys/dev/drm/radeon/radeon_i2c.c

407

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

sys/dev/drm/radeon/radeon_i2c.c

420

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

sys/dev/drm/radeon/radeon_i2c.c

423

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

sys/dev/drm/radeon/radeon_i2c.c

441

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);

sys/dev/drm/radeon/radeon_i2c.c

444

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);

sys/dev/drm/radeon/radeon_i2c.c

447

reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);

sys/dev/drm/radeon/radeon_i2c.c

476

WREG32(i2c_cntl_0, reg);

sys/dev/drm/radeon/radeon_i2c.c

508

WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);

sys/dev/drm/radeon/radeon_i2c.c

536

WREG32(i2c_cntl_0, reg);

sys/dev/drm/radeon/radeon_i2c.c

588

u32 tmp, reg;

sys/dev/drm/radeon/radeon_i2c.c

649

reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;

sys/dev/drm/radeon/radeon_i2c.c

652

reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);

sys/dev/drm/radeon/radeon_i2c.c

655

reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);

sys/dev/drm/radeon/radeon_i2c.c

658

reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);

sys/dev/drm/radeon/radeon_i2c.c

683

WREG32(AVIVO_DC_I2C_CONTROL1, reg);

sys/dev/drm/radeon/radeon_i2c.c

725

WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);

sys/dev/drm/radeon/radeon_i2c.c

768

WREG32(AVIVO_DC_I2C_CONTROL1, reg);

sys/dev/drm/radeon/radeon_irq_kms.c

571

u32 reg, u32 mask,

sys/dev/drm/radeon/radeon_irq_kms.c

574

u32 tmp = RREG32(reg);

sys/dev/drm/radeon/radeon_irq_kms.c

582

WREG32(reg, tmp |= mask);

sys/dev/drm/radeon/radeon_irq_kms.c

585

WREG32(reg, tmp & ~mask);

sys/dev/drm/radeon/radeon_mode.h

501

u32 reg;

sys/dev/drm/radeon/radeon_object.c

604

struct radeon_surface_reg *reg;

sys/dev/drm/radeon/radeon_object.c

615

reg = &rdev->surface_regs[bo->surface_reg];

sys/dev/drm/radeon/radeon_object.c

623

reg = &rdev->surface_regs[i];

sys/dev/drm/radeon/radeon_object.c

624

if (!reg->bo)

sys/dev/drm/radeon/radeon_object.c

627

old_object = reg->bo;

sys/dev/drm/radeon/radeon_object.c

637

reg = &rdev->surface_regs[steal];

sys/dev/drm/radeon/radeon_object.c

638

old_object = reg->bo;

sys/dev/drm/radeon/radeon_object.c

647

reg->bo = bo;

sys/dev/drm/radeon/radeon_object.c

659

struct radeon_surface_reg *reg;

sys/dev/drm/radeon/radeon_object.c

664

reg = &rdev->surface_regs[bo->surface_reg];

sys/dev/drm/radeon/radeon_object.c

667

reg->bo = NULL;

sys/dev/drm/radeon/radeon_uvd.c

658

switch (pkt->reg + i*4) {

sys/dev/drm/radeon/radeon_uvd.c

676

pkt->reg + i*4);

sys/dev/drm/radeon/rs400.c

278

uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/rs400.c

283

WREG32(RS480_NB_MC_INDEX, reg & 0xff);

sys/dev/drm/radeon/rs400.c

290

void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/rs400.c

293

WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);

sys/dev/drm/radeon/rs600.c

226

tmp = RREG32(voltage->gpio.reg);

sys/dev/drm/radeon/rs600.c

231

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/rs600.c

235

tmp = RREG32(voltage->gpio.reg);

sys/dev/drm/radeon/rs600.c

240

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/rs600.c

918

uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/rs600.c

923

WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/rs600.c

930

void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/rs600.c

933

WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/rs690.c

650

uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/rs690.c

655

WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));

sys/dev/drm/radeon/rs690.c

662

void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/rs690.c

665

WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/rv515.c

206

uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/drm/radeon/rv515.c

212

WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));

sys/dev/drm/radeon/rv515.c

220

void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/drm/radeon/rv515.c

225

WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));

sys/dev/drm/radeon/rv515d.h

200

#define PACKET0(reg, n) (CP_PACKET0 | \

sys/dev/drm/radeon/rv515d.h

201

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

sys/dev/drm/radeon/rv770d.h

985

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

sys/dev/drm/radeon/rv770d.h

986

(((reg) >> 2) & 0xFFFF) | \

sys/dev/drm/radeon/si.c

1299

u32 reg, u32 *val)

sys/dev/drm/radeon/si.c

1301

switch (reg) {

sys/dev/drm/radeon/si.c

1311

*val = RREG32(reg);

sys/dev/drm/radeon/si.c

3356

rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);

sys/dev/drm/radeon/si.c

4364

uint32_t reg;

sys/dev/drm/radeon/si.c

4366

reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);

sys/dev/drm/radeon/si.c

4368

reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);

sys/dev/drm/radeon/si.c

4369

rdev->vm_manager.saved_table_addr[i] = RREG32(reg);

sys/dev/drm/radeon/si.c

4397

static bool si_vm_reg_valid(u32 reg)

sys/dev/drm/radeon/si.c

4400

if (reg >= 0x28000)

sys/dev/drm/radeon/si.c

4404

if (reg >= 0xB000 && reg < 0xC000)

sys/dev/drm/radeon/si.c

4408

switch (reg) {

sys/dev/drm/radeon/si.c

4438

DRM_ERROR("Invalid register 0x%x in CS\n", reg);

sys/dev/drm/radeon/si.c

4467

u32 start_reg, reg, i;

sys/dev/drm/radeon/si.c

4476

reg = start_reg;

sys/dev/drm/radeon/si.c

4477

if (!si_vm_reg_valid(reg)) {

sys/dev/drm/radeon/si.c

4483

reg = start_reg + (4 * i);

sys/dev/drm/radeon/si.c

4484

if (!si_vm_reg_valid(reg)) {

sys/dev/drm/radeon/si.c

4497

reg = start_reg;

sys/dev/drm/radeon/si.c

4498

if (!si_vm_reg_valid(reg)) {

sys/dev/drm/radeon/si.c

4504

reg = start_reg + (4 * i);

sys/dev/drm/radeon/si.c

4505

if (!si_vm_reg_valid(reg)) {

sys/dev/drm/radeon/si.c

4522

u32 start_reg, end_reg, reg, i;

sys/dev/drm/radeon/si.c

4573

reg = ib[idx + 3] * 4;

sys/dev/drm/radeon/si.c

4574

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4586

reg = start_reg + (4 * i);

sys/dev/drm/radeon/si.c

4587

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4595

reg = ib[idx + 5] * 4;

sys/dev/drm/radeon/si.c

4596

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4602

reg = ib[idx + 3] * 4;

sys/dev/drm/radeon/si.c

4603

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4617

reg = start_reg + (4 * i);

sys/dev/drm/radeon/si.c

4618

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4640

u32 start_reg, reg, i;

sys/dev/drm/radeon/si.c

4676

reg = ib[idx + 3] * 4;

sys/dev/drm/radeon/si.c

4677

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4689

reg = start_reg + (4 * i);

sys/dev/drm/radeon/si.c

4690

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4698

reg = ib[idx + 5] * 4;

sys/dev/drm/radeon/si.c

4699

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si.c

4705

reg = ib[idx + 3] * 4;

sys/dev/drm/radeon/si.c

4706

if (!si_vm_reg_valid(reg))

sys/dev/drm/radeon/si_dpm.c

2660

u32 load_line_slope, reg;

sys/dev/drm/radeon/si_dpm.c

2671

reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;

sys/dev/drm/radeon/si_dpm.c

2672

reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);

sys/dev/drm/radeon/si_dpm.c

2673

WREG32(CG_CAC_CTRL, reg);

sys/dev/drm/radeon/si_dpm.c

4376

u32 reg;

sys/dev/drm/radeon/si_dpm.c

4454

reg = CG_R(0xffff) | CG_L(0);

sys/dev/drm/radeon/si_dpm.c

4455

table->initialState.levels[0].aT = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4482

reg = MIN_POWER_MASK | MAX_POWER_MASK;

sys/dev/drm/radeon/si_dpm.c

4483

table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4485

reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;

sys/dev/drm/radeon/si_dpm.c

4486

table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4508

u32 reg;

sys/dev/drm/radeon/si_dpm.c

4623

reg = MIN_POWER_MASK | MAX_POWER_MASK;

sys/dev/drm/radeon/si_dpm.c

4624

table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);

sys/dev/drm/radeon/si_dpm.c

4626

reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;

sys/dev/drm/radeon/si_dpm.c

4627

table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);

sys/dev/drm/radeon/sid.h

1586

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

sys/dev/drm/radeon/sid.h

1587

(((reg) >> 2) & 0xFFFF) | \

sys/dev/misc/amdsbwd/amdsbwd.c

130

pmio_read(struct resource *res, uint8_t reg)

sys/dev/misc/amdsbwd/amdsbwd.c

132

bus_write_1(res, 0, reg); /* Index */

sys/dev/misc/amdsbwd/amdsbwd.c

137

pmio_write(struct resource *res, uint8_t reg, uint8_t val)

sys/dev/misc/amdsbwd/amdsbwd.c

139

bus_write_1(res, 0, reg); /* Index */

sys/dev/misc/coremctl/coremctl.c

362

coremctl_mch_readreg(device_t dev, int reg, uint32_t *val)

sys/dev/misc/coremctl/coremctl.c

369

*val = CSR_READ_4(sc, reg);

sys/dev/misc/coremctl/coremctl.c

374

coremctl_mch_writereg(device_t dev, int reg, uint32_t val)

sys/dev/misc/coremctl/coremctl.c

381

CSR_WRITE_4(sc, reg, val);

sys/dev/misc/coremctl/coremctl.c

393

coremctl_pci_read_config(device_t dev, device_t child, int reg, int width)

sys/dev/misc/coremctl/coremctl.c

395

return pci_read_config(dev, reg, width);

sys/dev/misc/coremctl/coremctl.c

399

coremctl_pci_write_config(device_t dev, device_t child, int reg, uint32_t val,

sys/dev/misc/coremctl/coremctl.c

402

pci_write_config(dev, reg, val, width);

sys/dev/misc/cpuctl/cpuctl.c

180

uint64_t reg;

sys/dev/misc/cpuctl/cpuctl.c

202

ret = rdmsr_safe(data->msr, &reg);

sys/dev/misc/cpuctl/cpuctl.c

204

ret = wrmsr_safe(data->msr, reg | data->data);

sys/dev/misc/cpuctl/cpuctl.c

208

ret = rdmsr_safe(data->msr, &reg);

sys/dev/misc/cpuctl/cpuctl.c

210

ret = wrmsr_safe(data->msr, reg & ~data->data);

sys/dev/misc/musycc/musycc.c

1239

sc->reg->srd = sc->last = 0x1800;

sys/dev/misc/musycc/musycc.c

1241

sc->reg->srd = sc->last = 0x1820;

sys/dev/misc/musycc/musycc.c

1258

sc->reg->srd = sc->last = 0x0b00 + ch;

sys/dev/misc/musycc/musycc.c

1260

sc->reg->srd = sc->last = 0x0b20 + ch;

sys/dev/misc/musycc/musycc.c

1303

sc->reg->srd = sc->last = 0x0800 + ch;

sys/dev/misc/musycc/musycc.c

1305

sc->reg->srd = sc->last = 0x0820 + ch;

sys/dev/misc/musycc/musycc.c

1328

sc->reg->srd = sc->last = 0x0900 + sch->chan;

sys/dev/misc/musycc/musycc.c

1330

sc->reg->srd = sc->last = 0x0920 + sch->chan;

sys/dev/misc/musycc/musycc.c

1486

csc->reg = (struct globalr *)csc->virbase[0];

sys/dev/misc/musycc/musycc.c

1487

csc->reg->glcd = 0x3f30; /* XXX: designer magic */

sys/dev/misc/musycc/musycc.c

1507

sc->reg = (struct globalr *)

sys/dev/misc/musycc/musycc.c

1528

sc->reg->srd = sc->last = 0x100;

sys/dev/misc/musycc/musycc.c

219

struct globalr *reg;

sys/dev/misc/musycc/musycc.c

257

struct globalr *reg;

sys/dev/misc/musycc/musycc.c

359

sc->serial[i].reg->srd = 0;

sys/dev/misc/musycc/musycc.c

376

csc->reg->srd = 0x100;

sys/dev/misc/musycc/musycc.c

378

csc->reg->gbp = vtophys(csc->ram);

sys/dev/misc/musycc/musycc.c

385

csc->reg->srd = csc->serial[0].last = 0x400;

sys/dev/misc/musycc/musycc.c

401

kprintf("init_ctrl(%p) [%s] [%08x]\n", sc, sc->nodename, sc->csc->reg->glcd);

sys/dev/misc/musycc/musycc.c

404

kprintf("%s: glcd: [%08x]\n", sc->nodename, sc->csc->reg->glcd);

sys/dev/misc/musycc/musycc.c

405

sc->reg->gbp = vtophys(sc->ram);

sys/dev/misc/musycc/musycc.c

433

sc->reg->srd = sc->last = 0x500;

sys/dev/misc/musycc/musycc.c

435

sc->reg->srd = sc->last = 0x520;

sys/dev/misc/musycc/musycc.c

775

u = csc->reg->isd;

sys/dev/misc/musycc/musycc.c

804

kprintf(" cmd %08x (%08x) \n", sc->last, sc->reg->srd);

sys/dev/misc/musycc/musycc.c

839

csc->reg->isd = j << 16;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

188

#define GPIO_READ(sc, reg) \

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

190

(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg))

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

191

#define GPIO_WRITE(sc, reg, val) \

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

193

(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

194

#define TMS_WRITE(sc, reg, val) \

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

196

(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

197

#define TMS_READ(sc, reg) \

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

199

(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg))

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

200

#define VLM_WRITE(sc, reg, val) \

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

202

(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

203

#define VLM_READ(sc, reg) \

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

205

(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg))

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

562

int port, shift, reg;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

570

reg = SIO_GPDI0;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

573

reg = SIO_GPDI1;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

576

reg = SIO_GPDI2;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

579

reg = SIO_GPDI3;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

585

data = GPIO_READ(sc, reg);

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

594

int port, shift, reg;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

602

reg = SIO_GPDO0;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

605

reg = SIO_GPDO1;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

608

reg = SIO_GPDO2;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

611

reg = SIO_GPDO3;

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

617

data = GPIO_READ(sc, reg);

sys/dev/misc/nsclpcsio/nsclpcsio_isa.c

623

GPIO_WRITE(sc, reg, data);

sys/dev/misc/ppc/ppc.c

1341

int reg;

sys/dev/misc/ppc/ppc.c

1367

reg = mi->arg[1].i;

sys/dev/misc/ppc/ppc.c

1373

w_reg(reg, ppc, *ptr++);

sys/dev/misc/ppc/ppc.c

1377

w_reg(reg, ppc, *ptr++);

sys/dev/misc/ppc/ppc.c

1384

reg = mi->arg[1].i;

sys/dev/misc/ppc/ppc.c

1391

*ptr++ = r_reg(reg, ppc) & mask;

sys/dev/misc/ppc/ppc.c

1395

*ptr++ = r_reg(reg, ppc) & mask;

sys/dev/misc/ppc/ppc.c

1430

reg = mi->arg[0].i;

sys/dev/misc/ppc/ppc.c

1436

w_reg(reg, ppc, *p++);

sys/dev/misc/psm/psm.c

7078

elantech_read_1(KBDC kbdc, int hwversion, int reg, int *val)

sys/dev/misc/psm/psm.c

7089

res |= send_aux_command(kbdc, reg) != PSM_ACK;

sys/dev/misc/psm/psm.c

7099

elantech_write_1(KBDC kbdc, int hwversion, int reg, int val)

sys/dev/misc/psm/psm.c

7108

res |= send_aux_command(kbdc, reg) != PSM_ACK;

sys/dev/misc/syscons/syscons.c

4234

int reg;

sys/dev/misc/syscons/syscons.c

4247

reg = scp->sc->adp->va_palette_regs[i];

sys/dev/misc/syscons/syscons.c

4249

r = scp->sc->palette[reg * 3] >> (8 - rsize);

sys/dev/misc/syscons/syscons.c

4250

g = scp->sc->palette[reg * 3 + 1] >> (8 - gsize);

sys/dev/misc/syscons/syscons.c

4251

b = scp->sc->palette[reg * 3 + 2] >> (8 - bsize);

sys/dev/netif/ae/if_ae.c

1541

ae_vpd_read_word(struct ae_softc *sc, int reg, uint32_t *word)

sys/dev/netif/ae/if_ae.c

1551

val = 0x100 + reg * 4;

sys/dev/netif/ae/if_ae.c

1562

reg);

sys/dev/netif/ae/if_ae.c

157

#define AE_WRITE_4(_sc, reg, val) \

sys/dev/netif/ae/if_ae.c

1572

uint32_t word, reg, val;

sys/dev/netif/ae/if_ae.c

158

bus_space_write_4((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg), (val))

sys/dev/netif/ae/if_ae.c

159

#define AE_WRITE_2(_sc, reg, val) \

sys/dev/netif/ae/if_ae.c

160

bus_space_write_2((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg), (val))

sys/dev/netif/ae/if_ae.c

1600

reg = word >> AE_VPD_REG_SHIFT;

sys/dev/netif/ae/if_ae.c

1602

if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG)

sys/dev/netif/ae/if_ae.c

1608

if (reg == AE_EADDR0_REG)

sys/dev/netif/ae/if_ae.c

161

#define AE_WRITE_1(_sc, reg, val) \

sys/dev/netif/ae/if_ae.c

162

bus_space_write_1((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg), (val))

sys/dev/netif/ae/if_ae.c

163

#define AE_READ_4(_sc, reg) \

sys/dev/netif/ae/if_ae.c

164

bus_space_read_4((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg))

sys/dev/netif/ae/if_ae.c

165

#define AE_READ_2(_sc, reg) \

sys/dev/netif/ae/if_ae.c

166

bus_space_read_2((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg))

sys/dev/netif/ae/if_ae.c

167

#define AE_READ_1(_sc, reg) \

sys/dev/netif/ae/if_ae.c

168

bus_space_read_1((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg))

sys/dev/netif/ae/if_ae.c

170

#define AE_PHY_READ(sc, reg) \

sys/dev/netif/ae/if_ae.c

171

ae_miibus_readreg(sc->ae_dev, 0, reg)

sys/dev/netif/ae/if_ae.c

172

#define AE_PHY_WRITE(sc, reg, val) \

sys/dev/netif/ae/if_ae.c

173

ae_miibus_writereg(sc->ae_dev, 0, reg, val)

sys/dev/netif/ae/if_ae.c

437

ae_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/ae/if_ae.c

448

val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |

sys/dev/netif/ae/if_ae.c

463

device_printf(sc->ae_dev, "phy read timeout: %d.\n", reg);

sys/dev/netif/ae/if_ae.c

470

ae_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/ae/if_ae.c

481

aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |

sys/dev/netif/ae/if_ae.c

497

device_printf(sc->ae_dev, "phy write timeout: %d.\n", reg);

sys/dev/netif/age/if_age.c

1258

uint32_t reg, pmcs;

sys/dev/netif/age/if_age.c

1359

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

1360

reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);

sys/dev/netif/age/if_age.c

1361

reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);

sys/dev/netif/age/if_age.c

1363

reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;

sys/dev/netif/age/if_age.c

1365

reg |= MAC_CFG_RX_ENB;

sys/dev/netif/age/if_age.c

1366

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

1644

uint32_t reg;

sys/dev/netif/age/if_age.c

1706

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

1707

reg &= ~MAC_CFG_RXCSUM_ENB;

sys/dev/netif/age/if_age.c

1709

reg |= MAC_CFG_RXCSUM_ENB;

sys/dev/netif/age/if_age.c

1710

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

1731

uint32_t reg;

sys/dev/netif/age/if_age.c

1733

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

1734

reg &= ~MAC_CFG_FULL_DUPLEX;

sys/dev/netif/age/if_age.c

1735

reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);

sys/dev/netif/age/if_age.c

1736

reg &= ~MAC_CFG_SPEED_MASK;

sys/dev/netif/age/if_age.c

1742

reg |= MAC_CFG_SPEED_10_100;

sys/dev/netif/age/if_age.c

1745

reg |= MAC_CFG_SPEED_1000;

sys/dev/netif/age/if_age.c

1749

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/netif/age/if_age.c

1752

reg |= MAC_CFG_TX_FC;

sys/dev/netif/age/if_age.c

1754

reg |= MAC_CFG_RX_FC;

sys/dev/netif/age/if_age.c

1757

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

183

age_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/age/if_age.c

194

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/netif/age/if_age.c

203

device_printf(sc->age_dev, "phy read timeout : %d\n", reg);

sys/dev/netif/age/if_age.c

214

age_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/age/if_age.c

2205

uint32_t reg;

sys/dev/netif/age/if_age.c

2218

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/netif/age/if_age.c

2223

device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);

sys/dev/netif/age/if_age.c

2238

uint32_t reg, fsize;

sys/dev/netif/age/if_age.c

226

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/netif/age/if_age.c

2334

reg = CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/netif/age/if_age.c

2335

reg &= ~MASTER_MTIMER_ENB;

sys/dev/netif/age/if_age.c

2337

reg &= ~MASTER_ITIMER_ENB;

sys/dev/netif/age/if_age.c

2339

reg |= MASTER_ITIMER_ENB;

sys/dev/netif/age/if_age.c

2340

CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);

sys/dev/netif/age/if_age.c

235

device_printf(sc->age_dev, "phy write timeout : %d\n", reg);

sys/dev/netif/age/if_age.c

2396

reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);

sys/dev/netif/age/if_age.c

2397

rxf_lo = reg / 16;

sys/dev/netif/age/if_age.c

2400

rxf_hi = (reg * 7) / 8;

sys/dev/netif/age/if_age.c

2403

reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);

sys/dev/netif/age/if_age.c

2404

rrd_lo = reg / 8;

sys/dev/netif/age/if_age.c

2405

rrd_hi = (reg * 7) / 8;

sys/dev/netif/age/if_age.c

2494

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2496

reg |= MAC_CFG_RXCSUM_ENB;

sys/dev/netif/age/if_age.c

2503

CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/netif/age/if_age.c

2521

uint32_t reg;

sys/dev/netif/age/if_age.c

2559

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/netif/age/if_age.c

2565

"stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);

sys/dev/netif/age/if_age.c

2598

uint32_t reg;

sys/dev/netif/age/if_age.c

2601

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2602

if ((reg & MAC_CFG_TX_ENB) != 0) {

sys/dev/netif/age/if_age.c

2603

reg &= ~MAC_CFG_TX_ENB;

sys/dev/netif/age/if_age.c

2604

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

2607

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/netif/age/if_age.c

2608

if ((reg & DMA_CFG_RD_ENB) != 0) {

sys/dev/netif/age/if_age.c

2609

reg &= ~DMA_CFG_RD_ENB;

sys/dev/netif/age/if_age.c

2610

CSR_WRITE_4(sc, AGE_DMA_CFG, reg);

sys/dev/netif/age/if_age.c

2625

uint32_t reg;

sys/dev/netif/age/if_age.c

2628

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2629

if ((reg & MAC_CFG_RX_ENB) != 0) {

sys/dev/netif/age/if_age.c

2630

reg &= ~MAC_CFG_RX_ENB;

sys/dev/netif/age/if_age.c

2631

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

2634

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/netif/age/if_age.c

2635

if ((reg & DMA_CFG_WR_ENB) != 0) {

sys/dev/netif/age/if_age.c

2636

reg &= ~DMA_CFG_WR_ENB;

sys/dev/netif/age/if_age.c

2637

CSR_WRITE_4(sc, AGE_DMA_CFG, reg);

sys/dev/netif/age/if_age.c

276

uint32_t reg;

sys/dev/netif/age/if_age.c

2792

uint32_t reg;

sys/dev/netif/age/if_age.c

2794

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2795

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/netif/age/if_age.c

2797

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/netif/age/if_age.c

2798

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

280

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

284

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/netif/age/if_age.c

285

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/netif/age/if_age.c

374

uint32_t ea[2], off, reg, word;

sys/dev/netif/age/if_age.c

377

reg = CSR_READ_4(sc, AGE_SPI_CTRL);

sys/dev/netif/age/if_age.c

378

if ((reg & SPI_VPD_ENB) != 0) {

sys/dev/netif/age/if_age.c

380

reg &= ~SPI_VPD_ENB;

sys/dev/netif/age/if_age.c

381

CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);

sys/dev/netif/age/if_age.c

401

reg = 0;

sys/dev/netif/age/if_age.c

408

switch (reg) {

sys/dev/netif/age/if_age.c

421

reg = word >> 16;

sys/dev/netif/age/if_agevar.h

229

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/netif/age/if_agevar.h

230

bus_space_write_4((_sc)->age_mem_bt, (_sc)->age_mem_bh, (reg), (val))

sys/dev/netif/age/if_agevar.h

231

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/netif/age/if_agevar.h

232

bus_space_write_2((_sc)->age_mem_bt, (_sc)->age_mem_bh, (reg), (val))

sys/dev/netif/age/if_agevar.h

234

#define CSR_READ_4(_sc, reg) \

sys/dev/netif/age/if_agevar.h

235

bus_space_read_4((_sc)->age_mem_bt, (_sc)->age_mem_bh, (reg))

sys/dev/netif/age/if_agevar.h

236

#define CSR_READ_2(_sc, reg) \

sys/dev/netif/age/if_agevar.h

237

bus_space_read_2((_sc)->age_mem_bt, (_sc)->age_mem_bh, (reg))

sys/dev/netif/alc/if_alc.c

242

alc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/alc/if_alc.c

249

v = alc_mii_readreg_816x(sc, phy, reg);

sys/dev/netif/alc/if_alc.c

251

v = alc_mii_readreg_813x(sc, phy, reg);

sys/dev/netif/alc/if_alc.c

256

alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)

sys/dev/netif/alc/if_alc.c

268

reg == MII_EXTSR)

sys/dev/netif/alc/if_alc.c

272

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/netif/alc/if_alc.c

281

device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);

sys/dev/netif/alc/if_alc.c

289

alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)

sys/dev/netif/alc/if_alc.c

2891

uint32_t reg;

sys/dev/netif/alc/if_alc.c

2894

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

2895

reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |

sys/dev/netif/alc/if_alc.c

2901

reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;

sys/dev/netif/alc/if_alc.c

2907

reg |= MAC_CFG_SPEED_10_100;

sys/dev/netif/alc/if_alc.c

2910

reg |= MAC_CFG_SPEED_1000;

sys/dev/netif/alc/if_alc.c

2914

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/netif/alc/if_alc.c

2916

reg |= MAC_CFG_TX_FC;

sys/dev/netif/alc/if_alc.c

2918

reg |= MAC_CFG_RX_FC;

sys/dev/netif/alc/if_alc.c

2920

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/netif/alc/if_alc.c

2927

uint32_t *reg;

sys/dev/netif/alc/if_alc.c

2941

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;

sys/dev/netif/alc/if_alc.c

2942

reg++) {

sys/dev/netif/alc/if_alc.c

2947

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;

sys/dev/netif/alc/if_alc.c

2948

reg++) {

sys/dev/netif/alc/if_alc.c

2961

uint32_t *reg;

sys/dev/netif/alc/if_alc.c

2976

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;

sys/dev/netif/alc/if_alc.c

2977

reg++) {

sys/dev/netif/alc/if_alc.c

2978

*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/netif/alc/if_alc.c

2982

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;

sys/dev/netif/alc/if_alc.c

2983

reg++) {

sys/dev/netif/alc/if_alc.c

2984

*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/netif/alc/if_alc.c

299

MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));

sys/dev/netif/alc/if_alc.c

308

device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);

sys/dev/netif/alc/if_alc.c

316

alc_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/alc/if_alc.c

323

v = alc_mii_writereg_816x(sc, phy, reg, val);

sys/dev/netif/alc/if_alc.c

325

v = alc_mii_writereg_813x(sc, phy, reg, val);

sys/dev/netif/alc/if_alc.c

330

alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)

sys/dev/netif/alc/if_alc.c

337

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/netif/alc/if_alc.c

3441

uint32_t reg;

sys/dev/netif/alc/if_alc.c

3443

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/netif/alc/if_alc.c

3444

reg &= ~MISC3_25M_BY_SW;

sys/dev/netif/alc/if_alc.c

3445

reg |= MISC3_25M_NOTO_INTNL;

sys/dev/netif/alc/if_alc.c

3446

CSR_WRITE_4(sc, ALC_MISC3, reg);

sys/dev/netif/alc/if_alc.c

3448

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/netif/alc/if_alc.c

3454

reg &= ~MISC_PSW_OCP_MASK;

sys/dev/netif/alc/if_alc.c

3455

reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);

sys/dev/netif/alc/if_alc.c

3456

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/netif/alc/if_alc.c

3457

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/netif/alc/if_alc.c

3458

CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);

sys/dev/netif/alc/if_alc.c

3459

reg = CSR_READ_4(sc, ALC_MISC2);

sys/dev/netif/alc/if_alc.c

346

device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);

sys/dev/netif/alc/if_alc.c

3460

reg &= ~MISC2_CALB_START;

sys/dev/netif/alc/if_alc.c

3461

CSR_WRITE_4(sc, ALC_MISC2, reg);

sys/dev/netif/alc/if_alc.c

3462

CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);

sys/dev/netif/alc/if_alc.c

3465

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/netif/alc/if_alc.c

3468

reg &= ~MISC_ISO_ENB;

sys/dev/netif/alc/if_alc.c

3469

CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);

sys/dev/netif/alc/if_alc.c

3470

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/netif/alc/if_alc.c

3479

uint32_t pmcfg, reg;

sys/dev/netif/alc/if_alc.c

3498

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

3499

reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;

sys/dev/netif/alc/if_alc.c

3500

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/netif/alc/if_alc.c

352

alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)

sys/dev/netif/alc/if_alc.c

3521

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/netif/alc/if_alc.c

3522

if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |

sys/dev/netif/alc/if_alc.c

3529

device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);

sys/dev/netif/alc/if_alc.c

3534

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

3535

reg |= MASTER_CLK_SEL_DIS;

sys/dev/netif/alc/if_alc.c

3536

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/netif/alc/if_alc.c

3544

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/netif/alc/if_alc.c

3545

reg &= ~MISC3_25M_BY_SW;

sys/dev/netif/alc/if_alc.c

3546

reg |= MISC3_25M_NOTO_INTNL;

sys/dev/netif/alc/if_alc.c

3547

CSR_WRITE_4(sc, ALC_MISC3, reg);

sys/dev/netif/alc/if_alc.c

3548

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/netif/alc/if_alc.c

3549

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/netif/alc/if_alc.c

3551

reg &= ~MISC_ISO_ENB;

sys/dev/netif/alc/if_alc.c

3552

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/netif/alc/if_alc.c

3571

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/netif/alc/if_alc.c

362

((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |

sys/dev/netif/alc/if_alc.c

3690

reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;

sys/dev/netif/alc/if_alc.c

3692

reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;

sys/dev/netif/alc/if_alc.c

3693

CSR_WRITE_4(sc, ALC_IM_TIMER, reg);

sys/dev/netif/alc/if_alc.c

3698

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

3699

reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);

sys/dev/netif/alc/if_alc.c

3700

reg |= MASTER_SA_TIMER_ENB;

sys/dev/netif/alc/if_alc.c

3702

reg |= MASTER_IM_RX_TIMER_ENB;

sys/dev/netif/alc/if_alc.c

3705

reg |= MASTER_IM_TX_TIMER_ENB;

sys/dev/netif/alc/if_alc.c

3706

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/netif/alc/if_alc.c

372

device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);

sys/dev/netif/alc/if_alc.c

3782

reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &

sys/dev/netif/alc/if_alc.c

3785

reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;

sys/dev/netif/alc/if_alc.c

3786

CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);

sys/dev/netif/alc/if_alc.c

3788

reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<

sys/dev/netif/alc/if_alc.c

3792

reg >>= 1;

sys/dev/netif/alc/if_alc.c

3794

reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &

sys/dev/netif/alc/if_alc.c

3796

reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;

sys/dev/netif/alc/if_alc.c

3797

CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);

sys/dev/netif/alc/if_alc.c

3800

reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |

sys/dev/netif/alc/if_alc.c

3804

CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);

sys/dev/netif/alc/if_alc.c

3805

reg = WRR_PRI_RESTRICT_NONE;

sys/dev/netif/alc/if_alc.c

3806

reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |

sys/dev/netif/alc/if_alc.c

3810

CSR_WRITE_4(sc, ALC_WRR, reg);

sys/dev/netif/alc/if_alc.c

3826

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/netif/alc/if_alc.c

3827

reg &= SRAM_RX_FIFO_LEN_MASK;

sys/dev/netif/alc/if_alc.c

3828

reg *= 8;

sys/dev/netif/alc/if_alc.c

3829

if (reg > 8 * 1024)

sys/dev/netif/alc/if_alc.c

383

uint32_t reg;

sys/dev/netif/alc/if_alc.c

3830

reg -= RX_FIFO_PAUSE_816X_RSVD;

sys/dev/netif/alc/if_alc.c

3832

reg -= RX_BUF_SIZE_MAX;

sys/dev/netif/alc/if_alc.c

3833

reg /= 8;

sys/dev/netif/alc/if_alc.c

3835

((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &

sys/dev/netif/alc/if_alc.c

3842

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/netif/alc/if_alc.c

3843

rxf_hi = (reg * 8) / 10;

sys/dev/netif/alc/if_alc.c

3844

rxf_lo = (reg * 3) / 10;

sys/dev/netif/alc/if_alc.c

3859

reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &

sys/dev/netif/alc/if_alc.c

3861

reg |= RXQ_CFG_RSS_MODE_DIS;

sys/dev/netif/alc/if_alc.c

3863

reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<

sys/dev/netif/alc/if_alc.c

3867

reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;

sys/dev/netif/alc/if_alc.c

3871

reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;

sys/dev/netif/alc/if_alc.c

3873

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/netif/alc/if_alc.c

3876

reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;

sys/dev/netif/alc/if_alc.c

3877

reg |= sc->alc_rcb;

sys/dev/netif/alc/if_alc.c

3879

reg |= DMA_CFG_CMB_ENB;

sys/dev/netif/alc/if_alc.c

3881

reg |= DMA_CFG_SMB_ENB;

sys/dev/netif/alc/if_alc.c

3883

reg |= DMA_CFG_SMB_DIS;

sys/dev/netif/alc/if_alc.c

3884

reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<

sys/dev/netif/alc/if_alc.c

3886

reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<

sys/dev/netif/alc/if_alc.c

3888

reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &

sys/dev/netif/alc/if_alc.c

3890

reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &

sys/dev/netif/alc/if_alc.c

3896

reg |= DMA_CFG_RD_CHNL_SEL_2;

sys/dev/netif/alc/if_alc.c

3901

reg |= DMA_CFG_RD_CHNL_SEL_4;

sys/dev/netif/alc/if_alc.c

3905

CSR_WRITE_4(sc, ALC_DMA_CFG, reg);

sys/dev/netif/alc/if_alc.c

3920

reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |

sys/dev/netif/alc/if_alc.c

3927

reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;

sys/dev/netif/alc/if_alc.c

3930

reg |= MAC_CFG_SPEED_10_100;

sys/dev/netif/alc/if_alc.c

3932

reg |= MAC_CFG_SPEED_1000;

sys/dev/netif/alc/if_alc.c

3933

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/netif/alc/if_alc.c

3962

uint32_t reg;

sys/dev/netif/alc/if_alc.c

3980

reg = CSR_READ_4(sc, ALC_DMA_CFG);

sys/dev/netif/alc/if_alc.c

3981

reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);

sys/dev/netif/alc/if_alc.c

3982

reg |= DMA_CFG_SMB_DIS;

sys/dev/netif/alc/if_alc.c

3983

CSR_WRITE_4(sc, ALC_DMA_CFG, reg);

sys/dev/netif/alc/if_alc.c

4026

uint32_t reg;

sys/dev/netif/alc/if_alc.c

4031

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

4032

if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {

sys/dev/netif/alc/if_alc.c

4033

reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/netif/alc/if_alc.c

4034

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/netif/alc/if_alc.c

4037

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/netif/alc/if_alc.c

4038

if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)

sys/dev/netif/alc/if_alc.c

4044

"could not disable Rx/Tx MAC(0x%08x)!\n", reg);

sys/dev/netif/alc/if_alc.c

4076

uint32_t reg;

sys/dev/netif/alc/if_alc.c

4080

reg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/netif/alc/if_alc.c

4082

if ((reg & RXQ_CFG_ENB) != 0) {

sys/dev/netif/alc/if_alc.c

4083

reg &= ~RXQ_CFG_ENB;

sys/dev/netif/alc/if_alc.c

4084

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/netif/alc/if_alc.c

4087

if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {

sys/dev/netif/alc/if_alc.c

4088

reg &= ~RXQ_CFG_QUEUE0_ENB;

sys/dev/netif/alc/if_alc.c

4089

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/netif/alc/if_alc.c

4093

reg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/netif/alc/if_alc.c

4094

if ((reg & TXQ_CFG_ENB) != 0) {

sys/dev/netif/alc/if_alc.c

4095

reg &= ~TXQ_CFG_ENB;

sys/dev/netif/alc/if_alc.c

4096

CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);

sys/dev/netif/alc/if_alc.c

4100

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/netif/alc/if_alc.c

4101

if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)

sys/dev/netif/alc/if_alc.c

4107

"could not disable RxQ/TxQ (0x%08x)!\n", reg);

sys/dev/netif/alc/if_alc.c

417

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

418

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/netif/alc/if_alc.c

419

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/netif/alc/if_alc.c

4204

uint32_t reg;

sys/dev/netif/alc/if_alc.c

4207

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

4209

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/netif/alc/if_alc.c

4211

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/netif/alc/if_alc.c

4212

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/netif/alc/if_alc.c

426

alc_miidbg_readreg(struct alc_softc *sc, int reg)

sys/dev/netif/alc/if_alc.c

430

reg);

sys/dev/netif/alc/if_alc.c

436

alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)

sys/dev/netif/alc/if_alc.c

440

reg);

sys/dev/netif/alc/if_alc.c

446

alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)

sys/dev/netif/alc/if_alc.c

451

CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |

sys/dev/netif/alc/if_alc.c

468

devaddr, reg);

sys/dev/netif/alc/if_alc.c

476

alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)

sys/dev/netif/alc/if_alc.c

481

CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |

sys/dev/netif/alc/if_alc.c

499

devaddr, reg);

sys/dev/netif/alc/if_alc.c

770

uint32_t reg;

sys/dev/netif/alc/if_alc.c

776

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/netif/alc/if_alc.c

777

if ((reg & (SLD_PROGRESS | SLD_START)) == 0)

sys/dev/netif/alc/if_alc.c

782

CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);

sys/dev/netif/alc/if_alc.c

785

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/netif/alc/if_alc.c

786

if ((reg & SLD_START) == 0)

sys/dev/netif/alc/if_alc.c

798

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/netif/alc/if_alc.c

799

if ((reg & (EEPROM_LD_EEPROM_EXIST |

sys/dev/netif/alc/if_alc.c

802

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/netif/alc/if_alc.c

803

if ((reg & (EEPROM_LD_PROGRESS |

sys/dev/netif/alc/if_alc.c

809

CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |

sys/dev/netif/alc/if_alc.c

813

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/netif/alc/if_alc.c

814

if ((reg & EEPROM_LD_START) == 0)

sys/dev/netif/alc/if_alcvar.h

258

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/alc/if_alcvar.h

259

bus_space_write_4(sc->alc_res_btag, sc->alc_res_bhand, (reg), (val))

sys/dev/netif/alc/if_alcvar.h

260

#define CSR_READ_4(sc, reg) \

sys/dev/netif/alc/if_alcvar.h

261

bus_space_read_4(sc->alc_res_btag, sc->alc_res_bhand, (reg))

sys/dev/netif/alc/if_alcvar.h

262

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/alc/if_alcvar.h

263

bus_space_write_2(sc->alc_res_btag, sc->alc_res_bhand, (reg), (val))

sys/dev/netif/alc/if_alcvar.h

264

#define CSR_READ_2(sc, reg) \

sys/dev/netif/alc/if_alcvar.h

265

bus_space_read_2(sc->alc_res_btag, sc->alc_res_bhand, (reg))

sys/dev/netif/ale/if_ale.c

1388

uint32_t reg, pmcs;

sys/dev/netif/ale/if_ale.c

1397

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/netif/ale/if_ale.c

1398

reg |= PCIE_PHYMISC_FORCE_RCV_DET;

sys/dev/netif/ale/if_ale.c

1399

CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);

sys/dev/netif/ale/if_ale.c

1419

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

1420

reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |

sys/dev/netif/ale/if_ale.c

1423

reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;

sys/dev/netif/ale/if_ale.c

1425

reg |= MAC_CFG_RX_ENB;

sys/dev/netif/ale/if_ale.c

1426

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/netif/ale/if_ale.c

1430

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/netif/ale/if_ale.c

1431

reg |= PCIE_PHYMISC_FORCE_RCV_DET;

sys/dev/netif/ale/if_ale.c

1432

CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);

sys/dev/netif/ale/if_ale.c

181

ale_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/ale/if_ale.c

1813

uint32_t reg;

sys/dev/netif/ale/if_ale.c

1816

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

1817

reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |

sys/dev/netif/ale/if_ale.c

1823

reg |= MAC_CFG_SPEED_10_100;

sys/dev/netif/ale/if_ale.c

1826

reg |= MAC_CFG_SPEED_1000;

sys/dev/netif/ale/if_ale.c

1830

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/netif/ale/if_ale.c

1833

reg |= MAC_CFG_TX_FC;

sys/dev/netif/ale/if_ale.c

1835

reg |= MAC_CFG_RX_FC;

sys/dev/netif/ale/if_ale.c

1838

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/netif/ale/if_ale.c

1845

uint32_t *reg;

sys/dev/netif/ale/if_ale.c

1848

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {

sys/dev/netif/ale/if_ale.c

1853

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {

sys/dev/netif/ale/if_ale.c

1865

uint32_t *reg;

sys/dev/netif/ale/if_ale.c

1873

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {

sys/dev/netif/ale/if_ale.c

1874

*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/netif/ale/if_ale.c

1878

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {

sys/dev/netif/ale/if_ale.c

1879

*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/netif/ale/if_ale.c

193

if (reg == MII_100T2CR || reg == MII_100T2SR ||

sys/dev/netif/ale/if_ale.c

194

reg == MII_EXTSR)

sys/dev/netif/ale/if_ale.c

199

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/netif/ale/if_ale.c

208

device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);

sys/dev/netif/ale/if_ale.c

216

ale_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/ale/if_ale.c

2277

uint32_t reg;

sys/dev/netif/ale/if_ale.c

228

if (reg == MII_100T2CR || reg == MII_100T2SR ||

sys/dev/netif/ale/if_ale.c

229

reg == MII_EXTSR)

sys/dev/netif/ale/if_ale.c

2293

if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)

sys/dev/netif/ale/if_ale.c

2299

device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);

sys/dev/netif/ale/if_ale.c

2310

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/netif/ale/if_ale.c

235

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/netif/ale/if_ale.c

2394

reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;

sys/dev/netif/ale/if_ale.c

2395

reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;

sys/dev/netif/ale/if_ale.c

2396

CSR_WRITE_4(sc, ALE_IM_TIMER, reg);

sys/dev/netif/ale/if_ale.c

2397

reg = CSR_READ_4(sc, ALE_MASTER_CFG);

sys/dev/netif/ale/if_ale.c

2398

reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);

sys/dev/netif/ale/if_ale.c

2399

reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);

sys/dev/netif/ale/if_ale.c

2401

reg |= MASTER_IM_RX_TIMER_ENB;

sys/dev/netif/ale/if_ale.c

2403

reg |= MASTER_IM_TX_TIMER_ENB;

sys/dev/netif/ale/if_ale.c

2404

CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);

sys/dev/netif/ale/if_ale.c

2436

reg = sc->ale_max_frame_size;

sys/dev/netif/ale/if_ale.c

2438

reg = (sc->ale_max_frame_size * 2) / 3;

sys/dev/netif/ale/if_ale.c

244

device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);

sys/dev/netif/ale/if_ale.c

2440

reg = sc->ale_max_frame_size / 2;

sys/dev/netif/ale/if_ale.c

2442

roundup(reg, TX_JUMBO_THRESH_UNIT) >>

sys/dev/netif/ale/if_ale.c

2447

reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))

sys/dev/netif/ale/if_ale.c

2449

reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &

sys/dev/netif/ale/if_ale.c

2451

CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);

sys/dev/netif/ale/if_ale.c

2455

reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);

sys/dev/netif/ale/if_ale.c

2457

(((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<

sys/dev/netif/ale/if_ale.c

2461

reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/netif/ale/if_ale.c

2462

rxf_hi = (reg * 7) / 10;

sys/dev/netif/ale/if_ale.c

2463

rxf_lo = (reg * 3)/ 10;

sys/dev/netif/ale/if_ale.c

2480

reg = 0;

sys/dev/netif/ale/if_ale.c

2482

reg |= DMA_CFG_TXCMB_ENB;

sys/dev/netif/ale/if_ale.c

2485

sc->ale_dma_rd_burst | reg |

sys/dev/netif/ale/if_ale.c

2514

reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |

sys/dev/netif/ale/if_ale.c

2518

reg |= MAC_CFG_SPEED_10_100;

sys/dev/netif/ale/if_ale.c

2520

reg |= MAC_CFG_SPEED_1000;

sys/dev/netif/ale/if_ale.c

2521

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/netif/ale/if_ale.c

2548

uint32_t reg;

sys/dev/netif/ale/if_ale.c

255

uint32_t reg;

sys/dev/netif/ale/if_ale.c

2570

reg = CSR_READ_4(sc, ALE_TXQ_CFG);

sys/dev/netif/ale/if_ale.c

2571

reg &= ~TXQ_CFG_ENB;

sys/dev/netif/ale/if_ale.c

2572

CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);

sys/dev/netif/ale/if_ale.c

2573

reg = CSR_READ_4(sc, ALE_RXQ_CFG);

sys/dev/netif/ale/if_ale.c

2574

reg &= ~RXQ_CFG_ENB;

sys/dev/netif/ale/if_ale.c

2575

CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);

sys/dev/netif/ale/if_ale.c

2576

reg = CSR_READ_4(sc, ALE_DMA_CFG);

sys/dev/netif/ale/if_ale.c

2577

reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);

sys/dev/netif/ale/if_ale.c

2578

CSR_WRITE_4(sc, ALE_DMA_CFG, reg);

sys/dev/netif/ale/if_ale.c

2604

uint32_t reg;

sys/dev/netif/ale/if_ale.c

2607

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

2608

if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {

sys/dev/netif/ale/if_ale.c

2609

reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/netif/ale/if_ale.c

2610

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/netif/ale/if_ale.c

2614

reg = CSR_READ_4(sc, ALE_IDLE_STATUS);

sys/dev/netif/ale/if_ale.c

2615

if (reg == 0)

sys/dev/netif/ale/if_ale.c

2621

"could not disable Tx/Rx MAC(0x%08x)!\n", reg);

sys/dev/netif/ale/if_ale.c

2675

uint32_t reg;

sys/dev/netif/ale/if_ale.c

2678

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

2679

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/netif/ale/if_ale.c

2681

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/netif/ale/if_ale.c

2682

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/netif/ale/if_ale.c

290

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

291

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/netif/ale/if_ale.c

292

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/netif/ale/if_ale.c

354

uint32_t ea[2], reg;

sys/dev/netif/ale/if_ale.c

357

reg = CSR_READ_4(sc, ALE_SPI_CTRL);

sys/dev/netif/ale/if_ale.c

358

if ((reg & SPI_VPD_ENB) != 0) {

sys/dev/netif/ale/if_ale.c

359

reg &= ~SPI_VPD_ENB;

sys/dev/netif/ale/if_ale.c

360

CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);

sys/dev/netif/ale/if_ale.c

373

reg = CSR_READ_4(sc, ALE_TWSI_CTRL);

sys/dev/netif/ale/if_ale.c

374

if ((reg & TWSI_CTRL_SW_LD_START) == 0)

sys/dev/netif/ale/if_alevar.h

229

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/netif/ale/if_alevar.h

230

bus_space_write_4((_sc)->ale_mem_bt, (_sc)->ale_mem_bh, (reg), (val))

sys/dev/netif/ale/if_alevar.h

231

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/netif/ale/if_alevar.h

232

bus_space_write_2((_sc)->ale_mem_bt, (_sc)->ale_mem_bh, (reg), (val))

sys/dev/netif/ale/if_alevar.h

233

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/netif/ale/if_alevar.h

234

bus_space_write_1((_sc)->ale_mem_bt, (_sc)->ale_mem_bh, (reg), (val))

sys/dev/netif/ale/if_alevar.h

235

#define CSR_READ_2(_sc, reg) \

sys/dev/netif/ale/if_alevar.h

236

bus_space_read_2((_sc)->ale_mem_bt, (_sc)->ale_mem_bh, (reg))

sys/dev/netif/ale/if_alevar.h

237

#define CSR_READ_4(_sc, reg) \

sys/dev/netif/ale/if_alevar.h

238

bus_space_read_4((_sc)->ale_mem_bt, (_sc)->ale_mem_bh, (reg))

sys/dev/netif/ath/ath/if_ath.c

6049

ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,

sys/dev/netif/ath/ath/if_ath.c

6058

__func__, reg->regdomain, reg->country, reg->location,

sys/dev/netif/ath/ath/if_ath.c

6059

reg->ecm ? " ecm" : "");

sys/dev/netif/ath/ath/if_ath.c

6062

reg->country, reg->regdomain);

sys/dev/netif/ath/ath_hal/ah.c

228

ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)

sys/dev/netif/ath/ath_hal/ah.c

231

return ath_hal_waitfor(ah, reg, mask, val, AH_TIMEOUT);

sys/dev/netif/ath/ath_hal/ah.c

236

ath_hal_waitfor(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val, uint32_t timeout)

sys/dev/netif/ath/ath_hal/ah.c

241

if ((OS_REG_READ(ah, reg) & mask) == val)

sys/dev/netif/ath/ath_hal/ah.c

247

__func__, reg, OS_REG_READ(ah, reg), mask, val);

sys/dev/netif/ath/ath_hal/ah_decode.h

34

reg : 24;

sys/dev/netif/ath/ath_hal/ah_internal.h

609

extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,

sys/dev/netif/ath/ath_hal/ah_internal.h

611

extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,

sys/dev/netif/ath/ath_hal/ah_osdep.c

161

ath_hal_reg_whilst_asleep(struct ath_hal *ah, uint32_t reg)

sys/dev/netif/ath/ath_hal/ah_osdep.c

164

if (reg >= 0x4000 && reg < 0x5000)

sys/dev/netif/ath/ath_hal/ah_osdep.c

166

if (reg >= 0x6000 && reg < 0x7000)

sys/dev/netif/ath/ath_hal/ah_osdep.c

168

if (reg >= 0x7000 && reg < 0x8000)

sys/dev/netif/ath/ath_hal/ah_osdep.c

269

r->reg = 0;

sys/dev/netif/ath/ath_hal/ah_osdep.c

283

ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)

sys/dev/netif/ath/ath_hal/ah_osdep.c

290

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/netif/ath/ath_hal/ah_osdep.c

293

__func__, reg, val, ah->ah_powerMode);

sys/dev/netif/ath/ath_hal/ah_osdep.c

303

r->reg = reg;

sys/dev/netif/ath/ath_hal/ah_osdep.c

310

bus_space_write_4(tag, h, reg, val);

sys/dev/netif/ath/ath_hal/ah_osdep.c

311

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);

sys/dev/netif/ath/ath_hal/ah_osdep.c

317

ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)

sys/dev/netif/ath/ath_hal/ah_osdep.c

324

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/netif/ath/ath_hal/ah_osdep.c

327

__func__, reg, ah->ah_powerMode);

sys/dev/netif/ath/ath_hal/ah_osdep.c

332

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);

sys/dev/netif/ath/ath_hal/ah_osdep.c

333

val = bus_space_read_4(tag, h, reg);

sys/dev/netif/ath/ath_hal/ah_osdep.c

342

r->reg = reg;

sys/dev/netif/ath/ath_hal/ah_osdep.c

359

r->reg = id;

sys/dev/netif/ath/ath_hal/ah_osdep.c

379

ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)

sys/dev/netif/ath/ath_hal/ah_osdep.c

386

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/netif/ath/ath_hal/ah_osdep.c

389

__func__, reg, val, ah->ah_powerMode);

sys/dev/netif/ath/ath_hal/ah_osdep.c

395

bus_space_write_4(tag, h, reg, val);

sys/dev/netif/ath/ath_hal/ah_osdep.c

396

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);

sys/dev/netif/ath/ath_hal/ah_osdep.c

402

ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)

sys/dev/netif/ath/ath_hal/ah_osdep.c

410

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/netif/ath/ath_hal/ah_osdep.c

413

__func__, reg, ah->ah_powerMode);

sys/dev/netif/ath/ath_hal/ah_osdep.c

419

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);

sys/dev/netif/ath/ath_hal/ah_osdep.c

420

val = bus_space_read_4(tag, h, reg);

sys/dev/netif/ath/ath_hal/ah_osdep.h

152

extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);

sys/dev/netif/ath/ath_hal/ah_osdep.h

153

extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

193

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

197

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

198

reg &= ~(1 << gpio);

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

199

reg |= (val&1) << gpio;

sys/dev/netif/ath/ath_hal/ar5210/ar5210_misc.c

201

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/netif/ath/ath_hal/ar5210/ar5210_reset.c

209

uint32_t reg = ar5k0007_init[i].Offset;

sys/dev/netif/ath/ath_hal/ar5210/ar5210_reset.c

211

if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))

sys/dev/netif/ath/ath_hal/ar5210/ar5210_reset.c

212

OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

197

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

201

reg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

202

reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

203

reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

205

OS_REG_WRITE(ah, AR_GPIOCR, reg);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

215

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

219

reg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

220

reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

221

reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

223

OS_REG_WRITE(ah, AR_GPIOCR, reg);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

233

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

237

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

238

reg &= ~(1 << gpio);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

239

reg |= (val&1) << gpio;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_misc.c

241

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

331

uint32_t reg = ar5211Common[i][0];

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

333

if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

334

OS_REG_WRITE(ah, reg, ar5211Common[i][1]);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_gpio.c

74

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5212/ar5212_gpio.c

78

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_gpio.c

79

reg &= ~(1 << gpio);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_gpio.c

80

reg |= (val&1) << gpio;

sys/dev/netif/ath/ath_hal/ar5212/ar5212_gpio.c

82

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

302

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

319

reg = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

321

OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_misc.c

323

OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

2746

uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

2751

OS_REG_WRITE(ah, reg,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

2757

reg += rt->info[i].shortPreamble << 2;

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

2758

OS_REG_WRITE(ah, reg,

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

83

uint32_t reg = V(r, 0);

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

86

if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {

sys/dev/netif/ath/ath_hal/ar5212/ar5212_reset.c

87

OS_REG_WRITE(ah, reg, V(r, 1));

sys/dev/netif/ath/ath_hal/ar5312/ar5312_gpio.c

74

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_gpio.c

79

reg = OS_REG_READ(ah, gpioOffset+AR5312_GPIODO);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_gpio.c

80

reg &= ~(1 << gpio);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_gpio.c

81

reg |= (val&1) << gpio;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_gpio.c

83

OS_REG_WRITE(ah, gpioOffset+AR5312_GPIODO, reg);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

67

uint32_t reg = V(i, 0);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

70

if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

71

OS_REG_WRITE(ah, reg, V(i, 1));

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

771

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

794

reg = OS_REG_READ(ah,

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

799

reg |= resetBB; /* Cold and warm reset the baseband bits */

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

805

reg &= regMask;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

806

reg |= (resetBits | resetBB) ;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

810

reg);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

817

reg &= regMask;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

823

reg);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

851

reg = OS_REG_READ(ah,

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

856

reg |= resetBB; /* Cold and warm reset the baseband bits */

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

862

reg &= regMask;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

863

reg |= (resetBits | resetBB) ;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

867

reg);

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

874

reg &= regMask;

sys/dev/netif/ath/ath_hal/ar5312/ar5312_reset.c

880

reg);

sys/dev/netif/ath/ath_hal/ar5312/ar5315_gpio.c

74

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5312/ar5315_gpio.c

79

reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO);

sys/dev/netif/ath/ath_hal/ar5312/ar5315_gpio.c

80

reg &= ~(1 << gpio);

sys/dev/netif/ath/ath_hal/ar5312/ar5315_gpio.c

81

reg |= (val&1) << gpio;

sys/dev/netif/ath/ath_hal/ar5312/ar5315_gpio.c

83

OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODO, reg);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

124

reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

125

reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

126

reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

127

OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

139

uint32_t gpio_shift, reg;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

149

reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

150

reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

151

reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

152

OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

163

uint32_t reg;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

169

reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

171

reg |= AR_GPIO_BIT(gpio);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

173

reg &= ~AR_GPIO_BIT(gpio);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

174

OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c

86

uint32_t gpio_shift, reg;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_reset.c

461

unsigned int reg;

sys/dev/netif/ath/ath_hal/ar5416/ar5416_reset.c

462

reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));

sys/dev/netif/ath/ath_hal/ar5416/ar5416_reset.c

463

OS_REG_WRITE(ah,AR_STA_ID1, reg);

sys/dev/netif/ath/ath_hal/ar5416/ar5416_reset.c

464

ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg);

sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c

535

uint32_t reg = HAL_INI_VAL(ia, i, 0);

sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c

538

if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup)

sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c

541

OS_REG_WRITE(ah, reg, val);

sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c

544

if (reg >= 0x7800 && reg < 0x7900)

sys/dev/netif/bce/if_bce.c

1256

bce_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/netif/bce/if_bce.c

1276

val = BCE_MIPHY(phy) | BCE_MIREG(reg) |

sys/dev/netif/bce/if_bce.c

1297

phy, reg);

sys/dev/netif/bce/if_bce.c

1324

bce_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/netif/bce/if_bce.c

1344

val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |

sys/dev/netif/bce/if_bce.c

3683

uint32_t reg, val;

sys/dev/netif/bce/if_bce.c

3777

reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);

sys/dev/netif/bce/if_bce.c

3779

if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=

sys/dev/netif/bce/if_bce.c

3784

reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,

sys/dev/netif/bce/if_bcereg.h

533

#define REG_WR(sc, reg, val) \

sys/dev/netif/bce/if_bcereg.h

534

bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)

sys/dev/netif/bce/if_bcereg.h

535

#define REG_WR16(sc, reg, val) \

sys/dev/netif/bce/if_bcereg.h

536

bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)

sys/dev/netif/bce/if_bcereg.h

537

#define REG_RD(sc, reg) \

sys/dev/netif/bce/if_bcereg.h

538

bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)

sys/dev/netif/bce/if_bcereg.h

546

#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))

sys/dev/netif/bce/if_bcereg.h

547

#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))

sys/dev/netif/bfe/if_bfe.c

1007

bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)

sys/dev/netif/bfe/if_bfe.c

1015

(reg << BFE_MDIO_RA_SHIFT) |

sys/dev/netif/bfe/if_bfe.c

1047

u_long reg;

sys/dev/netif/bfe/if_bfe.c

1051

for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)

sys/dev/netif/bfe/if_bfe.c

1052

*val++ += CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

1054

for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)

sys/dev/netif/bfe/if_bfe.c

1055

*val++ += CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

480

bfe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/bfe/if_bfe.c

488

bfe_readphy(sc, reg, &ret);

sys/dev/netif/bfe/if_bfe.c

494

bfe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/bfe/if_bfe.c

501

bfe_writephy(sc, reg, val);

sys/dev/netif/bfe/if_bfe.c

669

u_long reg;

sys/dev/netif/bfe/if_bfe.c

672

for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)

sys/dev/netif/bfe/if_bfe.c

673

CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

674

for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)

sys/dev/netif/bfe/if_bfe.c

675

CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

965

bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,

sys/dev/netif/bfe/if_bfe.c

971

uint32_t val = CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

982

"%x to %s.\n", bit, reg,

sys/dev/netif/bfe/if_bfe.c

990

bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)

sys/dev/netif/bfe/if_bfe.c

999

(reg << BFE_MDIO_RA_SHIFT) |

sys/dev/netif/bfe/if_bfereg.h

397

#define PCI_SETBIT(dev, reg, x, s) \

sys/dev/netif/bfe/if_bfereg.h

398

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)

sys/dev/netif/bfe/if_bfereg.h

399

#define PCI_CLRBIT(dev, reg, x, s) \

sys/dev/netif/bfe/if_bfereg.h

400

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)

sys/dev/netif/bfe/if_bfereg.h

412

#define CSR_READ_4(sc, reg) \

sys/dev/netif/bfe/if_bfereg.h

413

bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg)

sys/dev/netif/bfe/if_bfereg.h

415

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/bfe/if_bfereg.h

416

bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val)

sys/dev/netif/bge/if_bge.c

5051

bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)

sys/dev/netif/bge/if_bge.c

5055

BGE_CLRBIT(sc, reg, bit);

sys/dev/netif/bge/if_bge.c

5057

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/netif/bge/if_bge.c

683

bge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/bge/if_bge.c

703

BGE_MIPHY(phy) | BGE_MIREG(reg));

sys/dev/netif/bge/if_bge.c

717

"(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);

sys/dev/netif/bge/if_bge.c

736

bge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/bge/if_bge.c

745

(reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))

sys/dev/netif/bge/if_bge.c

759

BGE_MIPHY(phy) | BGE_MIREG(reg) | val);

sys/dev/netif/bge/if_bge.c

771

"(phy %d, reg %d, val %d)\n", phy, reg, val);

sys/dev/netif/bge/if_bgereg.h

2250

#define PCI_SETBIT(dev, reg, x, s) \

sys/dev/netif/bge/if_bgereg.h

2251

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)

sys/dev/netif/bge/if_bgereg.h

2252

#define PCI_CLRBIT(dev, reg, x, s) \

sys/dev/netif/bge/if_bgereg.h

2253

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)

sys/dev/netif/bge/if_bgevar.h

74

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/bge/if_bgevar.h

75

bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)

sys/dev/netif/bge/if_bgevar.h

77

#define CSR_READ_4(sc, reg) \

sys/dev/netif/bge/if_bgevar.h

78

bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)

sys/dev/netif/bge/if_bgevar.h

80

#define BGE_SETBIT(sc, reg, x) \

sys/dev/netif/bge/if_bgevar.h

81

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

sys/dev/netif/bge/if_bgevar.h

83

#define BGE_CLRBIT(sc, reg, x) \

sys/dev/netif/bge/if_bgevar.h

84

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

sys/dev/netif/bge/if_bgevar.h

87

#define APE_WRITE_4(sc, reg, val) \

sys/dev/netif/bge/if_bgevar.h

88

bus_write_4(sc->bge_res2, reg, val)

sys/dev/netif/bge/if_bgevar.h

90

#define APE_READ_4(sc, reg) \

sys/dev/netif/bge/if_bgevar.h

91

bus_read_4(sc->bge_res2, reg)

sys/dev/netif/bge/if_bgevar.h

93

#define APE_SETBIT(sc, reg, x) \

sys/dev/netif/bge/if_bgevar.h

94

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))

sys/dev/netif/bge/if_bgevar.h

95

#define APE_CLRBIT(sc, reg, x) \

sys/dev/netif/bge/if_bgevar.h

96

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))

sys/dev/netif/bnx/if_bnx.c

478

bnx_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/bnx/if_bnx.c

498

BGE_MIPHY(phy) | BGE_MIREG(reg));

sys/dev/netif/bnx/if_bnx.c

5072

bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)

sys/dev/netif/bnx/if_bnx.c

5076

BNX_CLRBIT(sc, reg, bit);

sys/dev/netif/bnx/if_bnx.c

5078

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/netif/bnx/if_bnx.c

512

"(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);

sys/dev/netif/bnx/if_bnx.c

531

bnx_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/bnx/if_bnx.c

550

BGE_MIPHY(phy) | BGE_MIREG(reg) | val);

sys/dev/netif/bnx/if_bnx.c

562

"(phy %d, reg %d, val %d)\n", phy, reg, val);

sys/dev/netif/bnx/if_bnxvar.h

74

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/bnx/if_bnxvar.h

75

bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)

sys/dev/netif/bnx/if_bnxvar.h

77

#define CSR_READ_4(sc, reg) \

sys/dev/netif/bnx/if_bnxvar.h

78

bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)

sys/dev/netif/bnx/if_bnxvar.h

80

#define BNX_SETBIT(sc, reg, x) \

sys/dev/netif/bnx/if_bnxvar.h

81

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

sys/dev/netif/bnx/if_bnxvar.h

83

#define BNX_CLRBIT(sc, reg, x) \

sys/dev/netif/bnx/if_bnxvar.h

84

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

sys/dev/netif/bnx/if_bnxvar.h

87

#define APE_WRITE_4(sc, reg, val) \

sys/dev/netif/bnx/if_bnxvar.h

88

bus_write_4(sc->bnx_res2, reg, val)

sys/dev/netif/bnx/if_bnxvar.h

90

#define APE_READ_4(sc, reg) \

sys/dev/netif/bnx/if_bnxvar.h

91

bus_read_4(sc->bnx_res2, reg)

sys/dev/netif/bnx/if_bnxvar.h

93

#define APE_SETBIT(sc, reg, x) \

sys/dev/netif/bnx/if_bnxvar.h

94

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))

sys/dev/netif/bnx/if_bnxvar.h

95

#define APE_CLRBIT(sc, reg, x) \

sys/dev/netif/bnx/if_bnxvar.h

96

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))

sys/dev/netif/bwn/bwn/if_bwn.c

562

int error, i, msic, reg;

sys/dev/netif/bwn/bwn/if_bwn.c

633

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/netif/bwn/bwn/if_bwn.c

6778

uint16_t reg;

sys/dev/netif/bwn/bwn/if_bwn.c

6781

reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG);

sys/dev/netif/bwn/bwn/if_bwn.c

6782

if (reg) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1219

radio0, radio1, radio2, reg0, reg1, reg2, radio78, reg, index;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1287

reg = BWN_RF_READ(mac, 0x60);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1288

index = (reg & 0x001e) >> 1;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1289

rcc = (((rcc_table[index] << 1) | (reg & 0x0001)) | 0x0020);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1990

uint16_t reg, v, padmix;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1995

reg = 0x43;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

1998

reg = 0x52;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2003

reg = 0x43;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2007

reg = 0x52;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2017

return (reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2026

uint16_t reg, mask;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2078

reg = bwn_lo_txctl_regtable(mac, &mask, NULL);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2080

BWN_RF_MASK(mac, reg, mask);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2525

uint16_t pad, reg, value;

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2531

reg = bwn_lo_txctl_regtable(mac, &value, &pad);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

2533

BWN_RF_SETMASK(mac, reg, ~value, (rfatt->padmix ? value :0));

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3373

bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3410

if (reg == BWN_PHY_RFOVER) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3412

} else if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3428

if (reg == BWN_PHY_RFOVER)

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3430

if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3454

if (reg == BWN_PHY_RFOVER) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3456

} else if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3472

if (reg == BWN_PHY_RFOVER) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

3474

} else if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

492

bwn_phy_g_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

495

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

500

bwn_phy_g_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

503

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

508

bwn_phy_g_rf_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

511

KASSERT(reg != 1, ("%s:%d: fail", __func__, __LINE__));

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

512

BWN_WRITE_2(mac, BWN_RFCTL, reg | 0x80);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

517

bwn_phy_g_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

520

KASSERT(reg != 1, ("%s:%d: fail", __func__, __LINE__));

sys/dev/netif/bwn/bwn/if_bwn_phy_g.c

521

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.h

41

extern uint16_t bwn_phy_g_read(struct bwn_mac *mac, uint16_t reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.h

42

extern void bwn_phy_g_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.h

43

extern uint16_t bwn_phy_g_rf_read(struct bwn_mac *mac, uint16_t reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_g.h

44

extern void bwn_phy_g_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

1274

uint16_t reg;

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

1323

BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

1610

BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

1710

BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

1713

BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

1726

BWN_RF_WRITE(mac, v2[i].reg, v2[i].value);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

487

bwn_phy_lp_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

490

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

495

bwn_phy_lp_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

498

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

503

bwn_phy_lp_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask,

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

507

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

513

bwn_phy_lp_rf_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

516

KASSERT(reg != 1, ("unaccessible register %d", reg));

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

517

if (mac->mac_phy.rev < 2 && reg != 0x4001)

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

518

reg |= 0x100;

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

520

reg |= 0x200;

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

521

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

526

bwn_phy_lp_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

529

KASSERT(reg != 1, ("unaccessible register %d", reg));

sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c

530

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/netif/bwn/bwn/if_bwnreg.h

471

#define BWN_PHY_CCK(reg) ((reg) | BWN_PHYROUTE_BASE)

sys/dev/netif/bwn/bwn/if_bwnreg.h

472

#define BWN_PHY_N(reg) ((reg) | BWN_PHYROUTE_BASE) /* PHY-N */

sys/dev/netif/bwn/bwn/if_bwnreg.h

473

#define BWN_PHY_N_BMODE(reg) ((reg) | BWN_PHYROUTE_N_BMODE)

sys/dev/netif/bwn/bwn/if_bwnreg.h

474

#define BWN_PHY_OFDM(reg) ((reg) | BWN_PHYROUTE_OFDM_GPHY)

sys/dev/netif/bwn/bwn/if_bwnreg.h

475

#define BWN_PHY_EXTG(reg) ((reg) | BWN_PHYROUTE_EXT_GPHY)

sys/dev/netif/bwn/siba/siba_core.c

2939

siba_cc_set32(device_t dev, uint32_t reg, uint32_t val)

sys/dev/netif/bwn/siba/siba_core.c

2952

SIBA_CC_SET32(scc, reg, val);

sys/dev/netif/bwn/siba/siba_core.c

2956

siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask)

sys/dev/netif/bwn/siba/siba_core.c

2969

SIBA_CC_MASK32(scc, reg, mask);

sys/dev/netif/bwn/siba/siba_core.c

2973

siba_cc_read32(device_t dev, uint32_t reg)

sys/dev/netif/bwn/siba/siba_core.c

2986

return SIBA_CC_READ32(scc, reg);

sys/dev/netif/bwn/siba/siba_core.c

2990

siba_cc_write32(device_t dev, uint32_t reg, uint32_t val)

sys/dev/netif/bwn/siba/siba_core.c

3003

SIBA_CC_WRITE32(scc, reg, val);

sys/dev/netif/bwn/siba/sibavar.h

102

#define siba_mips_read_2(sc, core, reg) \

sys/dev/netif/bwn/siba/sibavar.h

104

(core * SIBA_CORE_LEN) + (reg))

sys/dev/netif/bwn/siba/sibavar.h

106

#define siba_mips_read_4(sc, core, reg) \

sys/dev/netif/bwn/siba/sibavar.h

108

(core * SIBA_CORE_LEN) + (reg))

sys/dev/netif/bwn/siba/sibavar.h

110

#define siba_mips_write_2(sc, core, reg, val) \

sys/dev/netif/bwn/siba/sibavar.h

112

(core * SIBA_CORE_LEN) + (reg), (val))

sys/dev/netif/bwn/siba/sibavar.h

114

#define siba_mips_write_4(sc, core, reg, val) \

sys/dev/netif/bwn/siba/sibavar.h

116

(core * SIBA_CORE_LEN) + (reg), (val))

sys/dev/netif/bwn/siba/sibavar.h

118

#define SIBA_READ_4(siba, reg) \

sys/dev/netif/bwn/siba/sibavar.h

119

bus_space_read_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))

sys/dev/netif/bwn/siba/sibavar.h

120

#define SIBA_READ_2(siba, reg) \

sys/dev/netif/bwn/siba/sibavar.h

121

bus_space_read_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))

sys/dev/netif/bwn/siba/sibavar.h

122

#define SIBA_READ_MULTI_1(siba, reg, addr, count) \

sys/dev/netif/bwn/siba/sibavar.h

124

(reg), (addr), (count))

sys/dev/netif/bwn/siba/sibavar.h

125

#define SIBA_READ_MULTI_2(siba, reg, addr, count) \

sys/dev/netif/bwn/siba/sibavar.h

127

(reg), (addr), (count))

sys/dev/netif/bwn/siba/sibavar.h

128

#define SIBA_READ_MULTI_4(siba, reg, addr, count) \

sys/dev/netif/bwn/siba/sibavar.h

130

(reg), (addr), (count))

sys/dev/netif/bwn/siba/sibavar.h

132

#define SIBA_WRITE_4(siba, reg, val) \

sys/dev/netif/bwn/siba/sibavar.h

134

(reg), (val))

sys/dev/netif/bwn/siba/sibavar.h

135

#define SIBA_WRITE_2(siba, reg, val) \

sys/dev/netif/bwn/siba/sibavar.h

137

(reg), (val))

sys/dev/netif/bwn/siba/sibavar.h

138

#define SIBA_WRITE_MULTI_1(siba, reg, addr, count) \

sys/dev/netif/bwn/siba/sibavar.h

140

(reg), (addr), (count))

sys/dev/netif/bwn/siba/sibavar.h

141

#define SIBA_WRITE_MULTI_2(siba, reg, addr, count) \

sys/dev/netif/bwn/siba/sibavar.h

143

(reg), (addr), (count))

sys/dev/netif/bwn/siba/sibavar.h

144

#define SIBA_WRITE_MULTI_4(siba, reg, addr, count) \

sys/dev/netif/bwn/siba/sibavar.h

146

(reg), (addr), (count))

sys/dev/netif/bwn/siba/sibavar.h

152

#define SIBA_SETBITS_4(siba, reg, bits) \

sys/dev/netif/bwn/siba/sibavar.h

153

SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) | (bits))

sys/dev/netif/bwn/siba/sibavar.h

154

#define SIBA_SETBITS_2(siba, reg, bits) \

sys/dev/netif/bwn/siba/sibavar.h

155

SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) | (bits))

sys/dev/netif/bwn/siba/sibavar.h

157

#define SIBA_FILT_SETBITS_4(siba, reg, filt, bits) \

sys/dev/netif/bwn/siba/sibavar.h

158

SIBA_WRITE_4((siba), (reg), (SIBA_READ_4((siba), \

sys/dev/netif/bwn/siba/sibavar.h

159

(reg)) & (filt)) | (bits))

sys/dev/netif/bwn/siba/sibavar.h

160

#define SIBA_FILT_SETBITS_2(siba, reg, filt, bits) \

sys/dev/netif/bwn/siba/sibavar.h

161

SIBA_WRITE_2((siba), (reg), (SIBA_READ_2((siba), \

sys/dev/netif/bwn/siba/sibavar.h

162

(reg)) & (filt)) | (bits))

sys/dev/netif/bwn/siba/sibavar.h

164

#define SIBA_CLRBITS_4(siba, reg, bits) \

sys/dev/netif/bwn/siba/sibavar.h

165

SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) & ~(bits))

sys/dev/netif/bwn/siba/sibavar.h

166

#define SIBA_CLRBITS_2(siba, reg, bits) \

sys/dev/netif/bwn/siba/sibavar.h

167

SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits))

sys/dev/netif/dc/if_dc.c

1645

u_int32_t reg;

sys/dev/netif/dc/if_dc.c

1659

reg = (p[0] | (p[1] << 8)) << 16;

sys/dev/netif/dc/if_dc.c

1660

CSR_WRITE_4(sc, DC_WATCHDOG, reg);

sys/dev/netif/dc/if_dc.c

1664

reg = (p[0] | (p[1] << 8)) << 16;

sys/dev/netif/dc/if_dc.c

1665

CSR_WRITE_4(sc, DC_WATCHDOG, reg);

sys/dev/netif/dc/if_dc.c

327

#define DC_SETBIT(sc, reg, x) \

sys/dev/netif/dc/if_dc.c

328

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/dc/if_dc.c

330

#define DC_CLRBIT(sc, reg, x) \

sys/dev/netif/dc/if_dc.c

331

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/dc/if_dc.c

764

dc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/dc/if_dc.c

795

switch(reg) {

sys/dev/netif/dc/if_dc.c

823

(phy << 23) | (reg << 18));

sys/dev/netif/dc/if_dc.c

836

switch(reg) {

sys/dev/netif/dc/if_dc.c

860

"phy_read: bad phy register %x\n", reg);

sys/dev/netif/dc/if_dc.c

873

frame.mii_regaddr = reg;

sys/dev/netif/dc/if_dc.c

886

dc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/dc/if_dc.c

903

(phy << 23) | (reg << 10) | data);

sys/dev/netif/dc/if_dc.c

912

switch(reg) {

sys/dev/netif/dc/if_dc.c

936

"phy_write: bad phy register %x\n", reg);

sys/dev/netif/dc/if_dc.c

946

frame.mii_regaddr = reg;

sys/dev/netif/dc/if_dcreg.h

756

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/dc/if_dcreg.h

757

bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)

sys/dev/netif/dc/if_dcreg.h

759

#define CSR_READ_4(sc, reg) \

sys/dev/netif/dc/if_dcreg.h

760

bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)

sys/dev/netif/em/if_em.c

3068

uint32_t reg;

sys/dev/netif/em/if_em.c

3070

reg = E1000_READ_REG(&adapter->hw, E1000_IOSFPC);

sys/dev/netif/em/if_em.c

3071

reg |= E1000_RCTL_RDMTS_HEX;

sys/dev/netif/em/if_em.c

3072

E1000_WRITE_REG(&adapter->hw, E1000_IOSFPC, reg);

sys/dev/netif/em/if_em.c

3073

reg = E1000_READ_REG(&adapter->hw, E1000_TARC(0));

sys/dev/netif/em/if_em.c

3074

reg |= E1000_TARC0_CB_MULTIQ_3_REQ;

sys/dev/netif/em/if_em.c

3075

E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), reg);

sys/dev/netif/em/if_em.c

4500

uint8_t pcie_ptr, reg;

sys/dev/netif/em/if_em.c

4547

reg = pcie_ptr + PCIER_LINKCTRL;

sys/dev/netif/em/if_em.c

4548

link_ctrl = pci_read_config(dev, reg, 2);

sys/dev/netif/em/if_em.c

4550

pci_write_config(dev, reg, link_ctrl, 2);

sys/dev/netif/emx/if_emx.c

2581

uint32_t reg;

sys/dev/netif/emx/if_emx.c

2583

reg = E1000_READ_REG(&sc->hw, E1000_IOSFPC);

sys/dev/netif/emx/if_emx.c

2584

reg |= E1000_RCTL_RDMTS_HEX;

sys/dev/netif/emx/if_emx.c

2585

E1000_WRITE_REG(&sc->hw, E1000_IOSFPC, reg);

sys/dev/netif/emx/if_emx.c

2586

reg = E1000_READ_REG(&sc->hw, E1000_TARC(0));

sys/dev/netif/emx/if_emx.c

2587

reg |= E1000_TARC0_CB_MULTIQ_3_REQ;

sys/dev/netif/emx/if_emx.c

2588

E1000_WRITE_REG(&sc->hw, E1000_TARC(0), reg);

sys/dev/netif/emx/if_emx.c

4296

uint8_t pcie_ptr, reg;

sys/dev/netif/emx/if_emx.c

4339

reg = pcie_ptr + PCIER_LINKCTRL;

sys/dev/netif/emx/if_emx.c

4340

link_ctrl = pci_read_config(dev, reg, 2);

sys/dev/netif/emx/if_emx.c

4342

pci_write_config(dev, reg, link_ctrl, 2);

sys/dev/netif/et/if_et.c

434

et_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/et/if_et.c

444

__SHIFTIN(reg, ET_MII_ADDR_REG);

sys/dev/netif/et/if_et.c

460

"read phy %d, reg %d timed out\n", phy, reg);

sys/dev/netif/et/if_et.c

477

et_miibus_writereg(device_t dev, int phy, int reg, int val0)

sys/dev/netif/et/if_et.c

487

__SHIFTIN(reg, ET_MII_ADDR_REG);

sys/dev/netif/et/if_et.c

503

"write phy %d, reg %d timed out\n", phy, reg);

sys/dev/netif/et/if_et.c

504

et_miibus_readreg(dev, phy, reg);

sys/dev/netif/et/if_etvar.h

64

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/et/if_etvar.h

65

bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/netif/et/if_etvar.h

66

#define CSR_READ_4(sc, reg) \

sys/dev/netif/et/if_etvar.h

67

bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/netif/fxp/if_fxp.c

2013

fxp_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/fxp/if_fxp.c

2020

(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));

sys/dev/netif/fxp/if_fxp.c

2033

fxp_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/netif/fxp/if_fxp.c

2039

(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |

sys/dev/netif/fxp/if_fxp.c

231

static int fxp_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/netif/fxp/if_fxp.c

232

static void fxp_miibus_writereg(device_t dev, int phy, int reg,

sys/dev/netif/fxp/if_fxp.c

864

u_int16_t reg;

sys/dev/netif/fxp/if_fxp.c

872

reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;

sys/dev/netif/fxp/if_fxp.c

874

reg = FXP_EEPROM_EECS;

sys/dev/netif/fxp/if_fxp.c

875

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/netif/fxp/if_fxp.c

877

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/netif/fxp/if_fxp.c

879

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/netif/fxp/if_fxp.c

894

u_int16_t reg, data;

sys/dev/netif/fxp/if_fxp.c

908

reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;

sys/dev/netif/fxp/if_fxp.c

910

reg = FXP_EEPROM_EECS;

sys/dev/netif/fxp/if_fxp.c

911

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/netif/fxp/if_fxp.c

913

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/netif/fxp/if_fxp.c

915

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/netif/fxp/if_fxp.c

917

reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;

sys/dev/netif/fxp/if_fxp.c

919

if (autosize && reg == 0) {

sys/dev/netif/fxp/if_fxp.c

928

reg = FXP_EEPROM_EECS;

sys/dev/netif/fxp/if_fxp.c

930

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/netif/fxp/if_fxp.c

934

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/netif/fxp/if_fxpvar.h

145

#define CSR_READ_1(sc, reg) \

sys/dev/netif/fxp/if_fxpvar.h

146

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/fxp/if_fxpvar.h

147

#define CSR_READ_2(sc, reg) \

sys/dev/netif/fxp/if_fxpvar.h

148

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/fxp/if_fxpvar.h

149

#define CSR_READ_4(sc, reg) \

sys/dev/netif/fxp/if_fxpvar.h

150

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/fxp/if_fxpvar.h

151

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/fxp/if_fxpvar.h

152

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/fxp/if_fxpvar.h

153

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/fxp/if_fxpvar.h

154

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/fxp/if_fxpvar.h

155

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/fxp/if_fxpvar.h

156

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1001

reg = E1000_READ_REG(hw, E1000_TXDCTL(0));

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1002

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1003

E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1006

reg = E1000_READ_REG(hw, E1000_TXDCTL(1));

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1007

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1008

E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1011

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1012

reg &= ~(0xF << 27); /* 30:27 */

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1014

reg &= ~(1 << 20);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1015

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1018

reg = E1000_READ_REG(hw, E1000_TARC(1));

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1020

reg &= ~(1 << 28);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1022

reg |= (1 << 28);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1023

E1000_WRITE_REG(hw, E1000_TARC(1), reg);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1028

reg = E1000_READ_REG(hw, E1000_RFCTL);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1029

reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1030

E1000_WRITE_REG(hw, E1000_RFCTL, reg);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1045

u32 reg;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1110

reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1113

ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1117

reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1118

ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1122

ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1135

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1136

reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;

sys/dev/netif/ig_hal/e1000_80003es2lan.c

1137

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/netif/ig_hal/e1000_80003es2lan.c

996

u32 reg;

sys/dev/netif/ig_hal/e1000_82542.c

448

u32 e1000_translate_register_82542(u32 reg)

sys/dev/netif/ig_hal/e1000_82542.c

456

switch (reg) {

sys/dev/netif/ig_hal/e1000_82542.c

458

reg = 0x00040;

sys/dev/netif/ig_hal/e1000_82542.c

461

reg = 0x00108;

sys/dev/netif/ig_hal/e1000_82542.c

464

reg = 0x00110;

sys/dev/netif/ig_hal/e1000_82542.c

467

reg = 0x00114;

sys/dev/netif/ig_hal/e1000_82542.c

470

reg = 0x00118;

sys/dev/netif/ig_hal/e1000_82542.c

473

reg = 0x00120;

sys/dev/netif/ig_hal/e1000_82542.c

476

reg = 0x00128;

sys/dev/netif/ig_hal/e1000_82542.c

479

reg = 0x00138;

sys/dev/netif/ig_hal/e1000_82542.c

482

reg = 0x0013C;

sys/dev/netif/ig_hal/e1000_82542.c

485

reg = 0x00140;

sys/dev/netif/ig_hal/e1000_82542.c

488

reg = 0x00148;

sys/dev/netif/ig_hal/e1000_82542.c

491

reg = 0x00150;

sys/dev/netif/ig_hal/e1000_82542.c

494

reg = 0x00160;

sys/dev/netif/ig_hal/e1000_82542.c

497

reg = 0x00168;

sys/dev/netif/ig_hal/e1000_82542.c

500

reg = 0x00200;

sys/dev/netif/ig_hal/e1000_82542.c

503

reg = 0x00420;

sys/dev/netif/ig_hal/e1000_82542.c

506

reg = 0x00424;

sys/dev/netif/ig_hal/e1000_82542.c

509

reg = 0x00428;

sys/dev/netif/ig_hal/e1000_82542.c

512

reg = 0x00430;

sys/dev/netif/ig_hal/e1000_82542.c

515

reg = 0x00438;

sys/dev/netif/ig_hal/e1000_82542.c

518

reg = 0x00440;

sys/dev/netif/ig_hal/e1000_82542.c

521

reg = 0x00600;

sys/dev/netif/ig_hal/e1000_82542.c

524

reg = 0x08010;

sys/dev/netif/ig_hal/e1000_82542.c

527

reg = 0x08018;

sys/dev/netif/ig_hal/e1000_82542.c

533

return reg;

sys/dev/netif/ig_hal/e1000_82571.c

1266

u32 reg;

sys/dev/netif/ig_hal/e1000_82571.c

1271

reg = E1000_READ_REG(hw, E1000_TXDCTL(0));

sys/dev/netif/ig_hal/e1000_82571.c

1272

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_82571.c

1273

E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);

sys/dev/netif/ig_hal/e1000_82571.c

1276

reg = E1000_READ_REG(hw, E1000_TXDCTL(1));

sys/dev/netif/ig_hal/e1000_82571.c

1277

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_82571.c

1278

E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);

sys/dev/netif/ig_hal/e1000_82571.c

1281

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/netif/ig_hal/e1000_82571.c

1282

reg &= ~(0xF << 27); /* 30:27 */

sys/dev/netif/ig_hal/e1000_82571.c

1286

reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);

sys/dev/netif/ig_hal/e1000_82571.c

1290

reg |= (1 << 26);

sys/dev/netif/ig_hal/e1000_82571.c

1295

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/netif/ig_hal/e1000_82571.c

1298

reg = E1000_READ_REG(hw, E1000_TARC(1));

sys/dev/netif/ig_hal/e1000_82571.c

1302

reg &= ~((1 << 29) | (1 << 30));

sys/dev/netif/ig_hal/e1000_82571.c

1303

reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);

sys/dev/netif/ig_hal/e1000_82571.c

1305

reg &= ~(1 << 28);

sys/dev/netif/ig_hal/e1000_82571.c

1307

reg |= (1 << 28);

sys/dev/netif/ig_hal/e1000_82571.c

1308

E1000_WRITE_REG(hw, E1000_TARC(1), reg);

sys/dev/netif/ig_hal/e1000_82571.c

1319

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_82571.c

1320

reg &= ~(1 << 29);

sys/dev/netif/ig_hal/e1000_82571.c

1321

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/netif/ig_hal/e1000_82571.c

1332

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/netif/ig_hal/e1000_82571.c

1333

reg &= ~(1 << 23);

sys/dev/netif/ig_hal/e1000_82571.c

1334

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_82571.c

1335

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/netif/ig_hal/e1000_82571.c

1342

reg = E1000_READ_REG(hw, E1000_PBA_ECC);

sys/dev/netif/ig_hal/e1000_82571.c

1343

reg |= E1000_PBA_ECC_CORR_EN;

sys/dev/netif/ig_hal/e1000_82571.c

1344

E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);

sys/dev/netif/ig_hal/e1000_82571.c

1352

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/netif/ig_hal/e1000_82571.c

1353

reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;

sys/dev/netif/ig_hal/e1000_82571.c

1354

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/netif/ig_hal/e1000_82571.c

1361

reg = E1000_READ_REG(hw, E1000_RFCTL);

sys/dev/netif/ig_hal/e1000_82571.c

1362

reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

sys/dev/netif/ig_hal/e1000_82571.c

1363

E1000_WRITE_REG(hw, E1000_RFCTL, reg);

sys/dev/netif/ig_hal/e1000_82571.c

1370

reg = E1000_READ_REG(hw, E1000_GCR);

sys/dev/netif/ig_hal/e1000_82571.c

1371

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_82571.c

1372

E1000_WRITE_REG(hw, E1000_GCR, reg);

sys/dev/netif/ig_hal/e1000_82571.c

1380

reg = E1000_READ_REG(hw, E1000_GCR2);

sys/dev/netif/ig_hal/e1000_82571.c

1381

reg |= 1;

sys/dev/netif/ig_hal/e1000_82571.c

1382

E1000_WRITE_REG(hw, E1000_GCR2, reg);

sys/dev/netif/ig_hal/e1000_82575.c

1295

u32 reg;

sys/dev/netif/ig_hal/e1000_82575.c

1304

reg = E1000_READ_REG(hw, E1000_PCS_CFG0);

sys/dev/netif/ig_hal/e1000_82575.c

1305

reg |= E1000_PCS_CFG_PCS_EN;

sys/dev/netif/ig_hal/e1000_82575.c

1306

E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);

sys/dev/netif/ig_hal/e1000_82575.c

1309

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/netif/ig_hal/e1000_82575.c

1310

reg &= ~E1000_CTRL_EXT_SDP3_DATA;

sys/dev/netif/ig_hal/e1000_82575.c

1311

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/netif/ig_hal/e1000_82575.c

134

u32 reg = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1393

u32 reg;

sys/dev/netif/ig_hal/e1000_82575.c

1403

reg = E1000_READ_REG(hw, E1000_PCS_CFG0);

sys/dev/netif/ig_hal/e1000_82575.c

1404

reg &= ~E1000_PCS_CFG_PCS_EN;

sys/dev/netif/ig_hal/e1000_82575.c

1405

E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);

sys/dev/netif/ig_hal/e1000_82575.c

1408

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/netif/ig_hal/e1000_82575.c

1409

reg |= E1000_CTRL_EXT_SDP3_DATA;

sys/dev/netif/ig_hal/e1000_82575.c

1410

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/netif/ig_hal/e1000_82575.c

142

reg = E1000_READ_REG(hw, E1000_MDIC);

sys/dev/netif/ig_hal/e1000_82575.c

143

ext_mdio = !!(reg & E1000_MDIC_DEST);

sys/dev/netif/ig_hal/e1000_82575.c

150

reg = E1000_READ_REG(hw, E1000_MDICNFG);

sys/dev/netif/ig_hal/e1000_82575.c

151

ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);

sys/dev/netif/ig_hal/e1000_82575.c

1635

u32 ctrl_ext, ctrl_reg, reg, anadv_reg;

sys/dev/netif/ig_hal/e1000_82575.c

1666

reg = E1000_READ_REG(hw, E1000_PCS_LCTL);

sys/dev/netif/ig_hal/e1000_82575.c

1676

reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);

sys/dev/netif/ig_hal/e1000_82575.c

1704

reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;

sys/dev/netif/ig_hal/e1000_82575.c

1716

reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |

sys/dev/netif/ig_hal/e1000_82575.c

1721

reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */

sys/dev/netif/ig_hal/e1000_82575.c

1725

reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;

sys/dev/netif/ig_hal/e1000_82575.c

1746

DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);

sys/dev/netif/ig_hal/e1000_82575.c

1749

reg |= E1000_PCS_LCTL_FSD; /* Force Speed */

sys/dev/netif/ig_hal/e1000_82575.c

1752

reg |= E1000_PCS_LCTL_FORCE_FCTRL;

sys/dev/netif/ig_hal/e1000_82575.c

1754

DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);

sys/dev/netif/ig_hal/e1000_82575.c

1757

E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);

sys/dev/netif/ig_hal/e1000_api.c

1352

s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,

sys/dev/netif/ig_hal/e1000_api.c

1355

return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);

sys/dev/netif/ig_hal/e1000_api.h

119

u32 e1000_translate_register_82542(u32 reg);

sys/dev/netif/ig_hal/e1000_api.h

89

s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,

sys/dev/netif/ig_hal/e1000_defines.h

1400

#define GG82563_REG(page, reg) \

sys/dev/netif/ig_hal/e1000_defines.h

1401

(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))

sys/dev/netif/ig_hal/e1000_hw.h

1063

s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

1064

s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

1065

void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_hw.h

1066

void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/ig_hal/e1000_i210.c

749

u32 i, reg;

sys/dev/netif/ig_hal/e1000_i210.c

754

reg = E1000_READ_REG(hw, E1000_EECD);

sys/dev/netif/ig_hal/e1000_i210.c

755

if (reg & E1000_EECD_FLUDONE_I210) {

sys/dev/netif/ig_hal/e1000_ich8lan.c

1011

u16 reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1020

&reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1027

reg &

sys/dev/netif/ig_hal/e1000_ich8lan.c

1040

reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1052

ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1057

reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1061

reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1067

reg |= 50 <<

sys/dev/netif/ig_hal/e1000_ich8lan.c

1074

ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1117

u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |

sys/dev/netif/ig_hal/e1000_ich8lan.c

1195

reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1196

E1000_WRITE_REG(hw, E1000_LTRV, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1199

reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1200

reg |= obff_hwm;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1201

E1000_WRITE_REG(hw, E1000_SVT, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1204

reg = E1000_READ_REG(hw, E1000_SVCR);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1205

reg |= E1000_SVCR_OFF_EN;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1210

reg |= E1000_SVCR_OFF_MASKINT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

1211

E1000_WRITE_REG(hw, E1000_SVCR, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

2474

u32 reg = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2498

reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);

sys/dev/netif/ig_hal/e1000_ich8lan.c

2499

reg |= E1000_CTRL_FRCSPD;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2500

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3078

u16 reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3106

hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3107

reg &= ~BM_WUC_HOST_WU_BIT;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3108

hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

4943

u32 ctrl, reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5030

reg = E1000_READ_REG(hw, E1000_FEXTNVM3);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5031

reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5032

reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5033

E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5056

reg = E1000_READ_REG(hw, E1000_KABGTXD);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5057

reg |= E1000_KABGTXD_BGSQLBIAS;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5058

E1000_WRITE_REG(hw, E1000_KABGTXD, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5162

u32 reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5167

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5168

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5171

reg |= E1000_CTRL_EXT_PHYPDEN;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5172

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5175

reg = E1000_READ_REG(hw, E1000_TXDCTL(0));

sys/dev/netif/ig_hal/e1000_ich8lan.c

5176

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5177

E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5180

reg = E1000_READ_REG(hw, E1000_TXDCTL(1));

sys/dev/netif/ig_hal/e1000_ich8lan.c

5181

reg |= (1 << 22);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5182

E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5185

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/netif/ig_hal/e1000_ich8lan.c

5187

reg |= (1 << 28) | (1 << 29);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5188

reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5189

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5192

reg = E1000_READ_REG(hw, E1000_TARC(1));

sys/dev/netif/ig_hal/e1000_ich8lan.c

5194

reg &= ~(1 << 28);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5196

reg |= (1 << 28);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5197

reg |= (1 << 24) | (1 << 26) | (1 << 30);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5198

E1000_WRITE_REG(hw, E1000_TARC(1), reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5202

reg = E1000_READ_REG(hw, E1000_STATUS);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5203

reg &= ~(1 << 31);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5204

E1000_WRITE_REG(hw, E1000_STATUS, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5210

reg = E1000_READ_REG(hw, E1000_RFCTL);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5211

reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5217

reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5218

E1000_WRITE_REG(hw, E1000_RFCTL, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5222

reg = E1000_READ_REG(hw, E1000_PBECCSTS);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5223

reg |= E1000_PBECCSTS_ECC_ENABLE;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5224

E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5226

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5227

reg |= E1000_CTRL_MEHE;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5228

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5543

u32 reg;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5555

reg = E1000_READ_REG(hw, E1000_PHY_CTRL);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5556

reg |= (E1000_PHY_CTRL_GBE_DISABLE |

sys/dev/netif/ig_hal/e1000_ich8lan.c

5558

E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5579

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/ig_hal/e1000_ich8lan.c

5580

E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);

sys/dev/netif/ig_hal/e1000_ich8lan.h

135

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

sys/dev/netif/ig_hal/e1000_ich8lan.h

136

((reg) & MAX_PHY_REG_ADDRESS))

sys/dev/netif/ig_hal/e1000_mac.c

2235

s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,

sys/dev/netif/ig_hal/e1000_mac.c

2244

E1000_WRITE_REG(hw, reg, regvalue);

sys/dev/netif/ig_hal/e1000_mac.c

2249

regvalue = E1000_READ_REG(hw, reg);

sys/dev/netif/ig_hal/e1000_mac.c

2254

DEBUGOUT1("Reg %08x did not indicate ready\n", reg);

sys/dev/netif/ig_hal/e1000_mac.c

288

u32 reg;

sys/dev/netif/ig_hal/e1000_mac.c

293

reg = E1000_READ_REG(hw, E1000_STATUS);

sys/dev/netif/ig_hal/e1000_mac.c

294

bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

sys/dev/netif/ig_hal/e1000_mac.h

80

s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,

sys/dev/netif/ig_hal/e1000_nvm.c

241

u32 i, reg = 0;

sys/dev/netif/ig_hal/e1000_nvm.c

247

reg = E1000_READ_REG(hw, E1000_EERD);

sys/dev/netif/ig_hal/e1000_nvm.c

249

reg = E1000_READ_REG(hw, E1000_EEWR);

sys/dev/netif/ig_hal/e1000_nvm.c

251

if (reg & E1000_NVM_RW_REG_DONE)

sys/dev/netif/ig_hal/e1000_osdep.c

101

e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/netif/ig_hal/e1000_osdep.c

110

pci_write_config(dev, pcie_ptr + reg, *value, 2);

sys/dev/netif/ig_hal/e1000_osdep.c

58

e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/netif/ig_hal/e1000_osdep.c

60

pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2);

sys/dev/netif/ig_hal/e1000_osdep.c

64

e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/netif/ig_hal/e1000_osdep.c

66

*value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);

sys/dev/netif/ig_hal/e1000_osdep.c

87

e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/netif/ig_hal/e1000_osdep.c

96

*value = pci_read_config(dev, pcie_ptr + reg, 2);

sys/dev/netif/ig_hal/e1000_osdep.h

110

#define E1000_READ_REG(hw, reg) \

sys/dev/netif/ig_hal/e1000_osdep.h

113

E1000_REGISTER(hw, reg))

sys/dev/netif/ig_hal/e1000_osdep.h

115

#define E1000_WRITE_REG(hw, reg, value) \

sys/dev/netif/ig_hal/e1000_osdep.h

118

E1000_REGISTER(hw, reg), value)

sys/dev/netif/ig_hal/e1000_osdep.h

120

#define E1000_READ_REG_ARRAY(hw, reg, index) \

sys/dev/netif/ig_hal/e1000_osdep.h

123

E1000_REGISTER(hw, reg) + ((index)<< 2))

sys/dev/netif/ig_hal/e1000_osdep.h

125

#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \

sys/dev/netif/ig_hal/e1000_osdep.h

128

E1000_REGISTER(hw, reg) + ((index)<< 2), value)

sys/dev/netif/ig_hal/e1000_osdep.h

133

#define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \

sys/dev/netif/ig_hal/e1000_osdep.h

136

E1000_REGISTER(hw, reg) + index)

sys/dev/netif/ig_hal/e1000_osdep.h

138

#define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \

sys/dev/netif/ig_hal/e1000_osdep.h

141

E1000_REGISTER(hw, reg) + index, value)

sys/dev/netif/ig_hal/e1000_osdep.h

143

#define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \

sys/dev/netif/ig_hal/e1000_osdep.h

146

E1000_REGISTER(hw, reg) + (index << 1), value)

sys/dev/netif/ig_hal/e1000_osdep.h

148

#define E1000_WRITE_REG_IO(hw, reg, value) do {\

sys/dev/netif/ig_hal/e1000_osdep.h

151

(hw)->io_base, reg); \

sys/dev/netif/ig_hal/e1000_osdep.h

156

#define E1000_READ_FLASH_REG(hw, reg) \

sys/dev/netif/ig_hal/e1000_osdep.h

158

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)

sys/dev/netif/ig_hal/e1000_osdep.h

160

#define E1000_READ_FLASH_REG16(hw, reg) \

sys/dev/netif/ig_hal/e1000_osdep.h

162

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)

sys/dev/netif/ig_hal/e1000_osdep.h

164

#define E1000_WRITE_FLASH_REG(hw, reg, value) \

sys/dev/netif/ig_hal/e1000_osdep.h

166

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)

sys/dev/netif/ig_hal/e1000_osdep.h

168

#define E1000_WRITE_FLASH_REG16(hw, reg, value) \

sys/dev/netif/ig_hal/e1000_osdep.h

170

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)

sys/dev/netif/ig_hal/e1000_osdep.h

93

#define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \

sys/dev/netif/ig_hal/e1000_osdep.h

94

? reg : e1000_translate_register_82542(reg))

sys/dev/netif/ig_hal/e1000_phy.c

3099

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)

sys/dev/netif/ig_hal/e1000_phy.c

3103

if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))

sys/dev/netif/ig_hal/e1000_phy.c

3439

u16 reg = BM_PHY_REG_NUM(offset);

sys/dev/netif/ig_hal/e1000_phy.c

3460

DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);

sys/dev/netif/ig_hal/e1000_phy.c

3463

ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);

sys/dev/netif/ig_hal/e1000_phy.c

3480

DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);

sys/dev/netif/ig_hal/e1000_phy.c

3544

u16 reg = BM_PHY_REG_NUM(offset);

sys/dev/netif/ig_hal/e1000_phy.c

3571

if (reg > MAX_PHY_MULTI_PAGE_REG) {

sys/dev/netif/ig_hal/e1000_phy.c

3584

page << IGP_PAGE_SHIFT, reg);

sys/dev/netif/ig_hal/e1000_phy.c

3586

ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,

sys/dev/netif/ig_hal/e1000_phy.c

3654

u16 reg = BM_PHY_REG_NUM(offset);

sys/dev/netif/ig_hal/e1000_phy.c

3687

!(MAX_PHY_REG_ADDRESS & reg) &&

sys/dev/netif/ig_hal/e1000_phy.c

3697

if (reg > MAX_PHY_MULTI_PAGE_REG) {

sys/dev/netif/ig_hal/e1000_phy.c

3710

page << IGP_PAGE_SHIFT, reg);

sys/dev/netif/ig_hal/e1000_phy.c

3712

ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,

sys/dev/netif/ig_hal/e1000_phy.h

149

#define BM_PHY_REG(page, reg) \

sys/dev/netif/ig_hal/e1000_phy.h

150

(((reg) & MAX_PHY_REG_ADDRESS) |\

sys/dev/netif/ig_hal/e1000_phy.h

152

(((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))

sys/dev/netif/ig_hal/e1000_vf.h

292

s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/netif/igb/if_igb.c

1225

uint32_t reg;

sys/dev/netif/igb/if_igb.c

1232

reg = E1000_READ_REG(hw, E1000_RCTL);

sys/dev/netif/igb/if_igb.c

1234

reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);

sys/dev/netif/igb/if_igb.c

1235

E1000_WRITE_REG(hw, E1000_RCTL, reg);

sys/dev/netif/igb/if_igb.c

1237

reg |= E1000_RCTL_MPE;

sys/dev/netif/igb/if_igb.c

1238

reg &= ~E1000_RCTL_UPE;

sys/dev/netif/igb/if_igb.c

1239

E1000_WRITE_REG(hw, E1000_RCTL, reg);

sys/dev/netif/igb/if_igb.c

1248

uint32_t reg;

sys/dev/netif/igb/if_igb.c

1255

reg = E1000_READ_REG(hw, E1000_RCTL);

sys/dev/netif/igb/if_igb.c

1256

reg &= ~E1000_RCTL_UPE;

sys/dev/netif/igb/if_igb.c

1271

reg &= ~E1000_RCTL_MPE;

sys/dev/netif/igb/if_igb.c

1272

E1000_WRITE_REG(hw, E1000_RCTL, reg);

sys/dev/netif/igb/if_igb.c

2845

uint32_t reg;

sys/dev/netif/igb/if_igb.c

2855

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/netif/igb/if_igb.c

2856

reg |= E1000_CTRL_VME;

sys/dev/netif/igb/if_igb.c

2857

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/netif/igb/if_igb.c

2862

reg = E1000_READ_REG(hw, E1000_RCTL);

sys/dev/netif/igb/if_igb.c

2863

reg &= ~E1000_RCTL_CFIEN;

sys/dev/netif/igb/if_igb.c

2864

reg |= E1000_RCTL_VFE;

sys/dev/netif/igb/if_igb.c

2865

E1000_WRITE_REG(hw, E1000_RCTL, reg);

sys/dev/netif/igb/if_igb.c

4961

uint32_t reg;

sys/dev/netif/igb/if_igb.c

4971

reg = ~E1000_DMACR_DMAC_EN;

sys/dev/netif/igb/if_igb.c

4972

E1000_WRITE_REG(hw, E1000_DMACR, reg);

sys/dev/netif/igb/if_igb.c

4985

reg = E1000_READ_REG(hw, E1000_FCRTC);

sys/dev/netif/igb/if_igb.c

4986

reg &= ~E1000_FCRTC_RTH_COAL_MASK;

sys/dev/netif/igb/if_igb.c

4987

reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)

sys/dev/netif/igb/if_igb.c

4989

E1000_WRITE_REG(hw, E1000_FCRTC, reg);

sys/dev/netif/igb/if_igb.c

4994

reg = E1000_READ_REG(hw, E1000_DMACR);

sys/dev/netif/igb/if_igb.c

4995

reg &= ~E1000_DMACR_DMACTHR_MASK;

sys/dev/netif/igb/if_igb.c

4996

reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)

sys/dev/netif/igb/if_igb.c

5000

reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);

sys/dev/netif/igb/if_igb.c

5014

reg |= ((sc->dma_coalesce * 5) >> 6);

sys/dev/netif/igb/if_igb.c

5016

reg |= (sc->dma_coalesce >> 5);

sys/dev/netif/igb/if_igb.c

5018

reg |= (sc->dma_coalesce >> 5);

sys/dev/netif/igb/if_igb.c

5021

E1000_WRITE_REG(hw, E1000_DMACR, reg);

sys/dev/netif/igb/if_igb.c

5026

reg = E1000_READ_REG(hw, E1000_DMCTLX);

sys/dev/netif/igb/if_igb.c

5028

reg |= IGB_DMCTLX_DCFLUSH_DIS;

sys/dev/netif/igb/if_igb.c

5038

reg |= 0xA;

sys/dev/netif/igb/if_igb.c

5040

reg |= 0x4;

sys/dev/netif/igb/if_igb.c

5042

reg |= 0x4;

sys/dev/netif/igb/if_igb.c

5044

E1000_WRITE_REG(hw, E1000_DMCTLX, reg);

sys/dev/netif/igb/if_igb.c

5051

reg = E1000_READ_REG(hw, E1000_PCIEMISC);

sys/dev/netif/igb/if_igb.c

5052

reg &= ~E1000_PCIEMISC_LX_DECISION;

sys/dev/netif/igb/if_igb.c

5053

E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);

sys/dev/netif/igb/if_igb.c

5055

reg = E1000_READ_REG(hw, E1000_PCIEMISC);

sys/dev/netif/igb/if_igb.c

5057

reg & ~E1000_PCIEMISC_LX_DECISION);

sys/dev/netif/igb/if_igb.h

431

#define UPDATE_VF_REG(reg, last, cur) \

sys/dev/netif/igb/if_igb.h

433

uint32_t new = E1000_READ_REG(hw, reg); \

sys/dev/netif/iwi/if_iwi.c

1316

CSR_WRITE_4(sc, data->reg, data->physaddr);

sys/dev/netif/iwi/if_iwi.c

3234

CSR_WRITE_4(sc, data->reg, data->physaddr);

sys/dev/netif/iwi/if_iwi.c

842

data->reg = IWI_CSR_RX_BASE + i * 4;

sys/dev/netif/iwi/if_iwireg.h

571

#define CSR_READ_1(sc, reg) \

sys/dev/netif/iwi/if_iwireg.h

572

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/iwi/if_iwireg.h

574

#define CSR_READ_2(sc, reg) \

sys/dev/netif/iwi/if_iwireg.h

575

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/iwi/if_iwireg.h

577

#define CSR_READ_4(sc, reg) \

sys/dev/netif/iwi/if_iwireg.h

578

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/iwi/if_iwireg.h

584

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/iwi/if_iwireg.h

585

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwi/if_iwireg.h

587

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/iwi/if_iwireg.h

588

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwi/if_iwireg.h

590

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/iwi/if_iwireg.h

591

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwi/if_iwivar.h

95

uint32_t reg;

sys/dev/netif/iwm/if_iwm.c

5981

uint16_t reg;

sys/dev/netif/iwm/if_iwm.c

5994

reg = pci_read_config(dev, PCIR_STATUS, sizeof(reg));

sys/dev/netif/iwm/if_iwm.c

5996

if (reg & PCIM_STATUS_INTxSTATE) {

sys/dev/netif/iwm/if_iwm.c

5997

reg &= ~PCIM_STATUS_INTxSTATE;

sys/dev/netif/iwm/if_iwm.c

5999

pci_write_config(dev, PCIR_STATUS, reg, sizeof(reg));

sys/dev/netif/iwm/if_iwm_pcie_trans.c

246

iwm_poll_bit(struct iwm_softc *sc, int reg,

sys/dev/netif/iwm/if_iwm_pcie_trans.c

250

if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/netif/iwm/if_iwm_pcie_trans.c

302

uint32_t reg, uint32_t bits, uint32_t mask)

sys/dev/netif/iwm/if_iwm_pcie_trans.c

308

val = iwm_read_prph(sc, reg) & mask;

sys/dev/netif/iwm/if_iwm_pcie_trans.c

310

iwm_write_prph(sc, reg, val);

sys/dev/netif/iwm/if_iwm_pcie_trans.c

316

iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/netif/iwm/if_iwm_pcie_trans.c

318

iwm_set_bits_mask_prph(sc, reg, bits, ~0);

sys/dev/netif/iwm/if_iwm_pcie_trans.c

322

iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/netif/iwm/if_iwm_pcie_trans.c

324

iwm_set_bits_mask_prph(sc, reg, 0, ~bits);

sys/dev/netif/iwm/if_iwm_pcie_trans.h

116

extern int iwm_poll_bit(struct iwm_softc *sc, int reg,

sys/dev/netif/iwm/if_iwm_pcie_trans.h

121

uint32_t reg, uint32_t bits, uint32_t mask);

sys/dev/netif/iwm/if_iwm_pcie_trans.h

122

extern void iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits);

sys/dev/netif/iwm/if_iwm_pcie_trans.h

123

extern void iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits);

sys/dev/netif/iwm/if_iwmreg.h

6954

#define IWM_READ(sc, reg) \

sys/dev/netif/iwm/if_iwmreg.h

6955

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/iwm/if_iwmreg.h

6957

#define IWM_WRITE(sc, reg, val) \

sys/dev/netif/iwm/if_iwmreg.h

6958

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwm/if_iwmreg.h

6960

#define IWM_WRITE_1(sc, reg, val) \

sys/dev/netif/iwm/if_iwmreg.h

6961

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwm/if_iwmreg.h

6963

#define IWM_SETBITS(sc, reg, mask) \

sys/dev/netif/iwm/if_iwmreg.h

6964

IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))

sys/dev/netif/iwm/if_iwmreg.h

6966

#define IWM_CLRBITS(sc, reg, mask) \

sys/dev/netif/iwm/if_iwmreg.h

6967

IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))

sys/dev/netif/iwn/if_iwn.c

6425

uint32_t reg;

sys/dev/netif/iwn/if_iwn.c

6450

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINKCTRL, 4);

sys/dev/netif/iwn/if_iwn.c

6451

if (!(reg & PCIEM_LNKCTL_ASPM_L0S)) /* L0s Entry disabled. */

sys/dev/netif/iwn/if_iwn.c

6454

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);

sys/dev/netif/iwn/if_iwn.c

6455

if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */

sys/dev/netif/iwn/if_iwn.c

8456

uint32_t reg;

sys/dev/netif/iwn/if_iwn.c

8474

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINKCTRL, 4);

sys/dev/netif/iwn/if_iwn.c

8476

if (reg & PCIEM_LNKCTL_ASPM_L1) /* L1 Entry enabled. */

sys/dev/netif/iwn/if_iwn.c

8478

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);

sys/dev/netif/iwn/if_iwn.c

8480

if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */

sys/dev/netif/iwn/if_iwnreg.h

2293

#define IWN_READ(sc, reg) \

sys/dev/netif/iwn/if_iwnreg.h

2294

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/iwn/if_iwnreg.h

2296

#define IWN_WRITE(sc, reg, val) \

sys/dev/netif/iwn/if_iwnreg.h

2297

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwn/if_iwnreg.h

2299

#define IWN_WRITE_1(sc, reg, val) \

sys/dev/netif/iwn/if_iwnreg.h

2300

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/iwn/if_iwnreg.h

2302

#define IWN_SETBITS(sc, reg, mask) \

sys/dev/netif/iwn/if_iwnreg.h

2303

IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))

sys/dev/netif/iwn/if_iwnreg.h

2305

#define IWN_CLRBITS(sc, reg, mask) \

sys/dev/netif/iwn/if_iwnreg.h

2306

IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))

sys/dev/netif/ix/if_ix.c

5384

ix_detect_fanfail(struct ix_softc *sc, uint32_t reg, boolean_t intr)

sys/dev/netif/ix/if_ix.c

5389

if (reg & mask) {

sys/dev/netif/ix/ixgbe_82598.c

1079

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_82598.c

1086

IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));

sys/dev/netif/ix/ixgbe_82598.c

1103

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_82598.c

1109

atlas_ctl = (reg << 8) | val;

sys/dev/netif/ix/ixgbe_82598.c

413

u32 reg;

sys/dev/netif/ix/ixgbe_82598.c

538

reg = hw->fc.pause_time * 0x00010001;

sys/dev/netif/ix/ixgbe_82598.c

540

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/netif/ix/ixgbe_82598.h

45

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_82598.h

46

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_82599.c

1692

#define IXGBE_WRITE_REG_BE32(a, reg, value) \

sys/dev/netif/ix/ixgbe_82599.c

1693

IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))

sys/dev/netif/ix/ixgbe_82599.c

2075

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_82599.c

2082

(reg << 8));

sys/dev/netif/ix/ixgbe_82599.c

2099

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_82599.c

2105

core_ctl = (reg << 8) | val;

sys/dev/netif/ix/ixgbe_82599.h

56

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_82599.h

57

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_api.c

1423

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_api.c

1425

return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,

sys/dev/netif/ix/ixgbe_api.c

1437

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_api.c

1439

return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,

sys/dev/netif/ix/ixgbe_api.c

1498

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/netif/ix/ixgbe_api.c

1501

reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/netif/ix/ixgbe_api.c

1513

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/netif/ix/ixgbe_api.c

1516

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/netif/ix/ixgbe_api.c

1563

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_api.c

1566

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/netif/ix/ixgbe_api.c

1578

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_api.c

1581

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/netif/ix/ixgbe_api.h

140

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_api.h

141

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_api.h

180

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/netif/ix/ixgbe_api.h

181

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/netif/ix/ixgbe_api.h

187

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/netif/ix/ixgbe_api.h

188

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/netif/ix/ixgbe_common.c

1079

u32 reg;

sys/dev/netif/ix/ixgbe_common.c

1084

reg = IXGBE_READ_REG(hw, IXGBE_STATUS);

sys/dev/netif/ix/ixgbe_common.c

1085

bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;

sys/dev/netif/ix/ixgbe_common.c

1089

reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_common.c

1090

if (reg & IXGBE_FACTPS_LFS)

sys/dev/netif/ix/ixgbe_common.c

1785

u32 reg;

sys/dev/netif/ix/ixgbe_common.c

1792

reg = IXGBE_READ_REG(hw, IXGBE_EERD);

sys/dev/netif/ix/ixgbe_common.c

1794

reg = IXGBE_READ_REG(hw, IXGBE_EEWR);

sys/dev/netif/ix/ixgbe_common.c

1796

if (reg & IXGBE_EEPROM_RW_REG_DONE) {

sys/dev/netif/ix/ixgbe_common.c

237

u32 reg = 0, reg_bp = 0;

sys/dev/netif/ix/ixgbe_common.c

274

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);

sys/dev/netif/ix/ixgbe_common.c

2814

u32 reg;

sys/dev/netif/ix/ixgbe_common.c

2926

reg = hw->fc.pause_time * 0x00010001;

sys/dev/netif/ix/ixgbe_common.c

2928

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/netif/ix/ixgbe_common.c

298

reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);

sys/dev/netif/ix/ixgbe_common.c

310

reg |= IXGBE_PCS1GANA_ASM_PAUSE;

sys/dev/netif/ix/ixgbe_common.c

311

reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;

sys/dev/netif/ix/ixgbe_common.c

332

reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;

sys/dev/netif/ix/ixgbe_common.c

352

IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);

sys/dev/netif/ix/ixgbe_common.c

353

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);

sys/dev/netif/ix/ixgbe_common.c

357

reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;

sys/dev/netif/ix/ixgbe_common.c

359

IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);

sys/dev/netif/ix/ixgbe_common.c

360

DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);

sys/dev/netif/ix/ixgbe_common.c

379

DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);

sys/dev/netif/ix/ixgbe_common.c

5213

u32 reg, i;

sys/dev/netif/ix/ixgbe_common.c

5215

reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);

sys/dev/netif/ix/ixgbe_common.c

5218

(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));

sys/dev/netif/ix/ixgbe_common.h

39

#define IXGBE_WRITE_REG64(hw, reg, value) \

sys/dev/netif/ix/ixgbe_common.h

41

IXGBE_WRITE_REG(hw, reg, (u32) value); \

sys/dev/netif/ix/ixgbe_common.h

42

IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \

sys/dev/netif/ix/ixgbe_dcb_82598.c

123

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

128

reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;

sys/dev/netif/ix/ixgbe_dcb_82598.c

129

IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

131

reg = IXGBE_READ_REG(hw, IXGBE_RMCS);

sys/dev/netif/ix/ixgbe_dcb_82598.c

133

reg &= ~IXGBE_RMCS_ARBDIS;

sys/dev/netif/ix/ixgbe_dcb_82598.c

135

reg |= IXGBE_RMCS_RRM;

sys/dev/netif/ix/ixgbe_dcb_82598.c

137

reg |= IXGBE_RMCS_DFP;

sys/dev/netif/ix/ixgbe_dcb_82598.c

139

IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

146

reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);

sys/dev/netif/ix/ixgbe_dcb_82598.c

149

reg |= IXGBE_RT2CR_LSP;

sys/dev/netif/ix/ixgbe_dcb_82598.c

151

IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

154

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/netif/ix/ixgbe_dcb_82598.c

155

reg |= IXGBE_RDRXCTL_RDMTS_1_2;

sys/dev/netif/ix/ixgbe_dcb_82598.c

156

reg |= IXGBE_RDRXCTL_MPBEN;

sys/dev/netif/ix/ixgbe_dcb_82598.c

157

reg |= IXGBE_RDRXCTL_MCEN;

sys/dev/netif/ix/ixgbe_dcb_82598.c

158

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

160

reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

sys/dev/netif/ix/ixgbe_dcb_82598.c

162

reg &= ~IXGBE_RXCTRL_DMBYPS;

sys/dev/netif/ix/ixgbe_dcb_82598.c

163

IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

182

u32 reg, max_credits;

sys/dev/netif/ix/ixgbe_dcb_82598.c

185

reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);

sys/dev/netif/ix/ixgbe_dcb_82598.c

188

reg &= ~IXGBE_DPMCS_ARBDIS;

sys/dev/netif/ix/ixgbe_dcb_82598.c

189

reg |= IXGBE_DPMCS_TSOEF;

sys/dev/netif/ix/ixgbe_dcb_82598.c

192

reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);

sys/dev/netif/ix/ixgbe_dcb_82598.c

194

IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

199

reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

200

reg |= refill[i];

sys/dev/netif/ix/ixgbe_dcb_82598.c

201

reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

204

reg |= IXGBE_TDTQ2TCCR_GSP;

sys/dev/netif/ix/ixgbe_dcb_82598.c

207

reg |= IXGBE_TDTQ2TCCR_LSP;

sys/dev/netif/ix/ixgbe_dcb_82598.c

209

IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

229

u32 reg;

sys/dev/netif/ix/ixgbe_dcb_82598.c

232

reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);

sys/dev/netif/ix/ixgbe_dcb_82598.c

234

reg &= ~IXGBE_PDPMCS_ARBDIS;

sys/dev/netif/ix/ixgbe_dcb_82598.c

236

reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);

sys/dev/netif/ix/ixgbe_dcb_82598.c

238

IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

242

reg = refill[i];

sys/dev/netif/ix/ixgbe_dcb_82598.c

243

reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

244

reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82598.c

247

reg |= IXGBE_TDPT2TCCR_GSP;

sys/dev/netif/ix/ixgbe_dcb_82598.c

250

reg |= IXGBE_TDPT2TCCR_LSP;

sys/dev/netif/ix/ixgbe_dcb_82598.c

252

IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

256

reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);

sys/dev/netif/ix/ixgbe_dcb_82598.c

257

reg |= IXGBE_DTXCTL_ENDBUBD;

sys/dev/netif/ix/ixgbe_dcb_82598.c

258

IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

272

u32 fcrtl, reg;

sys/dev/netif/ix/ixgbe_dcb_82598.c

276

reg = IXGBE_READ_REG(hw, IXGBE_RMCS);

sys/dev/netif/ix/ixgbe_dcb_82598.c

277

reg &= ~IXGBE_RMCS_TFCE_802_3X;

sys/dev/netif/ix/ixgbe_dcb_82598.c

278

reg |= IXGBE_RMCS_TFCE_PRIORITY;

sys/dev/netif/ix/ixgbe_dcb_82598.c

279

IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

282

reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);

sys/dev/netif/ix/ixgbe_dcb_82598.c

283

reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);

sys/dev/netif/ix/ixgbe_dcb_82598.c

286

reg |= IXGBE_FCTRL_RPFCE;

sys/dev/netif/ix/ixgbe_dcb_82598.c

288

IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

299

reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

sys/dev/netif/ix/ixgbe_dcb_82598.c

301

IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

305

reg = hw->fc.pause_time | (hw->fc.pause_time << 16);

sys/dev/netif/ix/ixgbe_dcb_82598.c

307

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

324

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

330

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));

sys/dev/netif/ix/ixgbe_dcb_82598.c

331

reg |= ((0x1010101) * j);

sys/dev/netif/ix/ixgbe_dcb_82598.c

332

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

333

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));

sys/dev/netif/ix/ixgbe_dcb_82598.c

334

reg |= ((0x1010101) * j);

sys/dev/netif/ix/ixgbe_dcb_82598.c

335

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);

sys/dev/netif/ix/ixgbe_dcb_82598.c

339

reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));

sys/dev/netif/ix/ixgbe_dcb_82598.c

340

reg |= ((0x1010101) * i);

sys/dev/netif/ix/ixgbe_dcb_82598.c

341

IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

125

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

134

reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;

sys/dev/netif/ix/ixgbe_dcb_82599.c

135

IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

143

reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

145

reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));

sys/dev/netif/ix/ixgbe_dcb_82599.c

147

IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

153

reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);

sys/dev/netif/ix/ixgbe_dcb_82599.c

155

reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

158

reg |= IXGBE_RTRPT4C_LSP;

sys/dev/netif/ix/ixgbe_dcb_82599.c

160

IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

167

reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;

sys/dev/netif/ix/ixgbe_dcb_82599.c

168

IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

186

u32 reg, max_credits;

sys/dev/netif/ix/ixgbe_dcb_82599.c

198

reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

199

reg |= refill[i];

sys/dev/netif/ix/ixgbe_dcb_82599.c

200

reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

203

reg |= IXGBE_RTTDT2C_GSP;

sys/dev/netif/ix/ixgbe_dcb_82599.c

206

reg |= IXGBE_RTTDT2C_LSP;

sys/dev/netif/ix/ixgbe_dcb_82599.c

208

IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

215

reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;

sys/dev/netif/ix/ixgbe_dcb_82599.c

216

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

236

u32 reg;

sys/dev/netif/ix/ixgbe_dcb_82599.c

243

reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |

sys/dev/netif/ix/ixgbe_dcb_82599.c

246

IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

254

reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

256

reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));

sys/dev/netif/ix/ixgbe_dcb_82599.c

258

IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

262

reg = refill[i];

sys/dev/netif/ix/ixgbe_dcb_82599.c

263

reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

264

reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

267

reg |= IXGBE_RTTPT2C_GSP;

sys/dev/netif/ix/ixgbe_dcb_82599.c

270

reg |= IXGBE_RTTPT2C_LSP;

sys/dev/netif/ix/ixgbe_dcb_82599.c

272

IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

279

reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |

sys/dev/netif/ix/ixgbe_dcb_82599.c

281

IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

296

u32 i, j, fcrtl, reg;

sys/dev/netif/ix/ixgbe_dcb_82599.c

303

reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);

sys/dev/netif/ix/ixgbe_dcb_82599.c

304

reg |= IXGBE_MFLCN_DPF;

sys/dev/netif/ix/ixgbe_dcb_82599.c

311

reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);

sys/dev/netif/ix/ixgbe_dcb_82599.c

314

reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;

sys/dev/netif/ix/ixgbe_dcb_82599.c

317

reg |= IXGBE_MFLCN_RPFCE;

sys/dev/netif/ix/ixgbe_dcb_82599.c

319

IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

339

reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

sys/dev/netif/ix/ixgbe_dcb_82599.c

350

reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;

sys/dev/netif/ix/ixgbe_dcb_82599.c

354

IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

363

reg = hw->fc.pause_time | (hw->fc.pause_time << 16);

sys/dev/netif/ix/ixgbe_dcb_82599.c

365

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

384

u32 reg = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

406

reg = 0x01010101 * (i / 4);

sys/dev/netif/ix/ixgbe_dcb_82599.c

407

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

420

reg = 0x00000000;

sys/dev/netif/ix/ixgbe_dcb_82599.c

422

reg = 0x01010101;

sys/dev/netif/ix/ixgbe_dcb_82599.c

424

reg = 0x02020202;

sys/dev/netif/ix/ixgbe_dcb_82599.c

426

reg = 0x03030303;

sys/dev/netif/ix/ixgbe_dcb_82599.c

428

reg = 0x04040404;

sys/dev/netif/ix/ixgbe_dcb_82599.c

430

reg = 0x05050505;

sys/dev/netif/ix/ixgbe_dcb_82599.c

432

reg = 0x06060606;

sys/dev/netif/ix/ixgbe_dcb_82599.c

434

reg = 0x07070707;

sys/dev/netif/ix/ixgbe_dcb_82599.c

435

IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

451

reg = 0x01010101 * (i / 8);

sys/dev/netif/ix/ixgbe_dcb_82599.c

452

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

465

reg = 0x00000000;

sys/dev/netif/ix/ixgbe_dcb_82599.c

467

reg = 0x01010101;

sys/dev/netif/ix/ixgbe_dcb_82599.c

469

reg = 0x02020202;

sys/dev/netif/ix/ixgbe_dcb_82599.c

471

reg = 0x03030303;

sys/dev/netif/ix/ixgbe_dcb_82599.c

472

IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

510

u32 reg;

sys/dev/netif/ix/ixgbe_dcb_82599.c

514

reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);

sys/dev/netif/ix/ixgbe_dcb_82599.c

515

reg |= IXGBE_RTTDCS_ARBDIS;

sys/dev/netif/ix/ixgbe_dcb_82599.c

516

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

518

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/netif/ix/ixgbe_dcb_82599.c

521

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/netif/ix/ixgbe_dcb_82599.c

525

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/netif/ix/ixgbe_dcb_82599.c

531

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/netif/ix/ixgbe_dcb_82599.c

540

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/netif/ix/ixgbe_dcb_82599.c

547

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/netif/ix/ixgbe_dcb_82599.c

550

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/netif/ix/ixgbe_dcb_82599.c

553

IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

557

reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;

sys/dev/netif/ix/ixgbe_dcb_82599.c

560

reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;

sys/dev/netif/ix/ixgbe_dcb_82599.c

562

reg |= IXGBE_MTQC_VT_ENA;

sys/dev/netif/ix/ixgbe_dcb_82599.c

564

IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

572

reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);

sys/dev/netif/ix/ixgbe_dcb_82599.c

573

reg &= ~IXGBE_RTTDCS_ARBDIS;

sys/dev/netif/ix/ixgbe_dcb_82599.c

574

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/netif/ix/ixgbe_dcb_82599.c

577

reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);

sys/dev/netif/ix/ixgbe_dcb_82599.c

578

reg |= IXGBE_SECTX_DCB;

sys/dev/netif/ix/ixgbe_dcb_82599.c

579

IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);

sys/dev/netif/ix/ixgbe_osdep_pf.c

104

ixgbe_write_reg_pf(struct ixgbe_hw *hw, u32 reg, u32 val)

sys/dev/netif/ix/ixgbe_osdep_pf.c

108

reg, val);

sys/dev/netif/ix/ixgbe_osdep_pf.c

112

ixgbe_read_reg_array_pf(struct ixgbe_hw *hw, u32 reg, u32 offset)

sys/dev/netif/ix/ixgbe_osdep_pf.c

116

reg + (offset << 2));

sys/dev/netif/ix/ixgbe_osdep_pf.c

120

ixgbe_write_reg_array_pf(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)

sys/dev/netif/ix/ixgbe_osdep_pf.c

124

reg + (offset << 2), val);

sys/dev/netif/ix/ixgbe_osdep_pf.c

48

ixgbe_read_pci_cfg_pf(struct ixgbe_hw *hw, u32 reg)

sys/dev/netif/ix/ixgbe_osdep_pf.c

50

return pci_read_config(((struct ix_softc *)hw->back)->dev, reg, 2);

sys/dev/netif/ix/ixgbe_osdep_pf.c

54

ixgbe_write_pci_cfg_pf(struct ixgbe_hw *hw, u32 reg, u16 value)

sys/dev/netif/ix/ixgbe_osdep_pf.c

56

pci_write_config(((struct ix_softc *)hw->back)->dev, reg, value, 2);

sys/dev/netif/ix/ixgbe_osdep_pf.c

60

ixgbe_read_reg_pf(struct ixgbe_hw *hw, u32 reg)

sys/dev/netif/ix/ixgbe_osdep_pf.c

67

sc->osdep.mem_bus_space_handle, reg);

sys/dev/netif/ix/ixgbe_osdep_pf.c

83

reg, retval);

sys/dev/netif/ix/ixgbe_osdep_pf.c

93

"Failed to read register 0x%08X.\n", reg);

sys/dev/netif/ix/ixgbe_osdep_pf.c

97

sc->osdep.mem_bus_space_handle, reg);

sys/dev/netif/ix/ixgbe_phy.c

113

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_phy.c

125

reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */

sys/dev/netif/ix/ixgbe_phy.c

126

csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);

sys/dev/netif/ix/ixgbe_phy.c

139

if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))

sys/dev/netif/ix/ixgbe_phy.c

191

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_phy.c

200

reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */

sys/dev/netif/ix/ixgbe_phy.c

201

csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);

sys/dev/netif/ix/ixgbe_phy.c

216

if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))

sys/dev/netif/ix/ixgbe_phy.c

2684

u16 reg;

sys/dev/netif/ix/ixgbe_phy.c

2691

&reg);

sys/dev/netif/ix/ixgbe_phy.c

2696

reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;

sys/dev/netif/ix/ixgbe_phy.c

2700

reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;

sys/dev/netif/ix/ixgbe_phy.c

2705

reg);

sys/dev/netif/ix/ixgbe_phy.h

215

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_phy.h

217

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_type.h

4032

s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);

sys/dev/netif/ix/ixgbe_type.h

4033

s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_type.h

4035

s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);

sys/dev/netif/ix/ixgbe_type.h

4036

s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_x540.c

737

u32 reg;

sys/dev/netif/ix/ixgbe_x540.c

743

reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));

sys/dev/netif/ix/ixgbe_x540.c

744

if (reg & IXGBE_EEC_FLUDONE) {

sys/dev/netif/ix/ixgbe_x550.c

1002

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/netif/ix/ixgbe_x550.c

1003

reg |= IXGBE_DMACR_DMAC_EN;

sys/dev/netif/ix/ixgbe_x550.c

1004

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/netif/ix/ixgbe_x550.c

114

static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)

sys/dev/netif/ix/ixgbe_x550.c

116

return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);

sys/dev/netif/ix/ixgbe_x550.c

127

static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)

sys/dev/netif/ix/ixgbe_x550.c

129

return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);

sys/dev/netif/ix/ixgbe_x550.c

1361

u32 reg;

sys/dev/netif/ix/ixgbe_x550.c

1366

reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);

sys/dev/netif/ix/ixgbe_x550.c

1367

reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);

sys/dev/netif/ix/ixgbe_x550.c

1368

IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);

sys/dev/netif/ix/ixgbe_x550.c

1371

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/netif/ix/ixgbe_x550.c

1372

reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);

sys/dev/netif/ix/ixgbe_x550.c

1373

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/netif/ix/ixgbe_x550.c

1384

u32 reg;

sys/dev/netif/ix/ixgbe_x550.c

1389

reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);

sys/dev/netif/ix/ixgbe_x550.c

1390

reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);

sys/dev/netif/ix/ixgbe_x550.c

1391

IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);

sys/dev/netif/ix/ixgbe_x550.c

1394

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/netif/ix/ixgbe_x550.c

1395

reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);

sys/dev/netif/ix/ixgbe_x550.c

1396

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/netif/ix/ixgbe_x550.c

140

static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)

sys/dev/netif/ix/ixgbe_x550.c

1408

u32 idx, reg, num_qs, start_q, bitmask;

sys/dev/netif/ix/ixgbe_x550.c

1413

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/netif/ix/ixgbe_x550.c

1414

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/netif/ix/ixgbe_x550.c

1433

reg = 0;

sys/dev/netif/ix/ixgbe_x550.c

1434

reg |= (bitmask << (start_q % 32));

sys/dev/netif/ix/ixgbe_x550.c

1435

IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);

sys/dev/netif/ix/ixgbe_x550.c

1436

IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);

sys/dev/netif/ix/ixgbe_x550.c

144

status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);

sys/dev/netif/ix/ixgbe_x550.c

1449

u32 i, j, reg, q, shift, vf, idx;

sys/dev/netif/ix/ixgbe_x550.c

1454

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/netif/ix/ixgbe_x550.c

1455

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/netif/ix/ixgbe_x550.c

159

static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)

sys/dev/netif/ix/ixgbe_x550.c

163

status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);

sys/dev/netif/ix/ixgbe_x550.c

182

u8 reg;

sys/dev/netif/ix/ixgbe_x550.c

185

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/netif/ix/ixgbe_x550.c

188

reg |= IXGBE_PE_BIT1;

sys/dev/netif/ix/ixgbe_x550.c

189

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/netif/ix/ixgbe_x550.c

193

status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);

sys/dev/netif/ix/ixgbe_x550.c

196

reg &= ~IXGBE_PE_BIT1;

sys/dev/netif/ix/ixgbe_x550.c

1961

u16 reg;

sys/dev/netif/ix/ixgbe_x550.c

1968

&reg);

sys/dev/netif/ix/ixgbe_x550.c

197

status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);

sys/dev/netif/ix/ixgbe_x550.c

1971

!(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))

sys/dev/netif/ix/ixgbe_x550.c

1977

&reg);

sys/dev/netif/ix/ixgbe_x550.c

1980

!(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |

sys/dev/netif/ix/ixgbe_x550.c

1987

&reg);

sys/dev/netif/ix/ixgbe_x550.c

1993

if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {

sys/dev/netif/ix/ixgbe_x550.c

1997

} else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {

sys/dev/netif/ix/ixgbe_x550.c

2001

&reg);

sys/dev/netif/ix/ixgbe_x550.c

2007

if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {

sys/dev/netif/ix/ixgbe_x550.c

201

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/netif/ix/ixgbe_x550.c

2016

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/netif/ix/ixgbe_x550.c

2019

!(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))

sys/dev/netif/ix/ixgbe_x550.c

2024

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/netif/ix/ixgbe_x550.c

2030

if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)

sys/dev/netif/ix/ixgbe_x550.c

204

reg &= ~IXGBE_PE_BIT1;

sys/dev/netif/ix/ixgbe_x550.c

2048

u16 reg;

sys/dev/netif/ix/ixgbe_x550.c

205

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/netif/ix/ixgbe_x550.c

2067

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/netif/ix/ixgbe_x550.c

2072

reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;

sys/dev/netif/ix/ixgbe_x550.c

2076

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);

sys/dev/netif/ix/ixgbe_x550.c

2085

&reg);

sys/dev/netif/ix/ixgbe_x550.c

2090

reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |

sys/dev/netif/ix/ixgbe_x550.c

2095

reg);

sys/dev/netif/ix/ixgbe_x550.c

2103

&reg);

sys/dev/netif/ix/ixgbe_x550.c

2108

reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |

sys/dev/netif/ix/ixgbe_x550.c

211

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/netif/ix/ixgbe_x550.c

2113

reg);

sys/dev/netif/ix/ixgbe_x550.c

2121

&reg);

sys/dev/netif/ix/ixgbe_x550.c

2126

reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;

sys/dev/netif/ix/ixgbe_x550.c

2130

reg);

sys/dev/netif/ix/ixgbe_x550.c

214

reg |= IXGBE_PE_BIT1;

sys/dev/netif/ix/ixgbe_x550.c

215

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/netif/ix/ixgbe_x550.c

2561

u16 reg;

sys/dev/netif/ix/ixgbe_x550.c

2566

&reg);

sys/dev/netif/ix/ixgbe_x550.c

2574

if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {

sys/dev/netif/ix/ixgbe_x550.c

2578

&reg);

sys/dev/netif/ix/ixgbe_x550.c

2583

reg &= ~IXGBE_MDIO_POWER_UP_STALL;

sys/dev/netif/ix/ixgbe_x550.c

2588

reg);

sys/dev/netif/ix/ixgbe_x550.c

3206

u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +

sys/dev/netif/ix/ixgbe_x550.c

3208

u32 value = IXGBE_READ_REG(hw, reg);

sys/dev/netif/ix/ixgbe_x550.c

546

u16 reg, u16 *val)

sys/dev/netif/ix/ixgbe_x550.c

548

return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);

sys/dev/netif/ix/ixgbe_x550.c

562

u16 reg, u16 *val)

sys/dev/netif/ix/ixgbe_x550.c

564

return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);

sys/dev/netif/ix/ixgbe_x550.c

577

u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_x550.c

579

return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);

sys/dev/netif/ix/ixgbe_x550.c

593

u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_x550.c

595

return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);

sys/dev/netif/ix/ixgbe_x550.c

887

u32 reg, high_pri_tc;

sys/dev/netif/ix/ixgbe_x550.c

892

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/netif/ix/ixgbe_x550.c

893

reg &= ~IXGBE_DMACR_DMAC_EN;

sys/dev/netif/ix/ixgbe_x550.c

894

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/netif/ix/ixgbe_x550.c

903

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/netif/ix/ixgbe_x550.c

906

reg &= ~IXGBE_DMACR_DMACWT_MASK;

sys/dev/netif/ix/ixgbe_x550.c

907

reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;

sys/dev/netif/ix/ixgbe_x550.c

909

reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;

sys/dev/netif/ix/ixgbe_x550.c

913

reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &

sys/dev/netif/ix/ixgbe_x550.c

916

reg |= IXGBE_DMACR_EN_MNG_IND;

sys/dev/netif/ix/ixgbe_x550.c

919

reg |= IXGBE_DMACR_DMAC_EN;

sys/dev/netif/ix/ixgbe_x550.c

920

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/netif/ix/ixgbe_x550.c

935

u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;

sys/dev/netif/ix/ixgbe_x550.c

958

reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));

sys/dev/netif/ix/ixgbe_x550.c

959

reg &= ~IXGBE_DMCTH_DMACRXT_MASK;

sys/dev/netif/ix/ixgbe_x550.c

974

reg |= (rx_pb_size > maxframe_size_kb) ?

sys/dev/netif/ix/ixgbe_x550.c

977

IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);

sys/dev/netif/ix/ixgbe_x550.c

990

u32 reg;

sys/dev/netif/ix/ixgbe_x550.c

995

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/netif/ix/ixgbe_x550.c

996

reg &= ~IXGBE_DMACR_DMAC_EN;

sys/dev/netif/ix/ixgbe_x550.c

997

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/netif/jme/if_jme.c

1981

uint32_t reg;

sys/dev/netif/jme/if_jme.c

1984

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

1985

reg &= ~RXMAC_CSUM_ENB;

sys/dev/netif/jme/if_jme.c

1987

reg |= RXMAC_CSUM_ENB;

sys/dev/netif/jme/if_jme.c

1988

CSR_WRITE_4(sc, JME_RXMAC, reg);

sys/dev/netif/jme/if_jme.c

2664

uint32_t reg;

sys/dev/netif/jme/if_jme.c

2735

reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;

sys/dev/netif/jme/if_jme.c

2736

reg |= TXMAC_THRESH_1_PKT;

sys/dev/netif/jme/if_jme.c

2737

reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;

sys/dev/netif/jme/if_jme.c

2738

CSR_WRITE_4(sc, JME_TXMAC, reg);

sys/dev/netif/jme/if_jme.c

2799

reg = CSR_READ_4(sc, JME_PMCS);

sys/dev/netif/jme/if_jme.c

2800

reg &= ~PMCS_WOL_ENB_MASK;

sys/dev/netif/jme/if_jme.c

2801

CSR_WRITE_4(sc, JME_PMCS, reg);

sys/dev/netif/jme/if_jme.c

2808

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

2809

reg |= RXMAC_PAD_10BYTES;

sys/dev/netif/jme/if_jme.c

281

jme_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/jme/if_jme.c

2812

reg |= RXMAC_CSUM_ENB;

sys/dev/netif/jme/if_jme.c

2813

CSR_WRITE_4(sc, JME_RXMAC, reg);

sys/dev/netif/jme/if_jme.c

2816

reg = CSR_READ_4(sc, JME_GPREG0);

sys/dev/netif/jme/if_jme.c

2817

reg &= ~GPREG0_PCC_UNIT_MASK;

sys/dev/netif/jme/if_jme.c

2819

reg |= GPREG0_PCC_UNIT_US;

sys/dev/netif/jme/if_jme.c

2827

reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |

sys/dev/netif/jme/if_jme.c

2832

reg &= ~GPREG0_POST_DW0_ENB;

sys/dev/netif/jme/if_jme.c

2834

reg &= ~GPREG0_PME_ENB;

sys/dev/netif/jme/if_jme.c

2836

reg &= ~GPREG0_PHY_ADDR_MASK;

sys/dev/netif/jme/if_jme.c

2837

reg |= sc->jme_phyaddr;

sys/dev/netif/jme/if_jme.c

2838

CSR_WRITE_4(sc, JME_GPREG0, reg);

sys/dev/netif/jme/if_jme.c

2963

uint32_t reg;

sys/dev/netif/jme/if_jme.c

2966

reg = CSR_READ_4(sc, JME_TXCSR);

sys/dev/netif/jme/if_jme.c

2967

if ((reg & TXCSR_TX_ENB) == 0)

sys/dev/netif/jme/if_jme.c

2969

reg &= ~TXCSR_TX_ENB;

sys/dev/netif/jme/if_jme.c

297

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/netif/jme/if_jme.c

2970

CSR_WRITE_4(sc, JME_TXCSR, reg);

sys/dev/netif/jme/if_jme.c

2983

uint32_t reg;

sys/dev/netif/jme/if_jme.c

2986

reg = CSR_READ_4(sc, JME_RXCSR);

sys/dev/netif/jme/if_jme.c

2987

if ((reg & RXCSR_RX_ENB) == 0)

sys/dev/netif/jme/if_jme.c

2989

reg &= ~RXCSR_RX_ENB;

sys/dev/netif/jme/if_jme.c

2990

CSR_WRITE_4(sc, JME_RXCSR, reg);

sys/dev/netif/jme/if_jme.c

306

"phy %d, reg %d\n", phy, reg);

sys/dev/netif/jme/if_jme.c

3103

uint32_t reg;

sys/dev/netif/jme/if_jme.c

3107

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

3108

reg &= ~RXMAC_VLAN_ENB;

sys/dev/netif/jme/if_jme.c

3110

reg |= RXMAC_VLAN_ENB;

sys/dev/netif/jme/if_jme.c

3111

CSR_WRITE_4(sc, JME_RXMAC, reg);

sys/dev/netif/jme/if_jme.c

317

jme_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/jme/if_jme.c

3293

uint32_t reg;

sys/dev/netif/jme/if_jme.c

3295

reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &

sys/dev/netif/jme/if_jme.c

3297

reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &

sys/dev/netif/jme/if_jme.c

3299

reg |= PCCTX_COAL_TXQ0;

sys/dev/netif/jme/if_jme.c

3300

CSR_WRITE_4(sc, JME_PCCTX, reg);

sys/dev/netif/jme/if_jme.c

3306

uint32_t reg;

sys/dev/netif/jme/if_jme.c

3309

reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &

sys/dev/netif/jme/if_jme.c

3311

reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &

sys/dev/netif/jme/if_jme.c

3314

CSR_WRITE_4(sc, JME_PCCRX(r), reg);

sys/dev/netif/jme/if_jme.c

333

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/netif/jme/if_jme.c

342

"phy %d, reg %d\n", phy, reg);

sys/dev/netif/jme/if_jme.c

3713

int reg, shift;

sys/dev/netif/jme/if_jme.c

3715

reg = i / JME_MSINUM_FACTOR;

sys/dev/netif/jme/if_jme.c

3716

KKASSERT(reg < JME_MSINUM_CNT);

sys/dev/netif/jme/if_jme.c

3720

sc->jme_msinum[reg] |=

sys/dev/netif/jme/if_jme.c

4055

jme_miiext_read(struct jme_softc *sc, int reg)

sys/dev/netif/jme/if_jme.c

4059

addr = JME_MII_EXT_ADDR_RD | reg;

sys/dev/netif/jme/if_jme.c

4067

jme_miiext_write(struct jme_softc *sc, int reg, int val)

sys/dev/netif/jme/if_jme.c

4071

addr = JME_MII_EXT_ADDR_WR | reg;

sys/dev/netif/jme/if_jme.c

559

uint32_t reg;

sys/dev/netif/jme/if_jme.c

564

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/netif/jme/if_jme.c

565

if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)

sys/dev/netif/jme/if_jme.c

575

reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;

sys/dev/netif/jme/if_jme.c

576

CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);

sys/dev/netif/jme/if_jme.c

579

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/netif/jme/if_jme.c

580

if ((reg & SMBINTF_CMD_TRIGGER) == 0)

sys/dev/netif/jme/if_jme.c

589

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/netif/jme/if_jme.c

590

*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;

sys/dev/netif/jme/if_jme.c

598

uint8_t fup, reg, val;

sys/dev/netif/jme/if_jme.c

615

if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)

sys/dev/netif/jme/if_jme.c

617

if (reg >= JME_PAR0 &&

sys/dev/netif/jme/if_jme.c

618

reg < JME_PAR0 + ETHER_ADDR_LEN) {

sys/dev/netif/jme/if_jme.c

622

eaddr[reg - JME_PAR0] = val;

sys/dev/netif/jme/if_jme.c

674

uint32_t reg;

sys/dev/netif/jme/if_jme.c

824

reg = CSR_READ_4(sc, JME_CHIPMODE);

sys/dev/netif/jme/if_jme.c

825

if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=

sys/dev/netif/jme/if_jme.c

830

(reg & CHIPMODE_FPGA_REV_MASK) >>

sys/dev/netif/jme/if_jme.c

836

rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;

sys/dev/netif/jme/if_jme.c

837

rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;

sys/dev/netif/jme/if_jme.c

876

reg = pci_read_config(dev, JME_PCI_SSCTRL, 4);

sys/dev/netif/jme/if_jme.c

877

if ((reg & SSCTRL_PHYMASK) == SSCTRL_PHYEA) {

sys/dev/netif/jme/if_jme.c

890

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/netif/jme/if_jme.c

891

if (reg & SMBCSR_EEPROM_PRESENT)

sys/dev/netif/jme/if_jme.c

893

if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {

sys/dev/netif/jme/if_jmevar.h

308

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/netif/jme/if_jmevar.h

309

bus_space_write_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg), (val))

sys/dev/netif/jme/if_jmevar.h

310

#define CSR_READ_4(_sc, reg) \

sys/dev/netif/jme/if_jmevar.h

311

bus_space_read_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg))

sys/dev/netif/lge/if_lge.c

198

#define LGE_SETBIT(sc, reg, x) \

sys/dev/netif/lge/if_lge.c

199

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/lge/if_lge.c

201

#define LGE_CLRBIT(sc, reg, x) \

sys/dev/netif/lge/if_lge.c

202

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/lge/if_lge.c

257

lge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/lge/if_lge.c

270

CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);

sys/dev/netif/lge/if_lge.c

286

lge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/lge/if_lge.c

292

(data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);

sys/dev/netif/lge/if_lgereg.h

544

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/lge/if_lgereg.h

545

bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)

sys/dev/netif/lge/if_lgereg.h

547

#define CSR_READ_2(sc, reg) \

sys/dev/netif/lge/if_lgereg.h

548

bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg)

sys/dev/netif/lge/if_lgereg.h

550

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/lge/if_lgereg.h

551

bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)

sys/dev/netif/lge/if_lgereg.h

553

#define CSR_READ_4(sc, reg) \

sys/dev/netif/lge/if_lgereg.h

554

bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg)

sys/dev/netif/lge/if_lgereg.h

556

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/lge/if_lgereg.h

557

bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)

sys/dev/netif/lge/if_lgereg.h

559

#define CSR_READ_1(sc, reg) \

sys/dev/netif/lge/if_lgereg.h

560

bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg)

sys/dev/netif/lnc/if_lnc_pci.c

220

uint16_t reg;

sys/dev/netif/lnc/if_lnc_pci.c

235

reg = le_pci_rdcsr(sc, LE_CSR15);

sys/dev/netif/lnc/if_lnc_pci.c

236

reg &= ~LE_C15_PORTSEL(LE_PORTSEL_MASK);

sys/dev/netif/lnc/if_lnc_pci.c

238

reg |= LE_C15_PORTSEL(LE_PORTSEL_10T);

sys/dev/netif/lnc/if_lnc_pci.c

240

reg |= LE_C15_PORTSEL(LE_PORTSEL_AUI);

sys/dev/netif/lnc/if_lnc_pci.c

241

le_pci_wrcsr(sc, LE_CSR15, reg);

sys/dev/netif/lnc/if_lnc_pci.c

244

reg = le_pci_rdbcr(sc, LE_BCR9);

sys/dev/netif/lnc/if_lnc_pci.c

246

reg |= LE_B9_FDEN;

sys/dev/netif/lnc/if_lnc_pci.c

252

reg |= LE_B9_AUIFD;

sys/dev/netif/lnc/if_lnc_pci.c

254

reg &= ~LE_B9_AUIFD;

sys/dev/netif/lnc/if_lnc_pci.c

256

reg &= ~LE_B9_FDEN;

sys/dev/netif/lnc/if_lnc_pci.c

257

le_pci_wrbcr(sc, LE_BCR9, reg);

sys/dev/netif/mii_layer/acphy.c

183

int reg;

sys/dev/netif/mii_layer/acphy.c

191

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/acphy.c

192

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO | BMCR_PDOWN);

sys/dev/netif/mii_layer/amphy.c

156

int reg;

sys/dev/netif/mii_layer/amphy.c

173

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/amphy.c

174

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/atphy.c

325

uint32_t reg;

sys/dev/netif/mii_layer/atphy.c

332

reg = PHY_READ(sc, ATPHY_SCR);

sys/dev/netif/mii_layer/atphy.c

334

reg |= ATPHY_SCR_AUTO_X_MODE;

sys/dev/netif/mii_layer/atphy.c

336

reg &= ~ATPHY_SCR_MAC_PDOWN;

sys/dev/netif/mii_layer/atphy.c

338

reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;

sys/dev/netif/mii_layer/atphy.c

340

reg |= ATPHY_SCR_POLARITY_REVERSAL;

sys/dev/netif/mii_layer/atphy.c

341

PHY_WRITE(sc, ATPHY_SCR, reg);

sys/dev/netif/mii_layer/brgphy.c

223

int reg, speed, gig;

sys/dev/netif/mii_layer/brgphy.c

240

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/brgphy.c

241

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/brgphy.c

346

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/netif/mii_layer/brgphy.c

347

if (reg & BMSR_LINK) {

sys/dev/netif/mii_layer/brgphy.c

576

int reg;

sys/dev/netif/mii_layer/brgphy.c

594

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

595

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/brgphy.c

604

int reg;

sys/dev/netif/mii_layer/brgphy.c

614

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

615

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/brgphy.c

641

int reg;

sys/dev/netif/mii_layer/brgphy.c

650

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

651

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/brgphy.c

658

int reg;

sys/dev/netif/mii_layer/brgphy.c

671

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

672

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/brgphy.c

679

int reg;

sys/dev/netif/mii_layer/brgphy.c

688

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

689

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/brgphy.c

696

int reg;

sys/dev/netif/mii_layer/brgphy.c

711

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

712

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/brgphy.c

719

int reg;

sys/dev/netif/mii_layer/brgphy.c

730

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/netif/mii_layer/brgphy.c

731

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/netif/mii_layer/ciphy.c

157

int reg, speed, gig;

sys/dev/netif/mii_layer/ciphy.c

174

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/ciphy.c

175

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/dcphy.c

206

int reg;

sys/dev/netif/mii_layer/dcphy.c

304

reg = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/netif/mii_layer/dcphy.c

305

if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))

sys/dev/netif/mii_layer/dcphy.c

339

int reg, anlpar, tstat = 0;

sys/dev/netif/mii_layer/dcphy.c

350

reg = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/netif/mii_layer/dcphy.c

351

if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))

sys/dev/netif/mii_layer/dcphy.c

395

if (!(reg & DC_TSTAT_LS100))

sys/dev/netif/mii_layer/dcphy.c

397

else if (!(reg & DC_TSTAT_LS10))

sys/dev/netif/mii_layer/dcphy.c

66

#define DC_SETBIT(sc, reg, x) \

sys/dev/netif/mii_layer/dcphy.c

67

CSR_WRITE_4(sc, reg, \

sys/dev/netif/mii_layer/dcphy.c

68

CSR_READ_4(sc, reg) | x)

sys/dev/netif/mii_layer/dcphy.c

70

#define DC_CLRBIT(sc, reg, x) \

sys/dev/netif/mii_layer/dcphy.c

71

CSR_WRITE_4(sc, reg, \

sys/dev/netif/mii_layer/dcphy.c

72

CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/mii_layer/e1000phy.c

197

uint16_t reg, page;

sys/dev/netif/mii_layer/e1000phy.c

199

reg = PHY_READ(sc, E1000_SCR);

sys/dev/netif/mii_layer/e1000phy.c

201

reg &= ~E1000_SCR_AUTO_X_MODE;

sys/dev/netif/mii_layer/e1000phy.c

202

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/netif/mii_layer/e1000phy.c

207

reg = PHY_READ(sc, E1000_SCR);

sys/dev/netif/mii_layer/e1000phy.c

208

reg &= ~E1000_SCR_MODE_MASK;

sys/dev/netif/mii_layer/e1000phy.c

209

reg |= E1000_SCR_MODE_1000BX;

sys/dev/netif/mii_layer/e1000phy.c

210

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/netif/mii_layer/e1000phy.c

224

reg &= ~E1000_SCR_EN_DETECT_MASK;

sys/dev/netif/mii_layer/e1000phy.c

225

reg |= E1000_SCR_AUTO_X_MODE;

sys/dev/netif/mii_layer/e1000phy.c

227

reg &= ~E1000_SCR_POWER_DOWN;

sys/dev/netif/mii_layer/e1000phy.c

228

reg |= E1000_SCR_ASSERT_CRS_ON_TX;

sys/dev/netif/mii_layer/e1000phy.c

231

reg |= (E1000_SCR_AUTO_X_MODE >> 1);

sys/dev/netif/mii_layer/e1000phy.c

232

reg |= E1000_SCR_ASSERT_CRS_ON_TX;

sys/dev/netif/mii_layer/e1000phy.c

235

reg |= E1000_SCR_AUTO_MDIX;

sys/dev/netif/mii_layer/e1000phy.c

236

reg &= ~(E1000_SCR_EN_DETECT |

sys/dev/netif/mii_layer/e1000phy.c

238

reg |= E1000_SCR_LPNP;

sys/dev/netif/mii_layer/e1000phy.c

243

reg &= ~E1000_SCR_AUTO_X_MODE;

sys/dev/netif/mii_layer/e1000phy.c

244

reg |= E1000_SCR_ASSERT_CRS_ON_TX;

sys/dev/netif/mii_layer/e1000phy.c

249

reg &= ~E1000_SCR_POLARITY_REVERSAL;

sys/dev/netif/mii_layer/e1000phy.c

251

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/netif/mii_layer/e1000phy.c

257

reg = PHY_READ(sc, E1000_SCR);

sys/dev/netif/mii_layer/e1000phy.c

258

reg |= E1000_SCR_RGMII_POWER_UP;

sys/dev/netif/mii_layer/e1000phy.c

259

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/netif/mii_layer/e1000phy.c

292

reg = PHY_READ(sc, E1000_ESCR);

sys/dev/netif/mii_layer/e1000phy.c

293

reg |= E1000_ESCR_TX_CLK_25;

sys/dev/netif/mii_layer/e1000phy.c

294

PHY_WRITE(sc, E1000_ESCR, reg);

sys/dev/netif/mii_layer/e1000phy.c

299

reg = PHY_READ(sc, E1000_CR);

sys/dev/netif/mii_layer/e1000phy.c

300

reg |= E1000_CR_RESET;

sys/dev/netif/mii_layer/e1000phy.c

301

PHY_WRITE(sc, E1000_CR, reg);

sys/dev/netif/mii_layer/e1000phy.c

309

int reg;

sys/dev/netif/mii_layer/e1000phy.c

326

reg = PHY_READ(sc, E1000_CR);

sys/dev/netif/mii_layer/e1000phy.c

327

PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);

sys/dev/netif/mii_layer/e1000phy.c

363

reg = PHY_READ(sc, E1000_CR);

sys/dev/netif/mii_layer/e1000phy.c

365

reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);

sys/dev/netif/mii_layer/e1000phy.c

378

reg = PHY_READ(sc, E1000_CR);

sys/dev/netif/mii_layer/e1000phy.c

379

reg &= ~E1000_CR_AUTO_NEG_ENABLE;

sys/dev/netif/mii_layer/e1000phy.c

380

PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);

sys/dev/netif/mii_layer/e1000phy.c

433

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/netif/mii_layer/e1000phy.c

434

if (reg & BMSR_LINK) {

sys/dev/netif/mii_layer/e1000phy.c

542

uint16_t reg;

sys/dev/netif/mii_layer/e1000phy.c

544

reg = PHY_READ(sc, E1000_AR);

sys/dev/netif/mii_layer/e1000phy.c

545

reg |= E1000_AR_10T | E1000_AR_10T_FD |

sys/dev/netif/mii_layer/e1000phy.c

548

PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);

sys/dev/netif/mii_layer/inphy.c

147

int reg;

sys/dev/netif/mii_layer/inphy.c

157

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/inphy.c

158

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/ip1000phy.c

166

uint32_t gig, reg, speed;

sys/dev/netif/mii_layer/ip1000phy.c

183

reg = PHY_READ(sc, IP1000PHY_MII_BMCR);

sys/dev/netif/mii_layer/ip1000phy.c

185

reg | IP1000PHY_BMCR_ISO);

sys/dev/netif/mii_layer/ip1000phy.c

280

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/netif/mii_layer/ip1000phy.c

281

if (reg & BMSR_LINK) {

sys/dev/netif/mii_layer/ip1000phy.c

387

uint32_t reg;

sys/dev/netif/mii_layer/ip1000phy.c

393

reg = IP1000PHY_1000CR_1000T | IP1000PHY_1000CR_1000T_FDX;

sys/dev/netif/mii_layer/ip1000phy.c

394

reg |= IP1000PHY_1000CR_MASTER;

sys/dev/netif/mii_layer/ip1000phy.c

395

PHY_WRITE(mii, IP1000PHY_MII_1000CR, reg);

sys/dev/netif/mii_layer/ip1000phy.c

422

uint32_t reg;

sys/dev/netif/mii_layer/ip1000phy.c

427

reg = PHY_READ(sc, IP1000PHY_MII_BMCR);

sys/dev/netif/mii_layer/ip1000phy.c

428

reg &= ~(IP1000PHY_BMCR_AUTOEN | IP1000PHY_BMCR_FDX);

sys/dev/netif/mii_layer/ip1000phy.c

429

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/netif/mii_layer/lxtphy.c

194

int reg;

sys/dev/netif/mii_layer/lxtphy.c

211

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/lxtphy.c

212

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/mii.c

201

miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/mii_layer/mii.c

206

return MIIBUS_READREG(parent, phy, reg);

sys/dev/netif/mii_layer/mii.c

210

miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/mii_layer/mii.c

215

return MIIBUS_WRITEREG(parent, phy, reg, data);

sys/dev/netif/mii_layer/mii_physubr.c

185

int reg, i;

sys/dev/netif/mii_layer/mii_physubr.c

188

reg = BMCR_RESET;

sys/dev/netif/mii_layer/mii_physubr.c

190

reg = BMCR_RESET | BMCR_ISO;

sys/dev/netif/mii_layer/mii_physubr.c

191

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/netif/mii_layer/mii_physubr.c

205

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/mii_physubr.c

206

if ((reg & BMCR_RESET) == 0)

sys/dev/netif/mii_layer/mii_physubr.c

212

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/mii_physubr.c

410

int reg;

sys/dev/netif/mii_layer/mii_physubr.c

426

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/netif/mii_layer/mii_physubr.c

427

if (reg & BMSR_LINK) {

sys/dev/netif/mii_layer/mlphy.c

199

int reg;

sys/dev/netif/mii_layer/mlphy.c

238

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/mlphy.c

239

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/mlphy.c

336

reg = PHY_READ(other, MII_BMSR) |

sys/dev/netif/mii_layer/mlphy.c

339

reg = PHY_READ(sc, MII_BMSR) |

sys/dev/netif/mii_layer/mlphy.c

342

if (reg & BMSR_LINK) {

sys/dev/netif/mii_layer/mlphy.c

397

int reg;

sys/dev/netif/mii_layer/mlphy.c

400

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/mlphy.c

401

reg &= ~BMCR_AUTOEN;

sys/dev/netif/mii_layer/mlphy.c

402

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/netif/mii_layer/nsgphy.c

175

int reg;

sys/dev/netif/mii_layer/nsgphy.c

192

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/nsgphy.c

193

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/nsphy.c

200

int reg;

sys/dev/netif/mii_layer/nsphy.c

217

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/nsphy.c

218

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/nsphy.c

228

reg = PHY_READ(sc, MII_NSPHY_PCR);

sys/dev/netif/mii_layer/nsphy.c

234

reg |= PCR_LED4MODE;

sys/dev/netif/mii_layer/nsphy.c

241

reg |= PCR_CIMDIS;

sys/dev/netif/mii_layer/nsphy.c

247

reg |= PCR_FLINK100;

sys/dev/netif/mii_layer/nsphy.c

259

reg |= PCR_CONGCTRL | PCR_TXREADYSEL;

sys/dev/netif/mii_layer/nsphy.c

263

PHY_WRITE(sc, MII_NSPHY_PCR, reg);

sys/dev/netif/mii_layer/pnaphy.c

155

int reg;

sys/dev/netif/mii_layer/pnaphy.c

172

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/pnaphy.c

173

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/pnphy.c

260

int reg;

sys/dev/netif/mii_layer/pnphy.c

265

reg = CSR_READ_4(dc_sc, DC_ISR);

sys/dev/netif/mii_layer/pnphy.c

267

if (!(reg & DC_ISR_LINKFAIL))

sys/dev/netif/mii_layer/pnphy.c

65

#define DC_SETBIT(sc, reg, x) \

sys/dev/netif/mii_layer/pnphy.c

66

CSR_WRITE_4(sc, reg, \

sys/dev/netif/mii_layer/pnphy.c

67

CSR_READ_4(sc, reg) | x)

sys/dev/netif/mii_layer/pnphy.c

69

#define DC_CLRBIT(sc, reg, x) \

sys/dev/netif/mii_layer/pnphy.c

70

CSR_WRITE_4(sc, reg, \

sys/dev/netif/mii_layer/pnphy.c

71

CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/mii_layer/qsphy.c

182

int reg;

sys/dev/netif/mii_layer/qsphy.c

190

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/qsphy.c

191

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/rgephy.c

158

int reg, speed, gig;

sys/dev/netif/mii_layer/rgephy.c

176

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/rgephy.c

177

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/rgephy.c

283

reg = PHY_READ(sc, RE_GMEDIASTAT);

sys/dev/netif/mii_layer/rgephy.c

284

if (reg & RE_GMEDIASTAT_LINK) {

sys/dev/netif/mii_layer/rgephy.c

289

reg = PHY_READ(sc, RGEPHY_SR);

sys/dev/netif/mii_layer/rgephy.c

290

if (reg & RGEPHY_SR_LINK) {

sys/dev/netif/mii_layer/ruephy.c

155

int reg;

sys/dev/netif/mii_layer/ruephy.c

203

reg = PHY_READ(sc, RUEPHY_MII_MSR) |

sys/dev/netif/mii_layer/ruephy.c

205

if (reg & RUEPHY_MSR_LINK) {

sys/dev/netif/mii_layer/tlphy.c

235

int reg;

sys/dev/netif/mii_layer/tlphy.c

255

reg = PHY_READ(&sc->sc_mii, MII_BMCR);

sys/dev/netif/mii_layer/tlphy.c

256

PHY_WRITE(&sc->sc_mii, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/tlphy.c

315

reg = PHY_READ(&sc->sc_mii, MII_BMSR) |

sys/dev/netif/mii_layer/tlphy.c

317

if (reg & BMSR_LINK) {

sys/dev/netif/mii_layer/ukphy.c

193

int reg;

sys/dev/netif/mii_layer/ukphy.c

210

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/ukphy.c

211

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/xmphy.c

164

int reg;

sys/dev/netif/mii_layer/xmphy.c

181

reg = PHY_READ(sc, MII_BMCR);

sys/dev/netif/mii_layer/xmphy.c

182

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/netif/mii_layer/xmphy.c

245

reg = PHY_READ(sc, XMPHY_MII_BMSR) |

sys/dev/netif/mii_layer/xmphy.c

247

if (reg & XMPHY_BMSR_LINK) {

sys/dev/netif/msk/if_msk.c

3343

uint32_t reg;

sys/dev/netif/msk/if_msk.c

3433

reg = GMF_OPER_ON | GMF_RX_F_FL_ON;

sys/dev/netif/msk/if_msk.c

3436

reg |= GMF_RX_OVER_ON;

sys/dev/netif/msk/if_msk.c

3437

CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);

sys/dev/netif/msk/if_msk.c

3455

reg = RX_GMF_FL_THR_DEF + 1;

sys/dev/netif/msk/if_msk.c

3459

reg = 0x178;

sys/dev/netif/msk/if_msk.c

3460

CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);

sys/dev/netif/msk/if_msk.c

3484

reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));

sys/dev/netif/msk/if_msk.c

3485

reg &= ~0x03;

sys/dev/netif/msk/if_msk.c

3486

CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);

sys/dev/netif/msk/if_msk.c

360

msk_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/msk/if_msk.c

369

return (msk_phy_readreg(sc_if, phy, reg));

sys/dev/netif/msk/if_msk.c

373

msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)

sys/dev/netif/msk/if_msk.c

381

GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

sys/dev/netif/msk/if_msk.c

401

msk_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/msk/if_msk.c

410

return (msk_phy_writereg(sc_if, phy, reg, val));

sys/dev/netif/msk/if_msk.c

414

msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/netif/msk/if_msk.c

423

GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));

sys/dev/netif/msk/if_mskreg.h

2113

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2114

bus_space_write_4((sc)->msk_res_bt, (sc)->msk_res_bh, (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2115

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2116

bus_space_write_2((sc)->msk_res_bt, (sc)->msk_res_bh, (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2117

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2118

bus_space_write_1((sc)->msk_res_bt, (sc)->msk_res_bh, (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2120

#define CSR_READ_4(sc, reg) \

sys/dev/netif/msk/if_mskreg.h

2121

bus_space_read_4((sc)->msk_res_bt, (sc)->msk_res_bh, (reg))

sys/dev/netif/msk/if_mskreg.h

2122

#define CSR_READ_2(sc, reg) \

sys/dev/netif/msk/if_mskreg.h

2123

bus_space_read_2((sc)->msk_res_bt, (sc)->msk_res_bh, (reg))

sys/dev/netif/msk/if_mskreg.h

2124

#define CSR_READ_1(sc, reg) \

sys/dev/netif/msk/if_mskreg.h

2125

bus_space_read_1((sc)->msk_res_bt, (sc)->msk_res_bh, (reg))

sys/dev/netif/msk/if_mskreg.h

2127

#define CSR_PCI_WRITE_4(sc, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2129

Y2_CFG_SPC + (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2130

#define CSR_PCI_WRITE_2(sc, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2132

Y2_CFG_SPC + (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2133

#define CSR_PCI_WRITE_1(sc, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2135

Y2_CFG_SPC + (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2137

#define CSR_PCI_READ_4(sc, reg) \

sys/dev/netif/msk/if_mskreg.h

2138

bus_space_read_4((sc)->msk_res_bt, (sc)->msk_res_bh, Y2_CFG_SPC + (reg))

sys/dev/netif/msk/if_mskreg.h

2139

#define CSR_PCI_READ_2(sc, reg) \

sys/dev/netif/msk/if_mskreg.h

2140

bus_space_read_2((sc)->msk_res_bt, (sc)->msk_res_bh, Y2_CFG_SPC + (reg))

sys/dev/netif/msk/if_mskreg.h

2141

#define CSR_PCI_READ_1(sc, reg) \

sys/dev/netif/msk/if_mskreg.h

2142

bus_space_read_1((sc)->msk_res_bt, (sc)->msk_res_bh, Y2_CFG_SPC + (reg))

sys/dev/netif/msk/if_mskreg.h

2144

#define MSK_IF_READ_4(sc_if, reg) \

sys/dev/netif/msk/if_mskreg.h

2145

CSR_READ_4((sc_if)->msk_softc, (reg))

sys/dev/netif/msk/if_mskreg.h

2146

#define MSK_IF_READ_2(sc_if, reg) \

sys/dev/netif/msk/if_mskreg.h

2147

CSR_READ_2((sc_if)->msk_softc, (reg))

sys/dev/netif/msk/if_mskreg.h

2148

#define MSK_IF_READ_1(sc_if, reg) \

sys/dev/netif/msk/if_mskreg.h

2149

CSR_READ_1((sc_if)->msk_softc, (reg))

sys/dev/netif/msk/if_mskreg.h

2151

#define MSK_IF_WRITE_4(sc_if, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2152

CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2153

#define MSK_IF_WRITE_2(sc_if, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2154

CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2155

#define MSK_IF_WRITE_1(sc_if, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2156

CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))

sys/dev/netif/msk/if_mskreg.h

2158

#define GMAC_REG(port, reg) \

sys/dev/netif/msk/if_mskreg.h

2159

((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))

sys/dev/netif/msk/if_mskreg.h

2160

#define GMAC_WRITE_2(sc, port, reg, val) \

sys/dev/netif/msk/if_mskreg.h

2161

CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))

sys/dev/netif/msk/if_mskreg.h

2162

#define GMAC_READ_2(sc, port, reg) \

sys/dev/netif/msk/if_mskreg.h

2163

CSR_READ_2((sc), GMAC_REG((port), (reg)))

sys/dev/netif/mxge/if_mxge.c

3559

int reg;

sys/dev/netif/mxge/if_mxge.c

3563

if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/netif/mxge/if_mxge.c

3564

lnk = pci_read_config(dev, reg + 0x12, 2);

sys/dev/netif/mxge/if_mxge.c

3568

pectl = pci_read_config(dev, reg + 0x8, 2);

sys/dev/netif/mxge/if_mxge.c

3570

pci_write_config(dev, reg + 0x8, pectl, 2);

sys/dev/netif/mxge/if_mxge.c

3574

pci_write_config(dev, reg + 0x8, sc->pectl, 2);

sys/dev/netif/mxge/if_mxge.c

512

int reg, status;

sys/dev/netif/mxge/if_mxge.c

521

if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/netif/mxge/if_mxge.c

522

pectl = pci_read_config(dev, reg + 0x8, 2);

sys/dev/netif/my/if_my.c

137

#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)

sys/dev/netif/my/if_my.c

138

#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/my/if_my.c

213

my_phy_readreg(struct my_softc * sc, int reg)

sys/dev/netif/my/if_my.c

219

data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);

sys/dev/netif/my/if_my.c

221

miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);

sys/dev/netif/my/if_my.c

255

my_phy_writereg(struct my_softc * sc, int reg, int data)

sys/dev/netif/my/if_my.c

261

CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);

sys/dev/netif/my/if_my.c

263

miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);

sys/dev/netif/my/if_myreg.h

380

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/my/if_myreg.h

381

bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val)

sys/dev/netif/my/if_myreg.h

382

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/my/if_myreg.h

383

bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val)

sys/dev/netif/my/if_myreg.h

384

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/my/if_myreg.h

385

bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)

sys/dev/netif/my/if_myreg.h

387

#define CSR_READ_4(sc, reg) \

sys/dev/netif/my/if_myreg.h

388

bus_space_read_4(sc->my_btag, sc->my_bhandle, reg)

sys/dev/netif/my/if_myreg.h

389

#define CSR_READ_2(sc, reg) \

sys/dev/netif/my/if_myreg.h

390

bus_space_read_2(sc->my_btag, sc->my_bhandle, reg)

sys/dev/netif/my/if_myreg.h

391

#define CSR_READ_1(sc, reg) \

sys/dev/netif/my/if_myreg.h

392

bus_space_read_1(sc->my_btag, sc->my_bhandle, reg)

sys/dev/netif/nfe/if_nfe.c

782

nfe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/nfe/if_nfe.c

795

NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);

sys/dev/netif/nfe/if_nfe.c

816

DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);

sys/dev/netif/nfe/if_nfe.c

822

nfe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/nfe/if_nfe.c

836

ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;

sys/dev/netif/nfe/if_nfereg.h

211

#define NFE_READ(sc, reg) \

sys/dev/netif/nfe/if_nfereg.h

212

bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))

sys/dev/netif/nfe/if_nfereg.h

214

#define NFE_WRITE(sc, reg, val) \

sys/dev/netif/nfe/if_nfereg.h

215

bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))

sys/dev/netif/nge/if_nge.c

231

#define NGE_SETBIT(sc, reg, x) \

sys/dev/netif/nge/if_nge.c

232

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/nge/if_nge.c

234

#define NGE_CLRBIT(sc, reg, x) \

sys/dev/netif/nge/if_nge.c

235

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/nge/if_nge.c

529

nge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/nge/if_nge.c

537

frame.mii_regaddr = reg;

sys/dev/netif/nge/if_nge.c

544

nge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/nge/if_nge.c

552

frame.mii_regaddr = reg;

sys/dev/netif/nge/if_ngereg.h

660

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/nge/if_ngereg.h

661

bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)

sys/dev/netif/nge/if_ngereg.h

663

#define CSR_READ_4(sc, reg) \

sys/dev/netif/nge/if_ngereg.h

664

bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg)

sys/dev/netif/oce/oce_hw.c

518

uint32_t reg;

sys/dev/netif/oce/oce_hw.c

520

reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);

sys/dev/netif/oce/oce_hw.c

521

reg |= HOSTINTR_MASK;

sys/dev/netif/oce/oce_hw.c

522

OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);

sys/dev/netif/oce/oce_hw.c

534

uint32_t reg;

sys/dev/netif/oce/oce_hw.c

536

reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);

sys/dev/netif/oce/oce_hw.c

537

reg &= ~HOSTINTR_MASK;

sys/dev/netif/oce/oce_hw.c

538

OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);

sys/dev/netif/pcn/if_pcn.c

187

#define PCN_CSR_SETBIT(sc, reg, x) \

sys/dev/netif/pcn/if_pcn.c

188

pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))

sys/dev/netif/pcn/if_pcn.c

190

#define PCN_CSR_CLRBIT(sc, reg, x) \

sys/dev/netif/pcn/if_pcn.c

191

pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))

sys/dev/netif/pcn/if_pcn.c

193

#define PCN_BCR_SETBIT(sc, reg, x) \

sys/dev/netif/pcn/if_pcn.c

194

pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))

sys/dev/netif/pcn/if_pcn.c

196

#define PCN_BCR_CLRBIT(sc, reg, x) \

sys/dev/netif/pcn/if_pcn.c

197

pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))

sys/dev/netif/pcn/if_pcn.c

200

pcn_csr_read(struct pcn_softc *sc, int reg)

sys/dev/netif/pcn/if_pcn.c

202

CSR_WRITE_4(sc, PCN_IO32_RAP, reg);

sys/dev/netif/pcn/if_pcn.c

207

pcn_csr_read16(struct pcn_softc *sc, int reg)

sys/dev/netif/pcn/if_pcn.c

209

CSR_WRITE_2(sc, PCN_IO16_RAP, reg);

sys/dev/netif/pcn/if_pcn.c

214

pcn_csr_write(struct pcn_softc *sc, int reg, int val)

sys/dev/netif/pcn/if_pcn.c

216

CSR_WRITE_4(sc, PCN_IO32_RAP, reg);

sys/dev/netif/pcn/if_pcn.c

222

pcn_bcr_read(struct pcn_softc *sc, int reg)

sys/dev/netif/pcn/if_pcn.c

224

CSR_WRITE_4(sc, PCN_IO32_RAP, reg);

sys/dev/netif/pcn/if_pcn.c

229

pcn_bcr_read16(struct pcn_softc *sc, int reg)

sys/dev/netif/pcn/if_pcn.c

231

CSR_WRITE_2(sc, PCN_IO16_RAP, reg);

sys/dev/netif/pcn/if_pcn.c

236

pcn_bcr_write(struct pcn_softc *sc, int reg, int val)

sys/dev/netif/pcn/if_pcn.c

238

CSR_WRITE_4(sc, PCN_IO32_RAP, reg);

sys/dev/netif/pcn/if_pcn.c

244

pcn_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/pcn/if_pcn.c

254

pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));

sys/dev/netif/pcn/if_pcn.c

265

pcn_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/pcn/if_pcn.c

271

pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));

sys/dev/netif/pcn/if_pcnreg.h

446

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/pcn/if_pcnreg.h

447

bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val)

sys/dev/netif/pcn/if_pcnreg.h

449

#define CSR_READ_4(sc, reg) \

sys/dev/netif/pcn/if_pcnreg.h

450

bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg)

sys/dev/netif/pcn/if_pcnreg.h

452

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/pcn/if_pcnreg.h

453

bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val)

sys/dev/netif/pcn/if_pcnreg.h

455

#define CSR_READ_2(sc, reg) \

sys/dev/netif/pcn/if_pcnreg.h

456

bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg)

sys/dev/netif/ral/rt2560.c

171

uint32_t reg;

sys/dev/netif/ral/rt2560.c

178

uint8_t reg;

sys/dev/netif/ral/rt2560.c

2061

rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)

sys/dev/netif/ral/rt2560.c

2076

tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;

sys/dev/netif/ral/rt2560.c

2079

DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);

sys/dev/netif/ral/rt2560.c

2083

rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)

sys/dev/netif/ral/rt2560.c

2098

val = RT2560_BBP_BUSY | reg << 8;

sys/dev/netif/ral/rt2560.c

2113

rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)

sys/dev/netif/ral/rt2560.c

2129

(reg & 0x3);

sys/dev/netif/ral/rt2560.c

2133

sc->rf_regs[reg] = val;

sys/dev/netif/ral/rt2560.c

2135

DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);

sys/dev/netif/ral/rt2560.c

2530

sc->bbp_prom[i].reg = val >> 8;

sys/dev/netif/ral/rt2560.c

2594

rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,

sys/dev/netif/ral/rt2560.c

2600

if (sc->bbp_prom[i].reg == 0 && sc->bbp_prom[i].val == 0)

sys/dev/netif/ral/rt2560.c

2602

rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/netif/ral/rt2560.c

2689

RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);

sys/dev/netif/ral/rt2560reg.h

309

#define RAL_READ(sc, reg) \

sys/dev/netif/ral/rt2560reg.h

310

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/ral/rt2560reg.h

312

#define RAL_WRITE(sc, reg, val) \

sys/dev/netif/ral/rt2560reg.h

313

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/ral/rt2560var.h

142

uint8_t reg;

sys/dev/netif/ral/rt2661.c

177

uint32_t reg;

sys/dev/netif/ral/rt2661.c

1788

rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)

sys/dev/netif/ral/rt2661.c

1803

tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;

sys/dev/netif/ral/rt2661.c

1806

DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);

sys/dev/netif/ral/rt2661.c

1810

rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)

sys/dev/netif/ral/rt2661.c

1825

val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;

sys/dev/netif/ral/rt2661.c

184

uint8_t reg;

sys/dev/netif/ral/rt2661.c

1840

rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)

sys/dev/netif/ral/rt2661.c

1856

(reg & 3);

sys/dev/netif/ral/rt2661.c

1860

sc->rf_regs[reg] = val;

sys/dev/netif/ral/rt2661.c

1862

DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);

sys/dev/netif/ral/rt2661.c

2278

sc->bbp_prom[i].reg = val >> 8;

sys/dev/netif/ral/rt2661.c

2280

DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,

sys/dev/netif/ral/rt2661.c

2305

rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,

sys/dev/netif/ral/rt2661.c

2311

if (sc->bbp_prom[i].reg == 0)

sys/dev/netif/ral/rt2661.c

2313

rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/netif/ral/rt2661.c

2383

RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);

sys/dev/netif/ral/rt2661reg.h

319

#define RAL_READ(sc, reg) \

sys/dev/netif/ral/rt2661reg.h

320

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/ral/rt2661reg.h

326

#define RAL_WRITE(sc, reg, val) \

sys/dev/netif/ral/rt2661reg.h

327

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/ral/rt2661var.h

141

uint8_t reg;

sys/dev/netif/ral/rt2860.c

1008

uint16_t reg;

sys/dev/netif/ral/rt2860.c

1036

reg = RT3070_EFUSE_DATA3 - (addr & 0xc);

sys/dev/netif/ral/rt2860.c

1037

tmp = RAL_READ(sc, reg);

sys/dev/netif/ral/rt2860.c

193

uint32_t reg;

sys/dev/netif/ral/rt2860.c

200

uint8_t reg;

sys/dev/netif/ral/rt2860.c

2123

rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)

sys/dev/netif/ral/rt2860.c

2139

RT2860_BBP_CSR_KICK | reg << 8 | val);

sys/dev/netif/ral/rt2860.c

2147

rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)

sys/dev/netif/ral/rt2860.c

2164

RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);

sys/dev/netif/ral/rt2860.c

2185

rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)

sys/dev/netif/ral/rt2860.c

2202

(val & 0x3fffff) << 2 | (reg & 3);

sys/dev/netif/ral/rt2860.c

2207

rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)

sys/dev/netif/ral/rt2860.c

222

uint8_t reg;

sys/dev/netif/ral/rt2860.c

2221

tmp = RT3070_RF_KICK | reg << 8;

sys/dev/netif/ral/rt2860.c

2238

rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)

sys/dev/netif/ral/rt2860.c

2253

tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;

sys/dev/netif/ral/rt2860.c

2736

rt3090_rf_write(sc, rt3090_def_rf[i].reg,

sys/dev/netif/ral/rt2860.c

2832

rt3090_rf_write(sc, rt5392_def_rf[i].reg,

sys/dev/netif/ral/rt2860.c

2837

rt3090_rf_write(sc, rt5390_def_rf[i].reg,

sys/dev/netif/ral/rt2860.c

3078

if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)

sys/dev/netif/ral/rt2860.c

3080

rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);

sys/dev/netif/ral/rt2860.c

3467

sc->bbp[i].reg = val >> 8;

sys/dev/netif/ral/rt2860.c

3468

DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));

sys/dev/netif/ral/rt2860.c

3475

sc->rf[i].reg = val >> 8;

sys/dev/netif/ral/rt2860.c

3476

DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,

sys/dev/netif/ral/rt2860.c

3606

uint32_t reg;

sys/dev/netif/ral/rt2860.c

3609

reg = val;

sys/dev/netif/ral/rt2860.c

3611

reg |= (uint32_t)val << 16;

sys/dev/netif/ral/rt2860.c

3613

sc->txpow20mhz[ridx] = reg;

sys/dev/netif/ral/rt2860.c

3614

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/dev/netif/ral/rt2860.c

3615

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/dev/netif/ral/rt2860.c

3751

rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,

sys/dev/netif/ral/rt2860.c

3789

rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,

sys/dev/netif/ral/rt2860.c

3947

RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);

sys/dev/netif/ral/rt2860.c

4037

if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)

sys/dev/netif/ral/rt2860.c

4039

rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);

sys/dev/netif/ral/rt2860reg.h

993

#define RAL_READ(sc, reg) \

sys/dev/netif/ral/rt2860reg.h

994

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/ral/rt2860reg.h

996

#define RAL_WRITE(sc, reg, val) \

sys/dev/netif/ral/rt2860reg.h

997

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/ral/rt2860var.h

191

uint8_t reg;

sys/dev/netif/re/if_re.c

2518

uint8_t pcie_ptr, reg;

sys/dev/netif/re/if_re.c

2531

reg = pcie_ptr + PCIER_LINKCTRL;

sys/dev/netif/re/if_re.c

2532

link_ctrl = pci_read_config(dev, reg, 2);

sys/dev/netif/re/if_re.c

2534

pci_write_config(dev, reg, link_ctrl, 2);

sys/dev/netif/re/if_revar.h

221

#define CSR_WRITE_STREAM_4(sc, reg, val) \

sys/dev/netif/re/if_revar.h

222

bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)

sys/dev/netif/re/if_revar.h

223

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/re/if_revar.h

224

bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)

sys/dev/netif/re/if_revar.h

225

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/re/if_revar.h

226

bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)

sys/dev/netif/re/if_revar.h

227

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/re/if_revar.h

228

bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)

sys/dev/netif/re/if_revar.h

230

#define CSR_READ_4(sc, reg) \

sys/dev/netif/re/if_revar.h

231

bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)

sys/dev/netif/re/if_revar.h

232

#define CSR_READ_2(sc, reg) \

sys/dev/netif/re/if_revar.h

233

bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)

sys/dev/netif/re/if_revar.h

234

#define CSR_READ_1(sc, reg) \

sys/dev/netif/re/if_revar.h

235

bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)

sys/dev/netif/re/if_revar.h

237

#define CSR_SETBIT_1(sc, reg, val) \

sys/dev/netif/re/if_revar.h

238

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))

sys/dev/netif/re/if_revar.h

239

#define CSR_CLRBIT_1(sc, reg, val) \

sys/dev/netif/re/if_revar.h

240

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))

sys/dev/netif/re/re.c

30992

static u_int8_t re_calc_efuse_dummy_bit(u_int16_t reg)

sys/dev/netif/re/re.c

30998

s=reg% 32;

sys/dev/netif/re/re.c

31013

u_int16_t reg = (u_int16_t)((DwCmd & 0x00FE0000) >> 17);

sys/dev/netif/re/re.c

31014

u_int32_t DummyPos = re_calc_efuse_dummy_bit(reg);

sys/dev/netif/re/re.c

31025

reg = (u_int16_t)((DwCmd & 0x007F0000) >> 16);

sys/dev/netif/re/re.c

31026

DummyPos = re_calc_efuse_dummy_bit(reg);

sys/dev/netif/re/re.c

31049

u_int8_t MP_ReadEfuse(struct re_softc *sc, u_int16_t reg)

sys/dev/netif/re/re.c

31059

temp = EFUSE_READ | ((reg & EFUSE_Reg_Mask) << EFUSE_Reg_Shift);

sys/dev/netif/re/re.c

31074

temp = (reg/2) & 0x03ff;

sys/dev/netif/re/re.c

31092

if (reg%2) {

sys/dev/netif/re/re.c

31100

temp = (reg/2) & 0x03ff;

sys/dev/netif/re/re.c

31118

if (reg%2) {

sys/dev/netif/re/re.c

31657

u_int32_t reg;

sys/dev/netif/re/re.c

31660

reg = 0xb8;

sys/dev/netif/re/re.c

31662

reg = 0x10;

sys/dev/netif/re/re.c

31664

if (OCP_read(sc, reg, 2) & 0x00008000)

sys/dev/netif/re/re.c

31705

u_int32_t reg;

sys/dev/netif/re/re.c

31714

reg = 0xB8;

sys/dev/netif/re/re.c

31716

reg = 0x10;

sys/dev/netif/re/re.c

31720

if (OCP_read(sc, reg, 2) & BIT_11)

sys/dev/netif/re/re.c

31742

u_int32_t reg;

sys/dev/netif/re/re.c

31747

reg = 0xB8;

sys/dev/netif/re/re.c

31749

reg = 0x10;

sys/dev/netif/re/re.c

31753

if ((OCP_read(sc, reg, 4) & BIT_11) == 0)

sys/dev/netif/re/re.c

4894

int reg;

sys/dev/netif/re/re.c

4967

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/netif/re/re.c

4969

sc->re_expcap = reg;

sys/dev/netif/re/re.c

5225

if (pci_find_cap(sc->dev, PCIY_PMG, &reg) == 0)

sys/dev/netif/re/re.h

1040

#define CSR_WRITE_STREAM_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val))

sys/dev/netif/re/re.h

1041

#define CSR_WRITE_STREAM_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_2(sc->re_btag, sc->re_bhandle, reg, val))

sys/dev/netif/re/re.h

1043

#define CSR_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val))

sys/dev/netif/re/re.h

1044

#define CSR_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val))

sys/dev/netif/re/re.h

1045

#define CSR_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val))

sys/dev/netif/re/re.h

1047

#define CSR_READ_4(sc, reg) ((sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_btag, sc->re_bhandle, reg))

sys/dev/netif/re/re.h

1048

#define CSR_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_btag, sc->re_bhandle, reg))

sys/dev/netif/re/re.h

1049

#define CSR_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_btag, sc->re_bhandle, reg))

sys/dev/netif/re/re.h

1052

#define RE_CMAC_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_cmac_tag, sc->re_cmac_handle, reg, val))

sys/dev/netif/re/re.h

1053

#define RE_CMAC_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_cmac_tag, sc->re_cmac_handle, reg, val))

sys/dev/netif/re/re.h

1054

#define RE_CMAC_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_cmac_tag, sc->re_cmac_handle, reg, val))

sys/dev/netif/re/re.h

1055

#define RE_CMAC_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_cmac_tag, sc->re_cmac_handle, reg))

sys/dev/netif/re/re.h

1056

#define RE_CMAC_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_cmac_tag, sc->re_cmac_handle, reg))

sys/dev/netif/re/re.h

1057

#define RE_CMAC_READ_4(sc, reg) (sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_cmac_tag, sc->re_cmac_handle, reg))

sys/dev/netif/re/re_dragonfly.h

43

#define RE_CMAC_WRITE_1(sc, reg, val) \

sys/dev/netif/re/re_dragonfly.h

44

bus_space_write_1(sc->re_cmac_tag, sc->re_cmac_handle, reg, val)

sys/dev/netif/re/re_dragonfly.h

45

#define RE_CMAC_WRITE_2(sc, reg, val) \

sys/dev/netif/re/re_dragonfly.h

46

bus_space_write_2(sc->re_cmac_tag, sc->re_cmac_handle, reg, val)

sys/dev/netif/re/re_dragonfly.h

47

#define RE_CMAC_WRITE_4(sc, reg, val) \

sys/dev/netif/re/re_dragonfly.h

48

bus_space_write_4(sc->re_cmac_tag, sc->re_cmac_handle, reg, val)

sys/dev/netif/re/re_dragonfly.h

49

#define RE_CMAC_READ_1(sc, reg) \

sys/dev/netif/re/re_dragonfly.h

50

bus_space_read_1(sc->re_cmac_tag, sc->re_cmac_handle, reg)

sys/dev/netif/re/re_dragonfly.h

51

#define RE_CMAC_READ_2(sc, reg) \

sys/dev/netif/re/re_dragonfly.h

52

bus_space_read_2(sc->re_cmac_tag, sc->re_cmac_handle, reg)

sys/dev/netif/re/re_dragonfly.h

53

#define RE_CMAC_READ_4(sc, reg) \

sys/dev/netif/re/re_dragonfly.h

54

bus_space_read_4(sc->re_cmac_tag, sc->re_cmac_handle, reg)

sys/dev/netif/rl/if_rl.c

521

rl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/rl/if_rl.c

534

switch (reg) {

sys/dev/netif/rl/if_rl.c

574

frame.mii_regaddr = reg;

sys/dev/netif/rl/if_rl.c

581

rl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/rl/if_rl.c

593

switch (reg) {

sys/dev/netif/rl/if_rl.c

623

frame.mii_regaddr = reg;

sys/dev/netif/rl/if_rlreg.h

391

#define CSR_WRITE_STREAM_4(sc, reg, val) \

sys/dev/netif/rl/if_rlreg.h

392

bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/netif/rl/if_rlreg.h

393

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/rl/if_rlreg.h

394

bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/netif/rl/if_rlreg.h

395

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/rl/if_rlreg.h

396

bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/netif/rl/if_rlreg.h

397

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/rl/if_rlreg.h

398

bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/netif/rl/if_rlreg.h

400

#define CSR_READ_4(sc, reg) \

sys/dev/netif/rl/if_rlreg.h

401

bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)

sys/dev/netif/rl/if_rlreg.h

402

#define CSR_READ_2(sc, reg) \

sys/dev/netif/rl/if_rlreg.h

403

bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)

sys/dev/netif/rl/if_rlreg.h

404

#define CSR_READ_1(sc, reg) \

sys/dev/netif/rl/if_rlreg.h

405

bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)

sys/dev/netif/sf/if_sf.c

210

#define SF_SETBIT(sc, reg, x) \

sys/dev/netif/sf/if_sf.c

211

csr_write_4(sc, reg, csr_read_4(sc, reg) | x)

sys/dev/netif/sf/if_sf.c

213

#define SF_CLRBIT(sc, reg, x) \

sys/dev/netif/sf/if_sf.c

214

csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)

sys/dev/netif/sf/if_sf.c

217

csr_read_4(struct sf_softc *sc, int reg)

sys/dev/netif/sf/if_sf.c

222

CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);

sys/dev/netif/sf/if_sf.c

225

val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));

sys/dev/netif/sf/if_sf.c

232

sf_read_eeprom(struct sf_softc *sc, int reg)

sys/dev/netif/sf/if_sf.c

237

(reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;

sys/dev/netif/sf/if_sf.c

243

csr_write_4(struct sf_softc *sc, int reg, u_int32_t val)

sys/dev/netif/sf/if_sf.c

246

CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);

sys/dev/netif/sf/if_sf.c

249

CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);

sys/dev/netif/sf/if_sf.c

351

sf_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/sf/if_sf.c

360

val = csr_read_4(sc, SF_PHY_REG(phy, reg));

sys/dev/netif/sf/if_sf.c

375

sf_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/sf/if_sf.c

383

csr_write_4(sc, SF_PHY_REG(phy, reg), val);

sys/dev/netif/sf/if_sf.c

386

busy = csr_read_4(sc, SF_PHY_REG(phy, reg));

sys/dev/netif/sf/if_sfreg.h

559

#define SF_PHY_REG(phy, reg) \

sys/dev/netif/sf/if_sfreg.h

561

(reg * sizeof(u_int32_t)))

sys/dev/netif/sf/if_sfreg.h

959

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/sf/if_sfreg.h

960

bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val)

sys/dev/netif/sf/if_sfreg.h

962

#define CSR_READ_4(sc, reg) \

sys/dev/netif/sf/if_sfreg.h

963

bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg)

sys/dev/netif/sf/if_sfreg.h

965

#define CSR_READ_1(sc, reg) \

sys/dev/netif/sf/if_sfreg.h

966

bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg)

sys/dev/netif/sis/if_sis.c

204

#define SIS_SETBIT(sc, reg, x) \

sys/dev/netif/sis/if_sis.c

205

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/sis/if_sis.c

207

#define SIS_CLRBIT(sc, reg, x) \

sys/dev/netif/sis/if_sis.c

208

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/sis/if_sis.c

394

uint8_t reg;

sys/dev/netif/sis/if_sis.c

401

reg = pci_read_config(bridge, 0x48, 1);

sys/dev/netif/sis/if_sis.c

402

pci_write_config(bridge, 0x48, reg|0x40, 1);

sys/dev/netif/sis/if_sis.c

412

pci_write_config(bridge, 0x48, reg & ~0x40, 1);

sys/dev/netif/sis/if_sis.c

608

sis_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/sis/if_sis.c

630

return CSR_READ_4(sc, NS_BMCR + (reg * 4));

sys/dev/netif/sis/if_sis.c

645

(phy << 11) | (reg << 6) | SIS_PHYOP_READ);

sys/dev/netif/sis/if_sis.c

668

frame.mii_regaddr = reg;

sys/dev/netif/sis/if_sis.c

676

sis_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/sis/if_sis.c

686

CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);

sys/dev/netif/sis/if_sis.c

698

(reg << 6) | SIS_PHYOP_WRITE);

sys/dev/netif/sis/if_sis.c

712

frame.mii_regaddr = reg;

sys/dev/netif/sis/if_sisreg.h

461

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/sis/if_sisreg.h

462

bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)

sys/dev/netif/sis/if_sisreg.h

464

#define CSR_READ_4(sc, reg) \

sys/dev/netif/sis/if_sisreg.h

465

bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg)

sys/dev/netif/sis/if_sisreg.h

467

#define CSR_READ_2(sc, reg) \

sys/dev/netif/sis/if_sisreg.h

468

bus_space_read_2(sc->sis_btag, sc->sis_bhandle, reg)

sys/dev/netif/sk/if_sk.c

2329

while(bhack[i].reg) {

sys/dev/netif/sk/if_sk.c

2331

bhack[i].reg, bhack[i].val);

sys/dev/netif/sk/if_sk.c

2435

uint16_t reg;

sys/dev/netif/sk/if_sk.c

2502

reg = SK_YU_READ_2(sc_if, YUKON_PAR);

sys/dev/netif/sk/if_sk.c

2503

DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));

sys/dev/netif/sk/if_sk.c

2506

reg |= YU_PAR_MIB_CLR;

sys/dev/netif/sk/if_sk.c

2507

DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));

sys/dev/netif/sk/if_sk.c

2509

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/netif/sk/if_sk.c

2513

reg &= ~YU_PAR_MIB_CLR;

sys/dev/netif/sk/if_sk.c

2514

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/netif/sk/if_sk.c

2527

reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);

sys/dev/netif/sk/if_sk.c

2529

reg |= YU_SMR_MFL_JUMBO;

sys/dev/netif/sk/if_sk.c

2530

SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);

sys/dev/netif/sk/if_sk.c

2542

reg = sk_win_read_2(sc_if->sk_softc,

sys/dev/netif/sk/if_sk.c

2544

SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);

sys/dev/netif/sk/if_sk.c

2748

uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);

sys/dev/netif/sk/if_sk.c

2749

reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;

sys/dev/netif/sk/if_sk.c

2752

reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);

sys/dev/netif/sk/if_sk.c

2754

SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);

sys/dev/netif/sk/if_sk.c

307

sk_win_read_4(struct sk_softc *sc, uint32_t reg)

sys/dev/netif/sk/if_sk.c

309

return CSR_READ_4(sc, reg);

sys/dev/netif/sk/if_sk.c

313

sk_win_read_2(struct sk_softc *sc, uint32_t reg)

sys/dev/netif/sk/if_sk.c

315

return CSR_READ_2(sc, reg);

sys/dev/netif/sk/if_sk.c

319

sk_win_read_1(struct sk_softc *sc, uint32_t reg)

sys/dev/netif/sk/if_sk.c

321

return CSR_READ_1(sc, reg);

sys/dev/netif/sk/if_sk.c

325

sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)

sys/dev/netif/sk/if_sk.c

327

CSR_WRITE_4(sc, reg, x);

sys/dev/netif/sk/if_sk.c

331

sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)

sys/dev/netif/sk/if_sk.c

333

CSR_WRITE_2(sc, reg, x);

sys/dev/netif/sk/if_sk.c

337

sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)

sys/dev/netif/sk/if_sk.c

339

CSR_WRITE_1(sc, reg, x);

sys/dev/netif/sk/if_sk.c

355

sk_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/sk/if_sk.c

360

return sk_xmac_miibus_readreg(sc_if, phy, reg);

sys/dev/netif/sk/if_sk.c

362

return sk_marv_miibus_readreg(sc_if, phy, reg);

sys/dev/netif/sk/if_sk.c

366

sk_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/sk/if_sk.c

371

return sk_xmac_miibus_writereg(sc_if, phy, reg, val);

sys/dev/netif/sk/if_sk.c

373

return sk_marv_miibus_writereg(sc_if, phy, reg, val);

sys/dev/netif/sk/if_sk.c

388

sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)

sys/dev/netif/sk/if_sk.c

397

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/netif/sk/if_sk.c

418

sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/netif/sk/if_sk.c

424

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/netif/sk/if_sk.c

468

sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)

sys/dev/netif/sk/if_sk.c

477

phy, reg));

sys/dev/netif/sk/if_sk.c

482

YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);

sys/dev/netif/sk/if_sk.c

502

phy, reg, val));

sys/dev/netif/sk/if_sk.c

508

sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/netif/sk/if_sk.c

513

phy, reg, val));

sys/dev/netif/sk/if_sk.c

517

YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);

sys/dev/netif/sk/if_skreg.h

105

#define SK_IF_READ_4(sc_if, skip, reg) \

sys/dev/netif/sk/if_skreg.h

106

sk_win_read_4(sc_if->sk_softc, reg + \

sys/dev/netif/sk/if_skreg.h

108

#define SK_IF_READ_2(sc_if, skip, reg) \

sys/dev/netif/sk/if_skreg.h

109

sk_win_read_2(sc_if->sk_softc, reg + \

sys/dev/netif/sk/if_skreg.h

111

#define SK_IF_READ_1(sc_if, skip, reg) \

sys/dev/netif/sk/if_skreg.h

112

sk_win_read_1(sc_if->sk_softc, reg + \

sys/dev/netif/sk/if_skreg.h

1146

#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \

sys/dev/netif/sk/if_skreg.h

115

#define SK_IF_WRITE_4(sc_if, skip, reg, val) \

sys/dev/netif/sk/if_skreg.h

1150

#define SK_XM_READ_4(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1152

SK_XMAC_REG(sc, reg)) & 0xFFFF) | \

sys/dev/netif/sk/if_skreg.h

1154

SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))

sys/dev/netif/sk/if_skreg.h

1156

#define SK_XM_WRITE_4(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1157

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \

sys/dev/netif/sk/if_skreg.h

1159

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \

sys/dev/netif/sk/if_skreg.h

1162

#define SK_XM_READ_4(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1163

sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))

sys/dev/netif/sk/if_skreg.h

1165

#define SK_XM_WRITE_4(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1166

sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))

sys/dev/netif/sk/if_skreg.h

1169

#define SK_XM_READ_2(sc, reg) \

sys/dev/netif/sk/if_skreg.h

117

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/netif/sk/if_skreg.h

1170

sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))

sys/dev/netif/sk/if_skreg.h

1172

#define SK_XM_WRITE_2(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1173

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)

sys/dev/netif/sk/if_skreg.h

1175

#define SK_XM_SETBIT_4(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1176

SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))

sys/dev/netif/sk/if_skreg.h

1178

#define SK_XM_CLRBIT_4(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1179

SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))

sys/dev/netif/sk/if_skreg.h

118

#define SK_IF_WRITE_2(sc_if, skip, reg, val) \

sys/dev/netif/sk/if_skreg.h

1181

#define SK_XM_SETBIT_2(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1182

SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))

sys/dev/netif/sk/if_skreg.h

1184

#define SK_XM_CLRBIT_2(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1185

SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))

sys/dev/netif/sk/if_skreg.h

1188

#define SK_YU_REG(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1189

((reg) + SK_MARV1_BASE + \

sys/dev/netif/sk/if_skreg.h

1192

#define SK_YU_READ_4(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1193

sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))

sys/dev/netif/sk/if_skreg.h

1195

#define SK_YU_READ_2(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1196

sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))

sys/dev/netif/sk/if_skreg.h

1198

#define SK_YU_WRITE_4(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1199

sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))

sys/dev/netif/sk/if_skreg.h

120

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/netif/sk/if_skreg.h

1201

#define SK_YU_WRITE_2(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1202

sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))

sys/dev/netif/sk/if_skreg.h

1204

#define SK_YU_SETBIT_4(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1205

SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))

sys/dev/netif/sk/if_skreg.h

1207

#define SK_YU_CLRBIT_4(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1208

SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))

sys/dev/netif/sk/if_skreg.h

121

#define SK_IF_WRITE_1(sc_if, skip, reg, val) \

sys/dev/netif/sk/if_skreg.h

1210

#define SK_YU_SETBIT_2(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1211

SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))

sys/dev/netif/sk/if_skreg.h

1213

#define SK_YU_CLRBIT_2(sc, reg, x) \

sys/dev/netif/sk/if_skreg.h

1214

SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))

sys/dev/netif/sk/if_skreg.h

123

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/netif/sk/if_skreg.h

1259

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1260

bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))

sys/dev/netif/sk/if_skreg.h

1261

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1262

bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))

sys/dev/netif/sk/if_skreg.h

1263

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/sk/if_skreg.h

1264

bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))

sys/dev/netif/sk/if_skreg.h

1266

#define CSR_READ_4(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1267

bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))

sys/dev/netif/sk/if_skreg.h

1268

#define CSR_READ_2(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1269

bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))

sys/dev/netif/sk/if_skreg.h

1270

#define CSR_READ_1(sc, reg) \

sys/dev/netif/sk/if_skreg.h

1271

bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))

sys/dev/netif/sk/if_skreg.h

549

#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)

sys/dev/netif/sk/if_skreg.h

75

#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)

sys/dev/netif/sk/if_skreg.h

78

#define SK_REG(reg) ((reg) & SK_REG_MASK)

sys/dev/netif/sk/if_skvar.h

148

int reg;

sys/dev/netif/sln/if_slnreg.h

255

#define SLN_WRITE_4(adapter, reg, val) bus_space_write_4(adapter->sln_bustag, adapter->sln_bushandle, reg, val)

sys/dev/netif/sln/if_slnreg.h

256

#define SLN_WRITE_2(adapter, reg, val) bus_space_write_2(adapter->sln_bustag, adapter->sln_bushandle, reg, val)

sys/dev/netif/sln/if_slnreg.h

257

#define SLN_WRITE_1(adapter, reg, val) bus_space_write_1(adapter->sln_bustag, adapter->sln_bushandle, reg, val)

sys/dev/netif/sln/if_slnreg.h

259

#define SLN_READ_4(adapter, reg) bus_space_read_4(adapter->sln_bustag, adapter->sln_bushandle, reg)

sys/dev/netif/sln/if_slnreg.h

260

#define SLN_READ_2(adapter, reg) bus_space_read_2(adapter->sln_bustag, adapter->sln_bushandle, reg)

sys/dev/netif/sln/if_slnreg.h

261

#define SLN_READ_1(adapter, reg) bus_space_read_1(adapter->sln_bustag, adapter->sln_bushandle, reg)

sys/dev/netif/ste/if_ste.c

168

#define STE_SETBIT4(sc, reg, x) \

sys/dev/netif/ste/if_ste.c

169

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)

sys/dev/netif/ste/if_ste.c

171

#define STE_CLRBIT4(sc, reg, x) \

sys/dev/netif/ste/if_ste.c

172

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/ste/if_ste.c

174

#define STE_SETBIT2(sc, reg, x) \

sys/dev/netif/ste/if_ste.c

175

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)

sys/dev/netif/ste/if_ste.c

177

#define STE_CLRBIT2(sc, reg, x) \

sys/dev/netif/ste/if_ste.c

178

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)

sys/dev/netif/ste/if_ste.c

180

#define STE_SETBIT1(sc, reg, x) \

sys/dev/netif/ste/if_ste.c

181

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)

sys/dev/netif/ste/if_ste.c

183

#define STE_CLRBIT1(sc, reg, x) \

sys/dev/netif/ste/if_ste.c

184

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)

sys/dev/netif/ste/if_ste.c

362

ste_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/ste/if_ste.c

375

frame.mii_regaddr = reg;

sys/dev/netif/ste/if_ste.c

382

ste_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/ste/if_ste.c

391

frame.mii_regaddr = reg;

sys/dev/netif/ste/if_stereg.h

433

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/ste/if_stereg.h

434

bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)

sys/dev/netif/ste/if_stereg.h

435

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/ste/if_stereg.h

436

bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)

sys/dev/netif/ste/if_stereg.h

437

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/ste/if_stereg.h

438

bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)

sys/dev/netif/ste/if_stereg.h

440

#define CSR_READ_4(sc, reg) \

sys/dev/netif/ste/if_stereg.h

441

bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg)

sys/dev/netif/ste/if_stereg.h

442

#define CSR_READ_2(sc, reg) \

sys/dev/netif/ste/if_stereg.h

443

bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg)

sys/dev/netif/ste/if_stereg.h

444

#define CSR_READ_1(sc, reg) \

sys/dev/netif/ste/if_stereg.h

445

bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg)

sys/dev/netif/stge/if_stge.c

396

stge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/stge/if_stge.c

404

if (reg == STGE_PhyCtrl) {

sys/dev/netif/stge/if_stge.c

411

frame.mii_regaddr = reg;

sys/dev/netif/stge/if_stge.c

417

if (reg != 1)

sys/dev/netif/stge/if_stge.c

430

stge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/netif/stge/if_stge.c

440

frame.mii_regaddr = reg;

sys/dev/netif/stge/if_stgereg.h

100

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/netif/stge/if_stgereg.h

101

bus_space_write_2((_sc)->sc_btag, (_sc)->sc_bhandle, (reg), (val))

sys/dev/netif/stge/if_stgereg.h

102

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/netif/stge/if_stgereg.h

103

bus_space_write_1((_sc)->sc_btag, (_sc)->sc_bhandle, (reg), (val))

sys/dev/netif/stge/if_stgereg.h

105

#define CSR_READ_4(_sc, reg) \

sys/dev/netif/stge/if_stgereg.h

106

bus_space_read_4((_sc)->sc_btag, (_sc)->sc_bhandle, (reg))

sys/dev/netif/stge/if_stgereg.h

107

#define CSR_READ_2(_sc, reg) \

sys/dev/netif/stge/if_stgereg.h

108

bus_space_read_2((_sc)->sc_btag, (_sc)->sc_bhandle, (reg))

sys/dev/netif/stge/if_stgereg.h

109

#define CSR_READ_1(_sc, reg) \

sys/dev/netif/stge/if_stgereg.h

110

bus_space_read_1((_sc)->sc_btag, (_sc)->sc_bhandle, (reg))

sys/dev/netif/stge/if_stgereg.h

98

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/netif/stge/if_stgereg.h

99

bus_space_write_4((_sc)->sc_btag, (_sc)->sc_bhandle, (reg), (val))

sys/dev/netif/ti/if_tireg.h

1027

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/ti/if_tireg.h

1028

bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val)

sys/dev/netif/ti/if_tireg.h

1030

#define CSR_READ_4(sc, reg) \

sys/dev/netif/ti/if_tireg.h

1031

bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg)

sys/dev/netif/ti/if_tireg.h

1033

#define TI_SETBIT(sc, reg, x) \

sys/dev/netif/ti/if_tireg.h

1034

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

sys/dev/netif/ti/if_tireg.h

1035

#define TI_CLRBIT(sc, reg, x) \

sys/dev/netif/ti/if_tireg.h

1036

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

sys/dev/netif/tl/if_tl.c

360

tl_dio_read8(struct tl_softc *sc, int reg)

sys/dev/netif/tl/if_tl.c

362

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

363

return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));

sys/dev/netif/tl/if_tl.c

367

tl_dio_read16(struct tl_softc *sc, int reg)

sys/dev/netif/tl/if_tl.c

369

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

370

return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));

sys/dev/netif/tl/if_tl.c

374

tl_dio_read32(struct tl_softc *sc, int reg)

sys/dev/netif/tl/if_tl.c

376

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

377

return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));

sys/dev/netif/tl/if_tl.c

381

tl_dio_write8(struct tl_softc *sc, int reg, int val)

sys/dev/netif/tl/if_tl.c

383

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

384

CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);

sys/dev/netif/tl/if_tl.c

389

tl_dio_write16(struct tl_softc *sc, int reg, int val)

sys/dev/netif/tl/if_tl.c

391

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

392

CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);

sys/dev/netif/tl/if_tl.c

397

tl_dio_write32(struct tl_softc *sc, int reg, int val)

sys/dev/netif/tl/if_tl.c

399

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

400

CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);

sys/dev/netif/tl/if_tl.c

405

tl_dio_setbit(struct tl_softc *sc, int reg, int bit)

sys/dev/netif/tl/if_tl.c

409

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

410

f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));

sys/dev/netif/tl/if_tl.c

412

CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/netif/tl/if_tl.c

418

tl_dio_clrbit(struct tl_softc *sc, int reg, int bit)

sys/dev/netif/tl/if_tl.c

422

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

423

f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));

sys/dev/netif/tl/if_tl.c

425

CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/netif/tl/if_tl.c

431

tl_dio_setbit16(struct tl_softc *sc, int reg, int bit)

sys/dev/netif/tl/if_tl.c

435

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

436

f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));

sys/dev/netif/tl/if_tl.c

438

CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/netif/tl/if_tl.c

444

tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit)

sys/dev/netif/tl/if_tl.c

448

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/netif/tl/if_tl.c

449

f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));

sys/dev/netif/tl/if_tl.c

451

CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/netif/tl/if_tl.c

755

tl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/tl/if_tl.c

764

frame.mii_regaddr = reg;

sys/dev/netif/tl/if_tl.c

771

tl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/tl/if_tl.c

780

frame.mii_regaddr = reg;

sys/dev/netif/tl/if_tlreg.h

491

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/tl/if_tlreg.h

492

bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)

sys/dev/netif/tl/if_tlreg.h

493

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/tl/if_tlreg.h

494

bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)

sys/dev/netif/tl/if_tlreg.h

495

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/tl/if_tlreg.h

496

bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)

sys/dev/netif/tl/if_tlreg.h

498

#define CSR_READ_4(sc, reg) \

sys/dev/netif/tl/if_tlreg.h

499

bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)

sys/dev/netif/tl/if_tlreg.h

500

#define CSR_READ_2(sc, reg) \

sys/dev/netif/tl/if_tlreg.h

501

bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)

sys/dev/netif/tl/if_tlreg.h

502

#define CSR_READ_1(sc, reg) \

sys/dev/netif/tl/if_tlreg.h

503

bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)

sys/dev/netif/tx/if_tx.c

1544

epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)

sys/dev/netif/tx/if_tx.c

1548

CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));

sys/dev/netif/tx/if_tx.c

1559

epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)

sys/dev/netif/tx/if_tx.c

1564

CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));

sys/dev/netif/tx/if_tx.c

1575

epic_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/tx/if_tx.c

1581

return (PHY_READ_2(sc, phy, reg));

sys/dev/netif/tx/if_tx.c

1585

epic_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/tx/if_tx.c

1591

PHY_WRITE_2(sc, phy, reg, data);

sys/dev/netif/tx/if_txvar.h

106

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/tx/if_txvar.h

107

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/tx/if_txvar.h

108

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/tx/if_txvar.h

109

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/tx/if_txvar.h

110

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/tx/if_txvar.h

111

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/tx/if_txvar.h

112

#define CSR_READ_4(sc, reg) \

sys/dev/netif/tx/if_txvar.h

113

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/tx/if_txvar.h

114

#define CSR_READ_2(sc, reg) \

sys/dev/netif/tx/if_txvar.h

115

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/tx/if_txvar.h

116

#define CSR_READ_1(sc, reg) \

sys/dev/netif/tx/if_txvar.h

117

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/tx/if_txvar.h

119

#define PHY_READ_2(sc, phy, reg) \

sys/dev/netif/tx/if_txvar.h

120

epic_read_phy_reg((sc), (phy), (reg))

sys/dev/netif/tx/if_txvar.h

121

#define PHY_WRITE_2(sc, phy, reg, val) \

sys/dev/netif/tx/if_txvar.h

122

epic_write_phy_reg((sc), (phy), (reg), (val))

sys/dev/netif/txp/if_txpreg.h

633

#define WRITE_REG(sc,reg,val) \

sys/dev/netif/txp/if_txpreg.h

634

bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)

sys/dev/netif/txp/if_txpreg.h

635

#define READ_REG(sc,reg) \

sys/dev/netif/txp/if_txpreg.h

636

bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)

sys/dev/netif/vge/if_vge.c

351

vge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/vge/if_vge.c

365

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/netif/vge/if_vge.c

387

vge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/vge/if_vge.c

400

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/netif/vge/if_vgevar.h

134

#define CSR_WRITE_STREAM_4(sc, reg, val) \

sys/dev/netif/vge/if_vgevar.h

135

bus_space_write_stream_4(sc->vge_btag, sc->vge_bhandle, reg, val)

sys/dev/netif/vge/if_vgevar.h

136

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/vge/if_vgevar.h

137

bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)

sys/dev/netif/vge/if_vgevar.h

138

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/vge/if_vgevar.h

139

bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)

sys/dev/netif/vge/if_vgevar.h

140

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/vge/if_vgevar.h

141

bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)

sys/dev/netif/vge/if_vgevar.h

143

#define CSR_READ_4(sc, reg) \

sys/dev/netif/vge/if_vgevar.h

144

bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)

sys/dev/netif/vge/if_vgevar.h

145

#define CSR_READ_2(sc, reg) \

sys/dev/netif/vge/if_vgevar.h

146

bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)

sys/dev/netif/vge/if_vgevar.h

147

#define CSR_READ_1(sc, reg) \

sys/dev/netif/vge/if_vgevar.h

148

bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)

sys/dev/netif/vge/if_vgevar.h

150

#define CSR_SETBIT_1(sc, reg, x) \

sys/dev/netif/vge/if_vgevar.h

151

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/netif/vge/if_vgevar.h

152

#define CSR_SETBIT_2(sc, reg, x) \

sys/dev/netif/vge/if_vgevar.h

153

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

sys/dev/netif/vge/if_vgevar.h

154

#define CSR_SETBIT_4(sc, reg, x) \

sys/dev/netif/vge/if_vgevar.h

155

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/vge/if_vgevar.h

157

#define CSR_CLRBIT_1(sc, reg, x) \

sys/dev/netif/vge/if_vgevar.h

158

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/netif/vge/if_vgevar.h

159

#define CSR_CLRBIT_2(sc, reg, x) \

sys/dev/netif/vge/if_vgevar.h

160

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))

sys/dev/netif/vge/if_vgevar.h

161

#define CSR_CLRBIT_4(sc, reg, x) \

sys/dev/netif/vge/if_vgevar.h

162

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/vr/if_vr.c

208

#define VR_SETBIT(sc, reg, x) \

sys/dev/netif/vr/if_vr.c

209

CSR_WRITE_1(sc, reg, \

sys/dev/netif/vr/if_vr.c

210

CSR_READ_1(sc, reg) | (x))

sys/dev/netif/vr/if_vr.c

212

#define VR_CLRBIT(sc, reg, x) \

sys/dev/netif/vr/if_vr.c

213

CSR_WRITE_1(sc, reg, \

sys/dev/netif/vr/if_vr.c

214

CSR_READ_1(sc, reg) & ~(x))

sys/dev/netif/vr/if_vr.c

216

#define VR_SETBIT16(sc, reg, x) \

sys/dev/netif/vr/if_vr.c

217

CSR_WRITE_2(sc, reg, \

sys/dev/netif/vr/if_vr.c

218

CSR_READ_2(sc, reg) | (x))

sys/dev/netif/vr/if_vr.c

220

#define VR_CLRBIT16(sc, reg, x) \

sys/dev/netif/vr/if_vr.c

221

CSR_WRITE_2(sc, reg, \

sys/dev/netif/vr/if_vr.c

222

CSR_READ_2(sc, reg) & ~(x))

sys/dev/netif/vr/if_vr.c

224

#define VR_SETBIT32(sc, reg, x) \

sys/dev/netif/vr/if_vr.c

225

CSR_WRITE_4(sc, reg, \

sys/dev/netif/vr/if_vr.c

226

CSR_READ_4(sc, reg) | (x))

sys/dev/netif/vr/if_vr.c

228

#define VR_CLRBIT32(sc, reg, x) \

sys/dev/netif/vr/if_vr.c

229

CSR_WRITE_4(sc, reg, \

sys/dev/netif/vr/if_vr.c

230

CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/vr/if_vr.c

449

vr_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/vr/if_vr.c

468

frame.mii_regaddr = reg;

sys/dev/netif/vr/if_vr.c

475

vr_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/vr/if_vr.c

494

frame.mii_regaddr = reg;

sys/dev/netif/vr/if_vrreg.h

483

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/vr/if_vrreg.h

484

bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)

sys/dev/netif/vr/if_vrreg.h

485

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/vr/if_vrreg.h

486

bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)

sys/dev/netif/vr/if_vrreg.h

487

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/vr/if_vrreg.h

488

bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)

sys/dev/netif/vr/if_vrreg.h

490

#define CSR_READ_4(sc, reg) \

sys/dev/netif/vr/if_vrreg.h

491

bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)

sys/dev/netif/vr/if_vrreg.h

492

#define CSR_READ_2(sc, reg) \

sys/dev/netif/vr/if_vrreg.h

493

bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)

sys/dev/netif/vr/if_vrreg.h

494

#define CSR_READ_1(sc, reg) \

sys/dev/netif/vr/if_vrreg.h

495

bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)

sys/dev/netif/wb/if_wb.c

213

#define WB_SETBIT(sc, reg, x) \

sys/dev/netif/wb/if_wb.c

214

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/wb/if_wb.c

216

#define WB_CLRBIT(sc, reg, x) \

sys/dev/netif/wb/if_wb.c

217

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/wb/if_wb.c

485

wb_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/wb/if_wb.c

493

frame.mii_regaddr = reg;

sys/dev/netif/wb/if_wb.c

500

wb_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/wb/if_wb.c

508

frame.mii_regaddr = reg;

sys/dev/netif/wb/if_wbreg.h

386

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/wb/if_wbreg.h

387

bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)

sys/dev/netif/wb/if_wbreg.h

388

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/wb/if_wbreg.h

389

bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)

sys/dev/netif/wb/if_wbreg.h

390

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/wb/if_wbreg.h

391

bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)

sys/dev/netif/wb/if_wbreg.h

393

#define CSR_READ_4(sc, reg) \

sys/dev/netif/wb/if_wbreg.h

394

bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)

sys/dev/netif/wb/if_wbreg.h

395

#define CSR_READ_2(sc, reg) \

sys/dev/netif/wb/if_wbreg.h

396

bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)

sys/dev/netif/wb/if_wbreg.h

397

#define CSR_READ_1(sc, reg) \

sys/dev/netif/wb/if_wbreg.h

398

bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)

sys/dev/netif/wi/if_wi_pci.c

160

u_int16_t reg;

sys/dev/netif/wi/if_wi_pci.c

208

reg = CSM_READ_1(sc, WI_COR_OFFSET);

sys/dev/netif/wi/if_wi_pci.c

209

if (reg != WI_COR_VALUE) {

sys/dev/netif/wi/if_wi_pci.c

211

"wanted %d, got %d\n", WI_COR_VALUE, reg);

sys/dev/netif/wi/if_wi_pci.c

239

reg = CSR_READ_2(sc, WI_HFA384X_SWSUPPORT0_OFF);

sys/dev/netif/wi/if_wi_pci.c

240

if (reg != WI_PRISM2STA_MAGIC) {

sys/dev/netif/wi/if_wi_pci.c

243

"wanted %d, got %d\n", WI_PRISM2STA_MAGIC, reg);

sys/dev/netif/wi/if_wireg.h

105

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/wi/if_wireg.h

107

(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)

sys/dev/netif/wi/if_wireg.h

108

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/wi/if_wireg.h

110

(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)

sys/dev/netif/wi/if_wireg.h

111

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/wi/if_wireg.h

113

(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)

sys/dev/netif/wi/if_wireg.h

115

#define CSR_READ_4(sc, reg) \

sys/dev/netif/wi/if_wireg.h

117

(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))

sys/dev/netif/wi/if_wireg.h

118

#define CSR_READ_2(sc, reg) \

sys/dev/netif/wi/if_wireg.h

120

(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))

sys/dev/netif/wi/if_wireg.h

121

#define CSR_READ_1(sc, reg) \

sys/dev/netif/wi/if_wireg.h

123

(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))

sys/dev/netif/wi/if_wireg.h

131

#define CSR_WRITE_STREAM_2(sc, reg, val) \

sys/dev/netif/wi/if_wireg.h

133

(sc->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg) * 2 : (reg)), val)

sys/dev/netif/wi/if_wireg.h

134

#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \

sys/dev/netif/wi/if_wireg.h

136

(sc->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg) * 2 : (reg)), val, count)

sys/dev/netif/wi/if_wireg.h

137

#define CSR_READ_STREAM_2(sc, reg) \

sys/dev/netif/wi/if_wireg.h

139

(sc->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg) * 2 : (reg)))

sys/dev/netif/wi/if_wireg.h

140

#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \

sys/dev/netif/wi/if_wireg.h

142

(sc->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg) * 2 : (reg)), buf, count)

sys/dev/netif/wpi/if_wpi.c

3846

uint32_t max, reg;

sys/dev/netif/wpi/if_wpi.c

3865

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINKCTRL, 1);

sys/dev/netif/wpi/if_wpi.c

3866

if (!(reg & PCIEM_LNKCTL_ASPM_L0S)) /* L0s Entry disabled. */

sys/dev/netif/wpi/if_wpi.c

3869

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);

sys/dev/netif/wpi/if_wpi.c

3870

if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */

sys/dev/netif/wpi/if_wpi.c

5195

uint32_t reg;

sys/dev/netif/wpi/if_wpi.c

5210

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINKCTRL, 1);

sys/dev/netif/wpi/if_wpi.c

5212

if (reg & PCIEM_LNKCTL_ASPM_L1) /* L1 Entry enabled. */

sys/dev/netif/wpi/if_wpi.c

5214

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);

sys/dev/netif/wpi/if_wpi.c

5216

if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */

sys/dev/netif/wpi/if_wpireg.h

1016

#define WPI_READ(sc, reg) \

sys/dev/netif/wpi/if_wpireg.h

1017

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/netif/wpi/if_wpireg.h

1019

#define WPI_WRITE(sc, reg, val) \

sys/dev/netif/wpi/if_wpireg.h

1020

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/netif/wpi/if_wpireg.h

1026

#define WPI_SETBITS(sc, reg, mask) \

sys/dev/netif/wpi/if_wpireg.h

1027

WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask))

sys/dev/netif/wpi/if_wpireg.h

1029

#define WPI_CLRBITS(sc, reg, mask) \

sys/dev/netif/wpi/if_wpireg.h

1030

WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask))

sys/dev/netif/xe/if_xe.c

1403

uint8_t page, reg;

sys/dev/netif/xe/if_xe.c

1413

reg = 0x0e - 2 * (idx%4);

sys/dev/netif/xe/if_xe.c

1416

idx+1, page, reg));

sys/dev/netif/xe/if_xe.c

1431

XE_OUTB(reg, addr[scp->mohawk ? 5 - i : i]);

sys/dev/netif/xe/if_xe.c

1432

if (++reg == 0x10) {

sys/dev/netif/xe/if_xe.c

1433

reg = 0x08;

sys/dev/netif/xe/if_xe.c

181

static u_int16_t xe_phy_readreg (struct xe_softc *scp, u_int16_t reg);

sys/dev/netif/xe/if_xe.c

1814

xe_phy_readreg(struct xe_softc *scp, u_int16_t reg) {

sys/dev/netif/xe/if_xe.c

182

static void xe_phy_writereg (struct xe_softc *scp, u_int16_t reg, u_int16_t data);

sys/dev/netif/xe/if_xe.c

1820

frame.mii_regaddr = reg;

sys/dev/netif/xe/if_xe.c

1831

xe_phy_writereg(struct xe_softc *scp, u_int16_t reg, u_int16_t data) {

sys/dev/netif/xe/if_xe.c

1837

frame.mii_regaddr = reg;

sys/dev/netif/xl/if_xl.c

528

xl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/netif/xl/if_xl.c

548

frame.mii_regaddr = reg;

sys/dev/netif/xl/if_xl.c

555

xl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/netif/xl/if_xl.c

568

frame.mii_regaddr = reg;

sys/dev/netif/xl/if_xlreg.h

638

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/netif/xl/if_xlreg.h

639

bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)

sys/dev/netif/xl/if_xlreg.h

640

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/netif/xl/if_xlreg.h

641

bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)

sys/dev/netif/xl/if_xlreg.h

642

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/netif/xl/if_xlreg.h

643

bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)

sys/dev/netif/xl/if_xlreg.h

645

#define CSR_READ_4(sc, reg) \

sys/dev/netif/xl/if_xlreg.h

646

bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)

sys/dev/netif/xl/if_xlreg.h

647

#define CSR_READ_2(sc, reg) \

sys/dev/netif/xl/if_xlreg.h

648

bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)

sys/dev/netif/xl/if_xlreg.h

649

#define CSR_READ_1(sc, reg) \

sys/dev/netif/xl/if_xlreg.h

650

bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)

sys/dev/pccard/cardbus/cardbus_cis.c

299

uint8_t reg;

sys/dev/pccard/cardbus/cardbus_cis.c

307

reg = *tupledata;

sys/dev/pccard/cardbus/cardbus_cis.c

309

if (reg & TPL_BAR_REG_AS) {

sys/dev/pccard/cardbus/cardbus_cis.c

315

bar = reg & TPL_BAR_REG_ASI_MASK;

sys/dev/pccard/cardbus/cardbus_cis.c

328

if (reg & TPL_BAR_REG_PREFETCHABLE)

sys/dev/pccard/cardbus/cardbus_cis.c

350

if (reg & TPL_BAR_REG_BELOW1MB)

sys/dev/pccard/exca/exca.c

142

exca_mem_getb(struct exca_softc *sc, int reg)

sys/dev/pccard/exca/exca.c

144

return (bus_space_read_1(sc->bst, sc->bsh, sc->offset + reg));

sys/dev/pccard/exca/exca.c

148

exca_mem_putb(struct exca_softc *sc, int reg, uint8_t val)

sys/dev/pccard/exca/exca.c

150

bus_space_write_1(sc->bst, sc->bsh, sc->offset + reg, val);

sys/dev/pccard/exca/exca.c

154

exca_io_getb(struct exca_softc *sc, int reg)

sys/dev/pccard/exca/exca.c

156

bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset);

sys/dev/pccard/exca/exca.c

161

exca_io_putb(struct exca_softc *sc, int reg, uint8_t val)

sys/dev/pccard/exca/exca.c

163

bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset);

sys/dev/pccard/exca/excavar.h

130

exca_getb(struct exca_softc *sc, int reg)

sys/dev/pccard/exca/excavar.h

132

return (sc->getb(sc, reg));

sys/dev/pccard/exca/excavar.h

136

exca_putb(struct exca_softc *sc, int reg, uint8_t val)

sys/dev/pccard/exca/excavar.h

138

sc->putb(sc, reg, val);

sys/dev/pccard/exca/excavar.h

142

exca_setb(struct exca_softc *sc, int reg, uint8_t mask)

sys/dev/pccard/exca/excavar.h

144

exca_putb(sc, reg, exca_getb(sc, reg) | mask);

sys/dev/pccard/exca/excavar.h

148

exca_clrb(struct exca_softc *sc, int reg, uint8_t mask)

sys/dev/pccard/exca/excavar.h

150

exca_putb(sc, reg, exca_getb(sc, reg) & ~mask);

sys/dev/pccard/pccbb/pccbb.c

1006

uint32_t reg;

sys/dev/pccard/pccbb/pccbb.c

1100

reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2);

sys/dev/pccard/pccbb/pccbb.c

1101

reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0|

sys/dev/pccard/pccbb/pccbb.c

1103

reg |= (prefetchable[0]?CBBM_BRIDGECTRL_PREFETCH_0:0)|

sys/dev/pccard/pccbb/pccbb.c

1105

pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2);

sys/dev/pccard/pccbb/pccbb.c

1511

cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width)

sys/dev/pccard/pccbb/pccbb.c

1519

b, s, f, reg, width);

sys/dev/pccard/pccbb/pccbb.c

1524

cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val,

sys/dev/pccard/pccbb/pccbb.c

1531

b, s, f, reg, val, width);

sys/dev/pccard/pccbb/pccbb.c

255

uint8_t reg;

sys/dev/pccard/pccbb/pccbb.c

256

reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) |

sys/dev/pccard/pccbb/pccbb.c

258

exca_putb(&sc->exca[0], EXCA_INTR, reg);

sys/dev/pccard/pccbb/pccbb.c

272

uint8_t reg;

sys/dev/pccard/pccbb/pccbb.c

274

reg = (exca_getb(&sc->exca[0], EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) |

sys/dev/pccard/pccbb/pccbb.c

276

exca_putb(&sc->exca[0], EXCA_INTR, reg);

sys/dev/pccard/pccbb/pccbb.c

683

uint8_t reg;

sys/dev/pccard/pccbb/pccbb.c

714

reg = exca_getb(&sc->exca[0], EXCA_INTR);

sys/dev/pccard/pccbb/pccbb.c

715

exca_putb(&sc->exca[0], EXCA_INTR, (reg & 0xf0) | 1);

sys/dev/pccard/pccbb/pccbb.c

716

return (reg);

sys/dev/pccard/pccbb/pccbb.c

725

cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg)

sys/dev/pccard/pccbb/pccbb.c

727

exca_putb(&sc->exca[0], EXCA_INTR, reg);

sys/dev/pccard/pccbb/pccbb.c

738

uint8_t reg = 0;

sys/dev/pccard/pccbb/pccbb.c

774

reg = cbb_o2micro_power_hack(sc);

sys/dev/pccard/pccbb/pccbb.c

832

cbb_o2micro_power_hack2(sc, reg);

sys/dev/pccard/pccbb/pccbb_pci.c

424

uint32_t mux, sysctrl, reg;

sys/dev/pccard/pccbb/pccbb_pci.c

533

reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);

sys/dev/pccard/pccbb/pccbb_pci.c

534

reg = (reg & 0x0f) |

sys/dev/pccard/pccbb/pccbb_pci.c

536

exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);

sys/dev/pccard/pccbb/pccbbvar.h

139

int reg, int width);

sys/dev/pccard/pccbb/pccbbvar.h

153

int reg, uint32_t val, int width);

sys/dev/pccard/pccbb/pccbbvar.h

160

cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pccard/pccbb/pccbbvar.h

162

bus_space_write_4(sc->bst, sc->bsh, reg, val);

sys/dev/pccard/pccbb/pccbbvar.h

166

cbb_get(struct cbb_softc *sc, uint32_t reg)

sys/dev/pccard/pccbb/pccbbvar.h

168

return (bus_space_read_4(sc->bst, sc->bsh, reg));

sys/dev/pccard/pccbb/pccbbvar.h

172

cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pccard/pccbb/pccbbvar.h

174

cbb_set(sc, reg, cbb_get(sc, reg) | bits);

sys/dev/pccard/pccbb/pccbbvar.h

178

cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pccard/pccbb/pccbbvar.h

180

cbb_set(sc, reg, cbb_get(sc, reg) & ~bits);

sys/dev/powermng/intpm/intpm.c

125

amd_pmio_read(struct resource *res, uint8_t reg)

sys/dev/powermng/intpm/intpm.c

127

bus_write_1(res, 0, reg); /* Index */

sys/dev/powermng/it/it.c

193

it_readreg(struct it_softc *sc, int reg)

sys/dev/powermng/it/it.c

195

bus_space_write_1(sc->sc_iot, sc->sc_ioh, ITC_ADDR, reg);

sys/dev/powermng/it/it.c

200

it_writereg(struct it_softc *sc, int reg, int val)

sys/dev/powermng/it/it.c

202

bus_space_write_1(sc->sc_iot, sc->sc_ioh, ITC_ADDR, reg);

sys/dev/powermng/lm/lm78.c

672

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

688

sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

713

if (sc->lm_sensors[n].reg == LM_FAN1 ||

sys/dev/powermng/lm/lm78.c

714

sc->lm_sensors[n].reg == LM_FAN2) {

sys/dev/powermng/lm/lm78.c

716

if (sc->lm_sensors[n].reg == LM_FAN1)

sys/dev/powermng/lm/lm78.c

722

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

758

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

778

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

791

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

811

sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg) << 1;

sys/dev/powermng/lm/lm78.c

812

sdata += sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1) >> 7;

sys/dev/powermng/lm/lm78.c

835

if (sc->lm_sensors[n].reg == LM_FAN1 ||

sys/dev/powermng/lm/lm78.c

836

sc->lm_sensors[n].reg == LM_FAN2 ||

sys/dev/powermng/lm/lm78.c

837

sc->lm_sensors[n].reg == LM_FAN3) {

sys/dev/powermng/lm/lm78.c

839

fan = (sc->lm_sensors[n].reg - LM_FAN1);

sys/dev/powermng/lm/lm78.c

844

if (sc->lm_sensors[n].reg == LM_FAN1 ||

sys/dev/powermng/lm/lm78.c

845

sc->lm_sensors[n].reg == LM_FAN2) {

sys/dev/powermng/lm/lm78.c

847

if (sc->lm_sensors[n].reg == LM_FAN1)

sys/dev/powermng/lm/lm78.c

851

} else if (sc->lm_sensors[n].reg == LM_FAN3) {

sys/dev/powermng/lm/lm78.c

854

} else if (sc->lm_sensors[n].reg == WB_BANK0_FAN4 ||

sys/dev/powermng/lm/lm78.c

855

sc->lm_sensors[n].reg == WB_BANK0_FAN5) {

sys/dev/powermng/lm/lm78.c

857

if (sc->lm_sensors[n].reg == WB_BANK0_FAN4)

sys/dev/powermng/lm/lm78.c

863

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

877

int reg, shift, data, divisor = 1;

sys/dev/powermng/lm/lm78.c

879

switch (sc->lm_sensors[n].reg) {

sys/dev/powermng/lm/lm78.c

881

reg = 0x47; shift = 0;

sys/dev/powermng/lm/lm78.c

884

reg = 0x47; shift = 4;

sys/dev/powermng/lm/lm78.c

887

reg = 0x5b; shift = 0;

sys/dev/powermng/lm/lm78.c

890

reg = 0x5b; shift = 4;

sys/dev/powermng/lm/lm78.c

893

reg = 0x5c; shift = 0;

sys/dev/powermng/lm/lm78.c

896

reg = 0x5c; shift = 4;

sys/dev/powermng/lm/lm78.c

899

reg = 0x9e; shift = 0;

sys/dev/powermng/lm/lm78.c

902

reg = 0; shift = 0;

sys/dev/powermng/lm/lm78.c

906

data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

911

if (reg != 0)

sys/dev/powermng/lm/lm78.c

912

divisor = (sc->lm_readreg(sc, reg) >> shift) & 0x7;

sys/dev/powermng/lm/lm78.c

924

datah = sc->lm_readreg(sc, sc->lm_sensors[n].reg);

sys/dev/powermng/lm/lm78.c

925

datal = sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1);

sys/dev/powermng/lm/lm78.c

946

sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg) << 1;

sys/dev/powermng/lm/lm78.c

947

sdata += sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1) >> 7;

sys/dev/powermng/lm/lm78_isa.c

247

lm_isa_readreg(struct lm_softc *lmsc, int reg)

sys/dev/powermng/lm/lm78_isa.c

251

bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_ADDR, reg);

sys/dev/powermng/lm/lm78_isa.c

256

lm_isa_writereg(struct lm_softc *lmsc, int reg, int val)

sys/dev/powermng/lm/lm78_isa.c

260

bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_ADDR, reg);

sys/dev/powermng/lm/lm78var.h

134

u_int8_t reg;

sys/dev/powermng/memtemp/memtemp_e5.c

354

int temp, reg;

sys/dev/powermng/memtemp/memtemp_e5.c

356

reg = PCI_E5_IMC_THERMAL_DIMMTEMPSTAT(dimm_sc->dimm_id);

sys/dev/powermng/memtemp/memtemp_e5.c

358

val = pci_read_config(dev, reg, 4);

sys/dev/powermng/memtemp/memtemp_e5.c

362

pci_write_config(dev, reg, val, 4);

sys/dev/powermng/uguru/uguru.c

1000

if (uguru_write_multi(iot, ioh, idx + 1, &reg, sizeof(reg)) ||

sys/dev/powermng/uguru/uguru.c

1011

idx, reg, val, data[0], data[1], data[2]);

sys/dev/powermng/uguru/uguru.c

1019

uint16_t reg;

sys/dev/powermng/uguru/uguru.c

1023

reg = sc->uguru_sensors[n].reg | 0x0880;

sys/dev/powermng/uguru/uguru.c

1024

if (uguru_ac5_read(sc->sc_iot, sc->sc_ioh, reg, &val, sizeof(val)))

sys/dev/powermng/uguru/uguru.c

1033

uint16_t reg, void *data, int count)

sys/dev/powermng/uguru/uguru.c

1037

buf[0] = reg >> 8;

sys/dev/powermng/uguru/uguru.c

1038

buf[1] = reg & 0xff;

sys/dev/powermng/uguru/uguru.c

121

uint8_t reg;

sys/dev/powermng/uguru/uguru.c

38

#define UGURU_READ(iot, ioh, reg) \

sys/dev/powermng/uguru/uguru.c

39

bus_space_read_1((iot), (ioh), (reg))

sys/dev/powermng/uguru/uguru.c

40

#define UGURU_WRITE(iot, ioh, reg, val) \

sys/dev/powermng/uguru/uguru.c

41

bus_space_write_1((iot), (ioh), (reg), (val))

sys/dev/powermng/uguru/uguru.c

981

uint8_t reg = sc->uguru_sensors[n].reg;

sys/dev/powermng/uguru/uguru.c

992

if (uguru_write_multi(iot, ioh, idx, &reg, sizeof(reg)) ||

sys/dev/raid/aac/aacvar.h

273

#define AAC_MEM0_SETREG4(sc, reg, val) bus_space_write_4(sc->aac_btag0, \

sys/dev/raid/aac/aacvar.h

274

sc->aac_bhandle0, reg, val)

sys/dev/raid/aac/aacvar.h

275

#define AAC_MEM0_GETREG4(sc, reg) bus_space_read_4(sc->aac_btag0, \

sys/dev/raid/aac/aacvar.h

276

sc->aac_bhandle0, reg)

sys/dev/raid/aac/aacvar.h

277

#define AAC_MEM0_SETREG2(sc, reg, val) bus_space_write_2(sc->aac_btag0, \

sys/dev/raid/aac/aacvar.h

278

sc->aac_bhandle0, reg, val)

sys/dev/raid/aac/aacvar.h

279

#define AAC_MEM0_GETREG2(sc, reg) bus_space_read_2(sc->aac_btag0, \

sys/dev/raid/aac/aacvar.h

280

sc->aac_bhandle0, reg)

sys/dev/raid/aac/aacvar.h

281

#define AAC_MEM0_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag0, \

sys/dev/raid/aac/aacvar.h

282

sc->aac_bhandle0, reg, val)

sys/dev/raid/aac/aacvar.h

283

#define AAC_MEM0_GETREG1(sc, reg) bus_space_read_1(sc->aac_btag0, \

sys/dev/raid/aac/aacvar.h

284

sc->aac_bhandle0, reg)

sys/dev/raid/aac/aacvar.h

286

#define AAC_MEM1_SETREG4(sc, reg, val) bus_space_write_4(sc->aac_btag1, \

sys/dev/raid/aac/aacvar.h

287

sc->aac_bhandle1, reg, val)

sys/dev/raid/aac/aacvar.h

288

#define AAC_MEM1_GETREG4(sc, reg) bus_space_read_4(sc->aac_btag1, \

sys/dev/raid/aac/aacvar.h

289

sc->aac_bhandle1, reg)

sys/dev/raid/aac/aacvar.h

290

#define AAC_MEM1_SETREG2(sc, reg, val) bus_space_write_2(sc->aac_btag1, \

sys/dev/raid/aac/aacvar.h

291

sc->aac_bhandle1, reg, val)

sys/dev/raid/aac/aacvar.h

292

#define AAC_MEM1_GETREG2(sc, reg) bus_space_read_2(sc->aac_btag1, \

sys/dev/raid/aac/aacvar.h

293

sc->aac_bhandle1, reg)

sys/dev/raid/aac/aacvar.h

294

#define AAC_MEM1_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag1, \

sys/dev/raid/aac/aacvar.h

295

sc->aac_bhandle1, reg, val)

sys/dev/raid/aac/aacvar.h

296

#define AAC_MEM1_GETREG1(sc, reg) bus_space_read_1(sc->aac_btag1, \

sys/dev/raid/aac/aacvar.h

297

sc->aac_bhandle1, reg)

sys/dev/raid/amr/amrreg.h

648

#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val)

sys/dev/raid/dpt/dpt_scsi.c

183

dpt_pio_wait (u_int32_t base, u_int reg, u_int bits, u_int state)

sys/dev/raid/dpt/dpt_scsi.c

189

c = inb(base + reg) & bits;

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

81

HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

83

return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1);

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

85

HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

87

return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

89

void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v)

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

91

pci_cfgregwrite(bus, dev, func, reg, v, 1);

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

93

void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)

sys/dev/raid/hpt27xx/hpt27xx_os_bsd.c

95

pci_cfgregwrite(bus, dev, func, reg, v, 4);

sys/dev/raid/hpt27xx/osm.h

157

HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);

sys/dev/raid/hpt27xx/osm.h

158

HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);

sys/dev/raid/hpt27xx/osm.h

159

void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v);

sys/dev/raid/hpt27xx/osm.h

160

void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v);

sys/dev/raid/hptrr/osm.h

126

#define pcicfg_read_dword(bus, dev, fn, reg) 0xffff

sys/dev/raid/mfi/mfivar.h

572

#define MFI_WRITE4(sc, reg, val) bus_space_write_4((sc)->mfi_btag, \

sys/dev/raid/mfi/mfivar.h

573

sc->mfi_bhandle, (reg), (val))

sys/dev/raid/mfi/mfivar.h

574

#define MFI_READ4(sc, reg) bus_space_read_4((sc)->mfi_btag, \

sys/dev/raid/mfi/mfivar.h

575

(sc)->mfi_bhandle, (reg))

sys/dev/raid/mfi/mfivar.h

576

#define MFI_WRITE2(sc, reg, val) bus_space_write_2((sc)->mfi_btag, \

sys/dev/raid/mfi/mfivar.h

577

sc->mfi_bhandle, (reg), (val))

sys/dev/raid/mfi/mfivar.h

578

#define MFI_READ2(sc, reg) bus_space_read_2((sc)->mfi_btag, \

sys/dev/raid/mfi/mfivar.h

579

(sc)->mfi_bhandle, (reg))

sys/dev/raid/mfi/mfivar.h

580

#define MFI_WRITE1(sc, reg, val) bus_space_write_1((sc)->mfi_btag, \

sys/dev/raid/mfi/mfivar.h

581

sc->mfi_bhandle, (reg), (val))

sys/dev/raid/mfi/mfivar.h

582

#define MFI_READ1(sc, reg) bus_space_read_1((sc)->mfi_btag, \

sys/dev/raid/mfi/mfivar.h

583

(sc)->mfi_bhandle, (reg))

sys/dev/raid/mly/mlyvar.h

239

#define MLY_SET_REG(sc, reg, val) bus_space_write_1(sc->mly_btag, sc->mly_bhandle, reg, val)

sys/dev/raid/mly/mlyvar.h

240

#define MLY_GET_REG(sc, reg) bus_space_read_1 (sc->mly_btag, sc->mly_bhandle, reg)

sys/dev/raid/mly/mlyvar.h

241

#define MLY_GET_REG2(sc, reg) bus_space_read_2 (sc->mly_btag, sc->mly_bhandle, reg)

sys/dev/raid/mly/mlyvar.h

242

#define MLY_GET_REG4(sc, reg) bus_space_read_4 (sc->mly_btag, sc->mly_bhandle, reg)

sys/dev/raid/mpr/mpr.c

144

uint32_t reg;

sys/dev/raid/mpr/mpr.c

170

reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/raid/mpr/mpr.c

171

if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {

sys/dev/raid/mpr/mpr.c

183

reg |= MPI2_DIAG_RESET_ADAPTER;

sys/dev/raid/mpr/mpr.c

185

reg);

sys/dev/raid/mpr/mpr.c

186

mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg);

sys/dev/raid/mpr/mpr.c

212

reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/raid/mpr/mpr.c

213

if (reg & MPI2_DIAG_RESET_ADAPTER) {

sys/dev/raid/mpr/mpr.c

216

reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/raid/mpr/mpr.c

217

if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {

sys/dev/raid/mpr/mpr.c

261

uint32_t reg, state;

sys/dev/raid/mpr/mpr.c

276

reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/raid/mpr/mpr.c

277

mpr_dprint(sc, MPR_INIT, " Doorbell= 0x%x\n", reg);

sys/dev/raid/mpr/mpr.c

283

if (reg & MPI2_DOORBELL_USED) {

sys/dev/raid/mpr/mpr.c

292

if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==

sys/dev/raid/mpr/mpr.c

301

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/raid/mpr/mpr.c

339

uint32_t reg, state;

sys/dev/raid/mpr/mpr.c

345

reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/raid/mpr/mpr.c

346

mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg);

sys/dev/raid/mpr/mpr.c

348

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/raid/mps/mps.c

123

uint32_t reg;

sys/dev/raid/mps/mps.c

140

reg = mps_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/raid/mps/mps.c

141

if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {

sys/dev/raid/mps/mps.c

151

reg | MPI2_DIAG_RESET_ADAPTER);

sys/dev/raid/mps/mps.c

157

reg = mps_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/raid/mps/mps.c

158

if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {

sys/dev/raid/mps/mps.c

188

uint32_t reg, state;

sys/dev/raid/mps/mps.c

195

reg = mps_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/raid/mps/mps.c

196

mps_dprint(sc, MPS_INFO, "Doorbell= 0x%x\n", reg);

sys/dev/raid/mps/mps.c

202

if (reg & MPI2_DOORBELL_USED) {

sys/dev/raid/mps/mps.c

209

if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==

sys/dev/raid/mps/mps.c

216

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/raid/mps/mps.c

252

uint32_t reg, state;

sys/dev/raid/mps/mps.c

258

reg = mps_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/raid/mps/mps.c

259

mps_dprint(sc, MPS_INFO, "Doorbell= 0x%x\n", reg);

sys/dev/raid/mps/mps.c

261

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/raid/twa/tw_cl_externs.h

159

extern TW_INT8 *tw_cli_describe_bits(TW_UINT32 reg, TW_INT8 *str);

sys/dev/raid/twa/tw_cl_misc.c

826

tw_cli_describe_bits(TW_UINT32 reg, TW_INT8 *str)

sys/dev/raid/twa/tw_cl_misc.c

830

if (reg & TWA_STATUS_COMMAND_QUEUE_EMPTY)

sys/dev/raid/twa/tw_cl_misc.c

832

if (reg & TWA_STATUS_MICROCONTROLLER_READY)

sys/dev/raid/twa/tw_cl_misc.c

834

if (reg & TWA_STATUS_RESPONSE_QUEUE_EMPTY)

sys/dev/raid/twa/tw_cl_misc.c

836

if (reg & TWA_STATUS_COMMAND_QUEUE_FULL)

sys/dev/raid/twa/tw_cl_misc.c

838

if (reg & TWA_STATUS_RESPONSE_INTERRUPT)

sys/dev/raid/twa/tw_cl_misc.c

840

if (reg & TWA_STATUS_COMMAND_INTERRUPT)

sys/dev/raid/twa/tw_cl_misc.c

842

if (reg & TWA_STATUS_ATTENTION_INTERRUPT)

sys/dev/raid/twa/tw_cl_misc.c

844

if (reg & TWA_STATUS_HOST_INTERRUPT)

sys/dev/raid/twa/tw_cl_misc.c

846

if (reg & TWA_STATUS_PCI_ABORT_INTERRUPT)

sys/dev/raid/twa/tw_cl_misc.c

848

if (reg & TWA_STATUS_QUEUE_ERROR_INTERRUPT)

sys/dev/raid/twa/tw_cl_misc.c

850

if (reg & TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT)

sys/dev/raid/tws/tws.c

351

u_int32_t reg;

sys/dev/raid/tws/tws.c

363

reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);

sys/dev/raid/tws/tws.c

364

TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0);

sys/dev/raid/tws/tws.c

452

u_int32_t reg;

sys/dev/raid/tws/tws.c

557

reg = tws_read_reg(sc, TWS_I2O0_CTL, 4);

sys/dev/raid/tws/tws.c

558

TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL);

sys/dev/raid/tws/tws.c

559

tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4);

sys/dev/raid/tws/tws_cam.c

1225

u_int32_t reg;

sys/dev/raid/tws/tws_cam.c

1230

reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);

sys/dev/raid/tws/tws_cam.c

1231

if (!( reg & TWS_BIT13 )) {

sys/dev/raid/tws/tws_cam.c

498

u_int32_t reg, status;

sys/dev/raid/tws/tws_cam.c

534

reg = (u_int32_t)( mfa>>32);

sys/dev/raid/tws/tws_cam.c

535

tws_write_reg(sc, TWS_I2O0_HOBQPH, reg, 4);

sys/dev/raid/tws/tws_cam.c

536

reg = (u_int32_t)(mfa);

sys/dev/raid/tws/tws_cam.c

537

tws_write_reg(sc, TWS_I2O0_HOBQPL, reg, 4);

sys/dev/raid/tws/tws_hdm.c

104

reg = (((u_int64_t)regh) << 32) | regl;

sys/dev/raid/tws/tws_hdm.c

106

TWS_TRACE_DEBUG(sc, "host outbound cleanup", reg, regl);

sys/dev/raid/tws/tws_hdm.c

410

u_int32_t reg;

sys/dev/raid/tws/tws_hdm.c

412

reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);

sys/dev/raid/tws/tws_hdm.c

413

if ( reg & TWS_BIT13 )

sys/dev/raid/tws/tws_hdm.c

442

u_int32_t reg;

sys/dev/raid/tws/tws_hdm.c

445

reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);

sys/dev/raid/tws/tws_hdm.c

446

reg = reg | TWS_BIT2;

sys/dev/raid/tws/tws_hdm.c

447

tws_write_reg(sc, TWS_I2O0_HIMASK, reg, 4);

sys/dev/raid/tws/tws_hdm.c

453

u_int32_t reg;

sys/dev/raid/tws/tws_hdm.c

456

reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);

sys/dev/raid/tws/tws_hdm.c

457

reg = reg & ~TWS_BIT2;

sys/dev/raid/tws/tws_hdm.c

458

tws_write_reg(sc, TWS_I2O0_HIMASK, reg, 4);

sys/dev/raid/tws/tws_hdm.c

465

u_int32_t reg;

sys/dev/raid/tws/tws_hdm.c

474

reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);

sys/dev/raid/tws/tws_hdm.c

475

} while ( reg & TWS_BIT13 );

sys/dev/raid/tws/tws_hdm.c

489

u_int32_t reg;

sys/dev/raid/tws/tws_hdm.c

491

reg = tws_read_reg(sc, TWS_I2O0_HIBDB, 4);

sys/dev/raid/tws/tws_hdm.c

492

TWS_TRACE_DEBUG(sc, "in bound door bell read ", reg, TWS_I2O0_HIBDB);

sys/dev/raid/tws/tws_hdm.c

493

tws_write_reg(sc, TWS_I2O0_HIBDB, reg | TWS_BIT8, 4);

sys/dev/raid/tws/tws_hdm.c

86

u_int64_t reg;

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1106

mxt_read_reg(atmel_mxt_softc_t *sc, uint16_t reg, void *rbuf, int bytes)

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1113

wreg[0] = reg & 255;

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1114

wreg[1] = reg >> 8;

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1130

reg, bytes, rbytes);

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1138

mxt_write_reg_buf(atmel_mxt_softc_t *sc, uint16_t reg, void *xbuf, int bytes)

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1145

wbuf[0] = reg & 255;

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1146

wbuf[1] = reg >> 8;

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1163

mxt_write_reg(atmel_mxt_softc_t *sc, uint16_t reg, uint8_t val)

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1165

return mxt_write_reg_buf(sc, reg, &val, 1);

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1172

uint16_t reg = obj->start_pos_lsb + (obj->start_pos_msb << 8);

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1177

return mxt_read_reg(sc, reg, rbuf, bytes);

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1184

uint16_t reg = obj->start_pos_lsb + (obj->start_pos_msb << 8);

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1186

reg += offset;

sys/dev/smbus/atmel_mxt/atmel_mxt.c

1187

return mxt_write_reg(sc, reg, val);

sys/dev/smbus/atmel_mxt/atmel_mxt.c

294

static int mxt_read_reg(atmel_mxt_softc_t *sc, uint16_t reg,

sys/dev/smbus/atmel_mxt/atmel_mxt.c

296

static int mxt_write_reg_buf(atmel_mxt_softc_t *sc, uint16_t reg,

sys/dev/smbus/atmel_mxt/atmel_mxt.c

298

static int mxt_write_reg(atmel_mxt_softc_t *sc, uint16_t reg, uint8_t val);

sys/dev/smbus/atmel_mxt/test_atmel.c

108

mxt_write_reg(int fd, uint16_t reg, uint8_t val)

sys/dev/smbus/atmel_mxt/test_atmel.c

110

return mxt_write_reg_buf(fd, reg, &val, 1);

sys/dev/smbus/atmel_mxt/test_atmel.c

116

uint16_t reg = obj->start_pos_lsb + (obj->start_pos_msb << 8);

sys/dev/smbus/atmel_mxt/test_atmel.c

121

return mxt_read_reg(fd, reg, rbuf, bytes);

sys/dev/smbus/atmel_mxt/test_atmel.c

54

mxt_read_reg(int fd, uint16_t reg, void *rbuf, int bytes)

sys/dev/smbus/atmel_mxt/test_atmel.c

61

wbuf[0] = reg & 255;

sys/dev/smbus/atmel_mxt/test_atmel.c

62

wbuf[1] = reg >> 8;

sys/dev/smbus/atmel_mxt/test_atmel.c

80

mxt_write_reg_buf(int fd, uint16_t reg, void *xbuf, int bytes)

sys/dev/smbus/atmel_mxt/test_atmel.c

87

wbuf[0] = reg & 0xff;

sys/dev/smbus/atmel_mxt/test_atmel.c

88

wbuf[1] = reg >> 8;

sys/dev/sound/pci/als4000.c

741

if (sc->reg) {

sys/dev/sound/pci/als4000.c

742

bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);

sys/dev/sound/pci/als4000.c

743

sc->reg = 0;

sys/dev/sound/pci/als4000.c

767

sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->regid, 0, ~0,

sys/dev/sound/pci/als4000.c

769

if (sc->reg == NULL) {

sys/dev/sound/pci/als4000.c

773

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/als4000.c

774

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/als4000.c

79

struct resource *reg, *irq;

sys/dev/sound/pci/als4000.c

856

rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_als4000));

sys/dev/sound/pci/atiixp.c

1101

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/atiixp.c

1137

if (sc->reg) {

sys/dev/sound/pci/atiixp.c

1138

bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/atiixp.c

1139

sc->reg = NULL;

sys/dev/sound/pci/atiixp.c

117

struct resource *reg, *irq;

sys/dev/sound/pci/atiixp.c

1210

sc->reg = bus_alloc_resource_any(dev, sc->regtype,

sys/dev/sound/pci/atiixp.c

1213

if (!sc->reg) {

sys/dev/sound/pci/atiixp.c

1218

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/atiixp.c

1219

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/atiixp.c

376

atiixp_rdcd(kobj_t obj, void *devinfo, int reg)

sys/dev/sound/pci/atiixp.c

385

data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |

sys/dev/sound/pci/atiixp.c

401

if (reg < 0x7c)

sys/dev/sound/pci/atiixp.c

402

device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg);

sys/dev/sound/pci/atiixp.c

408

atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data)

sys/dev/sound/pci/atiixp.c

416

(((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) |

sys/dev/sound/pci/atiixp.c

609

uint32_t reg, addr, sz, retry;

sys/dev/sound/pci/atiixp.c

612

reg = ch->dt_cur_bit;

sys/dev/sound/pci/atiixp.c

618

ptr = atiixp_rd(sc, reg);

sys/dev/sound/pci/aureal.c

556

struct resource *reg[10];

sys/dev/sound/pci/aureal.c

584

reg[j] = bus_alloc_resource_any(dev, type[j], &regid[j],

sys/dev/sound/pci/aureal.c

586

if (!reg[j]) {

sys/dev/sound/pci/aureal.c

588

reg[j] = bus_alloc_resource_any(dev, type[j],

sys/dev/sound/pci/aureal.c

591

if (reg[j]) {

sys/dev/sound/pci/aureal.c

592

au->st[i] = rman_get_bustag(reg[j]);

sys/dev/sound/pci/aureal.c

593

au->sh[i] = rman_get_bushandle(reg[j]);

sys/dev/sound/pci/aureal.c

649

rman_get_start(reg[0]), rman_get_start(irq),PCM_KLDSTRING(snd_aureal));

sys/dev/sound/pci/aureal.c

661

bus_release_resource(dev, type[i], regid[i], reg[i]);

sys/dev/sound/pci/cmi.c

1011

if (sc->reg)

sys/dev/sound/pci/cmi.c

1012

bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);

sys/dev/sound/pci/cmi.c

1039

bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);

sys/dev/sound/pci/cmi.c

116

struct resource *reg, *irq;

sys/dev/sound/pci/cmi.c

182

int reg, int shift, u_int32_t mask, u_int32_t val)

sys/dev/sound/pci/cmi.c

186

r = cmi_rd(sc, reg, 4);

sys/dev/sound/pci/cmi.c

189

cmi_wr(sc, reg, r, 4);

sys/dev/sound/pci/cmi.c

193

cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)

sys/dev/sound/pci/cmi.c

197

r = cmi_rd(sc, reg, 4);

sys/dev/sound/pci/cmi.c

199

cmi_wr(sc, reg, r, 4);

sys/dev/sound/pci/cmi.c

203

cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)

sys/dev/sound/pci/cmi.c

207

r = cmi_rd(sc, reg, 4);

sys/dev/sound/pci/cmi.c

209

cmi_wr(sc, reg, r, 4);

sys/dev/sound/pci/cmi.c

785

cmi_mread(struct mpu401 *arg, void *sc, int reg)

sys/dev/sound/pci/cmi.c

789

d = bus_space_read_1(0,0, 0x330 + reg);

sys/dev/sound/pci/cmi.c

796

cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)

sys/dev/sound/pci/cmi.c

799

bus_space_write_1(0,0,0x330 + reg , b);

sys/dev/sound/pci/cmi.c

948

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,

sys/dev/sound/pci/cmi.c

950

if (!sc->reg) {

sys/dev/sound/pci/cmi.c

954

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/cmi.c

955

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/cmi.c

998

rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));

sys/dev/sound/pci/cs4281.c

782

sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,

sys/dev/sound/pci/cs4281.c

784

if (!sc->reg) {

sys/dev/sound/pci/cs4281.c

786

sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,

sys/dev/sound/pci/cs4281.c

788

if (!sc->reg) {

sys/dev/sound/pci/cs4281.c

793

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/cs4281.c

794

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/cs4281.c

855

rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));

sys/dev/sound/pci/cs4281.c

863

if (sc->reg)

sys/dev/sound/pci/cs4281.c

864

bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/cs4281.c

893

bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/cs4281.c

91

struct resource *reg, *irq, *mem;

sys/dev/sound/pci/emu10k1.c

1160

emu_mread(struct mpu401 *arg, void *sc, int reg)

sys/dev/sound/pci/emu10k1.c

1164

d = emu_rd((struct sc_info *)sc, 0x18 + reg, 1);

sys/dev/sound/pci/emu10k1.c

1169

emu_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)

sys/dev/sound/pci/emu10k1.c

1172

emu_wr((struct sc_info *)sc, 0x18 + reg, b, 1);

sys/dev/sound/pci/emu10k1.c

2093

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);

sys/dev/sound/pci/emu10k1.c

2094

if (sc->reg == NULL) {

sys/dev/sound/pci/emu10k1.c

2098

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/emu10k1.c

2099

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/emu10k1.c

2136

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/emu10k1.c

2151

if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10k1.c

2174

bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10k1.c

219

struct resource *reg, *irq;

sys/dev/sound/pci/emu10k1.c

331

emu_rdptr(struct sc_info *sc, int chn, int reg)

sys/dev/sound/pci/emu10k1.c

335

ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10k1.c

338

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10k1.c

339

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10k1.c

340

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10k1.c

349

emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)

sys/dev/sound/pci/emu10k1.c

353

ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10k1.c

355

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10k1.c

356

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10k1.c

357

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10k1.c

461

int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;

sys/dev/sound/pci/emu10k1.c

463

reg |= 1 << 24;

sys/dev/sound/pci/emu10k1.c

464

reg |= channel << 16;

sys/dev/sound/pci/emu10k1.c

465

emu_wrptr(sc, 0, reg, enable);

sys/dev/sound/pci/emu10kx-midi.c

70

emu_mread(struct mpu401 *arg __unused, void *cookie, int reg)

sys/dev/sound/pci/emu10kx-midi.c

77

d = emu_rd(sc->card, 0x18 + reg, 1);

sys/dev/sound/pci/emu10kx-midi.c

79

d = emu_rdptr(sc->card, 0, sc->port + reg);

sys/dev/sound/pci/emu10kx-midi.c

85

emu_mwrite(struct mpu401 *arg __unused, void *cookie, int reg, unsigned char b)

sys/dev/sound/pci/emu10kx-midi.c

90

emu_wr(sc->card, 0x18 + reg, b, 1);

sys/dev/sound/pci/emu10kx-midi.c

92

emu_wrptr(sc->card, 0, sc->port + reg, b);

sys/dev/sound/pci/emu10kx.c

1453

int reg;

sys/dev/sound/pci/emu10kx.c

1455

reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;

sys/dev/sound/pci/emu10kx.c

1457

reg |= 1 << 24;

sys/dev/sound/pci/emu10kx.c

1458

reg |= channel << 16;

sys/dev/sound/pci/emu10kx.c

1459

emu_wrptr(sc, 0, reg, enable);

sys/dev/sound/pci/emu10kx.c

3195

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);

sys/dev/sound/pci/emu10kx.c

3196

if (sc->reg == NULL) {

sys/dev/sound/pci/emu10kx.c

3200

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/emu10kx.c

3201

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/emu10kx.c

3230

ksnprintf(status, 255, "rev %d at io 0x%lx irq %ld", sc->rev, rman_get_start(sc->reg), rman_get_start(sc->irq));

sys/dev/sound/pci/emu10kx.c

329

struct resource *reg;

sys/dev/sound/pci/emu10kx.c

3442

if (sc->reg)

sys/dev/sound/pci/emu10kx.c

3443

bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10kx.c

3524

if (sc->reg)

sys/dev/sound/pci/emu10kx.c

3525

bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10kx.c

650

emu_rdptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg)

sys/dev/sound/pci/emu10kx.c

654

ptr = ((reg << 16) & sc->address_mask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10kx.c

666

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10kx.c

667

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10kx.c

668

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10kx.c

677

emu_wrptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg, uint32_t data)

sys/dev/sound/pci/emu10kx.c

681

ptr = ((reg << 16) & sc->address_mask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10kx.c

690

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10kx.c

691

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10kx.c

692

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10kx.c

707

emu_rd_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg)

sys/dev/sound/pci/emu10kx.c

713

emu_wr_nolock(sc, EMU_A2_PTR, (reg << 16) | chn, 4);

sys/dev/sound/pci/emu10kx.c

722

emu_wr_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg, uint32_t data)

sys/dev/sound/pci/emu10kx.c

726

emu_wr_nolock(sc, EMU_A2_PTR, (reg << 16) | chn, 4);

sys/dev/sound/pci/emu10kx.h

154

uint32_t emu_rdptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg);

sys/dev/sound/pci/emu10kx.h

155

void emu_wrptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg, uint32_t data);

sys/dev/sound/pci/emu10kx.h

157

uint32_t emu_rd_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg);

sys/dev/sound/pci/emu10kx.h

158

void emu_wr_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg, uint32_t data);

sys/dev/sound/pci/emuxkireg.h

49

#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))

sys/dev/sound/pci/envy24.c

1343

u_int32_t reg, mask;

sys/dev/sound/pci/envy24.c

1366

reg = class | class << 2 |

sys/dev/sound/pci/envy24.c

1370

device_printf(sc->dev, "envy24_route(): MT_SPDOUT-->0x%04x\n", reg);

sys/dev/sound/pci/envy24.c

1372

envy24_wrmt(sc, ENVY24_MT_SPDOUT, reg, 2);

sys/dev/sound/pci/envy24.c

1376

reg = envy24_rdmt(sc, ENVY24_MT_PSDOUT, 2);

sys/dev/sound/pci/envy24.c

1377

reg = (reg & mask) | ((class | class << 8) << dac * 2);

sys/dev/sound/pci/envy24.c

1379

device_printf(sc->dev, "envy24_route(): MT_PSDOUT-->0x%04x\n", reg);

sys/dev/sound/pci/envy24.c

1381

envy24_wrmt(sc, ENVY24_MT_PSDOUT, reg, 2);

sys/dev/sound/pci/envy24.c

1383

reg = envy24_rdmt(sc, ENVY24_MT_RECORD, 4);

sys/dev/sound/pci/envy24.c

1384

reg = (reg & mask) |

sys/dev/sound/pci/envy24.c

1388

device_printf(sc->dev, "envy24_route(): MT_RECORD-->0x%08x\n", reg);

sys/dev/sound/pci/envy24.c

1390

envy24_wrmt(sc, ENVY24_MT_RECORD, reg, 4);

sys/dev/sound/pci/envy24.c

882

i2c_wr(void *codec, void (*ctrl)(void*, unsigned int, unsigned int), u_int32_t dev, int reg, u_int8_t val)

sys/dev/sound/pci/envy24.c

893

if (reg != 0xff) {

sys/dev/sound/pci/envy24.c

895

i2c_wrbit(ptr, ctrl, reg & mask);

sys/dev/sound/pci/es137x.c

1202

es1371_src_read(struct es_info *es, unsigned short reg)

sys/dev/sound/pci/es137x.c

1208

r |= ES1371_SRC_RAM_ADDRO(reg);

sys/dev/sound/pci/es137x.c

1214

es1371_src_write(struct es_info *es, unsigned short reg, unsigned short data)

sys/dev/sound/pci/es137x.c

1220

r |= ES1371_SRC_RAM_ADDRO(reg) | ES1371_SRC_RAM_DATAO(data);

sys/dev/sound/pci/es137x.c

1724

es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid,

sys/dev/sound/pci/es137x.c

1726

if (es->reg)

sys/dev/sound/pci/es137x.c

1732

es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid,

sys/dev/sound/pci/es137x.c

1734

if (es->reg)

sys/dev/sound/pci/es137x.c

1742

es->st = rman_get_bustag(es->reg);

sys/dev/sound/pci/es137x.c

1743

es->sh = rman_get_bushandle(es->reg);

sys/dev/sound/pci/es137x.c

1860

rman_get_start(es->reg), rman_get_start(es->irq),

sys/dev/sound/pci/es137x.c

1888

if (es->reg)

sys/dev/sound/pci/es137x.c

1889

bus_release_resource(dev, es->regtype, es->regid, es->reg);

sys/dev/sound/pci/es137x.c

1919

bus_release_resource(dev, es->regtype, es->regid, es->reg);

sys/dev/sound/pci/es137x.c

214

struct resource *reg, *irq;

sys/dev/sound/pci/es137x.c

691

uint32_t reg, ptr;

sys/dev/sound/pci/es137x.c

699

reg = ES1370_REG_DAC1_FRAMECNT;

sys/dev/sound/pci/es137x.c

701

reg = ES1370_REG_DAC2_FRAMECNT;

sys/dev/sound/pci/es137x.c

703

reg = ES1370_REG_ADC_FRAMECNT;

sys/dev/sound/pci/es137x.c

705

es_wr(es, ES1370_REG_MEMPAGE, reg >> 8, 4);

sys/dev/sound/pci/es137x.c

706

ptr = es_rd(es, reg & 0x000000ff, 4) >> 16;

sys/dev/sound/pci/es137x.c

857

uint32_t reg, cnt;

sys/dev/sound/pci/es137x.c

865

reg = ES1370_REG_DAC1_FRAMECNT;

sys/dev/sound/pci/es137x.c

867

reg = ES1370_REG_DAC2_FRAMECNT;

sys/dev/sound/pci/es137x.c

869

reg = ES1370_REG_ADC_FRAMECNT;

sys/dev/sound/pci/es137x.c

870

es_wr(es, ES1370_REG_MEMPAGE, reg >> 8, 4);

sys/dev/sound/pci/es137x.c

871

cnt = es_rd(es, reg & 0x000000ff, 4) >> 16;

sys/dev/sound/pci/fm801.c

145

struct resource *reg, *irq;

sys/dev/sound/pci/fm801.c

590

fm801->reg = bus_alloc_resource_any(dev, fm801->regtype,

sys/dev/sound/pci/fm801.c

592

if(!fm801->reg)

sys/dev/sound/pci/fm801.c

595

fm801->reg = bus_alloc_resource_any(dev,

sys/dev/sound/pci/fm801.c

601

if(fm801->reg) {

sys/dev/sound/pci/fm801.c

602

fm801->st = rman_get_bustag(fm801->reg);

sys/dev/sound/pci/fm801.c

603

fm801->sh = rman_get_bushandle(fm801->reg);

sys/dev/sound/pci/fm801.c

643

rman_get_start(fm801->reg), rman_get_start(fm801->irq),PCM_KLDSTRING(snd_fm801));

sys/dev/sound/pci/fm801.c

658

if (fm801->reg) bus_release_resource(dev, fm801->regtype, fm801->regid, fm801->reg);

sys/dev/sound/pci/fm801.c

690

bus_release_resource(dev, fm801->regtype, fm801->regid, fm801->reg);

sys/dev/sound/pci/fm801.c

725

return (fm801->reg);

sys/dev/sound/pci/hda/hdac.c

227

uint8_t reg;

sys/dev/sound/pci/hdspe-pcm.c

177

int reg;

sys/dev/sound/pci/hdspe-pcm.c

180

reg = HDSPE_OUT_ENABLE_BASE;

sys/dev/sound/pci/hdspe-pcm.c

182

reg = HDSPE_IN_ENABLE_BASE;

sys/dev/sound/pci/hdspe-pcm.c

186

hdspe_write_1(sc, reg + (4 * ch->lslot), value);

sys/dev/sound/pci/hdspe-pcm.c

187

hdspe_write_1(sc, reg + (4 * ch->rslot), value);

sys/dev/sound/pci/hdspe-pcm.c

487

sc->ctrl_register |= hr->reg;

sys/dev/sound/pci/hdspe-pcm.c

64

uint32_t reg;

sys/dev/sound/pci/maestro.c

152

struct resource *reg;

sys/dev/sound/pci/maestro.c

1782

struct resource *reg = NULL;

sys/dev/sound/pci/maestro.c

1847

reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &regid, RF_ACTIVE);

sys/dev/sound/pci/maestro.c

1848

if (reg != NULL) {

sys/dev/sound/pci/maestro.c

1849

ess->reg = reg;

sys/dev/sound/pci/maestro.c

1851

ess->st = rman_get_bustag(reg);

sys/dev/sound/pci/maestro.c

1852

ess->sh = rman_get_bushandle(reg);

sys/dev/sound/pci/maestro.c

1916

rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),

sys/dev/sound/pci/maestro.c

1929

if (reg != NULL)

sys/dev/sound/pci/maestro.c

1930

bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);

sys/dev/sound/pci/maestro.c

1975

bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);

sys/dev/sound/pci/maestro.c

423

wp_rdreg(struct agg_info *ess, u_int16_t reg)

sys/dev/sound/pci/maestro.c

425

AGG_WR(ess, PORT_DSP_INDEX, reg, 2);

sys/dev/sound/pci/maestro.c

430

wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)

sys/dev/sound/pci/maestro.c

432

AGG_WR(ess, PORT_DSP_INDEX, reg, 2);

sys/dev/sound/pci/maestro.c

452

wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)

sys/dev/sound/pci/maestro.c

454

wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));

sys/dev/sound/pci/maestro.c

455

if (wp_wait_data(ess, reg | (ch << 4)) != 0)

sys/dev/sound/pci/maestro.c

461

wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)

sys/dev/sound/pci/maestro.c

463

wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));

sys/dev/sound/pci/maestro.c

464

if (wp_wait_data(ess, reg | (ch << 4)) == 0) {

sys/dev/sound/pci/maestro.c

537

wc_rdreg(struct agg_info *ess, u_int16_t reg)

sys/dev/sound/pci/maestro.c

539

AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);

sys/dev/sound/pci/maestro.c

545

wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)

sys/dev/sound/pci/maestro.c

547

AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);

sys/dev/sound/pci/neomagic.c

134

bus_space_tag_t st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/neomagic.c

135

bus_space_handle_t sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/neomagic.c

152

bus_space_tag_t st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/neomagic.c

153

bus_space_handle_t sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/neomagic.c

620

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

sys/dev/sound/pci/neomagic.c

624

if (!sc->reg) {

sys/dev/sound/pci/neomagic.c

643

sc->reg);

sys/dev/sound/pci/neomagic.c

66

struct resource *reg, *irq, *buf;

sys/dev/sound/pci/neomagic.c

680

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regid,

sys/dev/sound/pci/neomagic.c

683

if (!sc->buf || !sc->reg) {

sys/dev/sound/pci/neomagic.c

706

rman_get_start(sc->buf), rman_get_start(sc->reg),

sys/dev/sound/pci/neomagic.c

719

if (sc->reg) bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);

sys/dev/sound/pci/neomagic.c

738

bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);

sys/dev/sound/pci/solo.c

119

static int ess_rd(struct ess_info *sc, int reg);

sys/dev/sound/pci/solo.c

120

static void ess_wr(struct ess_info *sc, int reg, u_int8_t val);

sys/dev/sound/pci/solo.c

129

static int ess_write(struct ess_info *sc, u_char reg, int val);

sys/dev/sound/pci/solo.c

130

static int ess_read(struct ess_info *sc, u_char reg);

sys/dev/sound/pci/solo.c

191

ess_rd(struct ess_info *sc, int reg)

sys/dev/sound/pci/solo.c

193

return port_rd(sc->sb, reg, 1);

sys/dev/sound/pci/solo.c

197

ess_wr(struct ess_info *sc, int reg, u_int8_t val)

sys/dev/sound/pci/solo.c

199

port_wr(sc->sb, reg, val, 1);

sys/dev/sound/pci/solo.c

278

ess_write(struct ess_info *sc, u_char reg, int val)

sys/dev/sound/pci/solo.c

280

return ess_cmd1(sc, reg, val);

sys/dev/sound/pci/solo.c

284

ess_read(struct ess_info *sc, u_char reg)

sys/dev/sound/pci/solo.c

286

return (ess_cmd(sc, 0xc0) && ess_cmd(sc, reg))? ess_get_byte(sc) : -1;

sys/dev/sound/pci/spicds.c

110

spicds_wrbit(codec, reg & mask);

sys/dev/sound/pci/spicds.c

120

spicds_wrbit(codec, reg & mask);

sys/dev/sound/pci/spicds.c

76

spicds_wrcd(struct spicds_info *codec, int reg, u_int16_t val)

sys/dev/sound/pci/spicds.c

81

device_printf(codec->dev, "spicds_wrcd(codec, 0x%02x, 0x%02x)\n", reg, val);

sys/dev/sound/pci/t4dwave.c

336

u_int32_t i, reg;

sys/dev/sound/pci/t4dwave.c

342

reg = bank? TR_REG_INTENB : TR_REG_INTENA;

sys/dev/sound/pci/t4dwave.c

344

i = tr_rd(tr, reg, 4);

sys/dev/sound/pci/t4dwave.c

349

tr_wr(tr, reg, i, 4);

sys/dev/sound/pci/t4dwave.c

864

tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,

sys/dev/sound/pci/t4dwave.c

866

if (tr->reg) {

sys/dev/sound/pci/t4dwave.c

867

tr->st = rman_get_bustag(tr->reg);

sys/dev/sound/pci/t4dwave.c

868

tr->sh = rman_get_bushandle(tr->reg);

sys/dev/sound/pci/t4dwave.c

926

rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave));

sys/dev/sound/pci/t4dwave.c

939

if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);

sys/dev/sound/pci/t4dwave.c

959

bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);

sys/dev/sound/pci/t4dwave.c

98

struct resource *reg, *irq;

sys/dev/sound/pci/via8233.c

1013

int i, reg, stat;

sys/dev/sound/pci/via8233.c

1024

reg = via->pch[i].rbase + VIA_RP_STATUS;

sys/dev/sound/pci/via8233.c

1025

stat = via_rd(via, reg, 1);

sys/dev/sound/pci/via8233.c

1032

via_wr(via, reg, stat, 1);

sys/dev/sound/pci/via8233.c

1040

reg = via->rch[i].rbase + VIA_RP_STATUS;

sys/dev/sound/pci/via8233.c

1041

stat = via_rd(via, reg, 1);

sys/dev/sound/pci/via8233.c

1048

via_wr(via, reg, stat, 1);

sys/dev/sound/pci/via8233.c

110

struct resource *reg, *irq;

sys/dev/sound/pci/via8233.c

1191

via->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &via->regid,

sys/dev/sound/pci/via8233.c

1193

if (!via->reg) {

sys/dev/sound/pci/via8233.c

1197

via->st = rman_get_bustag(via->reg);

sys/dev/sound/pci/via8233.c

1198

via->sh = rman_get_bushandle(via->reg);

sys/dev/sound/pci/via8233.c

1350

rman_get_start(via->reg), rman_get_start(via->irq),

sys/dev/sound/pci/via8233.c

1374

if (via->reg)

sys/dev/sound/pci/via8233.c

1375

bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via8233.c

1415

bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via8233.c

340

via_write_codec(kobj_t obj, void *addr, int reg, uint32_t val)

sys/dev/sound/pci/via8233.c

348

VIA_AC97_CODEC00_VALID | VIA_AC97_INDEX(reg) |

sys/dev/sound/pci/via8233.c

355

via_read_codec(kobj_t obj, void *addr, int reg)

sys/dev/sound/pci/via8233.c

363

VIA_AC97_READ | VIA_AC97_INDEX(reg), 4);

sys/dev/sound/pci/via82c686.c

180

via_write_codec(kobj_t obj, void *addr, int reg, u_int32_t val)

sys/dev/sound/pci/via82c686.c

186

via_wr(via, VIA_CODEC_CTL, VIA_CODEC_PRIVALID | VIA_CODEC_INDEX(reg) | val, 4);

sys/dev/sound/pci/via82c686.c

193

via_read_codec(kobj_t obj, void *addr, int reg)

sys/dev/sound/pci/via82c686.c

200

via_wr(via, VIA_CODEC_CTL, VIA_CODEC_PRIVALID | VIA_CODEC_READ | VIA_CODEC_INDEX(reg),4);

sys/dev/sound/pci/via82c686.c

312

int reg;

sys/dev/sound/pci/via82c686.c

324

reg = (ch->dir == PCMDIR_PLAY)? AC97_REGEXT_FDACRATE : AC97_REGEXT_LADCRATE;

sys/dev/sound/pci/via82c686.c

325

return ac97_setrate(via->codec, reg, speed);

sys/dev/sound/pci/via82c686.c

522

via->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,

sys/dev/sound/pci/via82c686.c

524

if (!via->reg) {

sys/dev/sound/pci/via82c686.c

528

via->st = rman_get_bustag(via->reg);

sys/dev/sound/pci/via82c686.c

529

via->sh = rman_get_bushandle(via->reg);

sys/dev/sound/pci/via82c686.c

592

rman_get_start(via->reg), rman_get_start(via->irq),

sys/dev/sound/pci/via82c686.c

603

if (via->reg) bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via82c686.c

626

bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via82c686.c

83

struct resource *reg, *irq;

sys/dev/sound/pci/vibes.c

121

sv_direct_get(struct sc_info *sc, u_int8_t reg)

sys/dev/sound/pci/vibes.c

123

return bus_space_read_1(sc->enh_st, sc->enh_sh, reg);

sys/dev/sound/pci/vibes.c

127

_sv_direct_set(struct sc_info *sc, u_int8_t reg, u_int8_t val, int line)

sys/dev/sound/pci/vibes.c

130

bus_space_write_1(sc->enh_st, sc->enh_sh, reg, val);

sys/dev/sound/pci/vibes.c

132

n = sv_direct_get(sc, reg);

sys/dev/sound/pci/vibes.c

134

device_printf(sc->dev, "sv_direct_set register 0x%02x %d != %d from line %d\n", reg, n, val, line);

sys/dev/sound/pci/vibes.c

139

sv_indirect_get(struct sc_info *sc, u_int8_t reg)

sys/dev/sound/pci/vibes.c

141

if (reg == SV_REG_FORMAT || reg == SV_REG_ANALOG_PWR)

sys/dev/sound/pci/vibes.c

142

reg |= SV_CM_INDEX_MCE;

sys/dev/sound/pci/vibes.c

144

bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg);

sys/dev/sound/pci/vibes.c

151

_sv_indirect_set(struct sc_info *sc, u_int8_t reg, u_int8_t val, int line)

sys/dev/sound/pci/vibes.c

153

if (reg == SV_REG_FORMAT || reg == SV_REG_ANALOG_PWR)

sys/dev/sound/pci/vibes.c

154

reg |= SV_CM_INDEX_MCE;

sys/dev/sound/pci/vibes.c

156

bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg);

sys/dev/sound/pci/vibes.c

159

reg &= ~SV_CM_INDEX_MCE;

sys/dev/sound/pci/vibes.c

160

if (reg != SV_REG_ADC_PLLM) {

sys/dev/sound/pci/vibes.c

162

n = sv_indirect_get(sc, reg);

sys/dev/sound/pci/vibes.c

164

device_printf(sc->dev, "sv_indirect_set register 0x%02x %d != %d line %d\n", reg, n, val, line);

sys/dev/sound/pci/vibes.c

462

u_int8_t reg; /* Register */

sys/dev/sound/pci/vibes.c

491

v = sv_indirect_get(sc, mt[dev].reg + channel) & ~mt[dev].max;

sys/dev/sound/pci/vibes.c

501

sv_indirect_set(sc, mt[dev].reg + channel, v);

sys/dev/sound/pci/vibes.c

518

if (mt[i].reg) sv_gain(sc, i, 0, 0);

sys/dev/sound/pcm/ac97.c

309

ac97_rdcd(struct ac97_info *codec, int reg)

sys/dev/sound/pcm/ac97.c

314

i[0] = AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

315

i[1] = AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

317

i[j-- & 1] = AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

321

" 0x%08x (retry: %d)\n", __func__, reg, 100 - j);

sys/dev/sound/pcm/ac97.c

326

return AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

330

ac97_wrcd(struct ac97_info *codec, int reg, u_int16_t val)

sys/dev/sound/pcm/ac97.c

332

AC97_WRITE(codec->methods, codec->devinfo, reg, val);

sys/dev/sound/pcm/ac97.c

44

int reg; /* register index */

sys/dev/sound/pcm/ac97.c

441

if (e->reg && e->enable && e->bits) {

sys/dev/sound/pcm/ac97.c

442

int mask, max, val, reg;

sys/dev/sound/pcm/ac97.c

444

reg = (e->reg >= 0) ? e->reg : -e->reg; /* AC97 register */

sys/dev/sound/pcm/ac97.c

457

if (e->reg > 0) {

sys/dev/sound/pcm/ac97.c

470

if (e->reg > 0) {

sys/dev/sound/pcm/ac97.c

501

int cur = ac97_rdcd(codec, reg);

sys/dev/sound/pcm/ac97.c

504

ac97_wrcd(codec, reg, val);

sys/dev/sound/pcm/ac97.c

509

printf("ac97_setmixer: reg=%d, bits=%d, enable=%d\n", e->reg, e->bits, e->enable);

sys/dev/sound/pcm/ac97.c

540

codec->mix[SOUND_MIXER_OGAIN].reg = AC97_MIXEXT_SURROUND;

sys/dev/sound/pcm/ac97.c

606

int reg;

sys/dev/sound/pcm/ac97.c

693

reg = codec->mix[i].reg;

sys/dev/sound/pcm/ac97.c

694

if (reg < 0)

sys/dev/sound/pcm/ac97.c

695

reg = -reg;

sys/dev/sound/pcm/ac97.c

696

if (k && reg) {

sys/dev/sound/pcm/ac97.c

697

j = old = ac97_rdcd(codec, reg);

sys/dev/sound/pcm/ac97.c

703

ac97_wrcd(codec, reg, j | 0x8000);

sys/dev/sound/pcm/ac97.c

704

j = ac97_rdcd(codec, reg);

sys/dev/sound/pcm/ac97.c

721

ac97_wrcd(codec, reg,

sys/dev/sound/pcm/ac97.c

723

k = ac97_rdcd(codec, reg) & j;

sys/dev/sound/pcm/ac97.c

725

if (reg == AC97_MIX_TONE &&

sys/dev/sound/pcm/ac97.c

737

} else if (reg == AC97_MIX_BEEP) {

sys/dev/sound/pcm/ac97.c

748

ac97_wrcd(codec, reg, old);

sys/dev/sound/pcm/ac97.h

106

u_int16_t ac97_rdcd(struct ac97_info *codec, int reg);

sys/dev/sound/pcm/ac97.h

107

void ac97_wrcd(struct ac97_info *codec, int reg, u_int16_t val);

sys/dev/video/cxm/cxm.h

292

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/video/cxm/cxm.h

293

bus_space_write_4((sc)->btag, (sc)->bhandle, (reg), (val))

sys/dev/video/cxm/cxm.h

294

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/video/cxm/cxm.h

295

bus_space_write_2((sc)->btag, (sc)->bhandle, (reg), val))

sys/dev/video/cxm/cxm.h

296

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/video/cxm/cxm.h

297

bus_space_write_1((sc)->btag, (sc)->bhandle, (reg), val))

sys/dev/video/cxm/cxm.h

298

#define CSR_READ_4(sc, reg) \

sys/dev/video/cxm/cxm.h

299

bus_space_read_4((sc)->btag, (sc)->bhandle, (reg))

sys/dev/video/cxm/cxm.h

300

#define CSR_READ_2(sc, reg) \

sys/dev/video/cxm/cxm.h

301

bus_space_read_2((sc)->btag, (sc)->bhandle, (reg))

sys/dev/video/cxm/cxm.h

302

#define CSR_READ_1(sc, reg) \

sys/dev/video/cxm/cxm.h

303

bus_space_read_1((sc)->btag, (sc)->bhandle, (reg))

sys/kern/sys_process.c

117

error = copyout(&r.reg, uap->addr, sizeof r.reg);

sys/kern/sys_process.c

485

iov.iov_len = sizeof(struct reg);

sys/kern/sys_process.c

489

uio.uio_resid = sizeof(struct reg);

sys/kern/sys_process.c

74

struct reg reg;

sys/kern/sys_process.c

88

error = copyin(uap->addr, &r.reg, sizeof r.reg);

sys/net/netisr.c

261

struct netmsg_port_registration *reg;

sys/net/netisr.c

277

reg = kmalloc(sizeof(*reg), M_TEMP, M_WAITOK|M_ZERO);

sys/net/netisr.c

278

reg->npr_port = port;

sys/net/netisr.c

279

TAILQ_INSERT_TAIL(&netreglist, reg, npr_entry);

sys/net/netisr.c

294

struct netmsg_port_registration *reg;

sys/net/netisr.c

299

TAILQ_FOREACH(reg, &netreglist, npr_entry) {

sys/net/netisr.c

300

lwkt_domsg(reg->npr_port, &smsg.lmsg, 0);

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2129

struct ieee80211_regdomain_req *reg;

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2141

reg = (struct ieee80211_regdomain_req *)

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2144

reg = (struct ieee80211_regdomain_req *)

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2148

if (reg == NULL) {

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2153

error = copyin(ireq->i_data, reg, IEEE80211_REGDOMAIN_SIZE(nchans));

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2156

if (reg->chaninfo.ic_nchans != nchans) {

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2159

reg->chaninfo.ic_nchans, nchans);

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2162

error = ieee80211_setregdomain(vap, reg);

sys/netproto/802_11/wlan/ieee80211_ioctl.c

2164

IEEE80211_FREE(reg, M_TEMP);

sys/netproto/802_11/wlan/ieee80211_regdomain.c

343

struct ieee80211_regdomain_req *reg)

sys/netproto/802_11/wlan/ieee80211_regdomain.c

350

if (reg->rd.location != 'I' && reg->rd.location != 'O' &&

sys/netproto/802_11/wlan/ieee80211_regdomain.c

351

reg->rd.location != ' ') {

sys/netproto/802_11/wlan/ieee80211_regdomain.c

353

"%s: invalid location 0x%x\n", __func__, reg->rd.location);

sys/netproto/802_11/wlan/ieee80211_regdomain.c

356

if (reg->rd.isocc[0] == '\0' || reg->rd.isocc[1] == '\0') {

sys/netproto/802_11/wlan/ieee80211_regdomain.c

359

reg->rd.isocc[0], reg->rd.isocc[1]);

sys/netproto/802_11/wlan/ieee80211_regdomain.c

362

if (reg->chaninfo.ic_nchans > IEEE80211_CHAN_MAX) {

sys/netproto/802_11/wlan/ieee80211_regdomain.c

365

reg->chaninfo.ic_nchans, IEEE80211_CHAN_MAX);

sys/netproto/802_11/wlan/ieee80211_regdomain.c

373

for (i = 0; i < reg->chaninfo.ic_nchans; i++) {

sys/netproto/802_11/wlan/ieee80211_regdomain.c

374

c = &reg->chaninfo.ic_chans[i];

sys/netproto/802_11/wlan/ieee80211_regdomain.c

404

error = ic->ic_setregdomain(ic, &reg->rd,

sys/netproto/802_11/wlan/ieee80211_regdomain.c

405

reg->chaninfo.ic_nchans, reg->chaninfo.ic_chans);

sys/netproto/802_11/wlan/ieee80211_regdomain.c

430

memcpy(&ic->ic_regdomain, &reg->rd, sizeof(reg->rd));

sys/netproto/802_11/wlan/ieee80211_regdomain.c

432

memcpy(ic->ic_channels, reg->chaninfo.ic_chans,

sys/netproto/802_11/wlan/ieee80211_regdomain.c

433

reg->chaninfo.ic_nchans * sizeof(struct ieee80211_channel));

sys/netproto/802_11/wlan/ieee80211_regdomain.c

434

ic->ic_nchans = reg->chaninfo.ic_nchans;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

588

int reg, end, asz;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

594

reg = gas->BitOffset / NBBY;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

596

if (reg >= end)

sys/platform/pc64/acpica/acpi_pstate_machdep.c

603

if (reg + asz > end)

sys/platform/pc64/acpica/acpi_pstate_machdep.c

611

int asz, reg;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

615

reg = res->pr_gas.BitOffset / NBBY;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

619

return bus_space_read_1(res->pr_bt, res->pr_bh, reg);

sys/platform/pc64/acpica/acpi_pstate_machdep.c

621

return bus_space_read_2(res->pr_bt, res->pr_bh, reg);

sys/platform/pc64/acpica/acpi_pstate_machdep.c

623

return bus_space_read_4(res->pr_bt, res->pr_bh, reg);

sys/platform/pc64/acpica/acpi_pstate_machdep.c

634

int asz, reg;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

638

reg = res->pr_gas.BitOffset / NBBY;

sys/platform/pc64/acpica/acpi_pstate_machdep.c

642

bus_space_write_1(res->pr_bt, res->pr_bh, reg, val);

sys/platform/pc64/acpica/acpi_pstate_machdep.c

645

bus_space_write_2(res->pr_bt, res->pr_bh, reg, val);

sys/platform/pc64/acpica/acpi_pstate_machdep.c

648

bus_space_write_4(res->pr_bt, res->pr_bh, reg, val);

sys/platform/pc64/include/md_var.h

83

struct reg;

sys/platform/pc64/isa/clock.c

530

rtcin(int reg)

sys/platform/pc64/isa/clock.c

535

outb(IO_RTC, reg);

sys/platform/pc64/isa/clock.c

544

writertc(u_char reg, u_char val)

sys/platform/pc64/isa/clock.c

548

outb(IO_RTC, reg);

sys/platform/pc64/x86_64/db_trace.c

459

#define DB_DRX_FUNC(reg) \

sys/platform/pc64/x86_64/db_trace.c

461

db_ ## reg (struct db_variable *vp, db_expr_t *valuep, int op) \

sys/platform/pc64/x86_64/db_trace.c

464

*valuep = r ## reg (); \

sys/platform/pc64/x86_64/db_trace.c

466

load_ ## reg (*valuep); \

sys/platform/pc64/x86_64/machdep.c

3009

fill_regs(struct lwp *lp, struct reg *regs)

sys/platform/pc64/x86_64/machdep.c

3020

set_regs(struct lwp *lp, struct reg *regs)

sys/platform/pc64/x86_64/procfs_machdep.c

80

procfs_read_regs(struct lwp *lp, struct reg *regs)

sys/platform/pc64/x86_64/procfs_machdep.c

86

procfs_write_regs(struct lwp *lp, struct reg *regs)

sys/platform/vkernel64/x86_64/cpu_regs.c

688

fill_regs(struct lwp *lp, struct reg *regs)

sys/platform/vkernel64/x86_64/cpu_regs.c

699

set_regs(struct lwp *lp, struct reg *regs)

sys/platform/vkernel64/x86_64/db_trace.c

452

#define DB_DRX_FUNC(reg) \

sys/platform/vkernel64/x86_64/db_trace.c

454

db_ ## reg (struct db_variable *vp, db_expr_t *valuep, int op) \

sys/platform/vkernel64/x86_64/db_trace.c

457

*valuep = r ## reg (); \

sys/platform/vkernel64/x86_64/db_trace.c

459

load_ ## reg (*valuep); \

sys/platform/vkernel64/x86_64/procfs_machdep.c

81

procfs_read_regs(struct lwp *lp, struct reg *regs)

sys/platform/vkernel64/x86_64/procfs_machdep.c

87

procfs_write_regs(struct lwp *lp, struct reg *regs)

sys/sys/procfs.h

36

typedef struct reg gregset_t;

sys/sys/reg.h

56

int fill_regs (struct lwp *lp, struct reg *regs);

sys/sys/reg.h

59

int set_regs (struct lwp *lp, struct reg *regs);

sys/sys/sysmsg.h

68

register_t reg;

sys/sys/sysmsg.h

83

#define sysmsg_reg sm_result.reg

sys/vfs/procfs/procfs.h

117

struct reg;

sys/vfs/procfs/procfs.h

126

int procfs_read_regs (struct lwp *, struct reg *);

sys/vfs/procfs/procfs.h

127

int procfs_write_regs (struct lwp *, struct reg *);

sys/vfs/procfs/procfs_regs.c

55

struct reg r;

sys/vfs/procfs/procfs_vnops.c

682

vap->va_bytes = vap->va_size = sizeof(struct reg);

test/nvmm/demo/smallkern/main.c

258

uint32_t *reg, val;

test/nvmm/demo/smallkern/main.c

306

reg = (uint32_t *)lapicbase;

test/nvmm/demo/smallkern/main.c

307

val = reg[LAPIC_ID/4];

tools/tools/ath/athdecode/main.c

112

switch (r->reg) {

tools/tools/ath/athdecode/main.c

190

fprintf(fd, "mark #%u value %u/0x%x", r->reg, r->val, r->val);

tools/tools/ath/athdecode/main.c

348

findreg(int reg)

tools/tools/ath/athdecode/main.c

355

if (dr->addr == reg &&

tools/tools/ath/athdecode/main.c

377

dr = findreg(r->reg);

tools/tools/ath/athdecode/main.c

379

snprintf(buf, sizeof (buf), "AR_%s (0x%x)", dr->name, r->reg);

tools/tools/ath/athdecode/main.c

381

} else if (AR_KEYTABLE(0) <= r->reg && r->reg < AR_KEYTABLE(128)) {

tools/tools/ath/athdecode/main.c

383

((r->reg - AR_KEYTABLE_0) >> 2) & 7,

tools/tools/ath/athdecode/main.c

384

(r->reg - AR_KEYTABLE_0) >> 5, r->reg);

tools/tools/ath/athdecode/main.c

387

} else if (AR_PHY_PCDAC_TX_POWER(0) <= r->reg && r->reg < AR_PHY_PCDAC_TX_POWER(PWR_TABLE_SIZE/2)) {

tools/tools/ath/athdecode/main.c

389

(r->reg - AR_PHY_PCDAC_TX_POWER_0) >> 2, r->reg);

tools/tools/ath/athdecode/main.c

392

} else if (AR_RATE_DURATION(0) <= r->reg && r->reg < AR_RATE_DURATION(32)) {

tools/tools/ath/athdecode/main.c

394

(r->reg - AR_RATE_DURATION_0) >> 2, r->reg);

tools/tools/ath/athdecode/main.c

396

} else if (AR_PHY_BASE <= r->reg) {

tools/tools/ath/athdecode/main.c

398

(r->reg - AR_PHY_BASE) >> 2, r->reg);

tools/tools/ath/athdecode/main.c

401

snprintf(buf, sizeof (buf), "0x%x", r->reg);

tools/tools/ath/athpoke/athpoke.c

102

uint32_t reg;

tools/tools/ath/athpoke/athpoke.c

110

reg = (uint32_t) strtoul(argv[0], &eptr, 0);

tools/tools/ath/athpoke/athpoke.c

114

reg = dr->addr;

tools/tools/ath/athpoke/athpoke.c

116

regwrite(s, &atd, reg, (uint32_t) strtoul(cp, NULL, 0));

tools/tools/ath/athpoke/athpoke.c

117

printf("%s = %08x\n", argv[0], regread(s, &atd, reg));

usr.bin/dc/bcode.c

1527

v = stack_tos(&bmachine.reg[index]);

usr.bin/dc/bcode.c

238

bmachine.reg = calloc(bmachine.reg_array_size,

usr.bin/dc/bcode.c

239

sizeof(bmachine.reg[0]));

usr.bin/dc/bcode.c

240

if (bmachine.reg == NULL)

usr.bin/dc/bcode.c

251

stack_init(&bmachine.reg[i]);

usr.bin/dc/bcode.c

49

struct stack *reg;

usr.bin/dc/bcode.c

794

v = stack_tos(&bmachine.reg[index]);

usr.bin/dc/bcode.c

816

stack_set_tos(&bmachine.reg[index], val);

usr.bin/dc/bcode.c

829

stack = &bmachine.reg[index];

usr.bin/dc/bcode.c

853

stack_push(&bmachine.reg[index], value);

usr.bin/dc/bcode.c

860

int reg;

usr.bin/dc/bcode.c

866

reg = readreg();

usr.bin/dc/bcode.c

867

if (reg >= 0) {

usr.bin/dc/bcode.c

877

stack = &bmachine.reg[reg];

usr.bin/dc/bcode.c

894

int reg;

usr.bin/dc/bcode.c

900

reg = readreg();

usr.bin/dc/bcode.c

901

if (reg >= 0) {

usr.bin/dc/bcode.c

918

stack = &bmachine.reg[reg];

usr.bin/pkill/pkill.c

139

regex_t reg;

usr.bin/pkill/pkill.c

348

if ((rv = regcomp(&reg, *argv, cflags)) != 0) {

usr.bin/pkill/pkill.c

349

regerror(rv, &reg, buf, sizeof(buf));

usr.bin/pkill/pkill.c

377

rv = regexec(&reg, mstr, 1, &regmatch, 0);

usr.bin/pkill/pkill.c

387

regerror(rv, &reg, buf, sizeof(buf));

usr.bin/pkill/pkill.c

401

regfree(&reg);

usr.bin/script/script.c

358

consume(FILE *fp, off_t len, char *buf, int reg)

usr.bin/script/script.c

362

if (reg) {

usr.bin/script/script.c

395

int reg;

usr.bin/script/script.c

400

reg = S_ISREG(pst.st_mode);

usr.bin/script/script.c

402

for (nread = 0; !reg || nread < pst.st_size; nread += save_len) {

usr.bin/script/script.c

404

if (reg)

usr.bin/script/script.c

412

if (reg && stamp.scr_len >

usr.bin/script/script.c

427

consume(fp, stamp.scr_len, buf, reg);

usr.bin/script/script.c

433

consume(fp, stamp.scr_len, buf, reg);

usr.bin/script/script.c

437

consume(fp, stamp.scr_len, buf, reg);

usr.bin/truss/x86_64-fbsd.c

111

struct reg regs = { .r_err = 0 };

usr.bin/truss/x86_64-fbsd.c

113

int i, reg;

usr.bin/truss/x86_64-fbsd.c

138

reg = 0;

usr.bin/truss/x86_64-fbsd.c

146

reg++;

usr.bin/truss/x86_64-fbsd.c

178

for (i = 0; i < nargs && reg < 6; i++, reg++) {

usr.bin/truss/x86_64-fbsd.c

179

switch (reg) {

usr.bin/truss/x86_64-fbsd.c

261

struct reg regs;

usr.sbin/dconschat/dconschat.c

176

struct csrreg *reg;

usr.sbin/dconschat/dconschat.c

178

reg = (struct csrreg *)&buf;

usr.sbin/dconschat/dconschat.c

189

printf("%d %02x %06x\n", state, reg->key, reg->val);

usr.sbin/dconschat/dconschat.c

192

if (reg->key == CSRKEY_SPEC &&

usr.sbin/dconschat/dconschat.c

193

reg->val == CSRVAL_VENDOR_PRIVATE)

usr.sbin/dconschat/dconschat.c

197

if (reg->key == CSRKEY_VER &&

usr.sbin/dconschat/dconschat.c

198

reg->val == DCONS_CSR_VAL_VER)

usr.sbin/dconschat/dconschat.c

202

if (reg->key == DCONS_CSR_KEY_HI)

usr.sbin/dconschat/dconschat.c

203

hi = reg->val;

usr.sbin/dconschat/dconschat.c

204

else if (reg->key == DCONS_CSR_KEY_LO) {

usr.sbin/dconschat/dconschat.c

205

lo = reg->val;

usr.sbin/fwcontrol/fwcontrol.c

221

u_int32_t max, reg, old;

usr.sbin/fwcontrol/fwcontrol.c

230

reg = read_write_quad(fd, devinfo->eui, BUGET_REG, 1, 0);

usr.sbin/fwcontrol/fwcontrol.c

232

devinfo->dst, devinfo->eui.hi, devinfo->eui.lo, reg);

usr.sbin/fwcontrol/fwcontrol.c

233

if (reg > 0) {

usr.sbin/fwcontrol/fwcontrol.c

234

old = (reg & 0x3f);

usr.sbin/fwcontrol/fwcontrol.c

235

max = (reg & 0x3f00) >> 8;

usr.sbin/fwcontrol/fwcontrol.c

295

struct csrreg *reg;

usr.sbin/fwcontrol/fwcontrol.c

304

reg = (struct csrreg *)hdr;

usr.sbin/fwcontrol/fwcontrol.c

305

printf("verndor ID: 0x%06x\n", reg->val);

usr.sbin/fwcontrol/fwcontrol.c

330

reg = crom_get(&cc);

usr.sbin/fwcontrol/fwcontrol.c

334

reg->key,

usr.sbin/fwcontrol/fwcontrol.c

335

key_types[(reg->key & CSRTYPE_MASK)>>6],

usr.sbin/fwcontrol/fwcontrol.c

336

reg->key & CSRKEY_MASK, reg->val,

usr.sbin/pciconf/cap.c

221

uint32_t reg;

usr.sbin/pciconf/cap.c

258

reg = read_config(fd, &p->pc_sel,

usr.sbin/pciconf/cap.c

260

if (reg != 0)

usr.sbin/pciconf/cap.c

261

printf("%08x", reg);

usr.sbin/pciconf/cap.c

262

reg = read_config(fd, &p->pc_sel,

usr.sbin/pciconf/cap.c

264

printf("%08x", reg);

usr.sbin/pciconf/pciconf.c

257

print_window(int reg, const char *type, int range, uint64_t base,

usr.sbin/pciconf/pciconf.c

262

reg, type, range, (uintmax_t)base, (uintmax_t)limit,

usr.sbin/pciconf/pciconf.c

733

read_config(int fd, struct pcisel *sel, long reg, int width)

usr.sbin/pciconf/pciconf.c

738

pi.pi_reg = reg;

usr.sbin/pciconf/pciconf.c

787

readone(int fd, struct pcisel *sel, long reg, int width)

usr.sbin/pciconf/pciconf.c

790

printf("%0*x", width*2, read_config(fd, sel, reg, width));

usr.sbin/pciconf/pciconf.c

794

readit(const char *name, const char *reg, int width)

usr.sbin/pciconf/pciconf.c

808

rend = rstart = strtol(reg, &end, 0);

usr.sbin/pciconf/pciconf.c

826

writeit(const char *name, const char *reg, const char *data, int width)

usr.sbin/pciconf/pciconf.c

832

pi.pi_reg = strtoul(reg, (char **)0, 0); /* XXX error check */

usr.sbin/pciconf/pciconf.h

38

uint32_t read_config(int fd, struct pcisel *sel, long reg, int width);

usr.sbin/rpcbind/pmap_svc.c

163

struct pmap reg;

usr.sbin/rpcbind/pmap_svc.c

174

reg.pm_prog, reg.pm_vers);

usr.sbin/rpcbind/pmap_svc.c

177

if (!svc_getargs(xprt, (xdrproc_t) xdr_pmap, (char *)&reg)) {

usr.sbin/rpcbind/pmap_svc.c

182

if (!check_access(xprt, op, &reg, PMAPVERS)) {

usr.sbin/rpcbind/pmap_svc.c

203

rpcbreg.r_prog = reg.pm_prog;

usr.sbin/rpcbind/pmap_svc.c

204

rpcbreg.r_vers = reg.pm_vers;

usr.sbin/rpcbind/pmap_svc.c

210

(int)((reg.pm_port >> 8) & 0xff),

usr.sbin/rpcbind/pmap_svc.c

211

(int)(reg.pm_port & 0xff));

usr.sbin/rpcbind/pmap_svc.c

213

if (reg.pm_prot == IPPROTO_UDP) {

usr.sbin/rpcbind/pmap_svc.c

215

} else if (reg.pm_prot == IPPROTO_TCP) {

usr.sbin/rpcbind/pmap_svc.c

257

struct pmap reg;

usr.sbin/rpcbind/pmap_svc.c

265

if (!svc_getargs(xprt, (xdrproc_t) xdr_pmap, (char *)&reg)) {

usr.sbin/rpcbind/pmap_svc.c

270

if (!check_access(xprt, PMAPPROC_GETPORT, &reg, PMAPVERS)) {

usr.sbin/rpcbind/pmap_svc.c

280

reg.pm_prog, reg.pm_vers,

usr.sbin/rpcbind/pmap_svc.c

281

reg.pm_prot == IPPROTO_UDP ? "udp" : "tcp", uaddr);

usr.sbin/rpcbind/pmap_svc.c

285

fnd = find_service_pmap(reg.pm_prog, reg.pm_vers, reg.pm_prot);

usr.sbin/rpcbind/pmap_svc.c

291

if (reg.pm_prot == IPPROTO_UDP) {

usr.sbin/rpcbind/pmap_svc.c

310

delete_prog(reg.pm_prog);

usr.sbin/rpcbind/pmap_svc.c

327

rpcbs_getaddr(RPCBVERS_2_STAT, reg.pm_prog, reg.pm_vers,

usr.sbin/rpcbind/pmap_svc.c

328

reg.pm_prot == IPPROTO_UDP ? udptrans : tcptrans,

usr.sbin/rpcbind/rpcb_svc_com.c

152

RPCB reg, *a;

usr.sbin/rpcbind/rpcb_svc_com.c

155

reg = *regp;

usr.sbin/rpcbind/rpcb_svc_com.c

161

fnd = find_service(reg.r_prog, reg.r_vers, reg.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

162

if (fnd && (fnd->rpcb_map.r_vers == reg.r_vers)) {

usr.sbin/rpcbind/rpcb_svc_com.c

163

if (!strcmp(fnd->rpcb_map.r_addr, reg.r_addr))

usr.sbin/rpcbind/rpcb_svc_com.c

179

a->r_prog = reg.r_prog;

usr.sbin/rpcbind/rpcb_svc_com.c

180

a->r_vers = reg.r_vers;

usr.sbin/rpcbind/rpcb_svc_com.c

181

a->r_netid = strdup(reg.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

182

a->r_addr = strdup(reg.r_addr);

usr.sbin/rpcbind/rpcb_svc_com.c

291

RPCB reg;

usr.sbin/rpcbind/rpcb_svc_com.c

299

reg.r_prog = rbl->rpcb_map.r_prog;

usr.sbin/rpcbind/rpcb_svc_com.c

300

reg.r_vers = rbl->rpcb_map.r_vers;

usr.sbin/rpcbind/rpcb_svc_com.c

301

reg.r_netid = strdup(rbl->rpcb_map.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

302

map_unset(&reg, "superuser");

usr.sbin/rpcbind/rpcb_svc_com.c

303

free(reg.r_netid);