ARRAY_SIZE - OpenBSD

sys/dev/ic/qwx.c

23741

for (i = 0; i < ARRAY_SIZE(arvif->bitrate_mask.control); i++) {

sys/dev/ic/qwz.c

20923

for (i = 0; i < ARRAY_SIZE(arvif->bitrate_mask.control); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

126

for (i = 0; i < ARRAY_SIZE(aca_regs); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

912

for (i = 0; i < ARRAY_SIZE(aca_regs); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

94

for (i = 0; i < ARRAY_SIZE(amdgpu_afmt_predefined_acr); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3204

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3208

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

372

if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

420

n = ARRAY_SIZE(common_modes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1649

for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2530

return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : "unknown";

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4004

for (j = 0; j < ARRAY_SIZE(ip_order); j++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4040

for (i = 0; i < ARRAY_SIZE(ip_order); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1261

for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

881

static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1384

sz = ARRAY_SIZE(amdgpu_underscan_enum_list);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1402

sz = ARRAY_SIZE(amdgpu_audio_enum_list);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1408

sz = ARRAY_SIZE(amdgpu_dither_enum_list);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

665

ARRAY_SIZE(dcc_retile_formats),

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

669

return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2318

for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2347

for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3112

.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3140

.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3312

for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

151

r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs));

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

152

if (r != ARRAY_SIZE(msgs))

sys/dev/pci/drm/amd/amdgpu/amdgpu_fdinfo.c

90

for (i = 0; i < ARRAY_SIZE(pl_name); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

547

#define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)},

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1284

if ((mode >= ARRAY_SIZE(nps_desc)) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

91

for (i = 0; i < ARRAY_SIZE(ip_map); ++i)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

236

for (i = 0; i < ARRAY_SIZE(mca->mca_caches); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

253

for (i = 0; i < ARRAY_SIZE(mca->mca_caches); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

546

for (i = 0; i < ARRAY_SIZE(reg_idx_array); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

136

.num_formats = ARRAY_SIZE(amdgpu_pmu_formats),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

138

.num_events = ARRAY_SIZE(vega20_events),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

140

.num_types = ARRAY_SIZE(vega20_types)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

171

.num_formats = ARRAY_SIZE(df_vega20_formats),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

173

.num_events = ARRAY_SIZE(df_vega20_events),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

201

.num_formats = ARRAY_SIZE(amdgpu_pmu_formats),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

203

.num_events = ARRAY_SIZE(arcturus_events),

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

205

.num_types = ARRAY_SIZE(arcturus_types)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

103

ras_block->block >= ARRAY_SIZE(ras_block_string))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

113

(((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1895

for (i = 0; i < ARRAY_SIZE(dump_event); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

238

address, page_pfns, ARRAY_SIZE(page_pfns));

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

322

for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4047

for (i = 0; i < ARRAY_SIZE(mgr->event_state); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

367

return idx < ARRAY_SIZE(sw_ring_info) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

373

return idx < ARRAY_SIZE(sw_ring_info) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1406

for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1211

error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1301

for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1306

for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1311

for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1314

for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1325

for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1343

for (i = 0; i < ARRAY_SIZE(xgmi_v6_4_0_mca_base_array); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1389

field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1392

field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1396

field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1438

for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1445

for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1454

for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1461

for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1470

for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1479

for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1497

for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1525

error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1574

for (i = 0; i < ARRAY_SIZE(xgmi_v6_4_0_mca_base_array); i++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

304

if (link_num < ARRAY_SIZE(link_map_6_4_x))

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

324

n = ARRAY_SIZE(smn_xgmi_6_4_pcs_state_hist1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

328

n = ARRAY_SIZE(smn_xgmi_6_4_1_pcs_state_hist1);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

295

xcp_cfg->num_res = ARRAY_SIZE(max_res);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

643

for (r = 0; r < ARRAY_SIZE(pcie_reg_addrs); r++) {

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

740

for (r = 0; r < ARRAY_SIZE(xgmi_reg_addrs); r++) {

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

814

for (r = 0; r < ARRAY_SIZE(wafl_reg_addrs); r++) {

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

908

arr_size = ARRAY_SIZE(usr_reg_addrs);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

913

arr_size = ARRAY_SIZE(usr1_reg_addrs);

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

275

for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {

sys/dev/pci/drm/amd/amdgpu/cik.c

1224

for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/cik.c

126

.codec_count = ARRAY_SIZE(cik_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/cik.c

836

ARRAY_SIZE(bonaire_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/cik.c

839

ARRAY_SIZE(bonaire_golden_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

842

ARRAY_SIZE(bonaire_golden_common_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

845

ARRAY_SIZE(bonaire_golden_spm_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

850

ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/cik.c

853

ARRAY_SIZE(kalindi_golden_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

856

ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

859

ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

864

ARRAY_SIZE(kalindi_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/cik.c

867

ARRAY_SIZE(godavari_golden_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

870

ARRAY_SIZE(kalindi_golden_common_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

873

ARRAY_SIZE(kalindi_golden_spm_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

878

ARRAY_SIZE(spectre_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/cik.c

88

.codec_count = ARRAY_SIZE(cik_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/cik.c

881

ARRAY_SIZE(spectre_golden_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

884

ARRAY_SIZE(spectre_golden_common_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

887

ARRAY_SIZE(spectre_golden_spm_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

892

ARRAY_SIZE(hawaii_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/cik.c

895

ARRAY_SIZE(hawaii_golden_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

898

ARRAY_SIZE(hawaii_golden_common_registers));

sys/dev/pci/drm/amd/amdgpu/cik.c

901

ARRAY_SIZE(hawaii_golden_spm_registers));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1378

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

154

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

157

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

162

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

165

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1355

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1349

for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

73

if (fb_channel_number >= ARRAY_SIZE(df_v1_7_channel_number))

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

300

if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3898

(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3903

(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3908

(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3924

(const u32)ARRAY_SIZE(golden_settings_gc_10_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3927

(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3932

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3935

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3940

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3943

(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3948

(const u32)ARRAY_SIZE(golden_settings_gc_10_3));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3951

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3956

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3961

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3966

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3971

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3976

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3982

(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3987

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3992

(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4713

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4726

reg_count = ARRAY_SIZE(gc_cp_reg_list_10);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4739

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8221

for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8229

for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8238

for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9653

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9667

reg_count = ARRAY_SIZE(gc_cp_reg_list_10);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9697

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9722

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9736

reg_count = ARRAY_SIZE(gc_cp_reg_list_10);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9767

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1534

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1547

reg_count = ARRAY_SIZE(gc_cp_reg_list_11);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1560

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

499

(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

506

(const u32)ARRAY_SIZE(golden_settings_gc_11_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7022

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7036

reg_count = ARRAY_SIZE(gc_cp_reg_list_11);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7066

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7091

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7105

reg_count = ARRAY_SIZE(gc_cp_reg_list_11);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7138

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1351

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1364

reg_count = ARRAY_SIZE(gc_cp_reg_list_12);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1377

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3595

(const u32)ARRAY_SIZE(golden_settings_gc_12_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3600

(const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5106

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5120

reg_count = ARRAY_SIZE(gc_cp_reg_list_12);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5145

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5170

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5184

reg_count = ARRAY_SIZE(gc_cp_reg_list_12);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5210

reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2365

(u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

402

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3209

(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3213

(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

996

ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

998

ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1496

(((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1498

(((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1500

(((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1517

for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1520

for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1528

for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1554

for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1580

for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1628

for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2067

const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2068

const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3938

ARRAY_SIZE(unique_indices),

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3941

ARRAY_SIZE(indirect_start_offsets));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3963

for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3970

for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

744

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

747

ARRAY_SIZE(golden_settings_iceland_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

750

ARRAY_SIZE(iceland_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

755

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

758

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

761

ARRAY_SIZE(fiji_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

767

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

770

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

773

ARRAY_SIZE(tonga_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

778

ARRAY_SIZE(golden_settings_vegam_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

781

ARRAY_SIZE(vegam_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

787

ARRAY_SIZE(golden_settings_polaris11_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

790

ARRAY_SIZE(polaris11_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

795

ARRAY_SIZE(golden_settings_polaris10_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

798

ARRAY_SIZE(polaris10_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

814

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

817

ARRAY_SIZE(cz_golden_settings_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

820

ARRAY_SIZE(cz_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

825

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

828

ARRAY_SIZE(stoney_golden_settings_a11));

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

831

ARRAY_SIZE(stoney_golden_common_all));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1102

ARRAY_SIZE(golden_settings_gc_9_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1105

ARRAY_SIZE(golden_settings_gc_9_0_vg10));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1110

ARRAY_SIZE(golden_settings_gc_9_2_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1113

ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1118

ARRAY_SIZE(golden_settings_gc_9_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1121

ARRAY_SIZE(golden_settings_gc_9_0_vg20));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1126

ARRAY_SIZE(golden_settings_gc_9_4_1_arct));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1131

ARRAY_SIZE(golden_settings_gc_9_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1135

ARRAY_SIZE(golden_settings_gc_9_1_rv2));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1139

ARRAY_SIZE(golden_settings_gc_9_1_rv1));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1144

ARRAY_SIZE(golden_settings_gc_9_1_rn));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1157

(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2186

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2199

reg_count = ARRAY_SIZE(gc_cp_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2836

unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2844

ARRAY_SIZE(indirect_start_offsets));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2899

for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2904

for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4681

for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5209

ARRAY_SIZE(rlcg_access_gc_9_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6742

if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6864

for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6883

for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6904

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6917

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6954

for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6997

for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7017

for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7022

for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7027

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7032

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7059

for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7253

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7267

reg_count = ARRAY_SIZE(gc_cp_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7298

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7312

reg_count = ARRAY_SIZE(gc_cp_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

706

for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

727

for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

750

for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

771

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

794

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

835

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

881

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

915

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

940

for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

945

for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

950

for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

955

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

960

for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1426

{ VML2_WALKER_MEM, ARRAY_SIZE(vml2_walker_mems), 1, 1,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1471

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1514

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_edc_counter_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1620

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_utc_blocks); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

521

ARRAY_SIZE(sgpr112_init_regs_aldebaran),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

546

ARRAY_SIZE(sgpr96_init_regs_aldebaran),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

586

ARRAY_SIZE(sgpr64_init_regs_aldebaran),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

664

ARRAY_SIZE(vgpr_init_regs_aldebaran),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

729

ARRAY_SIZE(golden_settings_gc_9_4_2_alde));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

736

ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

741

ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1011

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1025

reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1727

ARRAY_SIZE(rlcg_access_gc_9_4_3));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4400

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4430

for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4468

for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4490

for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4581

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4604

reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4650

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4671

reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

90

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

92

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

86

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

89

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

85

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

88

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

674

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

691

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

78

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

81

ARRAY_SIZE(golden_settings_iceland_a11));

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

832

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

849

for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

127

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

130

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

135

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

138

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

145

ARRAY_SIZE(golden_settings_polaris11_a11));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

150

ARRAY_SIZE(golden_settings_polaris10_a11));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

155

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

160

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

163

ARRAY_SIZE(golden_settings_stoney_common));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2110

ARRAY_SIZE(golden_settings_mmhub_1_0_0));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2113

ARRAY_SIZE(golden_settings_athub_1_0_0));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2120

ARRAY_SIZE(golden_settings_athub_1_0_0));

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

429

for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

435

for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

443

for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

449

for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

688

cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

694

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega10) ?

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

698

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega12) ?

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

702

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega20) ?

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

706

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_arcturus) ?

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

711

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_raven) ?

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

716

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_renoir) ?

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

721

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_aldebaran) ?

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

204

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

346

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

176

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

318

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

176

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

318

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

366

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11));

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

370

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_2));

sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c

144

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_3));

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

382

(const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1));

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

116

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0));

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

166

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_5, ARRAY_SIZE(jpeg_reg_list_2_5));

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

131

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_3_0, ARRAY_SIZE(jpeg_reg_list_3_0));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

142

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1297

ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1322

ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1431

ARRAY_SIZE(jpeg_v4_0_3_err_codes)))

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

215

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_3, ARRAY_SIZE(jpeg_reg_list_4_0_3));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

173

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_5, ARRAY_SIZE(jpeg_reg_list_4_0_5));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

119

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0, ARRAY_SIZE(jpeg_reg_list_5_0));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1046

ARRAY_SIZE(jpeg_v5_0_1_err_codes)))

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

207

r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

148

if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes))

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

159

(x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes)))

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

132

if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

143

(x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

764

for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

805

for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

824

for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1240

for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1279

for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1297

for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1319

for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1339

for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

707

ARRAY_SIZE(mmhub_v1_8_ce_reg_list),

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

709

ARRAY_SIZE(mmhub_v1_8_ras_memory_list),

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

715

ARRAY_SIZE(mmhub_v1_8_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

717

ARRAY_SIZE(mmhub_v1_8_ras_memory_list),

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

747

ARRAY_SIZE(mmhub_v1_8_ce_reg_list),

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

751

ARRAY_SIZE(mmhub_v1_8_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

828

ARRAY_SIZE(mmhub_v1_8_err_codes)))

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

157

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_navi1x) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

162

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_sienna_cichlid) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

166

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_beige_goby) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

97

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vangogh) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

113

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_0) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

120

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_1) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

111

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_2) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

205

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

210

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3_1) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

105

mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_1_0) ?

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1601

for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1640

for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1658

for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1682

for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_err_status_regs); i++) {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

285

ARRAY_SIZE(

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

289

ARRAY_SIZE(

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

293

ARRAY_SIZE(

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

299

ARRAY_SIZE(

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

303

ARRAY_SIZE(

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

307

ARRAY_SIZE(

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

202

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

352

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/nv.c

102

.codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

128

.codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/nv.c

133

.codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/nv.c

165

.codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

170

.codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/nv.c

175

.codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/nv.c

187

.codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

206

.codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

394

for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/nv.c

75

.codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

91

.codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

957

ARRAY_SIZE(sriov_sc_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

959

ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));

sys/dev/pci/drm/amd/amdgpu/nv.c

963

ARRAY_SIZE(sriov_sc_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/nv.c

965

ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

100

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

103

ARRAY_SIZE(golden_settings_iceland_a11));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

204

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

207

ARRAY_SIZE(golden_settings_fiji_a10));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

212

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

215

ARRAY_SIZE(golden_settings_tonga_a11));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

222

ARRAY_SIZE(golden_settings_polaris11_a11));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

227

ARRAY_SIZE(golden_settings_polaris10_a11));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

232

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

235

ARRAY_SIZE(cz_golden_settings_a11));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

240

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

243

ARRAY_SIZE(stoney_golden_settings_a11));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1800

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2357

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2379

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2650

for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

523

ARRAY_SIZE(golden_settings_sdma_4));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

526

ARRAY_SIZE(golden_settings_sdma_vg10));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

531

ARRAY_SIZE(golden_settings_sdma_4));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

534

ARRAY_SIZE(golden_settings_sdma_vg12));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

539

ARRAY_SIZE(golden_settings_sdma0_4_2_init));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

542

ARRAY_SIZE(golden_settings_sdma0_4_2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

545

ARRAY_SIZE(golden_settings_sdma1_4_2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

550

ARRAY_SIZE(golden_settings_sdma_arct));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

555

ARRAY_SIZE(golden_settings_sdma_aldebaran));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

561

ARRAY_SIZE(golden_settings_sdma_4_1));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

565

ARRAY_SIZE(golden_settings_sdma_rv2));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

569

ARRAY_SIZE(golden_settings_sdma_rv1));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

574

ARRAY_SIZE(golden_settings_sdma_4_3));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

176

for (i = 0; i < ARRAY_SIZE(sdma_v4_4_ras_fields); i++) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1403

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2054

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2076

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2473

ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2475

ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2505

ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2574

ARRAY_SIZE(sdma_v4_4_2_err_codes)))

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1384

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1876

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1898

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

242

(const u32)ARRAY_SIZE(golden_settings_sdma_5));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

245

(const u32)ARRAY_SIZE(golden_settings_sdma_nv10));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

250

(const u32)ARRAY_SIZE(golden_settings_sdma_5));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

253

(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

259

(const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

263

(const u32)ARRAY_SIZE(golden_settings_sdma_5));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

266

(const u32)ARRAY_SIZE(golden_settings_sdma_nv12));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

271

(const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1308

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1878

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1900

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1312

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1689

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1711

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1298

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1622

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1644

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);

sys/dev/pci/drm/amd/amdgpu/si.c

1259

for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/si.c

2172

ARRAY_SIZE(tahiti_golden_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2175

ARRAY_SIZE(tahiti_golden_rlc_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2178

ARRAY_SIZE(tahiti_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/si.c

2181

ARRAY_SIZE(tahiti_golden_registers2));

sys/dev/pci/drm/amd/amdgpu/si.c

2186

ARRAY_SIZE(pitcairn_golden_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2189

ARRAY_SIZE(pitcairn_golden_rlc_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2192

ARRAY_SIZE(pitcairn_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/si.c

2197

ARRAY_SIZE(verde_golden_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2200

ARRAY_SIZE(verde_golden_rlc_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2203

ARRAY_SIZE(verde_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/si.c

2206

ARRAY_SIZE(verde_pg_init));

sys/dev/pci/drm/amd/amdgpu/si.c

2211

ARRAY_SIZE(oland_golden_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2214

ARRAY_SIZE(oland_golden_rlc_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2217

ARRAY_SIZE(oland_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/si.c

2222

ARRAY_SIZE(hainan_golden_registers));

sys/dev/pci/drm/amd/amdgpu/si.c

2225

ARRAY_SIZE(hainan_golden_registers2));

sys/dev/pci/drm/amd/amdgpu/si.c

2228

ARRAY_SIZE(hainan_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/si.c

940

.codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/si.c

992

.codec_count = ARRAY_SIZE(tahiti_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/soc15.c

114

.codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/soc15.c

132

.codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/soc15.c

150

.codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/soc15.c

163

.codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/soc15.c

186

.codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc15.c

443

for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/soc15.c

98

.codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/soc21.c

110

.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc21.c

115

.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/soc21.c

135

.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc21.c

140

.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/soc21.c

315

for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/soc21.c

63

.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc21.c

68

.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/soc21.c

836

ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/soc21.c

838

ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));

sys/dev/pci/drm/amd/amdgpu/soc21.c

842

ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc21.c

844

ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));

sys/dev/pci/drm/amd/amdgpu/soc21.c

88

.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc21.c

93

.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),

sys/dev/pci/drm/amd/amdgpu/soc24.c

175

for (i = 0; i < ARRAY_SIZE(soc24_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdgpu/soc24.c

56

.codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_encode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/soc24.c

69

.codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_decode_array_vcn0),

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

601

page_pfn, ARRAY_SIZE(page_pfn));

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

644

page_pfn, ARRAY_SIZE(page_pfn));

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

675

0, ARRAY_SIZE(entries), UMC_ECC_NEW_DETECTED_TAG);

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

174

for (t = 0; t < ARRAY_SIZE(umc_v8_10_channelnum_map_colbit_table); t++)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

131

uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1978

uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2012

uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

233

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_2_0, ARRAY_SIZE(vcn_reg_list_2_0));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

407

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_2_5, ARRAY_SIZE(vcn_reg_list_2_5));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

305

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_3_0, ARRAY_SIZE(vcn_reg_list_3_0));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

256

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0, ARRAY_SIZE(vcn_reg_list_4_0));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1919

ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1944

ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2049

ARRAY_SIZE(vcn_v4_0_3_err_codes)))

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

245

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

233

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_5, ARRAY_SIZE(vcn_reg_list_4_0_5));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

193

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0, ARRAY_SIZE(vcn_reg_list_5_0));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1674

ARRAY_SIZE(vcn_v5_0_1_err_codes)))

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

225

r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1));

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

147

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

284

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

183

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

347

for (i = 0; i < ARRAY_SIZE(ih); i++) {

sys/dev/pci/drm/amd/amdgpu/vi.c

128

.codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/vi.c

153

.codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array),

sys/dev/pci/drm/amd/amdgpu/vi.c

199

.codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/vi.c

252

.codec_count = ARRAY_SIZE(cz_video_codecs_decode_array),

sys/dev/pci/drm/amd/amdgpu/vi.c

499

ARRAY_SIZE(iceland_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/vi.c

504

ARRAY_SIZE(fiji_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/vi.c

509

ARRAY_SIZE(tonga_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/vi.c

514

ARRAY_SIZE(cz_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/vi.c

519

ARRAY_SIZE(stoney_mgcg_cgcg_init));

sys/dev/pci/drm/amd/amdgpu/vi.c

846

for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3240

#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1587

num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1591

num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1595

num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1599

num_of_cache_types = ARRAY_SIZE(tonga_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1603

num_of_cache_types = ARRAY_SIZE(fiji_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1607

num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1611

num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1615

num_of_cache_types = ARRAY_SIZE(polaris12_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1619

num_of_cache_types = ARRAY_SIZE(vegam_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1625

num_of_cache_types = ARRAY_SIZE(vega10_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1629

num_of_cache_types = ARRAY_SIZE(vega12_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1634

num_of_cache_types = ARRAY_SIZE(vega20_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1638

num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1650

num_of_cache_types = ARRAY_SIZE(raven_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1654

num_of_cache_types = ARRAY_SIZE(renoir_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1661

num_of_cache_types = ARRAY_SIZE(navi10_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1665

num_of_cache_types = ARRAY_SIZE(navi14_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1669

num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1673

num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1677

num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1681

num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1685

num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1689

num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1693

num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1697

num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1722

num_of_cache_types = ARRAY_SIZE(dummy_cache_info);

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

797

num_attrs = ARRAY_SIZE(perf_attr_iommu);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1026

if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13285

if (ddc_line >= ARRAY_SIZE(dev->dm.fused_io))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2159

for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

814

if (ddc_line >= ARRAY_SIZE(adev->dm.fused_io)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8497

n = ARRAY_SIZE(common_modes);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8641

for (i = 0; i < ARRAY_SIZE(common_rates); i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

932

if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

952

if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

83

*count = ARRAY_SIZE(pipe_crc_sources);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3527

for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3555

for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3562

for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

125

for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1819

ARRAY_SIZE(formats));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1910

for (i = 0; i < ARRAY_SIZE(video_formats); i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

704

uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

708

for (i = 0; i < ARRAY_SIZE(max_comp_block); i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

715

for (j = 0; j < ARRAY_SIZE(gfx12_modifiers) - 1; j++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

716

for (i = 0; i < ARRAY_SIZE(max_comp_block); i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

721

for (i = 0; i < ARRAY_SIZE(gfx12_modifiers); i++)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

793

for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

813

for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

822

for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

205

ARRAY_SIZE(amdgpu_dm_wb_formats),

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

905

if (dcn314_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

856

if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

176

for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2590

for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2603

for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2607

return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2678

for (i = 0; i < ARRAY_SIZE(res_ctx->dio_link_enc_ref_cnts); i++)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

564

uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1994

for (i = 0; i < ARRAY_SIZE(fe_clk_en); i++) {

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1185

audio_array_size = ARRAY_SIZE(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1190

audio_array_size = ARRAY_SIZE(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1195

audio_array_size = ARRAY_SIZE(

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1391

for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

692

for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1177

audio_array_size = ARRAY_SIZE(

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1182

audio_array_size = ARRAY_SIZE(

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1187

audio_array_size = ARRAY_SIZE(

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

281

for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

249

arr_reg_val, ARRAY_SIZE(arr_reg_val));

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

289

arr_reg_val, ARRAY_SIZE(arr_reg_val));

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

460

arr_reg_val, ARRAY_SIZE(arr_reg_val));

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

160

i2c_command.number_of_payloads = ARRAY_SIZE(i2c_payloads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2327

int count = ARRAY_SIZE(prime_numbers);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

600

while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

610

while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

629

if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

153

for (i = 0; i < ARRAY_SIZE(mandatory_dpcd_blocks); i++) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1215

arr_reg_val, ARRAY_SIZE(arr_reg_val));

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

568

arr_reg_val, ARRAY_SIZE(arr_reg_val));

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

627

if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

671

if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

632

if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

716

if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

721

if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

727

if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

742

if (!enc10 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))