bin/csh/sem.c

596

if (pipe(pv) == -1)

bin/ksh/io.c

295

if (pipe(lpv) == -1)

bin/pax/ar_io.c

1248

if (pipe(fds) == -1)

include/unistd.h

364

int pipe(int *);

lib/libc/hidden/unistd.h

115

PROTO_NORMAL(pipe);

lib/libcurses/base/lib_mouse.c

655

if (pipe(handles) < 0) {

lib/libkvm/kvm_file2.c

693

struct pipe pipe;

lib/libkvm/kvm_file2.c

695

if (KREAD(kd, (u_long)fp->f_data, &pipe)) {

lib/libkvm/kvm_file2.c

699

kf->pipe_peer = PTRTOINT64(pipe.pipe_peer);

lib/libkvm/kvm_file2.c

700

kf->pipe_state = pipe.pipe_state;

libexec/fingerd/fingerd.c

200

if (pipe(p) == -1)

libexec/ftpd/popen.c

69

if (pipe(pdes) == -1)

libexec/spamd-setup/spamd-setup.c

265

if (pipe(pdes) != 0)

libexec/spamd-setup/spamd-setup.c

655

if (pipe(pdes) != 0)

libexec/spamd/grey.c

173

if (pipe(pdes) != 0) {

libexec/spamd/spamd.c

1480

if (pipe(greypipe) == -1) {

libexec/spamd/spamd.c

1485

if (pipe(trappipe) == -1) {

regress/lib/libc/explicit_bzero/explicit_bzero.c

131

ASSERT_EQ(0, pipe(fds));

regress/lib/libc/popen/popen.c

52

FILE *pipe;

regress/lib/libc/popen/popen.c

62

if ((pipe = popen(command, "w")) == NULL)

regress/lib/libc/popen/popen.c

65

if (fwrite(buffer, sizeof(char), BUFSIZE, pipe) != BUFSIZE)

regress/lib/libc/popen/popen.c

68

if (pclose(pipe) == -1)

regress/lib/libc/popen/popen.c

73

if ((pipe = popen(command, "r")) == NULL)

regress/lib/libc/popen/popen.c

77

while ((in = fgetc(pipe)) != EOF)

regress/lib/libc/popen/popen.c

93

if (pclose(pipe) == -1)

regress/lib/libc/sys/t_fsync.c

72

ATF_REQUIRE(pipe(fd) == 0);

regress/lib/libc/sys/t_pipe.c

93

RL(pipe(pp));

regress/lib/libc/sys/t_poll.c

106

pipe(pf);

regress/lib/libc/sys/t_poll.c

165

ATF_REQUIRE_EQ(pipe(fds), 0);

regress/lib/libc/sys/t_pollts.c

65

ATF_REQUIRE_EQ(pipe(fds), 0);

regress/lib/libc/sys/t_ptrace.c

159

ATF_REQUIRE(pipe(fds_toparent) == 0);

regress/lib/libc/sys/t_ptrace.c

160

ATF_REQUIRE(pipe(fds_fromparent) == 0);

regress/lib/libc/sys/t_sendrecv.c

121

error = pipe(fd);

regress/lib/libc/sys/t_write.c

113

ATF_REQUIRE(pipe(fds) == 0);

regress/lib/libc/sys/t_write.c

229

ATF_REQUIRE(pipe(fd) != -1);

regress/lib/libpthread/cancel2/cancel2.c

85

CHECKe(pipe(pipe_fd));

regress/lib/libpthread/dlopen/dlopen.c

302

if (pipe(fds))

regress/lib/libpthread/dlopen/dlopen.c

355

if (pipe(fds))

regress/lib/libpthread/poll/poll.c

106

CHECKe(pipe(tube));

regress/lib/libpthread/restart/read/read.c

25

CHECKe(pipe(fds));

regress/lib/libpthread/restart/readv/readv.c

27

CHECKe(pipe(fds));

regress/lib/libpthread/siginterrupt/siginterrupt.c

24

CHECKe(pipe(fds));

regress/sys/dev/kcov/kcov.c

503

if (pipe(pip) == -1)

regress/sys/dev/wscons/sigio.c

105

if (pipe(cfd) == -1)

regress/sys/dev/wscons/sigio.c

107

if (pipe(pfd) == -1)

regress/sys/kern/fchdir/fchdir.c

31

if (pipe(fds))

regress/sys/kern/flock/flock.c

117

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

1258

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

188

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

257

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

529

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

601

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

678

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

749

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

897

if (pipe(pfd) < 0)

regress/sys/kern/flock/flock.c

980

if (pipe(pfd) < 0)

regress/sys/kern/fork-exit/fork-exit.c

305

if (pipe(pipefds) == -1)

regress/sys/kern/kqueue/kqueue-pipe.c

54

ASS(pipe(fd) == 0,

regress/sys/kern/kqueue/kqueue-process.c

45

if (pipe(pfd1) == -1)

regress/sys/kern/kqueue/kqueue-process.c

47

if (pipe(pfd2) == -1)

regress/sys/kern/kqueue/kqueue-regress.c

211

if (pipe(fds) == -1)

regress/sys/kern/kqueue/kqueue-regress.c

255

if (pipe(fds) == -1)

regress/sys/kern/kqueue/kqueue-regress.c

97

if (pipe(p0) == -1)

regress/sys/kern/kqueue/kqueue-regress.c

99

if (pipe(p1) == -1)

regress/sys/kern/pipe/test-close.c

68

if (pipe(pip) == -1)

regress/sys/kern/pipe/test-kqueue.c

175

if (pipe(ctx->c_pipe) == -1)

regress/sys/kern/pipe/test-ping-pong.c

44

if (pipe(pip[0]) == -1)

regress/sys/kern/pipe/test-ping-pong.c

46

if (pipe(pip[1]) == -1)

regress/sys/kern/pipe/test-run-down.c

84

if (pipe(ctx->c_pipe) == -1)

regress/sys/kern/pipe/test-select.c

39

if (pipe(pip) == -1)

regress/sys/kern/pipe/test-thundering-herd.c

95

if (pipe(ctx.c_pipe) == -1)

regress/sys/kern/pipe/test-thundering-herd.c

97

if (pipe(ctx.c_cv) == -1)

regress/sys/kern/pledge/generic/manager.c

197

if (pipe(fildes) != 0) {

regress/sys/kern/poll/poll_iocond.c

128

if (pipe(fds) == -1)

regress/sys/kern/poll/poll_regevent.c

40

if (pipe(p1) == -1)

regress/sys/kern/poll/poll_regevent.c

42

if (pipe(p2) == -1)

regress/sys/kern/ptrace2/ptrace_test.c

188

ATF_REQUIRE(pipe(cpipe) == 0);

regress/sys/kern/ptrace2/ptrace_test.c

238

ATF_REQUIRE(pipe(cpipe) == 0);

regress/sys/kern/ptrace2/ptrace_test.c

252

ATF_REQUIRE(pipe(dpipe) == 0);

regress/sys/kern/ptrace2/ptrace_test.c

332

ATF_REQUIRE(pipe(cpipe) == 0);

regress/sys/kern/ptrace2/ptrace_test.c

346

ATF_REQUIRE(pipe(dpipe) == 0);

regress/sys/kern/rlimit-file/rlim-file.c

30

if (pipe(fds) == 0)

regress/sys/kern/select/select_iocond.c

129

if (pipe(fds) == -1)

regress/sys/kern/select/select_regevent.c

41

if (pipe(p1) == -1)

regress/sys/kern/select/select_regevent.c

43

if (pipe(p2) == -1)

regress/sys/kern/signal/sigio/sigio_pipe.c

31

assert(pipe(fds) == 0);

regress/sys/kern/signal/sigio/sigio_pipe.c

40

assert(pipe(fds) == 0);

regress/sys/kern/signal/sigio/sigio_pipe.c

49

assert(pipe(fds) == 0);

regress/sys/kern/signal/sigio/sigio_pipe.c

58

assert(pipe(fds) == 0);

regress/sys/kern/signal/sigio/sigio_pipe.c

67

assert(pipe(fds) == 0);

regress/sys/kern/signal/sigio/sigio_pipe.c

76

assert(pipe(fds) == 0);

regress/sys/kern/xonly/xonly.c

215

pipe(p);

regress/sys/net/pf_print/pf_print_test.c

90

if (pipe(fds) == -1)

sbin/init/init.c

996

if (pipe(p) == -1)

sbin/shutdown/shutdown.c

314

if (pipe(fd) == -1) {

sbin/unwind/libunbound/util/tube.c

57

#define socketpair(f, t, p, sv) pipe(sv)

sys/dev/fdt/rkpciephy.c

164

struct regmap *phy, *pipe;

sys/dev/fdt/rkpciephy.c

206

pipe = regmap_byphandle(grf);

sys/dev/fdt/rkpciephy.c

207

if (pipe != NULL) {

sys/dev/fdt/rkpciephy.c

215

regmap_write_4(pipe, RK3588_PHP_GRF_PCIESEL_CON, reg);

sys/dev/ic/qwx.c

14268

struct qwx_ce_pipe *pipe = &sc->ce.ce_pipe[ep->ul_pipe_id];

sys/dev/ic/qwx.c

14306

ctx = pipe->src_ring->per_transfer_context[pipe->src_ring->write_index];

sys/dev/ic/qwx.c

21699

qwx_ce_completed_send_next(struct qwx_ce_pipe *pipe)

sys/dev/ic/qwx.c

21701

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

21711

sw_index = pipe->src_ring->sw_index;

sys/dev/ic/qwx.c

21712

nentries_mask = pipe->src_ring->nentries_mask;

sys/dev/ic/qwx.c

21714

srng = &sc->hal.srng_list[pipe->src_ring->hal_ring_id];

sys/dev/ic/qwx.c

21724

ctx = pipe->src_ring->per_transfer_context[sw_index];

sys/dev/ic/qwx.c

21728

pipe->src_ring->sw_index = sw_index;

sys/dev/ic/qwx.c

21740

qwx_ce_tx_process_cb(struct qwx_ce_pipe *pipe)

sys/dev/ic/qwx.c

21742

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

21748

while ((tx_data = qwx_ce_completed_send_next(pipe)) != NULL) {

sys/dev/ic/qwx.c

21753

if ((!pipe->send_cb) || sc->hw_params.credit_flow) {

sys/dev/ic/qwx.c

21764

pipe->pipe_num, m->m_len);

sys/dev/ic/qwx.c

21765

pipe->send_cb(sc, m);

sys/dev/ic/qwx.c

21774

struct qwx_ce_pipe *pipe = &sc->ce.ce_pipe[pipe_id];

sys/dev/ic/qwx.c

21777

if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && attr->src_nentries)

sys/dev/ic/qwx.c

21778

qwx_ce_tx_process_cb(pipe);

sys/dev/ic/qwx.c

22087

struct qwx_ce_pipe *pipe;

sys/dev/ic/qwx.c

22091

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwx.c

22094

if (pipe->src_ring) {

sys/dev/ic/qwx.c

22095

qwx_ce_free_ring(sc, pipe->src_ring);

sys/dev/ic/qwx.c

22096

pipe->src_ring = NULL;

sys/dev/ic/qwx.c

22099

if (pipe->dest_ring) {

sys/dev/ic/qwx.c

22100

qwx_ce_free_ring(sc, pipe->dest_ring);

sys/dev/ic/qwx.c

22101

pipe->dest_ring = NULL;

sys/dev/ic/qwx.c

22104

if (pipe->status_ring) {

sys/dev/ic/qwx.c

22105

qwx_ce_free_ring(sc, pipe->status_ring);

sys/dev/ic/qwx.c

22106

pipe->status_ring = NULL;

sys/dev/ic/qwx.c

22112

qwx_ce_alloc_src_ring_transfer_contexts(struct qwx_ce_pipe *pipe,

sys/dev/ic/qwx.c

22115

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22121

txdata = mallocarray(pipe->src_ring->nentries, sizeof(*txdata),

sys/dev/ic/qwx.c

22126

size = sizeof(*txdata) * pipe->src_ring->nentries;

sys/dev/ic/qwx.c

22129

for (i = 0; i < pipe->src_ring->nentries; i++) {

sys/dev/ic/qwx.c

22142

pipe->src_ring->per_transfer_context[i] = ctx;

sys/dev/ic/qwx.c

22149

qwx_ce_alloc_dest_ring_transfer_contexts(struct qwx_ce_pipe *pipe,

sys/dev/ic/qwx.c

22152

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22158

rxdata = mallocarray(pipe->dest_ring->nentries, sizeof(*rxdata),

sys/dev/ic/qwx.c

22163

size = sizeof(*rxdata) * pipe->dest_ring->nentries;

sys/dev/ic/qwx.c

22166

for (i = 0; i < pipe->dest_ring->nentries; i++) {

sys/dev/ic/qwx.c

22179

pipe->dest_ring->per_transfer_context[i] = ctx;

sys/dev/ic/qwx.c

22233

struct qwx_ce_pipe *pipe = &sc->ce.ce_pipe[ce_id];

sys/dev/ic/qwx.c

22239

pipe->attr_flags = attr->flags;

sys/dev/ic/qwx.c

22242

pipe->send_cb = attr->send_cb;

sys/dev/ic/qwx.c

22248

pipe->src_ring = ring;

sys/dev/ic/qwx.c

22249

if (qwx_ce_alloc_src_ring_transfer_contexts(pipe, attr))

sys/dev/ic/qwx.c

22254

pipe->recv_cb = attr->recv_cb;

sys/dev/ic/qwx.c

22260

pipe->dest_ring = ring;

sys/dev/ic/qwx.c

22261

if (qwx_ce_alloc_dest_ring_transfer_contexts(pipe, attr))

sys/dev/ic/qwx.c

22268

pipe->status_ring = ring;

sys/dev/ic/qwx.c

22275

qwx_ce_rx_pipe_cleanup(struct qwx_ce_pipe *pipe)

sys/dev/ic/qwx.c

22277

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22278

struct qwx_ce_ring *ring = pipe->dest_ring;

sys/dev/ic/qwx.c

22283

if (!(ring && pipe->buf_sz))

sys/dev/ic/qwx.c

22345

struct qwx_ce_pipe *pipe;

sys/dev/ic/qwx.c

22351

pipe = &sc->ce.ce_pipe[pipe_num];

sys/dev/ic/qwx.c

22352

qwx_ce_rx_pipe_cleanup(pipe);

sys/dev/ic/qwx.c

22362

struct qwx_ce_pipe *pipe;

sys/dev/ic/qwx.c

22369

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwx.c

22370

pipe->pipe_num = i;

sys/dev/ic/qwx.c

22371

pipe->sc = sc;

sys/dev/ic/qwx.c

22372

pipe->buf_sz = attr->src_sz_max;

sys/dev/ic/qwx.c

22482

struct qwx_ce_pipe *pipe;

sys/dev/ic/qwx.c

22487

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwx.c

22489

if (pipe->src_ring) {

sys/dev/ic/qwx.c

22490

ret = qwx_ce_init_ring(sc, pipe->src_ring, i,

sys/dev/ic/qwx.c

22499

pipe->src_ring->write_index = 0;

sys/dev/ic/qwx.c

22500

pipe->src_ring->sw_index = 0;

sys/dev/ic/qwx.c

22503

if (pipe->dest_ring) {

sys/dev/ic/qwx.c

22504

ret = qwx_ce_init_ring(sc, pipe->dest_ring, i,

sys/dev/ic/qwx.c

22513

pipe->rx_buf_needed = pipe->dest_ring->nentries ?

sys/dev/ic/qwx.c

22514

pipe->dest_ring->nentries - 2 : 0;

sys/dev/ic/qwx.c

22516

pipe->dest_ring->write_index = 0;

sys/dev/ic/qwx.c

22517

pipe->dest_ring->sw_index = 0;

sys/dev/ic/qwx.c

22520

if (pipe->status_ring) {

sys/dev/ic/qwx.c

22521

ret = qwx_ce_init_ring(sc, pipe->status_ring, i,

sys/dev/ic/qwx.c

22530

pipe->status_ring->write_index = 0;

sys/dev/ic/qwx.c

22531

pipe->status_ring->sw_index = 0;

sys/dev/ic/qwx.c

22562

qwx_ce_rx_buf_enqueue_pipe(struct qwx_ce_pipe *pipe, bus_dmamap_t map)

sys/dev/ic/qwx.c

22564

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22565

struct qwx_ce_ring *ring = pipe->dest_ring;

sys/dev/ic/qwx.c

22602

pipe->rx_buf_needed--;

sys/dev/ic/qwx.c

22616

qwx_ce_rx_post_pipe(struct qwx_ce_pipe *pipe)

sys/dev/ic/qwx.c

22618

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22625

if (!pipe->dest_ring)

sys/dev/ic/qwx.c

22631

while (pipe->rx_buf_needed) {

sys/dev/ic/qwx.c

22638

if (pipe->buf_sz <= MCLBYTES)

sys/dev/ic/qwx.c

22641

MCLGETL(m, M_DONTWAIT, pipe->buf_sz);

sys/dev/ic/qwx.c

22647

idx = pipe->dest_ring->write_index;

sys/dev/ic/qwx.c

22648

ctx = pipe->dest_ring->per_transfer_context[idx];

sys/dev/ic/qwx.c

22651

m->m_len = m->m_pkthdr.len = pipe->buf_sz;

sys/dev/ic/qwx.c

22661

ret = qwx_ce_rx_buf_enqueue_pipe(pipe, rx_data->map);

sys/dev/ic/qwx.c

22682

struct qwx_ce_pipe *pipe;

sys/dev/ic/qwx.c

22687

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwx.c

22688

ret = qwx_ce_rx_post_pipe(pipe);

sys/dev/ic/qwx.c

22706

qwx_ce_completed_recv_next(struct qwx_ce_pipe *pipe,

sys/dev/ic/qwx.c

22709

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22718

sw_index = pipe->dest_ring->sw_index;

sys/dev/ic/qwx.c

22719

nentries_mask = pipe->dest_ring->nentries_mask;

sys/dev/ic/qwx.c

22721

srng = &sc->hal.srng_list[pipe->status_ring->hal_ring_id];

sys/dev/ic/qwx.c

22741

pipe->dest_ring->per_transfer_context[sw_index];

sys/dev/ic/qwx.c

22745

pipe->dest_ring->sw_index = sw_index;

sys/dev/ic/qwx.c

22747

pipe->rx_buf_needed++;

sys/dev/ic/qwx.c

22758

qwx_ce_recv_process_cb(struct qwx_ce_pipe *pipe)

sys/dev/ic/qwx.c

22760

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

22767

while (qwx_ce_completed_recv_next(pipe, &transfer_context,

sys/dev/ic/qwx.c

22789

pipe->pipe_num, m->m_len);

sys/dev/ic/qwx.c

22790

pipe->recv_cb(sc, m);

sys/dev/ic/qwx.c

22793

err = qwx_ce_rx_post_pipe(pipe);

sys/dev/ic/qwx.c

22796

__func__, pipe->pipe_num, err);

sys/dev/ic/qwx.c

22809

struct qwx_ce_pipe *pipe = &sc->ce.ce_pipe[ce_id];

sys/dev/ic/qwx.c

22814

if (qwx_ce_tx_process_cb(pipe))

sys/dev/ic/qwx.c

22818

if (pipe->recv_cb) {

sys/dev/ic/qwx.c

22819

if (qwx_ce_recv_process_cb(pipe))

sys/dev/ic/qwx.c

22830

struct qwx_ce_pipe *pipe = &sc->ce.ce_pipe[pipe_id];

sys/dev/ic/qwx.c

22846

if (pipe->attr_flags & CE_ATTR_DIS_INTR) {

sys/dev/ic/qwx.c

22850

write_index = pipe->src_ring->write_index;

sys/dev/ic/qwx.c

22852

sw_index = pipe->src_ring->sw_index;

sys/dev/ic/qwx.c

22857

num_used = pipe->src_ring->nentries - sw_index +

sys/dev/ic/qwx.c

22863

qwx_ce_poll_send_completed(sc, pipe->pipe_num);

sys/dev/ic/qwx.c

22871

write_index = pipe->src_ring->write_index;

sys/dev/ic/qwx.c

22872

nentries_mask = pipe->src_ring->nentries_mask;

sys/dev/ic/qwx.c

22874

srng = &sc->hal.srng_list[pipe->src_ring->hal_ring_id];

sys/dev/ic/qwx.c

22893

if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)

sys/dev/ic/qwx.c

22896

ctx = pipe->src_ring->per_transfer_context[write_index];

sys/dev/ic/qwx.c

22903

pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,

sys/dev/ic/qwx.c

6411

struct qwx_ce_pipe *pipe = arg;

sys/dev/ic/qwx.c

6412

struct qwx_softc *sc = pipe->sc;

sys/dev/ic/qwx.c

6415

((sc->msi_ce_irqmask & (1 << pipe->pipe_num)) == 0)) {

sys/dev/ic/qwx.c

6417

__func__, pipe->pipe_num);

sys/dev/ic/qwx.c

6421

return qwx_ce_per_engine_service(sc, pipe->pipe_num);

sys/dev/ic/qwz.c

11942

struct qwz_ce_pipe *pipe = &sc->ce.ce_pipe[ep->ul_pipe_id];

sys/dev/ic/qwz.c

11978

ctx = pipe->src_ring->per_transfer_context[pipe->src_ring->write_index];

sys/dev/ic/qwz.c

18987

qwz_ce_completed_send_next(struct qwz_ce_pipe *pipe)

sys/dev/ic/qwz.c

18989

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

18999

sw_index = pipe->src_ring->sw_index;

sys/dev/ic/qwz.c

19000

nentries_mask = pipe->src_ring->nentries_mask;

sys/dev/ic/qwz.c

19002

srng = &sc->hal.srng_list[pipe->src_ring->hal_ring_id];

sys/dev/ic/qwz.c

19012

ctx = pipe->src_ring->per_transfer_context[sw_index];

sys/dev/ic/qwz.c

19016

pipe->src_ring->sw_index = sw_index;

sys/dev/ic/qwz.c

19028

qwz_ce_send_done_cb(struct qwz_ce_pipe *pipe)

sys/dev/ic/qwz.c

19030

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19034

while ((tx_data = qwz_ce_completed_send_next(pipe)) != NULL) {

sys/dev/ic/qwz.c

19047

struct qwz_ce_pipe *pipe = &sc->ce.ce_pipe[pipe_id];

sys/dev/ic/qwz.c

19049

if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb)

sys/dev/ic/qwz.c

19050

pipe->send_cb(pipe);

sys/dev/ic/qwz.c

19336

struct qwz_ce_pipe *pipe;

sys/dev/ic/qwz.c

19340

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwz.c

19341

if (pipe->src_ring) {

sys/dev/ic/qwz.c

19342

qwz_ce_free_ring(sc, pipe->src_ring);

sys/dev/ic/qwz.c

19343

pipe->src_ring = NULL;

sys/dev/ic/qwz.c

19346

if (pipe->dest_ring) {

sys/dev/ic/qwz.c

19347

qwz_ce_free_ring(sc, pipe->dest_ring);

sys/dev/ic/qwz.c

19348

pipe->dest_ring = NULL;

sys/dev/ic/qwz.c

19351

if (pipe->status_ring) {

sys/dev/ic/qwz.c

19352

qwz_ce_free_ring(sc, pipe->status_ring);

sys/dev/ic/qwz.c

19353

pipe->status_ring = NULL;

sys/dev/ic/qwz.c

19359

qwz_ce_alloc_src_ring_transfer_contexts(struct qwz_ce_pipe *pipe,

sys/dev/ic/qwz.c

19362

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19368

txdata = mallocarray(pipe->src_ring->nentries, sizeof(*txdata),

sys/dev/ic/qwz.c

19373

size = sizeof(*txdata) * pipe->src_ring->nentries;

sys/dev/ic/qwz.c

19376

for (i = 0; i < pipe->src_ring->nentries; i++) {

sys/dev/ic/qwz.c

19389

pipe->src_ring->per_transfer_context[i] = ctx;

sys/dev/ic/qwz.c

19396

qwz_ce_alloc_dest_ring_transfer_contexts(struct qwz_ce_pipe *pipe,

sys/dev/ic/qwz.c

19399

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19405

rxdata = mallocarray(pipe->dest_ring->nentries, sizeof(*rxdata),

sys/dev/ic/qwz.c

19410

size = sizeof(*rxdata) * pipe->dest_ring->nentries;

sys/dev/ic/qwz.c

19413

for (i = 0; i < pipe->dest_ring->nentries; i++) {

sys/dev/ic/qwz.c

19426

pipe->dest_ring->per_transfer_context[i] = ctx;

sys/dev/ic/qwz.c

19480

struct qwz_ce_pipe *pipe = &sc->ce.ce_pipe[ce_id];

sys/dev/ic/qwz.c

19486

pipe->attr_flags = attr->flags;

sys/dev/ic/qwz.c

19489

pipe->send_cb = qwz_ce_send_done_cb;

sys/dev/ic/qwz.c

19495

pipe->src_ring = ring;

sys/dev/ic/qwz.c

19496

if (qwz_ce_alloc_src_ring_transfer_contexts(pipe, attr))

sys/dev/ic/qwz.c

19501

pipe->recv_cb = attr->recv_cb;

sys/dev/ic/qwz.c

19507

pipe->dest_ring = ring;

sys/dev/ic/qwz.c

19508

if (qwz_ce_alloc_dest_ring_transfer_contexts(pipe, attr))

sys/dev/ic/qwz.c

19515

pipe->status_ring = ring;

sys/dev/ic/qwz.c

19522

qwz_ce_rx_pipe_cleanup(struct qwz_ce_pipe *pipe)

sys/dev/ic/qwz.c

19524

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19525

struct qwz_ce_ring *ring = pipe->dest_ring;

sys/dev/ic/qwz.c

19530

if (!(ring && pipe->buf_sz))

sys/dev/ic/qwz.c

19592

struct qwz_ce_pipe *pipe;

sys/dev/ic/qwz.c

19596

pipe = &sc->ce.ce_pipe[pipe_num];

sys/dev/ic/qwz.c

19597

qwz_ce_rx_pipe_cleanup(pipe);

sys/dev/ic/qwz.c

19607

struct qwz_ce_pipe *pipe;

sys/dev/ic/qwz.c

19614

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwz.c

19615

pipe->pipe_num = i;

sys/dev/ic/qwz.c

19616

pipe->sc = sc;

sys/dev/ic/qwz.c

19617

pipe->buf_sz = attr->src_sz_max;

sys/dev/ic/qwz.c

19722

struct qwz_ce_pipe *pipe;

sys/dev/ic/qwz.c

19730

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwz.c

19732

if (pipe->src_ring) {

sys/dev/ic/qwz.c

19733

ret = qwz_ce_init_ring(sc, pipe->src_ring, i,

sys/dev/ic/qwz.c

19742

pipe->src_ring->write_index = 0;

sys/dev/ic/qwz.c

19743

pipe->src_ring->sw_index = 0;

sys/dev/ic/qwz.c

19746

if (pipe->dest_ring) {

sys/dev/ic/qwz.c

19747

ret = qwz_ce_init_ring(sc, pipe->dest_ring, i,

sys/dev/ic/qwz.c

19756

pipe->rx_buf_needed = pipe->dest_ring->nentries ?

sys/dev/ic/qwz.c

19757

pipe->dest_ring->nentries - 2 : 0;

sys/dev/ic/qwz.c

19759

pipe->dest_ring->write_index = 0;

sys/dev/ic/qwz.c

19760

pipe->dest_ring->sw_index = 0;

sys/dev/ic/qwz.c

19763

if (pipe->status_ring) {

sys/dev/ic/qwz.c

19764

ret = qwz_ce_init_ring(sc, pipe->status_ring, i,

sys/dev/ic/qwz.c

19773

pipe->status_ring->write_index = 0;

sys/dev/ic/qwz.c

19774

pipe->status_ring->sw_index = 0;

sys/dev/ic/qwz.c

19805

qwz_ce_rx_buf_enqueue_pipe(struct qwz_ce_pipe *pipe, bus_dmamap_t map)

sys/dev/ic/qwz.c

19807

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19808

struct qwz_ce_ring *ring = pipe->dest_ring;

sys/dev/ic/qwz.c

19845

pipe->rx_buf_needed--;

sys/dev/ic/qwz.c

19859

qwz_ce_rx_post_pipe(struct qwz_ce_pipe *pipe)

sys/dev/ic/qwz.c

19861

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19868

if (!pipe->dest_ring)

sys/dev/ic/qwz.c

19874

while (pipe->rx_buf_needed) {

sys/dev/ic/qwz.c

19881

if (pipe->buf_sz <= MCLBYTES)

sys/dev/ic/qwz.c

19884

MCLGETL(m, M_DONTWAIT, pipe->buf_sz);

sys/dev/ic/qwz.c

19890

idx = pipe->dest_ring->write_index;

sys/dev/ic/qwz.c

19891

ctx = pipe->dest_ring->per_transfer_context[idx];

sys/dev/ic/qwz.c

19894

m->m_len = m->m_pkthdr.len = pipe->buf_sz;

sys/dev/ic/qwz.c

19904

ret = qwz_ce_rx_buf_enqueue_pipe(pipe, rx_data->map);

sys/dev/ic/qwz.c

19925

struct qwz_ce_pipe *pipe;

sys/dev/ic/qwz.c

19930

pipe = &sc->ce.ce_pipe[i];

sys/dev/ic/qwz.c

19931

ret = qwz_ce_rx_post_pipe(pipe);

sys/dev/ic/qwz.c

19949

qwz_ce_completed_recv_next(struct qwz_ce_pipe *pipe,

sys/dev/ic/qwz.c

19952

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

19961

sw_index = pipe->dest_ring->sw_index;

sys/dev/ic/qwz.c

19962

nentries_mask = pipe->dest_ring->nentries_mask;

sys/dev/ic/qwz.c

19964

srng = &sc->hal.srng_list[pipe->status_ring->hal_ring_id];

sys/dev/ic/qwz.c

19984

pipe->dest_ring->per_transfer_context[sw_index];

sys/dev/ic/qwz.c

19988

pipe->dest_ring->sw_index = sw_index;

sys/dev/ic/qwz.c

19990

pipe->rx_buf_needed++;

sys/dev/ic/qwz.c

20001

qwz_ce_recv_process_cb(struct qwz_ce_pipe *pipe)

sys/dev/ic/qwz.c

20003

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

20010

while (qwz_ce_completed_recv_next(pipe, &transfer_context,

sys/dev/ic/qwz.c

20032

pipe->pipe_num, m->m_len);

sys/dev/ic/qwz.c

20033

pipe->recv_cb(sc, m);

sys/dev/ic/qwz.c

20036

err = qwz_ce_rx_post_pipe(pipe);

sys/dev/ic/qwz.c

20039

__func__, pipe->pipe_num, err);

sys/dev/ic/qwz.c

20052

struct qwz_ce_pipe *pipe = &sc->ce.ce_pipe[ce_id];

sys/dev/ic/qwz.c

20055

if (pipe->send_cb) {

sys/dev/ic/qwz.c

20056

if (pipe->send_cb(pipe))

sys/dev/ic/qwz.c

20060

if (pipe->recv_cb) {

sys/dev/ic/qwz.c

20061

if (qwz_ce_recv_process_cb(pipe))

sys/dev/ic/qwz.c

20072

struct qwz_ce_pipe *pipe = &sc->ce.ce_pipe[pipe_id];

sys/dev/ic/qwz.c

20088

if (pipe->attr_flags & CE_ATTR_DIS_INTR) {

sys/dev/ic/qwz.c

20092

write_index = pipe->src_ring->write_index;

sys/dev/ic/qwz.c

20094

sw_index = pipe->src_ring->sw_index;

sys/dev/ic/qwz.c

20099

num_used = pipe->src_ring->nentries - sw_index +

sys/dev/ic/qwz.c

20105

qwz_ce_poll_send_completed(sc, pipe->pipe_num);

sys/dev/ic/qwz.c

20113

write_index = pipe->src_ring->write_index;

sys/dev/ic/qwz.c

20114

nentries_mask = pipe->src_ring->nentries_mask;

sys/dev/ic/qwz.c

20116

srng = &sc->hal.srng_list[pipe->src_ring->hal_ring_id];

sys/dev/ic/qwz.c

20135

if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)

sys/dev/ic/qwz.c

20138

ctx = pipe->src_ring->per_transfer_context[write_index];

sys/dev/ic/qwz.c

20145

pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,

sys/dev/ic/qwz.c

3840

struct qwz_ce_pipe *pipe = arg;

sys/dev/ic/qwz.c

3841

struct qwz_softc *sc = pipe->sc;

sys/dev/ic/qwz.c

3844

((sc->msi_ce_irqmask & (1 << pipe->pipe_num)) == 0)) {

sys/dev/ic/qwz.c

3846

__func__, pipe->pipe_num);

sys/dev/ic/qwz.c

3850

return qwz_ce_per_engine_service(sc, pipe->pipe_num);

sys/dev/ic/qwzvar.h

1302

int (*send_cb)(struct qwz_ce_pipe *pipe);

sys/dev/pci/auich.c

1025

auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)

sys/dev/pci/auich.c

1031

qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV);

sys/dev/pci/auich.c

1060

bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI,

sys/dev/pci/auich.c

1062

bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL,

sys/dev/pci/auich.c

1069

auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)

sys/dev/pci/auich.c

1076

nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV);

sys/dev/pci/auich.c

1103

bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI,

sys/dev/pci/auich.c

770

auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)

sys/dev/pci/auich.c

775

bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0);

sys/dev/pci/auich.c

780

pipe + sc->sc_sts_reg);

sys/dev/pci/auich.c

783

pipe + sc->sc_sts_reg,

sys/dev/pci/auich.c

790

bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

144

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

147

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

149

lock_srbm(adev, mec, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

296

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

304

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

307

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

321

PACKET3_MAP_QUEUES_PIPE(pipe) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

44

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

48

nv_grbm_select(adev, mec, pipe, queue, vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

61

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

63

lock_srbm(adev, mec, pipe, queue_id, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

113

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

116

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

118

lock_srbm(adev, mec, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

195

uint32_t value, mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

198

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

201

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

204

((mec << 5) | (pipe << 3) | queue_id | 0x80));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

282

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

290

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

293

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

307

PACKET3_MAP_QUEUES_PIPE(pipe) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

44

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

48

nv_grbm_select(adev, mec, pipe, queue, vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

61

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

63

lock_srbm(adev, mec, pipe, queue_id, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

109

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

112

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

114

lock_srbm(adev, mec, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

180

uint32_t value, mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

183

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

186

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

189

((mec << 5) | (pipe << 3) | queue_id | 0x80));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

267

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

275

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

278

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

292

PACKET3_MAP_QUEUES_PIPE(pipe) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

42

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

46

soc21_grbm_select(adev, mec, pipe, queue, vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

59

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

61

lock_srbm(adev, mec, pipe, queue_id, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

30

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

34

soc24_grbm_select(adev, mec, pipe, queue, vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

47

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

49

lock_srbm(adev, mec, pipe, queue_id, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

60

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

63

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

65

lock_srbm(adev, mec, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

121

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

124

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

126

lock_srbm(adev, mec, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

48

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

51

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

67

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

69

lock_srbm(adev, mec, pipe, queue_id, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

116

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

119

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

121

lock_srbm(adev, mec, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

170

uint32_t value, mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

173

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

176

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

179

((mec << 5) | (pipe << 3) | queue_id | 0x80));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

42

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

45

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

61

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

63

lock_srbm(adev, mec, pipe, queue_id, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

164

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

167

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

169

kgd_gfx_v9_lock_srbm(adev, mec, pipe, 0, 0, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

307

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

315

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

318

mec, pipe, queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

332

PACKET3_MAP_QUEUES_PIPE(pipe) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

50

static void kgd_gfx_v9_lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

54

soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

67

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

69

kgd_gfx_v9_lock_srbm(adev, mec, pipe, queue_id, 0, inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

106

pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

142

amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

272

amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

356

rd->id.srbm.pipe = v1_data.srbm.pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

79

unsigned int instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

82

instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1552

unsigned int pipe, unsigned int flags, int *vpos,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1568

if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1610

vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1679

unsigned int pipe = crtc->index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1681

return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

174

int pipe = ring->pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

180

adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

184

bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

207

int i, j, queue, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

219

pipe = i % adev->gfx.mec.num_pipe_per_mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

223

set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

243

int i, queue, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

252

pipe = i % adev->gfx.me.num_pipe_per_me;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

256

set_bit(pipe * num_queue_per_pipe + queue,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

274

int mec, pipe, queue;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

284

amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

291

if ((mec == 1 && pipe > 1) || queue != 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

295

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

332

(unsigned char)ring->pipe, (unsigned char)ring->queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

48

int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

54

bit += pipe * adev->gfx.mec.num_queue_per_pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

61

int *mec, int *pipe, int *queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

610

int mec, pipe, queue;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

613

amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

615

set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

64

*pipe = (bit / adev->gfx.mec.num_queue_per_pipe)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

689

kiq_ring->pipe, kiq_ring->queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

72

int xcc_id, int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

74

return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

79

int me, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

86

bit += pipe * num_queue_per_pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

93

int me, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

95

return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

346

void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

551

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

591

int pipe, int queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

593

int *mec, int *pipe, int *queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

595

int mec, int pipe, int queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

601

int pipe, int queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

167

WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

169

RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

171

amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

176

tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

206

ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

253

tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1575

unsigned int pipe = crtc->index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1580

if (pipe >= adev->mode_info.num_crtc) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1581

DRM_ERROR("Invalid crtc %u\n", pipe);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1593

if (adev->mode_info.crtcs[pipe]) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1598

count = amdgpu_display_vblank_get_counter(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1604

dev, pipe, GET_DISTANCE_TO_VBLANKSTART,

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1606

&adev->mode_info.crtcs[pipe]->base.hwmode);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1607

} while (count != amdgpu_display_vblank_get_counter(adev, pipe));

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1614

pipe, vpos);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1625

count = amdgpu_display_vblank_get_counter(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1643

unsigned int pipe = crtc->index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1645

int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1660

unsigned int pipe = crtc->index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1662

int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

316

queue_input.pipe_id = ring->pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

341

queue_input.pipe_id = ring->pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

368

queue_input.pipe_id = ring->pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

607

int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

626

pipe == AMDGPU_MES_SCHED_PIPE ? "_2" : "1");

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

631

pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1");

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

634

r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], AMDGPU_UCODE_REQUIRED,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

636

if (r && need_retry && pipe == AMDGPU_MES_SCHED_PIPE) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

638

r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe],

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

647

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

648

adev->mes.uc_start_addr[pipe] =

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

651

adev->mes.data_start_addr[pipe] =

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

654

ucode_ptr = (u32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

656

adev->mes.fw_version[pipe] =

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

662

if (pipe == AMDGPU_MES_SCHED_PIPE) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

672

info->fw = adev->mes.fw[pipe];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

679

info->fw = adev->mes.fw[pipe];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

687

amdgpu_ucode_release(&adev->mes.fw[pipe]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

402

int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

683

unsigned int pipe, unsigned int flags, int *vpos,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

373

u32 pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umr.h

34

__u32 me, pipe, queue, vmid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umr.h

44

__u32 me, pipe, queue, vmid;

sys/dev/pci/drm/amd/amdgpu/cik.c

945

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/cik.c

948

(((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)|

sys/dev/pci/drm/amd/amdgpu/cik.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3753

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4548

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4550

nv_grbm_select(adev, me, pipe, q, vm);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4650

int me, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4659

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4670

snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4672

irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4680

int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4690

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4699

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4703

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5378

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5383

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5394

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5404

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6444

CP_PIPE_ID pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6449

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6732

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6738

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6854

nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6871

nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7148

nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7157

nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7179

nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8621

ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8624

ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8631

ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9053

uint32_t me, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9059

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9067

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9094

int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9106

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9120

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9218

(ring->pipe == pipe_id) &&

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9366

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9375

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9424

target += ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9539

if (ring->pipe == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9612

nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1041

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1043

soc21_grbm_select(adev, me, pipe, q, vm);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1125

int me, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1134

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1149

snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1151

irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1159

int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1170

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1179

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1183

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1464

int pipe, ucode_id, data_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1466

for (pipe = 0; pipe < 2; pipe++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1467

if (pipe==0) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1476

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1478

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1485

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2165

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2170

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2181

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2191

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3678

CP_PIPE_ID pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3683

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

397

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4049

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4192

soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4493

soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4502

soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4524

soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5839

ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5842

ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5849

ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6310

uint32_t me, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6316

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6324

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6355

int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6367

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6381

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6483

(ring->pipe == pipe_id) &&

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6633

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6642

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6701

target += ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6777

soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6779

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6869

soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6876

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6910

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6940

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1004

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1013

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1017

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1276

int pipe, ucode_id, data_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1278

for (pipe = 0; pipe < 2; pipe++) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1279

if (pipe == 0) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1288

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1290

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1296

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1836

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1841

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1850

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1860

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2674

CP_PIPE_ID pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2679

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2944

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3070

soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

336

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3371

soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3380

soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3402

soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4394

ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4397

ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4695

uint32_t me, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4701

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4706

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4737

int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4749

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4757

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4859

(ring->pipe == pipe_id) &&

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5009

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5018

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5250

soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5252

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5341

soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5347

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5380

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

897

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

899

soc24_grbm_select(adev, me, pipe, q, vm);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

962

int me, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

971

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

982

snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

984

irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

993

int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3003

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3094

ring->pipe = i;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3096

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3097

irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2076

ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2079

ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2770

int mec, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2774

size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2780

cik_srbm_select(adev, mec + 1, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2984

cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4072

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4074

cik_srbm_select(adev, me, pipe, q, vm);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4278

int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4286

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4292

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4296

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4608

int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4620

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4634

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4766

if ((ring->me == me_id) && (ring->pipe == pipe_id))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4791

if ((ring->me == me_id) && (ring->pipe == pipe_id))

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1847

int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1858

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1866

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1870

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3412

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3414

vi_srbm_select(adev, me, pipe, q, vm);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4300

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4352

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4599

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4610

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4634

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4981

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5076

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6007

ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6010

ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6367

int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6379

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6393

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6573

if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6600

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6767

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6774

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6788

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6816

if (i != ring->pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1995

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1997

soc15_grbm_select(adev, me, pipe, q, vm, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2153

int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2163

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2172

snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2176

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3528

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3854

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3865

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3896

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4080

adev->gfx.kiq[0].ring.pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5387

ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5390

ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5950

int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5962

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5976

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6003

int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6013

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6118

#define ENABLE_ECC_ON_ME_PIPE(me, pipe) \

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6119

WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6122

#define DISABLE_ECC_ON_ME_PIPE(me, pipe) \

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6123

WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6228

if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6255

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7103

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7112

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7126

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7155

if (i != ring->pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7211

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

964

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1001

+ ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1808

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

213

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2133

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2144

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2175

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2205

ring->pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2338

adev->gfx.kiq[xcc_id].ring.pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2829

ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2832

ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3066

struct amdgpu_device *adev, int me, int pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3078

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3092

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3119

int xcc_id, int me, int pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3129

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3326

if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3358

if (ring->me == me_id && ring->pipe == pipe_id &&

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3413

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3422

switch (pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3436

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3464

if (i != ring->pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3471

uint32_t pipe, uint32_t queue,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3478

soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3522

switch (ring->pipe) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3543

if (ring->pipe)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3556

r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3596

r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

782

u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

784

soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

971

int xcc_id, int mec, int pipe, int queue)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

984

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

997

ring->xcc_id, ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

103

static inline int jpeg_v4_0_3_core_reg_offset(u32 pipe)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

105

if (pipe)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

106

return ((0x40 * pipe) - 0xc80);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1123

int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1134

WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1214

adev->jpeg.inst[i].ring_dec[j].pipe = j;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

414

(ring->pipe ? (ring->pipe - 0x15) : 0),

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

576

int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

580

JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

581

~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

681

jpeg_v4_0_3_core_reg_offset(ring->pipe));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

699

jpeg_v4_0_3_core_reg_offset(ring->pipe));

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

725

jpeg_v4_0_3_core_reg_offset(ring->pipe),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

101

if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

102

return ((0x40 * pipe) - 0xc80);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

104

return ((0x40 * pipe) - 0x440);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

286

ring->pipe,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

406

int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

410

if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

411

data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

412

mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

415

data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

416

mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

614

ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

632

ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

652

(ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0),

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

822

int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

833

WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

915

adev->jpeg.inst[i].ring_dec[j].pipe = j;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

99

static int jpeg_v5_0_1_core_reg_offset(u32 pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1008

enum amdgpu_mes_pipe pipe, bool prime_icache)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1016

if (!adev->mes.fw[pipe])

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1019

r = mes_v11_0_allocate_ucode_buffer(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1023

r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1025

mes_v11_0_free_ucode_buffers(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1031

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1036

ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1044

lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1046

upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1053

lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1055

upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1080

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1087

&adev->mes.eop_gpu_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1088

&adev->mes.eop_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1096

adev->mes.eop_gpu_obj[pipe]->tbo.base.size);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1098

amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1099

amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1215

soc21_grbm_select(adev, 3, ring->pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1291

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1296

if (pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1298

else if (pipe == AMDGPU_MES_SCHED_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1303

if ((pipe == AMDGPU_MES_SCHED_PIPE) &&

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1314

if (pipe == AMDGPU_MES_SCHED_PIPE) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1334

ring->pipe = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1342

snprintf(ring->name, sizeof(ring->name), "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1357

ring->pipe = 1;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1367

ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1374

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1379

if (pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1381

else if (pipe == AMDGPU_MES_SCHED_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1401

adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1402

if (!adev->mes.mqd_backup[pipe]) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1415

int pipe, r, bo_size;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1427

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1428

if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1431

r = mes_v11_0_allocate_eop_buf(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1435

r = mes_v11_0_mqd_sw_init(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1473

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1478

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1479

kfree(adev->mes.mqd_backup[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1481

amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1482

&adev->mes.eop_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1484

amdgpu_ucode_release(&adev->mes.fw[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1514

soc21_grbm_select(adev, 3, ring->pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1550

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1717

int pipe, r;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1722

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1723

if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1725

r = amdgpu_mes_init_microcode(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

830

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

838

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

840

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

848

&adev->mes.ucode_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

849

&adev->mes.ucode_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

850

(void **)&adev->mes.ucode_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

856

memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

858

amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

859

amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

865

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

873

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

875

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

881

pipe, fw_size, GFX_MES_DRAM_SIZE);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

889

&adev->mes.data_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

890

&adev->mes.data_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

891

(void **)&adev->mes.data_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

897

memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

899

amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

900

amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

906

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

908

amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

909

&adev->mes.data_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

910

(void **)&adev->mes.data_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

912

amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

913

&adev->mes.ucode_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

914

(void **)&adev->mes.ucode_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

919

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

928

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

929

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

931

if (pipe == AMDGPU_MES_SCHED_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

934

else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

946

uint32_t pipe, data = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

966

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

968

pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

971

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

973

ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1004

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1012

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1014

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1021

&adev->mes.ucode_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1022

&adev->mes.ucode_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1023

(void **)&adev->mes.ucode_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1029

memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1031

amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1032

amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1038

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1046

adev->mes.fw[pipe]->data;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1048

fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1055

&adev->mes.data_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1056

&adev->mes.data_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1057

(void **)&adev->mes.data_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1063

memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1065

amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1066

amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1072

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1074

amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1075

&adev->mes.data_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1076

(void **)&adev->mes.data_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1078

amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1079

&adev->mes.ucode_fw_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1080

(void **)&adev->mes.ucode_fw_ptr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1086

uint32_t pipe, data = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1090

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1091

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1095

if (adev->mes.event_log_size >= (pipe + 1) * log_size) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1098

pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1101

pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1109

if (pipe == 0)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1115

ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1123

if (pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1155

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1160

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1162

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1165

ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1178

enum amdgpu_mes_pipe pipe, bool prime_icache)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1185

if (!adev->mes.fw[pipe])

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1188

r = mes_v12_0_allocate_ucode_buffer(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1192

r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1194

mes_v12_0_free_ucode_buffers(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1200

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1206

lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1208

upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1215

lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1217

upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1242

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1249

&adev->mes.eop_gpu_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1250

&adev->mes.eop_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1258

adev->mes.eop_gpu_obj[pipe]->tbo.base.size);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1260

amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1261

amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1382

soc21_grbm_select(adev, 3, ring->pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1463

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1468

if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1471

ring = &adev->mes.ring[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1473

if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1484

if (pipe == AMDGPU_MES_SCHED_PIPE) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1495

if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) ||

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1496

((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1499

soc21_grbm_select(adev, 3, pipe, 0, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

150

int pipe, void *pkt, int size,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1501

if (pipe == AMDGPU_MES_SCHED_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1503

else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1513

static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1517

ring = &adev->mes.ring[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1522

ring->pipe = pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1527

ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1529

snprintf(ring->name, sizeof(ring->name), "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1531

if (pipe == AMDGPU_MES_SCHED_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1549

ring->pipe = 1;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1559

ring->me, ring->pipe, ring->queue);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

156

struct amdgpu_ring *ring = &mes->ring[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1566

enum amdgpu_mes_pipe pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

157

spinlock_t *ring_lock = &mes->ring_lock[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1571

if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1574

ring = &adev->mes.ring[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1590

adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1591

if (!adev->mes.mqd_backup[pipe])

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1602

int pipe, r;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1616

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1617

r = mes_v12_0_allocate_eop_buf(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1621

r = mes_v12_0_mqd_sw_init(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1625

if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1629

r = mes_v12_0_ring_init(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1634

&adev->mes.resource_1[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1635

&adev->mes.resource_1_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1636

&adev->mes.resource_1_addr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1638

dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1650

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1652

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1653

amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1654

&adev->mes.resource_1_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1655

&adev->mes.resource_1_addr[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1657

kfree(adev->mes.mqd_backup[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1659

amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1660

&adev->mes.eop_gpu_addr[pipe],

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1662

amdgpu_ucode_release(&adev->mes.fw[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1664

if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1665

amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1666

&adev->mes.ring[pipe].mqd_gpu_addr,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1667

&adev->mes.ring[pipe].mqd_ptr);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1668

amdgpu_ring_fini(&adev->mes.ring[pipe]);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1732

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1904

int pipe, r;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1909

for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1910

r = amdgpu_mes_init_microcode(adev, pipe);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

223

pipe, op_str, misc_op_str);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

226

pipe, op_str);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

229

pipe, x_pkt->header.opcode);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

241

pipe, op_str, misc_op_str);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

244

pipe, op_str);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

247

pipe, x_pkt->header.opcode);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

510

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

528

pipe = AMDGPU_MES_KIQ_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

530

pipe = AMDGPU_MES_SCHED_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

532

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

541

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

567

pipe = AMDGPU_MES_KIQ_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

569

pipe = AMDGPU_MES_SCHED_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

571

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

616

static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

626

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

635

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

638

pipe = AMDGPU_MES_KIQ_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

640

pipe = AMDGPU_MES_SCHED_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

676

pipe = AMDGPU_MES_SCHED_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

702

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

707

static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

718

mes->resource_1_gpu_addr[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

720

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

725

static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

730

uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ?

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

740

if (pipe == AMDGPU_MES_SCHED_PIPE) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

764

mes->sch_ctx_gpu_addr[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

766

mes->query_status_fence_gpu_addr[pipe];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

793

pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

799

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

883

int pipe;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

913

pipe = AMDGPU_MES_KIQ_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

915

pipe = AMDGPU_MES_SCHED_PIPE;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

917

return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,

sys/dev/pci/drm/amd/amdgpu/nv.c

318

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/nv.c

321

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/nv.h

32

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/si.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/soc15.c

364

u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/soc15.c

367

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/soc15.h

110

u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);

sys/dev/pci/drm/amd/amdgpu/soc21.c

239

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/soc21.c

242

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/soc21.h

29

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/soc24.c

102

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/soc24.c

105

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/soc24.h

29

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdgpu/vi.c

579

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/amd/amdgpu/vi.c

582

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/pci/drm/amd/amdgpu/vi.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1043

q->pipe, q->queue,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1175

KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1313

retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1501

int pipe, queue;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1516

for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1517

int pipe_offset = pipe * get_queues_per_pipe(dqm);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1522

dqm->allocated_queues[pipe] |= 1 << queue;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2154

uint32_t mec, pipe, queue;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2163

amdgpu_queue_mask_bit_to_mec_queue(dqm->dev->adev, i, &mec, &pipe, &queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2167

dqm->dev->adev, pipe, queue, xcc_id);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2173

hang_info.pipe_id = pipe;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3665

int pipe, queue;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3692

for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3693

int pipe_offset = pipe * get_queues_per_pipe(dqm);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3701

pipe, queue,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3709

xcc_id, pipe, queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3718

for (pipe = sdma_engine_start;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3719

pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3720

pipe++) {

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3725

dqm->dev->adev, pipe, queue, &dump, &n_regs);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3730

pipe, queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

661

q->pipe, q->queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

702

retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

744

int pipe, bit, i;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

748

for (pipe = dqm->next_pipe_to_allocate, i = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

750

pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

752

if (!is_pipe_enabled(dqm, 0, pipe))

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

755

if (dqm->allocated_queues[pipe] != 0) {

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

756

bit = ffs(dqm->allocated_queues[pipe]) - 1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

757

dqm->allocated_queues[pipe] &= ~(1 << bit);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

758

q->pipe = pipe;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

768

pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

770

dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

778

dqm->allocated_queues[q->pipe] |= (1 << q->queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

83

static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

87

+ pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

885

q->pipe, q->queue);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

996

KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

157

kq->queue->pipe = KFD_CIK_HIQ_PIPE;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

160

kq->queue->pipe, kq->queue->queue,

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

205

kq->queue->pipe,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

612

uint32_t pipe;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10400

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10426

pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10481

wb_info->writeback_source_plane = pipe->plane_state;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1114

int pipe, bool *enabled,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

512

e->pipe = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2786

const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2803

if (!pipe[i].stream || !pipe[i].bottom_pipe)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2806

ASSERT(pipe[i].plane_state);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2809

if (!pipe[i].plane_state->visible)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2814

if (!pipe[i].plane_state->visible)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2822

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2823

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2824

data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2825

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2827

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2828

data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2829

data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2830

data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2831

data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2832

switch (pipe[i].plane_state->rotation) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2848

switch (pipe[i].plane_state->format) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2880

data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2881

data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2883

pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2884

data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2885

data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2887

pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2889

pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2890

switch (pipe[i].bottom_pipe->plane_state->rotation) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2915

if (!pipe[i].stream || pipe[i].bottom_pipe)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2921

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2922

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2923

pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2924

if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2927

if (pipe[i].plane_state) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2928

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2930

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2931

data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2932

data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2933

data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2934

data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2935

switch (pipe[i].plane_state->rotation) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2951

switch (pipe[i].plane_state->format) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2976

} else if (pipe[i].stream->dst.width != 0 &&

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2977

pipe[i].stream->dst.height != 0 &&

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2978

pipe[i].stream->src.width != 0 &&

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2979

pipe[i].stream->src.height != 0) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2980

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2982

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2983

data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2984

data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2985

data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2986

data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2990

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2992

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3009

static bool all_displays_in_sync(const struct pipe_ctx pipe[],

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3016

if (!resource_is_pipe_type(&pipe[i], OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3019

active_pipes[num_active_pipes++] = &pipe[i];

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3044

const struct pipe_ctx pipe[],

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3053

populate_initial_data(pipe, pipe_count, data);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3056

calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

120

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

122

if (pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

124

if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

126

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

129

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

218

struct pipe_ctx *pipe = safe_to_lower

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

222

if (pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

224

if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

226

if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

227

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

231

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

106

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

108

if (pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

110

if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

111

dc_is_virtual_signal(pipe->stream->signal))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

114

if (should_disable_otg(pipe)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

116

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

119

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

90

static bool should_disable_otg(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

94

if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

95

pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

109

struct pipe_ctx *pipe = safe_to_lower

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

113

if (pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

115

if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

116

!pipe->stream->link_enc)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

118

if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

119

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

123

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

490

static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

493

int width = pipe->plane_state->src_rect.width;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

494

int height = pipe->plane_state->src_rect.height;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

496

if (pipe->stream->timing.h_addressable == width &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

497

pipe->stream->timing.v_addressable == height &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

498

pipe->plane_state->dst_rect.width == width &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

499

pipe->plane_state->dst_rect.height == height)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

203

struct pipe_ctx *pipe = safe_to_lower

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

207

struct link_encoder *pipe_link_enc = pipe->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

211

if (pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

217

if (pipe->stream)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

218

pipe_link_enc = pipe->stream->link_enc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

238

if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

239

(pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

240

!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

243

if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

244

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

248

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

395

static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

398

int width = pipe->plane_state->src_rect.width;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

399

int height = pipe->plane_state->src_rect.height;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

401

if (pipe->stream->timing.h_addressable == width &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

402

pipe->stream->timing.v_addressable == height &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

403

pipe->plane_state->dst_rect.width == width &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

404

pipe->plane_state->dst_rect.height == height)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1302

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1304

if (pipe->plane_state == plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1305

memcpy(color, &pipe->visual_confirm_color, sizeof(struct tg_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1317

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1360

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1361

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1371

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1382

if (pipe->stream && pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1384

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1385

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1430

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1432

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1433

stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1441

if (pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1469

pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1472

dc->link_srv->set_dpms_off(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1473

pipe->stream->dpms_off = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2009

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2015

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2018

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2021

for (j = 0; pipe && j < stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2022

if (should_update_pipe_for_stream(context, pipe, streams[j]) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2024

dc->hwss.setup_stereo(pipe, dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2075

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2083

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2084

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2086

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2088

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2092

if (resource_calculate_det_for_stream(context, pipe) <

sys/dev/pci/drm/amd/display/dc/core/dc.c

2114

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2142

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2144

if (resource_is_pipe_type(pipe, OTG_MASTER)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2146

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2187

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2188

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2219

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2220

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2256

pipe = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2258

for (l = 0 ; pipe && l < context->stream_count; l++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2260

context->streams[l] == pipe->stream &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2262

dc->hwss.setup_stereo(pipe, dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2345

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2393

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2394

if (pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2504

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2507

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2510

if (!pipe->plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))

sys/dev/pci/drm/amd/display/dc/core/dc.c

2514

pipe->plane_state->status.is_flip_pending = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2515

dc->hwss.update_pending_status(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2516

if (pipe->plane_state->status.is_flip_pending)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3990

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3992

if (pipe->stream && pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3994

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3997

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4091

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4093

if (pipe->stream && pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4095

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4098

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4132

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4134

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

425

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

427

if (pipe->stream == stream && pipe->stream_res.tg) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

429

dc->hwss.set_long_vtotal(&pipe, 1, adjust->v_total_min, adjust->v_total_max);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4566

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4568

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

489

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4899

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4901

if (pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4909

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

491

if (pipe->stream == stream && pipe->stream_res.tg) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4911

if (pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

492

dc->hwss.set_drr(&pipe,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4921

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4923

if (resource_is_pipe_type(pipe, OTG_MASTER)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4924

odm_in_use = resource_get_odm_slice_count(pipe) > 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

526

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

528

if (pipe->stream == stream && pipe->stream_res.tg) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

532

if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

533

pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5586

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5623

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5624

subvp_pipe_type[i] = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5681

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5685

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5687

if (pipe->stream != NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5688

dc->hwss.disable_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5691

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5692

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5693

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5695

hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5705

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5707

if (pipe->stream != NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5708

dc->hwss.disable_pixel_data(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5710

hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

587

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

592

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

593

if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc.c

602

mux_mapping.otg_output_num = pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6129

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6142

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6144

if (pipe->stream == stream && pipe->stream_res.tg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6165

if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6166

pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6184

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6193

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6195

if (pipe->stream == stream && pipe->stream_res.tg)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6214

if (pipe->stream_res.abm &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

6215

pipe->stream_res.abm->funcs->save_restore)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6216

return pipe->stream_res.abm->funcs->save_restore(

sys/dev/pci/drm/amd/display/dc/core/dc.c

6217

pipe->stream_res.abm,

sys/dev/pci/drm/amd/display/dc/core/dc.c

653

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

658

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

659

if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc.c

668

mux_mapping.otg_output_num = pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

702

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

706

pipe = resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/core/dc.c

710

if (pipe == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc.c

718

param.windowa_x_end = pipe->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

719

param.windowa_y_end = pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

722

param.windowb_x_end = pipe->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

723

param.windowb_y_end = pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

736

param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

737

param.odm_mode = pipe->next_odm_pipe ? 1:0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

747

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/core/dc.c

775

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

781

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

782

if (pipe->stream == stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

789

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1193

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1195

if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1201

pipe->plane_state->status.is_flip_pending = false;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1202

dc->hwss.update_pending_status(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1203

if (!pipe->plane_state->status.is_flip_pending)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1208

ASSERT(!pipe->plane_state->status.is_flip_pending);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

662

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

664

if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

665

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

670

if (pipe_ctx->stream == pipe->stream)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1995

struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2002

while (pipe && resource_is_pipe_type(pipe, DPP_PIPE)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2004

dpp_pipes[i++] = pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2005

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2015

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2018

pipe = &res_ctx->pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2019

if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2020

if (resource_is_pipe_type(pipe, OPP_HEAD) ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2021

pipe->top_pipe->plane_state != plane)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2027

if (pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2028

while (pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2029

dpp_pipes[i++] = pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2030

pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2033

while (pipe && pipe->plane_state == plane) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2034

dpp_pipes[i++] = pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2035

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2087

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2090

const struct pipe_ctx *other_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2092

while (other_pipe && other_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2096

other_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2097

while (other_pipe && other_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2105

int resource_get_odm_slice_count(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2109

pipe = resource_get_otg_master(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2111

while (pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2113

pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2304

static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2315

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2316

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2317

pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2323

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2324

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2325

pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2331

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2332

pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2337

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2338

pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2343

pipe->plane_res.dpp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2348

pipe->plane_res.dpp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2487

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2491

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2492

if (pipe->stream == otg_master->stream && pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2493

result = resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2510

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2514

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2515

if (pipe->plane_state == plane)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2516

result = resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

660

const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

669

(dc_is_dp_signal(pipe->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

671

pipe->stream)))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

675

&& dc_is_dual_link_signal(pipe->stream->signal))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

678

if (dc_is_hdmi_signal(pipe->stream->signal)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

683

pipe_with_clk_src->stream, pipe->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

925

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

927

if (pipe->plane_state && pipe->stream && dc_state_get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

928

phantom_stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

740

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

747

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

748

if (pipe->stream == stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

757

return dc->hwss.dmdata_status_done(pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

819

struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

821

if (pipe->stream == stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

822

return pipe;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

412

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

414

if (pipe->stream == stream && pipe->stream_res.tg)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

461

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

463

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

470

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

480

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

482

if (!resource_is_pipe_type(pipe, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

485

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

487

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

488

uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

490

config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

493

config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

494

dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

661

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

667

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

671

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

672

!resource_is_pipe_type(pipe, DPP_PIPE))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

676

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

693

populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

890

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

894

if (resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

895

resource_is_pipe_type(pipe, DPP_PIPE) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

896

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

897

subvp_pipes[subvp_count++] = pipe;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

903

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

904

pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

906

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

913

if (resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

914

resource_is_pipe_type(pipe, DPP_PIPE) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

916

populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

917

} else if (resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

918

resource_is_pipe_type(pipe, DPP_PIPE) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

922

populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1004

pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1008

pipe->plane_state->format);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1010

pipe->plane_state->tiling_info.gfx9.swizzle);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1011

v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1012

v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1013

v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1014

v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1015

v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1025

v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1030

v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1032

v->output[input_idx] = pipe->stream->signal ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1036

switch (pipe->stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1200

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1203

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1206

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1209

pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1210

pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1211

pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1212

pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1214

pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1215

pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1216

vesa_sync_start = pipe->stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1217

pipe->stream->timing.v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1218

pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1220

asic_blank_end = (pipe->stream->timing.v_total -

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1222

pipe->stream->timing.v_border_top)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1223

* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1226

(pipe->stream->timing.v_border_top +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1227

pipe->stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1228

pipe->stream->timing.v_border_bottom)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1229

* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1231

pipe->pipe_dlg_param.vblank_start = asic_blank_start;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1232

pipe->pipe_dlg_param.vblank_end = asic_blank_end;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1234

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1235

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1237

pipe->plane_state->update_flags.bits.full_update = 1;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1240

((pipe->stream->view_format ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1242

pipe->stream->view_format ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1244

(pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1246

pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1248

if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1255

hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1256

hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1257

hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1258

hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1261

hsplit_pipe = resource_find_free_secondary_pipe_legacy(&context->res_ctx, pool, pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1263

split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1267

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1269

pipe->bottom_pipe = hsplit_pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1271

hsplit_pipe->bottom_pipe->top_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1279

resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1282

dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

302

const struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

308

if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

309

pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

311

input->src.hsplit_grp = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

312

} else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

314

} else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

318

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

323

input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

334

dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

337

input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

339

input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

341

input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

342

input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

343

input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

344

input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

348

input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

350

switch (pipe->plane_state->rotation) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

365

switch (pipe->plane_state->format) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

398

input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

399

input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

400

input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

401

input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

404

input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

405

input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

406

input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

407

input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

408

input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

409

input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

412

switch (pipe->plane_res.scl_data.lb_params.depth) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

422

input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

423

+ pipe->stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

425

input->dest.recout_width = pipe->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

426

input->dest.recout_height = pipe->plane_res.scl_data.recout.height;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

428

input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

429

input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

431

input->dest.htotal = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

432

input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

434

- pipe->stream->timing.h_addressable

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

435

- pipe->stream->timing.h_border_left

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

436

- pipe->stream->timing.h_border_right;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

438

input->dest.vtotal = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

439

input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

441

- pipe->stream->timing.v_addressable

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

442

- pipe->stream->timing.v_border_bottom

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

443

- pipe->stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

444

input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

445

input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

446

input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

447

input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

448

input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

455

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

459

struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

460

struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

461

struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

462

struct _vcs_dpi_display_rq_params_st *rq_param = &pipe->dml_rq_param;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

463

struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

464

struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

493

pipe_ctx_to_e2e_pipe_params(pipe, &input->pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

507

dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

519

pipe->plane_state->flip_immediate);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

710

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

717

if (pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

718

(pipe->plane_state->dst_rect.width <= 16 ||

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

719

pipe->plane_state->dst_rect.height <= 16 ||

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

720

pipe->plane_state->src_rect.width <= 16 ||

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

721

pipe->plane_state->src_rect.height <= 16)) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

894

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

896

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

899

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

905

v->htotal[input_idx] = pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

906

v->vtotal[input_idx] = pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

907

v->vactive[input_idx] = pipe->stream->timing.v_addressable +

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

908

pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

909

v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

911

- pipe->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

912

v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

913

if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

915

if (!pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

920

v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

921

v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

942

v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

943

v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

944

v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

945

v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

946

if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

947

if (pipe->plane_state->rotation % 2 == 0) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

948

int viewport_end = pipe->plane_res.scl_data.viewport.width

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

949

+ pipe->plane_res.scl_data.viewport.x;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

950

int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

951

+ pipe->bottom_pipe->plane_res.scl_data.viewport.x;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

955

- pipe->bottom_pipe->plane_res.scl_data.viewport.x;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

958

- pipe->plane_res.scl_data.viewport.x;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

960

int viewport_end = pipe->plane_res.scl_data.viewport.height

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

961

+ pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

962

int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

963

+ pipe->bottom_pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

967

- pipe->bottom_pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

970

- pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

972

v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

973

+ pipe->bottom_pipe->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

976

if (pipe->plane_state->rotation % 2 == 0) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

977

ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

979

ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

982

ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

984

ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

993

v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1184

pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1185

pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1186

pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1187

pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1195

context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1202

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1246

&pipes[pipe_idx].pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1369

pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1375

pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1377

pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1381

pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1384

pipes[pipe_cnt].pipe.src.dcc = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1385

pipes[pipe_cnt].pipe.src.dcc_rate = 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1386

pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1387

pipes[pipe_cnt].pipe.dest.synchronize_timings = synchronized_vblank;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1388

pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1389

pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1393

pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1394

pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1398

pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1399

pipes[pipe_cnt].pipe.dest.vtotal = v_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1400

pipes[pipe_cnt].pipe.dest.hactive =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1402

pipes[pipe_cnt].pipe.dest.vactive =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1404

pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1405

pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1407

pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1408

pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1412

pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1413

pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1416

pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1419

pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1422

pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1424

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1437

pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1439

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1441

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1447

pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1540

pipes[pipe_cnt].pipe.src.num_cursors = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1542

pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1544

pipes[pipe_cnt].pipe.src.cur0_src_width = 256;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1545

pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1548

pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1549

pipes[pipe_cnt].pipe.src.source_scan = dm_horz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1550

pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1551

pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1552

pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1553

pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1554

if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1555

pipes[pipe_cnt].pipe.src.viewport_width = 1920;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1556

pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1557

if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1558

pipes[pipe_cnt].pipe.src.viewport_height = 1080;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1559

pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1560

pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1561

pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1562

pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1563

pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1564

pipes[pipe_cnt].pipe.src.source_format = dm_444_32;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1565

pipes[pipe_cnt].pipe.src.cur0_src_width = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1566

pipes[pipe_cnt].pipe.src.cur1_src_width = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1567

pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1568

pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1569

pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1570

pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1571

pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1572

pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1573

pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1574

pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1575

pipes[pipe_cnt].pipe.scale_taps.htaps = 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1576

pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1577

pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1578

pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1580

if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1581

pipes[pipe_cnt].pipe.src.viewport_width /= 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1582

pipes[pipe_cnt].pipe.dest.recout_width /= 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1583

} else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1584

pipes[pipe_cnt].pipe.src.viewport_width /= 4;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1585

pipes[pipe_cnt].pipe.dest.recout_width /= 4;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1591

pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1592

pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1594

|| pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1599

pipes[pipe_cnt].pipe.src.is_hsplit = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1600

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1603

pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1607

pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1610

pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1613

pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1616

pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1622

pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1623

pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1624

pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1625

pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1626

pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1627

pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1628

pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1629

pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1630

pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1631

pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1632

pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1633

pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1634

pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1635

pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1638

pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1639

pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1640

pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1641

pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1643

pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1644

pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1646

pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1647

pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1648

pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1649

pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1650

pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1651

if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1652

pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1653

else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1654

pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1659

pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1664

pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1669

pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1670

pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1671

pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1672

pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1673

pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1674

pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1680

pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1681

pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1682

pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1683

pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1685

pipes[pipe_cnt].pipe.src.macro_tile_size =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1688

&pipes[pipe_cnt].pipe.src.sw_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1693

pipes[pipe_cnt].pipe.src.source_format = dm_420_8;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1697

pipes[pipe_cnt].pipe.src.source_format = dm_420_10;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1703

pipes[pipe_cnt].pipe.src.source_format = dm_444_64;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1707

pipes[pipe_cnt].pipe.src.source_format = dm_444_16;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1710

pipes[pipe_cnt].pipe.src.source_format = dm_444_8;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1713

pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1716

pipes[pipe_cnt].pipe.src.source_format = dm_444_32;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1752

pipes[pipe_cnt].pipe.dest.odm_combine =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1755

pipes[pipe_cnt].pipe.dest.odm_combine = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1761

pipes[pipe_cnt].pipe.dest.odm_combine =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1764

pipes[pipe_cnt].pipe.dest.odm_combine = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2168

pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2169

pipes[i].pipe.src.gpuvm = 1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2262

pipes[pipe_cnt].pipe.dest.odm_combine =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2265

pipes[pipe_cnt].pipe.dest.odm_combine = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2271

pipes[pipe_cnt].pipe.dest.odm_combine =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2274

pipes[pipe_cnt].pipe.dest.odm_combine = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2538

pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2546

pipes[pipe_cnt].pipe.dest.htotal,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1565

dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

787

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

788

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

791

const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

792

const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1566

dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

787

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

788

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

791

const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

792

const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1677

dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

833

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

834

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

837

const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

838

const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

250

pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

257

pipes[pipe_cnt].pipe.dest.htotal,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1192

if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1194

unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1198

if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1199

&& e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1764

dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

901

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

902

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

905

const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

906

const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

450

pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

451

pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1065

if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1067

unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1071

if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1574

dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

862

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

863

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

865

const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

866

const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

313

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

328

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

329

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

333

if (pipe->stream->adjust.v_total_min != 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

334

pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

336

pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

340

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

341

pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

346

pipes[pipe_cnt].pipe.dest.vblank_nom =

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

347

max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

348

pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

350

if (pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

351

(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

352

pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

357

pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

364

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

366

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

367

pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

368

pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

369

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

370

pipes[pipe_cnt].pipe.src.dcc_rate = 3;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

395

if (pipe_cnt == 1 && pipe->plane_state

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

396

&& pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

397

if (is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

398

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

400

} else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

403

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

416

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

418

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

421

if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

422

pipe->stream->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

424

if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1152

if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1154

unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1158

if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1662

dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

947

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

948

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

950

const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

951

const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1000

if (pipe->plane_state && !pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1001

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1002

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1003

pipe->stream->timing.v_total * (uint64_t)pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1004

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1005

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1049

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1050

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1052

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1055

if (pipe->plane_state && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1225

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1232

pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1233

if (resource_is_pipe_type(pipe, FREE_PIPE))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1237

if (resource_is_pipe_type(pipe, OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1241

update_slice_table_for_stream(table, pipe->stream, -1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1242

else if (resource_is_pipe_type(pipe, DPP_PIPE) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1243

resource_get_odm_slice_index(resource_get_opp_head(pipe)) == 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1247

update_slice_table_for_plane(table, pipe, pipe->plane_state, -1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1254

if (odm && resource_is_pipe_type(pipe, OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1256

table, pipe->stream, split[dc_pipe_idx] - 1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1257

else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1258

update_slice_table_for_plane(table, pipe,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1259

pipe->plane_state, split[dc_pipe_idx] - 1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1407

cur_policy[i] = pipes[i].pipe.dest.odm_combine_policy;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1408

pipes[i].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1420

pipes[i].pipe.dest.odm_combine_policy = cur_policy[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1705

pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1707

pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1709

pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1711

pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1730

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1814

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1818

pipe = &context->res_ctx.pipe_ctx[old_index];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1819

pipe->pipe_idx = old_index;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1822

if (!pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1827

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1828

pipe->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1839

if (!pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1842

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1843

pipe->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1848

return pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1959

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1966

if (pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1968

pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1969

if (pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1970

pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1973

if (pipe->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1974

if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1976

pipe->bottom_pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1981

if (pipe->prev_odm_pipe->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1983

pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1984

pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1987

pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1988

pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1991

memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1995

if (pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1996

pipe->top_pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1999

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2000

pipe->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2001

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2002

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2003

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2004

pipe->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2005

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2006

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2007

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2008

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2009

memset(&pipe->link_res, 0, sizeof(pipe->link_res));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2011

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2012

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2013

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2019

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2020

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2021

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2022

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2023

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2024

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2025

memset(&pipe->link_res, 0, sizeof(pipe->link_res));

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2033

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2039

if (!pipe->stream || newly_split[i])

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2045

if (!pipe->plane_state && !odm)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2069

pipe, hsplit_pipe, odm))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2091

pipe, pipe_4to1, odm))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2115

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2119

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2121

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2122

if (!resource_build_scaling_params(pipe))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2220

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2221

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2223

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2228

&& pipe->plane_state && mpo_pipe

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2230

&pipe->stream->src,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2232

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3387

pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3388

pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3391

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3403

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3404

(uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3405

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3406

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3409

dcn32_check_native_scaling_for_res(pipe, width, height)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

343

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3433

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

345

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3459

if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3460

pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3461

refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3462

pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3463

/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3469

if (dcn32_check_native_scaling_for_res(pipe, width, height)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3470

if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

348

if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

349

pipes[pipe_idx].pipe.dest.vstartup_start =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

351

pipes[pipe_idx].pipe.dest.vupdate_offset =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3529

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

353

pipes[pipe_idx].pipe.dest.vupdate_width =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3539

if (!pipe->stream || !pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3543

*fpo_candidate_stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

355

pipes[pipe_idx].pipe.dest.vready_offset =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3568

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

357

pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3570

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3574

if (fpo_candidate_stream && pipe->stream == fpo_candidate_stream) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3582

blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3583

(double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3585

pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed || blank_us >= dc->debug.fpo_vactive_max_blank_us) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

475

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

488

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

490

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

565

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

567

if (pipe->stream && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

568

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

570

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

614

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

618

refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

619

pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

620

/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

628

if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && !dcn32_is_center_timing(pipe) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

629

!pipe->stream->hw_cursor_req &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

630

!dc_state_get_stream_cursor_subvp_limit(pipe->stream, context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

631

!(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

632

(!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

633

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

634

(refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

635

!pipe->plane_state->address.tmz_surface &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

638

dcn32_allow_subvp_with_active_margin(pipe)))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

639

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

641

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

644

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

646

struct dc_stream_state *stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

687

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

690

if (resource_is_pipe_type(pipe, OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

691

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

693

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

695

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

737

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

743

phantom = dc_state_get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

744

if (phantom && pipe->stream && pipe->plane_state && !pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

745

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

757

subvp_pipes[index] = pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

801

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

819

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

823

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

824

!resource_is_pipe_type(pipe, DPP_PIPE))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

828

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

850

phantom_stream = dc_state_get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

852

main_timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

900

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

925

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

926

pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

930

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

931

!resource_is_pipe_type(pipe, DPP_PIPE))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

941

subvp_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

995

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

997

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

212

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

213

const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

312

if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

314

unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

318

if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

319

&& e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

49

const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

444

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

461

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

462

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

467

if (pipe->stream->adjust.v_total_max ==

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

468

pipe->stream->adjust.v_total_min &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

469

pipe->stream->adjust.v_total_min > timing->v_total) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

470

pipes[pipe_cnt].pipe.dest.vtotal =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

471

pipe->stream->adjust.v_total_min;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

472

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

473

pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

476

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

477

pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

482

pipes[pipe_cnt].pipe.dest.vblank_nom =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

483

max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

484

pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

486

if (pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

487

(pipe->plane_state->src_rect.height <

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

488

pipe->plane_state->dst_rect.height ||

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

489

pipe->plane_state->src_rect.width <

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

490

pipe->plane_state->dst_rect.width))

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

499

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

501

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

505

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

506

pipes[pipe_cnt].pipe.src.dcc_rate = 3;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

508

pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

533

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

534

if (is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

535

&& pipe->plane_state->src_rect.width <= 1920 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

536

pipe->plane_state->src_rect.height <= 1080) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

538

} else if (!is_dual_plane(pipe->plane_state->format) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

539

pipe->plane_state->src_rect.width <= 5120) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

545

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

557

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

559

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

562

if (pipe->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

564

pipe->stream->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

566

if (pipe->stream->apply_boot_odm_mode ==

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

477

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

494

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

495

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

500

if (pipe->stream->adjust.v_total_max ==

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

501

pipe->stream->adjust.v_total_min &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

502

pipe->stream->adjust.v_total_min > timing->v_total) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

503

pipes[pipe_cnt].pipe.dest.vtotal =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

504

pipe->stream->adjust.v_total_min;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

505

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total -

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

506

pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

509

pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

510

pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

515

pipes[pipe_cnt].pipe.dest.vblank_nom =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

516

max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

517

pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

519

if (pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

520

(pipe->plane_state->src_rect.height <

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

521

pipe->plane_state->dst_rect.height ||

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

522

pipe->plane_state->src_rect.width <

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

523

pipe->plane_state->dst_rect.width))

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

532

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

534

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

538

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

539

pipes[pipe_cnt].pipe.src.dcc_rate = 3;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

541

pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

566

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

567

if (is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

568

&& pipe->plane_state->src_rect.width <= 1920 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

569

pipe->plane_state->src_rect.height <= 1080) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

571

} else if (!is_dual_plane(pipe->plane_state->format) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

572

pipe->plane_state->src_rect.width <= 5120) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

578

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

590

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

592

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

595

if (pipe->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

597

pipe->stream->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

599

if (pipe->stream->apply_boot_odm_mode ==

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

174

pipe_src = &(pipes[i].pipe.src);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

175

pipe_dest = &(pipes[i].pipe.dest);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

176

scale_ratio_depth = &(pipes[i].pipe.scale_ratio_depth);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

177

scale_taps = &(pipes[i].pipe.scale_taps);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h

558

display_pipe_params_st pipe;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

533

display_pipe_source_params_st *src = &pipes[j].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

534

display_pipe_dest_params_st *dst = &pipes[j].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

535

scaler_ratio_depth_st *scl = &pipes[j].pipe.scale_ratio_depth;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

536

scaler_taps_st *taps = &pipes[j].pipe.scale_taps;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

784

display_pipe_source_params_st *src_k = &pipes[k].pipe.src;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

785

display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

827

if (pipes[j].pipe.src.immediate_flip) {

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

859

mode_lib->vba.SynchronizeTimingsFinal = pipes[0].pipe.dest.synchronize_timings;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

866

if (pipes[k].pipe.src.unbounded_req_mode == 0)

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

871

mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

873

ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

882

mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable || !!pipes[k].pipe.src.gpuvm || !!pipes[k].pipe.src.vm;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

884

(pipes[k].pipe.src.gpuvm_levels_force_en

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

886

< pipes[k].pipe.src.gpuvm_levels_force) ?

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

887

pipes[k].pipe.src.gpuvm_levels_force :

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

890

mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable || !!pipes[k].pipe.src.hostvm || !!pipes[k].pipe.src.vm;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

892

(pipes[k].pipe.src.hostvm_levels_force_en

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

894

< pipes[k].pipe.src.hostvm_levels_force) ?

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

895

pipes[k].pipe.src.hostvm_levels_force :

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

909

mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

910

mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1009

unsigned int htotal = e2e_pipe_param->pipe.dest.htotal;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1010

unsigned int hblank_end = e2e_pipe_param->pipe.dest.hblank_end;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1011

unsigned int vblank_start = e2e_pipe_param->pipe.dest.vblank_start;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1012

unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1013

bool interlaced = e2e_pipe_param->pipe.dest.interlaced;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1016

double pclk_freq_in_mhz = e2e_pipe_param->pipe.dest.pixel_rate_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1199

dcc_en = e2e_pipe_param->pipe.src.dcc;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1201

(enum source_format_class) e2e_pipe_param->pipe.src.source_format);

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1203

access_dir = (e2e_pipe_param->pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1205

(enum source_format_class) e2e_pipe_param->pipe.src.source_format,

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1208

(enum source_format_class) e2e_pipe_param->pipe.src.source_format,

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1210

vp_height_l = e2e_pipe_param->pipe.src.viewport_height;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1211

vp_width_l = e2e_pipe_param->pipe.src.viewport_width;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1212

vp_height_c = e2e_pipe_param->pipe.src.viewport_height_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1213

vp_width_c = e2e_pipe_param->pipe.src.viewport_width_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1216

htaps_l = e2e_pipe_param->pipe.scale_taps.htaps;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1217

htaps_c = e2e_pipe_param->pipe.scale_taps.htaps_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1218

hratios_l = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1219

hratios_c = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1220

vratio_l = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1221

vratio_c = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1224

vinit_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1225

vinit_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1226

vinit_bot_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1227

vinit_bot_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot_c;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1242

vupdate_offset = e2e_pipe_param->pipe.dest.vupdate_offset;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1243

vupdate_width = e2e_pipe_param->pipe.dest.vupdate_width;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1244

vready_offset = e2e_pipe_param->pipe.dest.vready_offset;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1251

vstartup_start = e2e_pipe_param->pipe.dest.vstartup_start;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1278

if (e2e_pipe_param->pipe.src.is_hsplit)

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1280

+ e2e_pipe_param->pipe.dest.recout_width;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1643

if (e2e_pipe_param->pipe.src.is_hsplit) {

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1644

if (e2e_pipe_param->pipe.dest.full_recout_width == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1646

full_recout_width = e2e_pipe_param->pipe.dest.recout_width * 2; /* assume half split for dcn1 */

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1648

full_recout_width = e2e_pipe_param->pipe.dest.full_recout_width;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1650

full_recout_width = e2e_pipe_param->pipe.dest.recout_width;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1817

hratios_cur0 = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio;

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1818

cur0_src_width = e2e_pipe_param->pipe.src.cur0_src_width; /* cursor source width */

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1819

cur0_bpp = (enum cursor_bpp) e2e_pipe_param->pipe.src.cur0_bpp;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

186

struct dc_stream_state *stream, const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

194

if (check_dp2p0_output_encoder(pipe))

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

477

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

479

if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

480

temp_pipe->stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

481

temp_pipe->plane_state = pipe->plane_state;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

482

temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

483

temp_pipe->stream_res = pipe->stream_res;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

484

temp_pipe->dsc_padding_params.dsc_hactive_padding = pipe->dsc_padding_params.dsc_hactive_padding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

485

temp_pipe->dsc_padding_params.dsc_htotal_padding = pipe->dsc_padding_params.dsc_htotal_padding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

486

temp_pipe->dsc_padding_params.dsc_pix_clk_100hz = pipe->dsc_padding_params.dsc_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

73

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

75

struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

79

if (pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

80

*pipe_regs_idx += dml_ctx->config.callbacks.get_mpc_slice_index(pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

32

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1158

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1160

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1161

if (!ctx->config.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1167

pipe->stream &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1168

pipe->prev_odm_pipe == NULL &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1169

pipe->top_pipe == NULL)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1170

ctx->config.callbacks.build_test_pattern_params(&state->res_ctx, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

149

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

151

if (!pipe->plane_state || !pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

154

get_plane_id(ctx, state, pipe->plane_state, pipe->stream->stream_id,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

155

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx],

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

157

if (plane_id_assigned_to_pipe == plane_id && !pipe->prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

158

&& (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

159

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

160

struct pipe_ctx *mpc_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

167

if (mpc_pipe->plane_state != pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

170

pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

227

static bool is_plane_using_pipe(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

229

if (pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

235

static bool is_pipe_free(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

237

if (!pipe->plane_state && !pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

348

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

365

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

366

if (!is_plane_using_pipe(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

369

pipe->pipe_idx = preferred_pipe_candidates[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

370

assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

381

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

382

if (!is_plane_using_pipe(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

385

pipe->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

386

assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

392

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

393

if (!is_plane_using_pipe(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

396

pipe->pipe_idx = last_resort_pipe_candidates[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

397

assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

414

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

431

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

432

if (is_pipe_free(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

435

pipe->pipe_idx = preferred_pipe_candidates[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

436

assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

447

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

448

if (is_pipe_free(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

451

pipe->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

452

assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

458

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

459

if (is_pipe_free(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

462

pipe->pipe_idx = last_resort_pipe_candidates[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

463

assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

538

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

546

pipe = &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

549

scratch->mpc_info.prev_odm_pipe->next_odm_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

551

pipe->prev_odm_pipe = scratch->mpc_info.prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

552

pipe->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

554

scratch->mpc_info.prev_odm_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

589

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

591

if (pipe->stream && pipe->stream->stream_id == stream_id && !pipe->top_pipe && !pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

592

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

593

pipes[num_found++] = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

594

pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

695

static void free_pipe(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

697

memset(pipe, 0, sizeof(struct pipe_ctx));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

719

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

723

pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][0]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

724

if (pipe->top_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

725

pipe->top_pipe->bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

727

if (pipe->bottom_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

728

pipe->bottom_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

107

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

112

if (pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

114

pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

115

if (pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

116

pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

118

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

119

pipe->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

120

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

121

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

122

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

123

pipe->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

124

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

125

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

126

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

127

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

128

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

129

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

130

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

136

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

137

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

138

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

139

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

140

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

141

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

151

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

153

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

156

if (!pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

192

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

194

if (pipe->stream && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

195

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

197

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

238

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

242

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

246

refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

247

pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

248

/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

255

if (pipe->plane_state && !pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

256

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_NONE && refresh_rate < 120 &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

258

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

260

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

263

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

265

struct dc_stream_state *stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

316

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

319

if (pipe->stream && !pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

320

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

322

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

324

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

368

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

374

if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

375

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

376

phantom = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

388

subvp_pipes[index] = pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

435

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

449

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

453

if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

457

if (ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

461

phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

462

main_timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

50

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

509

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

53

if (pipe->stream && pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

534

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

535

pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

539

if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

54

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

549

subvp_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

55

bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

611

enum mall_stream_type pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

613

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

616

if (pipe->plane_state && !pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

62

full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

63

pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) +

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

64

(pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

659

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

665

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

667

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

70

mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) /

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

794

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

799

if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

800

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

801

pipe->stream->use_dynamic_meta = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

802

pipe->plane_state->flip_immediate = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

803

if (!ctx->config.svp_pstate.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

847

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

849

if (pipe->plane_state && pipe->stream && ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

850

phantom_stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

859

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

86

if (pipe->plane_state->dcc.enable)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

860

pipe->plane_state->is_phantom = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1205

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1207

if (!pipe || !pipe->stream || !pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1210

while (pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1211

pipe_index = pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1213

if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1219

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

780

const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

987

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

989

if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

990

temp_pipe->stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

991

temp_pipe->plane_state = pipe->plane_state;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

992

temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

993

temp_pipe->stream_res = pipe->stream_res;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

39

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

84

bool dml2_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

179

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

181

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

182

if (!dml2->config.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

287

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

289

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

290

if (!dml2->config.callbacks.build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

48

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

56

if (lock && pipe->stream_res.tg->funcs->is_blanked &&

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

57

pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

60

val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

71

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

76

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

83

REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

90

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1283

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1291

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1152

static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1155

int vready_offset = pipe->pipe_dlg_param.vready_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1158

for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1162

for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1166

for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1170

for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2149

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2157

if (!pipe || pipe->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2164

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2166

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2238

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2241

if (!pipe || pipe->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2246

delay_cursor_until_vupdate(dc, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2248

if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2253

inst_flags.opp_inst = pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2261

pipe->stream_res.opp->inst, lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2353

static bool is_low_refresh_rate(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2356

pipe->stream->timing.pix_clk_100hz * 100 /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2357

pipe->stream->timing.h_total /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2358

pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2362

static uint8_t get_clock_divider(struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2368

if (account_low_refresh_rate && is_low_refresh_rate(pipe))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2371

if (pipe->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2374

while (pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2375

pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

62

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

64

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1393

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1402

if (!pipe || pipe->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1405

if (pipe->plane_state != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1406

flip_immediate = pipe->plane_state->flip_immediate;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1408

if (pipe->stream_res.gsl_group > 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1409

temp_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1422

temp_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1441

if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1442

if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1443

(!flip_immediate && pipe->stream_res.gsl_group > 0))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1444

dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1446

if (pipe->plane_state != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1447

flip_immediate = pipe->plane_state->flip_immediate;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1449

temp_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1456

if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1458

dcn20_setup_gsl_group_as_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1460

if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1465

inst_flags.otg_inst = pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1467

if (pipe->plane_state != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1468

hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1474

} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1476

pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1478

pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1481

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1484

dc->hwseq->funcs.perform_3dlut_wa_unlock(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1486

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1877

static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1880

int vready_offset = pipe->pipe_dlg_param.vready_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1883

for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1887

for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1891

for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1895

for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2052

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2061

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2063

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2064

ASSERT(!pipe->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2067

dc, pipe, pipe->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2097

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2100

dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2105

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2149

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2150

if (resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2151

!resource_is_pipe_type(pipe, DPP_PIPE) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2152

pipe->update_flags.bits.odm &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2154

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2162

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2164

if (pipe->plane_state && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2165

while (pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2167

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2177

if (pipe->stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2178

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2179

dcn20_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2182

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2187

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2188

if (!pipe->top_pipe && !pipe->prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2189

&& pipe->stream && pipe->stream->num_wb_info > 0

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2190

&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2191

|| pipe->stream->update_flags.raw)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2193

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2197

!pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2198

pipe->stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2199

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2202

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2271

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2273

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2274

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2275

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2285

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2292

if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2293

resource_get_odm_slice_count(old_pipe) < resource_get_odm_slice_count(pipe) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2294

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2296

struct timing_generator *tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2311

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2313

if (pipe->plane_state && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2319

while (pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2320

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2325

dc->hwss.apply_update_flags_for_phantom(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2327

dc->hwss.update_phantom_vp_position(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2328

dcn20_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2330

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2389

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2392

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2433

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2436

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

68

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

527

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

534

if (pipe->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

540

if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

542

pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

544

pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

547

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

549

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

41

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1154

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1156

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1159

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

384

static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

386

return pipe && pipe->stream

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

388

&& pipe->stream_res.stream_enc

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

389

&& pipe->stream_res.stream_enc->funcs->dig_source_otg

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

390

&& pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

391

&& pipe->stream->link && pipe->stream->link->link_enc

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

392

&& pipe->stream->link->link_enc->funcs->is_dig_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

393

&& pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

394

&& pipe->stream_res.stream_enc->funcs->is_fifo_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

395

&& pipe->stream_res.stream_enc->funcs->is_fifo_enabled(pipe->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

401

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

406

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

408

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

411

if (pipe->top_pipe || pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

414

if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

415

!pipe->stream->apply_seamless_boot_optimization &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

416

!pipe->stream->apply_edp_fast_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

417

if (dcn314_is_pipe_dig_fifo_on(pipe))

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

419

pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

429

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

431

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

434

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

436

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

437

int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

440

for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

445

pipe->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

446

pipe->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

450

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1246

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1252

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1255

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1259

if (!resource_is_pipe_type(pipe, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1262

if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1263

&& dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1264

pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1274

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1276

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1279

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1281

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1282

int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1285

for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1290

pipe->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1291

pipe->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1295

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1436

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1438

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1439

dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1440

if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1442

phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1443

phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1444

phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1445

phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1446

phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1576

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1583

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1822

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1826

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1827

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1829

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1831

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1835

dc->hwss.pipe_control_lock(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1837

dc->hwss.pipe_control_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

232

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

234

if (!pipe->stream || !pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

237

mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

381

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

385

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

386

pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

388

if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

406

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

407

if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

409

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

609

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

610

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

613

if (pipe->stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

614

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

616

if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

628

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

630

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

646

if (pipe->stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

647

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

651

if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

674

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

675

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

677

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

700

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

706

pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

707

pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

708

!pipe->plane_state->address.tmz_surface ? 2 : 0,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

734

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

735

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

737

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

743

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1252

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1254

if (!pipe->stream || !pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1257

mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1701

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1706

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1707

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1709

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1711

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1713

dc->hwss.pipe_control_lock(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1718

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1719

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1721

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1723

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1729

dc->hwss.pipe_control_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1740

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1741

tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1742

if (!resource_is_pipe_type(pipe, OTG_MASTER) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1744

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1748

dc->hwss.pipe_control_lock(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1932

static unsigned int dcn401_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1935

unsigned int vready_offset = pipe->global_sync.dcn4x.vready_offset_pixels;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1938

for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1942

for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1946

for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1950

for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2106

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2115

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2117

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2118

if (pipe->plane_state->triplebuffer_flips)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2123

dc, pipe, pipe->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2153

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2156

dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2206

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2207

if (resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2208

!resource_is_pipe_type(pipe, DPP_PIPE) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2209

pipe->update_flags.bits.odm &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2211

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2219

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2221

if (pipe->plane_state && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2222

while (pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2234

if (pipe->stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2235

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2236

dcn401_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2239

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2244

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2245

if (!pipe->top_pipe && !pipe->prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2246

&& pipe->stream && pipe->stream->num_wb_info > 0

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2247

&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2248

|| pipe->stream->update_flags.raw)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2250

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2254

!pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2255

pipe->stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2256

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2259

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2293

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2295

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2296

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2297

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2307

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2314

if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2315

resource_get_odm_slice_count(old_pipe) < resource_get_odm_slice_count(pipe) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2316

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2318

struct timing_generator *tg = pipe->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2334

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2336

if (pipe->plane_state && !pipe->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2342

while (pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2343

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2348

dc->hwss.apply_update_flags_for_phantom(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2350

dc->hwss.update_phantom_vp_position(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2351

dcn401_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2353

pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

253

struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

258

void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

305

void (*set_dmdata_attributes)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

310

void (*set_cursor_position)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

311

void (*set_cursor_attribute)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

312

void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

152

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

484

const struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

38

#define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0)

sys/dev/pci/drm/amd/display/dc/inc/resource.h

39

#define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F)

sys/dev/pci/drm/amd/display/dc/inc/resource.h

40

#define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd))

sys/dev/pci/drm/amd/display/dc/inc/resource.h

443

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

450

int resource_get_odm_slice_count(const struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

958

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

973

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

974

if (pipe->stream && pipe->stream->link) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

975

if (pipe->stream->link == link) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

976

link_stream = pipe->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

196

const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

198

return resource_is_pipe_type(pipe, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

199

pipe->stream->link == link;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

212

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

216

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

218

if (is_master_pipe_for_link(link, pipe) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

219

pipe->stream->dpms_off == false) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

220

pipes[(*count)++] = pipe;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

36

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

41

pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

42

if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

43

if (pipe->stream->link == link) {

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

44

*link_res = pipe->link_res;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1764

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1765

struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1767

if (pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1770

pipe->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1787

if (pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1788

resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1793

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1794

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1796

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1799

pipe->bottom_pipe = hsplit_pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1801

hsplit_pipe->bottom_pipe->top_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1810

if (pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1811

resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1836

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1843

if (pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1844

(pipe->plane_state->dst_rect.width <= 16 ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1845

pipe->plane_state->dst_rect.height <= 16 ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1846

pipe->plane_state->src_rect.width <= 16 ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1847

pipe->plane_state->src_rect.height <= 16))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1851

if (pipe->stream && !pipe->prev_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1852

(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1860

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1863

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1866

timing = pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1897

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1910

if ((pipe->stream->view_format ==

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1912

pipe->stream->view_format ==

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1914

(pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1916

pipe->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1919

if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1923

if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1928

if (pipe->stream->timing.h_addressable > 7680 &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1929

pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1936

if (resource_get_mpc_slice_count(pipe) == 2) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1942

else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1944

} else if (resource_get_mpc_slice_count(pipe) == 4) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1946

if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1947

|| !pipe->bottom_pipe)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1949

} else if (split[i] == 0 && pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1950

pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1953

} else if (resource_get_odm_slice_count(pipe) > 1) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1955

if (pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1961

if (resource_get_odm_slice_count(pipe) == 2) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1967

else if (pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1971

} else if (resource_get_odm_slice_count(pipe) == 4) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1973

if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1974

|| !pipe->next_odm_pipe)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1976

} else if (split[i] == 0 && pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1981

} else if (resource_get_mpc_slice_count(pipe) > 1) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1984

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2046

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2047

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2049

if (!pipe->stream || pipe_split_from[i] >= 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2054

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2055

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2059

pipe, hsplit_pipe))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2062

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2065

if (!pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2068

if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2072

if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2077

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2079

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2090

pipe, hsplit_pipe))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2092

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2096

pipe, hsplit_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2097

resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2102

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2211

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2214

if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2215

dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2216

memset(pipe, 0, sizeof(*pipe));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

67

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

822

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

823

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

826

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

831

&& pipe->plane_state && mpo_pipe

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

833

&pipe->stream->src,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

835

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

846

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

847

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

849

if (!pipe->stream || pipe_split_from[i] >= 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

854

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

855

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

859

pipe, hsplit_pipe))

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

862

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

865

if (!pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

868

if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

872

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

874

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

885

pipe, hsplit_pipe))

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

887

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

891

pipe, hsplit_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

892

resource_build_scaling_params(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

897

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1335

pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1587

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1591

pipe = &context->res_ctx.pipe_ctx[old_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1592

pipe->pipe_idx = old_index;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1595

if (!pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1600

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1601

pipe->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1612

if (!pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1615

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1616

pipe->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1621

return pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1701

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1702

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1704

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1709

&& pipe->plane_state && mpo_pipe

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1711

&pipe->stream->src,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1713

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1722

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1729

if (pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1731

pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1732

if (pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1733

pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1735

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1736

pipe->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1737

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1738

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1739

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1740

pipe->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1741

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1742

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1743

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1744

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1746

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1747

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1748

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1754

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1755

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1756

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1757

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1758

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1759

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1767

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1773

if (!pipe->stream || newly_split[i])

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1779

if (!pipe->plane_state && !odm)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1803

pipe, hsplit_pipe, odm))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1825

pipe, pipe_4to1, odm))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1849

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1853

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1855

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1856

if (!resource_build_scaling_params(pipe))

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1629

pipes[i].pipe.src.gpuvm = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1632

pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1634

pipes[i].pipe.src.hostvm = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1636

pipes[i].pipe.src.hostvm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1648

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1660

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1661

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1662

if (pipe->plane_state &&

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1663

(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1664

pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1672

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1673

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1674

pipes[pipe_cnt].pipe.src.gpuvm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1675

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1676

pipes[pipe_cnt].pipe.src.dcc_rate = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1704

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1705

if (is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1706

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1708

} else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1711

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1671

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1685

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1686

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1693

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1695

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1696

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1697

pipes[pipe_cnt].pipe.src.dcc_rate = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1702

int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1710

split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1717

pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1747

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1748

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1753

pipes[pipe_cnt].pipe.src.det_size_override = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1758

bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1759

|| (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1762

pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1764

if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1766

remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1767

pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1769

if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1771

remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1772

pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1775

pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1789

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1790

if (is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1791

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1795

} else if (!is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1796

&& pipe->plane_state->src_rect.width <= 5120

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1797

&& pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1800

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1617

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1629

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1630

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1637

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1639

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1640

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1641

pipes[pipe_cnt].pipe.src.dcc_rate = 3;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1674

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1675

if (is_dual_plane(pipe->plane_state->format)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1676

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1680

} else if (!is_dual_plane(pipe->plane_state->format)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1682

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1730

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1735

if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1736

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1737

pipe->stream->use_dynamic_meta = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1738

pipe->plane_state->flip_immediate = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1739

if (!resource_build_scaling_params(pipe)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1873

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1905

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1909

mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1911

if (resource_is_pipe_type(pipe, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1922

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1923

timing = &pipe->stream->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1925

pipes[pipe_cnt].pipe.src.gpuvm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1929

pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1935

mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1944

odm_slice_count = resource_get_odm_slice_count(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1948

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1951

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1954

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1957

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1960

pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1961

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1962

pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1968

switch (dc_state_get_pipe_subvp_type(context, pipe)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1970

pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1974

pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1975

pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1977

pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1980

pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1981

pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2733

struct pipe_ctx *idle_pipe, *pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2749

pipe = &old_ctx->pipe_ctx[head_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2750

if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2751

idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2752

idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

137

bool dcn32_is_center_timing(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

138

bool dcn32_is_psr_capable(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

159

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

171

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

179

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

114

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

119

if (pipe->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

121

pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

122

if (pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

123

pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

125

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

126

pipe->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

127

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

128

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

129

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

130

pipe->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

131

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

132

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

133

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

134

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

135

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

136

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

137

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

143

pipe->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

144

pipe->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

145

pipe->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

146

pipe->stream = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

147

memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

148

memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

159

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

161

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

164

if (!pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

176

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

178

if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

201

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

203

if (!pipe->stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

206

if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

212

bool dcn32_is_center_timing(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

216

if (pipe->stream) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

217

if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

218

pipe->stream->timing.v_addressable != pipe->stream->src.height) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

222

if (pipe->plane_state) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

223

if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

224

pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

233

bool dcn32_is_psr_capable(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

237

if (pipe->stream && pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

372

pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

377

pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

386

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

394

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

403

pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

404

if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

405

if (!is_dual_plane(pipe->plane_state->format)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

406

pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

407

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

408

if (pipe->plane_state->src_rect.width >= 5120 &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

409

pipe->plane_state->src_rect.height >= 2880)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

410

pipes[0].pipe.src.det_size_override = 320; // 5K or higher

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

591

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

595

if (pipe->stream->timing.h_addressable == width &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

596

pipe->stream->timing.v_addressable == height &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

597

pipe->plane_state->src_rect.width == width &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

598

pipe->plane_state->src_rect.height == height &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

599

pipe->plane_state->dst_rect.width == width &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

600

pipe->plane_state->dst_rect.height == height)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

618

static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

622

if (resource_is_pipe_type(pipe, OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

623

resource_is_pipe_type(pipe, DPP_PIPE)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

624

if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

656

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

657

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

659

if (resource_is_pipe_type(pipe, OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

660

resource_is_pipe_type(pipe, DPP_PIPE)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

664

subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

665

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

666

pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

667

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

668

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

672

drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

673

if (pipe->stream->ignore_msa_timing_param &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

674

(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

717

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

718

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

720

if (resource_is_pipe_type(pipe, OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

721

resource_is_pipe_type(pipe, DPP_PIPE)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

725

subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

726

refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

727

pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

728

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

729

refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

733

vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

734

if (pipe->stream->ignore_msa_timing_param &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

735

(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

755

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

762

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

763

odm_slice_count = resource_get_odm_slice_count(pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

766

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

768

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

770

pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4209

u32 tmp, pipe;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4225

pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4227

if (cfg->num_display > 0 && pipe != cfg->crtc_index) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4228

pipe = cfg->crtc_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4231

tmp |= DCCG_DISP1_SLOW_SELECT(pipe);

sys/dev/pci/drm/drm_internal.h

103

void drm_vblank_disable_and_save(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/drm_internal.h

104

int drm_vblank_get(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/drm_internal.h

105

void drm_vblank_put(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/drm_internal.h

106

u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/drm_vblank.c

1053

trace_drm_vblank_event_delivered(e->base.file_priv, e->pipe, seq);

sys/dev/pci/drm/drm_vblank.c

1106

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

1110

e->pipe = pipe;

sys/dev/pci/drm/drm_vblank.c

1132

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

1136

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

1142

e->pipe = pipe;

sys/dev/pci/drm/drm_vblank.c

1147

static int __enable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1150

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1162

static int drm_vblank_enable(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1164

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1179

ret = __enable_vblank(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1181

pipe, ret);

sys/dev/pci/drm/drm_vblank.c

1185

drm_update_vblank_count(dev, pipe, 0);

sys/dev/pci/drm/drm_vblank.c

1200

int drm_vblank_get(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1202

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1209

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

1215

ret = drm_vblank_enable(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1243

void drm_vblank_put(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1245

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1248

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

1291

void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1293

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1297

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

1313

ret = drm_vblank_get(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1315

pipe, ret))

sys/dev/pci/drm/drm_vblank.c

1318

last = drm_vblank_count(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1321

last != drm_vblank_count(dev, pipe),

sys/dev/pci/drm/drm_vblank.c

1324

drm_WARN(dev, ret == 0, "vblank wait timed out on crtc %i\n", pipe);

sys/dev/pci/drm/drm_vblank.c

1326

drm_vblank_put(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1358

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

1364

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

1375

pipe, vblank->enabled, vblank->inmodeset);

sys/dev/pci/drm/drm_vblank.c

1380

drm_vblank_disable_and_save(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1395

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

1398

if (e->pipe != pipe)

sys/dev/pci/drm/drm_vblank.c

1404

drm_vblank_put(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1502

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

1505

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

1510

pipe, vblank->enabled, vblank->inmodeset);

sys/dev/pci/drm/drm_vblank.c

1520

drm_reset_vblank_timestamp(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1527

drm_WARN_ON(dev, drm_vblank_enable(dev, pipe));

sys/dev/pci/drm/drm_vblank.c

1555

static void drm_vblank_restore(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1563

u32 max_vblank_count = drm_max_vblank_count(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1565

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

157

drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

1571

vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1578

cur_vblank = __get_vblank_counter(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1579

drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);

sys/dev/pci/drm/drm_vblank.c

1580

} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);

sys/dev/pci/drm/drm_vblank.c

1612

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

1613

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1619

drm_vblank_restore(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1623

static int drm_queue_vblank_event(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

1628

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1640

e->pipe = pipe;

sys/dev/pci/drm/drm_vblank.c

1646

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1671

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

1674

req_seq, seq, pipe);

sys/dev/pci/drm/drm_vblank.c

1676

trace_drm_vblank_event_queued(file_priv, pipe, req_seq);

sys/dev/pci/drm/drm_vblank.c

1680

drm_vblank_put(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1697

drm_vblank_put(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

170

drm_vblank_crtc(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

172

return &dev->vblank[pipe];

sys/dev/pci/drm/drm_vblank.c

1728

static void drm_wait_vblank_reply(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

1739

reply->sequence = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

1759

unsigned int flags, pipe, high_pipe;

sys/dev/pci/drm/drm_vblank.c

1787

pipe = 0;

sys/dev/pci/drm/drm_vblank.c

1794

pipe++;

sys/dev/pci/drm/drm_vblank.c

1797

pipe = pipe_index;

sys/dev/pci/drm/drm_vblank.c

1800

if (pipe >= dev->num_crtcs)

sys/dev/pci/drm/drm_vblank.c

1803

vblank = &dev->vblank[pipe];

sys/dev/pci/drm/drm_vblank.c

1811

drm_wait_vblank_reply(dev, pipe, &vblwait->reply);

sys/dev/pci/drm/drm_vblank.c

1815

ret = drm_vblank_get(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1819

pipe, ret);

sys/dev/pci/drm/drm_vblank.c

182

static void store_vblank(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

1822

seq = drm_vblank_count(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1849

return drm_queue_vblank_event(dev, pipe, req_seq, vblwait, file_priv);

sys/dev/pci/drm/drm_vblank.c

1856

req_seq, pipe);

sys/dev/pci/drm/drm_vblank.c

1858

drm_vblank_passed(drm_vblank_count(dev, pipe), req_seq) ||

sys/dev/pci/drm/drm_vblank.c

186

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1878

drm_wait_vblank_reply(dev, pipe, &vblwait->reply);

sys/dev/pci/drm/drm_vblank.c

1881

pipe, vblwait->reply.sequence);

sys/dev/pci/drm/drm_vblank.c

1884

pipe);

sys/dev/pci/drm/drm_vblank.c

1888

drm_vblank_put(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1892

static void drm_handle_vblank_events(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1894

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1902

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

1905

if (e->pipe != pipe)

sys/dev/pci/drm/drm_vblank.c

1914

drm_vblank_put(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1921

trace_drm_vblank_event(pipe, seq, now, high_prec);

sys/dev/pci/drm/drm_vblank.c

1934

bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

1936

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

1943

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

1961

drm_update_vblank_count(dev, pipe, true);

sys/dev/pci/drm/drm_vblank.c

1976

drm_handle_vblank_events(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

198

static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

200

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

2027

int pipe;

sys/dev/pci/drm/drm_vblank.c

2043

pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

2054

pipe, ret);

sys/dev/pci/drm/drm_vblank.c

2064

get_seq->sequence = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

2084

int pipe;

sys/dev/pci/drm/drm_vblank.c

209

static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

2109

pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

211

drm_WARN_ON_ONCE(dev, drm_max_vblank_count(dev, pipe) != 0);

sys/dev/pci/drm/drm_vblank.c

2121

pipe, ret);

sys/dev/pci/drm/drm_vblank.c

2125

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/pci/drm/drm_vblank.c

2134

e->pipe = pipe;

sys/dev/pci/drm/drm_vblank.c

215

static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

218

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

227

return drm_vblank_no_hw_counter(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

239

static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

253

cur_vblank = __get_vblank_counter(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

254

rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);

sys/dev/pci/drm/drm_vblank.c

255

} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);

sys/dev/pci/drm/drm_vblank.c

269

store_vblank(dev, pipe, 1, t_vblank, cur_vblank);

sys/dev/pci/drm/drm_vblank.c

286

static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

289

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

295

u32 max_vblank_count = drm_max_vblank_count(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

310

cur_vblank = __get_vblank_counter(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

311

rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, in_vblank_irq);

sys/dev/pci/drm/drm_vblank.c

312

} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);

sys/dev/pci/drm/drm_vblank.c

328

pipe, (long long)diff_ns, framedur_ns);

sys/dev/pci/drm/drm_vblank.c

334

pipe);

sys/dev/pci/drm/drm_vblank.c

352

" due to pre-modeset.\n", pipe, diff);

sys/dev/pci/drm/drm_vblank.c

358

pipe, (unsigned long long)atomic64_read(&vblank->count),

sys/dev/pci/drm/drm_vblank.c

375

store_vblank(dev, pipe, diff, t_vblank, cur_vblank);

sys/dev/pci/drm/drm_vblank.c

378

u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

380

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

383

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

414

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

424

drm_update_vblank_count(dev, pipe, false);

sys/dev/pci/drm/drm_vblank.c

425

vblank = drm_vblank_count(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

433

static void __disable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

436

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

452

void drm_vblank_disable_and_save(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

454

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

480

drm_update_vblank_count(dev, pipe, false);

sys/dev/pci/drm/drm_vblank.c

481

__disable_vblank(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

492

unsigned int pipe = vblank->pipe;

sys/dev/pci/drm/drm_vblank.c

497

drm_dbg_core(dev, "disabling vblank on crtc %u\n", pipe);

sys/dev/pci/drm/drm_vblank.c

498

drm_vblank_disable_and_save(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

544

vblank->pipe = i;

sys/dev/pci/drm/drm_vblank.c

619

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/pci/drm/drm_vblank.c

627

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))

sys/dev/pci/drm/drm_vblank.c

703

unsigned int pipe = crtc->index;

sys/dev/pci/drm/drm_vblank.c

704

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/pci/drm/drm_vblank.c

712

if (pipe >= dev->num_crtcs) {

sys/dev/pci/drm/drm_vblank.c

713

drm_err(dev, "Invalid crtc %u\n", pipe);

sys/dev/pci/drm/drm_vblank.c

733

pipe);

sys/dev/pci/drm/drm_vblank.c

759

pipe);

sys/dev/pci/drm/drm_vblank.c

775

pipe, duration_ns / 1000, *max_error / 1000, i);

sys/dev/pci/drm/drm_vblank.c

801

pipe, hpos, vpos,

sys/dev/pci/drm/drm_vblank.c

896

drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

899

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

945

static u64 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

948

struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);

sys/dev/pci/drm/drm_vblank.c

952

if (drm_WARN_ON(dev, pipe >= dev->num_crtcs)) {

sys/dev/pci/drm/drm_vblank_work.c

134

ret = drm_vblank_get(dev, vblank->pipe);

sys/dev/pci/drm/drm_vblank_work.c

145

cur_vbl = drm_vblank_count(dev, vblank->pipe);

sys/dev/pci/drm/drm_vblank_work.c

150

vblank->pipe, count, cur_vbl);

sys/dev/pci/drm/drm_vblank_work.c

153

drm_vblank_put(dev, vblank->pipe);

sys/dev/pci/drm/drm_vblank_work.c

198

drm_vblank_put(vblank->dev, vblank->pipe);

sys/dev/pci/drm/drm_vblank_work.c

286

vblank->pipe);

sys/dev/pci/drm/drm_vblank_work.c

63

drm_vblank_put(vblank->dev, vblank->pipe);

sys/dev/pci/drm/drm_vblank_work.c

85

drm_vblank_put(vblank->dev, vblank->pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

143

intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

147

intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/g4x_dp.c

165

intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

167

intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

226

intel_wait_for_vblank_if_active(display, !crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

254

enum port port, enum pipe *pipe)

sys/dev/pci/drm/i915/display/g4x_dp.c

256

enum pipe p;

sys/dev/pci/drm/i915/display/g4x_dp.c

262

*pipe = p;

sys/dev/pci/drm/i915/display/g4x_dp.c

271

*pipe = PIPE_A;

sys/dev/pci/drm/i915/display/g4x_dp.c

278

enum pipe *pipe)

sys/dev/pci/drm/i915/display/g4x_dp.c

289

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);

sys/dev/pci/drm/i915/display/g4x_dp.c

291

ret &= cpt_dp_port_selected(display, port, pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

293

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);

sys/dev/pci/drm/i915/display/g4x_dp.c

295

*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/g4x_dp.c

301

enum pipe *pipe)

sys/dev/pci/drm/i915/display/g4x_dp.c

314

encoder->port, pipe);

sys/dev/pci/drm/i915/display/g4x_dp.c

356

TRANS_DP_CTL(crtc->pipe));

sys/dev/pci/drm/i915/display/g4x_dp.c

436

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {

sys/dev/pci/drm/i915/display/g4x_dp.h

13

enum pipe;

sys/dev/pci/drm/i915/display/g4x_dp.h

24

enum pipe *pipe);

sys/dev/pci/drm/i915/display/g4x_dp.h

34

enum pipe *pipe)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

328

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

346

intel_de_rmw(display, TRANS_CHICKEN1(pipe),

sys/dev/pci/drm/i915/display/g4x_hdmi.c

363

intel_de_rmw(display, TRANS_CHICKEN1(pipe),

sys/dev/pci/drm/i915/display/g4x_hdmi.c

398

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/g4x_hdmi.c

56

hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

58

hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

60

hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

67

enum pipe *pipe)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

79

ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);

sys/dev/pci/drm/i915/display/hsw_ips.c

189

return HAS_IPS(display) && crtc->pipe == PIPE_A;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1085

"primary %c", pipe_name(pipe));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1100

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/i9xx_plane.c

1169

enum pipe pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1176

if (!plane->get_hw_state(plane, &pipe))

sys/dev/pci/drm/i915/display/i9xx_plane.c

1179

drm_WARN_ON(display->drm, pipe != crtc->pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1204

pipe == PIPE_B && val & DISP_MIRROR)

sys/dev/pci/drm/i915/display/i9xx_plane.c

1231

val = intel_de_read(display, PIPESRC(display, pipe));

sys/dev/pci/drm/i915/display/i9xx_plane.c

388

dspcntr |= DISP_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.c

636

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

639

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

sys/dev/pci/drm/i915/display/i9xx_plane.c

647

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

650

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

sys/dev/pci/drm/i915/display/i9xx_plane.c

698

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

701

i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

sys/dev/pci/drm/i915/display/i9xx_plane.c

709

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

712

i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

sys/dev/pci/drm/i915/display/i9xx_plane.c

722

enum pipe *pipe)

sys/dev/pci/drm/i915/display/i9xx_plane.c

736

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.c

746

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

748

*pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/i9xx_plane.c

929

intel_primary_plane_create(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/i9xx_plane.c

943

plane->pipe = pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

950

plane->i9xx_plane = (enum i9xx_plane_id) !pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

952

plane->i9xx_plane = (enum i9xx_plane_id) pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

954

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);

sys/dev/pci/drm/i915/display/i9xx_plane.h

11

enum pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.h

30

intel_primary_plane_create(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.h

48

intel_primary_plane_create(struct intel_display *display, int pipe)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

35

#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/i9xx_wm.c

1419

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1421

wm->pipe[pipe] = wm_state->wm;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1760

wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1897

switch (crtc->pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2058

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2060

wm->pipe[pipe] = wm_state->wm[wm->level];

sys/dev/pci/drm/i915/display/i9xx_wm.c

2064

wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2065

wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2066

wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2067

wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2219

return intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

288

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

292

switch (pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

312

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3226

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3233

results->wm_pipe[pipe] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3271

#define WM_DIRTY_PIPE(pipe) (1 << (pipe))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3282

enum pipe pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3285

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3286

if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3287

dirty |= WM_DIRTY_PIPE(pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3502

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3504

hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3511

u32 tmp = hw->wm_pipe[pipe];

sys/dev/pci/drm/i915/display/i9xx_wm.c

3672

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3673

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3674

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3680

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3681

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3682

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3694

enum pipe pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3697

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3698

tmp = intel_de_read(display, VLV_DDL(pipe));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3700

wm->ddl[pipe].plane[PLANE_PRIMARY] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3702

wm->ddl[pipe].plane[PLANE_CURSOR] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3704

wm->ddl[pipe].plane[PLANE_SPRITE0] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3706

wm->ddl[pipe].plane[PLANE_SPRITE1] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3712

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3713

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3714

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3717

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3718

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3719

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3726

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3727

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3730

wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3731

wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3734

wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3735

wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3739

wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3740

wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3741

wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3742

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3743

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3744

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3745

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3746

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3747

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3750

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3751

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3755

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3756

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3757

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3758

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3759

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3760

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3781

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3794

wm->pipe[pipe].plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

3843

pipe_name(pipe),

sys/dev/pci/drm/i915/display/i9xx_wm.c

3844

wm->pipe[pipe].plane[PLANE_PRIMARY],

sys/dev/pci/drm/i915/display/i9xx_wm.c

3845

wm->pipe[pipe].plane[PLANE_CURSOR],

sys/dev/pci/drm/i915/display/i9xx_wm.c

3846

wm->pipe[pipe].plane[PLANE_SPRITE0]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3869

intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3964

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3982

wm->pipe[pipe].plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

4000

pipe_name(pipe),

sys/dev/pci/drm/i915/display/i9xx_wm.c

4001

wm->pipe[pipe].plane[PLANE_PRIMARY],

sys/dev/pci/drm/i915/display/i9xx_wm.c

4002

wm->pipe[pipe].plane[PLANE_CURSOR],

sys/dev/pci/drm/i915/display/i9xx_wm.c

4003

wm->pipe[pipe].plane[PLANE_SPRITE0],

sys/dev/pci/drm/i915/display/i9xx_wm.c

4004

wm->pipe[pipe].plane[PLANE_SPRITE1]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4021

intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

779

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/i9xx_wm.c

808

enum pipe pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

810

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/i9xx_wm.c

811

trace_g4x_wm(intel_crtc_for_pipe(display, pipe), wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

815

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

816

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

817

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

822

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

823

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

824

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

840

enum pipe pipe;

sys/dev/pci/drm/i915/display/i9xx_wm.c

842

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

843

trace_vlv_wm(intel_crtc_for_pipe(display, pipe), wm);

sys/dev/pci/drm/i915/display/i9xx_wm.c

845

intel_de_write(display, VLV_DDL(pipe),

sys/dev/pci/drm/i915/display/i9xx_wm.c

846

(wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

847

(wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

848

(wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

849

(wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));

sys/dev/pci/drm/i915/display/i9xx_wm.c

865

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

866

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

867

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

869

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

870

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

871

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

877

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

878

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/pci/drm/i915/display/i9xx_wm.c

880

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

881

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));

sys/dev/pci/drm/i915/display/i9xx_wm.c

883

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

884

FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));

sys/dev/pci/drm/i915/display/i9xx_wm.c

887

FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

888

FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

889

FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

890

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

891

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

892

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

893

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

894

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

895

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

sys/dev/pci/drm/i915/display/i9xx_wm.c

898

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

899

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/pci/drm/i915/display/i9xx_wm.c

902

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

903

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

904

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

905

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

906

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

907

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

175

#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

sys/dev/pci/drm/i915/display/i9xx_wm_regs.h

220

#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \

sys/dev/pci/drm/i915/display/icl_dsi.c

1247

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/icl_dsi.c

1251

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)

sys/dev/pci/drm/i915/display/icl_dsi.c

1286

icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);

sys/dev/pci/drm/i915/display/icl_dsi.c

1461

icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);

sys/dev/pci/drm/i915/display/icl_dsi.c

1597

enum pipe pipe;

sys/dev/pci/drm/i915/display/icl_dsi.c

1603

pipe = intel_crtc->pipe;

sys/dev/pci/drm/i915/display/icl_dsi.c

1606

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&

sys/dev/pci/drm/i915/display/icl_dsi.c

1723

enum pipe *pipe)

sys/dev/pci/drm/i915/display/icl_dsi.c

1744

*pipe = PIPE_A;

sys/dev/pci/drm/i915/display/icl_dsi.c

1747

*pipe = PIPE_B;

sys/dev/pci/drm/i915/display/icl_dsi.c

1750

*pipe = PIPE_C;

sys/dev/pci/drm/i915/display/icl_dsi.c

1753

*pipe = PIPE_D;

sys/dev/pci/drm/i915/display/icl_dsi.c

307

dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);

sys/dev/pci/drm/i915/display/icl_dsi.c

308

dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);

sys/dev/pci/drm/i915/display/icl_dsi.c

707

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/icl_dsi.c

830

switch (pipe) {

sys/dev/pci/drm/i915/display/icl_dsi.c

832

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

604

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_audio.c

608

regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

609

regs->aud_config = VLV_AUD_CFG(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

610

regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

613

regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

614

regs->aud_config = CPT_AUD_CFG(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

615

regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

618

regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

619

regs->aud_config = IBX_AUD_CFG(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

620

regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);

sys/dev/pci/drm/i915/display/intel_audio.c

632

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_audio.c

638

ibx_audio_regs_init(display, pipe, &regs);

sys/dev/pci/drm/i915/display/intel_audio.c

668

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_audio.c

676

ibx_audio_regs_init(display, pipe, &regs);

sys/dev/pci/drm/i915/display/intel_audio_regs.h

137

#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

138

#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

139

#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

140

#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

141

#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

142

#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))

sys/dev/pci/drm/i915/display/intel_audio_regs.h

20

#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \

sys/dev/pci/drm/i915/display/intel_audio_regs.h

24

#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \

sys/dev/pci/drm/i915/display/intel_audio_regs.h

35

#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

38

#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

43

#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

46

#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

51

#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

54

#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)

sys/dev/pci/drm/i915/display/intel_audio_regs.h

57

#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)

sys/dev/pci/drm/i915/display/intel_backlight.c

1248

static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1305

static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1336

static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1378

static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1411

static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

1417

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

sys/dev/pci/drm/i915/display/intel_backlight.c

1420

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

1423

ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

1438

connector->base.base.id, connector->base.name, pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

1444

bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

150

static u32 lpt_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1512

cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1557

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

157

static u32 pch_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1626

static u32 intel_pwm_get_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

1631

panel->backlight.pwm_funcs->get(connector, pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

164

static u32 i9xx_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

1653

static int intel_pwm_setup_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

1658

ret = panel->backlight.pwm_funcs->setup(connector, pipe);

sys/dev/pci/drm/i915/display/intel_backlight.c

1664

panel->backlight.level = intel_pwm_get_backlight(connector, pipe);

sys/dev/pci/drm/i915/display/intel_backlight.c

1689

int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

1714

ret = panel->backlight.funcs->setup(connector, pipe);

sys/dev/pci/drm/i915/display/intel_backlight.c

185

static u32 vlv_get_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_backlight.c

189

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

sys/dev/pci/drm/i915/display/intel_backlight.c

192

return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

195

static u32 bxt_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

203

static u32 ext_pwm_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_backlight.c

270

enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_backlight.c

273

tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

274

intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level);

sys/dev/pci/drm/i915/display/intel_backlight.c

406

enum pipe pipe = to_intel_crtc(old_conn_state->crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_backlight.c

410

intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

627

enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_backlight.c

646

ctl2 = BLM_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_backlight.c

664

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_backlight.c

667

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

673

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

677

intel_de_write(display, VLV_BLC_PWM_CTL(pipe), ctl);

sys/dev/pci/drm/i915/display/intel_backlight.c

685

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2);

sys/dev/pci/drm/i915/display/intel_backlight.c

686

intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

687

intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

696

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_backlight.c

714

val | UTIL_PIN_PIPE(pipe) | UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);

sys/dev/pci/drm/i915/display/intel_backlight.c

816

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_backlight.c

821

drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.h

17

enum pipe;

sys/dev/pci/drm/i915/display/intel_backlight.h

20

int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

13

#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, _VLV_BLC_PWM_CTL2_B)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

17

#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, _VLV_BLC_PWM_CTL_B)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

21

#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B)

sys/dev/pci/drm/i915/display/intel_backlight_regs.h

36

#define BLM_PIPE(pipe) ((pipe) << 29)

sys/dev/pci/drm/i915/display/intel_bw.c

1284

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

1286

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_bw.c

1288

&old_bw_state->dbuf_bw[pipe];

sys/dev/pci/drm/i915/display/intel_bw.c

1290

&new_bw_state->dbuf_bw[pipe];

sys/dev/pci/drm/i915/display/intel_bw.c

1295

if (intel_bw_crtc_min_cdclk(display, old_bw_state->data_rate[pipe]) !=

sys/dev/pci/drm/i915/display/intel_bw.c

1296

intel_bw_crtc_min_cdclk(display, new_bw_state->data_rate[pipe]))

sys/dev/pci/drm/i915/display/intel_bw.c

1365

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

1371

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_bw.c

1372

const struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[pipe];

sys/dev/pci/drm/i915/display/intel_bw.c

1388

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

1393

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_bw.c

1396

bw_state->data_rate[pipe]));

sys/dev/pci/drm/i915/display/intel_bw.c

1433

new_bw_state->dbuf_bw[crtc->pipe] = new_dbuf_bw;

sys/dev/pci/drm/i915/display/intel_bw.c

1513

new_bw_state->data_rate[crtc->pipe] = new_data_rate;

sys/dev/pci/drm/i915/display/intel_bw.c

1514

new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;

sys/dev/pci/drm/i915/display/intel_bw.c

1521

new_bw_state->data_rate[crtc->pipe],

sys/dev/pci/drm/i915/display/intel_bw.c

1522

new_bw_state->num_active_planes[crtc->pipe]);

sys/dev/pci/drm/i915/display/intel_bw.c

1580

new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_bw.c

1582

new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_bw.c

1659

bw_state->data_rate[crtc->pipe] =

sys/dev/pci/drm/i915/display/intel_bw.c

1661

bw_state->num_active_planes[crtc->pipe] =

sys/dev/pci/drm/i915/display/intel_bw.c

1665

pipe_name(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_bw.c

1666

bw_state->data_rate[crtc->pipe],

sys/dev/pci/drm/i915/display/intel_bw.c

1667

bw_state->num_active_planes[crtc->pipe]);

sys/dev/pci/drm/i915/display/intel_bw.c

1685

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

1688

bw_state->active_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_bw.c

1693

skl_crtc_calc_dbuf_bw(&bw_state->dbuf_bw[pipe], crtc_state);

sys/dev/pci/drm/i915/display/intel_bw.c

1696

bw_state->pipe_sagv_reject |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_bw.c

1705

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

1710

bw_state->data_rate[pipe] = 0;

sys/dev/pci/drm/i915/display/intel_bw.c

1711

bw_state->num_active_planes[pipe] = 0;

sys/dev/pci/drm/i915/display/intel_bw.c

1712

memset(&bw_state->dbuf_bw[pipe], 0, sizeof(bw_state->dbuf_bw[pipe]));

sys/dev/pci/drm/i915/display/intel_bw.c

886

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

888

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_bw.c

889

num_active_planes += bw_state->num_active_planes[pipe];

sys/dev/pci/drm/i915/display/intel_bw.c

899

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_bw.c

901

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_bw.c

902

data_rate += bw_state->data_rate[pipe];

sys/dev/pci/drm/i915/display/intel_cdclk.c

1167

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

143

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

160

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

173

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

175

display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1886

static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1889

if (pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1892

return TGL_CDCLK_CD2X_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1894

if (pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1897

return ICL_CDCLK_CD2X_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1899

if (pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1902

return BXT_CDCLK_CD2X_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2103

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2113

bxt_cdclk_cd2x_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2133

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2158

intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));

sys/dev/pci/drm/i915/display/intel_cdclk.c

2160

if (pipe != INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2161

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));

sys/dev/pci/drm/i915/display/intel_cdclk.c

2166

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2206

_bxt_set_cdclk(display, &mid_cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2207

_bxt_set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2209

_bxt_set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2545

enum pipe pipe, const char *context)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2578

intel_cdclk_set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2712

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2723

pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2727

pipe = new_cdclk_state->pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2730

pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2745

intel_set_cdclk(display, &cdclk_config, pipe,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2764

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2775

pipe = new_cdclk_state->pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2777

pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2781

intel_set_cdclk(display, &new_cdclk_state->actual, pipe,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2852

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2861

if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2864

cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2888

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2889

min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2935

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2945

if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2948

cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2956

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2958

cdclk_state->min_voltage_level[pipe]);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3156

cdclk_state->pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3269

enum pipe pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3311

pipe = ilog2(new_cdclk_state->active_pipes);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3312

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3319

pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3337

} else if (pipe != INVALID_PIPE) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3338

new_cdclk_state->pipe = pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3342

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_cdclk.c

3390

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3393

cdclk_state->active_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3395

cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3396

cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3895

int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3897

return cdclk_state->min_cdclk[pipe];

sys/dev/pci/drm/i915/display/intel_cdclk.c

671

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

762

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.c

882

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cdclk.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_cdclk.h

66

int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_color.c

1031

intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1041

intel_de_write(display, GAMMA_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1044

intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1052

return intel_de_read(display, GAMMA_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1059

return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1098

tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1112

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1127

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), val);

sys/dev/pci/drm/i915/display/intel_color.c

1129

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1131

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1139

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1145

intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), 0);

sys/dev/pci/drm/i915/display/intel_color.c

1147

intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1149

intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);

sys/dev/pci/drm/i915/display/intel_color.c

1171

intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1248

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1257

intel_de_write_fw(display, PALETTE(display, pipe, i),

sys/dev/pci/drm/i915/display/intel_color.c

1267

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1271

PALETTE(display, pipe, 2 * i + 0),

sys/dev/pci/drm/i915/display/intel_color.c

1274

PALETTE(display, pipe, 2 * i + 1),

sys/dev/pci/drm/i915/display/intel_color.c

1303

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1307

PALETTE(display, pipe, 2 * i + 0),

sys/dev/pci/drm/i915/display/intel_color.c

1310

PALETTE(display, pipe, 2 * i + 1),

sys/dev/pci/drm/i915/display/intel_color.c

1314

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 0), lut[i].red);

sys/dev/pci/drm/i915/display/intel_color.c

1315

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 1), lut[i].green);

sys/dev/pci/drm/i915/display/intel_color.c

1316

intel_de_write_fw(display, PIPEGCMAX(display, pipe, 2), lut[i].blue);

sys/dev/pci/drm/i915/display/intel_color.c

1364

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1390

ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),

sys/dev/pci/drm/i915/display/intel_color.c

1393

ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),

sys/dev/pci/drm/i915/display/intel_color.c

1404

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1407

ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i),

sys/dev/pci/drm/i915/display/intel_color.c

1450

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1453

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1455

ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1463

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1475

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1477

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1479

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1484

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1491

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1498

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1501

ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);

sys/dev/pci/drm/i915/display/intel_color.c

1502

ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);

sys/dev/pci/drm/i915/display/intel_color.c

1503

ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);

sys/dev/pci/drm/i915/display/intel_color.c

1509

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1512

ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);

sys/dev/pci/drm/i915/display/intel_color.c

1513

ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);

sys/dev/pci/drm/i915/display/intel_color.c

1514

ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);

sys/dev/pci/drm/i915/display/intel_color.c

1611

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1618

ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1620

ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1638

ilk_lut_write_indexed(crtc_state, PRE_CSC_GAMC_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1645

ilk_lut_write_indexed(crtc_state, PRE_CSC_GAMC_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1649

ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0);

sys/dev/pci/drm/i915/display/intel_color.c

1680

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1683

ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);

sys/dev/pci/drm/i915/display/intel_color.c

1684

ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);

sys/dev/pci/drm/i915/display/intel_color.c

1685

ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);

sys/dev/pci/drm/i915/display/intel_color.c

1694

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1704

ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1706

ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1713

ilk_lut_write_indexed(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1715

ilk_lut_write_indexed(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1719

ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1730

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1743

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1745

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1752

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1754

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1773

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1775

ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1779

ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

1850

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1853

intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0),

sys/dev/pci/drm/i915/display/intel_color.c

1855

intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1),

sys/dev/pci/drm/i915/display/intel_color.c

1884

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

1887

intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 0),

sys/dev/pci/drm/i915/display/intel_color.c

1889

intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 1),

sys/dev/pci/drm/i915/display/intel_color.c

1912

intel_de_write_fw(display, CGM_PIPE_MODE(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_color.c

219

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

221

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

223

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

225

intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

228

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RY_GY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

230

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

233

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RU_GU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

235

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

238

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RV_GV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

240

intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

246

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

248

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

250

intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

258

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

261

csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

262

csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_PREOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

263

csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_PREOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

265

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

268

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

271

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

274

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

277

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

280

tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

286

csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

287

csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

288

csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

325

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

327

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3286

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

329

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3301

PALETTE(display, pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

331

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3313

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3328

PALETTE(display, pipe, 2 * i + 0));

sys/dev/pci/drm/i915/display/intel_color.c

3330

PALETTE(display, pipe, 2 * i + 1));

sys/dev/pci/drm/i915/display/intel_color.c

334

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

336

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BY(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3364

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3378

PALETTE(display, pipe, 2 * i + 0));

sys/dev/pci/drm/i915/display/intel_color.c

3380

PALETTE(display, pipe, 2 * i + 1));

sys/dev/pci/drm/i915/display/intel_color.c

3385

lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 0)));

sys/dev/pci/drm/i915/display/intel_color.c

3386

lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 1)));

sys/dev/pci/drm/i915/display/intel_color.c

3387

lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 2)));

sys/dev/pci/drm/i915/display/intel_color.c

339

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

341

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BU(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3416

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3429

u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));

sys/dev/pci/drm/i915/display/intel_color.c

3430

u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));

sys/dev/pci/drm/i915/display/intel_color.c

344

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3442

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3455

u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));

sys/dev/pci/drm/i915/display/intel_color.c

3456

u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));

sys/dev/pci/drm/i915/display/intel_color.c

346

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BV(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3469

crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

349

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3490

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3504

u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

351

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3516

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3529

u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));

sys/dev/pci/drm/i915/display/intel_color.c

353

intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3579

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3594

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3596

val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3601

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

361

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

364

csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3644

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

365

csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3656

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3658

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

366

csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3663

u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3668

intel_de_write_fw(display, PREC_PAL_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

368

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3709

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

371

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3726

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3728

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3733

u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

374

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3741

intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

377

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3775

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

3787

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3789

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

3794

u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3795

u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

380

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3800

intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

383

tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

386

csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

387

csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

388

csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3985

if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)

sys/dev/pci/drm/i915/display/intel_color.c

640

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

642

intel_de_write_fw(display, PIPE_WGC_C01_C00(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

644

intel_de_write_fw(display, PIPE_WGC_C02(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

647

intel_de_write_fw(display, PIPE_WGC_C11_C10(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

649

intel_de_write_fw(display, PIPE_WGC_C12(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

652

intel_de_write_fw(display, PIPE_WGC_C21_C20(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

654

intel_de_write_fw(display, PIPE_WGC_C22(display, pipe),

sys/dev/pci/drm/i915/display/intel_color.c

662

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

665

tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

669

tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

672

tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

676

tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

679

tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

683

tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));

sys/dev/pci/drm/i915/display/intel_color.c

742

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

744

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF01(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

746

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF23(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

748

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF45(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

750

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF67(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

752

intel_de_write_fw(display, CGM_PIPE_CSC_COEFF8(pipe),

sys/dev/pci/drm/i915/display/intel_color.c

760

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_color.c

763

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

767

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

771

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

775

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));

sys/dev/pci/drm/i915/display/intel_color.c

779

tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));

sys/dev/pci/drm/i915/display/intel_color_regs.h

120

#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)

sys/dev/pci/drm/i915/display/intel_color_regs.h

121

#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)

sys/dev/pci/drm/i915/display/intel_color_regs.h

122

#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)

sys/dev/pci/drm/i915/display/intel_color_regs.h

123

#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)

sys/dev/pci/drm/i915/display/intel_color_regs.h

124

#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)

sys/dev/pci/drm/i915/display/intel_color_regs.h

125

#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)

sys/dev/pci/drm/i915/display/intel_color_regs.h

126

#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)

sys/dev/pci/drm/i915/display/intel_color_regs.h

127

#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)

sys/dev/pci/drm/i915/display/intel_color_regs.h

128

#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)

sys/dev/pci/drm/i915/display/intel_color_regs.h

129

#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)

sys/dev/pci/drm/i915/display/intel_color_regs.h

130

#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)

sys/dev/pci/drm/i915/display/intel_color_regs.h

131

#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)

sys/dev/pci/drm/i915/display/intel_color_regs.h

132

#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)

sys/dev/pci/drm/i915/display/intel_color_regs.h

161

#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\

sys/dev/pci/drm/i915/display/intel_color_regs.h

164

#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

167

#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

170

#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

173

#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

176

#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

179

#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

182

#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

185

#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

188

#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

191

#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

194

#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

220

#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)

sys/dev/pci/drm/i915/display/intel_color_regs.h

221

#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)

sys/dev/pci/drm/i915/display/intel_color_regs.h

222

#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

223

#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

224

#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

236

#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)

sys/dev/pci/drm/i915/display/intel_color_regs.h

237

#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)

sys/dev/pci/drm/i915/display/intel_color_regs.h

250

#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

253

#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

264

#define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)

sys/dev/pci/drm/i915/display/intel_color_regs.h

265

#define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)

sys/dev/pci/drm/i915/display/intel_color_regs.h

266

#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)

sys/dev/pci/drm/i915/display/intel_color_regs.h

267

#define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)

sys/dev/pci/drm/i915/display/intel_color_regs.h

268

#define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)

sys/dev/pci/drm/i915/display/intel_color_regs.h

269

#define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)

sys/dev/pci/drm/i915/display/intel_color_regs.h

303

#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)

sys/dev/pci/drm/i915/display/intel_color_regs.h

304

#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)

sys/dev/pci/drm/i915/display/intel_color_regs.h

305

#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)

sys/dev/pci/drm/i915/display/intel_color_regs.h

306

#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)

sys/dev/pci/drm/i915/display/intel_color_regs.h

307

#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)

sys/dev/pci/drm/i915/display/intel_color_regs.h

308

#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

309

#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

310

#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)

sys/dev/pci/drm/i915/display/intel_color_regs.h

317

#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)

sys/dev/pci/drm/i915/display/intel_color_regs.h

33

#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \

sys/dev/pci/drm/i915/display/intel_color_regs.h

34

_PICK_EVEN_2RANGES(pipe, 2, \

sys/dev/pci/drm/i915/display/intel_color_regs.h

42

#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

48

#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

65

#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_color_regs.h

69

#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */

sys/dev/pci/drm/i915/display/intel_color_regs.h

73

#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)

sys/dev/pci/drm/i915/display/intel_connector.c

201

enum pipe pipe = 0;

sys/dev/pci/drm/i915/display/intel_connector.c

204

return encoder->get_hw_state(encoder, &pipe);

sys/dev/pci/drm/i915/display/intel_connector.c

207

enum pipe intel_connector_get_pipe(struct intel_connector *connector)

sys/dev/pci/drm/i915/display/intel_connector.c

216

return to_intel_crtc(connector->base.state->crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_connector.h

25

enum pipe intel_connector_get_pipe(struct intel_connector *connector);

sys/dev/pci/drm/i915/display/intel_crt.c

100

*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val);

sys/dev/pci/drm/i915/display/intel_crt.c

102

*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/intel_crt.c

108

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_crt.c

120

ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);

sys/dev/pci/drm/i915/display/intel_crt.c

198

adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_crt.c

200

adpa |= ADPA_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_crt.c

203

intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_crt.c

306

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_crt.c

310

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_crt.c

324

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_crt.c

340

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_crt.c

695

intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_crt.c

698

enum transcoder cpu_transcoder = (enum transcoder)pipe;

sys/dev/pci/drm/i915/display/intel_crt.c

738

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));

sys/dev/pci/drm/i915/display/intel_crt.c

775

while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)

sys/dev/pci/drm/i915/display/intel_crt.c

777

while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)

sys/dev/pci/drm/i915/display/intel_crt.c

790

} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

sys/dev/pci/drm/i915/display/intel_crt.c

92

i915_reg_t adpa_reg, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_crt.c

920

to_intel_crtc(connector->state->crtc)->pipe);

sys/dev/pci/drm/i915/display/intel_crt.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_crt.h

17

i915_reg_t adpa_reg, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_crt.h

22

i915_reg_t adpa_reg, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_crt_regs.h

16

#define ADPA_PIPE_SEL(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_crt_regs.h

18

#define ADPA_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe))

sys/dev/pci/drm/i915/display/intel_crtc.c

306

int intel_crtc_init(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_crtc.c

317

crtc->pipe = pipe;

sys/dev/pci/drm/i915/display/intel_crtc.c

318

crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe];

sys/dev/pci/drm/i915/display/intel_crtc.c

321

primary = skl_universal_plane_create(display, pipe, PLANE_1);

sys/dev/pci/drm/i915/display/intel_crtc.c

323

primary = intel_primary_plane_create(display, pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

332

for_each_sprite(display, pipe, sprite) {

sys/dev/pci/drm/i915/display/intel_crtc.c

336

plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite);

sys/dev/pci/drm/i915/display/intel_crtc.c

338

plane = intel_sprite_plane_create(display, pipe, sprite);

sys/dev/pci/drm/i915/display/intel_crtc.c

346

cursor = intel_cursor_plane_create(display, pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

376

funcs, "pipe %c", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_crtc.c

391

drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);

sys/dev/pci/drm/i915/display/intel_crtc.c

413

pipe_from_crtc_id->pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_crtc.c

54

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_crtc.c

59

if (crtc->pipe == pipe)

sys/dev/pci/drm/i915/display/intel_crtc.c

606

pipe_name(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_crtc.c

661

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_crtc.c

72

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_crtc.c

738

pipe_name(pipe), crtc->debug.start_vbl_count,

sys/dev/pci/drm/i915/display/intel_crtc.c

74

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_crtc.h

13

enum pipe;

sys/dev/pci/drm/i915/display/intel_crtc.h

41

int intel_crtc_init(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_crtc.h

57

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_crtc.h

59

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

381

if (plane->pipe == crtc->pipe)

sys/dev/pci/drm/i915/display/intel_cursor.c

1003

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_cursor.c

1013

cursor->pipe = pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

1014

cursor->i9xx_plane = (enum i9xx_plane_id) pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

1016

cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);

sys/dev/pci/drm/i915/display/intel_cursor.c

1065

"cursor %c", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

1080

zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1;

sys/dev/pci/drm/i915/display/intel_cursor.c

323

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_cursor.c

337

*pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_cursor.c

395

cntl |= MCURSOR_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_cursor.c

476

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

519

if (display->platform.cherryview && pipe == PIPE_C &&

sys/dev/pci/drm/i915/display/intel_cursor.c

537

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

542

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_cursor.c

553

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

558

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);

sys/dev/pci/drm/i915/display/intel_cursor.c

560

intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

570

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

580

intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_cursor.c

583

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);

sys/dev/pci/drm/i915/display/intel_cursor.c

622

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

629

intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),

sys/dev/pci/drm/i915/display/intel_cursor.c

632

intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

638

intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

640

intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

644

intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),

sys/dev/pci/drm/i915/display/intel_cursor.c

655

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

704

intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl);

sys/dev/pci/drm/i915/display/intel_cursor.c

705

intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl);

sys/dev/pci/drm/i915/display/intel_cursor.c

706

intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);

sys/dev/pci/drm/i915/display/intel_cursor.c

707

intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);

sys/dev/pci/drm/i915/display/intel_cursor.c

713

intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);

sys/dev/pci/drm/i915/display/intel_cursor.c

714

intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);

sys/dev/pci/drm/i915/display/intel_cursor.c

726

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_cursor.c

739

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_cursor.c

744

val = intel_de_read(display, CURCNTR(display, plane->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

749

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

751

*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/intel_cursor.c

764

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

765

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

766

error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

775

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

776

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.h

16

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_cursor.h

9

enum pipe;

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

100

#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

110

#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

12

#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

28

#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

44

#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

47

#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

56

#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

59

#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

66

#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

72

#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

75

#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

80

#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

88

#define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

92

#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)

sys/dev/pci/drm/i915/display/intel_cursor_regs.h

96

#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)

sys/dev/pci/drm/i915/display/intel_ddi.c

2493

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_ddi.c

2499

dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_ddi.c

2505

if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {

sys/dev/pci/drm/i915/display/intel_ddi.c

2530

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_ddi.c

2545

intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),

sys/dev/pci/drm/i915/display/intel_ddi.c

3028

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_ddi.c

3032

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

4458

if (display->platform.haswell && crtc->pipe == PIPE_A &&

sys/dev/pci/drm/i915/display/intel_ddi.c

4743

return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);

sys/dev/pci/drm/i915/display/intel_ddi.c

514

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_ddi.c

550

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_ddi.c

552

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/intel_ddi.c

750

enum pipe pipe = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

760

if (!encoder->get_hw_state(encoder, &pipe)) {

sys/dev/pci/drm/i915/display/intel_ddi.c

768

cpu_transcoder = (enum transcoder) pipe;

sys/dev/pci/drm/i915/display/intel_ddi.c

806

enum pipe p;

sys/dev/pci/drm/i915/display/intel_ddi.c

935

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_ddi.c

945

*pipe = ffs(pipe_mask) - 1;

sys/dev/pci/drm/i915/display/intel_ddi.h

22

enum pipe;

sys/dev/pci/drm/i915/display/intel_ddi.h

59

bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_display.c

1054

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

1065

intel_async_flip_vtd_wa(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1069

skl_wa_827(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1073

icl_wa_scalerclkgating(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1077

icl_wa_cursorclkgating(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1122

if (plane->pipe == crtc->pipe &&

sys/dev/pci/drm/i915/display/intel_display.c

1139

if (plane->pipe == crtc->pipe &&

sys/dev/pci/drm/i915/display/intel_display.c

1161

plane->pipe == crtc->pipe &&

sys/dev/pci/drm/i915/display/intel_display.c

1185

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

1208

intel_async_flip_vtd_wa(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1213

skl_wa_827(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1218

icl_wa_scalerclkgating(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1223

icl_wa_cursorclkgating(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1282

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1307

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_display.c

1524

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

1539

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1540

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1553

assert_fdi_tx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

1554

assert_fdi_rx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

1588

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1589

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1605

intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_display.c

1614

intel_de_write(display, WM_LINETIME(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_display.c

1732

enum pipe hsw_workaround_pipe;

sys/dev/pci/drm/i915/display/intel_display.c

1760

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

1767

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1768

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1786

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1787

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1953

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

1960

set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1964

set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

2041

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2050

intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_display.c

2052

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_display.c

2053

intel_de_write(display, CHV_BLEND(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2055

intel_de_write(display, CHV_CANVAS(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_display.c

2060

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

2089

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2101

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

211

skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

213

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2130

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2151

chv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

2153

vlv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

2161

intel_set_cpu_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

2168

i830_enable_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

2185

(crtc->pipe == PIPE_A || display->platform.i915g);

sys/dev/pci/drm/i915/display/intel_display.c

220

icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display.c

223

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

230

icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display.c

233

intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

257

static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

2600

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2610

PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2611

PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

2643

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2727

(pipe == PIPE_B || pipe == PIPE_C))

sys/dev/pci/drm/i915/display/intel_display.c

2728

intel_de_write(display, TRANS_VTOTAL(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2812

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2817

intel_de_write(display, PIPESRC(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

2897

enum pipe primary_pipe, pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

2907

(pipe - primary_pipe) * width, 0);

sys/dev/pci/drm/i915/display/intel_display.c

2916

tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

294

return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

2998

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3023

enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3028

power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

304

return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

312

return BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3265

intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);

sys/dev/pci/drm/i915/display/intel_display.c

3273

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3330

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3340

PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

3341

PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3365

enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3370

power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

340

BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3482

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3485

power_domain = POWER_DOMAIN_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3487

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3490

*primary_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3492

*secondary_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3511

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3514

power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3516

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3522

*primary_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3524

*secondary_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3549

static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3551

primary_pipes &= GENMASK(pipe, 0);

sys/dev/pci/drm/i915/display/intel_display.c

3581

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3584

power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3586

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3592

*primary_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3594

*secondary_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

3600

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display.c

361

BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3672

if (ultrajoiner_pipes & BIT(pipe)) {

sys/dev/pci/drm/i915/display/intel_display.c

3673

*primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3687

if (uncompressed_joiner_pipes & BIT(pipe)) {

sys/dev/pci/drm/i915/display/intel_display.c

3688

*primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3702

if (bigjoiner_pipes & BIT(pipe)) {

sys/dev/pci/drm/i915/display/intel_display.c

3703

*primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3744

enum pipe trans_pipe;

sys/dev/pci/drm/i915/display/intel_display.c

377

crtc->pipe != joiner_primary_pipe(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3776

if (trans_pipe == crtc->pipe)

sys/dev/pci/drm/i915/display/intel_display.c

3781

cpu_transcoder = (enum transcoder) crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3786

enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3787

if (secondary_pipes & BIT(crtc->pipe)) {

sys/dev/pci/drm/i915/display/intel_display.c

385

crtc->pipe == joiner_primary_pipe(crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

3903

if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))

sys/dev/pci/drm/i915/display/intel_display.c

3918

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

3920

enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes);

sys/dev/pci/drm/i915/display/intel_display.c

3922

if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

3936

POWER_DOMAIN_PIPE(crtc->pipe)))

sys/dev/pci/drm/i915/display/intel_display.c

397

return BIT(crtc->pipe) | crtc_state->joiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3979

tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3986

POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {

sys/dev/pci/drm/i915/display/intel_display.c

4088

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display.c

4090

if (!encoder->get_hw_state(encoder, &pipe))

sys/dev/pci/drm/i915/display/intel_display.c

4093

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

460

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display.c

4625

crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

463

cur_state = plane->get_hw_state(plane, &pipe);

sys/dev/pci/drm/i915/display/intel_display.c

4646

crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

4647

crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];

sys/dev/pci/drm/i915/display/intel_display.c

488

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

491

drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

504

assert_pll_enabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

511

(enum pipe) cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_display.c

518

intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

5647

enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_display.c

5661

first_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

567

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

5685

enabled_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

570

drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

5705

active_pipes |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

5707

active_pipes &= ~BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

5814

pipes & BIT(crtc->pipe) &&

sys/dev/pci/drm/i915/display/intel_display.c

5835

primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))

sys/dev/pci/drm/i915/display/intel_display.c

5981

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_display.c

6046

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_display.c

6242

enum pipe *failed_pipe)

sys/dev/pci/drm/i915/display/intel_display.c

6301

*failed_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

6316

enum pipe failed_pipe;

sys/dev/pci/drm/i915/display/intel_display.c

6574

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

6577

enum pipe pch_transcoder =

sys/dev/pci/drm/i915/display/intel_display.c

6878

disable_pipes |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

6882

if ((disable_pipes & BIT(crtc->pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

6892

if ((disable_pipes & BIT(crtc->pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

6914

if ((disable_pipes & BIT(crtc->pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

6960

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

6967

entries[pipe] = old_crtc_state->wm.skl.ddb;

sys/dev/pci/drm/i915/display/intel_display.c

6968

update_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

6970

modeset_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

6984

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

6986

if ((update_pipes & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7001

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

7003

if ((update_pipes & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7007

entries, I915_MAX_PIPES, pipe))

sys/dev/pci/drm/i915/display/intel_display.c

7010

entries[pipe] = new_crtc_state->wm.skl.ddb;

sys/dev/pci/drm/i915/display/intel_display.c

7011

update_pipes &= ~BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

7037

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

7039

if ((modeset_pipes & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7059

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

7061

if ((modeset_pipes & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7076

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

7078

if ((update_pipes & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7089

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

7091

if ((update_pipes & BIT(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7096

entries, I915_MAX_PIPES, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

7098

entries[pipe] = new_crtc_state->wm.skl.ddb;

sys/dev/pci/drm/i915/display/intel_display.c

7099

update_pipes &= ~BIT(pipe);

sys/dev/pci/drm/i915/display/intel_display.c

711

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

732

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display.c

735

tmp = intel_de_read(display, PIPE_CHICKEN(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

7393

intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);

sys/dev/pci/drm/i915/display/intel_display.c

7496

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

7506

intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);

sys/dev/pci/drm/i915/display/intel_display.c

764

intel_de_write(display, PIPE_CHICKEN(pipe), tmp);

sys/dev/pci/drm/i915/display/intel_display.c

819

num_encoders, pipe_name(primary_crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8232

void i830_enable_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display.c

8234

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

8235

enum transcoder cpu_transcoder = (enum transcoder)pipe;

sys/dev/pci/drm/i915/display/intel_display.c

8252

pipe_name(pipe), clock.vco, clock.dot);

sys/dev/pci/drm/i915/display/intel_display.c

8274

intel_de_write(display, PIPESRC(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

8277

intel_de_write(display, FP0(pipe), fp);

sys/dev/pci/drm/i915/display/intel_display.c

8278

intel_de_write(display, FP1(pipe), fp);

sys/dev/pci/drm/i915/display/intel_display.c

8285

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_display.c

8287

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8290

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8298

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8302

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8303

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8307

intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8308

intel_de_posting_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8313

void i830_disable_pipe(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display.c

8315

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display.c

8318

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8331

intel_de_write(display, TRANSCONF(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_display.c

8332

intel_de_posting_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

8336

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

sys/dev/pci/drm/i915/display/intel_display.c

8337

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display.c

873

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

880

intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),

sys/dev/pci/drm/i915/display/intel_display.c

885

intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),

sys/dev/pci/drm/i915/display/intel_display.h

238

for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)

sys/dev/pci/drm/i915/display/intel_display.h

249

for_each_if((pipe_mask) & BIT(intel_crtc->pipe))

sys/dev/pci/drm/i915/display/intel_display.h

255

for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))

sys/dev/pci/drm/i915/display/intel_display.h

436

void i830_enable_pipe(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display.h

437

void i830_disable_pipe(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1239

seq_printf(m, "%c\n", pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

662

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

665

seq_printf(m, "Pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

785

pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display_device.c

1775

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_device.c

1790

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1791

display_runtime->num_scalers[pipe] = 0;

sys/dev/pci/drm/i915/display/intel_display_device.c

1793

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1794

display_runtime->num_scalers[pipe] = 2;

sys/dev/pci/drm/i915/display/intel_display_device.c

1802

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1803

display_runtime->num_sprites[pipe] = 4;

sys/dev/pci/drm/i915/display/intel_display_device.c

1805

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1806

display_runtime->num_sprites[pipe] = 6;

sys/dev/pci/drm/i915/display/intel_display_device.c

1808

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1809

display_runtime->num_sprites[pipe] = 3;

sys/dev/pci/drm/i915/display/intel_display_device.c

1824

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1825

display_runtime->num_sprites[pipe] = 2;

sys/dev/pci/drm/i915/display/intel_display_device.c

1827

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1828

display_runtime->num_sprites[pipe] = 1;

sys/dev/pci/drm/i915/display/intel_display_device.c

1920

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_device.c

1921

if (display_runtime->num_scalers[pipe])

sys/dev/pci/drm/i915/display/intel_display_device.c

1922

display_runtime->num_scalers[pipe] = 1;

sys/dev/pci/drm/i915/display/intel_display_driver.c

175

plane->pipe);

sys/dev/pci/drm/i915/display/intel_display_driver.c

479

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_driver.c

497

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

498

ret = intel_crtc_init(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

103

enum pipe pipe, u32 fault_errors)

sys/dev/pci/drm/i915/display/intel_display_irq.c

105

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

121

intel_handle_vblank(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

123

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1252

enum pipe pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1285

pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1288

pipe = PIPE_B;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1291

pipe = PIPE_C;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1298

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1344

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1422

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1425

if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

1428

iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1432

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1436

intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1439

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1442

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1446

intel_dsb_irq_handler(display, pipe, INTEL_DSB_0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1449

intel_dsb_irq_handler(display, pipe, INTEL_DSB_1);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1452

intel_dsb_irq_handler(display, pipe, INTEL_DSB_2);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1456

intel_pipedmc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1459

hsw_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1462

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1468

pipe, fault_errors);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1583

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1587

i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1596

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1600

i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1625

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1629

i915_enable_pipestat(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1639

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1643

i915_disable_pipestat(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

1651

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1654

DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1672

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1675

DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1718

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1728

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1744

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1751

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1758

static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1760

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1823

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1825

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

1828

fault_errors = dpinvgtt & vlv_dpinvgtt_pipe_fault_mask(pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1831

pipe, fault_errors);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1945

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1962

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1963

i915_enable_pipestat(display, pipe, pipestat_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2004

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2012

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2014

POWER_DOMAIN_PIPE(pipe)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2015

intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2026

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

205

enum pipe pipe, u32 interrupt_mask,

sys/dev/pci/drm/i915/display/intel_display_irq.c

2057

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2059

POWER_DOMAIN_PIPE(pipe)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2060

intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

2080

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2089

for_each_pipe_masked(display, pipe, pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2090

intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

2091

display->irq.de_irq_mask[pipe],

sys/dev/pci/drm/i915/display/intel_display_irq.c

2092

~display->irq.de_irq_mask[pipe] | extra_ier);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2101

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2110

for_each_pipe_masked(display, pipe, pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2111

intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

218

new_val = display->irq.de_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

222

if (new_val != display->irq.de_irq_mask[pipe]) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

223

display->irq.de_irq_mask[pipe] = new_val;

sys/dev/pci/drm/i915/display/intel_display_irq.c

224

intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2240

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

225

intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

230

enum pipe pipe, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2307

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

2308

display->irq.de_irq_mask[pipe] = ~de_pipe_masked;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2311

POWER_DOMAIN_PIPE(pipe)))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2312

intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

2313

display->irq.de_irq_mask[pipe],

sys/dev/pci/drm/i915/display/intel_display_irq.c

232

bdw_update_pipe_irq(display, pipe, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

236

enum pipe pipe, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

238

bdw_update_pipe_irq(display, pipe, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

279

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

281

u32 status_mask = display->irq.pipestat_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

317

pipe_name(pipe), enable_mask, status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

323

enum pipe pipe, u32 status_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

326

i915_reg_t reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

331

pipe_name(pipe), status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

336

if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

339

display->irq.pipestat_irq_mask[pipe] |= status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

340

enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

347

enum pipe pipe, u32 status_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

350

i915_reg_t reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

355

pipe_name(pipe), status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.c

360

if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0)

sys/dev/pci/drm/i915/display/intel_display_irq.c

363

display->irq.pipestat_irq_mask[pipe] &= ~status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

364

enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

402

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

407

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

437

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

444

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

446

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

460

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

462

display_pipe_crc_irq_handler(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

463

intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

468

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

470

display_pipe_crc_irq_handler(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

471

intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

472

intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

473

intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

474

intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

475

intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

479

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

484

res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

489

res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

493

display_pipe_crc_irq_handler(display, pipe,

sys/dev/pci/drm/i915/display/intel_display_irq.c

494

intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

495

intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

496

intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

502

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

504

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

506

PIPESTAT(display, pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

509

display->irq.pipestat_irq_mask[pipe] = 0;

sys/dev/pci/drm/i915/display/intel_display_irq.c

516

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

526

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

541

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

554

status_mask |= display->irq.pipestat_irq_mask[pipe];

sys/dev/pci/drm/i915/display/intel_display_irq.c

559

reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

560

pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

561

enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

572

if (pipe_stats[pipe]) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

573

intel_de_write(display, reg, pipe_stats[pipe]);

sys/dev/pci/drm/i915/display/intel_display_irq.c

584

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

586

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

587

if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

588

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

590

if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

593

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

594

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

596

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

597

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

608

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

610

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

611

if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

612

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

614

if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

617

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

618

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

620

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

621

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

634

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

636

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

637

if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

638

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

640

if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)

sys/dev/pci/drm/i915/display/intel_display_irq.c

641

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

643

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

644

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

646

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_display_irq.c

647

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

656

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

684

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

686

pipe_name(pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

687

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

704

static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

706

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

740

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

751

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

754

if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

755

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

757

if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

759

ivb_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

761

hsw_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

764

fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

767

pipe, fault_errors);

sys/dev/pci/drm/i915/display/intel_display_irq.c

776

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

781

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

782

if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

783

intel_pch_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

790

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

815

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

817

pipe_name(pipe),

sys/dev/pci/drm/i915/display/intel_display_irq.c

818

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

825

static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_display_irq.c

827

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

853

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

865

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

868

fault_errors = gtt_fault & ilk_gtt_fault_pipe_fault_mask(pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

871

pipe, fault_errors);

sys/dev/pci/drm/i915/display/intel_display_irq.c

877

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

895

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

896

if (de_iir & DE_PIPE_VBLANK(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

897

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

899

if (de_iir & DE_PLANE_FLIP_DONE(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

900

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

902

if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

903

intel_cpu_fifo_underrun_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

905

if (de_iir & DE_PIPE_CRC_DONE(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

906

i9xx_pipe_crc_irq_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

928

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.c

956

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_irq.c

957

if (de_iir & DE_PIPE_VBLANK_IVB(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

958

intel_handle_vblank(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.c

960

if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))

sys/dev/pci/drm/i915/display/intel_display_irq.c

961

flip_done_handler(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.h

13

enum pipe;

sys/dev/pci/drm/i915/display/intel_display_irq.h

28

void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

29

void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

72

u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display_irq.h

73

void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

74

void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

1211

pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display_power.h

120

#define POWER_DOMAIN_PIPE(pipe) \

sys/dev/pci/drm/i915/display/intel_display_power.h

121

((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A))

sys/dev/pci/drm/i915/display/intel_display_power.h

122

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

sys/dev/pci/drm/i915/display/intel_display_power.h

123

((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1235

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1245

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1246

u32 val = intel_de_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1249

if (pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1252

intel_de_write(display, DPLL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1341

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1343

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1344

assert_pll_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1689

enum pipe pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1695

state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1700

drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1701

state != DP_SSS_PWR_GATE(pipe));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1702

enabled = state == DP_SSS_PWR_ON(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1708

ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1720

enum pipe pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1725

state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1730

if ((ctrl & DP_SSS_MASK(pipe)) == state)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1733

ctrl &= ~DP_SSC_MASK(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1734

ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1738

(ctrl & DP_SSS_MASK(pipe)) == state,

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

18

#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

25

#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

32

#define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

33

#define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

39

#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

45

#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1049

#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

11

#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1104

#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1124

#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1137

#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1150

#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1159

#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1168

#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1183

#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1192

#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1200

#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1209

#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

123

#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1230

#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1234

#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1235

#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1236

#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1237

#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))

sys/dev/pci/drm/i915/display/intel_display_regs.h

124

(pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1278

#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1279

GEN8_DE_PIPE_IER(pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1280

GEN8_DE_PIPE_IIR(pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1556

#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\

sys/dev/pci/drm/i915/display/intel_display_regs.h

1678

#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1809

#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1810

#define TRANS_DPLLA_SEL(pipe) 0

sys/dev/pci/drm/i915/display/intel_display_regs.h

1811

#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1816

#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1822

#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1828

#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1834

#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1840

#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1846

#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1852

#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1856

#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1860

#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1864

#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1868

#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1872

#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1876

#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1880

#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1884

#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1889

#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1893

#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1897

#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1906

#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1914

#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1922

#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

1992

#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2016

#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

223

#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \

sys/dev/pci/drm/i915/display/intel_display_regs.h

224

(pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2367

#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2380

#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2511

#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2514

#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2516

#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)

sys/dev/pci/drm/i915/display/intel_display_regs.h

269

#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

270

#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2819

#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2844

#define PIPE_FRMTMSTMP(pipe) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2845

_MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2850

#define PIPE_FLIPTMSTMP(pipe) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2851

_MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2856

#define PIPE_FLIPDONETIMSTMP(pipe) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2857

_MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2860

#define VLV_PIPE_MSA_MISC(__display, pipe) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2861

_MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2919

#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

332

#define CLKGATE_DIS_PSL(pipe) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

333

_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

339

#define CLKGATE_DIS_PSL_EXT(pipe) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

340

_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

396

#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)

sys/dev/pci/drm/i915/display/intel_display_regs.h

527

#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/pci/drm/i915/display/intel_display_regs.h

569

#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)

sys/dev/pci/drm/i915/display/intel_display_regs.h

574

#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)

sys/dev/pci/drm/i915/display/intel_display_regs.h

637

#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

639

#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

642

#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))

sys/dev/pci/drm/i915/display/intel_display_regs.h

695

#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)

sys/dev/pci/drm/i915/display/intel_display_regs.h

704

#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)

sys/dev/pci/drm/i915/display/intel_display_regs.h

718

#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)

sys/dev/pci/drm/i915/display/intel_display_regs.h

722

#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)

sys/dev/pci/drm/i915/display/intel_display_regs.h

726

#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)

sys/dev/pci/drm/i915/display/intel_display_regs.h

791

#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)

sys/dev/pci/drm/i915/display/intel_display_regs.h

842

#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)

sys/dev/pci/drm/i915/display/intel_display_regs.h

847

#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

878

#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

920

#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */

sys/dev/pci/drm/i915/display/intel_display_regs.h

938

#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)

sys/dev/pci/drm/i915/display/intel_display_regs.h

943

#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)

sys/dev/pci/drm/i915/display/intel_display_regs.h

951

#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)

sys/dev/pci/drm/i915/display/intel_display_regs.h

954

#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)

sys/dev/pci/drm/i915/display/intel_display_regs.h

958

#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)

sys/dev/pci/drm/i915/display/intel_display_regs.h

965

#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)

sys/dev/pci/drm/i915/display/intel_display_types.h

1183

enum pipe hsw_workaround_pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

1395

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

1487

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

1537

bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_display_types.h

1619

enum pipe vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

1632

enum pipe vlv_active_pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

1661

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

1940

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_display_types.h

222

bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_display_types.h

303

int (*setup)(struct intel_connector *connector, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_display_types.h

304

u32 (*get)(struct intel_connector *connector, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

1672

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dmc.c

1674

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

1678

tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));

sys/dev/pci/drm/i915/display/intel_dmc.c

1679

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);

sys/dev/pci/drm/i915/display/intel_dmc.c

1709

int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;

sys/dev/pci/drm/i915/display/intel_dmc.c

1719

enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

1728

enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

1737

enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

253

#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))

sys/dev/pci/drm/i915/display/intel_dmc.c

465

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dmc.c

475

for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)

sys/dev/pci/drm/i915/display/intel_dmc.c

476

intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),

sys/dev/pci/drm/i915/display/intel_dmc.c

479

for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)

sys/dev/pci/drm/i915/display/intel_dmc.c

480

intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),

sys/dev/pci/drm/i915/display/intel_dmc.c

696

static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dmc.c

704

return pipe >= PIPE_C;

sys/dev/pci/drm/i915/display/intel_dmc.c

737

return pipe >= PIPE_C;

sys/dev/pci/drm/i915/display/intel_dmc.c

761

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dmc.c

762

enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

774

else if (need_pipedmc_load_mmio(display, pipe))

sys/dev/pci/drm/i915/display/intel_dmc.c

780

intel_flipq_reset(display, pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

782

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

783

intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

787

intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));

sys/dev/pci/drm/i915/display/intel_dmc.c

789

intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);

sys/dev/pci/drm/i915/display/intel_dmc.c

796

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dmc.c

797

enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

803

intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_dmc.c

805

intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_dmc.c

808

intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);

sys/dev/pci/drm/i915/display/intel_dmc.c

809

intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));

sys/dev/pci/drm/i915/display/intel_dmc.c

811

intel_flipq_reset(display, pipe);

sys/dev/pci/drm/i915/display/intel_dmc.c

849

void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dmc.c

852

intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe),

sys/dev/pci/drm/i915/display/intel_dmc.c

868

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

870

enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);

sys/dev/pci/drm/i915/display/intel_dmc.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_dmc.h

25

void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dmc.h

28

enum pipe pipe, bool enable);

sys/dev/pci/drm/i915/display/intel_dmc.h

41

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dmc.h

49

void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

282

#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

288

#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

292

#define PIPEDMC_LOAD_HTP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

296

#define PIPEDMC_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_CTL_A, _PIPEDMC_CTL_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

303

#define PIPEDMC_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

314

#define PIPEDMC_FQ_CTRL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

321

#define PIPEDMC_FQ_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

328

#define PIPEDMC_FPQ_ATOMIC_TP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

342

#define PIPEDMC_FPQ_LINES_TO_W1 _MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

346

#define PIPEDMC_FPQ_LINES_TO_W2 _MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

350

#define PIPEDMC_SCANLINECMP(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

356

#define PIPEDMC_SCANLINECMPLOWER(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

364

#define PIPEDMC_SCANLINECMPUPPER(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

368

#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

372

_PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

373

_PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

374

_PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

375

_PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

387

#define PIPEDMC_FPQ_HP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

403

#define PIPEDMC_FPQ_TP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

419

#define PIPEDMC_FPQ_CHP(pipe, fq_id) _MMIO_PIPEDMC_FPQ((pipe), (fq_id), \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

427

#define PIPEDMC_FPQ_TS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

431

#define PIPEDMC_SCANLINE_RO(pipe) _MMIO_PIPE((pipe), _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

435

#define PIPEDMC_FPQ_CTL1(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

440

#define PIPEDMC_FPQ_CTL2(pipe) _MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

446

#define PIPEDMC_INTERRUPT(pipe) _MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

449

#define PIPEDMC_INTERRUPT_MASK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_MASK_A, _PIPEDMC_INTERRUPT_MASK_B)

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

457

#define PIPEDMC_BLOCK_PKGC_SW(pipe) _MMIO_PIPE(pipe, \

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

542

#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

544

#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

546

#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dmc_regs.h

548

#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe) REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_dp.c

2225

return pipe_bpp >= limits->pipe.min_bpp &&

sys/dev/pci/drm/i915/display/intel_dp.c

2226

pipe_bpp <= limits->pipe.max_bpp;

sys/dev/pci/drm/i915/display/intel_dp.c

2284

if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp)

sys/dev/pci/drm/i915/display/intel_dp.c

2315

int max_bpc = limits->pipe.max_bpp / 3;

sys/dev/pci/drm/i915/display/intel_dp.c

2482

fxp_q4_from_int(limits->pipe.max_bpp));

sys/dev/pci/drm/i915/display/intel_dp.c

2487

if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))

sys/dev/pci/drm/i915/display/intel_dp.c

2490

limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);

sys/dev/pci/drm/i915/display/intel_dp.c

2503

limits->pipe.max_bpp / 3);

sys/dev/pci/drm/i915/display/intel_dp.c

2520

limits->pipe.max_bpp,

sys/dev/pci/drm/i915/display/intel_dp.c

2535

limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);

sys/dev/pci/drm/i915/display/intel_dp.c

2536

limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);

sys/dev/pci/drm/i915/display/intel_dp.c

2538

if (limits->pipe.min_bpp <= 0 ||

sys/dev/pci/drm/i915/display/intel_dp.c

2539

limits->pipe.min_bpp > limits->pipe.max_bpp) {

sys/dev/pci/drm/i915/display/intel_dp.c

2544

orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp);

sys/dev/pci/drm/i915/display/intel_dp.c

2573

limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);

sys/dev/pci/drm/i915/display/intel_dp.c

2583

limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);

sys/dev/pci/drm/i915/display/intel_dp.c

2585

limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,

sys/dev/pci/drm/i915/display/intel_dp.c

2591

limits->pipe.max_bpp >= 30)

sys/dev/pci/drm/i915/display/intel_dp.c

2592

limits->pipe.min_bpp = max(limits->pipe.min_bpp, 30);

sys/dev/pci/drm/i915/display/intel_dp.c

2597

limits->pipe.min_bpp, limits->pipe.max_bpp,

sys/dev/pci/drm/i915/display/intel_dp.c

2680

pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dp.c

5319

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dp.c

5330

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_dp.c

5331

encoder = &intel_dp->mst.stream_encoders[pipe]->base;

sys/dev/pci/drm/i915/display/intel_dp.c

5393

*pipe_mask |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dp.c

6557

enum pipe pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_dp.c

6560

pipe = vlv_pps_backlight_initial_pipe(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

6562

intel_backlight_setup(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp.h

12

enum pipe;

sys/dev/pci/drm/i915/display/intel_dp.h

32

} pipe;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

175

intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

192

u32 pwm_level = panel->backlight.pwm_funcs->get(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

396

intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

410

ret = panel->backlight.pwm_funcs->setup(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

434

panel->backlight.level = intel_dp_aux_hdr_get_backlight(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

441

static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

519

static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

549

ret = panel->backlight.pwm_funcs->setup(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

586

panel->backlight.pwm_funcs->get(connector, pipe);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

805

enum pipe pipe = (enum pipe)cpu_transcoder;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

824

if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1355

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1358

*pipe = intel_mst->pipe;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1571

return &intel_dp->mst.stream_encoders[crtc->pipe]->base.base;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1621

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1626

return encoder->get_hw_state(encoder, &pipe);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1727

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1752

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1754

&intel_dp->mst.stream_encoders[pipe]->base.base;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1796

mst_stream_encoder_create(struct intel_digital_port *dig_port, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1808

intel_mst->pipe = pipe;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1813

DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1854

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1856

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1857

intel_dp->mst.stream_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

472

max_bpp = limits->pipe.max_bpp;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

473

min_bpp = limits->pipe.min_bpp;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

662

pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

808

mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

835

fec_pipe_mask |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dp_test.c

228

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dp_test.c

234

intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);

sys/dev/pci/drm/i915/display/intel_dp_test.c

242

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

248

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

254

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

266

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

268

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

270

intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val);

sys/dev/pci/drm/i915/display/intel_dp_test.c

271

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

284

intel_de_write(display, DDI_DP_COMP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_dp_test.c

296

intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0);

sys/dev/pci/drm/i915/display/intel_dp_test.c

41

limits->pipe.min_bpp = bpp;

sys/dev/pci/drm/i915/display/intel_dp_test.c

42

limits->pipe.max_bpp = bpp;

sys/dev/pci/drm/i915/display/intel_dp_test.c

443

*pipe_mask |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

142

crtc->pipe,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

342

pipe_mask |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

366

return state->inherited_dp_tunnels->ref[crtc->pipe].tunnel;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

390

drm_dp_tunnel_ref_get(tunnel, &state->inherited_dp_tunnels->ref[crtc->pipe]);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

447

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

452

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

453

if (state->inherited_dp_tunnels->ref[pipe].tunnel)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

454

drm_dp_tunnel_ref_put(&state->inherited_dp_tunnels->ref[pipe]);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

604

crtc->pipe,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

608

crtc->pipe, required_rate);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

639

crtc->pipe, 0);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1042

enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1048

if (pipe != PIPE_B) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1137

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1144

if (pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

687

enum dpio_phy vlv_pipe_to_phy(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

689

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

691

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

701

enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

703

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

705

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

875

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

884

if (ch == DPIO_CH0 && pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

896

if (pipe != PIPE_B) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

917

if (pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

926

if (pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

939

if (pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

122

static inline enum dpio_phy vlv_pipe_to_phy(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

126

static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

47

enum dpio_phy vlv_pipe_to_phy(enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

48

enum dpio_channel vlv_pipe_to_channel(enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1429

if (crtc->pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

1455

if (crtc->pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

1827

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

1834

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1836

intel_de_write(display, FP0(pipe), hw_state->fp0);

sys/dev/pci/drm/i915/display/intel_dpll.c

1837

intel_de_write(display, FP1(pipe), hw_state->fp1);

sys/dev/pci/drm/i915/display/intel_dpll.c

1844

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

1846

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1849

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

1853

intel_de_write(display, DPLL_MD(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

1861

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1866

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1867

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

1906

enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1907

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

1908

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

1916

if (pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_dpll.c

1959

if (pipe == PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

1965

if (pipe == PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

1987

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

1989

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1990

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

1993

if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

sys/dev/pci/drm/i915/display/intel_dpll.c

1994

drm_err(display->drm, "DPLL %d failed to lock\n", pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2002

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

2007

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2010

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

2018

intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md);

sys/dev/pci/drm/i915/display/intel_dpll.c

2019

intel_de_posting_read(display, DPLL_MD(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2027

enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2028

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2116

enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2117

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2118

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

2136

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

2139

if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1))

sys/dev/pci/drm/i915/display/intel_dpll.c

2140

drm_err(display->drm, "PLL %d failed to lock\n", pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2148

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

2153

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2156

intel_de_write(display, DPLL(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

2164

if (pipe != PIPE_A) {

sys/dev/pci/drm/i915/display/intel_dpll.c

2171

intel_de_write(display, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2175

display->state.chv_dpll_md[pipe] = hw_state->dpll_md;

sys/dev/pci/drm/i915/display/intel_dpll.c

2185

intel_de_write(display, DPLL_MD(display, pipe),

sys/dev/pci/drm/i915/display/intel_dpll.c

2187

intel_de_posting_read(display, DPLL_MD(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2201

int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dpll.c

2204

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2211

crtc_state->cpu_transcoder = (enum transcoder)pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

2229

void vlv_disable_pll(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2234

assert_transcoder_disabled(display, (enum transcoder)pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2238

if (pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

2241

intel_de_write(display, DPLL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_dpll.c

2242

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2245

void chv_disable_pll(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2247

enum dpio_channel ch = vlv_pipe_to_channel(pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2248

enum dpio_phy phy = vlv_pipe_to_phy(pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2252

assert_transcoder_disabled(display, (enum transcoder)pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2256

if (pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

2259

intel_de_write(display, DPLL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_dpll.c

2260

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2276

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

2285

intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);

sys/dev/pci/drm/i915/display/intel_dpll.c

2286

intel_de_posting_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

2298

void vlv_force_pll_off(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2301

chv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2303

vlv_disable_pll(display, pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

2308

enum pipe pipe, bool state)

sys/dev/pci/drm/i915/display/intel_dpll.c

2312

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_dpll.c

2318

void assert_pll_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2320

assert_pll(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_dpll.c

2323

void assert_pll_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_dpll.c

2325

assert_pll(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_dpll.c

400

if (display->platform.cherryview && crtc->pipe != PIPE_A)

sys/dev/pci/drm/i915/display/intel_dpll.c

401

tmp = display->state.chv_dpll_md[crtc->pipe];

sys/dev/pci/drm/i915/display/intel_dpll.c

404

DPLL_MD(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

409

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

412

hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

413

hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

477

enum pipe lvds_pipe;

sys/dev/pci/drm/i915/display/intel_dpll.c

481

lvds_pipe == crtc->pipe) {

sys/dev/pci/drm/i915/display/intel_dpll.c

519

enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

520

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

547

enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.c

548

enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_dpll.h

31

int vlv_force_pll_on(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dpll.h

33

void vlv_force_pll_off(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

36

void chv_disable_pll(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

38

void vlv_disable_pll(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

49

void assert_pll_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll.h

50

void assert_pll_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

429

drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

431

dpll_state->pipe_mask |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4664

pipe_mask = BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4669

pll->info->name, pipe_name(crtc->pipe), pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4673

pll->info->name, pipe_name(crtc->pipe), pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

468

drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

470

dpll_state->pipe_mask &= ~BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4708

u8 pipe_mask = BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4713

pll->info->name, pipe_name(crtc->pipe), pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4720

pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

622

id = (enum intel_dpll_id) crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpt_common.c

17

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dpt_common.c

24

intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_drrs.c

138

frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_drrs.c

142

frontbuffer_bits |= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dsb.c

239

static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_dsb.c

242

return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;

sys/dev/pci/drm/i915/display/intel_dsb.c

404

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dsb.c

406

intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

414

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dsb.c

416

intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

518

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dsb.c

520

intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask);

sys/dev/pci/drm/i915/display/intel_dsb.c

521

intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

751

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dsb.c

759

intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

762

intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

765

intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

773

intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

777

intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

780

intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

783

intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

793

intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

804

intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

840

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dsb.c

845

if (is_dsb_busy(display, pipe, dsb->id)) {

sys/dev/pci/drm/i915/display/intel_dsb.c

851

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

854

intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

857

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

861

intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

863

intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

866

intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

874

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dsb.c

878

ret = poll_timeout_us(is_busy = is_dsb_busy(display, pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

884

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

890

intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,

sys/dev/pci/drm/i915/display/intel_dsb.c

891

intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset,

sys/dev/pci/drm/i915/display/intel_dsb.c

892

intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset);

sys/dev/pci/drm/i915/display/intel_dsb.c

903

intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

905

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),

sys/dev/pci/drm/i915/display/intel_dsb.c

987

enum pipe pipe, enum intel_dsb_id dsb_id)

sys/dev/pci/drm/i915/display/intel_dsb.c

989

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_dsb.c

992

tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));

sys/dev/pci/drm/i915/display/intel_dsb.c

993

intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp);

sys/dev/pci/drm/i915/display/intel_dsb.h

19

enum pipe;

sys/dev/pci/drm/i915/display/intel_dsb.h

75

enum pipe pipe, enum intel_dsb_id dsb_id);

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

13

#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

14

(pipe) * 0x1000 + (id) * 0x100)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

15

#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

16

#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

17

#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

25

#define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

31

#define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

37

#define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

38

#define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

39

#define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

53

#define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

66

#define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

67

#define DSB_RM_TIMEOUT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

74

#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

75

#define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

79

#define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

84

#define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

85

#define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

86

#define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)

sys/dev/pci/drm/i915/display/intel_dsb_regs.h

87

#define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

164

enum pipe unused)

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

47

static u32 dcs_get_backlight(struct intel_connector *connector, enum pipe unused)

sys/dev/pci/drm/i915/display/intel_dvo.c

148

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_dvo.c

156

*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dvo.c

296

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_dvo.c

306

dvo_val |= DVO_PIPE_SEL(pipe);

sys/dev/pci/drm/i915/display/intel_dvo.c

423

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_dvo.c

460

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/intel_dvo.c

461

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

sys/dev/pci/drm/i915/display/intel_dvo.c

467

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_dvo.c

468

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

sys/dev/pci/drm/i915/display/intel_dvo_regs.h

17

#define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_fbc.c

1411

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1676

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1734

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1913

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1935

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1968

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

1004

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

1008

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

101

enum pipe pipe, bool state)

sys/dev/pci/drm/i915/display/intel_fdi.c

1020

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

1033

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

1036

intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1039

intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1040

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

1044

intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1045

intel_de_posting_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

105

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

1052

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

1057

intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

1058

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

1060

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

1063

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

1071

intel_de_write(display, FDI_RX_CHICKEN(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

1075

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

1078

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

1089

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

111

void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

113

assert_fdi_rx_pll(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

116

void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

118

assert_fdi_rx_pll(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

185

static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_fdi.c

187

enum pipe *pipe_to_reduce)

sys/dev/pci/drm/i915/display/intel_fdi.c

193

*pipe_to_reduce = pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

197

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/pci/drm/i915/display/intel_fdi.c

201

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/pci/drm/i915/display/intel_fdi.c

220

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_fdi.c

236

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/pci/drm/i915/display/intel_fdi.c

244

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/pci/drm/i915/display/intel_fdi.c

264

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

30

enum pipe pipe, bool state)

sys/dev/pci/drm/i915/display/intel_fdi.c

333

enum pipe pipe_to_reduce;

sys/dev/pci/drm/i915/display/intel_fdi.c

336

ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,

sys/dev/pci/drm/i915/display/intel_fdi.c

41

enum transcoder cpu_transcoder = (enum transcoder)pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

419

switch (crtc->pipe) {

sys/dev/pci/drm/i915/display/intel_fdi.c

434

MISSING_CASE(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

441

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

446

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

45

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

457

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

482

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

490

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

491

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

498

reg = FDI_RX_IMR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

507

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

515

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

52

void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

525

intel_de_write(display, FDI_RX_CHICKEN(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

527

intel_de_write(display, FDI_RX_CHICKEN(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

530

reg = FDI_RX_IIR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

54

assert_fdi_tx(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

545

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

547

intel_de_rmw(display, FDI_RX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

549

intel_de_posting_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

552

reg = FDI_RX_IIR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

57

void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

583

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

59

assert_fdi_tx(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

591

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

592

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

596

reg = FDI_RX_IMR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

606

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

617

intel_de_write(display, FDI_RX_MISC(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

620

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

63

enum pipe pipe, bool state)

sys/dev/pci/drm/i915/display/intel_fdi.c

635

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

637

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

641

reg = FDI_RX_IIR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

660

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

67

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

671

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

686

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

688

intel_de_posting_read(display, FDI_TX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

692

reg = FDI_RX_IIR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

718

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.c

728

intel_de_write(display, FDI_RX_TUSIZE1(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

729

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

73

void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

733

reg = FDI_RX_IMR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

743

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_fdi.c

748

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

75

assert_fdi_rx(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

754

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

762

reg = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

772

intel_de_write(display, FDI_RX_MISC(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

775

reg = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

78

void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

785

reg = FDI_RX_IIR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

80

assert_fdi_rx(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_fdi.c

807

intel_de_rmw(display, FDI_TX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

810

intel_de_rmw(display, FDI_RX_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_fdi.c

813

intel_de_posting_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_fdi.c

817

reg = FDI_RX_IIR(pipe);

sys/dev/pci/drm/i915/display/intel_fdi.c

83

void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fdi.c

95

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

999

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fdi.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_fdi.h

40

void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

41

void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

42

void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

43

void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

44

void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

45

void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi.h

46

void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

119

#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

125

#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

126

#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

145

#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

146

#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

28

#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

33

#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)

sys/dev/pci/drm/i915/display/intel_fdi_regs.h

83

#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

105

enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

109

trace_intel_cpu_fifo_underrun(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

110

drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

114

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

117

i915_reg_t reg = PIPESTAT(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

122

u32 enable_mask = i915_pipestat_enable_mask(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

130

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

135

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

137

u32 bit = (pipe == PIPE_A) ?

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

149

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

154

if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

157

intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

160

trace_intel_cpu_fifo_underrun(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

161

drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

165

enum pipe pipe, bool enable,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

170

ERR_INT_FIFO_UNDERRUN(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

180

intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

183

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

189

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

192

bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

194

bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

198

enum pipe pch_transcoder,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

213

enum pipe pch_transcoder = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

231

enum pipe pch_transcoder,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

255

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

257

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

266

i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

268

ilk_set_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

270

ivb_set_fifo_underrun_reporting(display, pipe, enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

272

bdw_set_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

294

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

300

ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

321

enum pipe pch_transcoder,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

365

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

367

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

378

if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

379

trace_intel_cpu_fifo_underrun(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

381

drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

397

enum pipe pch_transcoder)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

475

if (intel_has_pch_trancoder(display, crtc->pipe))

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

63

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

67

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

68

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

79

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

84

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

85

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

97

i915_reg_t reg = PIPESTAT(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

18

enum pipe pipe, bool enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

20

enum pipe pch_transcoder,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

23

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

25

enum pipe pch_transcoder);

sys/dev/pci/drm/i915/display/intel_flipq.c

162

intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

167

PIPEDMC_FQ_STATUS(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

178

return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));

sys/dev/pci/drm/i915/display/intel_flipq.c

185

intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

197

intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);

sys/dev/pci/drm/i915/display/intel_flipq.c

229

intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),

sys/dev/pci/drm/i915/display/intel_flipq.c

230

intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));

sys/dev/pci/drm/i915/display/intel_flipq.c

240

intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));

sys/dev/pci/drm/i915/display/intel_flipq.c

242

tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_flipq.c

254

void intel_flipq_reset(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_flipq.c

256

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_flipq.c

259

intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

261

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

262

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

267

intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

268

intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

273

intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

302

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

304

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_flipq.c

310

intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);

sys/dev/pci/drm/i915/display/intel_flipq.c

320

intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

324

intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

325

intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.c

433

pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_flipq.c

471

intel_dsb_reg_write(dsb, PIPEDMC_CTL(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_flipq.h

13

enum pipe;

sys/dev/pci/drm/i915/display/intel_flipq.h

21

void intel_flipq_reset(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

63

#define INTEL_FRONTBUFFER(pipe, plane_id) \

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

64

BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

65

#define INTEL_FRONTBUFFER_OVERLAY(pipe) \

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

66

BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

67

#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

68

GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

69

INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))

sys/dev/pci/drm/i915/display/intel_hdcp_regs.h

238

#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \

sys/dev/pci/drm/i915/display/intel_hdmi.c

1019

reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1021

reg = TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1059

i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1117

i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1166

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1509

PIPEDSL(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

288

i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

303

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

309

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

329

intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

333

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

340

enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_hdmi.c

341

i915_reg_t reg = TVIDEO_DIP_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

363

i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

381

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

387

intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

407

intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

411

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

418

enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_hdmi.c

419

u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

437

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

453

VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);

sys/dev/pci/drm/i915/display/intel_hdmi.c

459

VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_hdmi.c

479

intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_hdmi.c

484

VLV_TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

491

enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_hdmi.c

492

u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

994

reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_hdmi.c

996

reg = TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_link_bw.c

106

enum pipe max_bpp_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_link_bw.c

114

if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))

sys/dev/pci/drm/i915/display/intel_link_bw.c

139

max_bpp_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_link_bw.c

217

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_link_bw.c

221

if (pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_link_bw.c

224

if (new_limits->max_bpp_x16[pipe] ==

sys/dev/pci/drm/i915/display/intel_link_bw.c

225

old_limits->max_bpp_x16[pipe])

sys/dev/pci/drm/i915/display/intel_link_bw.c

229

new_limits->bpp_limit_reached_pipes & BIT(pipe)))

sys/dev/pci/drm/i915/display/intel_link_bw.c

232

new_limits->max_bpp_x16[pipe] =

sys/dev/pci/drm/i915/display/intel_link_bw.c

233

old_limits->max_bpp_x16[pipe];

sys/dev/pci/drm/i915/display/intel_link_bw.c

234

new_limits->bpp_limit_reached_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_link_bw.c

266

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_link_bw.c

274

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_link_bw.c

277

new_limits->max_bpp_x16[pipe] >

sys/dev/pci/drm/i915/display/intel_link_bw.c

278

old_limits->max_bpp_x16[pipe]))

sys/dev/pci/drm/i915/display/intel_link_bw.c

281

if (new_limits->max_bpp_x16[pipe] <

sys/dev/pci/drm/i915/display/intel_link_bw.c

282

old_limits->max_bpp_x16[pipe])

sys/dev/pci/drm/i915/display/intel_link_bw.c

56

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_link_bw.c

60

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/intel_link_bw.c

61

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_link_bw.c

67

limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;

sys/dev/pci/drm/i915/display/intel_link_bw.c

69

limits->force_fec_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_link_bw.c

71

limits->max_bpp_x16[pipe] = INT_MAX;

sys/dev/pci/drm/i915/display/intel_link_bw.c

75

limits->max_bpp_x16[pipe] = min(limits->max_bpp_x16[pipe], forced_bpp_x16);

sys/dev/pci/drm/i915/display/intel_link_bw.h

34

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

127

pdata->port[0].pipe = -1;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

128

pdata->port[1].pipe = -1;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

129

pdata->port[2].pipe = -1;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

372

ppdata->pipe = cpu_transcoder;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

381

ppdata->pipe = -1;

sys/dev/pci/drm/i915/display/intel_lvds.c

104

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_lvds.c

115

ret = intel_lvds_port_enabled(display, lvds_encoder->reg, pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

247

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_lvds.c

251

assert_fdi_rx_pll_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

254

assert_pll_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

264

temp |= LVDS_PIPE_SEL_CPT(pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

267

temp |= LVDS_PIPE_SEL(pipe);

sys/dev/pci/drm/i915/display/intel_lvds.c

430

if (DISPLAY_VER(display) < 4 && crtc->pipe == 0) {

sys/dev/pci/drm/i915/display/intel_lvds.c

88

i915_reg_t lvds_reg, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_lvds.c

96

*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

98

*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.h

13

enum pipe;

sys/dev/pci/drm/i915/display/intel_lvds.h

18

i915_reg_t lvds_reg, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_lvds.h

24

i915_reg_t lvds_reg, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

20

#define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_lvds_regs.h

22

#define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe))

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

164

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

181

intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

205

pipes |= BIT(temp_crtc->pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

226

*master_pipe_mask = BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

381

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

383

if (!plane->get_hw_state(plane, &pipe))

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

386

if (pipe == crtc->pipe)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

393

plane_crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

49

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

595

pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

666

enum pipe pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

669

visible = plane->get_hw_state(plane, &pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

671

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

679

str_enabled_disabled(visible), pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

694

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

726

pipe = 0;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

728

if (encoder->get_hw_state(encoder, &pipe)) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

729

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

75

BIT(pipe) |

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

769

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

867

intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

122

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

154

active = encoder->get_hw_state(encoder, &pipe);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

157

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

200

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

203

active = encoder->get_hw_state(encoder, &pipe);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

209

INTEL_DISPLAY_STATE_WARN(display, active && primary_crtc->pipe != pipe,

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

211

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_overlay.c

295

enum pipe pipe = overlay->crtc->pipe;

sys/dev/pci/drm/i915/display/intel_overlay.c

304

INTEL_FRONTBUFFER_OVERLAY(pipe));

sys/dev/pci/drm/i915/display/intel_overlay.c

310

intel_frontbuffer_flip_prepare(display, INTEL_FRONTBUFFER_OVERLAY(pipe));

sys/dev/pci/drm/i915/display/intel_overlay.c

368

intel_frontbuffer_flip_complete(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));

sys/dev/pci/drm/i915/display/intel_overlay.c

804

enum pipe pipe = overlay->crtc->pipe;

sys/dev/pci/drm/i915/display/intel_overlay.c

838

oconfig |= pipe == 0 ?

sys/dev/pci/drm/i915/display/intel_pch_display.c

100

assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB);

sys/dev/pci/drm/i915/display/intel_pch_display.c

101

assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC);

sys/dev/pci/drm/i915/display/intel_pch_display.c

102

assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID);

sys/dev/pci/drm/i915/display/intel_pch_display.c

106

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_pch_display.c

111

val = intel_de_read(display, PCH_TRANSCONF(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

115

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

183

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

186

PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

187

PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

194

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

197

PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

198

PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

205

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

208

PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

209

PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

216

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

219

PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

220

PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

224

enum pipe pch_transcoder)

sys/dev/pci/drm/i915/display/intel_pch_display.c

250

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

258

assert_fdi_tx_enabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

259

assert_fdi_rx_enabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

26

enum pipe pch_transcoder)

sys/dev/pci/drm/i915/display/intel_pch_display.c

262

reg = TRANS_CHICKEN2(pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

275

reg = PCH_TRANSCONF(pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

277

pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

310

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

316

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

32

enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_pch_display.c

320

assert_fdi_tx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

321

assert_fdi_rx_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

324

assert_pch_ports_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

326

reg = PCH_TRANSCONF(pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

331

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

335

intel_de_rmw(display, TRANS_CHICKEN2(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

367

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

370

assert_pch_transcoder_disabled(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

383

temp |= TRANS_DPLL_ENABLE(pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

384

sel = TRANS_DPLLB_SEL(pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

39

return crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

405

assert_pps_unlocked(display, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

410

ilk_pch_transcoder_set_timings(crtc_state, pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

419

u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))

sys/dev/pci/drm/i915/display/intel_pch_display.c

421

i915_reg_t reg = TRANS_DP_CTL(pipe);

sys/dev/pci/drm/i915/display/intel_pch_display.c

43

enum pipe pipe, enum port port,

sys/dev/pci/drm/i915/display/intel_pch_display.c

459

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

46

enum pipe port_pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

465

intel_de_rmw(display, TRANS_DP_CTL(pipe),

sys/dev/pci/drm/i915/display/intel_pch_display.c

471

TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pch_display.c

501

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

506

if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_display.c

51

INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

511

tmp = intel_de_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

523

pll_id = (enum intel_dpll_id) pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

526

if (tmp & TRANS_DPLLB_SEL(pipe))

sys/dev/pci/drm/i915/display/intel_pch_display.c

53

port_name(port), pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

554

assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder);

sys/dev/pci/drm/i915/display/intel_pch_display.c

62

enum pipe pipe, enum port port,

sys/dev/pci/drm/i915/display/intel_pch_display.c

65

enum pipe port_pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

70

INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

72

port_name(port), pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

81

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_pch_display.c

83

enum pipe port_pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.c

85

assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B);

sys/dev/pci/drm/i915/display/intel_pch_display.c

86

assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C);

sys/dev/pci/drm/i915/display/intel_pch_display.c

87

assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D);

sys/dev/pci/drm/i915/display/intel_pch_display.c

90

intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

92

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

95

intel_lvds_port_enabled(display, PCH_LVDS, &port_pipe) && port_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pch_display.c

97

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_pch_display.h

20

enum pipe pch_transcoder);

sys/dev/pci/drm/i915/display/intel_pch_display.h

21

enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);

sys/dev/pci/drm/i915/display/intel_pch_display.h

47

enum pipe pch_transcoder)

sys/dev/pci/drm/i915/display/intel_pfit.c

528

pfit_control |= PFIT_PIPE(crtc->pipe) | PFIT_FILTER_FUZZY;

sys/dev/pci/drm/i915/display/intel_pfit.c

576

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pfit.c

590

intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |

sys/dev/pci/drm/i915/display/intel_pfit.c

591

PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

593

intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE |

sys/dev/pci/drm/i915/display/intel_pfit.c

595

intel_de_write_fw(display, PF_WIN_POS(pipe),

sys/dev/pci/drm/i915/display/intel_pfit.c

597

intel_de_write_fw(display, PF_WIN_SZ(pipe),

sys/dev/pci/drm/i915/display/intel_pfit.c

605

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pfit.c

614

intel_de_write_fw(display, PF_CTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

615

intel_de_write_fw(display, PF_WIN_POS(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

616

intel_de_write_fw(display, PF_WIN_SZ(pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

624

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_pfit.c

626

ctl = intel_de_read(display, PF_CTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

631

pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);

sys/dev/pci/drm/i915/display/intel_pfit.c

633

pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pfit.c

637

pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

638

size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

651

drm_WARN_ON(display->drm, pipe != crtc->pipe);

sys/dev/pci/drm/i915/display/intel_pfit.c

679

intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_pfit.c

709

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_pfit.c

721

pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_pfit.c

723

pipe = PIPE_B;

sys/dev/pci/drm/i915/display/intel_pfit.c

725

if (pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_pfit.c

90

max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

13

#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

45

#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

48

#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

57

#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

65

#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

73

#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)

sys/dev/pci/drm/i915/display/intel_pfit_regs.h

77

#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

129

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

136

i9xx_pipe_crc_auto_source(display, pipe, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

176

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

196

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

201

i9xx_pipe_crc_auto_source(display, pipe, source);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

233

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

237

switch (pipe) {

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

315

pipe_config->hw.active && crtc->pipe == PIPE_A &&

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

337

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

365

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

408

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

414

return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

416

return vlv_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

420

return ivb_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

422

return skl_pipe_crc_ctl_reg(display, pipe, source, val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

589

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

600

power_domain = POWER_DOMAIN_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

612

ret = get_new_crc_ctl_reg(display, pipe, &source, &val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

617

intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

618

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

622

vlv_undo_pipe_scramble_reset(display, pipe);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

640

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

646

if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

652

intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

653

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

661

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

668

intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

669

intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

79

enum pipe pipe,

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

95

if (crtc->pipe != pipe)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

102

#define PIPE_CRC_EXP_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_3_A_IVB, _PIPE_CRC_EXP_3_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

108

#define PIPE_CRC_EXP_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

114

#define PIPE_CRC_EXP_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

12

#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

120

#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

125

#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

130

#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

135

#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

140

#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

145

#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

150

#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

63

#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

67

#define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

71

#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

75

#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

79

#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

82

#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

85

#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

88

#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

91

#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)

sys/dev/pci/drm/i915/display/intel_pipe_crc_regs.h

96

#define PIPE_CRC_EXP_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)

sys/dev/pci/drm/i915/display/intel_plane.c

1543

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_plane.c

1556

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_plane.c

1643

if ((joined_pipes & BIT(plane->pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_plane.c

341

intel_cdclk_min_cdclk(cdclk_state, crtc->pipe))

sys/dev/pci/drm/i915/display/intel_plane.c

349

intel_cdclk_min_cdclk(cdclk_state, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_plane.c

757

struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/intel_plane.c

815

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_plane.c

911

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_plane.c

969

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_plane_initial.c

312

&plane_configs[crtc->pipe];

sys/dev/pci/drm/i915/display/intel_plane_initial.c

410

&plane_configs[crtc->pipe];

sys/dev/pci/drm/i915/display/intel_plane_initial.c

46

if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) {

sys/dev/pci/drm/i915/display/intel_pmdemand.c

172

enum pipe pipe, int port_clock)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

177

pmdemand_state->ddi_clocks[pipe] = port_clock;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

192

crtc->pipe,

sys/dev/pci/drm/i915/display/intel_pmdemand.h

11

enum pipe;

sys/dev/pci/drm/i915/display/intel_pmdemand.h

28

enum pipe pipe, int port_clock);

sys/dev/pci/drm/i915/display/intel_pps.c

101

enum dpio_phy phy = vlv_pipe_to_phy(pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

102

enum dpio_channel ch = vlv_pipe_to_channel(pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1173

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1174

i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1178

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

sys/dev/pci/drm/i915/display/intel_pps.c

1203

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_pps.c

1212

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pps.c

1214

pipe_name(pipe), encoder->base.base.id,

sys/dev/pci/drm/i915/display/intel_pps.c

1217

if (intel_dp->pps.vlv_pps_pipe != pipe)

sys/dev/pci/drm/i915/display/intel_pps.c

1222

pipe_name(pipe), encoder->base.base.id,

sys/dev/pci/drm/i915/display/intel_pps.c

1230

static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_pps.c

1234

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1237

encoder->port, &pipe))

sys/dev/pci/drm/i915/display/intel_pps.c

1238

return pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1259

enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_pps.c

126

DP |= DP_PIPE_SEL_CHV(pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1261

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1268

pipe = vlv_active_pipe(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1270

if (pipe != PIPE_A && pipe != PIPE_B)

sys/dev/pci/drm/i915/display/intel_pps.c

1271

pipe = intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1273

if (pipe != PIPE_A && pipe != PIPE_B)

sys/dev/pci/drm/i915/display/intel_pps.c

1274

pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_pps.c

1276

return pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

128

DP |= DP_PIPE_SEL(pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1292

intel_dp->pps.vlv_pps_pipe != crtc->pipe) {

sys/dev/pci/drm/i915/display/intel_pps.c

130

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_pps.c

1305

vlv_steal_power_sequencer(display, crtc->pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1307

intel_dp->pps.vlv_active_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1313

intel_dp->pps.vlv_pps_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

140

if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) {

sys/dev/pci/drm/i915/display/intel_pps.c

143

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pps.c

164

vlv_force_pll_off(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

171

static enum pipe vlv_find_free_pps(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_pps.c

1840

void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_pps.c

1844

enum pipe panel_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_pps.c

1876

pp_reg = PP_CONTROL(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

1877

panel_pipe = pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1895

INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,

sys/dev/pci/drm/i915/display/intel_pps.c

1897

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_pps.c

206

static enum pipe

sys/dev/pci/drm/i915/display/intel_pps.c

211

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

224

pipe = vlv_find_free_pps(display);

sys/dev/pci/drm/i915/display/intel_pps.c

230

if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))

sys/dev/pci/drm/i915/display/intel_pps.c

231

pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_pps.c

233

vlv_steal_power_sequencer(display, pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

234

intel_dp->pps.vlv_pps_pipe = pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

28

enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

296

static enum pipe

sys/dev/pci/drm/i915/display/intel_pps.c

300

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

302

for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {

sys/dev/pci/drm/i915/display/intel_pps.c

304

PP_ON_DELAYS(display, pipe)) &

sys/dev/pci/drm/i915/display/intel_pps.c

310

if (!check(display, pipe))

sys/dev/pci/drm/i915/display/intel_pps.c

313

return pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

99

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.h

13

enum pipe;

sys/dev/pci/drm/i915/display/intel_pps.h

50

enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.h

63

void assert_pps_unlocked(struct intel_display *display, enum pipe pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

1198

enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_psr.c

1202

return pipe <= PIPE_B && port <= PORT_B;

sys/dev/pci/drm/i915/display/intel_psr.c

1204

return pipe == PIPE_A && port == PORT_A;

sys/dev/pci/drm/i915/display/intel_psr.c

1627

if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&

sys/dev/pci/drm/i915/display/intel_psr.c

1628

to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)

sys/dev/pci/drm/i915/display/intel_psr.c

1732

active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;

sys/dev/pci/drm/i915/display/intel_psr.c

1737

~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

1831

enum pipe pipe = intel_dp->psr.pipe;

sys/dev/pci/drm/i915/display/intel_psr.c

1846

0, LATENCY_REPORTING_REMOVED(pipe));

sys/dev/pci/drm/i915/display/intel_psr.c

1849

LATENCY_REPORTING_REMOVED(pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

1970

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

sys/dev/pci/drm/i915/display/intel_psr.c

2017

intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_psr.c

2111

intel_dp->psr.pipe,

sys/dev/pci/drm/i915/display/intel_psr.c

2170

LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

2203

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);

sys/dev/pci/drm/i915/display/intel_psr.c

2365

CURSURFLIVE(display, crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

2459

intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

2492

intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),

sys/dev/pci/drm/i915/display/intel_psr.c

2822

pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_psr.c

2947

intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0);

sys/dev/pci/drm/i915/display/intel_psr.c

3404

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

3434

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))

sys/dev/pci/drm/i915/display/intel_psr.c

3511

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

3824

intel_dp->psr.pipe,

sys/dev/pci/drm/i915/display/intel_psr.c

3910

active_non_psr_pipes |= BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

3912

active_non_psr_pipes &= ~BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

901

struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);

sys/dev/pci/drm/i915/display/intel_psr.c

944

intel_dp->psr.pipe,

sys/dev/pci/drm/i915/display/intel_psr_regs.h

267

#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1635

sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1637

sdvox |= SDVO_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1668

i915_reg_t sdvo_reg, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1676

*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1678

*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1680

*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1686

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1695

ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1859

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_sdvo.h

13

enum pipe;

sys/dev/pci/drm/i915/display/intel_sdvo.h

19

i915_reg_t sdvo_reg, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_sdvo.h

24

i915_reg_t sdvo_reg, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_sprite.c

1085

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1098

intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),

sys/dev/pci/drm/i915/display/intel_sprite.c

1115

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1127

intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),

sys/dev/pci/drm/i915/display/intel_sprite.c

1130

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

1131

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

1132

intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

1143

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1157

intel_de_write_fw(display, DVSSTRIDE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1159

intel_de_write_fw(display, DVSPOS(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1161

intel_de_write_fw(display, DVSSIZE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1163

intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);

sys/dev/pci/drm/i915/display/intel_sprite.c

1173

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1182

intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

1183

intel_de_write_fw(display, DVSKEYMSK(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1185

intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

1188

intel_de_write_fw(display, DVSLINOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1190

intel_de_write_fw(display, DVSTILEOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

1198

intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);

sys/dev/pci/drm/i915/display/intel_sprite.c

1199

intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);

sys/dev/pci/drm/i915/display/intel_sprite.c

1213

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1215

intel_de_write_fw(display, DVSCNTR(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

1217

intel_de_write_fw(display, DVSSCALE(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

1218

intel_de_write_fw(display, DVSSURF(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

1227

error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1228

error->surf = intel_de_read(display, DVSSURF(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1229

error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1234

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_sprite.c

1241

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_sprite.c

1246

ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

1248

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

145

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1594

enum pipe pipe, int sprite)

sys/dev/pci/drm/i915/display/intel_sprite.c

1624

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1687

if (display->platform.cherryview && pipe == PIPE_B) {

sys/dev/pci/drm/i915/display/intel_sprite.c

1696

plane->pipe = pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1698

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);

sys/dev/pci/drm/i915/display/intel_sprite.c

1706

"sprite %c", sprite_name(display, pipe, sprite));

sys/dev/pci/drm/i915/display/intel_sprite.c

172

intel_de_write_fw(display, SPCLRC0(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

174

intel_de_write_fw(display, SPCLRC1(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

347

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

361

intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),

sys/dev/pci/drm/i915/display/intel_sprite.c

372

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

379

intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

381

intel_de_write_fw(display, SPPOS(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

383

intel_de_write_fw(display, SPSIZE(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

394

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

403

if (display->platform.cherryview && pipe == PIPE_B)

sys/dev/pci/drm/i915/display/intel_sprite.c

407

intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

409

intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

411

intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

415

intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

417

intel_de_write_fw(display, SPLINOFF(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

419

intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),

sys/dev/pci/drm/i915/display/intel_sprite.c

427

intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);

sys/dev/pci/drm/i915/display/intel_sprite.c

428

intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);

sys/dev/pci/drm/i915/display/intel_sprite.c

440

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

443

intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

444

intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

453

error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

454

error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

455

error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

460

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_sprite.c

468

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

475

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

52

static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)

sys/dev/pci/drm/i915/display/intel_sprite.c

54

return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';

sys/dev/pci/drm/i915/display/intel_sprite.c

763

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

774

intel_de_write_fw(display, SPRGAMC(pipe, i),

sys/dev/pci/drm/i915/display/intel_sprite.c

777

intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

778

intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

779

intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

782

intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

783

intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

784

intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);

sys/dev/pci/drm/i915/display/intel_sprite.c

795

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

809

intel_de_write_fw(display, SPRSTRIDE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

811

intel_de_write_fw(display, SPRPOS(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

813

intel_de_write_fw(display, SPRSIZE(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

816

intel_de_write_fw(display, SPRSCALE(pipe), sprscale);

sys/dev/pci/drm/i915/display/intel_sprite.c

826

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

835

intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

836

intel_de_write_fw(display, SPRKEYMSK(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

838

intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);

sys/dev/pci/drm/i915/display/intel_sprite.c

844

intel_de_write_fw(display, SPROFFSET(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

847

intel_de_write_fw(display, SPRLINOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

849

intel_de_write_fw(display, SPRTILEOFF(pipe),

sys/dev/pci/drm/i915/display/intel_sprite.c

858

intel_de_write_fw(display, SPRCTL(pipe), sprctl);

sys/dev/pci/drm/i915/display/intel_sprite.c

859

intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);

sys/dev/pci/drm/i915/display/intel_sprite.c

870

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

872

intel_de_write_fw(display, SPRCTL(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

875

intel_de_write_fw(display, SPRSCALE(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

876

intel_de_write_fw(display, SPRSURF(pipe), 0);

sys/dev/pci/drm/i915/display/intel_sprite.c

885

error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

886

error->surf = intel_de_read(display, SPRSURF(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

887

error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

892

enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_sprite.c

899

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

906

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.h

14

enum pipe;

sys/dev/pci/drm/i915/display/intel_sprite.h

18

enum pipe pipe, int plane);

sys/dev/pci/drm/i915/display/intel_sprite.h

30

int pipe, int plane)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

109

#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

113

#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

118

#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

12

#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

147

#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

151

#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

155

#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

163

#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

171

#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

175

#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

179

#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

184

#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

188

#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

196

#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

200

#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

204

#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

219

#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

223

#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

227

#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

230

#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

231

_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

232

#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

233

_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

237

#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

266

#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

270

#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

274

#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

282

#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

290

#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

294

#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

298

#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

303

#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

307

#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

315

#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

322

#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

326

#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

334

#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

342

#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

37

#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

41

#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

45

#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

53

#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

61

#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

65

#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

69

#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

74

#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

78

#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

86

#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

90

#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */

sys/dev/pci/drm/i915/display/intel_sprite_regs.h

94

#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

104

to_intel_plane(plane)->pipe);

sys/dev/pci/drm/i915/display/intel_tv.c

1481

tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_tv.c

1607

tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_tv.c

916

intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)

sys/dev/pci/drm/i915/display/intel_tv.c

921

*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;

sys/dev/pci/drm/i915/display/intel_tv_regs.h

18

# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/pci/drm/i915/display/intel_vblank.c

111

frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),

sys/dev/pci/drm/i915/display/intel_vblank.c

112

PIPEFRAME(display, pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

129

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_vblank.c

134

return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

159

PIPE_FRMTMSTMP(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

168

PIPE_FRMTMSTMP(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

248

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vblank.c

259

position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

279

PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

336

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vblank.c

347

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

395

position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

sys/dev/pci/drm/i915/display/intel_vblank.c

482

enum pipe pipe)

sys/dev/pci/drm/i915/display/intel_vblank.c

484

i915_reg_t reg = PIPEDSL(display, pipe);

sys/dev/pci/drm/i915/display/intel_vblank.c

497

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vblank.c

502

ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),

sys/dev/pci/drm/i915/display/intel_vblank.c

508

pipe_name(pipe), str_on_off(state));

sys/dev/pci/drm/i915/display/intel_vblank.c

737

pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

78

enum pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/pci/drm/i915/display/intel_vdsc.c

379

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vdsc.c

393

pipe == PIPE_A)

sys/dev/pci/drm/i915/display/intel_vdsc.c

396

return POWER_DOMAIN_PIPE(pipe);

sys/dev/pci/drm/i915/display/intel_vdsc.c

421

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vdsc.c

429

dsc_reg[2] = BMG_DSC2_PPS(pipe, pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

431

dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

433

dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

460

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vdsc.c

51

drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);

sys/dev/pci/drm/i915/display/intel_vdsc.c

588

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

590

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

592

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

594

intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

598

ICL_DSC1_RC_BUF_THRESH_0(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

601

ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

604

ICL_DSC1_RC_BUF_THRESH_1(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

607

ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

662

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

665

ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

667

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

670

ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

672

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

675

ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

677

intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

680

ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

684

ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

687

ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

690

ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

693

ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

696

ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

699

ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

702

ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

705

ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),

sys/dev/pci/drm/i915/display/intel_vdsc.c

760

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_vdsc.c

771

intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

774

intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);

sys/dev/pci/drm/i915/display/intel_vdsc.c

780

ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;

sys/dev/pci/drm/i915/display/intel_vdsc.c

786

ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

203

#define LNL_DSC0_SU_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe), _LNL_DSC0_SU_PARAMETER_SET_0_PA, _LNL_DSC0_SU_PARAMETER_SET_0_PB)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

204

#define LNL_DSC1_SU_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe), _LNL_DSC1_SU_PARAMETER_SET_0_PA, _LNL_DSC1_SU_PARAMETER_SET_0_PB)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

224

#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

227

#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

230

#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

233

#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

249

#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

252

#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

255

#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

258

#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

275

#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

278

#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

281

#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

284

#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

303

#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

306

#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

309

#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

312

#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

328

#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

33

#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

331

#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

334

#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

337

#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

353

#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

356

#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

359

#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

362

#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

49

#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

66

#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

69

#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

72

#define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

75

#define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

78

#define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

81

#define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

82

#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

83

#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vga.c

49

enum pipe pipe;

sys/dev/pci/drm/i915/display/intel_vga.c

58

pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp);

sys/dev/pci/drm/i915/display/intel_vga.c

60

pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_vga.c

62

pipe = PIPE_A;

sys/dev/pci/drm/i915/display/intel_vga.c

65

pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_vga_regs.h

17

#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))

sys/dev/pci/drm/i915/display/intel_vga_regs.h

19

#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe))

sys/dev/pci/drm/i915/display/intel_wm_types.h

42

struct g4x_pipe_wm pipe[3];

sys/dev/pci/drm/i915/display/intel_wm_types.h

50

struct g4x_pipe_wm pipe[2];

sys/dev/pci/drm/i915/display/skl_scaler.c

212

crtc->pipe, scaler_user, *scaler_id,

sys/dev/pci/drm/i915/display/skl_scaler.c

234

crtc->pipe, scaler_user, src_w, src_h,

sys/dev/pci/drm/i915/display/skl_scaler.c

252

crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);

sys/dev/pci/drm/i915/display/skl_scaler.c

261

crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,

sys/dev/pci/drm/i915/display/skl_scaler.c

509

crtc->pipe, *scaler_id, name, idx);

sys/dev/pci/drm/i915/display/skl_scaler.c

541

if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))

sys/dev/pci/drm/i915/display/skl_scaler.c

688

enum pipe pipe, int id, int set)

sys/dev/pci/drm/i915/display/skl_scaler.c

693

GLK_PS_COEF_INDEX_SET(pipe, id, set),

sys/dev/pci/drm/i915/display/skl_scaler.c

707

GLK_PS_COEF_DATA_SET(pipe, id, set), tmp);

sys/dev/pci/drm/i915/display/skl_scaler.c

711

GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

727

struct intel_dsb *dsb, enum pipe pipe,

sys/dev/pci/drm/i915/display/skl_scaler.c

734

glk_program_nearest_filter_coefs(display, dsb, pipe, id, set);

sys/dev/pci/drm/i915/display/skl_scaler.c

749

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_scaler.c

786

skl_scaler_setup_filter(display, NULL, pipe, id, 0,

sys/dev/pci/drm/i915/display/skl_scaler.c

789

intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);

sys/dev/pci/drm/i915/display/skl_scaler.c

791

intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

793

intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

795

intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

797

intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),

sys/dev/pci/drm/i915/display/skl_scaler.c

809

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_scaler.c

853

skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0,

sys/dev/pci/drm/i915/display/skl_scaler.c

856

intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

858

intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

860

intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

862

intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

864

intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id),

sys/dev/pci/drm/i915/display/skl_scaler.c

875

intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

876

intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

877

intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0);

sys/dev/pci/drm/i915/display/skl_scaler.c

919

ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

926

pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

927

size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

967

SKL_PS_ECC_STAT(crtc->pipe, scaler_state->scaler_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1357

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1359

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1360

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1362

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1363

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1365

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1366

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1368

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1369

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1370

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1372

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1373

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1374

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1385

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1398

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1400

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1402

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1416

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1433

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1435

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1437

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1440

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1443

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1446

intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1451

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1469

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1471

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1482

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1498

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1513

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1518

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1529

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1550

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1552

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1554

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1557

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1559

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1561

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1564

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1568

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1570

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1576

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1580

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1583

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1607

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1613

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1627

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1650

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1652

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1662

error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1663

error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1664

error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1676

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1689

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1691

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2407

static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2409

return pipe - PIPE_A + INTEL_FBC_A;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2425

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2427

enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2436

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2442

if (DISPLAY_VER(display) == 9 && pipe == PIPE_C)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2452

enum pipe pipe, enum plane_id plane_id,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2455

if (skl_plane_has_planar(display, pipe, plane_id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2465

enum pipe pipe, enum plane_id plane_id,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2468

if (skl_plane_has_planar(display, pipe, plane_id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2478

enum pipe pipe, enum plane_id plane_id,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2687

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2690

bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2698

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2701

bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2706

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2708

return pipe != PIPE_C &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2713

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2719

if (skl_plane_has_rc_ccs(display, pipe, plane_id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2726

enum pipe pipe)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2728

return pipe != PIPE_C;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2732

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2738

if (glk_plane_has_rc_ccs(display, pipe))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2745

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2765

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2792

plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2802

intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2805

intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2807

intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2813

enum pipe pipe, enum plane_id plane_id)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2830

plane->pipe = pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2832

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2834

intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2902

formats = icl_get_plane_formats(display, pipe,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2905

formats = glk_get_plane_formats(display, pipe,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2908

formats = skl_get_plane_formats(display, pipe,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2924

caps = tgl_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2926

caps = icl_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2928

caps = glk_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2930

caps = skl_plane_caps(display, pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2945

pipe_name(pipe));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3012

enum pipe pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3020

if (!plane->get_hw_state(plane, &pipe))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3023

drm_WARN_ON(display->drm, pipe != crtc->pipe);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3042

val = intel_de_read(display, PLANE_CTL(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3052

color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3145

base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3148

offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3151

val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3155

val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3186

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3198

intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

688

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

731

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

733

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

735

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

737

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

739

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

741

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

744

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

746

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

748

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

751

PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

753

PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

755

PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

834

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

846

intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

849

intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

855

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

857

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

861

intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

865

intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

869

intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

880

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

884

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

885

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

893

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

898

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

908

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

911

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

916

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

917

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

922

enum pipe *pipe)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

930

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

935

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

937

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.h

18

enum pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.h

23

enum pipe pipe, enum plane_id plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

106

#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

11

#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

116

#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

12

_PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

128

#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

13

#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

14

(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

140

#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

148

#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

15

#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

157

#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

16

_MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

168

#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

17

#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

178

#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

18

_MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

190

#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

198

#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

20

#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

206

#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

217

#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

22

_PIPE((pipe), (reg_1_a), (reg_1_b)), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

225

#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

23

_PIPE((pipe), (reg_2_a), (reg_2_b)), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

24

_PIPE((pipe), (reg_5_a), (reg_5_b)), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

249

#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

25

_PIPE((pipe), (reg_6_a), (reg_6_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

26

#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

27

_MMIO(_SEL_FETCH((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

273

#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

281

#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

289

#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

297

#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

305

#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

313

#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

320

#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

333

#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

341

#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

349

#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

35

#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

357

#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

366

#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

374

#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

388

#define PLANE_MIN_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

406

#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

422

#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

437

#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

452

#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_watermark.c

1182

static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,

sys/dev/pci/drm/i915/display/skl_watermark.c

1190

return dbuf_slices[i].dbuf_mask[pipe];

sys/dev/pci/drm/i915/display/skl_watermark.c

1200

static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1214

return compute_dbuf_slices(pipe, active_pipes, join_mbus,

sys/dev/pci/drm/i915/display/skl_watermark.c

1218

static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1220

return compute_dbuf_slices(pipe, active_pipes, join_mbus,

sys/dev/pci/drm/i915/display/skl_watermark.c

1224

static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1226

return compute_dbuf_slices(pipe, active_pipes, join_mbus,

sys/dev/pci/drm/i915/display/skl_watermark.c

1230

static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1232

return compute_dbuf_slices(pipe, active_pipes, join_mbus,

sys/dev/pci/drm/i915/display/skl_watermark.c

1239

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

1242

return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);

sys/dev/pci/drm/i915/display/skl_watermark.c

1244

return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);

sys/dev/pci/drm/i915/display/skl_watermark.c

1246

return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);

sys/dev/pci/drm/i915/display/skl_watermark.c

1248

return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus);

sys/dev/pci/drm/i915/display/skl_watermark.c

1253

return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

1418

const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];

sys/dev/pci/drm/i915/display/skl_watermark.c

2376

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/skl_watermark.c

2499

enum pipe pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

2507

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/display/skl_watermark.c

2508

enabled_slices |= dbuf_state->slices[pipe];

sys/dev/pci/drm/i915/display/skl_watermark.c

2556

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

2558

new_dbuf_state->slices[pipe] =

sys/dev/pci/drm/i915/display/skl_watermark.c

2562

if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe])

sys/dev/pci/drm/i915/display/skl_watermark.c

2588

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

2590

new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

2592

if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe])

sys/dev/pci/drm/i915/display/skl_watermark.c

2877

display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;

sys/dev/pci/drm/i915/display/skl_watermark.c

2878

display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);

sys/dev/pci/drm/i915/display/skl_watermark.c

2883

if (display->pkgc.disable[crtc->pipe])

sys/dev/pci/drm/i915/display/skl_watermark.c

2886

max_linetime = max(display->pkgc.linetime[crtc->pipe], max_linetime);

sys/dev/pci/drm/i915/display/skl_watermark.c

3012

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

3022

val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));

sys/dev/pci/drm/i915/display/skl_watermark.c

3024

val = intel_de_read(display, CUR_WM(pipe, level));

sys/dev/pci/drm/i915/display/skl_watermark.c

3030

val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3032

val = intel_de_read(display, CUR_WM_TRANS(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3038

val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3040

val = intel_de_read(display, CUR_WM_SAGV(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3045

val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3047

val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3072

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

3081

dbuf_state->active_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3085

memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));

sys/dev/pci/drm/i915/display/skl_watermark.c

3100

skl_ddb_get_hw_plane_state(display, crtc->pipe,

sys/dev/pci/drm/i915/display/skl_watermark.c

3104

skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);

sys/dev/pci/drm/i915/display/skl_watermark.c

3105

skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);

sys/dev/pci/drm/i915/display/skl_watermark.c

3108

dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3117

crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;

sys/dev/pci/drm/i915/display/skl_watermark.c

3118

crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;

sys/dev/pci/drm/i915/display/skl_watermark.c

3121

dbuf_state->slices[pipe] =

sys/dev/pci/drm/i915/display/skl_watermark.c

3127

dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,

sys/dev/pci/drm/i915/display/skl_watermark.c

3128

dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,

sys/dev/pci/drm/i915/display/skl_watermark.c

3342

static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)

sys/dev/pci/drm/i915/display/skl_watermark.c

3344

switch (pipe) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3354

MISSING_CASE(pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3400

if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes))

sys/dev/pci/drm/i915/display/skl_watermark.c

3415

intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe),

sys/dev/pci/drm/i915/display/skl_watermark.c

3496

static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,

sys/dev/pci/drm/i915/display/skl_watermark.c

3500

enum pipe pipe = ffs(dbuf_state->active_pipes) - 1;

sys/dev/pci/drm/i915/display/skl_watermark.c

3507

crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3511

return pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

3518

enum pipe pipe)

sys/dev/pci/drm/i915/display/skl_watermark.c

3527

if (pipe != INVALID_PIPE)

sys/dev/pci/drm/i915/display/skl_watermark.c

3528

mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3538

enum pipe pipe)

sys/dev/pci/drm/i915/display/skl_watermark.c

3549

pipe != INVALID_PIPE ? pipe_name(pipe) : '*');

sys/dev/pci/drm/i915/display/skl_watermark.c

3551

mbus_ctl_join_update(display, new_dbuf_state, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3565

enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3569

intel_dbuf_mbus_join_update(state, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3587

enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3593

intel_dbuf_mbus_join_update(state, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3595

if (pipe != INVALID_PIPE) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3596

struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3722

entries[crtc->pipe] = crtc_state->wm.skl.ddb;

sys/dev/pci/drm/i915/display/skl_watermark.c

3732

if (dbuf_state->slices[crtc->pipe] & ~slices)

sys/dev/pci/drm/i915/display/skl_watermark.c

3736

I915_MAX_PIPES, crtc->pipe))

sys/dev/pci/drm/i915/display/skl_watermark.c

3792

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

3797

dbuf_state->active_pipes &= ~BIT(pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

3799

dbuf_state->weight[pipe] = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3800

dbuf_state->slices[pipe] = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3802

memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));

sys/dev/pci/drm/i915/display/skl_watermark.c

487

enum pipe for_pipe,

sys/dev/pci/drm/i915/display/skl_watermark.c

493

enum pipe pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

499

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/display/skl_watermark.c

500

int weight = dbuf_state->weight[pipe];

sys/dev/pci/drm/i915/display/skl_watermark.c

509

if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe])

sys/dev/pci/drm/i915/display/skl_watermark.c

513

if (pipe < for_pipe) {

sys/dev/pci/drm/i915/display/skl_watermark.c

516

} else if (pipe == for_pipe) {

sys/dev/pci/drm/i915/display/skl_watermark.c

533

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

540

if (new_dbuf_state->weight[pipe] == 0) {

sys/dev/pci/drm/i915/display/skl_watermark.c

541

skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

545

dbuf_slice_mask = new_dbuf_state->slices[pipe];

sys/dev/pci/drm/i915/display/skl_watermark.c

551

intel_crtc_dbuf_weights(new_dbuf_state, pipe,

sys/dev/pci/drm/i915/display/skl_watermark.c

557

skl_ddb_entry_init(&new_dbuf_state->ddb[pipe],

sys/dev/pci/drm/i915/display/skl_watermark.c

562

if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&

sys/dev/pci/drm/i915/display/skl_watermark.c

563

skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],

sys/dev/pci/drm/i915/display/skl_watermark.c

564

&new_dbuf_state->ddb[pipe]))

sys/dev/pci/drm/i915/display/skl_watermark.c

579

crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;

sys/dev/pci/drm/i915/display/skl_watermark.c

580

crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;

sys/dev/pci/drm/i915/display/skl_watermark.c

585

old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe],

sys/dev/pci/drm/i915/display/skl_watermark.c

586

old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end,

sys/dev/pci/drm/i915/display/skl_watermark.c

587

new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end,

sys/dev/pci/drm/i915/display/skl_watermark.c

671

const enum pipe pipe,

sys/dev/pci/drm/i915/display/skl_watermark.c

681

val = intel_de_read(display, CUR_BUF_CFG(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

686

val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

690

val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

699

val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

710

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/skl_watermark.c

714

power_domain = POWER_DOMAIN_PIPE(pipe);

sys/dev/pci/drm/i915/display/skl_watermark.c

720

skl_ddb_get_hw_plane_state(display, pipe,

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

13

#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \

sys/dev/pci/drm/i915/display/skl_watermark_regs.h

41

#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1315

drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1342

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1345

BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1909

enum pipe pipe;

sys/dev/pci/drm/i915/display/vlv_dsi.c

2016

intel_dsi_get_hw_state(encoder, &pipe));

sys/dev/pci/drm/i915/display/vlv_dsi.c

649

temp |= crtc->pipe ?

sys/dev/pci/drm/i915/display/vlv_dsi.c

731

enum pipe pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/vlv_dsi.c

739

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/vlv_dsi.c

935

enum pipe *pipe)

sys/dev/pci/drm/i915/display/vlv_dsi.c

995

*pipe = tmp;

sys/dev/pci/drm/i915/display/vlv_dsi.c

997

*pipe = port == PORT_A ? PIPE_A : PIPE_B;

sys/dev/pci/drm/i915/display/vlv_dsi_regs.h

421

#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

370

#define MEDIA_INSTR(pipe, op, sub_op, flags) \

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

371

(__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1269

int pipe;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1282

int pipe;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1311

info->pipe = gen8_plane_code[v].pipe;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1320

info->ctrl_reg = DSPCNTR(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1321

info->stride_reg = DSPSTRIDE(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1322

info->surf_reg = DSPSURF(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1324

info->ctrl_reg = SPRCTL(info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1325

info->stride_reg = SPRSTRIDE(info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1326

info->surf_reg = SPRSURF(info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1349

info->pipe = PIPE_A;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1353

info->pipe = PIPE_B;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1357

info->pipe = PIPE_C;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1362

info->pipe = PIPE_A;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1367

info->pipe = PIPE_B;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1372

info->pipe = PIPE_C;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1387

info->ctrl_reg = DSPCNTR(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1388

info->stride_reg = DSPSTRIDE(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1389

info->surf_reg = DSPSURF(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1444

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1449

set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);

sys/dev/pci/drm/i915/gvt/display.c

189

int pipe;

sys/dev/pci/drm/i915/gvt/display.c

201

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/gvt/display.c

202

vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=

sys/dev/pci/drm/i915/gvt/display.c

204

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

205

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

206

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

sys/dev/pci/drm/i915/gvt/display.c

207

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

sys/dev/pci/drm/i915/gvt/display.c

517

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/gvt/display.c

518

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

519

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

520

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

sys/dev/pci/drm/i915/gvt/display.c

521

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

sys/dev/pci/drm/i915/gvt/display.c

54

int pipe = -1;

sys/dev/pci/drm/i915/gvt/display.c

59

pipe = PIPE_A;

sys/dev/pci/drm/i915/gvt/display.c

62

pipe = PIPE_B;

sys/dev/pci/drm/i915/gvt/display.c

636

static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)

sys/dev/pci/drm/i915/gvt/display.c

648

if (pipe < PIPE_A || pipe > PIPE_C)

sys/dev/pci/drm/i915/gvt/display.c

65

pipe = PIPE_C;

sys/dev/pci/drm/i915/gvt/display.c

651

for_each_set_bit(event, irq->flip_done_event[pipe],

sys/dev/pci/drm/i915/gvt/display.c

653

clear_bit(event, irq->flip_done_event[pipe]);

sys/dev/pci/drm/i915/gvt/display.c

654

if (!pipe_is_enabled(vgpu, pipe))

sys/dev/pci/drm/i915/gvt/display.c

660

if (pipe_is_enabled(vgpu, pipe)) {

sys/dev/pci/drm/i915/gvt/display.c

661

vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;

sys/dev/pci/drm/i915/gvt/display.c

662

intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);

sys/dev/pci/drm/i915/gvt/display.c

670

int pipe;

sys/dev/pci/drm/i915/gvt/display.c

673

for_each_pipe(display, pipe)

sys/dev/pci/drm/i915/gvt/display.c

674

emulate_vblank_on_pipe(vgpu, pipe);

sys/dev/pci/drm/i915/gvt/display.c

68

return pipe;

sys/dev/pci/drm/i915/gvt/display.c

84

int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)

sys/dev/pci/drm/i915/gvt/display.c

90

pipe < PIPE_A || pipe >= I915_MAX_PIPES))

sys/dev/pci/drm/i915/gvt/display.c

93

if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)

sys/dev/pci/drm/i915/gvt/display.c

97

get_edp_pipe(vgpu) == pipe)

sys/dev/pci/drm/i915/gvt/display.h

167

int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

155

static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,

sys/dev/pci/drm/i915/gvt/fb_decoder.c

161

u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

218

int pipe;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

220

pipe = get_active_pipe(vgpu);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

221

if (pipe >= I915_MAX_PIPES)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

224

val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

258

plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

269

plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,

sys/dev/pci/drm/i915/gvt/fb_decoder.c

274

plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>

sys/dev/pci/drm/i915/gvt/fb_decoder.c

277

plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &

sys/dev/pci/drm/i915/gvt/fb_decoder.c

281

val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

350

int pipe;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

352

pipe = get_active_pipe(vgpu);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

353

if (pipe >= I915_MAX_PIPES)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

356

val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

382

plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

393

val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));

sys/dev/pci/drm/i915/gvt/handlers.c

1029

u32 pipe = DSPSURF_TO_PIPE(display, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1030

int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);

sys/dev/pci/drm/i915/gvt/handlers.c

1033

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1035

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

sys/dev/pci/drm/i915/gvt/handlers.c

1037

if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)

sys/dev/pci/drm/i915/gvt/handlers.c

1040

set_bit(event, vgpu->irq.flip_done_event[pipe]);

sys/dev/pci/drm/i915/gvt/handlers.c

1051

u32 pipe = SPRSURF_TO_PIPE(offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1052

int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);

sys/dev/pci/drm/i915/gvt/handlers.c

1055

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1057

if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)

sys/dev/pci/drm/i915/gvt/handlers.c

1060

set_bit(event, vgpu->irq.flip_done_event[pipe]);

sys/dev/pci/drm/i915/gvt/handlers.c

1071

enum pipe pipe = REG_50080_TO_PIPE(offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1073

int event = SKL_FLIP_EVENT(pipe, plane);

sys/dev/pci/drm/i915/gvt/handlers.c

1077

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1078

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

sys/dev/pci/drm/i915/gvt/handlers.c

1080

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1086

set_bit(event, vgpu->irq.flip_done_event[pipe]);

sys/dev/pci/drm/i915/gvt/handlers.c

851

enum pipe pipe, unsigned int train_pattern)

sys/dev/pci/drm/i915/gvt/handlers.c

858

fdi_rx_imr = FDI_RX_IMR(pipe);

sys/dev/pci/drm/i915/gvt/handlers.c

859

fdi_tx_ctl = FDI_TX_CTL(pipe);

sys/dev/pci/drm/i915/gvt/handlers.c

860

fdi_rx_ctl = FDI_RX_CTL(pipe);

sys/dev/pci/drm/i915/gvt/reg.h

58

#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)

sys/dev/pci/drm/i915/gvt/reg.h

60

#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))

sys/dev/pci/drm/i915/i915_irq.h

14

enum pipe;

sys/dev/pci/drm/i915/i915_reg.h

1021

#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)

sys/dev/pci/drm/i915/i915_reg.h

1027

#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

sys/dev/pci/drm/i915/i915_reg.h

1048

#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))

sys/dev/pci/drm/i915/i915_reg.h

1049

#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))

sys/dev/pci/drm/i915/i915_reg.h

350

#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))

sys/dev/pci/drm/i915/i915_reg.h

352

#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))

sys/dev/pci/drm/i915/i915_reg.h

766

#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))

sys/dev/pci/drm/i915/i915_reg.h

830

#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))

sys/dev/pci/drm/i915/i915_reg.h

836

#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))

sys/dev/pci/drm/i915/i915_reg.h

838

#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))

sys/dev/pci/drm/i915/i915_reg.h

870

#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))

sys/dev/pci/drm/i915/i915_reg.h

959

#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)

sys/dev/pci/drm/i915/i915_reg.h

991

#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \

sys/dev/pci/drm/i915/intel_clock_gating.c

136

enum pipe pipe;

sys/dev/pci/drm/i915/intel_clock_gating.c

138

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

139

intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),

sys/dev/pci/drm/i915/intel_clock_gating.c

142

intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),

sys/dev/pci/drm/i915/intel_clock_gating.c

145

DSPSURF(display, pipe));

sys/dev/pci/drm/i915/intel_clock_gating.c

207

enum pipe pipe;

sys/dev/pci/drm/i915/intel_clock_gating.c

222

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

223

val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));

sys/dev/pci/drm/i915/intel_clock_gating.c

230

intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);

sys/dev/pci/drm/i915/intel_clock_gating.c

233

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

234

intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),

sys/dev/pci/drm/i915/intel_clock_gating.c

430

enum pipe pipe;

sys/dev/pci/drm/i915/intel_clock_gating.c

441

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

443

intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),

sys/dev/pci/drm/i915/intel_clock_gating.c

478

enum pipe pipe;

sys/dev/pci/drm/i915/intel_clock_gating.c

486

for_each_pipe(display, pipe) {

sys/dev/pci/drm/i915/intel_clock_gating.c

488

intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

49

#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

50

#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

51

#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

52

#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

53

#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

54

#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

55

#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

56

#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

57

#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

58

#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

59

#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))

sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h

60

#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))

sys/dev/pci/drm/include/drm/drm_audio_component.h

50

int (*sync_audio_rate)(struct device *, int port, int pipe, int rate);

sys/dev/pci/drm/include/drm/drm_audio_component.h

63

int (*get_eld)(struct device *, int port, int pipe, bool *enabled,

sys/dev/pci/drm/include/drm/drm_audio_component.h

83

void (*pin_eld_notify)(void *audio_ptr, int port, int pipe);

sys/dev/pci/drm/include/drm/drm_vblank.h

201

unsigned int pipe;

sys/dev/pci/drm/include/drm/drm_vblank.h

273

bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/include/drm/drm_vblank.h

277

void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/include/drm/drm_vblank.h

50

unsigned int pipe;

sys/dev/pci/drm/include/drm/intel/intel_lpe_audio.h

37

int pipe;

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

1812

__u32 pipe;

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

887

int pipe;

sys/dev/pci/drm/radeon/cik.c

1842

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/pci/drm/radeon/cik.c

1844

u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |

sys/dev/pci/drm/radeon/cik.c

3506

ref_and_mask = CP2 << ring->pipe;

sys/dev/pci/drm/radeon/cik.c

3509

ref_and_mask = CP6 << ring->pipe;

sys/dev/pci/drm/radeon/cik.c

4148

cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/radeon/cik.c

4167

cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/radeon/cik.c

4189

cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/pci/drm/radeon/cik.c

4534

int pipe = (i < 4) ? i : (i - 4);

sys/dev/pci/drm/radeon/cik.c

4536

cik_srbm_select(rdev, me, pipe, 0, 0);

sys/dev/pci/drm/radeon/cik.c

4606

rdev->ring[idx].pipe,

sys/dev/pci/drm/radeon/cik.c

7069

switch (ring->pipe) {

sys/dev/pci/drm/radeon/cik.c

7083

DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);

sys/dev/pci/drm/radeon/cik.c

7087

switch (ring->pipe) {

sys/dev/pci/drm/radeon/cik.c

7101

DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);

sys/dev/pci/drm/radeon/cik.c

7112

switch (ring->pipe) {

sys/dev/pci/drm/radeon/cik.c

7126

DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);

sys/dev/pci/drm/radeon/cik.c

7130

switch (ring->pipe) {

sys/dev/pci/drm/radeon/cik.c

7144

DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);

sys/dev/pci/drm/radeon/cik.c

7942

if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))

sys/dev/pci/drm/radeon/cik.c

7944

if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))

sys/dev/pci/drm/radeon/cik.c

8413

ring->pipe = 0; /* first pipe */

sys/dev/pci/drm/radeon/cik.c

8425

ring->pipe = 0; /* first pipe */

sys/dev/pci/drm/radeon/cypress_dpm.c

1747

u32 tmp, pipe;

sys/dev/pci/drm/radeon/cypress_dpm.c

1764

pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;

sys/dev/pci/drm/radeon/cypress_dpm.c

1767

(!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {

sys/dev/pci/drm/radeon/cypress_dpm.c

1774

pipe = 0;

sys/dev/pci/drm/radeon/cypress_dpm.c

1776

pipe = i;

sys/dev/pci/drm/radeon/cypress_dpm.c

1779

tmp |= DCCG_DISP1_SLOW_SELECT(pipe);

sys/dev/pci/drm/radeon/radeon.h

828

u32 pipe;

sys/dev/pci/drm/radeon/radeon_audio.c

750

int pipe, bool *enabled,

sys/dev/pci/drm/radeon/radeon_display.c

1809

int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/radeon/radeon_display.c

1827

if (pipe == 0) {

sys/dev/pci/drm/radeon/radeon_display.c

1834

if (pipe == 1) {

sys/dev/pci/drm/radeon/radeon_display.c

1841

if (pipe == 2) {

sys/dev/pci/drm/radeon/radeon_display.c

1848

if (pipe == 3) {

sys/dev/pci/drm/radeon/radeon_display.c

1855

if (pipe == 4) {

sys/dev/pci/drm/radeon/radeon_display.c

1862

if (pipe == 5) {

sys/dev/pci/drm/radeon/radeon_display.c

1870

if (pipe == 0) {

sys/dev/pci/drm/radeon/radeon_display.c

1875

if (pipe == 1) {

sys/dev/pci/drm/radeon/radeon_display.c

1882

if (pipe == 0) {

sys/dev/pci/drm/radeon/radeon_display.c

1896

if (pipe == 1) {

sys/dev/pci/drm/radeon/radeon_display.c

1948

vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;

sys/dev/pci/drm/radeon/radeon_display.c

1990

unsigned int pipe = crtc->index;

sys/dev/pci/drm/radeon/radeon_display.c

1992

return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,

sys/dev/pci/drm/radeon/radeon_kms.c

763

unsigned int pipe = crtc->index;

sys/dev/pci/drm/radeon/radeon_kms.c

768

if (pipe >= rdev->num_crtc) {

sys/dev/pci/drm/radeon/radeon_kms.c

769

DRM_ERROR("Invalid crtc %u\n", pipe);

sys/dev/pci/drm/radeon/radeon_kms.c

781

if (rdev->mode_info.crtcs[pipe]) {

sys/dev/pci/drm/radeon/radeon_kms.c

786

count = radeon_get_vblank_counter(rdev, pipe);

sys/dev/pci/drm/radeon/radeon_kms.c

792

dev, pipe, GET_DISTANCE_TO_VBLANKSTART,

sys/dev/pci/drm/radeon/radeon_kms.c

794

&rdev->mode_info.crtcs[pipe]->base.hwmode);

sys/dev/pci/drm/radeon/radeon_kms.c

795

} while (count != radeon_get_vblank_counter(rdev, pipe));

sys/dev/pci/drm/radeon/radeon_kms.c

803

pipe, vpos);

sys/dev/pci/drm/radeon/radeon_kms.c

815

count = radeon_get_vblank_counter(rdev, pipe);

sys/dev/pci/drm/radeon/radeon_kms.c

833

unsigned int pipe = crtc->index;

sys/dev/pci/drm/radeon/radeon_kms.c

838

if (pipe >= rdev->num_crtc) {

sys/dev/pci/drm/radeon/radeon_kms.c

839

DRM_ERROR("Invalid crtc %d\n", pipe);

sys/dev/pci/drm/radeon/radeon_kms.c

844

rdev->irq.crtc_vblank_int[pipe] = true;

sys/dev/pci/drm/radeon/radeon_kms.c

860

unsigned int pipe = crtc->index;

sys/dev/pci/drm/radeon/radeon_kms.c

864

if (pipe >= rdev->num_crtc) {

sys/dev/pci/drm/radeon/radeon_kms.c

865

DRM_ERROR("Invalid crtc %d\n", pipe);

sys/dev/pci/drm/radeon/radeon_kms.c

870

rdev->irq.crtc_vblank_int[pipe] = false;

sys/dev/pci/drm/radeon/radeon_mode.h

838

extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/radeon/si_dpm.c

3626

u32 tmp, pipe;

sys/dev/pci/drm/radeon/si_dpm.c

3643

pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;

sys/dev/pci/drm/radeon/si_dpm.c

3646

(!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {

sys/dev/pci/drm/radeon/si_dpm.c

3653

pipe = 0;

sys/dev/pci/drm/radeon/si_dpm.c

3655

pipe = i;

sys/dev/pci/drm/radeon/si_dpm.c

3658

tmp |= DCCG_DISP1_SLOW_SELECT(pipe);

sys/dev/usb/dwc2/dwc2.c

1007

dwc2_device_isoc_close(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

1009

dwc2_close_pipe(pipe);

sys/dev/usb/dwc2/dwc2.c

1026

struct usbd_device *dev = xfer->pipe->device;

sys/dev/usb/dwc2/dwc2.c

1027

usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc;

sys/dev/usb/dwc2/dwc2.c

1040

DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->pipe);

sys/dev/usb/dwc2/dwc2.c

1150

dpipe->pipe.interval != USBD_DEFAULT_INTERVAL) {

sys/dev/usb/dwc2/dwc2.c

1151

ival = dpipe->pipe.interval;

sys/dev/usb/dwc2/dwc2.c

126

STATIC void dwc2_noop(struct usbd_pipe *pipe);

sys/dev/usb/dwc2/dwc2.c

358

dwc2_open(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

360

struct usbd_device *dev = pipe->device;

sys/dev/usb/dwc2/dwc2.c

361

struct dwc2_softc *sc = DWC2_PIPE2SC(pipe);

sys/dev/usb/dwc2/dwc2.c

362

struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe);

sys/dev/usb/dwc2/dwc2.c

363

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/dwc2/dwc2.c

368

DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype,

sys/dev/usb/dwc2/dwc2.c

378

pipe->methods = &dwc2_root_ctrl_methods;

sys/dev/usb/dwc2/dwc2.c

381

pipe->methods = &dwc2_root_intr_methods;

sys/dev/usb/dwc2/dwc2.c

394

pipe->methods = &dwc2_device_ctrl_methods;

sys/dev/usb/dwc2/dwc2.c

401

pipe->methods = &dwc2_device_intr_methods;

sys/dev/usb/dwc2/dwc2.c

404

pipe->methods = &dwc2_device_isoc_methods;

sys/dev/usb/dwc2/dwc2.c

407

pipe->methods = &dwc2_device_bulk_methods;

sys/dev/usb/dwc2/dwc2.c

433

dwc2_close_pipe(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

452

DPRINTF("xfer %p pipe %p status 0x%08x\n", xfer, xfer->pipe,

sys/dev/usb/dwc2/dwc2.c

529

dwc2_noop(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

535

dwc2_device_clear_toggle(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

537

DPRINTF("toggle %d -> 0", pipe->endpoint->savedtoggle);

sys/dev/usb/dwc2/dwc2.c

605

return dwc2_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/dwc2/dwc2.c

762

dwc2_root_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

780

return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/dwc2/dwc2.c

811

dwc2_root_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

829

return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/dwc2/dwc2.c

857

dwc2_device_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

859

struct dwc2_softc * const sc = DWC2_PIPE2SC(pipe);

sys/dev/usb/dwc2/dwc2.c

860

struct dwc2_pipe * const dpipe = DWC2_PIPE2DPIPE(pipe);

sys/dev/usb/dwc2/dwc2.c

862

dwc2_close_pipe(pipe);

sys/dev/usb/dwc2/dwc2.c

881

return dwc2_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/dwc2/dwc2.c

909

dwc2_device_bulk_close(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

911

dwc2_close_pipe(pipe);

sys/dev/usb/dwc2/dwc2.c

928

return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/dwc2/dwc2.c

952

KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer);

sys/dev/usb/dwc2/dwc2.c

958

dwc2_device_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/dwc2/dwc2.c

960

dwc2_close_pipe(pipe);

sys/dev/usb/dwc2/dwc2.c

966

if (xfer->pipe->repeat)

sys/dev/usb/dwc2/dwc2.c

979

return dwc2_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/dwc2/dwc2_hcd.c

2534

if (usb_pipeisoc(urb->pipe))

sys/dev/usb/dwc2/dwc2_hcd.c

4120

struct usbd_device *dev = dpipe->pipe.device;

sys/dev/usb/dwc2/dwc2_hcd.c

4185

struct usbd_device *dev = dpipe->pipe.device;

sys/dev/usb/dwc2/dwc2_hcd.c

4233

ed = xfer->pipe->endpoint->edesc;

sys/dev/usb/dwc2/dwc2_hcd.c

4703

usb_pipedevice(urb->pipe));

sys/dev/usb/dwc2/dwc2_hcd.c

4705

usb_pipeendpoint(urb->pipe),

sys/dev/usb/dwc2/dwc2_hcd.c

4706

usb_pipein(urb->pipe) ? "IN" : "OUT");

sys/dev/usb/dwc2/dwc2_hcd.c

4708

switch (usb_pipetype(urb->pipe)) {

sys/dev/usb/dwc2/dwc2_hcd.c

4724

usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?

sys/dev/usb/dwc2/dwc2_hcd.c

4755

if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {

sys/dev/usb/dwc2/dwc2_hcd.c

4827

if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||

sys/dev/usb/dwc2/dwc2_hcd.c

4828

usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {

sys/dev/usb/dwc2/dwc2_hcd.c

4835

switch (usb_pipetype(urb->pipe)) {

sys/dev/usb/dwc2/dwc2_hcd.c

4855

dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),

sys/dev/usb/dwc2/dwc2_hcd.c

4856

usb_pipeendpoint(urb->pipe), ep_type,

sys/dev/usb/dwc2/dwc2_hcd.c

4857

usb_pipein(urb->pipe),

sys/dev/usb/dwc2/dwc2_hcd.c

536

struct usbd_device *dev = dpipe->pipe.device;

sys/dev/usb/dwc2/dwc2_hcd.h

510

static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

512

return pipe->ep_num;

sys/dev/usb/dwc2/dwc2_hcd.h

515

static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

517

return pipe->pipe_type;

sys/dev/usb/dwc2/dwc2_hcd.h

520

static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

522

return pipe->maxp;

sys/dev/usb/dwc2/dwc2_hcd.h

525

static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

527

return pipe->maxp_mult;

sys/dev/usb/dwc2/dwc2_hcd.h

530

static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

532

return pipe->dev_addr;

sys/dev/usb/dwc2/dwc2_hcd.h

535

static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

537

return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;

sys/dev/usb/dwc2/dwc2_hcd.h

540

static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

542

return pipe->pipe_type == USB_ENDPOINT_XFER_INT;

sys/dev/usb/dwc2/dwc2_hcd.h

545

static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

547

return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;

sys/dev/usb/dwc2/dwc2_hcd.h

550

static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

552

return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;

sys/dev/usb/dwc2/dwc2_hcd.h

555

static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

557

return pipe->pipe_dir == USB_DIR_IN;

sys/dev/usb/dwc2/dwc2_hcd.h

560

static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

562

return !dwc2_hcd_is_pipe_in(pipe);

sys/dev/usb/dwc2/dwc2_hcd.h

638

return usb_pipetype(urb->pipe) == PIPE_BULK ||

sys/dev/usb/dwc2/dwc2_hcd.h

639

usb_pipetype(urb->pipe) == PIPE_CONTROL;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

2163

struct usbd_device *dev = dpipe->pipe.device;

sys/dev/usb/dwc2/dwc2var.h

52

struct usbd_pipe pipe; /* Must be first */

sys/dev/usb/dwc2/dwc2var.h

63

#define DWC2_PIPE2SC(pipe) DWC2_BUS2SC((pipe)->device->bus)

sys/dev/usb/dwc2/dwc2var.h

64

#define DWC2_XFER2SC(xfer) DWC2_PIPE2SC((xfer)->pipe)

sys/dev/usb/dwc2/dwc2var.h

65

#define DWC2_DPIPE2SC(d) DWC2_BUS2SC((d)->pipe.device->bus)

sys/dev/usb/dwc2/dwc2var.h

69

#define DWC2_XFER2DPIPE(x) (struct dwc2_pipe *)(x)->pipe;

sys/dev/usb/ehci.c

1155

ehci_device_clear_toggle(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

1157

struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;

sys/dev/usb/ehci.c

1355

ehci_open(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

1357

struct usbd_device *dev = pipe->device;

sys/dev/usb/ehci.c

1359

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/ehci.c

1362

struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;

sys/dev/usb/ehci.c

1370

pipe, addr, ed->bEndpointAddress));

sys/dev/usb/ehci.c

1384

if (pipe->device->depth == 0) {

sys/dev/usb/ehci.c

1387

pipe->methods = &ehci_root_ctrl_methods;

sys/dev/usb/ehci.c

1390

pipe->methods = &ehci_root_intr_methods;

sys/dev/usb/ehci.c

1467

htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle));

sys/dev/usb/ehci.c

1482

pipe->methods = &ehci_device_ctrl_methods;

sys/dev/usb/ehci.c

1488

pipe->methods = &ehci_device_bulk_methods;

sys/dev/usb/ehci.c

1494

pipe->methods = &ehci_device_intr_methods;

sys/dev/usb/ehci.c

1495

ival = pipe->interval;

sys/dev/usb/ehci.c

1506

pipe->methods = &ehci_device_isoc_methods;

sys/dev/usb/ehci.c

167

void ehci_device_clear_toggle(struct usbd_pipe *pipe);

sys/dev/usb/ehci.c

1790

return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ehci.c

2189

ehci_root_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

2210

return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ehci.c

2241

ehci_root_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

2361

iscontrol = UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) ==

sys/dev/usb/ehci.c

2369

mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/ehci.c

2493

struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe;

sys/dev/usb/ehci.c

2581

ehci_close_pipe(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

2583

struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;

sys/dev/usb/ehci.c

2584

struct ehci_softc *sc = (struct ehci_softc *)pipe->device->bus;

sys/dev/usb/ehci.c

2591

pipe->endpoint->savedtoggle =

sys/dev/usb/ehci.c

2610

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

2858

return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ehci.c

2865

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

2995

ehci_device_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

2997

ehci_close_pipe(pipe);

sys/dev/usb/ehci.c

3011

return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ehci.c

3018

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

3073

ehci_device_bulk_close(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

3075

ehci_close_pipe(pipe);

sys/dev/usb/ehci.c

3125

return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ehci.c

3133

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

3179

KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer);

sys/dev/usb/ehci.c

3190

ehci_device_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

3192

ehci_close_pipe(pipe);

sys/dev/usb/ehci.c

3199

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

3206

if (xfer->pipe->repeat) {

sys/dev/usb/ehci.c

3259

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

3261

usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc;

sys/dev/usb/ehci.c

3377

usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc;

sys/dev/usb/ehci.c

3480

EHCI_ITD_SET_DADDR(xfer->pipe->device->address)

sys/dev/usb/ehci.c

3505

usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc;

sys/dev/usb/ehci.c

3596

ehci_device_isoc_close(struct usbd_pipe *pipe)

sys/dev/usb/ehci.c

3604

struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;

sys/dev/usb/ehci.c

678

int attr = xfer->pipe->endpoint->edesc->bmAttributes;

sys/dev/usb/ehci.c

736

usb_rem_task(xfer->pipe->device, &xfer->abort_task);

sys/dev/usb/ehci.c

747

if (xfer != SIMPLEQ_FIRST(&xfer->pipe->queue))

sys/dev/usb/ehci.c

776

usb_rem_task(xfer->pipe->device, &xfer->abort_task);

sys/dev/usb/ehci.c

792

switch (xfer->pipe->endpoint->edesc->bInterval) {

sys/dev/usb/ehci.c

96

struct usbd_pipe pipe;

sys/dev/usb/if_bwfm_usb.c

856

if (usbd_is_dying(xfer->pipe->device))

sys/dev/usb/if_rsu.c

1443

usbd_clear_endpoint_stall_async(data->pipe);

sys/dev/usb/if_rsu.c

1470

usbd_setup_xfer(xfer, data->pipe, data, data->buf, RSU_RXBUFSZ,

sys/dev/usb/if_rsu.c

1490

usbd_clear_endpoint_stall_async(data->pipe);

sys/dev/usb/if_rsu.c

1513

struct usbd_pipe *pipe;

sys/dev/usb/if_rsu.c

1535

pipe = sc->pipe[sc->qid2idx[qid]];

sys/dev/usb/if_rsu.c

1608

data->pipe = pipe;

sys/dev/usb/if_rsu.c

1609

usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen,

sys/dev/usb/if_rsu.c

1972

struct usbd_pipe *pipe;

sys/dev/usb/if_rsu.c

1976

pipe = sc->pipe[sc->qid2idx[RSU_QID_VO]];

sys/dev/usb/if_rsu.c

1989

usbd_setup_xfer(data->xfer, pipe, NULL, data->buf,

sys/dev/usb/if_rsu.c

2245

data->pipe = sc->pipe[sc->qid2idx[RSU_QID_RXOFF]];

sys/dev/usb/if_rsu.c

2246

usbd_setup_xfer(data->xfer, data->pipe, data, data->buf,

sys/dev/usb/if_rsu.c

2339

usbd_abort_pipe(sc->pipe[i]);

sys/dev/usb/if_rsu.c

360

&sc->pipe[i]);

sys/dev/usb/if_rsu.c

379

if (sc->pipe[i] == NULL)

sys/dev/usb/if_rsu.c

381

usbd_close_pipe(sc->pipe[i]);

sys/dev/usb/if_rsu.c

699

struct usbd_pipe *pipe;

sys/dev/usb/if_rsu.c

730

pipe = sc->pipe[sc->qid2idx[RSU_QID_H2C]];

sys/dev/usb/if_rsu.c

731

usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, xferlen,

sys/dev/usb/if_rsureg.h

682

struct usbd_pipe *pipe;

sys/dev/usb/if_rsureg.h

689

struct usbd_pipe *pipe;

sys/dev/usb/if_rsureg.h

726

struct usbd_pipe *pipe[R92S_MAX_EP];

sys/dev/usb/if_urtwn.c

1433

usbd_clear_endpoint_stall_async(data->pipe);

sys/dev/usb/if_urtwn.c

148

struct usbd_pipe *pipe;

sys/dev/usb/if_urtwn.c

1641

struct usbd_pipe *pipe;

sys/dev/usb/if_urtwn.c

1670

pipe = sc->tx_pipe[sc->ac2idx[qid]];

sys/dev/usb/if_urtwn.c

1735

data->pipe = pipe;

sys/dev/usb/if_urtwn.c

1736

usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen,

sys/dev/usb/ohci.c

105

usbd_status ohci_setup_isoc(struct usbd_pipe *pipe);

sys/dev/usb/ohci.c

1304

opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

1367

opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

1369

uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc->

sys/dev/usb/ohci.c

1446

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

1454

if (xfer->pipe->repeat) {

sys/dev/usb/ohci.c

148

struct ohci_pipe *pipe, int ival);

sys/dev/usb/ohci.c

1554

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

1568

xfer->pipe->endpoint->edesc->bEndpointAddress));

sys/dev/usb/ohci.c

158

void ohci_device_clear_toggle(struct usbd_pipe *pipe);

sys/dev/usb/ohci.c

1887

ohci_open(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

1889

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

1890

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/ohci.c

1891

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

1903

pipe, pipe->device->address, ed->bEndpointAddress));

sys/dev/usb/ohci.c

1909

if (pipe->device->depth == 0) {

sys/dev/usb/ohci.c

1912

pipe->methods = &ohci_root_ctrl_methods;

sys/dev/usb/ohci.c

1915

pipe->methods = &ohci_root_intr_methods;

sys/dev/usb/ohci.c

1945

OHCI_ED_SET_FA(pipe->device->address) |

sys/dev/usb/ohci.c

1947

(pipe->device->speed == USB_SPEED_LOW ?

sys/dev/usb/ohci.c

1951

(pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0));

sys/dev/usb/ohci.c

1956

pipe->methods = &ohci_device_ctrl_methods;

sys/dev/usb/ohci.c

1968

pipe->methods = &ohci_device_intr_methods;

sys/dev/usb/ohci.c

1969

ival = pipe->interval;

sys/dev/usb/ohci.c

1974

pipe->methods = &ohci_device_isoc_methods;

sys/dev/usb/ohci.c

1975

return (ohci_setup_isoc(pipe));

sys/dev/usb/ohci.c

1977

pipe->methods = &ohci_device_bulk_methods;

sys/dev/usb/ohci.c

2036

ohci_close_pipe(struct usbd_pipe *pipe, struct ohci_soft_ed *head)

sys/dev/usb/ohci.c

2038

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

2039

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

2054

pipe, std);

sys/dev/usb/ohci.c

207

struct usbd_pipe pipe;

sys/dev/usb/ohci.c

2070

pipe->endpoint->savedtoggle =

sys/dev/usb/ohci.c

2088

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

2263

return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ohci.c

2589

ohci_root_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

2606

return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ohci.c

2637

ohci_root_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

2652

return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ohci.c

2689

ohci_device_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

2691

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

2692

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

2694

DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe));

sys/dev/usb/ohci.c

2695

ohci_close_pipe(pipe, sc->sc_ctrl_head);

sys/dev/usb/ohci.c

2702

ohci_device_clear_toggle(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

2704

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

2720

return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ohci.c

2727

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

2746

endpt = xfer->pipe->endpoint->edesc->bEndpointAddress;

sys/dev/usb/ohci.c

2827

ohci_device_bulk_close(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

2829

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

2830

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

2832

DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe));

sys/dev/usb/ohci.c

2833

ohci_close_pipe(pipe, sc->sc_bulk_head);

sys/dev/usb/ohci.c

2850

return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/ohci.c

2857

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

2879

endpt = xfer->pipe->endpoint->edesc->bEndpointAddress;

sys/dev/usb/ohci.c

2938

KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer);

sys/dev/usb/ohci.c

2945

ohci_device_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

2947

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

2948

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

2956

pipe, nslots, pos));

sys/dev/usb/ohci.c

3065

ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/ohci.c

3074

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

3216

struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;

sys/dev/usb/ohci.c

3276

ohci_setup_isoc(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

3278

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

3279

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

3294

ohci_device_isoc_close(struct usbd_pipe *pipe)

sys/dev/usb/ohci.c

3296

struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;

sys/dev/usb/ohci.c

3297

struct ohci_softc *sc = (struct ohci_softc *)pipe->device->bus;

sys/dev/usb/ohci.c

3299

DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe));

sys/dev/usb/ohci.c

3300

ohci_close_pipe(pipe, sc->sc_isoc_head);

sys/dev/usb/ohci.c

508

mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/uhci.c

1180

usb_rem_task(xfer->pipe->device, &xfer->abort_task);

sys/dev/usb/uhci.c

1189

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

1296

xfer->pipe->endpoint->edesc->bEndpointAddress,

sys/dev/usb/uhci.c

138

usbd_status uhci_setup_isoc(struct usbd_pipe *pipe);

sys/dev/usb/uhci.c

1522

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

1531

int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress;

sys/dev/usb/uhci.c

1541

mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/uhci.c

1560

if (xfer->pipe->device->speed == USB_SPEED_LOW)

sys/dev/usb/uhci.c

1595

uhci_device_clear_toggle(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

1597

struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;

sys/dev/usb/uhci.c

1615

return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/uhci.c

1622

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

1775

uhci_device_bulk_close(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

1777

struct uhci_softc *sc = (struct uhci_softc *)pipe->device->bus;

sys/dev/usb/uhci.c

1778

struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;

sys/dev/usb/uhci.c

1781

pipe->endpoint->savedtoggle = upipe->nexttoggle;

sys/dev/usb/uhci.c

1798

return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/uhci.c

1836

return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/uhci.c

1843

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

189

struct uhci_pipe *pipe, int ival);

sys/dev/usb/uhci.c

191

void uhci_device_clear_toggle(struct usbd_pipe *pipe);

sys/dev/usb/uhci.c

1920

uhci_device_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

1927

KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer);

sys/dev/usb/uhci.c

1934

uhci_device_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

1936

struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;

sys/dev/usb/uhci.c

1937

struct uhci_softc *sc = (struct uhci_softc *)pipe->device->bus;

sys/dev/usb/uhci.c

1967

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

1971

int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress;

sys/dev/usb/uhci.c

2108

uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue));

sys/dev/usb/uhci.c

2117

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

2190

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

2239

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

2283

uhci_device_isoc_close(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

2285

struct uhci_softc *sc = (struct uhci_softc *)pipe->device->bus;

sys/dev/usb/uhci.c

2286

struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;

sys/dev/usb/uhci.c

2326

uhci_setup_isoc(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

2328

struct uhci_softc *sc = (struct uhci_softc *)pipe->device->bus;

sys/dev/usb/uhci.c

2329

struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;

sys/dev/usb/uhci.c

2330

int addr = pipe->device->address;

sys/dev/usb/uhci.c

2331

int endpt = pipe->endpoint->edesc->bEndpointAddress;

sys/dev/usb/uhci.c

2409

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

2425

if (xfer->pipe->repeat) {

sys/dev/usb/uhci.c

2469

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

2498

struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;

sys/dev/usb/uhci.c

2625

uhci_open(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

2627

struct uhci_softc *sc = (struct uhci_softc *)pipe->device->bus;

sys/dev/usb/uhci.c

2628

struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;

sys/dev/usb/uhci.c

2629

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/uhci.c

2634

pipe, pipe->device->address, ed->bEndpointAddress));

sys/dev/usb/uhci.c

2636

upipe->nexttoggle = pipe->endpoint->savedtoggle;

sys/dev/usb/uhci.c

2639

if (pipe->device->depth == 0) {

sys/dev/usb/uhci.c

2642

pipe->methods = &uhci_root_ctrl_methods;

sys/dev/usb/uhci.c

2645

pipe->methods = &uhci_root_intr_methods;

sys/dev/usb/uhci.c

2653

pipe->methods = &uhci_device_ctrl_methods;

sys/dev/usb/uhci.c

2680

pipe->methods = &uhci_device_intr_methods;

sys/dev/usb/uhci.c

2681

ival = pipe->interval;

sys/dev/usb/uhci.c

2686

pipe->methods = &uhci_device_isoc_methods;

sys/dev/usb/uhci.c

2687

return (uhci_setup_isoc(pipe));

sys/dev/usb/uhci.c

2689

pipe->methods = &uhci_device_bulk_methods;

sys/dev/usb/uhci.c

2874

return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/uhci.c

3217

uhci_root_ctrl_close(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

3250

return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/uhci.c

3269

uhci_root_intr_close(struct usbd_pipe *pipe)

sys/dev/usb/uhci.c

3278

if (xfer->pipe->repeat)

sys/dev/usb/uhci.c

733

struct usbd_pipe *pipe;

sys/dev/usb/uhci.c

746

pipe = ex->xfer.pipe;

sys/dev/usb/uhci.c

747

if (pipe == NULL) {

sys/dev/usb/uhci.c

752

if (pipe->endpoint == NULL) {

sys/dev/usb/uhci.c

754

ex, DONE, pipe);

sys/dev/usb/uhci.c

757

if (pipe->device == NULL) {

sys/dev/usb/uhci.c

759

ex, DONE, pipe);

sys/dev/usb/uhci.c

76

struct usbd_pipe pipe;

sys/dev/usb/uhci.c

762

ed = pipe->endpoint->edesc;

sys/dev/usb/uhci.c

763

dev = pipe->device;

sys/dev/usb/uhci.c

768

dev->address, pipe,

sys/dev/usb/uhidev.c

881

if (!usbd_is_dying(xfer->pipe->device)) {

sys/dev/usb/umass.c

190

struct usbd_pipe *pipe,

sys/dev/usb/umass.c

739

umass_setup_transfer(struct umass_softc *sc, struct usbd_pipe *pipe,

sys/dev/usb/umass.c

750

usbd_setup_xfer(xfer, pipe, (void *)sc, buffer, buflen,

sys/dev/usb/umidi.c

1081

usbd_setup_xfer(ep->xfer, ep->pipe,

sys/dev/usb/umidi.c

1098

usbd_setup_xfer(ep->xfer, ep->pipe,

sys/dev/usb/umidi.c

352

err = usbd_open_pipe(sc->sc_iface, ep->addr, 0, &ep->pipe);

sys/dev/usb/umidi.c

364

usbd_close_pipe(ep->pipe);

sys/dev/usb/umidivar.h

88

struct usbd_pipe *pipe;

sys/dev/usb/usb.c

949

usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc;

sys/dev/usb/usb_subr.c

790

struct usbd_endpoint *ep, int ival, struct usbd_pipe **pipe)

sys/dev/usb/usb_subr.c

796

dev, iface, ep, pipe));

sys/dev/usb/usb_subr.c

814

*pipe = p;

sys/dev/usb/usbdi.c

148

usbd_dump_queue(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

152

printf("%s: pipe=%p\n", __func__, pipe);

sys/dev/usb/usbdi.c

153

SIMPLEQ_FOREACH(xfer, &pipe->queue, next) {

sys/dev/usb/usbdi.c

159

usbd_dump_pipe(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

161

printf("%s: pipe=%p\n", __func__, pipe);

sys/dev/usb/usbdi.c

162

if (pipe == NULL)

sys/dev/usb/usbdi.c

164

usbd_dump_iface(pipe->iface);

sys/dev/usb/usbdi.c

165

usbd_dump_device(pipe->device);

sys/dev/usb/usbdi.c

166

usbd_dump_endpoint(pipe->endpoint);

sys/dev/usb/usbdi.c

168

pipe->running, pipe->aborting);

sys/dev/usb/usbdi.c

169

printf(" intrxfer=%p, repeat=%d, interval=%d\n", pipe->intrxfer,

sys/dev/usb/usbdi.c

170

pipe->repeat, pipe->interval);

sys/dev/usb/usbdi.c

176

struct usbd_pipe **pipe)

sys/dev/usb/usbdi.c

178

return (usbd_open_pipe_ival(iface, address, flags, pipe,

sys/dev/usb/usbdi.c

184

u_int8_t flags, struct usbd_pipe **pipe, int ival)

sys/dev/usb/usbdi.c

209

*pipe = p;

sys/dev/usb/usbdi.c

215

u_int8_t flags, struct usbd_pipe **pipe, void *priv,

sys/dev/usb/usbdi.c

239

*pipe = ipipe;

sys/dev/usb/usbdi.c

254

usbd_close_pipe(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

257

if (pipe == NULL) {

sys/dev/usb/usbdi.c

263

if (!SIMPLEQ_EMPTY(&pipe->queue))

sys/dev/usb/usbdi.c

264

usbd_abort_pipe(pipe);

sys/dev/usb/usbdi.c

267

if (pipe->iface != NULL)

sys/dev/usb/usbdi.c

268

LIST_REMOVE(pipe, next);

sys/dev/usb/usbdi.c

269

pipe->endpoint->refcnt--;

sys/dev/usb/usbdi.c

270

pipe->methods->close(pipe);

sys/dev/usb/usbdi.c

271

if (pipe->intrxfer != NULL)

sys/dev/usb/usbdi.c

272

usbd_free_xfer(pipe->intrxfer);

sys/dev/usb/usbdi.c

273

free(pipe, M_USB, pipe->pipe_size);

sys/dev/usb/usbdi.c

280

struct usbd_pipe *pipe = xfer->pipe;

sys/dev/usb/usbdi.c

281

struct usbd_bus *bus = pipe->device->bus;

sys/dev/usb/usbdi.c

286

if (usbd_is_dying(pipe->device))

sys/dev/usb/usbdi.c

290

xfer, xfer->flags, pipe, pipe->running));

sys/dev/usb/usbdi.c

293

usbd_dump_queue(pipe);

sys/dev/usb/usbdi.c

298

if (pipe->aborting)

sys/dev/usb/usbdi.c

319

err = pipe->methods->transfer(xfer);

sys/dev/usb/usbdi.c

348

usbd_dopoll(pipe->device);

sys/dev/usb/usbdi.c

363

usbd_abort_pipe(pipe);

sys/dev/usb/usbdi.c

438

usbd_setup_xfer(struct usbd_xfer *xfer, struct usbd_pipe *pipe,

sys/dev/usb/usbdi.c

442

xfer->pipe = pipe;

sys/dev/usb/usbdi.c

460

xfer->pipe = dev->default_pipe;

sys/dev/usb/usbdi.c

475

usbd_setup_isoc_xfer(struct usbd_xfer *xfer, struct usbd_pipe *pipe,

sys/dev/usb/usbdi.c

481

xfer->pipe = pipe;

sys/dev/usb/usbdi.c

550

usbd_abort_pipe(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

556

if (pipe == NULL) {

sys/dev/usb/usbdi.c

562

DPRINTFN(2,("%s: pipe=%p\n", __func__, pipe));

sys/dev/usb/usbdi.c

565

usbd_dump_queue(pipe);

sys/dev/usb/usbdi.c

567

pipe->repeat = 0;

sys/dev/usb/usbdi.c

568

pipe->aborting = 1;

sys/dev/usb/usbdi.c

569

while ((xfer = SIMPLEQ_FIRST(&pipe->queue)) != NULL) {

sys/dev/usb/usbdi.c

57

void usbd_start_next(struct usbd_pipe *pipe);

sys/dev/usb/usbdi.c

571

pipe, xfer, pipe->methods));

sys/dev/usb/usbdi.c

573

pipe->methods->abort(xfer);

sys/dev/usb/usbdi.c

576

pipe->aborting = 0;

sys/dev/usb/usbdi.c

581

usbd_clear_endpoint_stall(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

583

struct usbd_device *dev = pipe->device;

sys/dev/usb/usbdi.c

593

usbd_clear_endpoint_toggle(pipe);

sys/dev/usb/usbdi.c

598

USETW(req.wIndex, pipe->endpoint->edesc->bEndpointAddress);

sys/dev/usb/usbdi.c

606

usbd_clear_endpoint_stall_async(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

608

struct usbd_device *dev = pipe->device;

sys/dev/usb/usbdi.c

613

usbd_clear_endpoint_toggle(pipe);

sys/dev/usb/usbdi.c

618

USETW(req.wIndex, pipe->endpoint->edesc->bEndpointAddress);

sys/dev/usb/usbdi.c

630

usbd_clear_endpoint_toggle(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

632

if (pipe->methods->cleartoggle != NULL)

sys/dev/usb/usbdi.c

633

pipe->methods->cleartoggle(pipe);

sys/dev/usb/usbdi.c

729

struct usbd_pipe *pipe = xfer->pipe;

sys/dev/usb/usbdi.c

730

struct usbd_bus *bus = pipe->device->bus;

sys/dev/usb/usbdi.c

740

"actlen=%d\n", pipe, xfer, xfer->status, xfer->actlen));

sys/dev/usb/usbdi.c

750

pipe->running = 0;

sys/dev/usb/usbdi.c

767

if (!pipe->repeat) {

sys/dev/usb/usbdi.c

773

if (!pipe->repeat) {

sys/dev/usb/usbdi.c

775

KASSERT(xfer == SIMPLEQ_FIRST(&pipe->queue));

sys/dev/usb/usbdi.c

776

SIMPLEQ_REMOVE_HEAD(&pipe->queue, next);

sys/dev/usb/usbdi.c

782

pipe->repeat, SIMPLEQ_FIRST(&pipe->queue)));

sys/dev/usb/usbdi.c

786

[UE_GET_XFERTYPE(pipe->endpoint->edesc->bmAttributes)];

sys/dev/usb/usbdi.c

805

if (pipe->repeat) {

sys/dev/usb/usbdi.c

808

pipe->methods->done(xfer);

sys/dev/usb/usbdi.c

810

pipe->methods->done(xfer);

sys/dev/usb/usbdi.c

818

if (!pipe->repeat) {

sys/dev/usb/usbdi.c

822

pipe->iface != NULL) /* not control pipe */

sys/dev/usb/usbdi.c

823

pipe->running = 0;

sys/dev/usb/usbdi.c

825

usbd_start_next(pipe);

sys/dev/usb/usbdi.c

832

struct usbd_pipe *pipe = xfer->pipe;

sys/dev/usb/usbdi.c

837

pipe, pipe->running, xfer->timeout));

sys/dev/usb/usbdi.c

846

SIMPLEQ_INSERT_TAIL(&pipe->queue, xfer, next);

sys/dev/usb/usbdi.c

847

if (pipe->running)

sys/dev/usb/usbdi.c

850

pipe->running = 1;

sys/dev/usb/usbdi.c

859

usbd_start_next(struct usbd_pipe *pipe)

sys/dev/usb/usbdi.c

867

if (pipe == NULL) {

sys/dev/usb/usbdi.c

871

if (pipe->methods == NULL || pipe->methods->start == NULL) {

sys/dev/usb/usbdi.c

872

printf("%s: pipe=%p no start method\n", __func__, pipe);

sys/dev/usb/usbdi.c

878

xfer = SIMPLEQ_FIRST(&pipe->queue);

sys/dev/usb/usbdi.c

879

DPRINTFN(5, ("%s: pipe=%p, xfer=%p\n", __func__, pipe, xfer));

sys/dev/usb/usbdi.c

881

pipe->running = 0;

sys/dev/usb/usbdi.c

883

err = pipe->methods->start(xfer);

sys/dev/usb/usbdi.c

886

pipe->running = 0;

sys/dev/usb/usbdi.h

101

void usbd_setup_isoc_xfer(struct usbd_xfer *xfer, struct usbd_pipe *pipe,

sys/dev/usb/usbdi.h

108

void usbd_abort_pipe(struct usbd_pipe *pipe);

sys/dev/usb/usbdi.h

109

usbd_status usbd_clear_endpoint_stall(struct usbd_pipe *pipe);

sys/dev/usb/usbdi.h

110

usbd_status usbd_clear_endpoint_stall_async(struct usbd_pipe *pipe);

sys/dev/usb/usbdi.h

111

void usbd_clear_endpoint_toggle(struct usbd_pipe *pipe);

sys/dev/usb/usbdi.h

118

u_int8_t flags, struct usbd_pipe **pipe, void *priv,

sys/dev/usb/usbdi.h

120

usbd_status usbd_do_request(struct usbd_device *pipe, usb_device_request_t *req,

sys/dev/usb/usbdi.h

124

usbd_status usbd_do_request_flags(struct usbd_device *pipe,

sys/dev/usb/usbdi.h

90

u_int8_t flags, struct usbd_pipe **pipe);

sys/dev/usb/usbdi.h

91

usbd_status usbd_close_pipe(struct usbd_pipe *pipe);

sys/dev/usb/usbdi.h

95

void usbd_setup_xfer(struct usbd_xfer *xfer, struct usbd_pipe *pipe,

sys/dev/usb/usbdivar.h

205

struct usbd_pipe *pipe;

sys/dev/usb/usbdivar.h

286

return (xfer->pipe->endpoint->edesc->bEndpointAddress & UE_DIR_IN);

sys/dev/usb/uticom.c

845

struct usbd_pipe *pipe;

sys/dev/usb/uticom.c

876

&pipe);

sys/dev/usb/uticom.c

898

usbd_setup_xfer(oxfer, pipe, (void *)sc, obuf, buffer_size,

sys/dev/usb/uticom.c

911

usbd_close_pipe(pipe);

sys/dev/usb/xhci.c

1088

skipxfer = SIMPLEQ_FIRST(&xp->pipe.queue);

sys/dev/usb/xhci.c

1209

struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe;

sys/dev/usb/xhci.c

1262

xhci_pipe_open(struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1264

struct xhci_softc *sc = (struct xhci_softc *)pipe->device->bus;

sys/dev/usb/xhci.c

1265

struct xhci_pipe *xp = (struct xhci_pipe *)pipe;

sys/dev/usb/xhci.c

1266

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/xhci.c

1276

if (pipe->device->depth == 0) {

sys/dev/usb/xhci.c

1279

pipe->methods = &xhci_root_ctrl_methods;

sys/dev/usb/xhci.c

1282

pipe->methods = &xhci_root_intr_methods;

sys/dev/usb/xhci.c

1285

pipe->methods = NULL;

sys/dev/usb/xhci.c

1298

pipe->methods = &xhci_device_ctrl_methods;

sys/dev/usb/xhci.c

1319

pipe->methods = &xhci_device_isoc_methods;

sys/dev/usb/xhci.c

1322

pipe->methods = &xhci_device_bulk_methods;

sys/dev/usb/xhci.c

1325

pipe->methods = &xhci_device_intr_methods;

sys/dev/usb/xhci.c

1337

slot = ((struct xhci_pipe *)pipe->device->default_pipe)->slot;

sys/dev/usb/xhci.c

1342

if (xhci_pipe_init(sc, pipe)) {

sys/dev/usb/xhci.c

1355

xhci_get_txinfo(struct xhci_softc *sc, struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1357

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/xhci.c

1358

usb_endpoint_ss_comp_descriptor_t *esscd = pipe->endpoint->esscd;

sys/dev/usb/xhci.c

1368

if (esscd && pipe->device->speed >= USB_SPEED_SUPER) {

sys/dev/usb/xhci.c

1407

xhci_pipe_interval(struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1409

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/xhci.c

1410

uint8_t speed = pipe->device->speed;

sys/dev/usb/xhci.c

1444

xhci_pipe_maxburst(struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1446

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/xhci.c

1447

usb_endpoint_ss_comp_descriptor_t *esscd = pipe->endpoint->esscd;

sys/dev/usb/xhci.c

1452

switch (pipe->device->speed) {

sys/dev/usb/xhci.c

1485

xhci_context_setup(struct xhci_softc *sc, struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1487

struct xhci_pipe *xp = (struct xhci_pipe *)pipe;

sys/dev/usb/xhci.c

1489

usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;

sys/dev/usb/xhci.c

1501

for (hub = pipe->device; hub->myhub->depth; hub = hub->myhub) {

sys/dev/usb/xhci.c

1511

switch (pipe->device->speed) {

sys/dev/usb/xhci.c

1535

sdev->ep_ctx[xp->dci-1]->info_lo = htole32(xhci_pipe_interval(pipe));

sys/dev/usb/xhci.c

1538

XHCI_EPCTX_SET_MAXB(xhci_pipe_maxburst(pipe)) |

sys/dev/usb/xhci.c

1541

sdev->ep_ctx[xp->dci-1]->txinfo = htole32(xhci_get_txinfo(sc, pipe));

sys/dev/usb/xhci.c

1565

if (pipe->device->hub != NULL) {

sys/dev/usb/xhci.c

1566

int nports = pipe->device->hub->nports;

sys/dev/usb/xhci.c

1571

if (UHUB_IS_MTT(pipe->device))

sys/dev/usb/xhci.c

1575

XHCI_SCTX_TT_THINK_TIME(pipe->device->hub->ttthink)

sys/dev/usb/xhci.c

1583

if (speed < XHCI_SPEED_HIGH && pipe->device->myhsport != NULL) {

sys/dev/usb/xhci.c

1584

struct usbd_device *hshub = pipe->device->myhsport->parent;

sys/dev/usb/xhci.c

1592

XHCI_SCTX_TT_PORT_NUM(pipe->device->myhsport->portno)

sys/dev/usb/xhci.c

1607

xhci_pipe_init(struct xhci_softc *sc, struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1609

struct xhci_pipe *xp = (struct xhci_pipe *)pipe;

sys/dev/usb/xhci.c

1614

struct usbd_device *dev = pipe->device;

sys/dev/usb/xhci.c

1616

" (epAddr=0x%x)\n", __func__, pipe, dev->address, dev->depth,

sys/dev/usb/xhci.c

1618

pipe->endpoint->edesc->bEndpointAddress);

sys/dev/usb/xhci.c

1629

error = xhci_context_setup(sc, pipe);

sys/dev/usb/xhci.c

1659

xhci_pipe_close(struct usbd_pipe *pipe)

sys/dev/usb/xhci.c

1661

struct xhci_softc *sc = (struct xhci_softc *)pipe->device->bus;

sys/dev/usb/xhci.c

1662

struct xhci_pipe *xp = (struct xhci_pipe *)pipe;

sys/dev/usb/xhci.c

1666

if (pipe->device->depth == 0)

sys/dev/usb/xhci.c

1936

struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe;

sys/dev/usb/xhci.c

2337

struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe;

sys/dev/usb/xhci.c

2441

return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/xhci.c

2822

return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/xhci.c

2865

uint32_t npkt, mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/xhci.c

2885

uint32_t mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/xhci.c

2894

maxb = xhci_pipe_maxburst(xfer->pipe);

sys/dev/usb/xhci.c

2920

return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/xhci.c

2927

struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe;

sys/dev/usb/xhci.c

3034

return (xhci_device_generic_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));

sys/dev/usb/xhci.c

3041

struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe;

sys/dev/usb/xhci.c

3044

uint32_t mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/xhci.c

3157

if (xfer->pipe->repeat) {

sys/dev/usb/xhci.c

3166

KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer);

sys/dev/usb/xhci.c

3187

struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe;

sys/dev/usb/xhci.c

60

struct usbd_pipe pipe;

sys/dev/usb/xhci.c

808

last = SIMPLEQ_FIRST(&xp->pipe.queue);

sys/dev/usb/xhci.c

815

xfer = SIMPLEQ_FIRST(&xp->pipe.queue);

sys/dev/usb/xhci.c

889

xfertype = UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes);

sys/kern/kern_sysctl.c

1643

struct pipe *pipe = (struct pipe *)fp->f_data;

sys/kern/kern_sysctl.c

1646

kf->pipe_peer = PTRTOINT64(pipe->pipe_peer);

sys/kern/kern_sysctl.c

1647

kf->pipe_state = pipe->pipe_state;

sys/kern/sys_pipe.c

127

void pipe_wakeup(struct pipe *);

sys/kern/sys_pipe.c

129

int pipe_create(struct pipe *);

sys/kern/sys_pipe.c

130

void pipe_destroy(struct pipe *);

sys/kern/sys_pipe.c

131

int pipe_rundown(struct pipe *);

sys/kern/sys_pipe.c

132

struct pipe *pipe_peer(struct pipe *);

sys/kern/sys_pipe.c

133

int pipe_buffer_realloc(struct pipe *, u_int);

sys/kern/sys_pipe.c

134

void pipe_buffer_free(struct pipe *);

sys/kern/sys_pipe.c

136

int pipe_iolock(struct pipe *);

sys/kern/sys_pipe.c

137

void pipe_iounlock(struct pipe *);

sys/kern/sys_pipe.c

138

int pipe_iosleep(struct pipe *, const char *);

sys/kern/sys_pipe.c

177

struct pipe *rpipe, *wpipe = NULL;

sys/kern/sys_pipe.c

246

pipe_buffer_realloc(struct pipe *cpipe, u_int size)

sys/kern/sys_pipe.c

278

pipe_create(struct pipe *cpipe)

sys/kern/sys_pipe.c

295

struct pipe *

sys/kern/sys_pipe.c

296

pipe_peer(struct pipe *cpipe)

sys/kern/sys_pipe.c

298

struct pipe *peer;

sys/kern/sys_pipe.c

312

pipe_iolock(struct pipe *cpipe)

sys/kern/sys_pipe.c

333

pipe_iounlock(struct pipe *cpipe)

sys/kern/sys_pipe.c

355

pipe_iosleep(struct pipe *cpipe, const char *wmesg)

sys/kern/sys_pipe.c

368

pipe_wakeup(struct pipe *cpipe)

sys/kern/sys_pipe.c

381

struct pipe *rpipe = fp->f_data;

sys/kern/sys_pipe.c

481

struct pipe *rpipe = fp->f_data, *wpipe;

sys/kern/sys_pipe.c

51

struct pipe pp_wpipe;

sys/kern/sys_pipe.c

52

struct pipe pp_rpipe;

sys/kern/sys_pipe.c

673

struct pipe *mpipe = fp->f_data;

sys/kern/sys_pipe.c

716

struct pipe *pipe = fp->f_data;

sys/kern/sys_pipe.c

720

rw_enter_read(pipe->pipe_lock);

sys/kern/sys_pipe.c

722

ub->st_blksize = pipe->pipe_buffer.size;

sys/kern/sys_pipe.c

723

ub->st_size = pipe->pipe_buffer.cnt;

sys/kern/sys_pipe.c

725

ub->st_atim.tv_sec = pipe->pipe_atime.tv_sec;

sys/kern/sys_pipe.c

726

ub->st_atim.tv_nsec = pipe->pipe_atime.tv_nsec;

sys/kern/sys_pipe.c

727

ub->st_mtim.tv_sec = pipe->pipe_mtime.tv_sec;

sys/kern/sys_pipe.c

728

ub->st_mtim.tv_nsec = pipe->pipe_mtime.tv_nsec;

sys/kern/sys_pipe.c

729

ub->st_ctim.tv_sec = pipe->pipe_ctime.tv_sec;

sys/kern/sys_pipe.c

730

ub->st_ctim.tv_nsec = pipe->pipe_ctime.tv_nsec;

sys/kern/sys_pipe.c

733

rw_exit_read(pipe->pipe_lock);

sys/kern/sys_pipe.c

744

struct pipe *cpipe = fp->f_data;

sys/kern/sys_pipe.c

757

pipe_buffer_free(struct pipe *cpipe)

sys/kern/sys_pipe.c

779

pipe_destroy(struct pipe *cpipe)

sys/kern/sys_pipe.c

781

struct pipe *ppipe;

sys/kern/sys_pipe.c

823

pipe_rundown(struct pipe *cpipe)

sys/kern/sys_pipe.c

839

struct pipe *rpipe = kn->kn_fp->f_data, *wpipe;

sys/kern/sys_pipe.c

893

struct pipe *cpipe = kn->kn_hook;

sys/kern/sys_pipe.c

901

struct pipe *rpipe = kn->kn_fp->f_data, *wpipe;

sys/kern/sys_pipe.c

922

struct pipe *rpipe = kn->kn_fp->f_data, *wpipe;

sys/kern/sys_pipe.c

943

struct pipe *rpipe = kn->kn_fp->f_data, *wpipe;

sys/kern/sys_pipe.c

963

struct pipe *rpipe = kn->kn_fp->f_data;

sys/kern/sys_pipe.c

976

struct pipe *rpipe = kn->kn_fp->f_data;

sys/sys/pipe.h

88

struct pipe *pipe_peer; /* [p] link with other direction */

usr.bin/bc/bc.y

1145

if (pipe(p) == -1)

usr.bin/calendar/io.c

342

if (pipe(pdes) == -1) {

usr.bin/calendar/io.c

404

if (pipe(pdes) == -1)

usr.bin/cvs/client.c

221

if (pipe(ifd) == -1)

usr.bin/cvs/client.c

223

if (pipe(ofd) == -1)

usr.bin/cvs/util.c

891

if (in != NULL && pipe(fds) == -1) {

usr.bin/lex/filter.c

151

if (pipe(pipes) == -1)

usr.bin/m4/gnum4.c

638

if (pipe(p) == -1)

usr.bin/mail/popen.c

106

if (pipe(p) == -1)

usr.bin/mail/popen.c

154

if (fp_head->pipe)

usr.bin/mail/popen.c

161

register_file(FILE *fp, int pipe, pid_t pid)

usr.bin/mail/popen.c

168

fpp->pipe = pipe;

usr.bin/mail/popen.c

45

int pipe;

usr.bin/make/cmd_exec.c

139

if (pipe(fds) == -1) {

usr.bin/mg/dired.c

690

if (pipe(fds) == -1) {

usr.bin/nm/nm.c

893

if (pipe(pip) == -1)

usr.bin/openssl/speed.c

2746

if (pipe(fd) == -1) {

usr.bin/passwd/pwd_check.c

108

if (checker != NULL && pipe(pipefds) == -1) {

usr.bin/rdist/child.c

453

if (pipe(fildes) == -1) {

usr.bin/rdist/common.c

677

if (pipe(fd) == -1) {

usr.bin/rpcgen/rpc_main.c

310

(void) pipe(pd);

usr.bin/sdiff/sdiff.c

312

if (pipe(fd))

usr.bin/sendbug/sendbug.c

324

if (pipe(filedes) == -1) {

usr.bin/skeyaudit/skeyaudit.c

215

if (pipe(pfd) == -1)

usr.bin/ssh/misc.c

2788

if (pipe(p) == -1) {

usr.bin/ssh/monitor.c

1647

if (pipe(pair) == -1)

usr.bin/ssh/readpass.c

60

if (pipe(p) == -1) {

usr.bin/ssh/session.c

357

if (pipe(pin) == -1) {

usr.bin/ssh/session.c

361

if (pipe(pout) == -1) {

usr.bin/ssh/session.c

367

if (pipe(perr) == -1) {

usr.bin/ssh/ssh-sk-client.c

64

if (pipe(execpipe) == -1) {

usr.bin/ssh/sshconnect.c

191

if (pipe(pin) == -1 || pipe(pout) == -1)

usr.bin/ssh/sshconnect2.c

2039

if (pipe(to) == -1) {

usr.bin/ssh/sshconnect2.c

2043

if (pipe(from) == -1) {

usr.bin/tmux/window-copy.c

1181

window_copy_do_copy_end_of_line(struct window_copy_cmd_state *cs, int pipe,

usr.bin/tmux/window-copy.c

1198

if (pipe) {

usr.bin/tmux/window-copy.c

1218

if (pipe)

usr.bin/tmux/window-copy.c

1268

window_copy_do_copy_line(struct window_copy_cmd_state *cs, int pipe, int cancel)

usr.bin/tmux/window-copy.c

1284

if (pipe) {

usr.bin/tmux/window-copy.c

1306

if (pipe)

usr.bin/vacation/vacation.c

460

if (pipe(pvect) == -1) {

usr.bin/vi/ex/ex_argv.c

613

if (pipe(std_output) < 0) {

usr.bin/vi/ex/ex_filter.c

114

} else if (ftype != FILTER_READ && pipe(input) < 0) {

usr.bin/vi/ex/ex_filter.c

120

if (pipe(output) < 0) {

usr.bin/watch/watch.c

454

if (pipe(fds) == -1)

usr.sbin/bgpd/bgpd.c

1292

getsockpair(int pipe[2])

usr.sbin/bgpd/bgpd.c

1297

PF_UNSPEC, pipe) == -1)

usr.sbin/bgpd/bgpd.c

1302

if (setsockopt(pipe[i], SOL_SOCKET, SO_RCVBUF,

usr.sbin/bgpd/bgpd.c

1312

if (setsockopt(pipe[i], SOL_SOCKET, SO_SNDBUF,

usr.sbin/bgplgd/slowcgi.c

960

if (pipe(s_in) == -1)

usr.sbin/bgplgd/slowcgi.c

962

if (pipe(s_out) == -1)

usr.sbin/bgplgd/slowcgi.c

964

if (pipe(s_err) == -1)

usr.sbin/cron/atrun.c

442

if (pipe(output_pipe) != 0) { /* child's stdout/stderr */

usr.sbin/cron/do_command.c

111

if (pipe(stdin_pipe) != 0 || pipe(stdout_pipe) != 0) {

usr.sbin/cron/popen.c

78

if (pipe(pdes) == -1)

usr.sbin/dhcpd/dhcpd.c

223

if (pipe(pfpipe) == -1)

usr.sbin/lpd/printer.c

1195

pipe(fildes);

usr.sbin/lpd/printer.c

953

if (pipe(p) == -1) {

usr.sbin/lpr/lpd/printjob.c

1121

pipe(p);

usr.sbin/lpr/lpd/printjob.c

1376

pipe(p);

usr.sbin/lpr/lpd/printjob.c

593

pipe(p);

usr.sbin/nsd/popen3.c

43

if(fdinptr != NULL && pipe(fdin) == -1) {

usr.sbin/nsd/popen3.c

46

if(fdoutptr != NULL && pipe(fdout) == -1) {

usr.sbin/nsd/popen3.c

49

if(fderrptr != NULL && pipe(fderr) == -1) {

usr.sbin/nsd/popen3.c

52

if(pipe(fdsig) == -1 ||

usr.sbin/nsd/server.c

1729

if(pipe(pipefd) < 0) {

usr.sbin/nsd/server.c

3459

if(pipe(nsd->verifier_pipe) == -1) {

usr.sbin/rdate/rdate.c

128

if (pipe(p) == -1)

usr.sbin/smtpd/smtpd.c

1467

if (pipe(pipefd) == -1) {

usr.sbin/syslogd/syslogd.c

732

pipe(lockpipe);

usr.sbin/unbound/dnstap/dtstream.c

2158

if(pipe(dtio->commandpipe) == -1) {

usr.sbin/unbound/util/tube.c

57

#define socketpair(f, t, p, sv) pipe(sv)