lib/libcrypto/asn1/a_time.c

76

.funcs = NULL,

lib/libcrypto/asn1/asn1t.h

103

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

115

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

160

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

172

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

223

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

235

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

256

.funcs = &tname##_aux, \

lib/libcrypto/asn1/asn1t.h

268

.funcs = &tname##_aux, \

lib/libcrypto/asn1/asn1t.h

280

.funcs = &tname##_aux, \

lib/libcrypto/asn1/asn1t.h

342

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

354

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

366

.funcs = &tname##_aux, \

lib/libcrypto/asn1/asn1t.h

643

const void *funcs; /* functions that handle this type */

lib/libcrypto/asn1/asn1t.h

832

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

844

.funcs = NULL, \

lib/libcrypto/asn1/asn1t.h

854

.funcs = &fptrs, \

lib/libcrypto/asn1/asn_mime.c

378

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/bio_ndef.c

110

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/bio_ndef.c

247

aux = ndef_aux->it->funcs;

lib/libcrypto/asn1/p8_pkey.c

112

.funcs = &PKCS8_PRIV_KEY_INFO_aux,

lib/libcrypto/asn1/tasn_dec.c

284

if (it->funcs != NULL)

lib/libcrypto/asn1/tasn_dec.c

391

if (it->utype != V_ASN1_ANY || it->funcs != NULL)

lib/libcrypto/asn1/tasn_dec.c

423

if (it->funcs != NULL) {

lib/libcrypto/asn1/tasn_dec.c

424

const ASN1_PRIMITIVE_FUNCS *pf = it->funcs;

lib/libcrypto/asn1/tasn_dec.c

652

if ((aux = it->funcs) != NULL)

lib/libcrypto/asn1/tasn_dec.c

753

if ((aux = it->funcs) != NULL)

lib/libcrypto/asn1/tasn_dec.c

915

const ASN1_EXTERN_FUNCS *ef = it->funcs;

lib/libcrypto/asn1/tasn_enc.c

146

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/tasn_enc.c

204

ef = it->funcs;

lib/libcrypto/asn1/tasn_enc.c

572

if (it->funcs != NULL) {

lib/libcrypto/asn1/tasn_enc.c

573

const ASN1_PRIMITIVE_FUNCS *pf = it->funcs;

lib/libcrypto/asn1/tasn_fre.c

135

ef = it->funcs;

lib/libcrypto/asn1/tasn_fre.c

194

if (it != NULL && it->funcs != NULL) {

lib/libcrypto/asn1/tasn_fre.c

195

const ASN1_PRIMITIVE_FUNCS *pf = it->funcs;

lib/libcrypto/asn1/tasn_fre.c

90

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/tasn_new.c

110

ef = it->funcs;

lib/libcrypto/asn1/tasn_new.c

191

ef = it->funcs;

lib/libcrypto/asn1/tasn_new.c

274

if (it != NULL && it->funcs != NULL) {

lib/libcrypto/asn1/tasn_new.c

275

const ASN1_PRIMITIVE_FUNCS *pf = it->funcs;

lib/libcrypto/asn1/tasn_new.c

326

if (it != NULL && it->funcs != NULL) {

lib/libcrypto/asn1/tasn_new.c

327

const ASN1_PRIMITIVE_FUNCS *pf = it->funcs;

lib/libcrypto/asn1/tasn_new.c

98

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/tasn_prn.c

116

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/tasn_prn.c

160

ef = it->funcs;

lib/libcrypto/asn1/tasn_prn.c

413

if (it->funcs != NULL) {

lib/libcrypto/asn1/tasn_prn.c

414

const ASN1_PRIMITIVE_FUNCS *pf = it->funcs;

lib/libcrypto/asn1/tasn_typ.c

501

.funcs = NULL,

lib/libcrypto/asn1/tasn_typ.c

542

.funcs = NULL,

lib/libcrypto/asn1/tasn_typ.c

583

.funcs = NULL,

lib/libcrypto/asn1/tasn_typ.c

688

.funcs = NULL,

lib/libcrypto/asn1/tasn_typ.c

707

.funcs = NULL,

lib/libcrypto/asn1/tasn_utl.c

115

aux = it->funcs;

lib/libcrypto/asn1/tasn_utl.c

130

const ASN1_AUX *aux = it->funcs;

lib/libcrypto/asn1/x_algor.c

104

.funcs = NULL,

lib/libcrypto/asn1/x_attrib.c

89

.funcs = NULL,

lib/libcrypto/asn1/x_bignum.c

109

.funcs = &bignum_pf,

lib/libcrypto/asn1/x_bignum.c

98

.funcs = &bignum_pf,

lib/libcrypto/asn1/x_crl.c

184

.funcs = &X509_CRL_INFO_aux,

lib/libcrypto/asn1/x_crl.c

421

.funcs = &X509_CRL_aux,

lib/libcrypto/asn1/x_exten.c

108

.funcs = NULL,

lib/libcrypto/asn1/x_long.c

103

.funcs = &long_pf,

lib/libcrypto/asn1/x_long.c

114

.funcs = &long_pf,

lib/libcrypto/asn1/x_name.c

168

.funcs = NULL,

lib/libcrypto/asn1/x_name.c

186

.funcs = NULL,

lib/libcrypto/asn1/x_name.c

212

.funcs = &x509_name_ff,

lib/libcrypto/asn1/x_pubkey.c

110

.funcs = &X509_PUBKEY_aux,

lib/libcrypto/asn1/x_pubkey.c

258

const ASN1_EXTERN_FUNCS *ef = it->funcs;

lib/libcrypto/asn1/x_pubkey.c

403

.funcs = &pkey_pubkey_asn1_ff,

lib/libcrypto/asn1/x_pubkey.c

503

.funcs = &rsa_pubkey_asn1_ff,

lib/libcrypto/asn1/x_pubkey.c

599

.funcs = &dsa_pubkey_asn1_ff,

lib/libcrypto/asn1/x_pubkey.c

696

.funcs = &ec_pubkey_asn1_ff,

lib/libcrypto/asn1/x_req.c

134

.funcs = &X509_REQ_INFO_aux,

lib/libcrypto/asn1/x_req.c

199

.funcs = &X509_REQ_aux,

lib/libcrypto/asn1/x_spki.c

150

.funcs = NULL,

lib/libcrypto/asn1/x_x509.c

140

.funcs = &X509_CINF_aux,

lib/libcrypto/asn1/x_x509.c

247

.funcs = &X509_aux,

lib/libcrypto/cms/cms_asn1.c

1000

.funcs = &CMS_RecipientInfo_aux,

lib/libcrypto/cms/cms_asn1.c

1048

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1089

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1123

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

116

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1199

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1233

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1394

.funcs = &CMS_ContentInfo_aux,

lib/libcrypto/cms/cms_asn1.c

1420

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1443

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1472

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1506

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1548

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

1593

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

164

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

191

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

218

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

301

.funcs = &CMS_SignerInfo_aux,

lib/libcrypto/cms/cms_asn1.c

328

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

355

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

410

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

437

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

471

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

512

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

539

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

573

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

600

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

645

.funcs = &CMS_RecipientEncryptedKey_aux,

lib/libcrypto/cms/cms_asn1.c

672

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

706

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

779

.funcs = &CMS_KeyAgreeRecipientInfo_aux,

lib/libcrypto/cms/cms_asn1.c

813

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

854

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

89

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

895

.funcs = NULL,

lib/libcrypto/cms/cms_asn1.c

922

.funcs = NULL,

lib/libcrypto/dh/dh_asn1.c

122

.funcs = &DHparams_aux,

lib/libcrypto/dsa/dsa_asn1.c

117

.funcs = &DSA_SIG_aux,

lib/libcrypto/dsa/dsa_asn1.c

238

.funcs = &DSAPrivateKey_aux,

lib/libcrypto/dsa/dsa_asn1.c

297

.funcs = &DSAparams_aux,

lib/libcrypto/dsa/dsa_asn1.c

391

.funcs = &DSAPublicKey_aux,

lib/libcrypto/ec/ec_asn1.c

182

.funcs = NULL,

lib/libcrypto/ec/ec_asn1.c

267

.funcs = NULL,

lib/libcrypto/ec/ec_asn1.c

334

.funcs = NULL,

lib/libcrypto/ec/ec_asn1.c

368

.funcs = NULL,

lib/libcrypto/ec/ec_asn1.c

423

.funcs = NULL,

lib/libcrypto/ec/ec_asn1.c

469

.funcs = NULL,

lib/libcrypto/ec/ec_asn1.c

535

.funcs = NULL,

lib/libcrypto/ecdsa/ecdsa.c

96

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

1032

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

165

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

223

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

295

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

353

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

426

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

484

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

556

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

614

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

679

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

758

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

837

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

909

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

93

.funcs = NULL,

lib/libcrypto/ocsp/ocsp_asn.c

974

.funcs = NULL,

lib/libcrypto/pkcs12/p12_asn.c

162

.funcs = NULL,

lib/libcrypto/pkcs12/p12_asn.c

268

.funcs = NULL,

lib/libcrypto/pkcs12/p12_asn.c

413

.funcs = NULL,

lib/libcrypto/pkcs12/p12_asn.c

463

.funcs = NULL,

lib/libcrypto/pkcs12/p12_asn.c

482

.funcs = NULL,

lib/libcrypto/pkcs12/p12_asn.c

97

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

207

.funcs = &PKCS7_aux,

lib/libcrypto/pkcs7/pk7_asn1.c

300

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

417

.funcs = &PKCS7_SIGNER_INFO_aux,

lib/libcrypto/pkcs7/pk7_asn1.c

475

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

540

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

631

.funcs = &PKCS7_RECIP_INFO_aux,

lib/libcrypto/pkcs7/pk7_asn1.c

696

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

789

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

847

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

919

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

974

.funcs = NULL,

lib/libcrypto/pkcs7/pk7_asn1.c

997

.funcs = NULL,

lib/libcrypto/rsa/rsa_asn1.c

164

.funcs = &RSAPrivateKey_aux,

lib/libcrypto/rsa/rsa_asn1.c

201

.funcs = &RSAPublicKey_aux,

lib/libcrypto/rsa/rsa_asn1.c

263

.funcs = &RSA_PSS_PARAMS_aux,

lib/libcrypto/rsa/rsa_asn1.c

347

.funcs = &RSA_OAEP_PARAMS_aux,

lib/libcrypto/sm2/sm2_crypt.c

82

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

210

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

311

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

431

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

532

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

648

.funcs = &TS_RESP_aux,

lib/libcrypto/ts/ts_asn1.c

742

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

806

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

870

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

88

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

941

.funcs = NULL,

lib/libcrypto/ts/ts_asn1.c

999

.funcs = NULL,

lib/libcrypto/x509/x509_addr.c

108

.funcs = NULL,

lib/libcrypto/x509/x509_addr.c

136

.funcs = NULL,

lib/libcrypto/x509/x509_addr.c

164

.funcs = NULL,

lib/libcrypto/x509/x509_addr.c

192

.funcs = NULL,

lib/libcrypto/x509/x509_addr.c

211

.funcs = NULL,

lib/libcrypto/x509/x509_akeya.c

95

.funcs = NULL,

lib/libcrypto/x509/x509_asid.c

101

.funcs = NULL,

lib/libcrypto/x509/x509_asid.c

129

.funcs = NULL,

lib/libcrypto/x509/x509_asid.c

157

.funcs = NULL,

lib/libcrypto/x509/x509_asid.c

185

.funcs = NULL,

lib/libcrypto/x509/x509_bcons.c

120

.funcs = NULL,

lib/libcrypto/x509/x509_cpols.c

121

.funcs = NULL,

lib/libcrypto/x509/x509_cpols.c

179

.funcs = NULL,

lib/libcrypto/x509/x509_cpols.c

277

.funcs = NULL,

lib/libcrypto/x509/x509_cpols.c

335

.funcs = NULL,

lib/libcrypto/x509/x509_cpols.c

393

.funcs = NULL,

lib/libcrypto/x509/x509_crld.c

424

.funcs = &DIST_POINT_NAME_aux,

lib/libcrypto/x509/x509_crld.c

490

.funcs = NULL,

lib/libcrypto/x509/x509_crld.c

539

.funcs = NULL,

lib/libcrypto/x509/x509_crld.c

625

.funcs = NULL,

lib/libcrypto/x509/x509_extku.c

133

.funcs = NULL,

lib/libcrypto/x509/x509_genn.c

150

.funcs = NULL,

lib/libcrypto/x509/x509_genn.c

259

.funcs = NULL,

lib/libcrypto/x509/x509_genn.c

308

.funcs = NULL,

lib/libcrypto/x509/x509_genn.c

91

.funcs = NULL,

lib/libcrypto/x509/x509_info.c

143

.funcs = NULL,

lib/libcrypto/x509/x509_info.c

192

.funcs = NULL,

lib/libcrypto/x509/x509_ncons.c

136

.funcs = NULL,

lib/libcrypto/x509/x509_ncons.c

164

.funcs = NULL,

lib/libcrypto/x509/x509_pcons.c

121

.funcs = NULL,

lib/libcrypto/x509/x509_pku.c

113

.funcs = NULL,

lib/libcrypto/x509/x509_pmaps.c

119

.funcs = NULL,

lib/libcrypto/x509/x509_pmaps.c

138

.funcs = NULL,

regress/lib/libcrypto/bio/bio_asn1.c

48

.funcs = &WAF_aux,

regress/lib/libpthread/dlopen/dlopen.c

597

struct funcs *f;

regress/usr.bin/bc/t19.c

29

struct func funcs[] = { {"s", sinl},

regress/usr.bin/bc/t19.c

46

for (fi = 0; fi < nitems(funcs); fi++) {

regress/usr.bin/bc/t19.c

52

if (v == 0.0 && funcs[fi].f == logl)

regress/usr.bin/bc/t19.c

56

scale[si], funcs[fi].name, v);

regress/usr.bin/bc/t19.c

60

d2 = funcs[fi].f(v);

regress/usr.bin/bc/t19.c

67

if (funcs[fi].f == expl)

regress/usr.bin/bc/t19.c

71

funcs[fi].name, scale[si],

sys/dev/fdt/rkdrm.c

390

sc->sc_ddev.mode_config.funcs = &rkdrm_mode_config_funcs;

sys/dev/fdt/sxipio.c

359

for (j = 0; j < nitems(sc->sc_pins[i].funcs); j++) {

sys/dev/fdt/sxipio.c

360

if (sc->sc_pins[i].funcs[j].name == NULL)

sys/dev/fdt/sxipio.c

362

if (strcmp(func, sc->sc_pins[i].funcs[j].name) == 0)

sys/dev/fdt/sxipio.c

365

if (j >= nitems(sc->sc_pins[i].funcs))

sys/dev/fdt/sxipio.c

371

mux = sc->sc_pins[i].funcs[j].mux;

sys/dev/fdt/sxipio.c

552

if (strcmp(sc->sc_pins[i].funcs[0].name, "gpio_in") != 0 ||

sys/dev/fdt/sxipio.c

553

strcmp(sc->sc_pins[i].funcs[1].name, "gpio_out") != 0)

sys/dev/fdt/sxipiovar.h

28

struct sxipio_func funcs[10];

sys/dev/ic/anxdp.c

692

sc->sc_panel->funcs != NULL &&

sys/dev/ic/anxdp.c

693

sc->sc_panel->funcs->enable != NULL)

sys/dev/ic/anxdp.c

694

sc->sc_panel->funcs->enable(sc->sc_panel);

sys/dev/ic/anxdp.c

901

sc->sc_bridge.funcs = &anxdp_bridge_funcs;

sys/dev/ic/anxdp.c

908

if (sc->sc_panel != NULL && sc->sc_panel->funcs != NULL &&

sys/dev/ic/anxdp.c

909

sc->sc_panel->funcs->prepare != NULL)

sys/dev/ic/anxdp.c

910

sc->sc_panel->funcs->prepare(sc->sc_panel);

sys/dev/ic/dwhdmi.c

920

sc->sc_bridge.funcs = &dwhdmi_bridge_funcs;

sys/dev/ic/if_wi.c

195

wi_attach(struct wi_softc *sc, struct wi_funcs *funcs)

sys/dev/ic/if_wi.c

207

sc->sc_funcs = funcs;

sys/dev/ic/if_wi.c

228

ifp->if_ioctl = funcs->f_ioctl;

sys/dev/ic/if_wi.c

229

ifp->if_start = funcs->f_start;

sys/dev/ic/if_wi.c

230

ifp->if_watchdog = funcs->f_watchdog;

sys/dev/ic/if_wi.c

321

timeout_set(&sc->sc_timo, funcs->f_inquire, sc);

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

272

adev->gfxhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

273

r = adev->gfxhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

287

adev->gfx.rlc.funcs->resume(adev);

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

318

if (adev->ip_blocks[i].version->funcs->late_init) {

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

319

r = adev->ip_blocks[i].version->funcs->late_init(

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

324

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1574

((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1577

((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

402

const struct amd_ip_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

622

.funcs = &acp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1397

adev->gfx.imu.funcs) /* Not need to do mode2 reset for IMU enabled APUs */

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

520

if (adev->gfx.funcs->get_gpu_clock_counter)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

521

return adev->gfx.funcs->get_gpu_clock_counter(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

720

gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

845

ring->funcs = ring_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

711

adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

629

adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

608

adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

922

adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

924

adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

682

if (!adev->smuio.funcs ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

683

!adev->smuio.funcs->get_rom_index_offset ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

684

!adev->smuio.funcs->get_rom_data_offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

691

adev->smuio.funcs->get_rom_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

693

adev->smuio.funcs->get_rom_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

695

if (adev->nbio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

696

adev->nbio.funcs->get_rom_offset) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

697

rom_offset = adev->nbio.funcs->get_rom_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

137

(adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

138

adev->smuio.funcs->get_socket_id(adev) :

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

250

socket_id = (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

251

adev->smuio.funcs->get_socket_id(adev) :

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

572

ring->funcs = &cper_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

83

(adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

84

adev->smuio.funcs->get_socket_id(adev) :

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1027

if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1057

if (ring->funcs->parse_cs) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

364

if (p->uf_bo && ring->funcs->no_user_fence)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

389

r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1091

if (adev->gfx.funcs->read_wave_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1092

adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1185

if (adev->gfx.funcs->read_wave_vgprs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1186

adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1188

if (adev->gfx.funcs->read_wave_sgprs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1189

adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1882

if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1925

!ring->funcs->preempt_ib)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

433

if (adev->gfx.funcs->read_wave_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

434

adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

438

if (adev->gfx.funcs->read_wave_vgprs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

439

adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

441

if (adev->gfx.funcs->read_wave_sgprs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

442

adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

272

coredump->ring->funcs->type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

287

if (ip_block->version->funcs->print_ip_state) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

288

drm_printf(&p, "IP: %s\n", ip_block->version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

289

ip_block->version->funcs->print_ip_state(ip_block, &p);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1000

pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1047

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1048

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1077

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1078

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1079

if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1080

pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1132

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1133

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1154

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1155

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1156

if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1157

pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1201

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1202

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1230

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1231

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1232

if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1233

pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1279

return adev->nbio.funcs->get_rev_id(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2334

if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2336

r = adev->ip_blocks[i].version->funcs->set_clockgating_state(

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2341

adev->ip_blocks[i].version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2369

if (!adev->ip_blocks[i].version->funcs->set_powergating_state)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2371

r = adev->ip_blocks[i].version->funcs->set_powergating_state(

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2376

adev->ip_blocks[i].version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2400

if (adev->ip_blocks[i].version->funcs->get_clockgating_state)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2401

adev->ip_blocks[i].version->funcs->get_clockgating_state(

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2424

if (adev->ip_blocks[i].version->funcs->wait_for_idle) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2425

r = adev->ip_blocks[i].version->funcs->wait_for_idle(

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2567

ip_block_version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2917

adev->ip_blocks[i].version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2919

} else if (ip_block->version->funcs->early_init) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2920

r = ip_block->version->funcs->early_init(ip_block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2926

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3008

r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3012

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3035

r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3039

adev->ip_blocks[i].version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3075

r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3080

.version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3114

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3187

if (adev->ip_blocks[i].version->funcs->sw_init) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3188

r = adev->ip_blocks[i].version->funcs->sw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

319

if (ip_block->version->funcs->suspend) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3192

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

320

r = ip_block->version->funcs->suspend(ip_block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3205

r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3225

r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

324

ip_block->version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

337

if (ip_block->version->funcs->resume) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

338

r = ip_block->version->funcs->resume(ip_block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

342

ip_block->version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3444

adev->ip_blocks[i].version->funcs->set_clockgating_state) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3446

r = adev->ip_blocks[i].version->funcs->set_clockgating_state(&adev->ip_blocks[i],

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3451

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3485

adev->ip_blocks[i].version->funcs->set_powergating_state) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3487

r = adev->ip_blocks[i].version->funcs->set_powergating_state(&adev->ip_blocks[i],

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3492

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3556

if (adev->ip_blocks[i].version->funcs->late_init) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3557

r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3561

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3637

if (!ip_block->version->funcs->hw_fini) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3639

ip_block->version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3641

r = ip_block->version->funcs->hw_fini(ip_block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3646

ip_block->version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3684

if (!adev->ip_blocks[i].version->funcs->early_fini)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3687

r = adev->ip_blocks[i].version->funcs->early_fini(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3691

adev->ip_blocks[i].version->funcs->name, r);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3757

if (adev->ip_blocks[i].version->funcs->sw_fini) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3758

r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

376

if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3763

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

377

pkg_type = adev->smuio.funcs->get_pkg_type(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3776

if (adev->ip_blocks[i].version->funcs->late_fini)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3777

adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3928

(adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4010

r = block->version->funcs->hw_init(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4013

block->version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4050

r = block->version->funcs->hw_init(block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4055

block->version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4716

r = adev->gfxhub.funcs->get_xgmi_info(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5320

if (!adev->ip_blocks[i].version->funcs->prepare_suspend)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5322

r = adev->ip_blocks[i].version->funcs->prepare_suspend(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5346

if (!adev->ip_blocks[i].version->funcs->complete)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5348

adev->ip_blocks[i].version->funcs->complete(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5429

r = adev->gfxhub.funcs->get_xgmi_info(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5436

adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5581

if (adev->ip_blocks[i].version->funcs->check_soft_reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5583

adev->ip_blocks[i].version->funcs->check_soft_reset(

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5586

dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5612

adev->ip_blocks[i].version->funcs->pre_soft_reset) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5613

r = adev->ip_blocks[i].version->funcs->pre_soft_reset(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5674

adev->ip_blocks[i].version->funcs->soft_reset) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5675

r = adev->ip_blocks[i].version->funcs->soft_reset(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5703

adev->ip_blocks[i].version->funcs->post_soft_reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5704

r = adev->ip_blocks[i].version->funcs->post_soft_reset(&adev->ip_blocks[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5920

u32 memsize = adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6031

if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6032

tmp_adev->ip_blocks[i].version->funcs

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7107

adev->nbio.funcs->enable_doorbell_interrupt)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7108

adev->nbio.funcs->enable_doorbell_interrupt(adev, false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7126

adev->nbio.funcs->enable_doorbell_interrupt)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7127

adev->nbio.funcs->enable_doorbell_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7129

if (amdgpu_passthrough(adev) && adev->nbio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7130

adev->nbio.funcs->clear_doorbell_interrupt)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7131

adev->nbio.funcs->clear_doorbell_interrupt(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7513

if (ring && ring->funcs->emit_hdp_flush)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7586

address = adev->nbio.funcs->get_pcie_port_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7587

data = adev->nbio.funcs->get_pcie_port_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7602

address = adev->nbio.funcs->get_pcie_port_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7603

data = adev->nbio.funcs->get_pcie_port_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7691

if (ring->funcs->type != AMDGPU_RING_TYPE_GFX &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7692

ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7836

!amdgpu_sriov_vf(ring->adev) && ring->funcs->soft_recovery)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

896

adev->gfx.rlc.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

897

adev->gfx.rlc.funcs->is_rlcg_access_range) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

898

if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

964

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

965

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

988

if (unlikely(!adev->nbio.funcs)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

992

pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

993

pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

997

if (unlikely(!adev->nbio.funcs))

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

61

const struct amdgpu_df_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2921

adev->nbio.funcs = &nbio_v6_1_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2927

adev->nbio.funcs = &nbio_v7_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2933

adev->nbio.funcs = &nbio_v7_4_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2938

adev->nbio.funcs = &nbio_v7_9_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2945

adev->nbio.funcs = &nbio_v7_11_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2953

adev->nbio.funcs = &nbio_v7_2_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2964

adev->nbio.funcs = &nbio_v2_3_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2970

adev->nbio.funcs = &nbio_v4_3_sriov_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2972

adev->nbio.funcs = &nbio_v4_3_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2977

adev->nbio.funcs = &nbio_v7_7_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2981

adev->nbio.funcs = &nbif_v6_3_1_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2999

adev->hdp.funcs = &hdp_v4_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3007

adev->hdp.funcs = &hdp_v5_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3010

adev->hdp.funcs = &hdp_v5_2_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3016

adev->hdp.funcs = &hdp_v6_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3019

adev->hdp.funcs = &hdp_v7_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3029

adev->df.funcs = &df_v3_6_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3036

adev->df.funcs = &df_v1_7_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3039

adev->df.funcs = &df_v4_3_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3042

adev->df.funcs = &df_v4_6_2_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3046

adev->df.funcs = &df_v4_15_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3058

adev->smuio.funcs = &smuio_v9_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3066

adev->smuio.funcs = &smuio_v11_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3076

adev->smuio.funcs = &smuio_v11_0_6_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3079

adev->smuio.funcs = &smuio_v13_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3083

adev->smuio.funcs = &smuio_v13_0_3_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3084

if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3092

adev->smuio.funcs = &smuio_v13_0_6_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3095

adev->smuio.funcs = &smuio_v14_0_2_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3106

adev->lsdma.funcs = &lsdma_v6_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

3110

adev->lsdma.funcs = &lsdma_v7_0_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

156

adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

28

#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

29

#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

30

#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

31

#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

32

#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

33

#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

34

#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

35

#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

36

#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

37

#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

38

#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

1006

if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

1007

ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

1014

if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

448

if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

544

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1074

BUG_ON(!ring->funcs->emit_rreg);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1142

BUG_ON(!ring->funcs->emit_wreg);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1495

for (i = 0; i <= ring->funcs->align_mask; ++i)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1496

ib->ptr[i] = ring->funcs->nop;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1497

ib->length_dw = ring->funcs->align_mask + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1800

(xcp_mgr->funcs && xcp_mgr->funcs->switch_partition_mode);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1826

(xcp_mgr->funcs && xcp_mgr->funcs->switch_partition_mode);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

819

if (adev->gfx.funcs->init_spm_golden) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

942

if (adev->gfx.cp_ecc_error_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

469

const struct amdgpu_gfx_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

549

#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

550

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

551

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

552

#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

553

#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfxhub.h

44

const struct amdgpu_gfxhub_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1415

if (!adev->psp.funcs) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1503

if (adev->nbio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1504

adev->nbio.funcs->get_memory_partition_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1505

mode = adev->nbio.funcs->get_memory_partition_mode(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

707

job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;

sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.c

55

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.c

60

if (adev->nbio.funcs->get_memsize)

sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.c

61

adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.h

42

const struct amdgpu_hdp_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

184

(!ring->funcs->secure_submission_supported)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

189

alloc_size = ring->funcs->emit_frame_size + num_ibs *

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

190

ring->funcs->emit_ib_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

199

if (ring->funcs->emit_pipeline_sync && job &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

211

if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

212

ring->funcs->emit_mem_sync(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

214

if (ring->funcs->emit_wave_limit &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

216

ring->funcs->emit_wave_limit(ring, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

218

if (ring->funcs->insert_start)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

219

ring->funcs->insert_start(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

231

if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

235

if (ring->funcs->init_cond_exec)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

244

if (job && ring->funcs->emit_cntxcntl) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

253

if (job && ring->funcs->emit_frame_cntl) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

261

if (job && ring->funcs->emit_frame_cntl) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

273

if (job && ring->funcs->emit_frame_cntl)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

287

if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

302

if (ring->funcs->insert_end)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

303

ring->funcs->insert_end(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

308

if (job && ring->funcs->emit_switch_buffer)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

311

if (ring->funcs->emit_wave_limit &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

313

ring->funcs->emit_wave_limit(ring, false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

426

if (!ring->sched.ready || !ring->funcs->test_ib)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

430

ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

434

if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

435

ring->funcs->type == AMDGPU_RING_TYPE_VCE ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

436

ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

437

ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

438

ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

439

ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)

sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h

54

const struct amdgpu_imu_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

138

if (!src || !src->funcs->set || !src->num_types)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

142

r = src->funcs->set(adev, src, k,

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

407

if (!source->funcs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

492

r = src->funcs->process(adev, src, &entry);

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

557

r = src->funcs->set(adev, src, type, state);

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

584

if (!src || !src->funcs || !src->funcs->set)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

613

if (!src->enabled_types || !src->funcs->set)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

647

if (!src->enabled_types || !src->funcs->set)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

681

if (!src->enabled_types || !src->funcs->set)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h

64

const struct amdgpu_irq_src_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

336

.funcs = &isp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

344

.funcs = &isp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

49

if (isp->funcs->hw_init != NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

50

return isp->funcs->hw_init(isp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

65

if (isp->funcs->hw_fini != NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

66

return isp->funcs->hw_fini(isp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.h

46

const struct isp_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

135

ring->funcs->reset) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

43

if (adev->ip_blocks[i].version->funcs->dump_ip_state)

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

44

adev->ip_blocks[i].version->funcs

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

299

!adev->jpeg.inst[i].ras_poison_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1031

if (adev->gfx.funcs->get_gfx_shadow_info) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

383

if (adev->gfx.funcs->get_gfx_shadow_info) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

386

adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

59

ret = adev->lsdma.funcs->copy_mem(adev, src_addr, dst_addr, current_copy_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

83

ret = adev->lsdma.funcs->fill_mem(adev, dst_addr, data, current_fill_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

28

const struct amdgpu_lsdma_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

274

r = adev->mes.funcs->suspend_gang(&adev->mes, &input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

298

r = adev->mes.funcs->resume_gang(&adev->mes, &input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

314

queue_input.queue_type = ring->funcs->type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

322

r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

339

queue_input.queue_type = ring->funcs->type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

347

r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

365

queue_input.queue_type = ring->funcs->type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

375

if (ring->funcs->type == AMDGPU_RING_TYPE_GFX)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

379

r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

417

r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

457

if (!adev->mes.funcs->misc_op) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

463

r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

486

if (!adev->mes.funcs->misc_op) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

493

r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

515

if (!adev->mes.funcs->misc_op) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

522

r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

541

if (!adev->mes.funcs->misc_op) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

565

r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

580

if (!adev->mes.funcs->misc_op) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

592

r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

711

if (!adev->mes.funcs->misc_op) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

718

r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

146

const struct amdgpu_mes_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h

70

const struct amdgpu_mmhub_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

343

const struct amdgpu_display_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c

51

if (adev->nbio.funcs && adev->nbio.funcs->get_pcie_replay_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c

52

return adev->nbio.funcs->get_pcie_replay_count(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c

61

(!adev->nbio.funcs || !adev->nbio.funcs->get_pcie_replay_count))

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

114

const struct amdgpu_nbio_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

675

bo->tbo.base.funcs = &amdgpu_gem_object_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

236

if ((!pe->adev->df.funcs) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

237

(!pe->adev->df.funcs->pmc_start))

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

247

target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

256

pe->adev->df.funcs->pmc_start(pe->adev, hwc->config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

275

if ((!pe->adev->df.funcs) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

276

(!pe->adev->df.funcs->pmc_get_count))

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

284

pe->adev->df.funcs->pmc_get_count(pe->adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

307

if ((!pe->adev->df.funcs) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

308

(!pe->adev->df.funcs->pmc_stop))

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

314

pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

340

if ((!pe->adev->df.funcs) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

341

(!pe->adev->df.funcs->pmc_start))

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

360

target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

389

if ((!pe->adev->df.funcs) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

390

(!pe->adev->df.funcs->pmc_stop))

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

398

pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2444

if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2445

ret = psp->funcs->wait_for_bootloader(psp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2452

if (psp->funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2453

psp->funcs->get_ras_capability) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2454

return psp->funcs->get_ras_capability(psp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2467

if (psp->funcs && psp->funcs->is_reload_needed)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2468

return psp->funcs->is_reload_needed(psp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2496

(psp->funcs->bootloader_load_kdb != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2505

(psp->funcs->bootloader_load_spl != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2514

(psp->funcs->bootloader_load_sysdrv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2523

(psp->funcs->bootloader_load_soc_drv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2532

(psp->funcs->bootloader_load_intf_drv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2541

(psp->funcs->bootloader_load_dbg_drv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2550

(psp->funcs->bootloader_load_ras_drv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2559

(psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2568

(psp->funcs->bootloader_load_spdm_drv != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2577

(psp->funcs->bootloader_load_sos != NULL)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4492

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4500

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4508

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4516

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4524

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4532

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4540

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4548

.funcs = &psp_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

365

const struct psp_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

458

#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

459

#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

460

#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

462

((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

464

((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

466

((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

468

((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

470

((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

472

((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

474

((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

476

((psp)->funcs->bootloader_load_ras_drv ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

477

(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

479

((psp)->funcs->bootloader_load_ipkeymgr_drv ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

480

(psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

482

((psp)->funcs->bootloader_load_spdm_drv ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

483

(psp)->funcs->bootloader_load_spdm_drv((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

485

((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

487

((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

489

((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

491

((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

493

#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

494

#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

497

((psp)->funcs->load_usbc_pd_fw ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

498

(psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

501

((psp)->funcs->read_usbc_pd_fw ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

502

(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

505

((psp)->funcs->update_spirom ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

506

(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

509

((psp)->funcs->dump_spirom ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

510

(psp)->funcs->dump_spirom((psp), fw_pri_mc_addr) : -EINVAL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

513

((psp)->funcs->vbflash_stat ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

514

(psp)->funcs->vbflash_stat((psp)) : -EINVAL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

517

((psp)->funcs->fatal_error_recovery_quirk ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

518

(psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

521

((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

524

((psp)->funcs->reg_program_no_ring ? \

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

525

(psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1230

adev->smuio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1231

adev->smuio.funcs->get_socket_id &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1232

adev->smuio.funcs->get_die_id) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1236

adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1237

adev->smuio.funcs->get_die_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1253

adev->smuio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1254

adev->smuio.funcs->get_socket_id &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1255

adev->smuio.funcs->get_die_id) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1259

adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1260

adev->smuio.funcs->get_die_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1276

adev->smuio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1277

adev->smuio.funcs->get_socket_id &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1278

adev->smuio.funcs->get_die_id) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1282

adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1283

adev->smuio.funcs->get_die_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2857

if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2858

socket = adev->smuio.funcs->get_socket_id(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2885

if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2886

socket = adev->smuio.funcs->get_socket_id(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3924

} else if (adev->df.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3925

adev->df.funcs->query_ras_poison_mode &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3929

adev->df.funcs->query_ras_poison_mode(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4205

if (adev->smuio.funcs &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4206

adev->smuio.funcs->get_socket_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4207

con->features |= ((adev->smuio.funcs->get_socket_id(adev)) <<

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

116

ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

121

if (ring->funcs->begin_use)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

122

ring->funcs->begin_use(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

142

memset32(&ring->ring[occupied], ring->funcs->nop, chunk1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

145

memset32(ring->ring, ring->funcs->nop, chunk2);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

162

while (ib->length_dw & ring->funcs->align_mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

163

ib->ptr[ib->length_dw++] = ring->funcs->nop;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

183

count = ring->funcs->align_mask + 1 -

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

184

(ring->wptr & ring->funcs->align_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

185

count &= ring->funcs->align_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

188

ring->funcs->insert_nop(ring, count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

193

if (ring->funcs->end_use)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

194

ring->funcs->end_use(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

208

if (ring->funcs->end_use)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

209

ring->funcs->end_use(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

249

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

251

if (ring->funcs->type == AMDGPU_RING_TYPE_MES)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

331

if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

338

max_ibs_dw = ring->funcs->emit_frame_size +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

339

amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

340

max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

354

ring->ptr_mask = ring->funcs->support_64bit_ptrs ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

367

r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_bytes,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

384

if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

385

hw_ip = ring->funcs->type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

465

if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

475

ring->funcs->soft_recovery(ring, vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

512

if (ring->funcs->type == AMDGPU_RING_TYPE_CPER)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

531

if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

572

if (ring->funcs->type == AMDGPU_RING_TYPE_CPER)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

586

if (ring->funcs->type == AMDGPU_RING_TYPE_CPER)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

703

bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

705

bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

723

prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

742

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

745

mqd_mgr = &adev->mqds[ring->funcs->type];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

829

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

85

ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

96

if (ring->funcs->begin_use)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

97

ring->funcs->begin_use(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

301

const struct amdgpu_ring_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

424

#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

425

#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

426

#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

427

#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

428

#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

429

#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

430

#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

431

#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

432

#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

433

#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

434

#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

435

#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

436

#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

437

#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

438

#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

439

#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

440

#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

441

#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

442

#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

443

#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

444

#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

445

#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

446

#define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

447

#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

448

#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

449

#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

450

#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

451

#define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

484

memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

531

if (!ring->funcs->init_cond_exec)

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

134

adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

197

max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

44

if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

50

adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

69

if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

75

adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

295

const struct amdgpu_rlc_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

541

if (sdma_instance->funcs->soft_reset_kernel_queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

542

return sdma_instance->funcs->soft_reset_kernel_queue(adev, instance_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

580

if (sdma_instance->funcs->stop_kernel_queue) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

581

sdma_instance->funcs->stop_kernel_queue(gfx_ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

583

sdma_instance->funcs->stop_kernel_queue(page_ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

593

if (sdma_instance->funcs->start_kernel_queue) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

594

sdma_instance->funcs->start_kernel_queue(gfx_ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

596

sdma_instance->funcs->start_kernel_queue(page_ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

77

const struct amdgpu_sdma_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

51

const struct amdgpu_smuio_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

596

const struct amdgpu_psp_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

141

const struct amdgpu_umc_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

327

adev->umsch_mm.ring.funcs = &umsch_v4_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

549

.funcs = &umsch_mm_v4_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

139

const struct umsch_mm_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

212

((umsch)->funcs->set_hw_resources ? (umsch)->funcs->set_hw_resources((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

214

((umsch)->funcs->add_queue ? (umsch)->funcs->add_queue((umsch), (input)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

216

((umsch)->funcs->remove_queue ? (umsch)->funcs->remove_queue((umsch), (input)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

219

((umsch)->funcs->set_regs ? (umsch)->funcs->set_regs((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

221

((umsch)->funcs->init_microcode ? (umsch)->funcs->init_microcode((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

223

((umsch)->funcs->load_microcode ? (umsch)->funcs->load_microcode((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

226

((umsch)->funcs->ring_init ? (umsch)->funcs->ring_init((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

228

((umsch)->funcs->ring_start ? (umsch)->funcs->ring_start((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

230

((umsch)->funcs->ring_stop ? (umsch)->funcs->ring_stop((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

232

((umsch)->funcs->ring_fini ? (umsch)->funcs->ring_fini((umsch)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1297

!adev->vcn.inst[i].ras_poison_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

516

if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

544

ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

776

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

806

if (ring->funcs->emit_gds_switch && job->gds_switch_needed)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

836

bool gds_switch_needed = ring->funcs->emit_gds_switch &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

859

gds_switch_needed &= !!ring->funcs->emit_gds_switch;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

860

vm_flush_needed &= !!ring->funcs->emit_vm_flush &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

863

ring->funcs->emit_wreg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

867

ring->funcs->emit_cleaner_shader && job->base.s_fence &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

875

if (ring->funcs->init_cond_exec)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

883

ring->funcs->emit_cleaner_shader(ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

893

if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

894

adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

896

if (ring->funcs->emit_gds_switch &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

946

if (ring->funcs->emit_switch_buffer) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

1019

.funcs = &vpe_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

491

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

494

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

998

adev->vpe.ring.funcs = &vpe_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

101

((vpe)->funcs->set_regs ? (vpe)->funcs->set_regs((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

103

((vpe)->funcs->irq_init ? (vpe)->funcs->irq_init((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

105

((vpe)->funcs->init_microcode ? (vpe)->funcs->init_microcode((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

107

((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

67

const struct vpe_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

93

#define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ? (vpe)->funcs->ring_init((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

94

#define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ? (vpe)->funcs->ring_start((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

95

#define vpe_ring_stop(vpe) ((vpe)->funcs->ring_stop ? (vpe)->funcs->ring_stop((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

96

#define vpe_ring_fini(vpe) ((vpe)->funcs->ring_fini ? (vpe)->funcs->ring_fini((vpe)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

99

((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

162

ret = xcp_mgr->funcs->get_ip_details(xcp_mgr, i, j,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

172

if (xcp_mgr->funcs->get_xcp_mem_id) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

173

ret = xcp_mgr->funcs->get_xcp_mem_id(

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

194

if (!xcp_mgr->funcs || !xcp_mgr->funcs->switch_partition_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

203

ret = xcp_mgr->funcs->switch_partition_mode(xcp_mgr, mode, &num_xcps);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

207

if (xcp_mgr->funcs->query_partition_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

243

if (!xcp_mgr->funcs || !xcp_mgr->funcs->query_partition_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

266

mode = xcp_mgr->funcs->query_partition_mode(xcp_mgr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

343

xcp_mgr->funcs = xcp_funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

531

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

534

(ring->funcs->type == AMDGPU_RING_TYPE_CPER))

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

539

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

553

dev_err(adev->dev, "Not support ring type %d!", ring->funcs->type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

562

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

576

.gpu_sched[ring->funcs->type][ring->hw_prio].num_scheds;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

577

adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[ring->funcs->type][ring->hw_prio]

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

580

ring->name, sel_xcp_id, ring->funcs->type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

607

if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

608

ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

623

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

624

ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

791

if (xcp_mgr->funcs && xcp_mgr->funcs->get_xcp_res_info)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

792

return xcp_mgr->funcs->get_xcp_res_info(xcp_mgr, mode, xcp_cfg);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

121

struct amdgpu_xcp_mgr_funcs *funcs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1569

.socket_id = adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

550

if ((!adev->df.funcs) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

551

(!adev->df.funcs->get_fica) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

552

(!adev->df.funcs->set_fica))

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

555

fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

559

fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

564

adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

125

if (adev->nbio.funcs->get_compute_partition_mode) {

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

126

mode = adev->nbio.funcs->get_compute_partition_mode(adev);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

425

if (adev->gfx.funcs->switch_partition_mode)

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

426

adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

90

if (adev->gfx.funcs->get_xccs_per_xcp)

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

91

num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev);

sys/dev/pci/drm/amd/amdgpu/cik.c

1860

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/cik.c

1871

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/cik.c

2194

.funcs = &cik_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

449

.funcs = &cik_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1253

adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1270

adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1271

adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1366

.funcs = &cik_sdma_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

206

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

209

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

448

.funcs = &cz_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2811

adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3632

adev->mode_info.funcs = &dce_v10_0_display_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3656

adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3659

adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3662

adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3670

.funcs = &dce_v10_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3678

.funcs = &dce_v10_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2764

adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3528

adev->mode_info.funcs = &dce_v6_0_display_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3552

adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3555

adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3558

adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3567

.funcs = &dce_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3576

.funcs = &dce_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2725

adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3540

adev->mode_info.funcs = &dce_v8_0_display_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3564

adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3567

adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3570

adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3578

.funcs = &dce_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3586

.funcs = &dce_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3594

.funcs = &dce_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3602

.funcs = &dce_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3610

.funcs = &dce_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

100

adev->df.funcs->enable_broadcast_mode(adev, false);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

72

fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

85

adev->df.funcs->enable_broadcast_mode(adev, true);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

102

address = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

103

data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

124

address = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

125

data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

143

address = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

144

data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

224

adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

226

adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

299

fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

313

adev->df.funcs->enable_broadcast_mode(adev, true);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

332

adev->df.funcs->enable_broadcast_mode(adev, false);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

51

address = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

52

data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

74

address = adev->nbio.funcs->get_pcie_index_offset(adev);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

75

data = adev->nbio.funcs->get_pcie_data_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10001

adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10004

adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10007

adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10010

adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10027

adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10031

adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10247

.funcs = &gfx_v10_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3733

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3771

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3798

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4904

if (adev->gfx.rlc.funcs) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4905

if (adev->gfx.rlc.funcs->init) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4906

r = adev->gfx.rlc.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5449

adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5581

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5605

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7794

adev->gfx.funcs = &gfx_v10_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8618

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8636

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8637

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8748

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8774

if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9009

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9037

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9501

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9961

adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9964

adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9967

adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9998

adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1518

if (adev->gfx.imu.funcs->load_microcode)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1519

adev->gfx.imu.funcs->load_microcode(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1521

if (adev->gfx.imu.funcs->setup_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1522

adev->gfx.imu.funcs->setup_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1523

if (adev->gfx.imu.funcs->start_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1524

adev->gfx.imu.funcs->start_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2236

adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2465

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2482

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

374

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

416

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

448

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4656

r = adev->gfxhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4664

adev->gfxhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4749

if (adev->gfx.imu.funcs) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4751

if (adev->gfx.imu.funcs->program_rlc_ram)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4752

adev->gfx.imu.funcs->program_rlc_ram(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4760

if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4761

if (adev->gfx.imu.funcs->load_microcode)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4762

adev->gfx.imu.funcs->load_microcode(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4763

if (adev->gfx.imu.funcs->setup_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4764

adev->gfx.imu.funcs->setup_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4765

if (adev->gfx.imu.funcs->start_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4766

adev->gfx.imu.funcs->start_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4816

if (adev->nbio.funcs->gc_doorbell_init)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4817

adev->nbio.funcs->gc_doorbell_init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4918

adev->gfxhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5239

adev->gfx.funcs = &gfx_v11_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

547

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5596

&& ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5597

|| (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

574

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5836

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5854

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5855

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5963

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5989

if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

611

ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6274

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6302

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7332

adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7335

adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7338

adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7368

adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7371

adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7374

adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7377

adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7380

adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7391

adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7396

adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7539

.funcs = &gfx_v11_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

805

if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

806

err = adev->gfx.imu.funcs->init_microcode(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

919

if (adev->gfx.rlc.funcs->update_spm_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

920

adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1325

if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1327

if (adev->gfx.imu.funcs->load_microcode)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1328

adev->gfx.imu.funcs->load_microcode(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1330

if (adev->gfx.imu.funcs->setup_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1331

adev->gfx.imu.funcs->setup_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1332

if (adev->gfx.imu.funcs->start_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1333

adev->gfx.imu.funcs->start_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1901

adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2080

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2097

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

313

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3520

r = adev->gfxhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3528

adev->gfxhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

355

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3613

if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3615

if (adev->gfx.imu.funcs->program_rlc_ram)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3616

adev->gfx.imu.funcs->program_rlc_ram(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3624

if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3625

if (adev->gfx.imu.funcs->load_microcode)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3626

adev->gfx.imu.funcs->load_microcode(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3627

if (adev->gfx.imu.funcs->setup_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3628

adev->gfx.imu.funcs->setup_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3629

if (adev->gfx.imu.funcs->start_imu)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3630

adev->gfx.imu.funcs->start_imu(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3677

if (adev->nbio.funcs->gc_doorbell_init)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3678

adev->nbio.funcs->gc_doorbell_init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3776

adev->gfxhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3826

if (adev->smuio.funcs &&

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3827

adev->smuio.funcs->get_gpu_clock_counter)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3828

clock = adev->smuio.funcs->get_gpu_clock_counter(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3856

adev->gfx.funcs = &gfx_v12_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

386

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3979

&& ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3980

|| (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4391

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4409

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4410

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4489

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4515

if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4659

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

467

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4687

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

504

ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5084

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5596

adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5599

adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5602

adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5628

adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5631

adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5634

adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5637

adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5647

adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5652

adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5782

.funcs = &gfx_v12_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

649

if (adev->gfx.imu.funcs) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

650

if (adev->gfx.imu.funcs->init_microcode) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

651

err = adev->gfx.imu.funcs->init_microcode(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

762

if (adev->gfx.rlc.funcs->update_spm_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

763

adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2288

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2314

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2344

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2513

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2514

adev->gfx.rlc.funcs->reset(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2542

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3032

adev->gfx.funcs = &gfx_v6_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3033

adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3064

r = adev->gfx.rlc.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3135

r = adev->gfx.rlc.funcs->resume(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3153

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3511

adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3513

adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3534

adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3537

adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3540

adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3601

.funcs = &gfx_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2071

int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2073

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3108

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3150

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3182

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3247

if (adev->gfx.rlc.funcs->update_spm_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3248

adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3432

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3438

adev->gfx.rlc.funcs->reset(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3469

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4108

adev->gfx.funcs = &gfx_v7_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4109

adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4353

r = adev->gfx.rlc.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4444

adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4446

r = adev->gfx.rlc.funcs->resume(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4464

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4545

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4979

adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4981

adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5002

adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5005

adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5008

adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5082

.funcs = &gfx_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5090

.funcs = &gfx_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5098

.funcs = &gfx_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1276

if (adev->gfx.rlc.funcs->update_spm_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1277

adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1954

r = adev->gfx.rlc.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3858

adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4076

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4077

adev->gfx.rlc.funcs->reset(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4079

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4390

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4540

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4752

r = adev->gfx.rlc.funcs->resume(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4872

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4964

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5091

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5231

adev->gfx.funcs = &gfx_v8_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6003

if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6004

(ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6150

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6168

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6328

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6953

adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6956

adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6959

adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6990

adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6993

adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6996

adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6999

adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7002

adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7007

adev->gfx.rlc.funcs = &iceland_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7107

.funcs = &gfx_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7116

.funcs = &gfx_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1014

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1148

adev->smuio.funcs->get_die_id(adev));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2314

if (adev->gfx.rlc.funcs) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2315

if (adev->gfx.rlc.funcs->init) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2316

r = adev->gfx.rlc.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2770

adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3200

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3236

adev->gfx.rlc.funcs->start(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3536

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3671

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4033

r = adev->gfx.rlc.funcs->resume(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4096

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4168

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4204

BUG_ON(!ring->funcs->emit_rreg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4796

adev->gfx.funcs = &gfx_v9_0_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5384

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5402

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5403

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5586

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5601

if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5879

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5907

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5909

bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7165

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7595

adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7598

adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7602

adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7606

adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7638

adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7641

adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7644

adev->gfx.bad_op_irq.funcs = &gfx_v9_0_bad_op_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7647

adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7650

adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7664

adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7833

.funcs = &gfx_v9_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

956

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

986

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1094

r = adev->gfx.rlc.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1457

if (adev->gfx.rlc.funcs->update_spm_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1458

adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1816

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1950

if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

205

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

235

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2364

r = adev->gfx.rlc.funcs->resume(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2463

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

262

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2826

if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2844

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2845

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2920

int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3018

switch (ring->funcs->type) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4394

.socket_id = adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4564

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4813

adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4816

adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4844

adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4847

adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4850

adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4853

adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4858

adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4983

.funcs = &gfx_v9_4_3_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

803

if (adev->psp.funcs) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

922

adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1009

if (adev->umc.funcs && adev->umc.funcs->init_registers)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1010

adev->umc.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1025

adev->gfxhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1026

adev->mmhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1043

if (adev->gmc.ecc_irq.funcs &&

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1099

r = adev->mmhub.funcs->set_clockgating(adev, state);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1117

adev->mmhub.funcs->get_clockgating(adev, flags);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1153

.funcs = &gmc_v10_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

198

adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

202

adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

600

adev->mmhub.funcs = &mmhub_v2_3_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

603

adev->mmhub.funcs = &mmhub_v2_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

619

adev->gfxhub.funcs = &gfxhub_v2_1_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

622

adev->gfxhub.funcs = &gfxhub_v2_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

670

base = adev->gfxhub.funcs->get_fb_location(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

682

adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

704

adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

717

adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

772

adev->gfxhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

774

adev->mmhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

952

r = adev->gfxhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

957

r = adev->mmhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

961

adev->hdp.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

969

adev->gfxhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

970

adev->mmhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

996

if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

997

adev->gfxhub.funcs->utcl2_harvest(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

1038

r = adev->mmhub.funcs->set_clockgating(adev, state);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

1049

adev->mmhub.funcs->get_clockgating(adev, flags);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

1082

.funcs = &gmc_v11_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

194

adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

198

adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

594

adev->mmhub.funcs = &mmhub_v3_0_1_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

597

adev->mmhub.funcs = &mmhub_v3_0_2_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

602

adev->mmhub.funcs = &mmhub_v3_3_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

605

adev->mmhub.funcs = &mmhub_v3_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

614

adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

620

adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

623

adev->gfxhub.funcs = &gfxhub_v3_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

670

base = adev->mmhub.funcs->get_fb_location(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

684

adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

702

adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

715

adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

761

adev->mmhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

763

adev->gfxhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

928

r = adev->mmhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

937

adev->mmhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

961

if (adev->umc.funcs && adev->umc.funcs->init_registers)

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

962

adev->umc.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

976

adev->mmhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

991

if (adev->gmc.ecc_irq.funcs &&

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

1025

r = adev->mmhub.funcs->set_clockgating(adev, state);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

1036

adev->mmhub.funcs->get_clockgating(adev, flags);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

1069

.funcs = &gmc_v12_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

187

adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

191

adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

373

adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

377

adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

624

adev->mmhub.funcs = &mmhub_v4_1_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

636

adev->gfxhub.funcs = &gfxhub_v12_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

684

base = adev->mmhub.funcs->get_fb_location(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

696

adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

714

adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

728

adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

775

adev->mmhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

777

adev->gfxhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

917

r = adev->mmhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

926

adev->mmhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

948

if (adev->umc.funcs && adev->umc.funcs->init_registers)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

949

adev->umc.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

963

adev->mmhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

978

if (adev->gmc.ecc_irq.funcs &&

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1163

adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1171

.funcs = &gmc_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1382

adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1390

.funcs = &gmc_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1398

.funcs = &gmc_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1753

adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1761

.funcs = &gmc_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1769

.funcs = &gmc_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1777

.funcs = &gmc_v8_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1387

if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested &&

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1388

adev->nbio.funcs->is_nps_switch_requested(adev)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1419

adev->umc.funcs = &umc_v6_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1448

if (1 & adev->smuio.funcs->get_die_id(adev))

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1473

adev->mmhub.funcs = &mmhub_v9_4_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1476

adev->mmhub.funcs = &mmhub_v1_7_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1480

adev->mmhub.funcs = &mmhub_v1_8_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1483

adev->mmhub.funcs = &mmhub_v1_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1513

adev->gfxhub.funcs = &gfxhub_v1_2_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1515

adev->gfxhub.funcs = &gfxhub_v1_0_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1600

adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1605

adev->smuio.funcs->get_pkg_type(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1659

if (adev->df.funcs &&

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1660

adev->df.funcs->enable_ecc_force_par_wr_rmw)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1661

adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1680

u64 base = adev->mmhub.funcs->get_fb_location(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1695

adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1718

adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1752

adev->gfxhub.funcs->get_mc_fb_offset(adev) +

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1872

adev->gfxhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1874

adev->mmhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1908

if (adev->df.funcs &&

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1909

adev->df.funcs->get_hbm_channel_number) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1910

numchan = adev->df.funcs->get_hbm_channel_number(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2164

r = adev->gfxhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2169

r = adev->mmhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2211

if (adev->mmhub.funcs->update_power_gating)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2212

adev->mmhub.funcs->update_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2214

adev->hdp.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2226

adev->gfxhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2227

adev->mmhub.funcs->set_fault_enable_default(adev, value);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2235

if (adev->umc.funcs && adev->umc.funcs->init_registers)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2236

adev->umc.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2258

adev->gfxhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2259

adev->mmhub.funcs->gart_disable(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2279

if (adev->mmhub.funcs->update_power_gating)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2280

adev->mmhub.funcs->update_power_gating(adev, false);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2289

if (adev->gmc.ecc_irq.funcs &&

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2347

adev->mmhub.funcs->set_clockgating(adev, state);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2358

adev->mmhub.funcs->get_clockgating(adev, flags);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2392

.funcs = &gmc_v9_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

573

if (adev->gfx.funcs->ih_node_to_logical_xcc) {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

574

xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

761

adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

767

adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

47

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

33

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

33

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

44

if (adev->nbio.funcs->get_memsize)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

45

adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

440

.funcs = &iceland_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

334

adev->nbio.funcs->ih_control(adev);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

356

adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

563

adev->irq.self_irq.funcs = &ih_v6_0_self_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

816

.funcs = &ih_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

306

adev->nbio.funcs->ih_control(adev);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

327

adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

532

adev->irq.self_irq.funcs = &ih_v6_1_self_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

795

.funcs = &ih_v6_1_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

306

adev->nbio.funcs->ih_control(adev);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

327

adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

528

adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

786

.funcs = &ih_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_0.c

190

isp->funcs = &isp_v4_1_0_funcs;

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_1.c

376

isp->funcs = &isp_v4_1_1_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

307

if (ring->funcs->parse_cs)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

591

adev->jpeg.inst->ring_dec->funcs = &jpeg_v1_0_decode_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

601

adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

163

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

568

if (ring->funcs->parse_cs)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

835

adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

846

adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

854

.funcs = &jpeg_v2_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

219

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

763

adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

765

adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

789

adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

792

adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

801

.funcs = &jpeg_v2_5_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

809

.funcs = &jpeg_v2_6_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

178

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

627

adev->jpeg.inst->ring_dec->funcs = &jpeg_v3_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

638

adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

647

.funcs = &jpeg_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

198

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

792

adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

807

adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

810

adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

818

.funcs = &jpeg_v4_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1212

adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1239

adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1242

adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1250

.funcs = &jpeg_v4_0_3_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1457

adev->jpeg.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

402

adev->nbio.funcs->vcn_doorbell_range(

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

841

if (ring->funcs->parse_cs)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

515

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

843

adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

861

adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

870

.funcs = &jpeg_v4_0_5_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

166

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

713

adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

724

adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

732

.funcs = &jpeg_v5_0_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1077

adev->jpeg.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

278

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

913

adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_1_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

940

adev->jpeg.inst->irq.funcs = &jpeg_v5_0_1_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

943

adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v5_0_1_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

952

.funcs = &jpeg_v5_0_1_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

149

r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

173

r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

314

if (adev->gfx.funcs->get_gfx_shadow_info) {

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

315

adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true);

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

445

r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

481

r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1331

ring->funcs = &mes_v11_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1417

adev->mes.funcs = &mes_v11_0_funcs;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1750

.funcs = &mes_v11_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1519

ring->funcs = &mes_v12_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1604

adev->mes.funcs = &mes_v12_0_funcs;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1935

.funcs = &mes_v12_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

701

.socket_id = adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

405

adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

407

adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

475

adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

477

adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

581

adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

583

adev->virt.rcv_irq.funcs = &xgpu_vi_mailbox_rcv_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

329

adev->nbio.funcs->ih_control(adev);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

361

adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

541

adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

728

.funcs = &navi10_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

537

adev->nbio.ras_err_event_athub_irq.funcs =

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

618

adev->nbio.ras_err_event_athub_irq.funcs =

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

552

adev->nbio.ras_controller_irq.funcs =

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

570

adev->nbio.ras_err_event_athub_irq.funcs =

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

646

adev->nbio.ras_controller_irq.funcs =

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

664

adev->nbio.ras_err_event_athub_irq.funcs =

sys/dev/pci/drm/amd/amdgpu/nv.c

1000

adev->nbio.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

1005

if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))

sys/dev/pci/drm/amd/amdgpu/nv.c

1006

adev->nbio.funcs->remap_hdp_registers(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

1008

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/nv.c

1022

adev->nbio.funcs->enable_doorbell_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/nv.c

1023

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/nv.c

1059

adev->nbio.funcs->update_medium_grain_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/nv.c

1061

adev->nbio.funcs->update_medium_grain_light_sleep(adev,

sys/dev/pci/drm/amd/amdgpu/nv.c

1063

adev->hdp.funcs->update_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/nv.c

1065

adev->smuio.funcs->update_rom_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/nv.c

1088

adev->nbio.funcs->get_clockgating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/nv.c

1090

adev->hdp.funcs->get_clock_gating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/nv.c

1092

adev->smuio.funcs->get_clock_gating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/nv.c

308

return adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

430

u32 memsize = adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

519

if (adev->nbio.funcs->program_aspm)

sys/dev/pci/drm/amd/amdgpu/nv.c

520

adev->nbio.funcs->program_aspm(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

529

.funcs = &nv_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/nv.c

608

if (adev->gfx.funcs->update_perfmon_mgcg)

sys/dev/pci/drm/amd/amdgpu/nv.c

609

adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);

sys/dev/pci/drm/amd/amdgpu/nv.c

611

if (adev->nbio.funcs->enable_aspm &&

sys/dev/pci/drm/amd/amdgpu/nv.c

613

adev->nbio.funcs->enable_aspm(adev, !enter);

sys/dev/pci/drm/amd/amdgpu/nv.c

642

adev->nbio.funcs->set_reg_remap(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

972

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/nv.c

991

if (adev->nbio.funcs->apply_lc_spc_mode_wa)

sys/dev/pci/drm/amd/amdgpu/nv.c

992

adev->nbio.funcs->apply_lc_spc_mode_wa(adev);

sys/dev/pci/drm/amd/amdgpu/nv.c

994

if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)

sys/dev/pci/drm/amd/amdgpu/nv.c

995

adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

173

psp->funcs = &psp_v10_0_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

686

psp->funcs = &psp_v11_0_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

185

psp->funcs = &psp_v11_0_8_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

290

psp->funcs = &psp_v12_0_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

976

psp->funcs = &psp_v13_0_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

354

psp->funcs = &psp_v13_0_4_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

704

psp->funcs = &psp_v14_0_funcs;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

382

psp->funcs = &psp_v3_1_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1147

adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1164

adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1165

adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1260

.funcs = &sdma_v2_4_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

231

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

234

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1589

adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1606

adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1607

adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1703

.funcs = &sdma_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1712

.funcs = &sdma_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

407

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

410

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2482

adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2485

adev->sdma.instance[i].page.funcs =

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2538

adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2539

adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2540

adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2541

adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2542

adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2543

adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2544

adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2743

.funcs = &sdma_v4_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

791

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

794

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

869

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

870

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1462

adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2179

adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2182

adev->sdma.instance[i].page.funcs =

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2238

adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2239

adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2240

adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2241

adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2242

adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2243

adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2244

adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2245

adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2386

.funcs = &sdma_v4_4_2_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2466

.socket_id = adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

358

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

361

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

437

adev->nbio.funcs->get_hdp_flush_done_offset(adev),

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

438

adev->nbio.funcs->get_hdp_flush_req_offset(adev),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1403

adev->sdma.instance[i].funcs = &sdma_v5_0_sdma_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1975

adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1993

adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1994

adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2093

.funcs = &sdma_v5_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

414

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

417

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

503

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

504

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

782

adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1322

adev->sdma.instance[i].funcs = &sdma_v5_2_sdma_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1979

adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1997

adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1998

adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2097

.funcs = &sdma_v5_2_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

262

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

265

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

352

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

353

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

626

adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1788

adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1810

adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1811

adev->sdma.fence_irq.funcs = &sdma_v6_0_fence_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1812

adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1907

.funcs = &sdma_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

248

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

251

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

335

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

336

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

565

adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1722

adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1744

adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1745

adev->sdma.fence_irq.funcs = &sdma_v7_0_fence_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1746

adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1858

.funcs = &sdma_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

252

amdgpu_ring_write(ring, ring->funcs->nop |

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

255

amdgpu_ring_write(ring, ring->funcs->nop);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

339

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

340

amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

561

adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/si.c

1500

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/si.c

1511

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/si.c

2696

.funcs = &si_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/si_dma.c

753

adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

764

adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

859

.funcs = &si_dma_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/si_ih.c

312

.funcs = &si_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

100

if (adev->gfxhub.funcs->mode2_save_regs)

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

101

adev->gfxhub.funcs->mode2_save_regs(adev);

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

102

if (adev->gfxhub.funcs->halt)

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

103

adev->gfxhub.funcs->halt(adev);

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

161

if (adev->gfxhub.funcs->mode2_restore_regs)

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

162

adev->gfxhub.funcs->mode2_restore_regs(adev);

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

163

adev->gfxhub.funcs->init(adev);

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

164

r = adev->gfxhub.funcs->gart_enable(adev);

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

196

if (adev->ip_blocks[i].version->funcs->late_init) {

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

197

r = adev->ip_blocks[i].version->funcs->late_init(

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

202

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c

197

if (adev->ip_blocks[i].version->funcs->late_init) {

sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c

198

r = adev->ip_blocks[i].version->funcs->late_init(

sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c

203

adev->ip_blocks[i].version->funcs->name,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1246

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1258

if (adev->df.funcs &&

sys/dev/pci/drm/amd/amdgpu/soc15.c

1259

adev->df.funcs->sw_init)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1260

adev->df.funcs->sw_init(adev);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1269

if (adev->df.funcs &&

sys/dev/pci/drm/amd/amdgpu/soc15.c

1270

adev->df.funcs->sw_fini)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1271

adev->df.funcs->sw_fini(adev);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1282

adev->nbio.funcs->sdma_doorbell_range(adev, i,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1296

adev->nbio.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1301

if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))

sys/dev/pci/drm/amd/amdgpu/soc15.c

1302

adev->nbio.funcs->remap_hdp_registers(adev);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1305

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1327

adev->nbio.funcs->enable_doorbell_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1328

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1429

adev->nbio.funcs->update_medium_grain_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1431

adev->nbio.funcs->update_medium_grain_light_sleep(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1433

adev->hdp.funcs->update_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1439

adev->smuio.funcs->update_rom_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1441

adev->df.funcs->update_medium_grain_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1447

adev->nbio.funcs->update_medium_grain_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1449

adev->nbio.funcs->update_medium_grain_light_sleep(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1451

adev->hdp.funcs->update_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1460

adev->hdp.funcs->update_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1477

if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1478

adev->nbio.funcs->get_clockgating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1480

if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1481

adev->hdp.funcs->get_clock_gating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1499

if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1500

adev->smuio.funcs->get_clock_gating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1502

if (adev->df.funcs && adev->df.funcs->get_clockgating_state)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1503

adev->df.funcs->get_clockgating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc15.c

342

return adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/soc15.c

513

adev->nbio.funcs->enable_doorbell_interrupt(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc15.c

521

adev->nbio.funcs->enable_doorbell_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc15.c

703

if (adev->nbio.funcs->program_aspm)

sys/dev/pci/drm/amd/amdgpu/soc15.c

704

adev->nbio.funcs->program_aspm(adev);

sys/dev/pci/drm/amd/amdgpu/soc15.c

713

.funcs = &soc15_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/soc15.c

968

adev->nbio.funcs->set_reg_remap(adev);

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

41

((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

46

((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \

sys/dev/pci/drm/amd/amdgpu/soc21.c

1009

adev->nbio.funcs->get_clockgating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc21.c

1011

adev->hdp.funcs->get_clock_gating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc21.c

223

return adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

358

u32 memsize = adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

446

if (adev->nbio.funcs->program_aspm)

sys/dev/pci/drm/amd/amdgpu/soc21.c

447

adev->nbio.funcs->program_aspm(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

455

.funcs = &soc21_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/soc21.c

534

if (adev->gfx.funcs->update_perfmon_mgcg)

sys/dev/pci/drm/amd/amdgpu/soc21.c

535

adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);

sys/dev/pci/drm/amd/amdgpu/soc21.c

564

adev->nbio.funcs->set_reg_remap(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

848

adev->nbio.ras_err_event_athub_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/soc21.c

859

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc21.c

881

adev->nbio.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

886

if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))

sys/dev/pci/drm/amd/amdgpu/soc21.c

887

adev->nbio.funcs->remap_hdp_registers(adev);

sys/dev/pci/drm/amd/amdgpu/soc21.c

889

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc21.c

903

adev->nbio.funcs->enable_doorbell_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc21.c

904

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc21.c

910

adev->nbio.ras_err_event_athub_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/soc21.c

974

adev->nbio.funcs->update_medium_grain_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc21.c

976

adev->nbio.funcs->update_medium_grain_light_sleep(adev,

sys/dev/pci/drm/amd/amdgpu/soc21.c

978

adev->hdp.funcs->update_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc21.c

995

adev->lsdma.funcs->update_memory_power_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

248

(adev->nbio.funcs->program_aspm))

sys/dev/pci/drm/amd/amdgpu/soc24.c

249

adev->nbio.funcs->program_aspm(adev);

sys/dev/pci/drm/amd/amdgpu/soc24.c

257

.funcs = &soc24_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/soc24.c

342

if (adev->gfx.funcs->update_perfmon_mgcg)

sys/dev/pci/drm/amd/amdgpu/soc24.c

343

adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);

sys/dev/pci/drm/amd/amdgpu/soc24.c

369

adev->nbio.funcs->set_reg_remap(adev);

sys/dev/pci/drm/amd/amdgpu/soc24.c

450

adev->nbio.ras_err_event_athub_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/soc24.c

462

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc24.c

484

adev->nbio.funcs->init_registers(adev);

sys/dev/pci/drm/amd/amdgpu/soc24.c

489

if (adev->nbio.funcs->remap_hdp_registers)

sys/dev/pci/drm/amd/amdgpu/soc24.c

490

adev->nbio.funcs->remap_hdp_registers(adev);

sys/dev/pci/drm/amd/amdgpu/soc24.c

492

if (adev->df.funcs->hw_init)

sys/dev/pci/drm/amd/amdgpu/soc24.c

493

adev->df.funcs->hw_init(adev);

sys/dev/pci/drm/amd/amdgpu/soc24.c

496

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc24.c

510

adev->nbio.funcs->enable_doorbell_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc24.c

511

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);

sys/dev/pci/drm/amd/amdgpu/soc24.c

517

adev->nbio.ras_err_event_athub_irq.funcs)

sys/dev/pci/drm/amd/amdgpu/soc24.c

546

adev->nbio.funcs->update_medium_grain_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

548

adev->nbio.funcs->update_medium_grain_light_sleep(adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

550

adev->hdp.funcs->update_clock_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

567

adev->lsdma.funcs->update_memory_power_gating(adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

581

adev->nbio.funcs->get_clockgating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc24.c

583

adev->hdp.funcs->get_clock_gating_state(adev, flags);

sys/dev/pci/drm/amd/amdgpu/soc24.c

93

return adev->nbio.funcs->get_memsize(adev);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

498

.funcs = &tonga_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

147

.socket_id = adev->smuio.funcs->get_socket_id(adev),

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

364

adev->smuio.funcs &&

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

365

adev->smuio.funcs->get_socket_id)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

366

addr_in.ma.socket_id = adev->smuio.funcs->get_socket_id(adev);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

225

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

433

umsch->funcs = &umsch_mm_v4_0_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

203

adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

530

adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

848

.funcs = &uvd_v3_1_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

797

adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

808

adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

817

.funcs = &uvd_v4_2_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

904

adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

915

adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

924

.funcs = &uvd_v5_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1635

adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1638

adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1648

adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1665

adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1674

.funcs = &uvd_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1683

.funcs = &uvd_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1692

.funcs = &uvd_v6_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

406

adev->uvd.inst->ring_enc[i].funcs = NULL;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1607

adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1621

adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1642

adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1651

.funcs = &uvd_v7_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

660

adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

673

adev->vce.irq.funcs = &vce_v2_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

682

.funcs = &vce_v2_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

1002

.funcs = &vce_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

1010

.funcs = &vce_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

1018

.funcs = &vce_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

973

adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

979

adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

994

adev->vce.irq.funcs = &vce_v3_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

859

adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

873

adev->vce.irq.funcs = &vce_v4_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

882

.funcs = &vce_v4_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1959

if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1961

else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2187

adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2195

adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2206

adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2214

.funcs = &vcn_v1_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2176

adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2184

adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2195

adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2204

.funcs = &vcn_v2_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

288

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

179

if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1921

adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1934

adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

206

ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC &&

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2103

adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2106

adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2150

.funcs = &vcn_v2_5_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2159

.funcs = &vcn_v2_6_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

486

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2160

adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2162

adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2176

adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2341

adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2367

.funcs = &vcn_v3_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

414

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2026

adev->vcn.inst[i].ring_enc[0].funcs =

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2229

adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2232

adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2258

.funcs = &vcn_v4_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

346

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1670

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1871

adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1874

adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1900

.funcs = &vcn_v4_0_3_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2075

adev->vcn.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

302

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1530

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1698

adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1724

.funcs = &vcn_v4_0_5_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

300

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1251

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1419

adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1445

.funcs = &vcn_v5_0_0_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

264

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1372

adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1551

adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1554

adev->vcn.inst->ras_poison_irq.funcs = &vcn_v5_0_1_ras_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1585

.funcs = &vcn_v5_0_1_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1705

adev->vcn.inst->ras_poison_irq.funcs) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

282

adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

273

adev->nbio.funcs->ih_control(adev);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

293

adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

471

adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

658

.funcs = &vega10_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

319

adev->nbio.funcs->ih_control(adev);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

357

adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

557

adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

754

.funcs = &vega20_ih_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vi.c

1312

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/vi.c

1323

if (!ring || !ring->funcs->emit_wreg) {

sys/dev/pci/drm/amd/amdgpu/vi.c

2046

.funcs = &vi_common_ip_funcs,

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

258

adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

396

vpe->funcs = &vpe_v6_1_funcs;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

397

vpe->trap_irq.funcs = &vpe_v6_1_trap_irq_funcs;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2131

kdev->adev->smuio.funcs->get_pkg_type(kdev->adev) ==

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

259

r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

289

r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12702

if (obj->funcs == adev->dm.atomic_obj.funcs) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1401

dmcu->funcs->dmcu_init(dmcu);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1402

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2547

create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2548

create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3648

.funcs = &amdgpu_dm_funcs,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4789

if (obj->funcs == dm->atomic_obj.funcs)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4843

adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5959

if (adev->mode_info.funcs == NULL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5960

adev->mode_info.funcs = &dm_display_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8744

if (aconnector->base.funcs->reset)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8745

aconnector->base.funcs->reset(&aconnector->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

755

if (acrtc->base.funcs->reset)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

756

acrtc->base.funcs->reset(&acrtc->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1306

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1307

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1582

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1768

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1952

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2132

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2307

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2361

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2430

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2499

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4025

if (hubbub && hubbub->funcs->get_mall_en)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4026

hubbub->funcs->get_mall_en(hubbub, &mall_in_use);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

770

struct mod_hdcp_ddc_funcs *ddc_funcs = &config->ddc.funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

809

cp_psp->funcs.update_stream_config = update_config;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

810

cp_psp->funcs.enable_assr = enable_assr;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1333

ctx->dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

854

adev->crtc_irq.funcs = &dm_crtc_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

857

adev->vline0_irq.funcs = &dm_vline0_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

860

adev->dmub_outbox_irq.funcs = &dm_dmub_outbox_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

863

adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

866

adev->dmub_trace_irq.funcs = &dm_dmub_trace_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

869

adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

872

adev->hpd_irq.funcs = &dm_hpd_irq_funcs;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1519

if (res_pool->funcs->remove_stream_from_ctx &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1520

res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1470

plane->funcs->atomic_destroy_state(plane, plane->state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1900

if (plane->funcs->reset)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1901

plane->funcs->reset(plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

757

struct pp_smu_funcs *funcs)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

762

funcs->ctx.ver = PP_SMU_VER_RV;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

763

funcs->rv_funcs.pp_smu.dm = ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

764

funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

765

funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

766

funcs->rv_funcs.set_display_count =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

768

funcs->rv_funcs.set_min_deep_sleep_dcfclk =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

770

funcs->rv_funcs.set_hard_min_dcfclk_by_freq =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

772

funcs->rv_funcs.set_hard_min_fclk_by_freq =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

776

funcs->ctx.ver = PP_SMU_VER_NV;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

777

funcs->nv_funcs.pp_smu.dm = ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

778

funcs->nv_funcs.set_display_count = pp_nv_set_display_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

779

funcs->nv_funcs.set_hard_min_dcfclk_by_freq =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

781

funcs->nv_funcs.set_min_deep_sleep_dcfclk =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

783

funcs->nv_funcs.set_voltage_by_freq =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

785

funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

788

funcs->nv_funcs.set_pme_wa_enable = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

790

funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

792

funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

794

funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

795

funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

799

funcs->ctx.ver = PP_SMU_VER_RN;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

800

funcs->rn_funcs.pp_smu.dm = ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

801

funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

802

funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

214

if (wbcon->base.base.funcs->reset)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

215

wbcon->base.base.funcs->reset(&wbcon->base.base);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2877

bp->base.funcs = &vbios_funcs;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3710

bp->base.funcs = &vbios_funcs;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_interface.c

54

bios->funcs->bios_parser_destroy(dcb);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

256

bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

270

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

271

dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

333

int ss_info_num = bp->funcs->get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

338

enum bp_result result = bp->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

362

result = bp->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

449

base->funcs = &dce_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

300

clk_mgr->base.funcs = &dce110_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

112

bp->funcs->set_dce_clock(bp, &dce_clk_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

114

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

116

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

143

bp->funcs->set_dce_clock(bp, &dce_clk_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

154

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

156

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

185

bp->funcs->set_dce_clock(bp, &dce_clk_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

236

clk_mgr->base.funcs = &dce112_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

89

bp->funcs->set_dce_clock(bp, &dce_clk_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

137

clk_mgr->base.funcs = &dce120_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

64

result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

161

clk_mgr->base.funcs = &dce60_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

158

clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

159

clk_mgr->funcs->set_dprefclk(clk_mgr);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

177

clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

178

clk_mgr->funcs->set_dprefclk(clk_mgr);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

323

clk_mgr->base.funcs = &rv1_clk_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

324

clk_mgr->funcs = &rv1_clk_internal_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

137

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

139

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

42

clk_mgr->funcs = &rv2_clk_internal_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

122

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

163

if (!stream_enc->funcs->get_fifo_cal_average_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

165

fifo_level = stream_enc->funcs->get_fifo_cal_average_level(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

168

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

172

dccg->funcs->otg_drop_pixel(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

175

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

194

if (!stream_enc->funcs->get_fifo_cal_average_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

196

fifo_level = stream_enc->funcs->get_fifo_cal_average_level(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

199

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

201

dccg->funcs->otg_add_pixel(dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

203

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

336

dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

338

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

541

clk_mgr->base.funcs = &dcn2_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

187

clk_mgr->base.funcs = &dcn201_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

125

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

246

dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

248

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

715

clk_mgr->base.funcs = &dcn21_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

74

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

75

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

155

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

157

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

165

clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

317

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

319

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

425

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

529

clk_mgr->base.funcs = &dcn3_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

687

clk_mgr->base.base.funcs = &vg_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

83

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

84

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

102

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

103

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

126

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

129

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

683

clk_mgr->base.base.funcs = &dcn31_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

199

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

200

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

226

if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

227

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

231

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

925

clk_mgr->base.base.funcs = &dcn314_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

116

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

119

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

613

clk_mgr->base.base.funcs = &dcn315_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

78

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

79

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

94

if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

95

pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

118

if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

119

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

123

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

588

clk_mgr->base.base.funcs = &dcn316_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

90

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

91

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1064

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1153

clk_mgr->base.funcs = &dcn32_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

260

clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

286

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

343

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

382

if (!stream_enc->funcs->get_fifo_cal_average_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

384

fifo_level = stream_enc->funcs->get_fifo_cal_average_level(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

387

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

391

dccg->funcs->otg_drop_pixel(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

394

dccg->funcs->set_fifo_errdet_ovr_en(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

436

if (!stream_enc->funcs->get_fifo_cal_average_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

438

fifo_level = stream_enc->funcs->get_fifo_cal_average_level(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

441

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

443

dccg->funcs->otg_add_pixel(dccg,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

445

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

838

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

840

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

941

int ss_info_num = bp->funcs->get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

946

enum bp_result result = bp->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1378

clk_mgr->base.base.funcs = &dcn35_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

177

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

178

link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

225

new_pipe_link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

226

new_pipe_link_enc->funcs->is_dig_enabled(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

229

new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

230

new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

243

if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

244

pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

248

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

274

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

311

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

320

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1207

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1274

int ss_info_num = bp->funcs->get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1279

enum bp_result result = bp->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1424

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1560

clk_mgr->base.funcs = &dcn401_funcs;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

308

clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

539

ASSERT(otg_master->clock_source->funcs->program_pix_clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

547

otg_master->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

585

clk_mgr->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

752

params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1154

if (dc->res_pool->funcs->update_bw_bounding_box) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1156

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1369

if (tg->funcs->enable_crtc) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1370

if (dc->hwseq->funcs.blank_pixel_data)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1371

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1372

tg->funcs->enable_crtc(tg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1395

if (dc->res_pool->funcs->prepare_mcache_programming)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1396

dc->res_pool->funcs->prepare_mcache_programming(dc, dangling_context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1409

if (tg->funcs->disable_phantom_crtc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1410

tg->funcs->disable_phantom_crtc(tg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1449

if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1453

enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1457

tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1463

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1649

unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1673

if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1675

pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1678

pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1720

if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1722

pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1725

pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1791

if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1796

enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1808

tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1832

if (!tg->funcs->get_hw_timing) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1837

if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1913

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/core/dc.c

1917

if (tg->funcs->get_optc_source)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1918

tg->funcs->get_optc_source(tg,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1925

} else if (se && se->funcs->get_pixels_per_cycle) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1926

uint32_t pixels_per_cycle = se->funcs->get_pixels_per_cycle(se);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1943

if (!se || !se->funcs->dp_get_pixel_format) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1948

if (!se->funcs->dp_get_pixel_format(

sys/dev/pci/drm/amd/display/dc/core/dc.c

203

connectors_num = bios->funcs->get_connectors_number(bios);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2087

!tg->funcs->is_tg_enabled(tg) ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2135

if (!dcb->funcs->is_accelerated_mode(dcb)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2140

if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2146

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2211

if (dc->res_pool->funcs->prepare_mcache_programming)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2212

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2217

if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2220

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

232

struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2413

if (res == DC_OK && dc->res_pool->funcs->link_encs_assign && !dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2414

dc->res_pool->funcs->link_encs_assign(

sys/dev/pci/drm/amd/display/dc/core/dc.c

2492

if (acquire && pool->funcs->acquire_post_bldn_3dlut)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2493

ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2494

else if (!acquire && pool->funcs->release_post_bldn_3dlut)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2495

ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2536

if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2537

dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3051

if (dc->clk_mgr->funcs->are_clock_states_equal) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3052

if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3343

if (dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

353

if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

354

link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3566

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3637

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3641

odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3698

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3720

if (pipe_ctx->stream_res.tg->funcs->is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3721

if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3728

pipe_ctx->stream_res.abm->funcs->set_abm_level(

sys/dev/pci/drm/amd/display/dc/core/dc.c

396

link_enc->funcs->destroy(&link_enc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4087

if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4088

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4151

top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4164

top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4172

if (dc->hwseq->funcs.wait_for_pipe_update_if_needed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4173

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4326

if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe && update_type == UPDATE_TYPE_FULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4330

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4340

cur_pipe->plane_res.hubp->funcs->validate_dml_output(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4411

top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4412

top_pipe_to_program->stream_res.tg->funcs->wait_for_state(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4415

top_pipe_to_program->stream_res.tg->funcs->wait_for_state(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4418

top_pipe_to_program->stream_res.tg->funcs->wait_for_state(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4434

top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4492

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4493

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4673

if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

532

if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

533

pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5467

if (dc->clk_mgr->funcs->set_low_power_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5468

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5494

return dmcu->funcs->is_dmcu_initialized(dmcu);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5601

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5602

if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5615

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_fclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5616

idle_fclk_khz = dc->clk_mgr->funcs->get_hard_min_fclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5618

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5619

idle_dramclk_khz = dc->clk_mgr->funcs->get_hard_min_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5657

if (dc->clk_mgr->funcs->set_hard_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5658

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5660

if (dc->clk_mgr->funcs->set_hard_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5661

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5667

if (dc->clk_mgr->funcs->get_memclk_states_from_smu)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5668

dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5670

if (dc->clk_mgr->funcs->set_hard_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5671

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5673

if (dc->clk_mgr->funcs->set_hard_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5674

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5691

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5692

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5693

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5696

hubp->funcs->set_blank_regs(hubp, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5699

if (dc->clk_mgr->funcs->set_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5700

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5701

if (dc->clk_mgr->funcs->set_min_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5702

dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5711

hubp->funcs->set_blank_regs(hubp, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

575

dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5751

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5752

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5761

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5762

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);

sys/dev/pci/drm/amd/display/dc/core/dc.c

577

dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);

sys/dev/pci/drm/amd/display/dc/core/dc.c

611

else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

sys/dev/pci/drm/amd/display/dc/core/dc.c

6165

if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6166

pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6215

pipe->stream_res.abm->funcs->save_restore)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6216

return pipe->stream_res.abm->funcs->save_restore(

sys/dev/pci/drm/amd/display/dc/core/dc.c

6229

if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

6231

stream_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6286

if (dc->res_pool->funcs->get_power_profile)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6287

profile.power_level = dc->res_pool->funcs->get_power_profile(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6304

if (dc->res_pool->funcs->get_det_buffer_size)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6305

return dc->res_pool->funcs->get_det_buffer_size(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

750

if (tg->funcs->configure_crc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

751

return tg->funcs->configure_crc(tg, &param);

sys/dev/pci/drm/amd/display/dc/core/dc.c

791

if (tg->funcs->get_crc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

792

return tg->funcs->get_crc(tg, idx, r_cr, g_y, b_cb);

sys/dev/pci/drm/amd/display/dc/core/dc.c

811

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/core/dc.c

850

pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

851

pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

sys/dev/pci/drm/amd/display/dc/core/dc.c

857

pipes->stream_res.opp->funcs->

sys/dev/pci/drm/amd/display/dc/core/dc.c

934

if (dc->res_pool && dc->res_pool->funcs->link_encs_assign &&

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1027

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1028

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1040

if (dpp && dpp->funcs->dpp_setup) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1042

dpp->funcs->dpp_setup(dpp,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1050

if (dpp && dpp->funcs->set_cursor_matrix) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1051

dpp->funcs->set_cursor_matrix(dpp,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1065

if (dpp->funcs->dpp_program_bias_and_scale) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1066

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1076

if (mpc->funcs->power_on_mpc_mem_pwr)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1077

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1087

if (mpc->funcs->set_output_csc != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1088

mpc->funcs->set_output_csc(mpc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1101

if (mpc->funcs->set_ocsc_default != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1102

mpc->funcs->set_ocsc_default(mpc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1152

if (!hws->funcs.wait_for_blank_complete)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1162

hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1178

if (tg->funcs->wait_odm_doublebuffer_pending_clear)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1179

tg->funcs->wait_odm_doublebuffer_pending_clear(tg);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1180

if (tg->funcs->wait_otg_disable)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1181

tg->funcs->wait_otg_disable(tg);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1249

dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

294

if (!tg->funcs->is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

297

if (tg->funcs->is_blanked(tg))

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

695

pipe_ctx->stream_res.tg->funcs->set_drr)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

696

pipe_ctx->stream_res.tg->funcs->set_drr(

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

815

if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

839

if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

958

hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

975

hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

301

dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

559

link->dc->res_pool->funcs->link_encs_assign) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1538

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1542

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1550

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1554

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1563

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1569

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2156

otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2202

if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2204

opp->funcs->opp_get_left_edge_extra_pixel_count(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2496

if (pool->funcs->build_pipe_pix_clk_params)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2497

pool->funcs->build_pipe_pix_clk_params(otg_master);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2845

return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2890

if (pool->funcs->remove_stream_from_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2891

pool->funcs->remove_stream_from_ctx(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2982

if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2994

sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3123

if (!pool->funcs->acquire_free_pipe_as_secondary_opp_head) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3127

new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3142

new_bottom_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3200

if (!pool->funcs->release_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3211

pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3215

pool->funcs->release_pipe(context, last_opp_head, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3262

if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3266

new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3322

if (!pool->funcs->release_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3334

pool->funcs->release_pipe(context, last_dpp_pipe, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3645

if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3648

inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3655

tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

367

dc->res_pool->funcs->destroy(&dc->res_pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3674

if (pipe_ctx->stream_res.tg->funcs->get_optc_source)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3675

pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3701

if (pool->mpc->funcs->read_mpcc_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3704

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3756

if (dcb->funcs->is_accelerated_mode(dcb))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3900

dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

432

if (!aud->funcs->endpoint_valid(aud)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4321

if (dc->res_pool->funcs->validate_global) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4322

result = dc->res_pool->funcs->validate_global(dc, new_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

433

aud->funcs->destroy(&aud);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4340

if (dc->res_pool->funcs->patch_unknown_plane_state &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4343

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4372

result = dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, validate_mode);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4803

if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4804

vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4924

} else if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5078

if (!tg->funcs->validate_timing(tg, &stream->timing))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5083

!link->link_enc->funcs->validate_output_with_stream(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5108

if (dc->res_pool->funcs->validate_plane)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5109

return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5537

if (context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5538

context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config(context, mcache_params);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

204

if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

298

if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

299

max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

537

if (dwb->funcs->is_enabled(dwb)) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

572

if (dwb->funcs->set_fc_enable)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

573

dwb->funcs->set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

635

if (dwb->funcs->is_enabled(dwb))

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

657

return tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

725

tg->funcs->get_scanoutpos(tg,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

795

if (hubp->funcs->dmdata_set_attributes != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

797

hubp->funcs->dmdata_set_attributes(hubp, attr);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

807

if (dc->res_pool->funcs->add_dsc_to_stream_resource) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

808

return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

173

const struct dc_vbios_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1357

if (dc->clk_mgr->funcs->exit_low_power_state) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1407

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1424

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

43

const struct dsc_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

38

dmcu->funcs->is_dmcu_initialized(dmcu) &&

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

39

dmcu->funcs->send_edid_cea) {

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

40

return dmcu->funcs->send_edid_cea(dmcu,

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

55

dmcu->funcs->is_dmcu_initialized(dmcu) &&

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

56

dmcu->funcs->recv_edid_cea_ack) {

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

57

return dmcu->funcs->recv_edid_cea_ack(dmcu, offset);

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

71

dmcu->funcs->is_dmcu_initialized(dmcu) &&

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

72

dmcu->funcs->recv_amd_vsdb) {

sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c

73

return dmcu->funcs->recv_amd_vsdb(dmcu,

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

140

spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

161

base->funcs = &dccg2_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

78

base->funcs = &dccg201_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

125

base->funcs = &dccg21_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

71

base->funcs = &dccg3_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

96

base->funcs = &dccg3_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

70

base->funcs = &dccg301_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

748

base->funcs = &dccg31_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

399

base->funcs = &dccg314_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

368

base->funcs = &dccg32_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2463

base->funcs = &dccg35_funcs;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

907

base->funcs = &dccg401_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

272

base->funcs = &dce_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

295

abm_dce->base.funcs = &dce_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1294

static const struct audio_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1342

audio->base.funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1368

audio->base.funcs = &dce60_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

526

aux_engine110->base.funcs = &aux_functions;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

528

aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

250

struct dce_aux_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

268

bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

282

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

283

dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

308

bp->funcs->set_dce_clock(bp, &dce_clk_params);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

329

bp->funcs->set_dce_clock(bp, &dce_clk_params);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

332

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

334

dmcu->funcs->set_psr_wait_loop(dmcu,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

356

bp->funcs->get_firmware_info(bp, &fw_info);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

404

int ss_info_num = bp->funcs->get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

409

enum bp_result result = bp->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

433

result = bp->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

477

result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

822

base->funcs = &dce_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

888

clk_mgr_dce->base.funcs = &dce110_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

913

clk_mgr_dce->base.funcs = &dce112_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

935

clk_mgr_dce->base.funcs = &dce120_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

956

clk_mgr_dce->base.funcs = &dce120_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1053

if (clk_src->bios->funcs->set_pixel_clock(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1104

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1113

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1155

if (clk_src->bios->funcs->set_pixel_clock(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1185

bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1472

*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1496

bp_result = clk_src->bios->funcs->get_spread_spectrum_info(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1683

clk_src->base.funcs = &dce110_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1780

clk_src->base.funcs = &dce112_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1807

clk_src->base.funcs = &dcn20_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1823

clk_src->base.funcs = &dcn3_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1839

clk_src->base.funcs = &dcn31_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1855

clk_src->base.funcs = &dcn401_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1870

clk_src->base.funcs = &dcn3_clk_src_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

447

bp_result = clk_src->bios->funcs->adjust_pixel_clock(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

641

result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

748

clk_src->bios->funcs->

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

892

if (clk_src->bios->funcs->set_pixel_clock(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

952

if (clk_src->bios->funcs->set_pixel_clock(

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1078

base->funcs = &dce_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1118

dmcu_dce->base.funcs = &dce_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1139

dmcu_dce->base.funcs = &dcn10_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1160

dmcu_dce->base.funcs = &dcn20_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1181

dmcu_dce->base.funcs = &dcn21_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

181

link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

229

link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

616

link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

664

link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

45

if (dcb->funcs->get_i2c_info(dcb, id, &i2c_info) != BP_RESULT_OK)

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

281

ipp_dce->base.funcs = &dce_ipp_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

299

ipp_dce->base.funcs = &dce60_ipp_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

129

result = bp->funcs->transmitter_control(bp, cntl);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1718

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1721

enc110->base.funcs = &dce60_lnk_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

429

enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

482

enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

816

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

819

enc110->base.funcs = &dce110_lnk_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

1005

dce_mi->base.funcs = &dce120_mi_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

963

dce_mi->base.funcs = &dce_mi_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

980

dce_mi->base.funcs = &dce60_mi_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

993

dce_mi->base.funcs = &dce112_mi_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

708

static const struct opp_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

731

opp110->base.funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

750

opp110->base.funcs = &dce60_opp_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

290

dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1562

enc110->base.funcs = &dce110_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

549

if (enc110->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

665

if (enc110->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

689

if (enc110->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1644

xfm_dce->base.funcs = &dce_transform_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1673

xfm_dce->base.funcs = &dce60_transform_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

210

base->funcs = &abm_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

323

link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

327

link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

483

psr->funcs = &psr_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.h

36

const struct dmub_psr_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

430

replay->funcs = &replay_funcs;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h

15

const struct dmub_replay_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

455

compressor->base.funcs = &dce110_compressor_funcs;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

1038

dce_mi->base.funcs = &dce110_mem_input_v_funcs;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_v.c

39

static const struct opp_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_v.c

50

opp110->base.funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1399

tg->funcs->get_position(tg, &position1);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1400

tg->funcs->get_position(tg, &position2);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

146

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2074

tg->funcs->get_scanoutpos(

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

217

tg->funcs->wait_for_vblank(tg);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

218

tg->funcs->wait_for_vactive(tg);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2351

tg110->base.funcs = &dce110_tg_funcs;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

238

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

342

result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

346

tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

696

tg110->base.funcs = &dce110_tg_v_funcs;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

704

xfm_dce->base.funcs = &dce110_xfmv_funcs;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

823

bp->funcs->get_embedded_panel_info(bp, &panel_info)) {

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1062

tg->funcs->get_scanoutpos(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1266

tg110->base.funcs = &dce120_tg_funcs;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

151

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

217

if (!tg->funcs->is_counter_moving(tg)) {

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

224

if (!tg->funcs->is_counter_moving(tg)) {

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

235

if (!tg->funcs->is_counter_moving(tg)) {

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

256

tg110->base.funcs = &dce60_tg_funcs;

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

238

tg110->base.funcs = &dce80_tg_funcs;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

124

dwbc10->base.funcs = &dcn10_dwbc_funcs;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

69

dwbc->funcs->disable(dwbc);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

138

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

346

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

398

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

432

if (tg->funcs->read_otg_state)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

433

tg->funcs->read_otg_state(tg, &s);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

500

if (tg->funcs->read_otg_state)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

501

tg->funcs->read_otg_state(tg, &s);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

504

tg->funcs->clear_optc_underflow(tg);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

517

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

520

hubp->funcs->hubp_clear_underflow(hubp);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

85

dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c

68

ippn10->base.funcs = &dcn10_ipp_funcs;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c

85

ippn10->base.funcs = &dcn20_ipp_funcs;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

337

dwbc20->base.funcs = &dcn20_dwbc_funcs;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

120

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

124

enc10->base.funcs = &dcn201_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c

114

mpc201->base.funcs = &dcn201_mpc_funcs;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.c

69

oppn201->base.funcs = &dcn201_opp_funcs;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

341

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

345

enc10->base.funcs = &dcn21_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

142

if (afmt->funcs->afmt_poweron == NULL)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

151

if (mute && afmt->funcs->afmt_powerdown)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

152

afmt->funcs->afmt_powerdown(afmt);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

153

if (!mute && afmt->funcs->afmt_poweron)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

154

afmt->funcs->afmt_poweron(afmt);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

173

if (afmt->funcs->afmt_poweron)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

174

afmt->funcs->afmt_poweron(afmt);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

210

afmt3->base.funcs = &dcn30_afmt_funcs;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

52

if (afmt->funcs->afmt_poweron)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

53

afmt->funcs->afmt_poweron(afmt);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

133

const struct afmt_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

234

mcif_wb30->base.funcs = &dcn30_mmhubbub_funcs;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

259

vpg3->base.funcs = &dcn30_vpg_funcs;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

215

dcn301_panel_cntl->base.funcs = &dcn301_link_panel_cntl_funcs;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

87

afmt31->base.funcs = &dcn31_afmt_funcs;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c

114

apg31->base.funcs = &dcn31_apg_funcs;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

72

const struct apg_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

172

dcn31_panel_cntl->base.funcs = &dcn31_link_panel_cntl_funcs;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

87

vpg31->base.funcs = &dcn31_vpg_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

100

result = bp->funcs->transmitter_control(bp, cntl);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1059

if (enc->funcs->is_dig_enabled && !enc->funcs->is_dig_enabled(enc)) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

360

enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

678

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

681

enc10->base.funcs = &dcn10_lnk_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1473

if (enc->afmt && enc->afmt->funcs->afmt_powerdown)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1474

enc->afmt->funcs->afmt_powerdown(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1618

enc1->base.funcs = &dcn10_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

496

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

616

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

277

if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

400

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

404

enc10->base.funcs = &dcn20_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

652

enc1->base.funcs = &dcn20_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

100

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

104

enc10->base.funcs = &dcn30_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

349

enc1->base.vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

430

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

445

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

460

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

467

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

474

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

485

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

546

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

58

enc1->base.vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

592

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

700

enc->afmt->funcs->audio_info_immediate_update(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

715

enc->afmt->funcs->audio_mute_control(enc->afmt, mute);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

724

enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

746

enc->afmt->funcs->setup_dp_audio(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

767

enc->afmt->funcs->setup_hdmi_audio(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

824

enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

888

enc1->base.funcs = &dcn30_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

89

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

93

enc10->base.funcs = &dcn301_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

292

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

296

enc10->base.funcs = &dcn31_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

406

enc10->base.funcs = &dcn31_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

561

if (enc->funcs->is_dig_enabled && !enc->funcs->is_dig_enabled(enc))

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

123

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

163

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

265

enc->afmt->funcs->audio_info_immediate_update(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

495

enc1->base.funcs = &dcn314_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

249

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

253

enc10->base.funcs = &dcn32_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

121

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

223

enc->afmt->funcs->audio_info_immediate_update(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

482

enc1->base.funcs = &dcn32_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

81

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

105

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

109

enc10->base.funcs = &dcn321_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

178

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

182

enc10->base.funcs = &dcn35_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

379

if (enc->funcs->is_dig_enabled && !enc->funcs->is_dig_enabled(enc))

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

108

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

211

enc->afmt->funcs->audio_info_immediate_update(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

509

enc1->base.funcs = &dcn35_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

69

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

231

const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

235

enc10->base.funcs = &dcn401_link_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

121

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

222

enc->afmt->funcs->audio_info_immediate_update(enc->afmt);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

783

enc1->base.funcs = &dcn401_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

81

if (enc1->base.bp->funcs->encoder_control(

sys/dev/pci/drm/amd/display/dc/dm_cp_psp.h

57

struct cp_psp_funcs funcs;

sys/dev/pci/drm/amd/display/dc/dm_services.h

210

struct pp_smu_funcs *funcs);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1003

v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1151

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1234

context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1244

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1725

dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1780

if (dc->res_pool->funcs->populate_dml_pipes)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1781

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2280

if (dc->res_pool->funcs->populate_dml_pipes)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2281

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

462

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

725

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

728

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

522

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1518

dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1520

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1564

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1657

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1799

context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1803

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2163

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2167

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2252

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3104

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3107

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

662

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

665

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

104

lib->funcs = dml20_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

107

lib->funcs = dml20v2_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

110

lib->funcs = dml21_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

113

lib->funcs = dml30_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

117

lib->funcs = dml31_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

120

lib->funcs = dml314_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.c

123

lib->funcs = dml32_funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h

91

struct dml_funcs funcs;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

69

mode_lib->funcs.recalculate(mode_lib);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

76

mode_lib->funcs.validate(mode_lib);

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

974

mode_lib->funcs.recalculate(mode_lib);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

168

if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

169

context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

246

if (in_dc->res_pool->funcs->program_mcache_pipe_config) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1812

struct dml2_core_shared_calculation_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2301

struct dml2_core_shared_calculation_funcs funcs;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c

29

if (!in_out->dml2_instance->funcs.check_mode_supported)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c

32

return in_out->dml2_instance->funcs.check_mode_supported(in_out);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c

37

if (!in_out->dml2_instance->funcs.build_mode_programming)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c

40

return in_out->dml2_instance->funcs.build_mode_programming(in_out);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c

45

if (!in_out->dml2_instance->funcs.build_mcache_programming)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c

48

return in_out->dml2_instance->funcs.build_mcache_programming(in_out);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

1168

dml->funcs = soc15_funcs;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

972

struct dml2_top_funcs funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

583

dpp->base.funcs = &dcn10_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

417

dpp->base.funcs = &dcn20_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

308

dpp->base.funcs = &dcn201_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1514

dpp->base.funcs = &dcn30_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

157

dpp->base.funcs = &dcn32_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

138

dpp->base.funcs = &dcn35_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

272

dpp->base.funcs = &dcn401_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

596

if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

601

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool || dc->debug.disable_dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

605

max_dscclk_khz = dc->clk_mgr->funcs->get_max_clock_khz(dc->clk_mgr, CLK_TYPE_DSCCLK);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

607

dsc->funcs->dsc_get_single_enc_caps(&single_dsc_enc_caps, max_dscclk_khz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

646

dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

648

max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

678

if (dsc->funcs->dsc_get_enc_caps) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

679

dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

71

dsc->base.funcs = &dcn20_dsc_funcs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

68

dsc->base.funcs = &dcn35_dsc_funcs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

56

dsc->base.funcs = &dcn401_dsc_funcs;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

267

dwbc30->base.funcs = &dcn30_dwbc_funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

147

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

179

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

369

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

386

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

166

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

197

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

391

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

408

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

151

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

174

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

402

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

410

translate->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

151

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

174

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

402

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

410

translate->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

198

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

230

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

391

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

408

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

227

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

259

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

364

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

381

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

206

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

238

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

354

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

371

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

237

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

269

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

371

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

388

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

227

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

259

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

355

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

372

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

239

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

270

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

330

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

347

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

231

static const struct hw_factory_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

263

factory->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

315

static const struct hw_translate_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

333

tr->funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

129

return gpio->pin->funcs->change_mode(gpio->pin, mode);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

153

return gpio->pin->funcs->set_config(gpio->pin, config_data);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

160

return gpio->service->translate.funcs->id_to_offset(

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

290

gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

293

gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

296

gpio->service->factory.funcs->init_generic(&gpio->hw_container.generic, service->ctx, id, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

299

gpio->service->factory.funcs->init_hpd(&gpio->hw_container.hpd, service->ctx, id, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

87

return gpio->pin->funcs->get_value(gpio->pin, value);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

99

return gpio->pin->funcs->set_value(gpio->pin, value);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

134

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

151

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

183

if (service->translate.funcs->id_to_offset) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

184

service->translate.funcs->id_to_offset(id, en, &pin);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

321

*pin = service->factory.funcs->get_ddc_pin(gpio);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

322

service->factory.funcs->define_ddc_registers(*pin, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

325

*pin = service->factory.funcs->get_ddc_pin(gpio);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

326

service->factory.funcs->define_ddc_registers(*pin, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

329

*pin = service->factory.funcs->get_generic_pin(gpio);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

330

service->factory.funcs->define_generic_registers(*pin, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

333

*pin = service->factory.funcs->get_hpd_pin(gpio);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

334

service->factory.funcs->define_hpd_registers(*pin, en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

351

if (!(*pin)->funcs->open(*pin, mode)) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

377

pin->funcs->close(pin);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

498

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en))

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

205

static const struct hw_gpio_pin_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

222

ddc->base.base.funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

69

} *funcs;

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

100

pin->base.base.funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

83

static const struct hw_gpio_pin_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

40

const struct hw_gpio_pin_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

104

static const struct hw_gpio_pin_funcs funcs = {

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

121

pin->base.base.funcs = &funcs;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h

42

const struct hw_translate_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

501

result = bp->funcs->transmitter_control(bp, cntl);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

621

enc31->base.funcs = &dcn31_hpo_dp_link_encoder_funcs;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

458

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

465

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

472

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

483

enc->vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

573

enc3->base.vpg->funcs->update_generic_info_packet(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

644

enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

665

enc->apg->funcs->enable_apg(enc->apg);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

686

enc->apg->funcs->disable_apg(enc->apg);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

770

enc3->base.funcs = &dcn30_str_enc_funcs;

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

82

enc31->base.funcs = &dcn32_hpo_dp_link_encoder_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

843

if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe))

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

846

if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

936

hubbub1->base.funcs = &hubbub1_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

233

if (!hubbub->funcs->dcc_support_pixel_format(input->format,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

237

if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

626

hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

684

hubbub->base.funcs = &hubbub2_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

99

hubbub->base.funcs = &hubbub201_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

715

hubbub->base.funcs = &hubbub21_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

292

if (!hubbub->funcs->dcc_support_pixel_format(input->format,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

296

if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

500

hubbub3->base.funcs = &hubbub30_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

77

hubbub3->base.funcs = &hubbub301_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1089

hubbub31->base.funcs = &hubbub31_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

819

if (!hubbub->funcs->dcc_support_pixel_format(input->format,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

823

if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

1054

hubbub2->base.funcs = &hubbub32_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

606

hubbub2->base.funcs = &hubbub35_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1000

if (!hubbub->funcs->dcc_support_swizzle_addr3(input->swizzle_mode_addr3,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1264

hubbub2->base.funcs = &hubbub4_01_funcs;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

924

if (!hubbub->funcs->dcc_support_pixel_format_plane0_plane1(input->format,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

931

if (!hubbub->funcs->dcc_support_swizzle_addr3(input->swizzle_mode_addr3,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

995

if (!hubbub->funcs->dcc_support_swizzle_addr3(input->swizzle_mode_addr3,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1272

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1410

hubp1->base.funcs = &dcn10_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1063

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1708

hubp2->base.funcs = &dcn20_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

146

hubp201->base.funcs = &dcn201_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

854

hubp21->base.funcs = &dcn21_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

573

hubp2->base.funcs = &dcn30_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

126

hubp2->base.funcs = &dcn31_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

222

hubp2->base.funcs = &dcn32_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

234

hubp2->base.funcs = &dcn35_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1087

hubp2->base.funcs = &dcn401_hubp_funcs;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

784

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

56

if (lock && pipe->stream_res.tg->funcs->is_blanked &&

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

57

pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

114

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

126

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

138

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

164

if (clear_tiling && mi->funcs->mem_input_clear_tiling)

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

165

mi->funcs->mem_input_clear_tiling(mi);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

168

mi->funcs->mem_input_program_surface_flip_and_addr(mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

91

bp_result = dcb->funcs->enable_disp_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1032

ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1036

ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1102

if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1104

clk_mgr->funcs->enable_pme_wa(clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1107

pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1137

if (clk_mgr->funcs->enable_pme_wa)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1139

clk_mgr->funcs->enable_pme_wa(clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1166

pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1168

pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1173

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1176

pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1188

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1189

dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1191

if (dccg && dccg->funcs->set_dtbclk_dto)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1192

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1195

} else if (dccg && dccg->funcs->disable_symclk_se) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1196

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1214

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1217

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1232

hws->funcs.edp_backlight_control(link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1238

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1241

pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1270

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1458

state->clk_mgr->funcs->get_dp_ref_clk_frequency(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1483

if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1493

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1498

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1507

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1512

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1531

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1539

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1541

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1558

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1571

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1596

if (hws->funcs.disable_stream_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1597

hws->funcs.disable_stream_gating(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1608

pipe_ctx->stream_res.audio->funcs->az_configure(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1616

if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1618

pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1625

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1630

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1637

odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1643

odm_pipe->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1659

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1661

if (hws->funcs.setup_vupdate_interrupt)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1662

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1675

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1676

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1680

pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1710

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1742

link_enc->funcs->disable_output(link_enc, signal);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1745

link_enc->funcs->fec_set_enable(link_enc, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1746

link_enc->funcs->fec_set_ready(link_enc, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1760

dc->res_pool->timing_generators[i]->funcs->disable_crtc(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1769

if (dc->res_pool->dp_clock_source->funcs->cs_power_down(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1774

if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1789

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1805

if (tg->funcs->disable_vga)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1806

tg->funcs->disable_vga(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1873

dsc->funcs->dsc_read_state(dsc, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1878

if (tg->funcs->set_dsc_config)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1879

tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1884

if (se->funcs->dp_set_dsc_config)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1885

se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1886

if (se->funcs->dp_set_dsc_pps_info_packet)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1887

se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1890

if (dccg->funcs->set_ref_dscclk)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1891

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1892

dsc->funcs->dsc_disable(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1896

pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1931

if (hws->funcs.init_pipes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1932

hws->funcs.init_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1943

if (edp_link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1944

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1964

hws->funcs.is_dp_dig_pixel_rate_div_policy &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1965

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1967

dc->res_pool->dccg->funcs->get_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2007

hws->funcs.edp_backlight_control(edp_link_with_sink, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2010

if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2024

if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2063

pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2072

pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2099

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2108

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2146

if ((tg != NULL) && tg->funcs) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2149

if (tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2150

tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2165

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2191

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2281

compr->funcs->surface_address_and_pitch(compr, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2282

compr->funcs->set_fbc_invalidation_triggers(compr, 1);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2284

compr->funcs->enable_fbc(compr, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

230

bp_result = dcb->funcs->enable_disp_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2323

pipe_ctx_old->stream_res.audio->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2337

pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2342

pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2345

pipe_ctx_old->plane_res.mi->funcs->free_mem_input(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2351

old_clk->funcs->cs_power_down(old_clk);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2400

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2403

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2406

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2412

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2440

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2468

hws->funcs.reset_hw_ctx_wrap(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2475

dcb->funcs->set_scratch_critical_state(dcb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2493

hws->funcs.enable_display_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2499

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2503

if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2504

dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2535

if (hws->funcs.resync_fifo_dccg_dio)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2536

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2543

dcb->funcs->set_scratch_critical_state(dcb, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2568

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2616

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2636

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2646

pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2662

pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2670

pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2672

!pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2696

if (!tg->funcs->is_counter_moving(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2701

if (tg->funcs->did_triggered_reset_occur(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2710

tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2711

tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2742

grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2749

grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2756

grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2764

grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2783

grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2789

grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2799

grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2822

xfm->funcs->transform_reset(xfm);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2824

hws->funcs.enable_display_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2827

hws->funcs.enable_display_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2830

hws->funcs.enable_display_pipe_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2845

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2851

tg->funcs->disable_vga(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2855

tg->funcs->set_blank(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2861

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2868

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2875

abm->funcs->abm_init(abm, backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2879

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2882

dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2895

dccg->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2910

dccg->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2943

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2955

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2961

mi->funcs->mem_input_program_surface_config(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2969

if (mi->funcs->set_blank)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2970

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2973

mi->funcs->mem_input_program_pte_vm(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

298

ipp->funcs->ipp_program_prescale(ipp, &prescale_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2983

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2986

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

302

ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3038

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3047

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

307

ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3082

hws->funcs.enable_display_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3085

dc->res_pool->transforms[fe_idx]->funcs->transform_reset(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

310

ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3114

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

313

ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3158

if (ipp->funcs->ipp_cursor_set_position)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3159

ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3160

if (mi->funcs->set_cursor_position)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3161

mi->funcs->set_cursor_position(mi, &pos_cpy, &param);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3169

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3170

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3174

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3175

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3179

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3180

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3200

if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3204

fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3206

if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3207

panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3209

abm->funcs->set_backlight_level_pwm(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

321

ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3225

abm->funcs->set_abm_immediate_disable(abm,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3229

panel_cntl->funcs->store_backlight_level(panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3239

abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3247

link->link_enc->funcs->enable_lvds_output(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3261

link->link_enc->funcs->enable_tmds_output(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3308

pipes[i].clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3318

if (dc->clk_mgr->funcs->notify_link_rate_change)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3319

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3322

if (dmcu != NULL && dmcu->funcs->lock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3323

dmcu->funcs->lock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3331

if (dmcu != NULL && dmcu->funcs->unlock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3332

dmcu->funcs->unlock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3349

else if (dmcu != NULL && dmcu->funcs->lock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3350

dmcu->funcs->lock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3359

if (dmcu != NULL && dmcu->funcs->unlock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3360

dmcu->funcs->unlock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3427

dc->hwseq->funcs = dce110_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

612

xfm->funcs->opp_power_on_regamma_lut(xfm, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

617

xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

620

xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

621

xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

623

xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

626

xfm->funcs->opp_power_on_regamma_lut(xfm, false);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

648

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

652

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

653

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

657

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

691

tg->funcs->set_early_control(tg, early_control);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

700

result = bios->funcs->transmitter_control(bios, cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

801

link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

878

bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

882

bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

928

if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

968

bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

132

bp_result = dcb->funcs->enable_disp_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

158

dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

172

bp_result = dcb->funcs->enable_disp_power_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

266

dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

131

compr->funcs->surface_address_and_pitch(compr, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

132

compr->funcs->set_fbc_invalidation_triggers(compr, 1);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

134

compr->funcs->enable_fbc(compr, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

160

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

192

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

246

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

251

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

260

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

265

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

298

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

310

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

316

mi->funcs->mem_input_program_surface_config(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

324

if (mi->funcs->set_blank)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

325

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

328

mi->funcs->mem_input_program_pte_vm(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

341

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

393

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

402

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

425

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

49

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1013

if (hws->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1014

hws->funcs.dpp_root_clock_control(hws, plane_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1020

if (hws->funcs.dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1021

hws->funcs.dpp_pg_control(hws, plane_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1023

if (hws->funcs.hubp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1024

hws->funcs.hubp_pg_control(hws, plane_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1041

hubp->funcs->set_blank(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1046

hws->funcs.hubp_pg_control(hws, 0, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1075

hws->funcs.hubp_pg_control(hws, 0, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1079

hubp->funcs->set_hubp_blank_en(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1090

if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1093

if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1095

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1106

bp->funcs->enable_disp_power_gating(bp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1111

bp->funcs->enable_disp_power_gating(bp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1115

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1117

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1118

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1134

underflow = tg->funcs->is_optc_underflow_occurred(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1145

if (tg->funcs->set_blank_data_double_buffer)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1146

tg->funcs->set_blank_data_double_buffer(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1148

if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1149

tg->funcs->clear_optc_underflow(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1199

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1201

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1218

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1235

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

124

if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1252

if (pipe_ctx->stream_res.tg->funcs->set_blank_color)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1253

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1257

if (pipe_ctx->stream_res.tg->funcs->is_blanked &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1258

!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1259

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1265

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1308

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1329

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

133

frame_count = tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1331

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1372

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1373

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1385

if (hubp != NULL && hubp->funcs->hubp_disable_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1386

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1395

if (hubp != NULL && hubp->funcs->hubp_disable_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1396

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1407

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1408

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1420

if (!hubbub->funcs->verify_allow_pstate_change_high)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1423

if (!hubbub->funcs->verify_allow_pstate_change_high(hubbub)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1433

if (!hubbub->funcs->verify_allow_pstate_change_high(hubbub))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1453

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1459

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1467

if (hubp->funcs->hubp_disconnect)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1468

hubp->funcs->hubp_disconnect(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1471

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1498

if (hws->funcs.dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1499

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1501

if (hws->funcs.hubp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1502

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1504

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1505

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1513

if (hws->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1514

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1529

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1531

dpp->funcs->dpp_dppclk_control(dpp, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1534

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1541

hws->funcs.plane_atomic_power_down(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1561

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1598

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1599

if (hws->funcs.init_blank != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1600

hws->funcs.init_blank(dc, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1601

tg->funcs->lock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1603

tg->funcs->lock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1604

tg->funcs->set_blank(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1620

if (hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1621

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1622

if (hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1623

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1635

dc->res_pool->mpc->funcs->mpc_init_single_inst(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1651

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1657

tg->funcs->tg_init(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1666

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1667

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1684

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1686

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1687

tg->funcs->unlock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1694

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1695

if (tg->funcs->init_odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1696

tg->funcs->init_odm(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1699

tg->funcs->tg_init(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1717

if (hws->funcs.dsc_pg_control != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1732

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1733

if (tg->funcs->get_dsc_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1734

tg->funcs->get_dsc_status(tg, &optc_dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1738

tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1748

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1754

hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1771

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1772

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1781

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1782

dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1784

if (!dcb->funcs->is_accelerated_mode(dcb))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1785

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1788

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1797

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1801

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1822

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1825

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1826

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1828

if (link->link_enc->funcs->fec_is_active &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1829

link->link_enc->funcs->fec_is_active(link->link_enc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1837

if (hws->funcs.enable_power_gating_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1838

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1846

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1848

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1849

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1850

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1860

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1867

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1873

abm->funcs->abm_init(abm, backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1876

dmcu->funcs->dmcu_init(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1880

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1895

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1896

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1915

if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1916

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1917

dc->hwseq->funcs.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1918

dc->hwseq->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1920

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1921

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1927

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1928

link->link_enc->funcs->is_dig_enabled(link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1929

dc->hwseq->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1930

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1942

if (dc->clk_mgr->funcs->set_low_power_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1943

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1970

if (hws->funcs.enable_stream_gating)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1971

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1973

old_clk->funcs->cs_power_down(old_clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

200

if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2017

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2046

dpp_base->funcs->dpp_program_input_lut(dpp_base, &plane_state->gamma_correction);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

205

cur_frame = tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2051

dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2054

dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2057

dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2060

dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2062

dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2070

dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2074

dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2124

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2132

dpp->funcs->dpp_program_regamma_pwl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2136

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2161

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2164

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2166

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2169

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2260

dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2279

if (!tg->funcs->is_counter_moving(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2284

if (tg->funcs->did_triggered_reset_occur(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2293

tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2294

tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

240

!tg->funcs->is_tg_enabled(tg) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2406

dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2415

grouped_pipes[i]->stream_res.tg->funcs->get_hw_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2418

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2453

dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2457

dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2489

tg->funcs->get_otg_active_size(tg, &width, &height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2491

if (!tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2496

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2497

opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2516

grouped_pipes[i]->stream_res.tg->funcs->align_vblanks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2532

tg->funcs->get_otg_active_size(tg, &width, &height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2533

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2534

opp->funcs->opp_program_dpg_dimensions(opp, width, height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2560

tg->funcs->get_otg_active_size(tg, &width, &height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2562

if (!tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2567

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2568

opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2585

grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2603

grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2613

tg->funcs->get_otg_active_size(tg, &width, &height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2614

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2615

opp->funcs->opp_program_dpg_dimensions(opp, width, height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2633

if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2634

grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2726

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2727

hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

273

dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2738

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2747

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2750

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2758

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2765

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2790

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2820

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2833

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2849

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2853

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2854

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2863

dpp->funcs->dpp_setup(dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2872

if (dpp->funcs->dpp_program_bias_and_scale)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2873

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2882

if (mpc->funcs->set_bg_color) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2883

mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2935

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2941

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2944

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2947

mpc->funcs->assert_mpcc_idle_before_connect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2951

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2973

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3029

dpp->funcs->dpp_dppclk_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3035

dc->res_pool->dccg->funcs->update_dpp_dto(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3050

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3052

hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3058

hubp->funcs->hubp_setup_interdependent(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

306

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3073

hws->funcs.update_mpcc(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3086

hubp->funcs->mem_program_viewport(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3120

hubp->funcs->hubp_program_surface_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3136

hubp->funcs->set_blank(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3162

if (stream_res->tg->funcs->set_blank_color)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3163

stream_res->tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3168

if (stream_res->tg->funcs->set_blank)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3169

stream_res->tg->funcs->set_blank(stream_res->tg, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3172

stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3176

if (stream_res->tg->funcs->set_blank) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3177

stream_res->tg->funcs->wait_for_state(stream_res->tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3178

stream_res->tg->funcs->set_blank(stream_res->tg, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3197

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3211

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3219

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3222

if (hws->funcs.setup_vupdate_interrupt)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3223

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3225

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3233

hws->funcs.set_hdr_multiplier(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3247

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3267

!tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3277

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3278

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3340

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3345

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3350

dc->optimized_required = hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3366

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3378

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3383

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3388

hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3405

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3433

if ((tg != NULL) && tg->funcs) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3436

if (tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3437

tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3452

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3469

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3530

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3535

pipe_ctx->stream_res.tg->funcs->program_stereo(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3564

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3575

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3576

res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3578

hubp->funcs->set_blank(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3583

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3607

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3616

tg->funcs->is_stereo_left_eye) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3618

!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3624

unsigned int cur_frame = tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3629

hubbub->funcs->allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3640

hubbub->funcs->update_dchub(hubbub, dh_data);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3859

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3860

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3867

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3869

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3881

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3896

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3999

tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4012

if (tg->funcs->setup_vertical_interrupt2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4013

tg->funcs->setup_vertical_interrupt2(tg, start_line);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4032

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4036

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4045

pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4060

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_clock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4063

dc->clk_mgr->funcs->get_clock(dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4083

if (dc->clk_mgr->funcs->update_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4084

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4096

if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4097

dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4110

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4137

if (clear_tiling && hubp->funcs->hubp_clear_tiling)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4138

hubp->funcs->hubp_clear_tiling(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4141

hubp->funcs->hubp_program_surface_flip_and_addr(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

466

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

467

if (dpp->funcs->dpp_get_gamut_remap) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

468

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

541

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

564

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

599

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

634

if (tg->funcs->read_otg_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

635

tg->funcs->read_otg_state(tg, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

644

if (pool->opps[i]->funcs->dpg_is_blanked)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

645

s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

647

s.blank_enabled = tg->funcs->is_blanked(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

678

tg->funcs->clear_optc_underflow(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

689

dsc->funcs->dsc_read_state(dsc, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

705

if (enc->funcs->enc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

706

enc->funcs->enc_read_state(enc, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

726

if (lenc && lenc->funcs->read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

727

lenc->funcs->read_state(lenc, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

758

if (hpo_dp_stream_enc && hpo_dp_stream_enc->funcs->read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

759

hpo_dp_stream_enc->funcs->read_state(hpo_dp_stream_enc, &hpo_dp_se_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

789

if (hpo_dp_link_enc->funcs->read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

790

hpo_dp_link_enc->funcs->read_state(hpo_dp_link_enc, &hpo_dp_le_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

818

if (tg->funcs->is_optc_underflow_occurred(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

819

tg->funcs->clear_optc_underflow(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

823

if (hubp->funcs->hubp_get_underflow_status(hubp)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

824

hubp->funcs->hubp_clear_underflow(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

126

dc->hwseq->funcs = dcn10_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1011

if (mpc->funcs->power_on_mpc_mem_pwr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1012

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1015

if (mpc->funcs->set_output_csc != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1016

mpc->funcs->set_output_csc(mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1021

if (mpc->funcs->set_ocsc_default != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1022

mpc->funcs->set_ocsc_default(mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1042

if (mpc->funcs->power_on_mpc_mem_pwr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1043

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1045

&& mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1063

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1064

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1084

result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1105

result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1107

result = dpp_base->funcs->dpp_program_3dlut(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1110

result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1128

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1129

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1138

dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1143

dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1154

dpp_base->funcs->dpp_set_degamma(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1158

dpp_base->funcs->dpp_set_degamma(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1162

dpp_base->funcs->dpp_set_degamma(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1166

dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1168

dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1176

dpp_base->funcs->dpp_set_degamma(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1184

dpp_base->funcs->dpp_set_degamma(dpp_base,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1205

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1210

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1275

stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1288

if (hws->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1297

if (hws->funcs.dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1298

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1300

if (hws->funcs.hubp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1301

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1321

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1324

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1327

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1377

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1383

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1384

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1426

if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1476

pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1478

pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1481

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1483

if (dc->hwseq->funcs.perform_3dlut_wa_unlock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1484

dc->hwseq->funcs.perform_3dlut_wa_unlock(pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1486

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1693

dpp->funcs->dpp_dppclk_control(dpp, false, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1696

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1704

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1706

if (hubp->funcs->hubp_setup2) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1707

hubp->funcs->hubp_setup2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

171

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1713

hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1722

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1723

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1726

if (hubp->funcs->hubp_setup_interdependent2) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1727

hubp->funcs->hubp_setup_interdependent2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1731

hubp->funcs->hubp_setup_interdependent(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1747

dpp->funcs->dpp_setup(dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1754

if (dpp->funcs->set_cursor_matrix) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1755

dpp->funcs->set_cursor_matrix(dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1759

if (dpp->funcs->dpp_program_bias_and_scale) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1761

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1770

hws->funcs.update_mpcc(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1781

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1790

hubp->funcs->mem_program_viewport(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1797

if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1798

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1843

hubp->funcs->hubp_program_surface_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1871

hubp->funcs->set_blank(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1873

if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1874

hubp->funcs->phantom_hubp_post_enable(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1909

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1918

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1920

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1923

if (hws->funcs.setup_vupdate_interrupt)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1924

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1939

hws->funcs.blank_pixel_data(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1950

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1953

if (hws->funcs.enable_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1954

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1958

if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1959

dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1963

if (dc->res_pool->hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1964

dc->res_pool->hubbub->funcs->program_det_size(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1967

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1968

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1979

hws->funcs.set_hdr_multiplier(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1986

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1995

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2005

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2011

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2021

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2031

odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2080

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2081

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2103

if (tg->funcs->enable_crtc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2104

if (dc->hwseq->funcs.blank_pixel_data)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2105

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2107

tg->funcs->enable_crtc(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2117

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2135

if (hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2136

hubbub->funcs->program_det_size(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2138

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2139

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2142

hws->funcs.plane_atomic_disconnect(dc, dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2153

hws->funcs.update_odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2154

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2166

if (hws->funcs.program_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2167

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2192

&& hws->funcs.program_all_writeback_pipes_in_tree)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2193

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2199

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2202

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2226

if (dc->hwseq->funcs.dsc_pg_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2227

is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2236

dsc->funcs->dsc_wait_disconnect_pending_clear(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2237

dsc->funcs->dsc_disable(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2238

if (dccg->funcs->set_ref_dscclk)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2239

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2279

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2298

if (tg->funcs->get_optc_double_buffer_pending) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2300

&& tg->funcs->get_optc_double_buffer_pending(tg); j++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2306

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2307

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2345

if (hwseq->funcs.update_force_pstate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2346

dc->hwseq->funcs.update_force_pstate(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2351

if (hwseq->funcs.program_mall_pipe_config)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2352

hwseq->funcs.program_mall_pipe_config(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2356

dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2366

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2369

hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2383

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2402

dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2412

if (hubbub->funcs->program_compbuf_size) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2421

hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2443

hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2451

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2454

if (hubbub->funcs->program_compbuf_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2455

hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2466

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2475

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2478

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2492

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2508

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2516

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2520

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2522

if (hws->funcs.setup_vupdate_interrupt)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2523

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2526

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2553

optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2555

mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2556

mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2558

mcif_wb->funcs->enable_mcif(mcif_wb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2560

dwb->funcs->enable(dwb, &wb_info->dwb_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2575

dwb->funcs->disable(dwb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2576

mcif_wb->funcs->disable_mcif(mcif_wb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2588

if (!opp->funcs->dpg_is_pending(opp))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2599

return opp->funcs->dpg_is_blanked(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2608

return hubp->funcs->dmdata_status_done(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2620

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2633

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2635

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2658

hubp->funcs->dmdata_set_attributes(hubp, &attr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2680

dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2698

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2743

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2766

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2780

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2786

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2787

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2789

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2793

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2805

if (tg->funcs->setup_vertical_interrupt2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2806

tg->funcs->setup_vertical_interrupt2(tg, start_line);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2839

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2859

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

286

if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2861

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2862

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2863

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

287

pipe_ctx->stream_res.tg->funcs->set_gsl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2882

if (dccg && dccg->funcs->set_dtbclk_dto)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2883

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

290

if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

291

pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2925

if (hws->funcs.enable_stream_gating)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2926

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2928

old_clk->funcs->cs_power_down(old_clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2987

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2993

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2996

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2999

mpc->funcs->assert_mpcc_idle_before_connect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3003

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

301

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

302

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3046

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3047

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3049

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3053

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3055

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3058

if (dccg->funcs->enable_symclk_se && link_enc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3062

if (dccg->funcs->disable_symclk_se)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3063

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3066

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3071

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3072

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3102

tg->funcs->set_early_control(tg, early_control);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3124

if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3127

stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3138

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3139

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3142

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3143

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3146

if (hws->funcs.enable_power_gating_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3147

hws->funcs.enable_power_gating_plane(hws, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3153

hws->funcs.dccg_init(hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3166

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3173

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3174

tg->funcs->lock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3180

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3184

res_pool->mpc->funcs->mpc_init(res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3211

hubp->funcs->hubp_init(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3218

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3228

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3229

tg->funcs->unlock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3244

tg->funcs->tg_init(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3247

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3248

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3259

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

397

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

398

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

422

tg->funcs->get_otg_active_size(tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

427

tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

436

if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

449

opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

460

bottom_opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

471

hws->funcs.wait_for_blank_complete(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

621

if (dpp5 && dpp5->funcs->dpp_force_disable_cursor)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

622

dpp5->funcs->dpp_force_disable_cursor(dpp5);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

724

if (hubp->funcs->hubp_update_mall_sel)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

725

hubp->funcs->hubp_update_mall_sel(hubp, 0, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

729

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

731

dpp->funcs->dpp_dppclk_control(dpp, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

735

hws->funcs.plane_atomic_power_down(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

765

if (tg && tg->funcs->disable_phantom_crtc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

766

tg->funcs->disable_phantom_crtc(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

847

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

853

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

854

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

876

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

884

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

886

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

900

if (dccg->funcs->set_dtbclk_p_src)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

901

dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

907

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

908

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

919

if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

92

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

920

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

922

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

93

if (dpp->funcs->dpp_get_gamut_remap) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

938

if (mpc->funcs->set_out_rate_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

94

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

940

mpc->funcs->set_out_rate_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

949

opp_heads[i]->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

952

opp_heads[i]->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

958

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

961

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

981

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

982

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

994

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

995

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

144

dc->hwseq->funcs = dcn20_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

149

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

180

tg->funcs->get_otg_active_size(tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

185

tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

189

opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

199

hws->funcs.wait_for_blank_complete(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

231

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

232

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

234

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

235

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

237

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

244

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

248

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

266

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

275

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

283

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

284

tg->funcs->lock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

290

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

294

res_pool->mpc->funcs->mpc_init(res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

321

hubp->funcs->hubp_init(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

326

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

336

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

337

tg->funcs->unlock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

352

tg->funcs->tg_init(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

358

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

391

if (mpc->funcs->get_mpcc_for_dpp_from_secondary)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

392

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

395

if (mpcc_to_remove != NULL && mpc->funcs->remove_mpcc_from_secondary) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

396

mpc->funcs->remove_mpcc_from_secondary(mpc, mpc_tree_params, mpcc_to_remove);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

401

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

403

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

415

if (hubp->funcs->hubp_disconnect)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

416

hubp->funcs->hubp_disconnect(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

419

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

487

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

492

if (mpc->funcs->get_mpcc_for_dpp_from_secondary)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

493

remove_mpcc = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

496

if (remove_mpcc != NULL && mpc->funcs->remove_mpcc_from_secondary)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

497

mpc->funcs->remove_mpcc_from_secondary(mpc, mpc_tree_params, remove_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

500

remove_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

504

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, remove_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

507

mpc->funcs->assert_mpcc_idle_before_connect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

512

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

538

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

542

pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

544

pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

547

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

549

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

553

hws->funcs.verify_allow_pstate_change_high(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

562

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

564

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

588

hubp->funcs->dmdata_set_attributes(hubp, &attr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

606

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing))

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

609

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

613

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

135

dc->hwseq->funcs = dcn201_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

102

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

112

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

198

if (abm->funcs && abm->funcs->set_pipe_ex) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

199

abm->funcs->set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

208

panel_cntl->funcs->store_backlight_level(panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

230

if (abm->funcs && abm->funcs->set_pipe_ex) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

231

abm->funcs->set_pipe_ex(abm,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

265

if (abm->funcs && abm->funcs->set_pipe_ex) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

266

abm->funcs->set_pipe_ex(abm,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

279

if (abm->funcs && abm->funcs->set_backlight_level_pwm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

280

abm->funcs->set_backlight_level_pwm(abm, backlight_pwm_u16_16,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

83

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

149

dc->hwseq->funcs = dcn21_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1170

dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1171

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1183

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1198

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1212

if (tg && tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1216

if (tg->funcs->get_optc_double_buffer_pending)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1217

pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1219

if (tg->funcs->get_otg_double_buffer_pending)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1220

pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1222

if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1223

pending_updates |= tg->funcs->get_pipe_update_pending(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1244

tg->funcs->get_scanoutpos(tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1250

out_data->otg_frame_count = tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1252

out_data->otg_underflow = tg->funcs->is_optc_underflow_occurred(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1259

if (hubp->funcs->hubp_get_underflow_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1260

out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1262

if (hubp->funcs->hubp_in_blank)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1263

out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1265

if (hubp->funcs->hubp_get_current_read_line)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1266

out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1268

if (hubp->funcs->hubp_get_det_config_error)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1269

out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1273

if (hubbub->funcs->get_det_sizes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1274

hubbub->funcs->get_det_sizes(hubbub, out_data->curr_det_sizes, out_data->target_det_sizes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1276

if (hubbub->funcs->compbuf_config_error)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1277

out_data->compbuf_config_error = hubbub->funcs->compbuf_config_error(hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

182

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

248

result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

290

acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

295

result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

300

result = mpc->funcs->program_shaper(mpc, shaper_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

307

mpc->funcs->release_rmu(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

331

dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

341

result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

344

if (dpp_base->funcs->dpp_program_blnd_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

345

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

346

if (dpp_base->funcs->dpp_program_shaper_lut &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

347

dpp_base->funcs->dpp_program_3dlut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

348

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

373

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

388

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

404

if (ret == false && mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

419

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

420

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

443

dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

446

mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

447

mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

464

dwb->funcs->update(dwb, &wb_info->dwb_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

502

mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

518

mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

546

mcif_wb->funcs->enable_mcif(mcif_wb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

548

dwb->funcs->enable(dwb, &wb_info->dwb_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

565

dwb->funcs->disable(dwb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

567

mcif_wb->funcs->disable_mcif(mcif_wb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

569

dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

624

if (dwb->funcs->is_enabled(dwb)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

649

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

650

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

653

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

654

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

656

if (!dcb->funcs->is_accelerated_mode(dcb)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

657

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

658

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

685

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

689

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

709

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

712

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

713

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

715

if (link->link_enc->funcs->fec_is_active &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

716

link->link_enc->funcs->fec_is_active(link->link_enc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

724

if (hws->funcs.enable_power_gating_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

725

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

733

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

734

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

735

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

736

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

752

if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

753

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

755

hws->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

758

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

764

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

765

link->link_enc->funcs->is_dig_enabled(link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

766

hws->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

767

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

778

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

785

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

792

abms[i]->funcs->abm_init(abms[i], backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

807

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

808

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

810

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

811

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

814

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

816

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

818

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

819

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

821

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

822

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

836

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

841

if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

842

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

843

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

844

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

845

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

846

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

868

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

872

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

873

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

877

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

902

if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

905

stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

91

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

93

if (dpp->funcs->dpp_get_gamut_remap) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

94

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

154

dc->hwseq->funcs = dcn30_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

151

dc->hwseq->funcs = dcn301_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

38

dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

39

dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

40

dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

36

dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

37

dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

38

dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

39

dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

102

dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

104

dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

119

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

120

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

122

if (!dcb->funcs->is_accelerated_mode(dcb)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

123

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

124

if (hws->funcs.disable_vga)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

125

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

128

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

129

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

139

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

143

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

166

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

169

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

170

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

172

if (link->link_enc->funcs->fec_is_active &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

173

link->link_enc->funcs->fec_is_active(link->link_enc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

181

if (hws->funcs.enable_power_gating_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

182

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

190

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

200

if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

201

tg->funcs->get_optc_source(tg, &num_opps,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

213

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

214

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

215

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

222

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

229

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

236

abms[i]->funcs->abm_init(abms[i], backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

246

if (hws->funcs.setup_hpo_hw_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

247

hws->funcs.setup_hpo_hw_control(hws, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

258

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

259

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

261

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

262

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

264

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

265

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

267

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

268

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

271

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

272

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

294

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

296

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

337

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

338

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

395

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

399

if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

400

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

404

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

409

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

410

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

414

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

508

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

539

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

543

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

545

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

546

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

547

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

595

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

638

dc->res_pool->hubbub->funcs->program_det_size &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

639

dc->res_pool->hubbub->funcs->wait_for_det_apply) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

640

dc->res_pool->hubbub->funcs->program_det_size(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

643

dc->res_pool->hubbub->funcs->wait_for_det_apply(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

648

if (hws->funcs.enable_stream_gating)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

649

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

651

old_clk->funcs->cs_power_down(old_clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

680

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

94

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

95

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

98

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

156

dc->hwseq->funcs = dcn31_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

112

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

113

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

118

odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

119

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

128

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

134

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

139

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

142

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

185

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

190

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

193

if (mpc->funcs->set_out_rate_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

195

mpc->funcs->set_out_rate_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

204

odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

219

dsc->funcs->dsc_disconnect(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

237

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

239

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

288

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

289

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

333

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

376

if (hws->funcs.calculate_dccg_k1_k2_values)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

377

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

389

&& pipe->stream_res.stream_enc->funcs->dig_source_otg

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

390

&& pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

392

&& pipe->stream->link->link_enc->funcs->is_dig_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

393

&& pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

394

&& pipe->stream_res.stream_enc->funcs->is_fifo_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

395

&& pipe->stream_res.stream_enc->funcs->is_fifo_enabled(pipe->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

419

pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

425

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

445

pipe->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

450

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

460

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

461

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

490

pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

515

else if (dmcu != NULL && dmcu->funcs->lock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

516

dmcu->funcs->lock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

525

if (dmcu != NULL && dmcu->funcs->unlock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

526

dmcu->funcs->unlock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

557

if (dpp && dpp->funcs->dpp_force_disable_cursor)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

558

dpp->funcs->dpp_force_disable_cursor(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

94

if (dsc->funcs->dsc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

95

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

163

dc->hwseq->funcs = dcn314_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1003

if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1005

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1030

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1048

if (dsc->funcs->dsc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1049

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1068

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1069

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1070

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1078

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1079

odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1080

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1085

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1091

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1096

dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1099

odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1142

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1147

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1151

odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1154

odm_pipe->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1171

dsc->funcs->dsc_disconnect(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1180

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1190

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1209

if ((odm_combine_factor == 2) || (hws->funcs.is_dp_dig_pixel_rate_div_policy &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1210

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1235

if (hws->funcs.calculate_dccg_k1_k2_values)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1236

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1264

pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1270

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1290

pipe->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1295

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1324

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1328

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1333

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1334

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1336

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1340

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1381

pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1406

else if (dmcu != NULL && dmcu->funcs->lock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1407

dmcu->funcs->lock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1416

if (dmcu != NULL && dmcu->funcs->unlock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1417

dmcu->funcs->unlock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1522

bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1526

hws->funcs.dsc_pg_control(hws, dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1530

hws->funcs.dsc_pg_control(hws, dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1559

if (hws->funcs.reset_back_end_for_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1560

hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1561

if (hws->funcs.enable_stream_gating)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1562

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1564

old_clk->funcs->cs_power_down(old_clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1585

old_pipe->stream_res.tg->funcs->wait_for_state(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1588

old_pipe->stream_res.tg->funcs->wait_for_state(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1615

if (hws->funcs.apply_single_controller_ctx_to_hw)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1616

status = hws->funcs.apply_single_controller_ctx_to_hw(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1624

if (hws->funcs.resync_fifo_dccg_dio)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1625

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1649

tg->funcs->get_otg_active_size(tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1654

tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1683

if (opp && opp->funcs->opp_set_disp_pattern_generator)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1684

opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1695

if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1696

bottom_opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1705

hws->funcs.wait_for_blank_complete(bottom_opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1710

hws->funcs.wait_for_blank_complete(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1803

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1830

!tg->funcs->is_tg_enabled(tg) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1847

if (hubbub->funcs->program_compbuf_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1848

hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

243

} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

244

num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

409

pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

464

result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

468

result = mpc->funcs->program_shaper(mpc, shaper_lut, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

497

mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

511

mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

515

result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

517

result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

542

dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

552

dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

556

hws->funcs.set_mcm_luts)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

557

result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

575

if (ret == false && mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

590

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

591

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

618

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

619

hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

620

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

621

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

655

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

656

hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

657

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

658

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

677

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

701

hubp->funcs->hubp_update_mall_sel(hubp, 1, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

704

hubp->funcs->hubp_update_mall_sel(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

729

if (hws && hws->funcs.update_mall_sel)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

730

hws->funcs.update_mall_sel(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

737

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

744

hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

769

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

772

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

789

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

790

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

793

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

794

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

796

if (!dcb->funcs->is_accelerated_mode(dcb)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

797

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

798

hws->funcs.disable_vga(dc->hwseq);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

817

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

821

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

841

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

844

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

845

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

848

if (link->link_enc->funcs->fec_is_active &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

849

link->link_enc->funcs->fec_is_active(link->link_enc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

857

if (hws->funcs.enable_power_gating_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

858

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

869

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

876

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

878

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

879

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

908

if (edp_link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

909

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

911

hws->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

914

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

922

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

923

link->link_enc->funcs->is_dig_enabled(link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

924

hws->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

925

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

936

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

943

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

949

if (abms[i] != NULL && abms[i]->funcs != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

950

abms[i]->funcs->abm_init(abms[i], backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

965

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

966

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

968

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

969

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

971

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

973

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

975

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

976

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

979

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

980

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

982

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

983

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

172

dc->hwseq->funcs = dcn32_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

100

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

101

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

103

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

106

dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

109

dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

119

if (dc->res_pool->pg_cntl->funcs->print_pg_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1192

if (pg_cntl->funcs->hpo_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1193

pg_cntl->funcs->hpo_pg_control(pg_cntl, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

120

dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1200

if (pg_cntl->funcs->hubp_dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1201

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1207

if (pg_cntl->funcs->dsc_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1208

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1214

if (pg_cntl->funcs->dsc_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1215

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1220

if (pg_cntl->funcs->hubp_dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1221

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1227

if (pg_cntl->funcs->plane_otg_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1228

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1269

if (pg_cntl->funcs->plane_otg_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1270

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1275

if (pg_cntl->funcs->dsc_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1276

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1283

if (pg_cntl->funcs->hubp_dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1284

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1289

if (pg_cntl->funcs->dsc_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1290

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1295

if (pg_cntl->funcs->hpo_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1296

pg_cntl->funcs->hpo_pg_control(pg_cntl, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1312

if (dc->hwseq->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1313

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1316

if (dc->hwseq->funcs.dpstream_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1317

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1322

if (dc->hwseq->funcs.physymclk_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1323

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1329

if (dc->res_pool->dccg->funcs->enable_dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1330

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1332

if (dc->res_pool->dccg->funcs->disable_dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1333

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1342

if (dc->hwseq->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1343

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1346

if (dc->hwseq->funcs.dpstream_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1347

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1352

if (dc->hwseq->funcs.physymclk_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1353

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1424

if ((tg != NULL) && tg->funcs) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1438

if (tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1439

tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1457

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1483

if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1484

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1485

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal(pipe_ctx[i]->stream_res.tg, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

150

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

151

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

155

if (!dcb->funcs->is_accelerated_mode(dcb)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

157

hws->funcs.bios_golden_init(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

161

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

162

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

172

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

176

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

199

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

202

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

203

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

205

if (link->link_enc->funcs->fec_is_active &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

206

link->link_enc->funcs->fec_is_active(link->link_enc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

214

if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

215

res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

222

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

232

if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

233

tg->funcs->get_optc_source(tg, &num_opps,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

245

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

248

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

250

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

256

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

263

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

269

if (abms[i] != NULL && abms[i]->funcs != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

270

abms[i]->funcs->abm_init(abms[i], backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

281

if (hws->funcs.setup_hpo_hw_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

282

hws->funcs.setup_hpo_hw_control(hws, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

292

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

293

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

295

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

296

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

298

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

299

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

303

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

304

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

307

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

308

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

310

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

311

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

321

if (dc->res_pool->pg_cntl->funcs->init_pg_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

322

dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

351

if (dsc->funcs->dsc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

352

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

368

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

369

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

374

odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

375

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

384

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

390

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

395

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

398

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

441

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

446

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

449

if (mpc->funcs->set_out_rate_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

451

mpc->funcs->set_out_rate_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

460

odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

475

dsc->funcs->dsc_disconnect(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

485

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

486

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

496

if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

497

hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

507

if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

508

hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

529

if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

530

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

531

dc->hwseq->funcs.edp_backlight_control &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

532

dc->hwseq->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

534

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

535

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

541

if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

542

link->link_enc->funcs->is_dig_enabled(link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

543

dc->hwseq->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

544

dc->hwseq->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

556

if (dc->clk_mgr->funcs->set_low_power_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

557

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

650

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

651

if (hws->funcs.init_blank != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

652

hws->funcs.init_blank(dc, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

653

tg->funcs->lock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

655

tg->funcs->lock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

656

tg->funcs->set_blank(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

672

if (hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

673

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

674

if (hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

675

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

687

dc->res_pool->mpc->funcs->mpc_init_single_inst(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

703

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

709

tg->funcs->tg_init(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

718

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

719

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

736

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

738

if (tg->funcs->is_tg_enabled(tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

739

tg->funcs->unlock(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

746

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

747

if (tg->funcs->init_odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

748

tg->funcs->init_odm(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

751

tg->funcs->tg_init(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

769

if (pg_cntl->funcs->dsc_pg_control != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

784

if (tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

785

if (tg->funcs->get_dsc_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

786

tg->funcs->get_dsc_status(tg, &optc_dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

790

tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

802

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

809

pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

823

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

826

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

829

dpp->funcs->dpp_dppclk_control(dpp, false, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

831

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

844

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

851

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

852

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

878

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

880

dpp->funcs->dpp_dppclk_control(dpp, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

885

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

886

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

909

if (hws->funcs.plane_atomic_disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

910

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

915

if (tg && tg->funcs->disable_phantom_crtc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

916

tg->funcs->disable_phantom_crtc(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

997

if (tg && tg->funcs->is_tg_enabled(tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

176

dc->hwseq->funcs = dcn35_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

110

if (pg_cntl->funcs->dsc_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

111

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

116

if (pg_cntl->funcs->hubp_dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

117

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

124

if (pg_cntl->funcs->plane_otg_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

125

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

165

if (pg_cntl->funcs->plane_otg_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

166

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

173

if (pg_cntl->funcs->hubp_dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

174

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

178

if (pg_cntl->funcs->dsc_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

179

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

170

dc->hwseq->funcs = dcn351_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1002

tg->funcs->set_early_control(tg, early_control);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1030

pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1052

else if (dmcu != NULL && dmcu->funcs->lock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1053

dmcu->funcs->lock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1067

else if (dmcu != NULL && dmcu->funcs->lock_phy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1068

dmcu->funcs->unlock_phy(dmcu);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

111

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

117

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1221

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1222

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1263

else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1264

num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

133

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1386

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1389

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1398

dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1403

if (hubbub->funcs->program_arbiter) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1404

dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1408

if (hubbub->funcs->program_compbuf_segments) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1412

hubbub->funcs->program_compbuf_segments(hubbub, compbuf_size, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1443

hubbub->funcs->program_watermarks(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1448

if (hubbub->funcs->program_arbiter) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1449

hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1455

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1458

if (hubbub->funcs->program_compbuf_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1459

hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1461

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1469

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1472

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

148

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

149

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

152

dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

153

dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1556

old_pipe->stream_res.dsc->funcs->dsc_disconnect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

157

if (res_pool->dccg->funcs->dccg_init)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1578

otg_master->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

158

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1583

otg_master->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1588

opp_heads[i]->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1591

opp_heads[i]->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1604

dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1623

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1627

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1631

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1646

dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1647

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1651

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1656

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1687

hubbub->funcs->wait_for_det_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1688

hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1691

if (hubbub && opp_heads[slice_idx]->plane_res.hubp && hubbub->funcs->wait_for_det_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1692

hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1710

!tg->funcs->is_tg_enabled(tg) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1722

!tg->funcs->is_tg_enabled(tg) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1743

!tg->funcs->is_tg_enabled(tg) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1777

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1778

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1781

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1782

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1785

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1786

if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1787

pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1790

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1791

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1794

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1795

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1797

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1807

if (hubbub->funcs->program_compbuf_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1808

hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

181

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1839

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1859

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1861

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1862

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1863

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

187

(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1881

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1882

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1922

if (hws->funcs.reset_back_end_for_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1923

hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1924

if (hws->funcs.enable_stream_gating)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1925

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1927

old_clk->funcs->cs_power_down(old_clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1964

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1973

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1975

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1978

if (hws->funcs.setup_vupdate_interrupt)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1979

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1994

hws->funcs.blank_pixel_data(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2005

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2008

if (hws->funcs.enable_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2009

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2013

if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2014

dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2018

if (dc->res_pool->hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2019

dc->res_pool->hubbub->funcs->program_det_size(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2021

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2022

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2033

hws->funcs.set_hdr_multiplier(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2040

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2049

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2059

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2065

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2075

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2085

odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

210

link->link_enc->funcs->hw_init(link->link_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

213

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2136

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2137

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

214

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2159

if (tg->funcs->enable_crtc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2160

if (dc->hwseq->funcs.blank_pixel_data)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2163

tg->funcs->enable_crtc(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

217

if (link->link_enc->funcs->fec_is_active &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2173

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

218

link->link_enc->funcs->fec_is_active(link->link_enc))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2192

if (hubbub->funcs->program_det_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2193

hubbub->funcs->program_det_size(hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2195

if (dc->res_pool->hubbub->funcs->program_det_segments)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2196

dc->res_pool->hubbub->funcs->program_det_segments(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2199

hws->funcs.plane_atomic_disconnect(dc, dc->current_state,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2210

hws->funcs.update_odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2211

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2223

if (hws->funcs.program_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2249

&& hws->funcs.program_all_writeback_pipes_in_tree)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2250

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2256

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2259

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

226

if (hws->funcs.enable_power_gating_plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

227

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2301

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2320

if (tg->funcs->get_optc_double_buffer_pending) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2322

&& tg->funcs->get_optc_double_buffer_pending(tg); j++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2328

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2329

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2368

if (hwseq->funcs.update_force_pstate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2369

dc->hwseq->funcs.update_force_pstate(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2374

if (hwseq->funcs.program_mall_pipe_config)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2375

hwseq->funcs.program_mall_pipe_config(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2379

dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

238

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2390

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2394

tg->funcs->get_frame_count(tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2407

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2423

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2431

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2435

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2437

if (hws->funcs.setup_vupdate_interrupt)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2438

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2441

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2442

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

245

hws->funcs.init_pipes(dc, dc->current_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

247

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

248

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2665

if (hws->funcs.dpp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2666

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2668

if (hws->funcs.hubp_pg_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2669

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2671

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2672

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2681

if (hws->funcs.dpp_root_clock_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2682

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

277

if (edp_link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

278

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

280

hws->funcs.power_down &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

283

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

293

if (link->link_enc->funcs->is_dig_enabled &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

294

link->link_enc->funcs->is_dig_enabled(link->link_enc) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

295

hws->funcs.power_down) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

296

hws->funcs.power_down(dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

307

audio->funcs->hw_init(audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

314

backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

320

if (abms[i] != NULL && abms[i]->funcs != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

321

abms[i]->funcs->abm_init(abms[i], backlight, user_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

338

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

339

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

341

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

342

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

344

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

345

dc->res_pool->hubbub->funcs->force_pstate_change_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

348

if (dc->res_pool->hubbub->funcs->init_crb)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

349

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

351

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

352

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

366

dc->res_pool->funcs->update_bw_bounding_box(dc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

386

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

442

if (mpc->funcs->populate_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

443

mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

445

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

446

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

462

if (mpc->funcs->mcm.populate_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

463

mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

464

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

465

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

473

if (hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

474

hubp->funcs->hubp_enable_3dlut_fl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

478

if (mpc->funcs->populate_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

479

mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

480

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

481

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

499

if (mpc->funcs->mcm.is_config_supported &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

500

!mpc->funcs->mcm.is_config_supported(width))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

503

if (mpc->funcs->program_lut_read_write_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

504

mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

505

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

506

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

508

if (hubp->funcs->hubp_program_3dlut_fl_addr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

509

hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

511

if (mpc->funcs->mcm.program_bit_depth)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

512

mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

532

if (hubp->funcs->hubp_program_3dlut_fl_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

533

hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

535

if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

536

hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

549

if (hubp->funcs->hubp_program_3dlut_fl_format)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

550

hubp->funcs->hubp_program_3dlut_fl_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

551

if (hubp->funcs->hubp_update_3dlut_fl_bias_scale &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

552

mpc->funcs->mcm.program_bias_scale) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

553

mpc->funcs->mcm.program_bias_scale(mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

557

hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

573

if (hubp->funcs->hubp_program_3dlut_fl_crossbar)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

574

hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

579

if (mpc->funcs->mcm.program_lut_read_write_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

580

mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

582

if (mpc->funcs->mcm.program_3dlut_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

583

mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

585

if (mpc->funcs->update_3dlut_fast_load_select)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

586

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

588

if (hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

589

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

591

if (mpc->funcs->program_lut_mode) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

592

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

593

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

594

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

606

if (hubp->funcs->hubp_enable_3dlut_fl) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

607

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

627

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

638

result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

651

result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

654

if (mpc->funcs->program_3dlut) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

656

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

658

result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

677

if (ret == false && mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

692

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

693

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

71

if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

72

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

783

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

784

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

794

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

801

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

803

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

81

dc->clk_mgr->funcs->update_clocks(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

810

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

812

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

821

if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

822

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

831

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

843

opp_heads[i]->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

846

opp_heads[i]->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

852

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

856

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

859

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

864

hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

871

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

872

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

884

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

885

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

970

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

972

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

974

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

977

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

982

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

983

dc->res_pool->dccg->funcs->set_pixel_rate_div(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

152

dc->hwseq->funcs = dcn401_private_funcs;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

198

struct hwseq_private_funcs funcs;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

185

const struct clock_source_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

83

const struct compressor_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

325

const struct resource_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h

34

const struct abm_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/audio.h

60

const struct audio_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

94

const struct aux_engine_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

347

struct clk_mgr_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

348

struct clk_mgr_internal_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

76

const struct dccg_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

259

const struct hubbub_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h

50

const struct dmcu_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

70

const struct dpp_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h

157

const struct dwbc_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

119

const struct hubp_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/ipp.h

40

const struct ipp_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

235

const struct hpo_dp_link_encoder_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

79

const struct link_encoder_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/mcif_wb.h

69

const struct mcif_wb_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

83

const struct mem_input_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

325

const struct mpc_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

241

const struct opp_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

64

const struct panel_cntl_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h

34

const struct pg_cntl_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

113

const struct stream_encoder_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

292

const struct hpo_dp_stream_encoder_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

185

const struct timing_generator_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h

39

const struct transform_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/inc/hw/vpg.h

48

const struct vpg_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

101

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

115

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

129

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

145

.funcs = &vupdate_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

161

.funcs = &vblank_irq_info_funcs,\

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

167

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

222

if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

416

irq_service->funcs = &irq_service_funcs_dce110;

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

105

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

113

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

121

.funcs = &vupdate_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

129

.funcs = &vblank_irq_info_funcs,\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

135

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

254

irq_service->funcs = &irq_service_funcs_dce120;

sys/dev/pci/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

96

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

100

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

115

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

131

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

147

.funcs = &vblank_irq_info_funcs_dce60\

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

152

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

352

irq_service->funcs = &irq_service_funcs_dce60;

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

86

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

106

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

122

.funcs = &vupdate_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

138

.funcs = &vblank_irq_info_funcs,\

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

144

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

264

irq_service->funcs = &irq_service_funcs_dce80;

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

77

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

91

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

193

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

202

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

209

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

220

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

228

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

236

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

241

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

366

irq_service->funcs = &irq_service_funcs_dcn10;

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

198

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

207

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

214

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

225

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

233

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

241

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

246

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

371

irq_service->funcs = &irq_service_funcs_dcn20;

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

145

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

154

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

161

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

169

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

180

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

187

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

195

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

200

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

325

irq_service->funcs = &irq_service_funcs_dcn201;

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

220

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

229

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

236

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

247

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

255

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

263

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

270

.funcs = &dmub_outbox_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

275

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

399

irq_service->funcs = &irq_service_funcs_dcn21;

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

229

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

238

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

245

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

256

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

264

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

271

.funcs = &dmub_trace_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

279

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

284

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

410

irq_service->funcs = &irq_service_funcs_dcn30;

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

193

.funcs = &dmub_trace_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

216

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

225

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

232

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

243

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

251

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

259

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

262

#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

375

irq_service->funcs = &irq_service_funcs_dcn302;

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

140

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

149

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

156

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

167

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

175

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

183

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

186

#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

271

irq_service->funcs = &irq_service_funcs_dcn303;

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

215

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

224

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

231

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

242

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

250

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

258

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

265

.funcs = &outbox_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

270

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

390

irq_service->funcs = &irq_service_funcs_dcn31;

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

217

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

226

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

233

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

244

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

252

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

260

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

267

.funcs = &outbox_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

272

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

392

irq_service->funcs = &irq_service_funcs_dcn314;

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

222

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

231

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

238

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

249

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

257

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

265

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

272

.funcs = &outbox_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

277

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

397

irq_service->funcs = &irq_service_funcs_dcn315;

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

226

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

235

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

242

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

250

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

260

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

268

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

275

.funcs = &vline1_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

282

.funcs = &vline2_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

289

.funcs = &outbox_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

294

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

422

irq_service->funcs = &irq_service_funcs_dcn32;

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

212

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

220

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

226

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

235

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

241

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

247

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

253

REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

256

REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

386

irq_service->funcs = &irq_service_funcs_dcn35;

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

191

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

199

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

205

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

214

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

220

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

226

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

232

REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

235

REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

368

irq_service->funcs = &irq_service_funcs_dcn351;

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

190

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

204

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

213

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

219

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

225

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

231

REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

234

REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

367

irq_service->funcs = &irq_service_funcs_dcn36;

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

206

.funcs = &hpd_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

215

.funcs = &hpd_rx_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

222

.funcs = &pflip_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

230

.funcs = &vblank_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

240

.funcs = &vupdate_no_lock_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

248

.funcs = &vline0_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

255

.funcs = &vline1_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

262

.funcs = &vline2_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

269

.funcs = &outbox_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

274

.funcs = &dummy_irq_info_funcs\

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

400

irq_service->funcs = &irq_service_funcs_dcn401;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

125

if (info->funcs && info->funcs->set) {

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

126

if (info->funcs->set == dal_irq_service_dummy_set) {

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

132

return info->funcs->set(irq_service, info, enable);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

166

if (info->funcs && info->funcs->ack) {

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

167

if (info->funcs->ack == dal_irq_service_dummy_ack) {

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

172

return info->funcs->ack(irq_service, info);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

185

return irq_service->funcs->to_dal_irq_source(

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

56

struct irq_source_info_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

69

const struct irq_service_funcs *funcs;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

102

if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

103

link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

107

pipes[i]->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

120

pipes[i]->stream_res.audio->funcs->az_configure(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

128

pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio &&

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

130

pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio(pipes[i]->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

141

pipes[i]->stream_res.tg->funcs->enable_crtc(pipes[i]->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

508

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

509

opp->funcs->opp_program_bit_depth_reduction(opp, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

510

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

527

odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

547

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

548

opp->funcs->opp_program_bit_depth_reduction(opp, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

549

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

559

odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

879

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

892

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

896

pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

919

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

920

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

922

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

924

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

927

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

940

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

99

pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

101

link_enc->funcs->connect_dig_be_to_fe(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

119

stream_encoder->funcs->setup_stereo_sync(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

125

stream_encoder->funcs->dp_set_stream_attribute(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

132

stream_encoder->funcs->hdmi_set_stream_attribute(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

138

stream_encoder->funcs->dvi_set_stream_attribute(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

143

stream_encoder->funcs->lvds_set_stream_attribute(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

168

link_enc->funcs->enable_dp_output(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

173

link_enc->funcs->enable_dp_mst_output(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

194

link_enc->funcs->disable_output(link_enc, signal);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

212

link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

230

link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

246

link_enc->funcs->update_mst_stream_allocation_table(link_enc, table);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

253

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

258

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

268

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

271

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

282

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

287

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

290

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

44

stream_encoder->funcs->set_throttled_vcp_size(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

61

link_enc->funcs->connect_dig_be_to_fe(link_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

66

if (stream_enc->funcs->enable_stream)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

67

stream_enc->funcs->enable_stream(stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

69

if (stream_enc->funcs->map_stream_to_link)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

70

stream_enc->funcs->map_stream_to_link(stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

72

if (stream_enc->funcs->set_input_mode)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

73

stream_enc->funcs->set_input_mode(stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

75

if (stream_enc->funcs->enable_fifo)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

76

stream_enc->funcs->enable_fifo(stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

94

if (stream_enc->funcs->disable_fifo)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

95

stream_enc->funcs->disable_fifo(stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

96

if (stream_enc->funcs->set_input_mode)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

97

stream_enc->funcs->set_input_mode(stream_enc, 0);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

98

if (stream_enc->funcs->enable_stream)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

99

stream_enc->funcs->enable_stream(stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

137

link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

103

if (link_enc->funcs->enable_dpia_output)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

104

link_enc->funcs->enable_dpia_output(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

135

if (link_enc->funcs->disable_dpia_output)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

136

link_enc->funcs->disable_dpia_output(link_enc, link->ddc_hw_inst, digmode);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

140

link_enc->funcs->disable_output(link_enc, signal);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

168

return link->is_dig_mapping_flexible && link->dc->res_pool->funcs->link_encs_assign;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

57

link_enc->funcs->update_mst_stream_allocation_table(link_enc, table);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

75

link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

118

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

119

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

123

link_res->hpo_dp_link_enc->funcs->enable_link_phy(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

139

link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

140

link_res->hpo_dp_link_enc->funcs->disable_link_phy(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

142

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

143

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

153

link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

163

link_res->hpo_dp_link_enc->funcs->set_ffe(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

173

link_res->hpo_dp_link_enc->funcs->update_stream_allocation_table(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

181

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

189

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

196

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

41

hpo_dp_link_encoder->funcs->set_throttled_vcp_size(hpo_dp_link_encoder,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

70

hpo_dp_stream_encoder->funcs->set_hblank_min_symbol_width(hpo_dp_stream_encoder,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

79

stream_enc->funcs->enable_stream(stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

80

stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

87

stream_enc->funcs->disable(stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

96

stream_enc->funcs->set_stream_attribute(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

165

link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

188

link_res->hpo_dp_link_enc->funcs->set_ffe(

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1197

if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1198

dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

657

if (!link->link_enc->funcs->is_in_alt_mode)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

660

is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

671

if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

827

link->dc->res_pool->funcs->link_encs_assign &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1002

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

129

link->link_enc->funcs->get_dig_frontend &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

130

link->link_enc->funcs->is_dig_enabled(link->link_enc)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

131

int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

136

dc->res_pool->stream_enc[j]->funcs->dp_blank(link,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2101

state->clk_mgr->funcs->update_clocks(state->clk_mgr,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2439

if (pipe_ctx->stream_res.tg->funcs->set_out_mux)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2440

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2443

if (vpg && vpg->funcs->vpg_powerdown)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2444

vpg->funcs->vpg_powerdown(vpg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2497

link_enc->funcs->setup(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2504

if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2509

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2517

if (vpg && vpg->funcs->vpg_poweron)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2518

vpg->funcs->vpg_poweron(vpg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2605

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2606

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2618

link_enc->funcs->setup(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

670

if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

724

cp_psp->funcs.update_stream_config(cp_psp->handle, &config);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

822

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

846

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

847

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

848

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

853

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

854

odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

855

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

866

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

867

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

878

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

884

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

891

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

897

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

898

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

901

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

908

odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

930

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

931

if (dccg->funcs->set_ref_dscclk)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

932

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

974

dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

979

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

985

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

996

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

389

link->panel_cntl->funcs->destroy(&link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

400

link->link_enc->funcs->destroy(&link->link_enc);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

463

const struct dc_vbios_funcs *bp_funcs = bios->funcs;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

483

bios->funcs->get_connector_id(bios, init_params->connector_index);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

489

if (bios->funcs->get_disp_connector_caps_info) {

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

490

bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

502

if (link->dc->res_pool->funcs->link_init)

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

503

link->dc->res_pool->funcs->link_init(link);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

625

link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

644

if (link->dc->res_pool->funcs->panel_cntl_create &&

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

651

link->dc->res_pool->funcs->panel_cntl_create(

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

725

if (bios->funcs->get_atom_dc_golden_table)

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

726

bios->funcs->get_atom_dc_golden_table(bios);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

742

link->link_enc->funcs->destroy(&link->link_enc);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

745

link->panel_cntl->funcs->destroy(&link->panel_cntl);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

813

if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

814

link->dpia_preferred_eng_id = link->dc->res_pool->funcs->get_preferred_eng_id_dpia(link->ddc_hw_inst);

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

40

stream_enc->funcs->hdmi_frl_set_stream_attribute(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

123

dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

527

if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

528

ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2222

if (link_enc && link_enc->funcs->get_max_link_cap) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2223

link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2258

link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

152

if (link_enc->funcs->fec_set_ready == NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

162

link_enc->funcs->fec_set_ready(link_enc, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

172

link_enc->funcs->fec_set_ready(link_enc, false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

187

if (link_enc == NULL || link_enc->funcs == NULL || link_enc->funcs->fec_set_enable == NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

200

link_enc->funcs->fec_set_enable(link_enc, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

205

link_enc->funcs->fec_set_enable(link_enc, false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

87

if (dc->clk_mgr->funcs->notify_link_rate_change)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

88

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1051

replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1108

replay->funcs->replay_send_cmd(replay, msg, cmd_data);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1126

replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1147

replay->funcs->replay_residency(replay, panel_inst, residency, is_start, mode);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1168

replay->funcs->replay_set_power_opt_and_coasting_vtotal) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1169

replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1208

fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1210

if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1211

return panel_cntl->funcs->get_current_backlight(panel_cntl);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1212

else if (abm != NULL && abm->funcs->get_current_backlight != NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1213

return (int) abm->funcs->get_current_backlight(abm);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1222

if (abm == NULL || abm->funcs->get_target_backlight == NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1225

return (int) abm->funcs->get_target_backlight(abm);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1286

} else if (cp_psp && cp_psp->funcs.enable_assr && enable) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1294

result = cp_psp->funcs.enable_assr(cp_psp->handle, link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

607

if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

608

psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

612

force_static && psr->funcs->psr_force_static)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

613

psr->funcs->psr_force_static(psr, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

623

psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

624

} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

626

dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

644

psr->funcs->psr_get_state(psr, state, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

646

dmcu->funcs->get_psr_state(dmcu, state);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

890

link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

895

link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

919

psr->funcs->psr_get_residency(psr, residency, panel_inst, mode);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

931

psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

952

replay->funcs->replay_set_power_opt) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

953

replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

963

replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

981

replay->funcs->replay_get_state(replay, &pr_state, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

104

if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

107

bp_result = dcb->funcs->get_gpio_pin_info(dcb,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

51

if (encoder != NULL && encoder->funcs->enable_hpd != NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

52

encoder->funcs->enable_hpd(encoder);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

59

if (encoder != NULL && encoder->funcs->enable_hpd != NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

60

encoder->funcs->disable_hpd(encoder);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

319

mcif_wb20->base.funcs = &dcn20_mmhubbub_funcs;

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

234

mcif_wb30->base.funcs = &dcn32_mmhubbub_funcs;

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

247

mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

509

mpc10->base.funcs = &dcn10_mpc_funcs;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

598

mpc20->base.funcs = &dcn20_mpc_funcs;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1563

mpc30->base.funcs = &dcn30_mpc_funcs;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

1038

mpc30->base.funcs = &dcn32_mpc_funcs;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

622

mpc401->base.funcs = &dcn401_mpc_funcs;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

408

oppn10->base.funcs = &dcn10_opp_funcs;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

409

oppn20->base.funcs = &dcn20_opp_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1673

optc1->base.funcs = &dcn10_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

229

optc->funcs->set_vtotal_min_max(optc, v_total, v_total);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

286

optc->funcs->program_global_sync(optc,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

293

optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

305

if (optc->funcs->is_two_pixels_per_container(&patched_crtc_timing) || optc1->opp_count == 2)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

505

if (optc->funcs->is_optc_underflow_occurred(optc) == true)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

506

optc->funcs->clear_optc_underflow(optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

714

optc->funcs->get_position(optc, &position1);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

715

optc->funcs->get_position(optc, &position2);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

945

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

956

optc->funcs->setup_manual_trigger(optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

173

h_div_2 = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

570

optc1->base.funcs = &dcn20_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

188

optc1->base.funcs = &dcn201_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

209

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

428

optc1->base.funcs = &dcn30_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

180

optc1->base.funcs = &dcn30_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

74

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

83

optc->funcs->setup_manual_trigger(optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

92

optc->funcs->set_vtotal_min_max(optc, 0, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

201

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

216

optc->funcs->setup_manual_trigger(optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

224

optc->funcs->set_vtotal_min_max(optc, 0, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

384

optc1->base.funcs = &dcn31_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

177

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

263

optc1->base.funcs = &dcn314_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

241

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

294

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

372

optc1->base.funcs = &dcn32_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

296

if (optc->funcs && optc->funcs->setup_manual_trigger)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

297

optc->funcs->setup_manual_trigger(optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

327

if (optc->funcs && optc->funcs->set_vtotal_min_max)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

328

optc->funcs->set_vtotal_min_max(optc,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

338

if (optc->funcs && optc->funcs->set_vtotal_min_max)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

339

optc->funcs->set_vtotal_min_max(optc, 0, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

367

if (optc->funcs && optc->funcs->set_vtotal_min_max)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

368

optc->funcs->set_vtotal_min_max(optc, 0, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

379

if (optc->funcs && optc->funcs->set_vtotal_min_max)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

380

optc->funcs->set_vtotal_min_max(optc, max_otg_v_total, max_otg_v_total);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

399

if (optc->funcs && optc->funcs->set_vtotal_min_max)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

400

optc->funcs->set_vtotal_min_max(optc, 0, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

422

if (optc->funcs && optc->funcs->set_vtotal_min_max)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

423

optc->funcs->set_vtotal_min_max(optc,

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

518

optc1->base.funcs = &dcn35_tg_funcs;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

281

h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

359

optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

368

optc->funcs->set_vtotal_min_max(optc, 0, 0);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

540

optc1->base.funcs = &dcn401_tg_funcs;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

555

base->funcs = &pg_cntl35_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1011

pool->base.funcs = &dce100_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1150

hws->funcs.enable_display_power_gating(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1160

pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1170

pipe_ctx->stream_res.tg->funcs->enable_advanced_request(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1175

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1183

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1362

pool->base.funcs = &dce110_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

920

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1234

pool->base.funcs = &dce112_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1076

pool->base.funcs = &dce120_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1097

pool->base.funcs = &dce60_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1295

pool->base.funcs = &dce60_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

899

pool->base.funcs = &dce60_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1107

pool->base.funcs = &dce80_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1307

pool->base.funcs = &dce80_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

905

pool->base.funcs = &dce80_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1034

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1114

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1331

pool->base.funcs = &dcn10_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

921

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

927

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1111

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1138

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1254

else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1256

else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1257

if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1264

if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1265

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1266

(hws->funcs.is_dp_dig_pixel_rate_div_policy &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1267

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1285

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1295

if (pool->funcs->build_pipe_pix_clk_params) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1296

pool->funcs->build_pipe_pix_clk_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1672

if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2024

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2176

if (dc->res_pool->hubbub->funcs->get_dcc_compression_cap)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2177

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2408

pool->base.funcs = &dcn20_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2728

dc->hwseq->funcs.enable_power_gating_plane = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1033

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1097

pool->base.funcs = &dcn201_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

937

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

951

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1399

pool->base.funcs = &dcn21_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

682

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

708

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

786

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1102

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1129

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1648

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1649

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1868

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2075

if (dc->res_pool->funcs->calculate_wm_and_dlg)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2076

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2293

pool->base.funcs = &dcn30_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2360

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2364

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2368

if (ctx->dc_bios->funcs->get_lttpr_interop) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2372

bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1073

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1100

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1308

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1311

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1426

pool->base.funcs = &dcn301_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1486

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1490

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1494

if (ctx->dc_bios->funcs->get_lttpr_interop) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1498

bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1052

pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1212

pool->funcs = &dcn302_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1277

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1281

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1285

if (ctx->dc_bios->funcs->get_lttpr_interop) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1289

bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

973

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

976

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1153

pool->funcs = &dcn303_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1222

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1226

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1230

if (ctx->dc_bios->funcs->get_lttpr_interop) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1234

bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

918

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

921

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

996

pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1403

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1430

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1797

if (dc->res_pool->funcs->calculate_wm_and_dlg)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1798

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1895

pool->base.funcs = &dcn31_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1968

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1972

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2254

link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1462

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1488

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1736

if (dc->res_pool->funcs->calculate_wm_and_dlg)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1737

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1825

pool->base.funcs = &dcn314_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1900

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1904

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1403

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1430

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1865

pool->base.funcs = &dcn315_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1929

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1933

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1399

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1426

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1741

pool->base.funcs = &dcn316_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1805

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1809

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1409

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1436

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1787

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2189

pool->base.funcs = &dcn32_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2287

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2291

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2529

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

97

} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

98

return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1390

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1416

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1693

pool->base.funcs = &dcn321_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1787

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1791

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2024

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1472

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1499

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1844

pool->base.funcs = &dcn35_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1936

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1940

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1452

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1479

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1817

pool->base.funcs = &dcn351_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1907

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1911

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1453

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1480

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1817

pool->base.funcs = &dcn36_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1908

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1912

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1412

pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1439

pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1733

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1869

pool->base.funcs = &dcn401_res_pool_funcs;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1985

if (ctx->dc_bios->funcs->get_lttpr_caps) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1989

bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2225

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

215

if (dc->clk_mgr->funcs->is_smu_present &&

sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

216

dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) {

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c

116

enc->funcs = &virtual_lnk_enc_funcs;

sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c

151

enc->funcs = &virtual_str_enc_funcs;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

522

struct dmub_srv_base_funcs funcs;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

556

struct dmub_srv_base_funcs funcs;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

101

srv->funcs.reg_write(srv->user_ctx, addr, reg_val);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

107

uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

84

reg_val = srv->funcs.reg_read(srv->user_ctx, addr);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

86

srv->funcs.reg_write(srv->user_ctx, addr, reg_val);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

51

#define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

54

((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

164

struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

178

funcs->reset = dmub_dcn20_reset;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

179

funcs->reset_release = dmub_dcn20_reset_release;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

180

funcs->backdoor_load = dmub_dcn20_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

181

funcs->setup_windows = dmub_dcn20_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

182

funcs->setup_mailbox = dmub_dcn20_setup_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

183

funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

184

funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

185

funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

186

funcs->is_supported = dmub_dcn20_is_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

187

funcs->is_hw_init = dmub_dcn20_is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

188

funcs->set_gpint = dmub_dcn20_set_gpint;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

189

funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

190

funcs->get_gpint_response = dmub_dcn20_get_gpint_response;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

191

funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

192

funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

193

funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

194

funcs->get_current_time = dmub_dcn20_get_current_time;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

197

funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

198

funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

199

funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

202

funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

203

funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

204

funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

206

funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

214

funcs->backdoor_load = dmub_dcn30_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

215

funcs->setup_windows = dmub_dcn30_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

220

funcs->backdoor_load = dmub_dcn30_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

221

funcs->setup_windows = dmub_dcn30_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

226

funcs->backdoor_load = dmub_dcn30_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

227

funcs->setup_windows = dmub_dcn30_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

232

funcs->backdoor_load = dmub_dcn30_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

233

funcs->setup_windows = dmub_dcn30_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

244

funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

251

funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

253

funcs->reset = dmub_dcn31_reset;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

254

funcs->reset_release = dmub_dcn31_reset_release;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

255

funcs->backdoor_load = dmub_dcn31_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

256

funcs->setup_windows = dmub_dcn31_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

257

funcs->setup_mailbox = dmub_dcn31_setup_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

258

funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

259

funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

260

funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

261

funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

262

funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

263

funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

264

funcs->is_supported = dmub_dcn31_is_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

265

funcs->is_hw_init = dmub_dcn31_is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

266

funcs->set_gpint = dmub_dcn31_set_gpint;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

267

funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

268

funcs->get_gpint_response = dmub_dcn31_get_gpint_response;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

269

funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

270

funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

271

funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

272

funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

273

funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

275

funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

276

funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

277

funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

279

funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

280

funcs->should_detect = dmub_dcn31_should_detect;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

281

funcs->get_current_time = dmub_dcn31_get_current_time;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

288

funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

289

funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

290

funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

291

funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

292

funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

293

funcs->reset = dmub_dcn32_reset;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

294

funcs->reset_release = dmub_dcn32_reset_release;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

295

funcs->backdoor_load = dmub_dcn32_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

296

funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

297

funcs->setup_windows = dmub_dcn32_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

298

funcs->setup_mailbox = dmub_dcn32_setup_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

299

funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

300

funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

301

funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

302

funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

303

funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

304

funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

305

funcs->is_supported = dmub_dcn32_is_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

306

funcs->is_hw_init = dmub_dcn32_is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

307

funcs->set_gpint = dmub_dcn32_set_gpint;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

308

funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

309

funcs->get_gpint_response = dmub_dcn32_get_gpint_response;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

310

funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

311

funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

312

funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

313

funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

316

funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

317

funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

318

funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

319

funcs->get_current_time = dmub_dcn32_get_current_time;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

320

funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

321

funcs->init_reg_offsets = dmub_srv_dcn32_regs_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

329

funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

330

funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

331

funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

332

funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

333

funcs->reset = dmub_dcn35_reset;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

334

funcs->reset_release = dmub_dcn35_reset_release;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

335

funcs->backdoor_load = dmub_dcn35_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

336

funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

337

funcs->setup_windows = dmub_dcn35_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

338

funcs->setup_mailbox = dmub_dcn35_setup_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

339

funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

340

funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

341

funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

342

funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

343

funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

344

funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

345

funcs->is_supported = dmub_dcn35_is_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

346

funcs->is_hw_init = dmub_dcn35_is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

347

funcs->set_gpint = dmub_dcn35_set_gpint;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

348

funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

349

funcs->get_gpint_response = dmub_dcn35_get_gpint_response;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

350

funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

351

funcs->get_fw_status = dmub_dcn35_get_fw_boot_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

352

funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

353

funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

354

funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

356

funcs->setup_outbox0 = dmub_dcn35_setup_outbox0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

357

funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

358

funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

360

funcs->get_current_time = dmub_dcn35_get_current_time;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

361

funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

363

funcs->init_reg_offsets = dmub_srv_dcn35_regs_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

365

funcs->init_reg_offsets = dmub_srv_dcn351_regs_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

367

funcs->init_reg_offsets = dmub_srv_dcn36_regs_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

369

funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

370

funcs->should_detect = dmub_dcn35_should_detect;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

375

funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

376

funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

377

funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

378

funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

379

funcs->reset = dmub_dcn401_reset;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

380

funcs->reset_release = dmub_dcn401_reset_release;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

381

funcs->backdoor_load = dmub_dcn401_backdoor_load;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

382

funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

383

funcs->setup_windows = dmub_dcn401_setup_windows;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

384

funcs->setup_mailbox = dmub_dcn401_setup_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

385

funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

386

funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

387

funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

388

funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

389

funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

390

funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

391

funcs->is_supported = dmub_dcn401_is_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

392

funcs->is_hw_init = dmub_dcn401_is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

393

funcs->set_gpint = dmub_dcn401_set_gpint;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

394

funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

395

funcs->get_gpint_response = dmub_dcn401_get_gpint_response;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

396

funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

397

funcs->get_fw_status = dmub_dcn401_get_fw_boot_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

398

funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

399

funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

401

funcs->setup_outbox0 = dmub_dcn401_setup_outbox0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

402

funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

403

funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

405

funcs->get_current_time = dmub_dcn401_get_current_time;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

406

funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

408

funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

409

funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

410

funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

411

funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

412

funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

413

funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

416

funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

417

funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

418

funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

419

funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

420

funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

421

funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

422

funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

433

} else if (funcs->send_reg_inbox0_cmd_msg) {

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

452

dmub->funcs = params->funcs;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_execution.c

500

const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_execution.c

501

&& hdcp->config.ddc.funcs.atomic_write_poll_read_aux

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

188

const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

514

const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_aux

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

172

success = hdcp->config.ddc.funcs.read_dpcd(hdcp->config.ddc.handle,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

188

success = hdcp->config.ddc.funcs.read_i2c(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

243

success = hdcp->config.ddc.funcs.write_dpcd(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

262

success = hdcp->config.ddc.funcs.write_i2c(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

685

return hdcp->config.ddc.funcs.write_dpcd(hdcp->config.ddc.handle, cp_irq_addrs,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

710

return hdcp->config.ddc.funcs.atomic_write_poll_read_aux(

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

747

return hdcp->config.ddc.funcs.atomic_write_poll_read_i2c(

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

185

} funcs;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

190

void *funcs;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

757

result = res_pool->multiple_abms[inst]->funcs->init_abm_config(

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

760

result = res_pool->abm->funcs->init_abm_config(

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

775

if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

782

result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

787

result = dmcu->funcs->load_iram(

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

792

result = dmcu->funcs->load_iram(

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

797

result = dmcu->funcs->load_iram(

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

801

result = dmcu->funcs->load_iram(

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3331

.funcs = &kv_dpm_ip_funcs,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3360

adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8125

.funcs = &si_dpm_ip_funcs,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8157

adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

303

.funcs = &pp_ip_funcs,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4660

source->funcs = &smu7_irq_funcs;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

654

source->funcs = &smu9_irq_funcs;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2099

!((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2100

!amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2101

adev->gfx.rlc.funcs->stop(adev);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2799

.funcs = &smu_ip_funcs,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2807

.funcs = &smu_ip_funcs,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2815

.funcs = &smu_ip_funcs,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2823

.funcs = &smu_ip_funcs,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1495

irq_src->funcs = &smu_v11_0_irq_funcs;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

276

if (adev->smuio.funcs->get_socket_id(adev) ||

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

277

adev->smuio.funcs->get_die_id(adev))

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

556

if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

557

return adev->smuio.funcs->get_die_id(adev) == 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1388

irq_src->funcs = &smu_v13_0_irq_funcs;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1970

irq_src->funcs = &smu_v13_0_6_irq_funcs;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1044

irq_src->funcs = &smu_v14_0_irq_funcs;

sys/dev/pci/drm/apple/apple_drv.c

530

apple->drm.mode_config.funcs = &apple_mode_config_funcs;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5790

mgr->funcs = NULL;

sys/dev/pci/drm/display/drm_dp_tunnel.c

25

((__obj)->funcs == &tunnel_group_funcs)

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

158

const struct drm_connector_hdmi_audio_funcs *funcs,

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

176

if (!funcs ||

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

177

!funcs->prepare ||

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

178

!funcs->shutdown)

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

181

connector->hdmi_audio.funcs = funcs;

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

20

const struct drm_connector_hdmi_audio_funcs *funcs =

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

21

connector->hdmi_audio.funcs;

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

23

if (funcs->startup)

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

24

return funcs->startup(connector);

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

34

const struct drm_connector_hdmi_audio_funcs *funcs =

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

35

connector->hdmi_audio.funcs;

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

37

return funcs->prepare(connector, fmt, hparms);

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

43

const struct drm_connector_hdmi_audio_funcs *funcs =

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

44

connector->hdmi_audio.funcs;

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

46

return funcs->shutdown(connector);

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

53

const struct drm_connector_hdmi_audio_funcs *funcs =

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

54

connector->hdmi_audio.funcs;

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

56

if (funcs->mute_stream)

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

57

return funcs->mute_stream(connector, enable, direction);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

104

data->funcs = funcs;

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

121

connector->cec.funcs = &drm_connector_hdmi_cec_adapter_funcs;

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

123

ret = funcs->init(connector);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

18

const struct drm_connector_hdmi_cec_funcs *funcs;

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

26

return data->funcs->enable(connector, enable);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

34

return data->funcs->log_addr(connector, logical_addr);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

43

return data->funcs->transmit(connector, attempts, signal_free_time, msg);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

74

if (data->funcs->uninit)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

75

data->funcs->uninit(connector);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

87

const struct drm_connector_hdmi_cec_funcs *funcs,

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

97

if (!funcs->init || !funcs->enable || !funcs->log_addr || !funcs->transmit)

sys/dev/pci/drm/display/drm_hdmi_cec_notifier_helper.c

57

connector->cec.funcs = &drm_connector_cec_notifier_funcs;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

1136

if (connector->hdmi.funcs->read_edid)

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

1137

drm_edid = connector->hdmi.funcs->read_edid(connector);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

535

const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

541

if (funcs && funcs->tmds_char_rate_valid) {

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

544

status = funcs->tmds_char_rate_valid(connector, mode, clock);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

897

const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

903

if (!funcs || !funcs->clear_infoframe) {

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

908

ret = funcs->clear_infoframe(connector, type);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

932

const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

940

if (!funcs || !funcs->write_infoframe) {

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

949

ret = funcs->write_infoframe(connector, frame->any.type, buffer, len);

sys/dev/pci/drm/drm_atomic.c

1177

connector_state = connector->funcs->atomic_duplicate_state(connector);

sys/dev/pci/drm/drm_atomic.c

1233

if (connector->funcs->atomic_print_state)

sys/dev/pci/drm/drm_atomic.c

1234

connector->funcs->atomic_print_state(p, state);

sys/dev/pci/drm/drm_atomic.c

1341

if (!bridge->funcs->atomic_duplicate_state)

sys/dev/pci/drm/drm_atomic.c

1520

if (config->funcs->atomic_check) {

sys/dev/pci/drm/drm_atomic.c

1521

ret = config->funcs->atomic_check(state->dev, state);

sys/dev/pci/drm/drm_atomic.c

1596

return config->funcs->atomic_commit(state->dev, state, false);

sys/dev/pci/drm/drm_atomic.c

1625

return config->funcs->atomic_commit(state->dev, state, true);

sys/dev/pci/drm/drm_atomic.c

170

if (!config->funcs->atomic_state_alloc) {

sys/dev/pci/drm/drm_atomic.c

1802

if (obj->funcs->atomic_print_state)

sys/dev/pci/drm/drm_atomic.c

1803

obj->funcs->atomic_print_state(p, state);

sys/dev/pci/drm/drm_atomic.c

183

return config->funcs->atomic_state_alloc(dev);

sys/dev/pci/drm/drm_atomic.c

209

connector->funcs->atomic_destroy_state(connector,

sys/dev/pci/drm/drm_atomic.c

224

crtc->funcs->atomic_destroy_state(crtc,

sys/dev/pci/drm/drm_atomic.c

244

plane->funcs->atomic_destroy_state(plane,

sys/dev/pci/drm/drm_atomic.c

255

obj->funcs->atomic_destroy_state(obj,

sys/dev/pci/drm/drm_atomic.c

290

if (config->funcs->atomic_state_clear)

sys/dev/pci/drm/drm_atomic.c

291

config->funcs->atomic_state_clear(state);

sys/dev/pci/drm/drm_atomic.c

314

if (config->funcs->atomic_state_free) {

sys/dev/pci/drm/drm_atomic.c

315

config->funcs->atomic_state_free(state);

sys/dev/pci/drm/drm_atomic.c

360

crtc_state = crtc->funcs->atomic_duplicate_state(crtc);

sys/dev/pci/drm/drm_atomic.c

457

if (crtc->funcs->atomic_print_state)

sys/dev/pci/drm/drm_atomic.c

458

crtc->funcs->atomic_print_state(p, state);

sys/dev/pci/drm/drm_atomic.c

545

plane_state = plane->funcs->atomic_duplicate_state(plane);

sys/dev/pci/drm/drm_atomic.c

732

if (plane->funcs->atomic_print_state)

sys/dev/pci/drm/drm_atomic.c

733

plane->funcs->atomic_print_state(p, state);

sys/dev/pci/drm/drm_atomic.c

789

const struct drm_private_state_funcs *funcs)

sys/dev/pci/drm/drm_atomic.c

796

obj->funcs = funcs;

sys/dev/pci/drm/drm_atomic.c

813

obj->funcs->atomic_destroy_state(obj, obj->state);

sys/dev/pci/drm/drm_atomic.c

866

obj_state = obj->funcs->atomic_duplicate_state(obj);

sys/dev/pci/drm/drm_atomic_helper.c

1034

const struct drm_plane_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1038

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1044

if (!funcs || !funcs->atomic_check)

sys/dev/pci/drm/drm_atomic_helper.c

1047

ret = funcs->atomic_check(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

1057

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1059

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1061

if (!funcs || !funcs->atomic_check)

sys/dev/pci/drm/drm_atomic_helper.c

1064

ret = funcs->atomic_check(crtc, state);

sys/dev/pci/drm/drm_atomic_helper.c

1190

const struct drm_encoder_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

122

const struct drm_connector_helper_funcs *funcs = connector->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1222

funcs = encoder->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1236

if (funcs) {

sys/dev/pci/drm/drm_atomic_helper.c

1237

if (funcs->atomic_disable)

sys/dev/pci/drm/drm_atomic_helper.c

1238

funcs->atomic_disable(encoder, state);

sys/dev/pci/drm/drm_atomic_helper.c

1239

else if (new_conn_state->crtc && funcs->prepare)

sys/dev/pci/drm/drm_atomic_helper.c

1240

funcs->prepare(encoder);

sys/dev/pci/drm/drm_atomic_helper.c

1241

else if (funcs->disable)

sys/dev/pci/drm/drm_atomic_helper.c

1242

funcs->disable(encoder);

sys/dev/pci/drm/drm_atomic_helper.c

1243

else if (funcs->dpms)

sys/dev/pci/drm/drm_atomic_helper.c

1244

funcs->dpms(encoder, DRM_MODE_DPMS_OFF);

sys/dev/pci/drm/drm_atomic_helper.c

1266

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1276

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

128

if (funcs->atomic_best_encoder)

sys/dev/pci/drm/drm_atomic_helper.c

1283

if (new_crtc_state->enable && funcs->prepare)

sys/dev/pci/drm/drm_atomic_helper.c

1284

funcs->prepare(crtc);

sys/dev/pci/drm/drm_atomic_helper.c

1285

else if (funcs->atomic_disable)

sys/dev/pci/drm/drm_atomic_helper.c

1286

funcs->atomic_disable(crtc, state);

sys/dev/pci/drm/drm_atomic_helper.c

1287

else if (funcs->disable)

sys/dev/pci/drm/drm_atomic_helper.c

1288

funcs->disable(crtc);

sys/dev/pci/drm/drm_atomic_helper.c

1289

else if (funcs->dpms)

sys/dev/pci/drm/drm_atomic_helper.c

129

new_encoder = funcs->atomic_best_encoder(connector,

sys/dev/pci/drm/drm_atomic_helper.c

1290

funcs->dpms(crtc, DRM_MODE_DPMS_OFF);

sys/dev/pci/drm/drm_atomic_helper.c

131

else if (funcs->best_encoder)

sys/dev/pci/drm/drm_atomic_helper.c

132

new_encoder = funcs->best_encoder(connector);

sys/dev/pci/drm/drm_atomic_helper.c

1503

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1508

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1510

if (new_crtc_state->enable && funcs->mode_set_nofb) {

sys/dev/pci/drm/drm_atomic_helper.c

1514

funcs->mode_set_nofb(crtc);

sys/dev/pci/drm/drm_atomic_helper.c

1519

const struct drm_encoder_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1528

funcs = encoder->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1543

if (funcs && funcs->atomic_mode_set) {

sys/dev/pci/drm/drm_atomic_helper.c

1544

funcs->atomic_mode_set(encoder, new_crtc_state,

sys/dev/pci/drm/drm_atomic_helper.c

1546

} else if (funcs && funcs->mode_set) {

sys/dev/pci/drm/drm_atomic_helper.c

1547

funcs->mode_set(encoder, mode, adjusted_mode);

sys/dev/pci/drm/drm_atomic_helper.c

1600

const struct drm_connector_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1602

funcs = connector->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1603

if (!funcs->atomic_commit)

sys/dev/pci/drm/drm_atomic_helper.c

1608

funcs->atomic_commit(connector, state);

sys/dev/pci/drm/drm_atomic_helper.c

1673

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1682

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1687

if (funcs->atomic_enable)

sys/dev/pci/drm/drm_atomic_helper.c

1688

funcs->atomic_enable(crtc, state);

sys/dev/pci/drm/drm_atomic_helper.c

1689

else if (funcs->commit)

sys/dev/pci/drm/drm_atomic_helper.c

1690

funcs->commit(crtc);

sys/dev/pci/drm/drm_atomic_helper.c

1712

const struct drm_encoder_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

1724

funcs = encoder->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1735

if (funcs) {

sys/dev/pci/drm/drm_atomic_helper.c

1736

if (funcs->atomic_enable)

sys/dev/pci/drm/drm_atomic_helper.c

1737

funcs->atomic_enable(encoder, state);

sys/dev/pci/drm/drm_atomic_helper.c

1738

else if (funcs->enable)

sys/dev/pci/drm/drm_atomic_helper.c

1739

funcs->enable(encoder);

sys/dev/pci/drm/drm_atomic_helper.c

1740

else if (funcs->commit)

sys/dev/pci/drm/drm_atomic_helper.c

1741

funcs->commit(encoder);

sys/dev/pci/drm/drm_atomic_helper.c

2040

const struct drm_mode_config_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2047

funcs = dev->mode_config.helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2074

if (funcs && funcs->atomic_commit_tail)

sys/dev/pci/drm/drm_atomic_helper.c

2075

funcs->atomic_commit_tail(state);

sys/dev/pci/drm/drm_atomic_helper.c

2119

const struct drm_plane_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2145

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2146

if (!funcs->atomic_async_update) {

sys/dev/pci/drm/drm_atomic_helper.c

2173

ret = funcs->atomic_async_check(plane, state, false);

sys/dev/pci/drm/drm_atomic_helper.c

2200

const struct drm_plane_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2207

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2208

funcs->atomic_async_update(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

2524

const struct drm_mode_config_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2527

funcs = state->dev->mode_config.helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2621

if (funcs && funcs->atomic_commit_setup)

sys/dev/pci/drm/drm_atomic_helper.c

2622

return funcs->atomic_commit_setup(state);

sys/dev/pci/drm/drm_atomic_helper.c

2837

const struct drm_plane_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2839

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2841

if (funcs->prepare_fb) {

sys/dev/pci/drm/drm_atomic_helper.c

2842

ret = funcs->prepare_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2846

WARN_ON_ONCE(funcs->cleanup_fb);

sys/dev/pci/drm/drm_atomic_helper.c

2858

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2860

if (funcs->begin_fb_access) {

sys/dev/pci/drm/drm_atomic_helper.c

2861

ret = funcs->begin_fb_access(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2871

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2876

if (funcs->end_fb_access)

sys/dev/pci/drm/drm_atomic_helper.c

2877

funcs->end_fb_access(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2882

const struct drm_plane_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2887

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2889

if (funcs->cleanup_fb)

sys/dev/pci/drm/drm_atomic_helper.c

2890

funcs->cleanup_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2915

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2917

if (funcs->end_fb_access)

sys/dev/pci/drm/drm_atomic_helper.c

2918

funcs->end_fb_access(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2922

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2924

if (funcs->cleanup_fb)

sys/dev/pci/drm/drm_atomic_helper.c

2925

funcs->cleanup_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

298

const struct drm_connector_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2989

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

2991

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2993

if (!funcs || !funcs->atomic_begin)

sys/dev/pci/drm/drm_atomic_helper.c

2999

funcs->atomic_begin(crtc, state);

sys/dev/pci/drm/drm_atomic_helper.c

3003

const struct drm_plane_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

3006

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3008

if (!funcs)

sys/dev/pci/drm/drm_atomic_helper.c

3031

if (disabling && funcs->atomic_disable) {

sys/dev/pci/drm/drm_atomic_helper.c

3040

funcs->atomic_disable(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

3042

funcs->atomic_update(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

3044

if (!disabling && funcs->atomic_enable) {

sys/dev/pci/drm/drm_atomic_helper.c

3046

funcs->atomic_enable(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

3052

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

3054

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3056

if (!funcs || !funcs->atomic_flush)

sys/dev/pci/drm/drm_atomic_helper.c

3062

funcs->atomic_flush(crtc, state);

sys/dev/pci/drm/drm_atomic_helper.c

3070

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3072

if (funcs->end_fb_access)

sys/dev/pci/drm/drm_atomic_helper.c

3073

funcs->end_fb_access(plane, old_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

3214

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3216

if (funcs->cleanup_fb)

sys/dev/pci/drm/drm_atomic_helper.c

3217

funcs->cleanup_fb(plane, old_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

358

funcs = connector->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

360

if (funcs->atomic_best_encoder)

sys/dev/pci/drm/drm_atomic_helper.c

361

new_encoder = funcs->atomic_best_encoder(connector, state);

sys/dev/pci/drm/drm_atomic_helper.c

362

else if (funcs->best_encoder)

sys/dev/pci/drm/drm_atomic_helper.c

363

new_encoder = funcs->best_encoder(connector);

sys/dev/pci/drm/drm_atomic_helper.c

436

const struct drm_encoder_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

453

funcs = encoder->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

465

if (funcs && funcs->atomic_check) {

sys/dev/pci/drm/drm_atomic_helper.c

466

ret = funcs->atomic_check(encoder, new_crtc_state,

sys/dev/pci/drm/drm_atomic_helper.c

474

} else if (funcs && funcs->mode_fixup) {

sys/dev/pci/drm/drm_atomic_helper.c

475

ret = funcs->mode_fixup(encoder, &new_crtc_state->mode,

sys/dev/pci/drm/drm_atomic_helper.c

487

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_atomic_helper.c

496

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

497

if (!funcs || !funcs->mode_fixup)

sys/dev/pci/drm/drm_atomic_helper.c

500

ret = funcs->mode_fixup(crtc, &new_crtc_state->mode,

sys/dev/pci/drm/drm_atomic_helper.c

714

const struct drm_connector_helper_funcs *funcs = connector->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

741

if (funcs->atomic_check)

sys/dev/pci/drm/drm_atomic_helper.c

742

ret = funcs->atomic_check(connector, state);

sys/dev/pci/drm/drm_atomic_helper.c

787

const struct drm_connector_helper_funcs *funcs = connector->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

792

if (funcs->atomic_check)

sys/dev/pci/drm/drm_atomic_helper.c

793

ret = funcs->atomic_check(connector, state);

sys/dev/pci/drm/drm_atomic_state_helper.c

120

crtc->funcs->atomic_destroy_state(crtc, crtc->state);

sys/dev/pci/drm/drm_atomic_uapi.c

423

} else if (crtc->funcs->atomic_set_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

424

return crtc->funcs->atomic_set_property(crtc, state, property, val);

sys/dev/pci/drm/drm_atomic_uapi.c

460

else if (crtc->funcs->atomic_get_property)

sys/dev/pci/drm/drm_atomic_uapi.c

461

return crtc->funcs->atomic_get_property(crtc, state, property, val);

sys/dev/pci/drm/drm_atomic_uapi.c

554

} else if (plane->funcs->atomic_set_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

555

return plane->funcs->atomic_set_property(plane, state,

sys/dev/pci/drm/drm_atomic_uapi.c

631

} else if (plane->funcs->atomic_get_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

632

return plane->funcs->atomic_get_property(plane, state, property, val);

sys/dev/pci/drm/drm_atomic_uapi.c

784

} else if (connector->funcs->atomic_set_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

785

return connector->funcs->atomic_set_property(connector,

sys/dev/pci/drm/drm_atomic_uapi.c

869

} else if (connector->funcs->atomic_get_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

870

return connector->funcs->atomic_get_property(connector,

sys/dev/pci/drm/drm_bridge.c

1003

in_bus_fmts = cur_bridge->funcs->atomic_get_input_bus_fmts(cur_bridge,

sys/dev/pci/drm/drm_bridge.c

1091

if (last_bridge->funcs->atomic_get_output_bus_fmts) {

sys/dev/pci/drm/drm_bridge.c

1092

const struct drm_bridge_funcs *funcs = last_bridge->funcs;

sys/dev/pci/drm/drm_bridge.c

1101

out_bus_fmts = funcs->atomic_get_output_bus_fmts(last_bridge,

sys/dev/pci/drm/drm_bridge.c

1264

return bridge->funcs->detect(bridge, connector);

sys/dev/pci/drm/drm_bridge.c

1288

return bridge->funcs->get_modes(bridge, connector);

sys/dev/pci/drm/drm_bridge.c

1310

return bridge->funcs->edid_read(bridge, connector);

sys/dev/pci/drm/drm_bridge.c

1348

if (bridge->funcs->hpd_enable)

sys/dev/pci/drm/drm_bridge.c

1349

bridge->funcs->hpd_enable(bridge);

sys/dev/pci/drm/drm_bridge.c

1374

if (bridge->funcs->hpd_disable)

sys/dev/pci/drm/drm_bridge.c

1375

bridge->funcs->hpd_disable(bridge);

sys/dev/pci/drm/drm_bridge.c

1459

drm_printf(p, "bridge[%u]: %ps\n", idx, bridge->funcs);

sys/dev/pci/drm/drm_bridge.c

207

if (bridge->funcs->destroy)

sys/dev/pci/drm/drm_bridge.c

208

bridge->funcs->destroy(bridge);

sys/dev/pci/drm/drm_bridge.c

262

const struct drm_bridge_funcs *funcs)

sys/dev/pci/drm/drm_bridge.c

271

if (!funcs) {

sys/dev/pci/drm/drm_bridge.c

282

bridge->funcs = funcs;

sys/dev/pci/drm/drm_bridge.c

374

state = bridge->funcs->atomic_duplicate_state(bridge);

sys/dev/pci/drm/drm_bridge.c

385

bridge->funcs->atomic_destroy_state(bridge, state);

sys/dev/pci/drm/drm_bridge.c

395

return bridge->funcs->atomic_reset != NULL;

sys/dev/pci/drm/drm_bridge.c

450

if (bridge->funcs->attach) {

sys/dev/pci/drm/drm_bridge.c

451

ret = bridge->funcs->attach(bridge, encoder, flags);

sys/dev/pci/drm/drm_bridge.c

459

state = bridge->funcs->atomic_reset(bridge);

sys/dev/pci/drm/drm_bridge.c

473

if (bridge->funcs->detach)

sys/dev/pci/drm/drm_bridge.c

474

bridge->funcs->detach(bridge);

sys/dev/pci/drm/drm_bridge.c

506

if (bridge->funcs->detach)

sys/dev/pci/drm/drm_bridge.c

507

bridge->funcs->detach(bridge);

sys/dev/pci/drm/drm_bridge.c

633

if (!bridge->funcs->mode_valid)

sys/dev/pci/drm/drm_bridge.c

636

ret = bridge->funcs->mode_valid(bridge, info, mode);

sys/dev/pci/drm/drm_bridge.c

668

if (bridge->funcs->mode_set)

sys/dev/pci/drm/drm_bridge.c

669

bridge->funcs->mode_set(bridge, mode, adjusted_mode);

sys/dev/pci/drm/drm_bridge.c

697

if (iter->funcs->atomic_disable) {

sys/dev/pci/drm/drm_bridge.c

698

iter->funcs->atomic_disable(iter, state);

sys/dev/pci/drm/drm_bridge.c

699

} else if (iter->funcs->disable) {

sys/dev/pci/drm/drm_bridge.c

700

iter->funcs->disable(iter);

sys/dev/pci/drm/drm_bridge.c

712

if (state && bridge->funcs->atomic_post_disable)

sys/dev/pci/drm/drm_bridge.c

713

bridge->funcs->atomic_post_disable(bridge, state);

sys/dev/pci/drm/drm_bridge.c

714

else if (bridge->funcs->post_disable)

sys/dev/pci/drm/drm_bridge.c

715

bridge->funcs->post_disable(bridge);

sys/dev/pci/drm/drm_bridge.c

807

if (state && bridge->funcs->atomic_pre_enable)

sys/dev/pci/drm/drm_bridge.c

808

bridge->funcs->atomic_pre_enable(bridge, state);

sys/dev/pci/drm/drm_bridge.c

809

else if (bridge->funcs->pre_enable)

sys/dev/pci/drm/drm_bridge.c

810

bridge->funcs->pre_enable(bridge);

sys/dev/pci/drm/drm_bridge.c

914

if (bridge->funcs->atomic_enable) {

sys/dev/pci/drm/drm_bridge.c

915

bridge->funcs->atomic_enable(bridge, state);

sys/dev/pci/drm/drm_bridge.c

916

} else if (bridge->funcs->enable) {

sys/dev/pci/drm/drm_bridge.c

917

bridge->funcs->enable(bridge);

sys/dev/pci/drm/drm_bridge.c

927

if (bridge->funcs->atomic_check) {

sys/dev/pci/drm/drm_bridge.c

936

ret = bridge->funcs->atomic_check(bridge, bridge_state,

sys/dev/pci/drm/drm_bridge.c

940

} else if (bridge->funcs->mode_fixup) {

sys/dev/pci/drm/drm_bridge.c

941

if (!bridge->funcs->mode_fixup(bridge, &crtc_state->mode,

sys/dev/pci/drm/drm_bridge.c

974

if (!cur_bridge->funcs->atomic_get_input_bus_fmts) {

sys/dev/pci/drm/drm_client.c

130

if (client->funcs && client->funcs->hotplug) {

sys/dev/pci/drm/drm_client.c

141

ret = client->funcs->hotplug(client);

sys/dev/pci/drm/drm_client.c

452

if (!buffer || !buffer->fb || !buffer->fb->funcs->dirty)

sys/dev/pci/drm/drm_client.c

463

return buffer->fb->funcs->dirty(buffer->fb, buffer->client->file,

sys/dev/pci/drm/drm_client.c

467

return buffer->fb->funcs->dirty(buffer->fb, buffer->client->file,

sys/dev/pci/drm/drm_client.c

79

const char *name, const struct drm_client_funcs *funcs)

sys/dev/pci/drm/drm_client.c

88

client->funcs = funcs;

sys/dev/pci/drm/drm_client_event.c

114

if (!client->funcs || !client->funcs->restore)

sys/dev/pci/drm/drm_client_event.c

117

ret = client->funcs->restore(client);

sys/dev/pci/drm/drm_client_event.c

133

if (client->funcs && client->funcs->suspend)

sys/dev/pci/drm/drm_client_event.c

134

ret = client->funcs->suspend(client, holds_console_lock);

sys/dev/pci/drm/drm_client_event.c

163

if (client->funcs && client->funcs->resume)

sys/dev/pci/drm/drm_client_event.c

164

ret = client->funcs->resume(client, holds_console_lock);

sys/dev/pci/drm/drm_client_event.c

42

if (client->funcs && client->funcs->unregister) {

sys/dev/pci/drm/drm_client_event.c

43

client->funcs->unregister(client);

sys/dev/pci/drm/drm_client_event.c

58

if (!client->funcs || !client->funcs->hotplug)

sys/dev/pci/drm/drm_client_event.c

70

ret = client->funcs->hotplug(client);

sys/dev/pci/drm/drm_client_modeset.c

1155

if (crtc->funcs->cursor_set2) {

sys/dev/pci/drm/drm_client_modeset.c

1156

ret = crtc->funcs->cursor_set2(crtc, NULL, 0, 0, 0, 0, 0);

sys/dev/pci/drm/drm_client_modeset.c

1159

} else if (crtc->funcs->cursor_set) {

sys/dev/pci/drm/drm_client_modeset.c

1160

ret = crtc->funcs->cursor_set(crtc, NULL, 0, 0, 0);

sys/dev/pci/drm/drm_client_modeset.c

1268

connector->funcs->dpms(connector, dpms_mode);

sys/dev/pci/drm/drm_client_modeset.c

879

total_modes_count += connectors[i]->funcs->fill_modes(connectors[i], width, height);

sys/dev/pci/drm/drm_color_mgmt.c

252

if (crtc->funcs->gamma_set)

sys/dev/pci/drm/drm_color_mgmt.c

293

if (crtc->funcs->gamma_set)

sys/dev/pci/drm/drm_color_mgmt.c

294

return crtc->funcs->gamma_set(crtc, red, green, blue, size, ctx);

sys/dev/pci/drm/drm_connector.c

202

connector->funcs->destroy(connector);

sys/dev/pci/drm/drm_connector.c

220

connector->funcs->destroy(connector);

sys/dev/pci/drm/drm_connector.c

226

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

236

(!funcs->atomic_destroy_state ||

sys/dev/pci/drm/drm_connector.c

237

!funcs->atomic_duplicate_state));

sys/dev/pci/drm/drm_connector.c

247

connector->funcs = funcs;

sys/dev/pci/drm/drm_connector.c

3088

if (panel && panel->funcs && panel->funcs->get_orientation)

sys/dev/pci/drm/drm_connector.c

3089

orientation = panel->funcs->get_orientation(panel);

sys/dev/pci/drm/drm_connector.c

3254

ret = (*connector->funcs->dpms)(connector, (int)value);

sys/dev/pci/drm/drm_connector.c

3262

} else if (connector->funcs->set_property)

sys/dev/pci/drm/drm_connector.c

3263

ret = connector->funcs->set_property(connector, property, value);

sys/dev/pci/drm/drm_connector.c

3379

connector->funcs->fill_modes(connector,

sys/dev/pci/drm/drm_connector.c

3528

if (connector->funcs->oob_hotplug_event)

sys/dev/pci/drm/drm_connector.c

3529

connector->funcs->oob_hotplug_event(connector, status);

sys/dev/pci/drm/drm_connector.c

367

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

373

ret = drm_connector_init_only(dev, connector, funcs, connector_type, ddc);

sys/dev/pci/drm/drm_connector.c

405

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

408

if (drm_WARN_ON(dev, !(funcs && funcs->destroy)))

sys/dev/pci/drm/drm_connector.c

411

return drm_connector_init_and_add(dev, connector, funcs, connector_type, NULL);

sys/dev/pci/drm/drm_connector.c

445

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

449

if (drm_WARN_ON(dev, !(funcs && funcs->destroy)))

sys/dev/pci/drm/drm_connector.c

452

return drm_connector_init_only(dev, connector, funcs, connector_type, ddc);

sys/dev/pci/drm/drm_connector.c

482

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

486

if (drm_WARN_ON(dev, !(funcs && funcs->destroy)))

sys/dev/pci/drm/drm_connector.c

489

return drm_connector_init_and_add(dev, connector, funcs, connector_type, ddc);

sys/dev/pci/drm/drm_connector.c

524

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

530

if (drm_WARN_ON(dev, funcs && funcs->destroy))

sys/dev/pci/drm/drm_connector.c

533

ret = drm_connector_init_and_add(dev, connector, funcs, connector_type, ddc);

sys/dev/pci/drm/drm_connector.c

575

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/drm_connector.c

604

ret = drmm_connector_init(dev, connector, funcs, connector_type, ddc);

sys/dev/pci/drm/drm_connector.c

625

if (connector->funcs->reset)

sys/dev/pci/drm/drm_connector.c

626

connector->funcs->reset(connector);

sys/dev/pci/drm/drm_connector.c

634

connector->hdmi.funcs = hdmi_funcs;

sys/dev/pci/drm/drm_connector.c

726

if (connector->cec.funcs &&

sys/dev/pci/drm/drm_connector.c

727

connector->cec.funcs->phys_addr_invalidate)

sys/dev/pci/drm/drm_connector.c

728

connector->cec.funcs->phys_addr_invalidate(connector);

sys/dev/pci/drm/drm_connector.c

748

if (connector->cec.funcs &&

sys/dev/pci/drm/drm_connector.c

749

connector->cec.funcs->phys_addr_set)

sys/dev/pci/drm/drm_connector.c

750

connector->cec.funcs->phys_addr_set(connector, addr);

sys/dev/pci/drm/drm_connector.c

809

WARN_ON(connector->state && !connector->funcs->atomic_destroy_state);

sys/dev/pci/drm/drm_connector.c

810

if (connector->state && connector->funcs->atomic_destroy_state)

sys/dev/pci/drm/drm_connector.c

811

connector->funcs->atomic_destroy_state(connector,

sys/dev/pci/drm/drm_connector.c

860

if (connector->funcs->late_register) {

sys/dev/pci/drm/drm_connector.c

861

ret = connector->funcs->late_register(connector);

sys/dev/pci/drm/drm_connector.c

887

if (connector->funcs->early_unregister)

sys/dev/pci/drm/drm_connector.c

888

connector->funcs->early_unregister(connector);

sys/dev/pci/drm/drm_connector.c

915

if (WARN_ON(!(connector->funcs && connector->funcs->destroy)))

sys/dev/pci/drm/drm_connector.c

956

if (connector->funcs->early_unregister)

sys/dev/pci/drm/drm_connector.c

957

connector->funcs->early_unregister(connector);

sys/dev/pci/drm/drm_crtc.c

118

if (crtc->funcs->late_register)

sys/dev/pci/drm/drm_crtc.c

119

ret = crtc->funcs->late_register(crtc);

sys/dev/pci/drm/drm_crtc.c

132

if (crtc->funcs->early_unregister)

sys/dev/pci/drm/drm_crtc.c

133

crtc->funcs->early_unregister(crtc);

sys/dev/pci/drm/drm_crtc.c

238

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/drm_crtc.c

252

(!funcs->atomic_destroy_state ||

sys/dev/pci/drm/drm_crtc.c

253

!funcs->atomic_duplicate_state));

sys/dev/pci/drm/drm_crtc.c

256

crtc->funcs = funcs;

sys/dev/pci/drm/drm_crtc.c

344

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/drm_crtc.c

350

WARN_ON(!funcs->destroy);

sys/dev/pci/drm/drm_crtc.c

353

ret = __drm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs,

sys/dev/pci/drm/drm_crtc.c

374

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/drm_crtc.c

380

drm_WARN_ON(dev, funcs && funcs->destroy);

sys/dev/pci/drm/drm_crtc.c

382

ret = __drm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs,

sys/dev/pci/drm/drm_crtc.c

426

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/drm_crtc.c

433

ret = __drmm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs,

sys/dev/pci/drm/drm_crtc.c

447

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/drm_crtc.c

455

if (WARN_ON(!funcs || funcs->destroy))

sys/dev/pci/drm/drm_crtc.c

465

ret = __drmm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs,

sys/dev/pci/drm/drm_crtc.c

503

WARN_ON(crtc->state && !crtc->funcs->atomic_destroy_state);

sys/dev/pci/drm/drm_crtc.c

504

if (crtc->state && crtc->funcs->atomic_destroy_state)

sys/dev/pci/drm/drm_crtc.c

505

crtc->funcs->atomic_destroy_state(crtc, crtc->state);

sys/dev/pci/drm/drm_crtc.c

608

ret = crtc->funcs->set_config(set, ctx);

sys/dev/pci/drm/drm_crtc.c

869

ret = crtc->funcs->set_config(&set, &ctx);

sys/dev/pci/drm/drm_crtc.c

904

if (crtc->funcs->set_property)

sys/dev/pci/drm/drm_crtc.c

905

ret = crtc->funcs->set_property(crtc, property, value);

sys/dev/pci/drm/drm_crtc_helper.c

785

set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);

sys/dev/pci/drm/drm_debugfs.c

813

if (connector->funcs->debugfs_init)

sys/dev/pci/drm/drm_debugfs.c

814

connector->funcs->debugfs_init(connector, root);

sys/dev/pci/drm/drm_debugfs.c

868

if (encoder->funcs && encoder->funcs->debugfs_init)

sys/dev/pci/drm/drm_debugfs.c

869

encoder->funcs->debugfs_init(encoder, root);

sys/dev/pci/drm/drm_debugfs_crc.c

147

ret = crtc->funcs->verify_crc_source(crtc, source, &values_cnt);

sys/dev/pci/drm/drm_debugfs_crc.c

217

ret = crtc->funcs->verify_crc_source(crtc, crc->source, &values_cnt);

sys/dev/pci/drm/drm_debugfs_crc.c

246

ret = crtc->funcs->set_crc_source(crtc, crc->source);

sys/dev/pci/drm/drm_debugfs_crc.c

269

crtc->funcs->set_crc_source(crtc, NULL);

sys/dev/pci/drm/drm_debugfs_crc.c

373

if (!crtc->funcs->set_crc_source || !crtc->funcs->verify_crc_source)

sys/dev/pci/drm/drm_debugfs_crc.c

88

if (crtc->funcs->get_crc_sources) {

sys/dev/pci/drm/drm_debugfs_crc.c

90

const char *const *sources = crtc->funcs->get_crc_sources(crtc,

sys/dev/pci/drm/drm_debugfs_crc.c

99

if (!crtc->funcs->verify_crc_source(crtc, sources[i],

sys/dev/pci/drm/drm_encoder.c

103

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/drm_encoder.c

118

encoder->funcs = funcs;

sys/dev/pci/drm/drm_encoder.c

165

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/drm_encoder.c

171

WARN_ON(!funcs->destroy);

sys/dev/pci/drm/drm_encoder.c

174

ret = __drm_encoder_init(dev, encoder, funcs, encoder_type, name, ap);

sys/dev/pci/drm/drm_encoder.c

223

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/drm_encoder.c

230

if (drm_WARN_ON(dev, funcs && funcs->destroy))

sys/dev/pci/drm/drm_encoder.c

233

ret = __drm_encoder_init(dev, encoder, funcs, encoder_type, name, args);

sys/dev/pci/drm/drm_encoder.c

245

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/drm_encoder.c

260

ret = __drmm_encoder_init(dev, encoder, funcs, encoder_type, name, ap);

sys/dev/pci/drm/drm_encoder.c

288

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/drm_encoder.c

295

ret = __drmm_encoder_init(dev, encoder, funcs, encoder_type, name, ap);

sys/dev/pci/drm/drm_encoder.c

80

if (encoder->funcs && encoder->funcs->late_register)

sys/dev/pci/drm/drm_encoder.c

81

ret = encoder->funcs->late_register(encoder);

sys/dev/pci/drm/drm_encoder.c

94

if (encoder->funcs && encoder->funcs->early_unregister)

sys/dev/pci/drm/drm_encoder.c

95

encoder->funcs->early_unregister(encoder);

sys/dev/pci/drm/drm_fb_helper.c

123

if (crtc->funcs->gamma_set == NULL)

sys/dev/pci/drm/drm_fb_helper.c

130

crtc->funcs->gamma_set(crtc, r_base, g_base, b_base,

sys/dev/pci/drm/drm_fb_helper.c

141

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_fb_helper.c

150

funcs = mode_set->crtc->helper_private;

sys/dev/pci/drm/drm_fb_helper.c

151

if (funcs->mode_set_base_atomic == NULL)

sys/dev/pci/drm/drm_fb_helper.c

157

funcs->mode_set_base_atomic(mode_set->crtc,

sys/dev/pci/drm/drm_fb_helper.c

182

const struct drm_crtc_helper_funcs *funcs;

sys/dev/pci/drm/drm_fb_helper.c

192

funcs = crtc->helper_private;

sys/dev/pci/drm/drm_fb_helper.c

203

if (funcs->mode_set_base_atomic == NULL)

sys/dev/pci/drm/drm_fb_helper.c

207

funcs->mode_set_base_atomic(mode_set->crtc, fb, crtc->x,

sys/dev/pci/drm/drm_fb_helper.c

253

if (fb_helper->funcs->fb_restore)

sys/dev/pci/drm/drm_fb_helper.c

254

fb_helper->funcs->fb_restore(fb_helper);

sys/dev/pci/drm/drm_fb_helper.c

377

if (drm_WARN_ON_ONCE(dev, !helper->funcs->fb_dirty))

sys/dev/pci/drm/drm_fb_helper.c

386

ret = helper->funcs->fb_dirty(helper, &clip_copy);

sys/dev/pci/drm/drm_fb_helper.c

424

const struct drm_fb_helper_funcs *funcs)

sys/dev/pci/drm/drm_fb_helper.c

446

helper->funcs = funcs;

sys/dev/pci/drm/drm_fb_helper.c

488

if (!fb_helper->client.funcs) {

sys/dev/pci/drm/drm_fb_helper.c

616

if (!fb_helper->client.funcs)

sys/dev/pci/drm/drm_fb_helper.c

777

if (fb_helper->funcs->fb_set_suspend)

sys/dev/pci/drm/drm_fb_helper.c

778

fb_helper->funcs->fb_set_suspend(fb_helper, suspend);

sys/dev/pci/drm/drm_fb_helper.c

877

if (!crtc->funcs->gamma_set || !crtc->gamma_size) {

sys/dev/pci/drm/drm_fb_helper.c

895

ret = crtc->funcs->gamma_set(crtc, r, g, b,

sys/dev/pci/drm/drm_fbdev_dma.c

195

if (helper->fb->funcs->dirty) {

sys/dev/pci/drm/drm_fbdev_dma.c

200

ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);

sys/dev/pci/drm/drm_fbdev_dma.c

323

fb_helper->funcs = &drm_fbdev_dma_helper_funcs;

sys/dev/pci/drm/drm_fbdev_dma.c

335

if (fb->funcs->dirty)

sys/dev/pci/drm/drm_fbdev_shmem.c

117

if (helper->fb->funcs->dirty) {

sys/dev/pci/drm/drm_fbdev_shmem.c

118

ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);

sys/dev/pci/drm/drm_fbdev_shmem.c

168

fb_helper->funcs = &drm_fbdev_shmem_helper_funcs;

sys/dev/pci/drm/drm_fbdev_ttm.c

163

if (helper->fb->funcs->dirty) {

sys/dev/pci/drm/drm_fbdev_ttm.c

164

ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);

sys/dev/pci/drm/drm_fbdev_ttm.c

203

fb_helper->funcs = &drm_fbdev_ttm_helper_funcs;

sys/dev/pci/drm/drm_file.c

964

size_t add_size = (obj->funcs && obj->funcs->rss) ?

sys/dev/pci/drm/drm_file.c

965

obj->funcs->rss(obj) : obj->size;

sys/dev/pci/drm/drm_file.c

967

if (obj->funcs && obj->funcs->status) {

sys/dev/pci/drm/drm_file.c

968

s = obj->funcs->status(obj);

sys/dev/pci/drm/drm_fourcc.c

433

if (dev->mode_config.funcs->get_format_info)

sys/dev/pci/drm/drm_fourcc.c

434

info = dev->mode_config.funcs->get_format_info(pixel_format,

sys/dev/pci/drm/drm_framebuffer.c

305

fb = dev->mode_config.funcs->fb_create(dev, file_priv, info, r);

sys/dev/pci/drm/drm_framebuffer.c

541

if (!fb->funcs->create_handle) {

sys/dev/pci/drm/drm_framebuffer.c

563

ret = fb->funcs->create_handle(fb, file_priv, &r->handle);

sys/dev/pci/drm/drm_framebuffer.c

603

(fb->format->num_planes > 1 || !fb->funcs->create_handle)) {

sys/dev/pci/drm/drm_framebuffer.c

661

ret = fb->funcs->create_handle(fb, file_priv,

sys/dev/pci/drm/drm_framebuffer.c

764

if (fb->funcs->dirty) {

sys/dev/pci/drm/drm_framebuffer.c

765

ret = fb->funcs->dirty(fb, file_priv, flags, r->color,

sys/dev/pci/drm/drm_framebuffer.c

841

fb->funcs->destroy(fb);

sys/dev/pci/drm/drm_framebuffer.c

864

const struct drm_framebuffer_funcs *funcs)

sys/dev/pci/drm/drm_framebuffer.c

885

fb->funcs = funcs;

sys/dev/pci/drm/drm_gem.c

1294

if (WARN_ON(!obj->funcs->free))

sys/dev/pci/drm/drm_gem.c

1297

obj->funcs->free(obj);

sys/dev/pci/drm/drm_gem.c

1374

vma->vm_ops = obj->funcs->vm_ops;

sys/dev/pci/drm/drm_gem.c

1376

if (obj->funcs->mmap) {

sys/dev/pci/drm/drm_gem.c

1377

ret = obj->funcs->mmap(obj, vma);

sys/dev/pci/drm/drm_gem.c

1484

vma->vm_ops = obj->funcs->vm_ops;

sys/dev/pci/drm/drm_gem.c

1487

uvm_obj_init(&obj->uobj, obj->funcs->vm_ops, 1);

sys/dev/pci/drm/drm_gem.c

1490

if (obj->funcs->mmap) {

sys/dev/pci/drm/drm_gem.c

1491

ret = obj->funcs->mmap(obj, accessprot, off, size);

sys/dev/pci/drm/drm_gem.c

1584

if (obj->funcs->print_info)

sys/dev/pci/drm/drm_gem.c

1585

obj->funcs->print_info(p, indent, obj);

sys/dev/pci/drm/drm_gem.c

1594

if (!obj->funcs->vmap)

sys/dev/pci/drm/drm_gem.c

1597

ret = obj->funcs->vmap(obj, map);

sys/dev/pci/drm/drm_gem.c

1614

if (obj->funcs->vunmap)

sys/dev/pci/drm/drm_gem.c

1615

obj->funcs->vunmap(obj, map);

sys/dev/pci/drm/drm_gem.c

1933

if (obj->funcs->evict)

sys/dev/pci/drm/drm_gem.c

1934

return obj->funcs->evict(obj);

sys/dev/pci/drm/drm_gem.c

517

if (obj->funcs->close)

sys/dev/pci/drm/drm_gem.c

518

obj->funcs->close(obj, file_priv);

sys/dev/pci/drm/drm_gem.c

657

if (obj->funcs->open) {

sys/dev/pci/drm/drm_gem.c

658

ret = obj->funcs->open(obj, file_priv);

sys/dev/pci/drm/drm_gem_dma_helper.c

54

obj->base.funcs = &drm_gem_dma_default_funcs;

sys/dev/pci/drm/drm_gpuvm.c

1041

obj->funcs = &drm_gpuvm_object_funcs;

sys/dev/pci/drm/drm_ioctl.c

292

if (!crtc->funcs->page_flip_target)

sys/dev/pci/drm/drm_mode_config.c

201

if (plane->funcs->reset)

sys/dev/pci/drm/drm_mode_config.c

202

plane->funcs->reset(plane);

sys/dev/pci/drm/drm_mode_config.c

205

if (crtc->funcs->reset)

sys/dev/pci/drm/drm_mode_config.c

206

crtc->funcs->reset(crtc);

sys/dev/pci/drm/drm_mode_config.c

209

if (encoder->funcs && encoder->funcs->reset)

sys/dev/pci/drm/drm_mode_config.c

210

encoder->funcs->reset(encoder);

sys/dev/pci/drm/drm_mode_config.c

214

if (connector->funcs->reset)

sys/dev/pci/drm/drm_mode_config.c

215

connector->funcs->reset(connector);

sys/dev/pci/drm/drm_mode_config.c

523

encoder->funcs->destroy(encoder);

sys/dev/pci/drm/drm_mode_config.c

551

plane->funcs->destroy(plane);

sys/dev/pci/drm/drm_mode_config.c

555

crtc->funcs->destroy(crtc);

sys/dev/pci/drm/drm_mode_config.c

684

WARN(crtc->cursor && crtc->funcs->cursor_set,

sys/dev/pci/drm/drm_mode_config.c

687

WARN(crtc->cursor && crtc->funcs->cursor_set2,

sys/dev/pci/drm/drm_mode_config.c

690

WARN(crtc->cursor && crtc->funcs->cursor_move,

sys/dev/pci/drm/drm_modes.c

1680

if (dev->mode_config.funcs->mode_valid)

sys/dev/pci/drm/drm_modes.c

1681

return dev->mode_config.funcs->mode_valid(dev, mode);

sys/dev/pci/drm/drm_modeset_helper.c

146

const struct drm_crtc_funcs *funcs)

sys/dev/pci/drm/drm_modeset_helper.c

166

ret = drm_crtc_init_with_planes(dev, crtc, primary, NULL, funcs, NULL);

sys/dev/pci/drm/drm_panel.c

129

if (panel->funcs && panel->funcs->prepare) {

sys/dev/pci/drm/drm_panel.c

130

ret = panel->funcs->prepare(panel);

sys/dev/pci/drm/drm_panel.c

137

if (!follower->funcs->panel_prepared)

sys/dev/pci/drm/drm_panel.c

140

ret = follower->funcs->panel_prepared(follower);

sys/dev/pci/drm/drm_panel.c

143

follower->funcs->panel_prepared, ret);

sys/dev/pci/drm/drm_panel.c

185

if (!follower->funcs->panel_unpreparing)

sys/dev/pci/drm/drm_panel.c

188

ret = follower->funcs->panel_unpreparing(follower);

sys/dev/pci/drm/drm_panel.c

191

follower->funcs->panel_unpreparing, ret);

sys/dev/pci/drm/drm_panel.c

194

if (panel->funcs && panel->funcs->unprepare) {

sys/dev/pci/drm/drm_panel.c

195

ret = panel->funcs->unprepare(panel);

sys/dev/pci/drm/drm_panel.c

231

if (panel->funcs && panel->funcs->enable) {

sys/dev/pci/drm/drm_panel.c

232

ret = panel->funcs->enable(panel);

sys/dev/pci/drm/drm_panel.c

244

if (!follower->funcs->panel_enabled)

sys/dev/pci/drm/drm_panel.c

247

ret = follower->funcs->panel_enabled(follower);

sys/dev/pci/drm/drm_panel.c

250

follower->funcs->panel_enabled, ret);

sys/dev/pci/drm/drm_panel.c

291

if (!follower->funcs->panel_disabling)

sys/dev/pci/drm/drm_panel.c

294

ret = follower->funcs->panel_disabling(follower);

sys/dev/pci/drm/drm_panel.c

297

follower->funcs->panel_disabling, ret);

sys/dev/pci/drm/drm_panel.c

305

if (panel->funcs && panel->funcs->disable) {

sys/dev/pci/drm/drm_panel.c

306

ret = panel->funcs->disable(panel);

sys/dev/pci/drm/drm_panel.c

334

if (panel->funcs && panel->funcs->get_modes) {

sys/dev/pci/drm/drm_panel.c

337

num = panel->funcs->get_modes(panel, connector);

sys/dev/pci/drm/drm_panel.c

404

const struct drm_panel_funcs *funcs,

sys/dev/pci/drm/drm_panel.c

411

if (!funcs) {

sys/dev/pci/drm/drm_panel.c

422

panel->funcs = funcs;

sys/dev/pci/drm/drm_panel.c

433

drm_panel_init(panel, dev, funcs, connector_type);

sys/dev/pci/drm/drm_panel.c

60

const struct drm_panel_funcs *funcs, int connector_type)

sys/dev/pci/drm/drm_panel.c

625

if (panel->prepared && follower->funcs->panel_prepared) {

sys/dev/pci/drm/drm_panel.c

626

ret = follower->funcs->panel_prepared(follower);

sys/dev/pci/drm/drm_panel.c

629

follower->funcs->panel_prepared, ret);

sys/dev/pci/drm/drm_panel.c

631

if (panel->enabled && follower->funcs->panel_enabled) {

sys/dev/pci/drm/drm_panel.c

632

ret = follower->funcs->panel_enabled(follower);

sys/dev/pci/drm/drm_panel.c

635

follower->funcs->panel_enabled, ret);

sys/dev/pci/drm/drm_panel.c

664

if (panel->enabled && follower->funcs->panel_disabling) {

sys/dev/pci/drm/drm_panel.c

665

ret = follower->funcs->panel_disabling(follower);

sys/dev/pci/drm/drm_panel.c

668

follower->funcs->panel_disabling, ret);

sys/dev/pci/drm/drm_panel.c

670

if (panel->prepared && follower->funcs->panel_unpreparing) {

sys/dev/pci/drm/drm_panel.c

671

ret = follower->funcs->panel_unpreparing(follower);

sys/dev/pci/drm/drm_panel.c

674

follower->funcs->panel_unpreparing, ret);

sys/dev/pci/drm/drm_panel.c

69

panel->funcs = funcs;

sys/dev/pci/drm/drm_plane.c

1035

ret = plane->funcs->disable_plane(plane, ctx);

sys/dev/pci/drm/drm_plane.c

1052

ret = plane->funcs->update_plane(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1086

return plane->funcs->disable_plane(plane, ctx);

sys/dev/pci/drm/drm_plane.c

1101

return plane->funcs->update_plane(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1320

if (!crtc->funcs->cursor_set && !crtc->funcs->cursor_set2) {

sys/dev/pci/drm/drm_plane.c

1325

if (crtc->funcs->cursor_set2)

sys/dev/pci/drm/drm_plane.c

1326

ret = crtc->funcs->cursor_set2(crtc, file_priv, req->handle,

sys/dev/pci/drm/drm_plane.c

1329

ret = crtc->funcs->cursor_set(crtc, file_priv, req->handle,

sys/dev/pci/drm/drm_plane.c

1334

if (crtc->funcs->cursor_move) {

sys/dev/pci/drm/drm_plane.c

1335

ret = crtc->funcs->cursor_move(crtc, req->x, req->y);

sys/dev/pci/drm/drm_plane.c

1420

if (crtc->funcs->page_flip_target) {

sys/dev/pci/drm/drm_plane.c

1454

} else if (crtc->funcs->page_flip == NULL ||

sys/dev/pci/drm/drm_plane.c

1537

if (crtc->funcs->page_flip_target)

sys/dev/pci/drm/drm_plane.c

1538

ret = crtc->funcs->page_flip_target(crtc, fb, e,

sys/dev/pci/drm/drm_plane.c

1543

ret = crtc->funcs->page_flip(crtc, fb, e, page_flip->flags,

sys/dev/pci/drm/drm_plane.c

1574

if (ret && crtc->funcs->page_flip_target)

sys/dev/pci/drm/drm_plane.c

363

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/drm_plane.c

390

(!funcs->atomic_destroy_state ||

sys/dev/pci/drm/drm_plane.c

391

!funcs->atomic_duplicate_state));

sys/dev/pci/drm/drm_plane.c

401

plane->funcs = funcs;

sys/dev/pci/drm/drm_plane.c

485

plane->funcs->format_mod_supported);

sys/dev/pci/drm/drm_plane.c

492

if (plane->funcs->format_mod_supported_async) {

sys/dev/pci/drm/drm_plane.c

494

plane->funcs->format_mod_supported_async);

sys/dev/pci/drm/drm_plane.c

534

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/drm_plane.c

543

WARN_ON(!funcs->destroy);

sys/dev/pci/drm/drm_plane.c

546

ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs,

sys/dev/pci/drm/drm_plane.c

566

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/drm_plane.c

577

if (WARN_ON(!funcs || funcs->destroy))

sys/dev/pci/drm/drm_plane.c

587

ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs,

sys/dev/pci/drm/drm_plane.c

605

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/drm_plane.c

616

if (drm_WARN_ON(dev, !funcs))

sys/dev/pci/drm/drm_plane.c

626

ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs,

sys/dev/pci/drm/drm_plane.c

649

if (plane->funcs->late_register)

sys/dev/pci/drm/drm_plane.c

650

ret = plane->funcs->late_register(plane);

sys/dev/pci/drm/drm_plane.c

670

if (plane->funcs->early_unregister)

sys/dev/pci/drm/drm_plane.c

671

plane->funcs->early_unregister(plane);

sys/dev/pci/drm/drm_plane.c

703

WARN_ON(plane->state && !plane->funcs->atomic_destroy_state);

sys/dev/pci/drm/drm_plane.c

704

if (plane->state && plane->funcs->atomic_destroy_state)

sys/dev/pci/drm/drm_plane.c

705

plane->funcs->atomic_destroy_state(plane, plane->state);

sys/dev/pci/drm/drm_plane.c

759

ret = plane->funcs->disable_plane(plane, NULL);

sys/dev/pci/drm/drm_plane.c

793

if (plane->funcs->set_property)

sys/dev/pci/drm/drm_plane.c

794

ret = plane->funcs->set_property(plane, property, value);

sys/dev/pci/drm/drm_plane.c

928

if (plane->funcs->format_mod_supported) {

sys/dev/pci/drm/drm_plane.c

929

if (!plane->funcs->format_mod_supported(plane, format, modifier))

sys/dev/pci/drm/drm_plane_helper.c

215

return plane->funcs->disable_plane(plane, ctx);

sys/dev/pci/drm/drm_plane_helper.c

237

ret = crtc->funcs->set_config(&set, ctx);

sys/dev/pci/drm/drm_prime.c

388

if (obj->funcs && obj->funcs->export)

sys/dev/pci/drm/drm_prime.c

389

dmabuf = obj->funcs->export(obj, flags);

sys/dev/pci/drm/drm_prime.c

616

!obj->funcs->get_sg_table)

sys/dev/pci/drm/drm_prime.c

618

if (!obj->funcs->get_sg_table)

sys/dev/pci/drm/drm_prime.c

622

if (!obj->funcs->pin)

sys/dev/pci/drm/drm_prime.c

628

ret = obj->funcs->pin(obj);

sys/dev/pci/drm/drm_prime.c

650

if (!obj->funcs->unpin)

sys/dev/pci/drm/drm_prime.c

656

obj->funcs->unpin(obj);

sys/dev/pci/drm/drm_prime.c

685

if (WARN_ON(!obj->funcs->get_sg_table))

sys/dev/pci/drm/drm_prime.c

688

sgt = obj->funcs->get_sg_table(obj);

sys/dev/pci/drm/drm_prime.c

782

if (obj->funcs && obj->funcs->mmap) {

sys/dev/pci/drm/drm_prime.c

783

vma->vm_ops = obj->funcs->vm_ops;

sys/dev/pci/drm/drm_prime.c

786

ret = obj->funcs->mmap(obj, vma);

sys/dev/pci/drm/drm_probe_helper.c

234

const struct drm_connector_helper_funcs *funcs =

sys/dev/pci/drm/drm_probe_helper.c

237

if (funcs && funcs->disable_hpd)

sys/dev/pci/drm/drm_probe_helper.c

238

funcs->disable_hpd(connector);

sys/dev/pci/drm/drm_probe_helper.c

251

const struct drm_connector_helper_funcs *funcs =

sys/dev/pci/drm/drm_probe_helper.c

254

if (funcs && funcs->enable_hpd)

sys/dev/pci/drm/drm_probe_helper.c

255

funcs->enable_hpd(connector);

sys/dev/pci/drm/drm_probe_helper.c

346

const struct drm_connector_helper_funcs *funcs = connector->helper_private;

sys/dev/pci/drm/drm_probe_helper.c

348

if (funcs->detect_ctx)

sys/dev/pci/drm/drm_probe_helper.c

349

return funcs->detect_ctx(connector, ctx, force);

sys/dev/pci/drm/drm_probe_helper.c

350

else if (connector->funcs->detect)

sys/dev/pci/drm/drm_probe_helper.c

351

return connector->funcs->detect(connector, force);

sys/dev/pci/drm/drm_probe_helper.c

595

if (connector->funcs->force)

sys/dev/pci/drm/drm_probe_helper.c

596

connector->funcs->force(connector);

sys/dev/pci/drm/drm_vblank.c

1155

if (crtc->funcs->enable_vblank)

sys/dev/pci/drm/drm_vblank.c

1156

return crtc->funcs->enable_vblank(crtc);

sys/dev/pci/drm/drm_vblank.c

1615

drm_WARN_ON_ONCE(dev, !crtc->funcs->get_vblank_timestamp);

sys/dev/pci/drm/drm_vblank.c

1918

if (crtc && crtc->funcs->get_vblank_timestamp)

sys/dev/pci/drm/drm_vblank.c

223

if (crtc->funcs->get_vblank_counter)

sys/dev/pci/drm/drm_vblank.c

224

return crtc->funcs->get_vblank_counter(crtc);

sys/dev/pci/drm/drm_vblank.c

419

!crtc->funcs->get_vblank_timestamp,

sys/dev/pci/drm/drm_vblank.c

441

if (crtc->funcs->disable_vblank)

sys/dev/pci/drm/drm_vblank.c

442

crtc->funcs->disable_vblank(crtc);

sys/dev/pci/drm/drm_vblank.c

881

if (crtc && crtc->funcs->get_vblank_timestamp && max_error > 0) {

sys/dev/pci/drm/drm_vblank.c

882

ret = crtc->funcs->get_vblank_timestamp(crtc, &max_error,

sys/dev/pci/drm/i915/display/i9xx_wm.c

3591

if (!display->funcs.wm->optimize_watermarks)

sys/dev/pci/drm/i915/display/i9xx_wm.c

4159

display->funcs.wm = &ilk_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4162

display->funcs.wm = &vlv_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4165

display->funcs.wm = &g4x_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4171

display->funcs.wm = &nop_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4173

display->funcs.wm = &pnv_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4176

display->funcs.wm = &i965_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4178

display->funcs.wm = &i9xx_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4181

display->funcs.wm = &i845_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4183

display->funcs.wm = &i9xx_wm_funcs;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4187

display->funcs.wm = &nop_funcs;

sys/dev/pci/drm/i915/display/intel_audio.c

759

if (display->funcs.audio)

sys/dev/pci/drm/i915/display/intel_audio.c

760

display->funcs.audio->audio_codec_enable(encoder,

sys/dev/pci/drm/i915/display/intel_audio.c

818

if (display->funcs.audio)

sys/dev/pci/drm/i915/display/intel_audio.c

819

display->funcs.audio->audio_codec_disable(encoder,

sys/dev/pci/drm/i915/display/intel_audio.c

869

if (display->funcs.audio)

sys/dev/pci/drm/i915/display/intel_audio.c

870

display->funcs.audio->audio_codec_get_config(encoder, crtc_state);

sys/dev/pci/drm/i915/display/intel_audio.c

898

display->funcs.audio = &g4x_audio_funcs;

sys/dev/pci/drm/i915/display/intel_audio.c

901

display->funcs.audio = &ibx_audio_funcs;

sys/dev/pci/drm/i915/display/intel_audio.c

903

display->funcs.audio = &hsw_audio_funcs;

sys/dev/pci/drm/i915/display/intel_backlight.c

1709

if (drm_WARN_ON(display->drm, !panel->backlight.funcs))

sys/dev/pci/drm/i915/display/intel_backlight.c

1714

ret = panel->backlight.funcs->setup(connector, pipe);

sys/dev/pci/drm/i915/display/intel_backlight.c

1875

panel->backlight.funcs = &pwm_bl_funcs;

sys/dev/pci/drm/i915/display/intel_backlight.c

307

panel->backlight.funcs->set(conn_state, level);

sys/dev/pci/drm/i915/display/intel_backlight.c

480

panel->backlight.funcs->disable(old_conn_state, 0);

sys/dev/pci/drm/i915/display/intel_backlight.c

804

panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level);

sys/dev/pci/drm/i915/display/intel_backlight.c

840

val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector));

sys/dev/pci/drm/i915/display/intel_cdclk.c

168

display->funcs.cdclk->get_cdclk(display, cdclk_config);

sys/dev/pci/drm/i915/display/intel_cdclk.c

175

display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);

sys/dev/pci/drm/i915/display/intel_cdclk.c

182

return display->funcs.cdclk->modeset_calc_cdclk(state);

sys/dev/pci/drm/i915/display/intel_cdclk.c

188

return display->funcs.cdclk->calc_voltage_level(cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2552

if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))

sys/dev/pci/drm/i915/display/intel_cdclk.c

3787

display->funcs.cdclk = &xe3lpd_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3790

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3793

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3796

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3799

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3805

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3808

display->funcs.cdclk = &rplu_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3811

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3814

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3817

display->funcs.cdclk = &tgl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3820

display->funcs.cdclk = &ehl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3823

display->funcs.cdclk = &icl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3826

display->funcs.cdclk = &bxt_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3832

display->funcs.cdclk = &skl_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3834

display->funcs.cdclk = &bdw_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3836

display->funcs.cdclk = &hsw_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3838

display->funcs.cdclk = &chv_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3840

display->funcs.cdclk = &vlv_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3842

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3844

display->funcs.cdclk = &ilk_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3846

display->funcs.cdclk = &gm45_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3848

display->funcs.cdclk = &g33_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3850

display->funcs.cdclk = &i965gm_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3852

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3854

display->funcs.cdclk = &pnv_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3856

display->funcs.cdclk = &g33_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3858

display->funcs.cdclk = &i945gm_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3860

display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3862

display->funcs.cdclk = &i915gm_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3864

display->funcs.cdclk = &i915g_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3866

display->funcs.cdclk = &i865g_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3868

display->funcs.cdclk = &i85x_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3870

display->funcs.cdclk = &i845g_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3872

display->funcs.cdclk = &i830_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3875

if (drm_WARN(display->drm, !display->funcs.cdclk,

sys/dev/pci/drm/i915/display/intel_cdclk.c

3877

display->funcs.cdclk = &i830_cdclk_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

1923

display->funcs.color->load_luts(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1931

if (display->funcs.color->color_commit_noarm)

sys/dev/pci/drm/i915/display/intel_color.c

1932

display->funcs.color->color_commit_noarm(dsb, crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1940

display->funcs.color->color_commit_arm(dsb, crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

1947

if (display->funcs.color->color_post_update)

sys/dev/pci/drm/i915/display/intel_color.c

1948

display->funcs.color->color_post_update(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2012

display->funcs.color->load_luts(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2103

return display->funcs.color->color_check(state, crtc);

sys/dev/pci/drm/i915/display/intel_color.c

2110

display->funcs.color->get_config(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2112

display->funcs.color->read_luts(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2114

if (display->funcs.color->read_csc)

sys/dev/pci/drm/i915/display/intel_color.c

2115

display->funcs.color->read_csc(crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2132

return display->funcs.color->lut_equal(crtc_state, blob1, blob2,

sys/dev/pci/drm/i915/display/intel_color.c

4013

display->funcs.color = &chv_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4015

display->funcs.color = &vlv_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4017

display->funcs.color = &i965_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4019

display->funcs.color = &i9xx_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4022

display->funcs.color = &tgl_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4024

display->funcs.color = &icl_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4026

display->funcs.color = &glk_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4028

display->funcs.color = &skl_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4030

display->funcs.color = &bdw_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4032

display->funcs.color = &hsw_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4034

display->funcs.color = &ivb_color_funcs;

sys/dev/pci/drm/i915/display/intel_color.c

4036

display->funcs.color = &ilk_color_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

309

const struct drm_crtc_funcs *funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

357

funcs = &g4x_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

359

funcs = &i965_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

362

funcs = &i915gm_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

364

funcs = &i915_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

366

funcs = &i8xx_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

369

funcs = &bdw_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

371

funcs = &ilk_crtc_funcs;

sys/dev/pci/drm/i915/display/intel_crtc.c

376

funcs, "pipe %c", pipe_name(pipe));

sys/dev/pci/drm/i915/display/intel_crtc.c

90

return crtc->base.funcs->get_vblank_counter(&crtc->base);

sys/dev/pci/drm/i915/display/intel_display.c

2163

if (!display->funcs.wm->initial_watermarks)

sys/dev/pci/drm/i915/display/intel_display.c

4024

if (!display->funcs.display->get_pipe_config(crtc, crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

6713

display->funcs.display->crtc_enable(state, crtc);

sys/dev/pci/drm/i915/display/intel_display.c

6841

display->funcs.display->crtc_disable(state, crtc);

sys/dev/pci/drm/i915/display/intel_display.c

7447

display->funcs.display->commit_modeset_enables(state);

sys/dev/pci/drm/i915/display/intel_display.c

8145

display->funcs.display = &skl_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8147

display->funcs.display = &ddi_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8149

display->funcs.display = &pch_split_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8152

display->funcs.display = &vlv_display_funcs;

sys/dev/pci/drm/i915/display/intel_display.c

8154

display->funcs.display = &i9xx_display_funcs;

sys/dev/pci/drm/i915/display/intel_display_core.h

319

} funcs;

sys/dev/pci/drm/i915/display/intel_display_driver.c

127

mode_config->funcs = &intel_mode_funcs;

sys/dev/pci/drm/i915/display/intel_display_types.h

439

const struct intel_panel_bl_funcs *funcs;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

703

panel->backlight.funcs = &intel_dp_hdr_bl_funcs;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

710

panel->backlight.funcs = &intel_dp_vesa_bl_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1752

ret = display->funcs.dpll->crtc_compute_clock(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

1776

if (!display->funcs.dpll->crtc_get_dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

1779

ret = display->funcs.dpll->crtc_get_dpll(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

1793

display->funcs.dpll = &mtl_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1795

display->funcs.dpll = &dg2_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1797

display->funcs.dpll = &hsw_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1799

display->funcs.dpll = &ilk_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1801

display->funcs.dpll = &chv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1803

display->funcs.dpll = &vlv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1805

display->funcs.dpll = &g4x_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1807

display->funcs.dpll = &pnv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1809

display->funcs.dpll = &i9xx_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1811

display->funcs.dpll = &i8xx_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1313

{ .name = "WRPLL 1", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1314

{ .name = "WRPLL 2", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1315

{ .name = "SPLL", .funcs = &hsw_ddi_spll_funcs, .id = DPLL_ID_SPLL, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1316

{ .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1318

{ .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1320

{ .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2022

{ .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2024

{ .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2025

{ .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2026

{ .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

238

pll->info->funcs->enable(display, pll, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

245

pll->info->funcs->disable(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2505

{ .name = "PORT PLL A", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2506

{ .name = "PORT PLL B", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2507

{ .name = "PORT PLL C", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4161

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4162

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4163

{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4165

{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4166

{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4167

{ .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4168

{ .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4184

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4185

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4186

{ .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4209

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4210

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4211

{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4213

{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4214

{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4215

{ .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4216

{ .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4217

{ .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4218

{ .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4234

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4235

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4236

{ .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4251

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4252

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4253

{ .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4254

{ .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4269

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4270

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4271

{ .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4272

{ .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4287

{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4288

{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4289

{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4291

{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4292

{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4293

{ .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4294

{ .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4495

if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4498

return pll->info->funcs->get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4513

return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

680

{ .name = "PCH DPLL A", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_A, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

681

{ .name = "PCH DPLL B", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_B, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

324

const struct intel_dpll_funcs *funcs;

sys/dev/pci/drm/i915/display/intel_dsi.c

84

const struct mipi_dsi_host_ops *funcs,

sys/dev/pci/drm/i915/display/intel_dsi.c

94

host->base.ops = funcs;

sys/dev/pci/drm/i915/display/intel_dsi.h

170

const struct mipi_dsi_host_ops *funcs,

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

203

panel->backlight.funcs = &dcs_bl_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2092

fbc->funcs = &ivb_fbc_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2094

fbc->funcs = &snb_fbc_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2096

fbc->funcs = &ilk_fbc_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2098

fbc->funcs = &g4x_fbc_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2100

fbc->funcs = &i965_fbc_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2102

fbc->funcs = &i8xx_fbc_funcs;

sys/dev/pci/drm/i915/display/intel_fbc.c

2207

fbc->funcs->set_false_color(fbc, fbc->false_color);

sys/dev/pci/drm/i915/display/intel_fbc.c

2227

if (fbc->funcs->set_false_color)

sys/dev/pci/drm/i915/display/intel_fbc.c

720

return fbc->funcs->is_active(fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

730

fbc->funcs->activate(fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

739

fbc->funcs->deactivate(fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

744

return fbc->funcs->is_compressing(fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

756

fbc->funcs->nuke(fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

905

fbc->funcs->program_cfb(fbc);

sys/dev/pci/drm/i915/display/intel_fbc.c

99

const struct intel_fbc_funcs *funcs;

sys/dev/pci/drm/i915/display/intel_fbdev.c

183

if (helper->fb->funcs->dirty)

sys/dev/pci/drm/i915/display/intel_fbdev.c

184

return helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);

sys/dev/pci/drm/i915/display/intel_fbdev.c

316

helper->funcs = &intel_fb_helper_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

1112

display->funcs.fdi = &ilk_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

1114

display->funcs.fdi = &gen6_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

1117

display->funcs.fdi = &ivb_funcs;

sys/dev/pci/drm/i915/display/intel_fdi.c

126

display->funcs.fdi->fdi_link_train(crtc, crtc_state);

sys/dev/pci/drm/i915/display/intel_global_state.c

114

const struct intel_global_state_funcs *funcs)

sys/dev/pci/drm/i915/display/intel_global_state.c

123

obj->funcs = funcs;

sys/dev/pci/drm/i915/display/intel_global_state.c

209

obj_state = obj->funcs->atomic_duplicate_state(obj);

sys/dev/pci/drm/i915/display/intel_global_state.c

95

obj->funcs->atomic_destroy_state(obj, obj_state);

sys/dev/pci/drm/i915/display/intel_global_state.h

27

const struct intel_global_state_funcs *funcs;

sys/dev/pci/drm/i915/display/intel_global_state.h

41

const struct intel_global_state_funcs *funcs);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1451

if (display->funcs.hotplug)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1452

display->funcs.hotplug->hpd_enable_detection(encoder);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1461

if (display->funcs.hotplug)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1462

display->funcs.hotplug->hpd_irq_setup(display);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1473

display->funcs.hotplug = &i915_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1476

display->funcs.hotplug = &icp_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1478

display->funcs.hotplug = &dg1_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1480

display->funcs.hotplug = &xelpdp_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1482

display->funcs.hotplug = &gen11_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1484

display->funcs.hotplug = &bxt_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1486

display->funcs.hotplug = &icp_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1488

display->funcs.hotplug = &spt_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1490

display->funcs.hotplug = &ilk_hpd_funcs;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

86

display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);

sys/dev/pci/drm/i915/display/intel_plane.c

195

if (!plane->funcs->format_mod_supported(plane, format, modifier))

sys/dev/pci/drm/i915/display/intel_plane_initial.c

422

display->funcs.display->get_initial_plane_config(crtc, plane_config);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

430

if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config))

sys/dev/pci/drm/i915/display/intel_wm.c

101

if (display->funcs.wm->compute_global_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

102

return display->funcs.wm->compute_global_watermarks(state);

sys/dev/pci/drm/i915/display/intel_wm.c

109

if (display->funcs.wm->get_hw_state)

sys/dev/pci/drm/i915/display/intel_wm.c

110

return display->funcs.wm->get_hw_state(display);

sys/dev/pci/drm/i915/display/intel_wm.c

115

if (display->funcs.wm->sanitize)

sys/dev/pci/drm/i915/display/intel_wm.c

116

return display->funcs.wm->sanitize(display);

sys/dev/pci/drm/i915/display/intel_wm.c

51

if (display->funcs.wm->update_wm)

sys/dev/pci/drm/i915/display/intel_wm.c

52

display->funcs.wm->update_wm(display);

sys/dev/pci/drm/i915/display/intel_wm.c

60

if (!display->funcs.wm->compute_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

63

return display->funcs.wm->compute_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

71

if (display->funcs.wm->initial_watermarks) {

sys/dev/pci/drm/i915/display/intel_wm.c

72

display->funcs.wm->initial_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

84

if (display->funcs.wm->atomic_update_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

85

display->funcs.wm->atomic_update_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/intel_wm.c

93

if (display->funcs.wm->optimize_watermarks)

sys/dev/pci/drm/i915/display/intel_wm.c

94

display->funcs.wm->optimize_watermarks(state, crtc);

sys/dev/pci/drm/i915/display/skl_watermark.c

3965

display->funcs.wm = &skl_wm_funcs;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

88

obj->base.funcs = &i915_gem_object_funcs;

sys/dev/pci/drm/i915/intel_uncore.c

2071

(uncore)->funcs.mmio_writeb = x##_write8; \

sys/dev/pci/drm/i915/intel_uncore.c

2072

(uncore)->funcs.mmio_writew = x##_write16; \

sys/dev/pci/drm/i915/intel_uncore.c

2073

(uncore)->funcs.mmio_writel = x##_write32; \

sys/dev/pci/drm/i915/intel_uncore.c

2078

(uncore)->funcs.mmio_readb = x##_read8; \

sys/dev/pci/drm/i915/intel_uncore.c

2079

(uncore)->funcs.mmio_readw = x##_read16; \

sys/dev/pci/drm/i915/intel_uncore.c

2080

(uncore)->funcs.mmio_readl = x##_read32; \

sys/dev/pci/drm/i915/intel_uncore.c

2081

(uncore)->funcs.mmio_readq = x##_read64; \

sys/dev/pci/drm/i915/intel_uncore.c

2087

(uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \

sys/dev/pci/drm/i915/intel_uncore.c

2093

(uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \

sys/dev/pci/drm/i915/intel_uncore.c

2578

GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);

sys/dev/pci/drm/i915/intel_uncore.c

2579

GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);

sys/dev/pci/drm/i915/intel_uncore.c

2927

fw_domains = uncore->funcs.read_fw_domains(uncore, reg);

sys/dev/pci/drm/i915/intel_uncore.c

2930

fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);

sys/dev/pci/drm/i915/intel_uncore.h

170

struct intel_uncore_funcs funcs;

sys/dev/pci/drm/i915/intel_uncore.h

362

return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \

sys/dev/pci/drm/i915/intel_uncore.h

369

uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

1010

if (objs_state->ptr->funcs != &drm_dp_mst_topology_state_funcs)

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

747

const struct drm_private_state_funcs *funcs;

sys/dev/pci/drm/include/drm/display/drm_hdmi_audio_helper.h

15

const struct drm_connector_hdmi_audio_funcs *funcs,

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

43

const struct drm_connector_hdmi_cec_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_atomic.h

309

const struct drm_private_state_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_atomic.h

609

const struct drm_private_state_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_bridge.h

1016

const struct drm_bridge_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_bridge.h

1173

const struct drm_bridge_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_bridge.h

1189

#define devm_drm_bridge_alloc(dev, type, member, funcs) \

sys/dev/pci/drm/include/drm/drm_bridge.h

1191

offsetof(type, member), funcs))

sys/dev/pci/drm/include/drm/drm_bridge.h

1235

if (!bridge->funcs || !bridge->funcs->atomic_reset)

sys/dev/pci/drm/include/drm/drm_client.h

121

const struct drm_client_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_client.h

163

const char *name, const struct drm_client_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_connector.h

1773

const struct drm_connector_hdmi_audio_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_connector.h

1847

const struct drm_connector_hdmi_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_connector.h

1879

const struct drm_connector_cec_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_connector.h

2026

const struct drm_connector_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_connector.h

2321

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_connector.h

2325

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_connector.h

2330

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_connector.h

2335

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_connector.h

2341

const struct drm_connector_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_crtc.h

1059

const struct drm_crtc_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_crtc.h

1212

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_crtc.h

1220

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_crtc.h

1230

const struct drm_crtc_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_crtc.h

1252

#define drmm_crtc_alloc_with_planes(dev, type, member, primary, cursor, funcs, name, ...) \

sys/dev/pci/drm/include/drm/drm_crtc.h

1255

primary, cursor, funcs, \

sys/dev/pci/drm/include/drm/drm_drv.h

577

(dev->mode_config.funcs && dev->mode_config.funcs->atomic_commit != NULL);

sys/dev/pci/drm/include/drm/drm_encoder.h

192

const struct drm_encoder_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_encoder.h

208

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_encoder.h

214

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_encoder.h

220

const struct drm_encoder_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_encoder.h

242

#define drmm_encoder_alloc(dev, type, member, funcs, encoder_type, name, ...) \

sys/dev/pci/drm/include/drm/drm_encoder.h

244

offsetof(type, member), funcs, \

sys/dev/pci/drm/include/drm/drm_encoder.h

260

#define drmm_plain_encoder_alloc(dev, funcs, encoder_type, name, ...) \

sys/dev/pci/drm/include/drm/drm_encoder.h

263

0, funcs, encoder_type, name, ##__VA_ARGS__))

sys/dev/pci/drm/include/drm/drm_fb_helper.h

149

const struct drm_fb_helper_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_fb_helper.h

251

const struct drm_fb_helper_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_fb_helper.h

296

const struct drm_fb_helper_funcs *funcs)

sys/dev/pci/drm/include/drm/drm_framebuffer.h

148

const struct drm_framebuffer_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_framebuffer.h

215

const struct drm_framebuffer_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_gem.h

456

const struct drm_gem_object_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_gem_framebuffer_helper.h

30

const struct drm_framebuffer_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_gem_framebuffer_helper.h

35

const struct drm_framebuffer_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_mode_config.h

538

const struct drm_mode_config_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_modeset_helper.h

41

const struct drm_crtc_funcs *funcs);

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1190

const struct drm_connector_helper_funcs *funcs)

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1192

connector->helper_private = funcs;

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1498

const struct drm_plane_helper_funcs *funcs)

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1500

plane->helper_private = funcs;

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

501

const struct drm_crtc_helper_funcs *funcs)

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

503

crtc->helper_private = funcs;

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

850

const struct drm_encoder_helper_funcs *funcs)

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

852

encoder->helper_private = funcs;

sys/dev/pci/drm/include/drm/drm_panel.h

185

const struct drm_panel_follower_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_panel.h

229

const struct drm_panel_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_panel.h

298

const struct drm_panel_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_panel.h

318

#define devm_drm_panel_alloc(dev, type, member, funcs, connector_type) \

sys/dev/pci/drm/include/drm/drm_panel.h

320

offsetof(type, member), funcs, \

sys/dev/pci/drm/include/drm/drm_panel.h

324

const struct drm_panel_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_plane.h

710

const struct drm_plane_funcs *funcs;

sys/dev/pci/drm/include/drm/drm_plane.h

814

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_plane.h

826

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_plane.h

859

#define drmm_universal_plane_alloc(dev, type, member, possible_crtcs, funcs, formats, \

sys/dev/pci/drm/include/drm/drm_plane.h

863

possible_crtcs, funcs, formats, \

sys/dev/pci/drm/include/drm/drm_plane.h

871

const struct drm_plane_funcs *funcs,

sys/dev/pci/drm/include/drm/drm_plane.h

903

#define drm_universal_plane_alloc(dev, type, member, possible_crtcs, funcs, formats, \

sys/dev/pci/drm/include/drm/drm_plane.h

907

possible_crtcs, funcs, formats, \

sys/dev/pci/drm/include/drm/ttm/ttm_device.h

226

const struct ttm_device_funcs *funcs;

sys/dev/pci/drm/include/drm/ttm/ttm_device.h

300

int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *funcs,

sys/dev/pci/drm/radeon/radeon.h

1771

struct radeon_audio_basic_funcs *funcs;

sys/dev/pci/drm/radeon/radeon_audio.c

212

if (rdev->audio.funcs->enable)

sys/dev/pci/drm/radeon/radeon_audio.c

213

rdev->audio.funcs->enable(rdev, pin, enable_mask);

sys/dev/pci/drm/radeon/radeon_audio.c

221

rdev->audio.funcs = &dce6_funcs;

sys/dev/pci/drm/radeon/radeon_audio.c

225

rdev->audio.funcs = &dce4_funcs;

sys/dev/pci/drm/radeon/radeon_audio.c

229

rdev->audio.funcs = &dce32_funcs;

sys/dev/pci/drm/radeon/radeon_audio.c

233

rdev->audio.funcs = &r600_funcs;

sys/dev/pci/drm/radeon/radeon_audio.c

290

if (rdev->audio.funcs->endpoint_rreg)

sys/dev/pci/drm/radeon/radeon_audio.c

291

return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg);

sys/dev/pci/drm/radeon/radeon_audio.c

299

if (rdev->audio.funcs->endpoint_wreg)

sys/dev/pci/drm/radeon/radeon_audio.c

300

rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);

sys/dev/pci/drm/radeon/radeon_connectors.c

729

crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);

sys/dev/pci/drm/radeon/radeon_display.c

1586

rdev_to_drm(rdev)->mode_config.funcs = &radeon_mode_funcs;

sys/dev/pci/drm/radeon/radeon_display.c

461

crtc->funcs->get_vblank_counter(crtc)) > 0)))

sys/dev/pci/drm/radeon/radeon_display.c

583

crtc->funcs->get_vblank_counter(crtc);

sys/dev/pci/drm/radeon/radeon_drv.c

939

crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);

sys/dev/pci/drm/radeon/radeon_fbdev.c

254

fb_helper->funcs = &radeon_fbdev_fb_helper_funcs;

sys/dev/pci/drm/radeon/radeon_object.c

154

bo->tbo.base.funcs = &radeon_gem_object_funcs;

sys/dev/pci/drm/radeon/radeon_prime.c

62

bo->tbo.base.funcs = &radeon_gem_object_funcs;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

540

old_tt = priv->ttm_dev->funcs->ttm_tt_create(bo, 0);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

31

KUNIT_EXPECT_PTR_EQ(test, ttm_dev->funcs, &ttm_dev_funcs);

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

64

KUNIT_EXPECT_PTR_EQ(test, ttm_devs[i].funcs, &ttm_dev_funcs);

sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c

122

struct ttm_device_funcs *funcs)

sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c

127

err = ttm_device_init(ttm, funcs, drm->dev,

sys/dev/pci/drm/ttm/tests/ttm_tt_test.c

232

devs->ttm_dev->funcs = &ttm_dev_empty_funcs;

sys/dev/pci/drm/ttm/ttm_bo.c

1146

if (bo->pin_count || !bo->bdev->funcs->eviction_valuable(bo, &place)) {

sys/dev/pci/drm/ttm/ttm_bo.c

1200

if (bo->bdev->funcs->swap_notify)

sys/dev/pci/drm/ttm/ttm_bo.c

1201

bo->bdev->funcs->swap_notify(bo);

sys/dev/pci/drm/ttm/ttm_bo.c

155

ret = bdev->funcs->move(bo, evict, ctx, mem, hop);

sys/dev/pci/drm/ttm/ttm_bo.c

182

if (bo->bdev->funcs->delete_mem_notify)

sys/dev/pci/drm/ttm/ttm_bo.c

183

bo->bdev->funcs->delete_mem_notify(bo);

sys/dev/pci/drm/ttm/ttm_bo.c

269

if (bo->bdev->funcs->release_notify)

sys/dev/pci/drm/ttm/ttm_bo.c

270

bo->bdev->funcs->release_notify(bo);

sys/dev/pci/drm/ttm/ttm_bo.c

372

bdev->funcs->evict_flags(bo, &placement);

sys/dev/pci/drm/ttm/ttm_bo.c

525

if (bo->pin_count || !bo->bdev->funcs->eviction_valuable(bo, evict_walk->place))

sys/dev/pci/drm/ttm/ttm_bo_util.c

56

if (!bdev->funcs->io_mem_reserve)

sys/dev/pci/drm/ttm/ttm_bo_util.c

59

return bdev->funcs->io_mem_reserve(bdev, mem);

sys/dev/pci/drm/ttm/ttm_bo_util.c

71

if (bdev->funcs->io_mem_free)

sys/dev/pci/drm/ttm/ttm_bo_util.c

72

bdev->funcs->io_mem_free(bdev, mem);

sys/dev/pci/drm/ttm/ttm_bo_vm.c

406

if (bdev->funcs->io_mem_pfn)

sys/dev/pci/drm/ttm/ttm_bo_vm.c

407

return bdev->funcs->io_mem_pfn(bo, page_offset);

sys/dev/pci/drm/ttm/ttm_bo_vm.c

724

if (bo->bdev->funcs->access_memory)

sys/dev/pci/drm/ttm/ttm_bo_vm.c

725

ret = bo->bdev->funcs->access_memory

sys/dev/pci/drm/ttm/ttm_bo_vm.c

93

if (bdev->funcs->io_mem_pfn)

sys/dev/pci/drm/ttm/ttm_bo_vm.c

94

return bdev->funcs->io_mem_pfn(bo, page_offset);

sys/dev/pci/drm/ttm/ttm_device.c

207

int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *funcs,

sys/dev/pci/drm/ttm/ttm_device.c

229

bdev->funcs = funcs;

sys/dev/pci/drm/ttm/ttm_tt.c

101

bo->ttm = bdev->funcs->ttm_tt_create(bo, page_flags);

sys/dev/pci/drm/ttm/ttm_tt.c

156

bdev->funcs->ttm_tt_destroy(bdev, ttm);

sys/dev/pci/drm/ttm/ttm_tt.c

452

if (bdev->funcs->ttm_tt_populate)

sys/dev/pci/drm/ttm/ttm_tt.c

453

ret = bdev->funcs->ttm_tt_populate(bdev, ttm, ctx);

sys/dev/pci/drm/ttm/ttm_tt.c

490

if (bdev->funcs->ttm_tt_unpopulate)

sys/dev/pci/drm/ttm/ttm_tt.c

491

bdev->funcs->ttm_tt_unpopulate(bdev, ttm);

sys/dev/pci/if_ice.c

4525

uint16_t funcs;

sys/dev/pci/if_ice.c

4528

funcs = ice_popcount16(hw->dev_caps.common_cap.valid_functions &

sys/dev/pci/if_ice.c

4531

if (!funcs)

sys/dev/pci/if_ice.c

4534

return max / funcs;

usr.bin/ssh/sshkey.c

1462

if (impl->funcs->generate == NULL)

usr.bin/ssh/sshkey.c

1467

if ((ret = impl->funcs->generate(k, bits)) != 0) {

usr.bin/ssh/sshkey.c

1569

if ((r = impl->funcs->copy_public(k, n)) != 0)

usr.bin/ssh/sshkey.c

1990

if ((ret = impl->funcs->deserialize_public(ktype, b, key)) != 0)

usr.bin/ssh/sshkey.c

2164

if (impl->funcs->sign == NULL)

usr.bin/ssh/sshkey.c

2167

r = impl->funcs->sign(key, sigp, lenp, data, datalen,

usr.bin/ssh/sshkey.c

2194

return impl->funcs->verify(key, sig, siglen, data, dlen,

usr.bin/ssh/sshkey.c

2279

if ((ret = impl->funcs->serialize_public(k, cert,

usr.bin/ssh/sshkey.c

2517

if ((r = impl->funcs->serialize_private(key, b, opts)) != 0)

usr.bin/ssh/sshkey.c

2612

if ((r = impl->funcs->deserialize_private(tname, buf, k)) != 0)

usr.bin/ssh/sshkey.c

374

if (impl->funcs->size != NULL)

usr.bin/ssh/sshkey.c

375

return impl->funcs->size(k);

usr.bin/ssh/sshkey.c

676

if (impl != NULL && impl->funcs->alloc != NULL) {

usr.bin/ssh/sshkey.c

677

if (impl->funcs->alloc(k) != 0) {

usr.bin/ssh/sshkey.c

734

impl->funcs->cleanup != NULL)

usr.bin/ssh/sshkey.c

735

impl->funcs->cleanup(k);

usr.bin/ssh/sshkey.c

789

return impl->funcs->equal(a, b);

usr.bin/ssh/sshkey.c

846

return impl->funcs->serialize_public(key, b, opts);

usr.bin/ssh/sshkey.h

176

const struct sshkey_impl_funcs *funcs;