games/hunt/hunt/list.c

160

int enable;

games/hunt/hunt/list.c

173

enable = 1;

games/hunt/hunt/list.c

174

setsockopt(s, SOL_SOCKET, SO_BROADCAST, &enable, sizeof enable);

lib/libcurses/base/lib_mouse.c

445

enable_xterm_mouse(SCREEN *sp, int enable)

lib/libcurses/base/lib_mouse.c

447

TPUTS_TRACE(enable

lib/libcurses/base/lib_mouse.c

451

sp->_emxmouse_activated = enable;

lib/libcurses/base/lib_mouse.c

453

NCURSES_PUTP2("xterm-mouse", TIPARM_1(sp->_mouse_xtermcap, enable));

lib/libcurses/base/lib_mouse.c

455

sp->_mouse_active = enable;

lib/libcurses/base/lib_mouse.c

460

enable_win32_mouse(SCREEN *sp, int enable)

lib/libcurses/base/lib_mouse.c

463

enable_xterm_mouse(sp, enable);

lib/libcurses/base/lib_mouse.c

465

sp->_mouse_active = enable;

lib/libcurses/base/lib_mouse.c

555

enable_gpm_mouse(SCREEN *sp, bool enable)

lib/libcurses/base/lib_mouse.c

559

T((T_CALLED("enable_gpm_mouse(%d)"), enable));

lib/libcurses/base/lib_mouse.c

561

if (enable && !sp->_mouse_active) {

lib/libcurses/base/lib_mouse.c

600

if (!enable && sp->_mouse_active) {

lib/libcurses/base/lib_mouse.c

606

result = enable;

lib/libcurses/curses.priv.h

713

#define _nc_set_read_thread(enable) /* nothing */

lib/libcurses/tty/lib_tstp.c

290

_nc_set_read_thread(bool enable)

lib/libcurses/tty/lib_tstp.c

293

if (enable) {

lib/libcurses/tty/lib_tstp.c

389

_nc_signal_handler(int enable)

lib/libcurses/tty/lib_tstp.c

391

T((T_CALLED("_nc_signal_handler(%d)"), enable));

lib/libcurses/tty/lib_tstp.c

399

if (!enable) {

lib/libcurses/tty/lib_tstp.c

420

if (enable) {

regress/sys/kern/bind/bind.c

11

int fd1, fd2, enable = 1;

regress/sys/kern/bind/bind.c

29

if (setsockopt(fd1, SOL_SOCKET, SO_REUSEPORT, &enable,

regress/sys/kern/bind/bind.c

39

if (setsockopt(fd2, SOL_SOCKET, SO_REUSEPORT, &enable,

sys/arch/arm/cortex/ampintc.c

564

ampintc_route(int irq, int enable, struct cpu_info *ci)

sys/arch/arm/cortex/ampintc.c

573

if (enable == IRQ_ENABLE)

sys/arch/arm/cortex/ampintc.c

605

ampintc_route_irq(void *v, int enable, struct cpu_info *ci)

sys/arch/arm/cortex/ampintc.c

612

if (enable) {

sys/arch/arm/cortex/ampintc.c

618

ampintc_route(ih->ih_irq, enable, ci);

sys/arch/arm64/arm64/intr.c

632

arm_intr_route(void *cookie, int enable, struct cpu_info *ci)

sys/arch/arm64/arm64/intr.c

638

ic->ic_route(ih->ih_ih, enable, ci);

sys/arch/arm64/dev/agintc.c

1044

agintc_route_irq(void *v, int enable, struct cpu_info *ci)

sys/arch/arm64/dev/agintc.c

1049

if (enable) {

sys/arch/arm64/dev/agintc.c

1058

agintc_route(struct agintc_softc *sc, int irq, int enable, struct cpu_info *ci)

sys/arch/arm64/dev/ampintc.c

591

ampintc_route(int irq, int enable, struct cpu_info *ci)

sys/arch/arm64/dev/ampintc.c

600

if (enable == IRQ_ENABLE)

sys/arch/arm64/dev/ampintc.c

650

ampintc_route_irq(void *v, int enable, struct cpu_info *ci)

sys/arch/arm64/dev/ampintc.c

657

if (enable) {

sys/arch/arm64/dev/ampintc.c

663

ampintc_route(ih->ih_irq, enable, ci);

sys/arch/arm64/dev/apldc.c

1159

.enable = apldckbd_enable,

sys/arch/arm64/dev/apldc.c

1354

.enable = apldcms_enable,

sys/arch/arm64/dev/aplhidev.c

586

.enable = aplkbd_enable,

sys/arch/arm64/dev/aplhidev.c

788

.enable = aplms_enable,

sys/arch/arm64/dev/bcm2836_intr.c

605

bcm_intc_intr_route(void *cookie, int enable, struct cpu_info *ci)

sys/arch/arm64/dev/bcm2836_intr.c

611

if (enable)

sys/arch/armv7/armv7/intr.c

608

arm_intr_route(void *cookie, int enable, struct cpu_info *ci)

sys/arch/armv7/armv7/intr.c

614

ic->ic_route(ih->ih_ih, enable, ci);

sys/arch/armv7/omap/ommmc.c

806

ommmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)

sys/arch/armv7/omap/ommmc.c

811

if (enable) {

sys/arch/i386/pci/pci_machdep.c

379

tag.mode2.enable = 0xf0 | (function << 1);

sys/arch/i386/pci/pci_machdep.c

407

*fp = (tag.mode2.enable >> 1) & 0x7;

sys/arch/i386/pci/pci_machdep.c

465

outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);

sys/arch/i386/pci/pci_machdep.c

503

outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);

sys/arch/i386/pci/pci_machdep.h

53

u_int8_t enable;

sys/arch/macppc/dev/zs.c

364

cs->enable = zs_enable;

sys/arch/macppc/dev/zs.c

835

void macobio_modem_power(int enable);

sys/arch/macppc/pci/macobio.c

281

macobio_modem_power(int enable)

sys/arch/macppc/pci/macobio.c

288

if (enable)

sys/arch/macppc/pci/macobio.c

295

if (enable) {

sys/arch/macppc/pci/macobio.c

52

void macobio_modem_power(int enable);

sys/arch/octeon/dev/cn30xxasx.c

69

cn30xxasx_enable(struct cn30xxasx_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxasx.c

71

cn30xxasx_enable_tx(sc, enable);

sys/arch/octeon/dev/cn30xxasx.c

72

cn30xxasx_enable_rx(sc, enable);

sys/arch/octeon/dev/cn30xxasx.c

77

cn30xxasx_enable_tx(struct cn30xxasx_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxasx.c

82

if (enable)

sys/arch/octeon/dev/cn30xxasx.c

91

cn30xxasx_enable_rx(struct cn30xxasx_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxasx.c

96

if (enable)

sys/arch/octeon/dev/cn30xxgmx.c

1309

cn30xxgmx_sgmii_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

1316

if (!enable)

sys/arch/octeon/dev/cn30xxgmx.c

453

cn30xxgmx_link_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

457

cn30xxgmx_tx_int_enable(sc, enable);

sys/arch/octeon/dev/cn30xxgmx.c

458

cn30xxgmx_rx_int_enable(sc, enable);

sys/arch/octeon/dev/cn30xxgmx.c

461

if (enable) {

sys/arch/octeon/dev/cn30xxgmx.c

503

cn30xxgmx_tx_ovr_bp_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

509

if (enable) {

sys/arch/octeon/dev/cn30xxgmx.c

525

cn30xxgmx_rx_pause_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

527

if (enable) {

sys/arch/octeon/dev/cn30xxgmx.c

537

cn30xxgmx_tx_int_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

548

_GMX_WR8(sc, GMX0_TX_INT_EN, enable ? tx_int_xxx : 0);

sys/arch/octeon/dev/cn30xxgmx.c

552

cn30xxgmx_rx_int_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

577

_GMX_PORT_WR8(sc, GMX0_RX0_INT_EN, enable ? rx_int_xxx : 0);

sys/arch/octeon/dev/cn30xxgmx.c

603

uint64_t rx_frm_ctl, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

608

if (enable)

sys/arch/octeon/dev/cn30xxgmx.c

697

cn30xxgmx_port_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

699

(*sc->sc_port_ops->port_ops_enable)(sc, enable);

sys/arch/octeon/dev/cn30xxgmx.c

861

cn30xxgmx_agl_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxgmx.c

863

if (enable)

sys/arch/octeon/dev/cn30xxgmx.c

951

cn30xxgmx_rgmii_enable(struct cn30xxgmx_port_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxpip.c

141

int enable)

sys/arch/octeon/dev/cn30xxpip.c

146

if (enable)

sys/arch/octeon/dev/cn30xxpko.c

115

cn30xxpko_port_enable(struct cn30xxpko_softc *sc, int enable)

sys/arch/octeon/dev/cn30xxpko.c

128

SET(mem_queue_qos, ((enable ? 0xffULL : 0x00ULL) << 53) &

sys/arch/powerpc/include/cpu.h

402

ppc_intr_enable(int enable)

sys/arch/powerpc/include/cpu.h

405

if (enable != 0) {

sys/arch/riscv64/dev/plic.c

473

plic_intr_route(void *cookie, int enable, struct cpu_info *ci)

sys/arch/riscv64/dev/plic.c

482

if (enable == IRQ_ENABLE) {

sys/arch/riscv64/dev/plic.c

694

plic_intr_route_grid(int irq, int enable, int cpu)

sys/arch/riscv64/dev/plic.c

707

if (enable == IRQ_ENABLE)

sys/arch/riscv64/riscv64/intr.c

536

riscv_intr_route(void *cookie, int enable, struct cpu_info *ci)

sys/arch/riscv64/riscv64/intr.c

542

ic->ic_route(ih->ih_ih, enable, ci);

sys/arch/sparc64/dev/creator.c

266

curs->enable = sc->sc_curs_enabled;

sys/arch/sparc64/dev/creator.c

383

sc->sc_curs_enabled = curs->enable;

sys/arch/sparc64/dev/z8530kbd.c

325

if (!cs->enable)

sys/dev/acpi/acpi.c

2484

acpi_toggle_wakedev(struct acpi_softc *sc, struct aml_node *node, int enable)

sys/dev/acpi/acpi.c

2491

wentry->q_enabled = enable ? 1 : 0;

sys/dev/acpi/acpi.c

2494

wentry->q_gpe, enable ? "en" : "dis");

sys/dev/acpi/acpidmar.c

1752

iommu_enable_qi(struct iommu_softc *iommu, int enable)

sys/dev/acpi/acpidmar.c

1762

if (enable) {

sys/dev/acpi/acpidmar.c

1813

iommu_enable_translation(struct iommu_softc *iommu, int enable)

sys/dev/acpi/acpidmar.c

1820

if (enable) {

sys/dev/acpi/acpidmar.h

305

context_set_fpd(struct context_entry *ce, int enable)

sys/dev/acpi/acpidmar.h

308

if (enable)

sys/dev/acpi/aplgpio.c

275

uint32_t status, enable;

sys/dev/acpi/aplgpio.c

285

enable = bus_space_read_4(sc->sc_memt, sc->sc_memh,

sys/dev/acpi/aplgpio.c

287

status &= enable;

sys/dev/acpi/glkgpio.c

275

uint32_t status, enable;

sys/dev/acpi/glkgpio.c

285

enable = bus_space_read_4(sc->sc_memt, sc->sc_memh,

sys/dev/acpi/glkgpio.c

287

status &= enable;

sys/dev/acpi/inthid.c

335

inthid_button_array_enable(struct inthid_softc *sc, int enable)

sys/dev/acpi/inthid.c

346

if (inthid_eval(sc, INTHID_FUNC_BTNE, enable ? cap : 1, NULL) != 0) {

sys/dev/acpi/pchgpio.c

743

uint32_t enable;

sys/dev/acpi/pchgpio.c

759

enable = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],

sys/dev/acpi/pchgpio.c

761

enable &= ~(1 << bit);

sys/dev/acpi/pchgpio.c

763

sc->sc_device->gpi_ie + bank * 4, enable);

sys/dev/acpi/pchgpio.c

773

uint32_t status, enable;

sys/dev/acpi/pchgpio.c

788

enable = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],

sys/dev/acpi/pchgpio.c

790

status &= enable;

sys/dev/cardbus/com_cardbus.c

271

sc->enable = com_cardbus_enable;

sys/dev/cardbus/if_rtw_cardbus.c

163

rtw_cardbus_funcregen(struct rtw_regs *regs, int enable)

sys/dev/cardbus/if_rtw_cardbus.c

168

if (enable) {

sys/dev/fdt/dwmmc.c

574

dwmmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)

sys/dev/fdt/dwmmc.c

578

if (enable)

sys/dev/fdt/hiclock.c

171

sc->sc_cd.cd_enable = hiclock_compat[i].enable;

sys/dev/fdt/hiclock.c

67

void (*enable)(void *, uint32_t *, int);

sys/dev/fdt/hiclock.c

83

.enable = hi3670_crgctrl_enable,

sys/dev/fdt/hiclock.c

97

.enable = hi3670_crgctrl_enable,

sys/dev/fdt/if_mvpp.c

3503

uint8_t byte, uint8_t enable)

sys/dev/fdt/if_mvpp.c

3506

pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;

sys/dev/fdt/if_mvpp.c

3511

uint8_t *byte, uint8_t *enable)

sys/dev/fdt/if_mvpp.c

3514

*enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];

sys/dev/fdt/if_mvpp.c

3529

mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t enable)

sys/dev/fdt/if_mvpp.c

3534

if (!(enable & BIT(i)))

sys/dev/fdt/if_mvpp.c

3543

pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable;

sys/dev/fdt/if_mvpp.c

3554

uint32_t *word, uint32_t *enable)

sys/dev/fdt/if_mvpp.c

3563

((uint8_t *)enable)[index] = mask;

sys/dev/fdt/imxesdhc.c

758

imxesdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)

sys/dev/fdt/imxesdhc.c

762

if (enable) {

sys/dev/fdt/qcpas.c

1318

uint32_t enable;

sys/dev/fdt/qcpas.c

1326

msg.enable = 1;

sys/dev/fdt/rkanxdp.c

179

.enable = rkanxdp_encoder_enable,

sys/dev/fdt/rkclock.c

363

void (*enable)(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

489

sc->sc_cd.cd_enable = rkclock_compat[i].enable;

sys/dev/fdt/rkdwhdmi.c

219

.enable = rkdwhdmi_encoder_enable,

sys/dev/fdt/rkvop.c

392

if (enabled != state->enable)

sys/dev/fdt/sfp.c

140

sfp_gpio_enable(void *cookie, int enable)

sys/dev/fdt/sfp.c

145

gpio_controller_set_pin(sc->sc_tx_disable_gpio, !enable);

sys/dev/fdt/sxiccmu.c

364

void (*enable)(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

390

.enable = sxiccmu_pll6_enable

sys/dev/fdt/sxiccmu.c

399

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

404

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

409

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

414

.enable = sxiccmu_mmc_enable

sys/dev/fdt/sxiccmu.c

419

.enable = sxiccmu_gate_enable,

sys/dev/fdt/sxiccmu.c

425

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

430

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

435

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

440

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

445

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

450

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

455

.enable = sxiccmu_gate_enable,

sys/dev/fdt/sxiccmu.c

470

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

475

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

480

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

494

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

499

.enable = sxiccmu_gate_enable,

sys/dev/fdt/sxiccmu.c

505

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

510

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

515

.enable = sxiccmu_gate_enable,

sys/dev/fdt/sxiccmu.c

521

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

530

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

535

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

540

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

545

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

550

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

555

.enable = sxiccmu_gate_enable

sys/dev/fdt/sxiccmu.c

564

.enable = sxiccmu_mmc_enable

sys/dev/fdt/sxiccmu.c

569

.enable = sxiccmu_gate_enable,

sys/dev/fdt/sxiccmu.c

575

.enable = sxiccmu_gate_enable,

sys/dev/fdt/sxiccmu.c

614

clock->sc_cd.cd_enable = sxiccmu_devices[i].enable;

sys/dev/fdt/sxidog.c

143

int enable;

sys/dev/fdt/sxidog.c

156

enable = (period > 0) ? WDOG_RST_EN : 0;

sys/dev/fdt/sxidog.c

158

enable | WDOG_EN | WDOG_INTV_VALUE(period));

sys/dev/fdt/sxidog.c

162

enable = (period > 0) ? WDOG0_EN : 0;

sys/dev/fdt/sxidog.c

164

enable | WDOG0_INTV_VALUE(period) | sc->sc_key);

sys/dev/fdt/sximmc.c

524

sximmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)

sys/dev/fdt/sximmc.c

530

if (enable)

sys/dev/fdt/sxitemp.c

120

uint32_t enable, irq;

sys/dev/fdt/sxitemp.c

162

enable = irq = 0;

sys/dev/fdt/sxitemp.c

164

enable |= THS_CTRL2_SENSE0_EN;

sys/dev/fdt/sxitemp.c

168

enable |= THS_CTRL2_SENSE1_EN;

sys/dev/fdt/sxitemp.c

172

enable |= THS_CTRL2_SENSE2_EN;

sys/dev/fdt/sxitemp.c

182

HWRITE4(sc, THS_CTRL2, THS_CTRL2_ADC_ACQ(31) | enable);

sys/dev/hid/hidcc.c

652

sc->sc_enable = hca->enable;

sys/dev/hid/hidcc.c

761

.enable = hidcc_enable,

sys/dev/hid/hidccvar.h

30

int (*enable)(void *, int);

sys/dev/i2c/iasuskbd.c

209

.enable = iasuskbd_enable,

sys/dev/i2c/icc.c

98

.enable = icc_enable,

sys/dev/i2c/ietp.c

341

ietp_iic_set_absolute_mode(struct ietp_softc *sc, bool enable)

sys/dev/i2c/ietp.c

374

val = enable ? IETP_CTRL_ABSOLUTE : IETP_CTRL_STANDARD;

sys/dev/ic/aac.c

2025

aac_sa_set_interrupts(struct aac_softc *sc, int enable)

sys/dev/ic/aac.c

2028

sc->aac_dev.dv_xname, enable ? "en" : "dis"));

sys/dev/ic/aac.c

2030

if (enable)

sys/dev/ic/aac.c

2037

aac_rx_set_interrupts(struct aac_softc *sc, int enable)

sys/dev/ic/aac.c

2040

sc->aac_dev.dv_xname, enable ? "en" : "dis"));

sys/dev/ic/aac.c

2042

if (enable)

sys/dev/ic/aac.c

2049

aac_fa_set_interrupts(struct aac_softc *sc, int enable)

sys/dev/ic/aac.c

2052

sc->aac_dev.dv_xname, enable ? "en" : "dis"));

sys/dev/ic/aac.c

2054

if (enable) {

sys/dev/ic/aac.c

2064

aac_rkt_set_interrupts(struct aac_softc *sc, int enable)

sys/dev/ic/aac.c

2067

sc->aac_dev.dv_xname, enable ? "en" : "dis"));

sys/dev/ic/aac.c

2069

if (enable)

sys/dev/ic/aic79xx.c

6758

ahd_intr_enable(struct ahd_softc *ahd, int enable)

sys/dev/ic/aic79xx.c

6766

if (enable) {

sys/dev/ic/aic79xx.c

6793

ahd_enable_coalescing(struct ahd_softc *ahd, int enable)

sys/dev/ic/aic79xx.c

6797

if (enable)

sys/dev/ic/aic79xx.c

9387

if (cel->enable != 0) {

sys/dev/ic/aic79xx.h

1352

void ahd_intr_enable(struct ahd_softc *ahd, int enable);

sys/dev/ic/aic79xx.h

1358

int enable);

sys/dev/ic/aic7xxx.c

4923

ahc_intr_enable(struct ahc_softc *ahc, int enable)

sys/dev/ic/aic7xxx.c

4931

if (enable) {

sys/dev/ic/aic7xxx.c

6779

if (cel->enable != 0) {

sys/dev/ic/aic7xxxvar.h

1198

void ahc_intr_enable(struct ahc_softc *ahc, int enable);

sys/dev/ic/anxdp.c

693

sc->sc_panel->funcs->enable != NULL)

sys/dev/ic/anxdp.c

694

sc->sc_panel->funcs->enable(sc->sc_panel);

sys/dev/ic/anxdp.c

732

.enable = anxdp_bridge_enable,

sys/dev/ic/ar5210.c

1911

ar5k_ar5210_softcrypto(struct ath_hal *hal, HAL_BOOL enable)

sys/dev/ic/ar5210.c

1917

if (enable == AH_TRUE) {

sys/dev/ic/ar5210.c

2316

ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable)

sys/dev/ic/ar5210.c

2324

if (enable == AH_TRUE) {

sys/dev/ic/ar5211.c

2022

ar5k_ar5211_softcrypto(struct ath_hal *hal, HAL_BOOL enable)

sys/dev/ic/ar5211.c

2028

if (enable == AH_TRUE) {

sys/dev/ic/ar5211.c

2463

ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable)

sys/dev/ic/ar5211.c

2470

if (enable == AH_TRUE) {

sys/dev/ic/ar5212.c

2385

ar5k_ar5212_softcrypto(struct ath_hal *hal, HAL_BOOL enable)

sys/dev/ic/ar5212.c

2391

if (enable == AH_TRUE) {

sys/dev/ic/ar5212.c

2890

ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable)

sys/dev/ic/ar5212.c

2897

if (enable == AH_TRUE) {

sys/dev/ic/ar5xxx.h

1052

_t void (_a _n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \

sys/dev/ic/atw.c

1460

atw_bbp_io_enable(struct atw_softc *sc, int enable)

sys/dev/ic/atw.c

1462

if (enable) {

sys/dev/ic/bcm2835_vcprop.h

362

uint32_t enable; /* 1 - visible */

sys/dev/ic/bt485.c

360

data->curenb = cursorp->enable;

sys/dev/ic/bt485.c

417

cursorp->enable = data->curenb; /* DOCUR */

sys/dev/ic/com.c

1581

if (!sc->enable)

sys/dev/ic/comvar.h

134

int (*enable)(struct com_softc *);

sys/dev/ic/dwhdmi.c

713

.enable = dwhdmi_bridge_enable,

sys/dev/ic/dwhdmiphy.c

177

dwhdmi_phy_enable_power(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

183

reg |= (enable << HDMI_PHY_CONF0_PDZ_OFFSET);

sys/dev/ic/dwhdmiphy.c

188

dwhdmi_phy_enable_tmds(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

194

reg |= (enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);

sys/dev/ic/dwhdmiphy.c

199

dwhdmi_phy_gen2_pddq(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

205

reg |= (enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);

sys/dev/ic/dwhdmiphy.c

210

dwhdmi_phy_gen2_txpwron(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

216

reg |= (enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);

sys/dev/ic/dwhdmiphy.c

221

dwhdmi_phy_sel_data_en_pol(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

227

reg |= (enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);

sys/dev/ic/dwhdmiphy.c

232

dwhdmi_phy_sel_interface_control(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

238

reg |= (enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);

sys/dev/ic/dwhdmiphy.c

243

dwhdmi_phy_enable_svsret(struct dwhdmi_softc *sc, uint8_t enable)

sys/dev/ic/dwhdmiphy.c

249

reg |= (enable << HDMI_PHY_CONF0_SVSRET_OFFSET);

sys/dev/ic/dwiic.c

202

dwiic_enable(struct dwiic_softc *sc, int enable)

sys/dev/ic/dwiic.c

207

dwiic_write(sc, DW_IC_ENABLE, enable);

sys/dev/ic/dwiic.c

208

if ((dwiic_read(sc, DW_IC_ENABLE_STATUS) & 1) == enable)

sys/dev/ic/dwiic.c

215

(enable ? "en" : "dis"));

sys/dev/ic/lemac.c

433

lemac_multicast_op(u_int16_t *mctbl, const u_char *mca, int enable)

sys/dev/ic/lemac.c

455

if (enable) {

sys/dev/ic/malo.c

160

uint16_t enable;

sys/dev/ic/malo.c

2131

malo_cmd_set_radio(struct malo_softc *sc, uint16_t enable,

sys/dev/ic/malo.c

2146

body->enable = htole16(enable);

sys/dev/ic/qwx.c

11073

qwx_qmi_wlanfw_wlan_ini_send(struct qwx_softc *sc, int enable)

sys/dev/ic/qwx.c

11079

req.enablefwlog = enable ? 1 : 0;

sys/dev/ic/qwx.c

23124

qwx_mac_config_mon_status_default(struct qwx_softc *sc, int enable)

sys/dev/ic/qwx.c

23133

if (enable)

sys/dev/ic/qwx.c

23145

if (enable && !sc->hw_params.rxdma1_enable) {

sys/dev/ic/qwxreg.h

3929

uint32_t enable;

sys/dev/ic/qwxreg.h

4025

uint32_t enable;

sys/dev/ic/qwxreg.h

4034

uint32_t enable;

sys/dev/ic/qwxreg.h

4087

uint32_t enable;

sys/dev/ic/qwxreg.h

4101

uint32_t enable;

sys/dev/ic/qwxreg.h

5514

uint32_t enable;

sys/dev/ic/qwxreg.h

5554

uint32_t enable;

sys/dev/ic/qwxreg.h

5828

uint32_t enable;

sys/dev/ic/qwxreg.h

6017

uint32_t enable;

sys/dev/ic/qwxreg.h

6151

uint8_t enable;

sys/dev/ic/qwz.c

20332

qwz_mac_config_mon_status_default(struct qwz_softc *sc, int enable)

sys/dev/ic/qwz.c

20341

if (enable)

sys/dev/ic/qwz.c

20353

if (enable && !sc->hw_params.rxdma1_enable) {

sys/dev/ic/qwzreg.h

3984

uint32_t enable;

sys/dev/ic/qwzreg.h

4080

uint32_t enable;

sys/dev/ic/qwzreg.h

4089

uint32_t enable;

sys/dev/ic/qwzreg.h

4142

uint32_t enable;

sys/dev/ic/qwzreg.h

4156

uint32_t enable;

sys/dev/ic/qwzreg.h

5568

uint32_t enable;

sys/dev/ic/qwzreg.h

5608

uint32_t enable;

sys/dev/ic/qwzreg.h

5882

uint32_t enable;

sys/dev/ic/qwzreg.h

6071

uint32_t enable;

sys/dev/ic/qwzreg.h

6205

uint8_t enable;

sys/dev/ic/re.c

2369

re_wol(struct ifnet *ifp, int enable)

sys/dev/ic/re.c

2374

if (enable) {

sys/dev/ic/re.c

2391

if (enable) {

sys/dev/ic/rtw.c

1050

rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable)

sys/dev/ic/rtw.c

1055

enable ? "enable" : "disable", flags));

sys/dev/ic/rtw.c

1066

if (enable)

sys/dev/ic/rtw.c

270

rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)

sys/dev/ic/rtw.c

277

if (enable)

sys/dev/ic/rtw.c

284

rtw_txdac_enable(sc, !enable);

sys/dev/ic/rtw.c

371

rtw_config0123_enable(struct rtw_regs *regs, int enable)

sys/dev/ic/rtw.c

376

if (enable)

sys/dev/ic/rtw.c

388

rtw_anaparm_enable(struct rtw_regs *regs, int enable)

sys/dev/ic/rtw.c

394

if (enable)

sys/dev/ic/rtw.c

404

rtw_txdac_enable(struct rtw_softc *sc, int enable)

sys/dev/ic/rtw.c

410

if (enable)

sys/dev/ic/rtw.c

4480

uint32_t enable;

sys/dev/ic/rtw.c

4486

enable = 0x0;

sys/dev/ic/rtw.c

4489

enable = MAX2820_ENABLE_DEFAULT;

sys/dev/ic/rtw.c

4492

return rtw_rf_hostwrite(sc, MAX2820_ENABLE, enable);

sys/dev/ic/w83l518d.c

71

wb_led(struct wb_softc *wb, int enable)

sys/dev/ic/w83l518d.c

76

if (enable)

sys/dev/ic/w83l518d_sdmmc.c

548

wb_sdmmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)

sys/dev/ic/w83l518d_sdmmc.c

550

REPORT(sch, "TRACE: sdmmc/card_enable_intr(wb, enable=%d)\n", enable);

sys/dev/ic/xl.c

2638

xl_wol(struct ifnet *ifp, int enable)

sys/dev/ic/xl.c

2643

if (enable) {

sys/dev/ic/z8530sc.h

122

int (*enable)(struct zs_chanstate *);

sys/dev/ic/z8530tty.c

343

if (!cs->enable)

sys/dev/ic/z8530tty.c

496

if (cs->enable) {

sys/dev/ic/z8530tty.c

497

if ((*cs->enable)(cs)) {

sys/dev/ofw/ofw_misc.c

363

sfp_do_enable(uint32_t phandle, int enable)

sys/dev/ofw/ofw_misc.c

372

return sd->sd_enable(sd->sd_cookie, enable);

sys/dev/ofw/ofw_regulator.c

109

regulator_fixed_set(int node, int enable)

sys/dev/ofw/ofw_regulator.c

121

if (enable)

sys/dev/ofw/ofw_regulator.c

151

if (enable)

sys/dev/ofw/ofw_regulator.c

158

if (enable && startup_delay > 0)

sys/dev/ofw/ofw_regulator.c

165

regulator_set(uint32_t phandle, int enable)

sys/dev/ofw/ofw_regulator.c

178

if (OF_getproplen(node, "regulator-always-on") == 0 && !enable)

sys/dev/ofw/ofw_regulator.c

187

return rd->rd_enable(rd->rd_cookie, enable);

sys/dev/ofw/ofw_regulator.c

190

return regulator_fixed_set(node, enable);

sys/dev/pci/agp.c

387

if (sc->sc_methods->enable != NULL) {

sys/dev/pci/agp.c

388

ret = sc->sc_methods->enable(sc->sc_chipc, mode);

sys/dev/pci/agpvar.h

70

int (*enable)(void *, u_int32_t mode);

sys/dev/pci/ahc_pci.c

1137

ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,

sys/dev/pci/ahc_pci.c

1158

if (enable)

sys/dev/pci/ahc_pci.c

1172

if (enable)

sys/dev/pci/ahc_pci.c

1199

int enable;

sys/dev/pci/ahc_pci.c

1204

enable = FALSE;

sys/dev/pci/ahc_pci.c

1222

enable = TRUE;

sys/dev/pci/ahc_pci.c

1234

ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);

sys/dev/pci/ahc_pci.c

1245

ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);

sys/dev/pci/ahc_pci.c

1257

ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);

sys/dev/pci/ahc_pci.c

1282

if (1/*bootverbose*/ && enable) {

sys/dev/pci/ahc_pci.c

1288

ahc_scbram_config(ahc, enable, pcheck, fast, large);

sys/dev/pci/ahc_pci.c

635

static void ahc_scbram_config(struct ahc_softc *ahc, int enable,

sys/dev/pci/auixp.c

773

u_int32_t status, enable, detected_codecs;

sys/dev/pci/auixp.c

820

enable = bus_space_read_4(iot, ioh, ATI_REG_IER);

sys/dev/pci/auixp.c

821

enable &= ~detected_codecs;

sys/dev/pci/auixp.c

822

bus_space_write_4(iot, ioh, ATI_REG_IER, enable);

sys/dev/pci/azalia.c

1635

this->w[this->audiofunc].enable = 1;

sys/dev/pci/azalia.c

1664

if (!w->enable)

sys/dev/pci/azalia.c

1672

w->enable = 0;

sys/dev/pci/azalia.c

1925

if (!w->enable || w->type != COP_AWTYPE_PIN_COMPLEX)

sys/dev/pci/azalia.c

2310

if (w->enable == 0)

sys/dev/pci/azalia.c

2440

if (w->enable == 0)

sys/dev/pci/azalia.c

2533

if (w->enable == 0)

sys/dev/pci/azalia.c

2957

this->enable = 1;

sys/dev/pci/azalia.c

2980

this->enable = 0;

sys/dev/pci/azalia.c

3047

if (!this->w[this->w[i].connections[j]].enable)

sys/dev/pci/azalia.c

3105

if (w->enable == 0)

sys/dev/pci/azalia.c

3198

if (codec->w[i].enable == 0)

sys/dev/pci/azalia.c

3228

if (codec->w[j].enable == 0) {

sys/dev/pci/azalia.c

3229

codec->w[i].enable = 0;

sys/dev/pci/azalia.c

3353

this->enable = 0;

sys/dev/pci/azalia.c

3460

if (w->enable)

sys/dev/pci/azalia.h

557

int enable;

sys/dev/pci/azalia_codec.c

2641

nid == 0x1d && w->enable == 0) {

sys/dev/pci/azalia_codec.c

2645

w->enable = 1;

sys/dev/pci/azalia_codec.c

2652

w->enable = 1;

sys/dev/pci/azalia_codec.c

2659

w->enable = 1;

sys/dev/pci/azalia_codec.c

2666

w->enable = 1;

sys/dev/pci/azalia_codec.c

2673

w->enable = 1;

sys/dev/pci/azalia_codec.c

2680

w->enable = 1;

sys/dev/pci/azalia_codec.c

2687

w->enable = 1;

sys/dev/pci/azalia_codec.c

2691

nid == 0x1c && w->enable == 0 && w->d.pin.device == CORB_CD_CD) {

sys/dev/pci/azalia_codec.c

2694

w->enable = 1;

sys/dev/pci/azalia_codec.c

577

if (!VALID_WIDGET_NID(nid, this) || !this->w[nid].enable)

sys/dev/pci/azalia_codec.c

697

this->w[conv].enable = 0;

sys/dev/pci/azalia_codec.c

904

if (!w->enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

194

int (*set_debug_mode)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

597

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

599

amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

38

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

42

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

46

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1986

bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1990

if (enable) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

779

static void amdgpu_gfx_do_off_ctrl(struct amdgpu_device *adev, bool enable,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

789

if (enable) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

846

void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

851

amdgpu_gfx_do_off_ctrl(adev, enable, no_delay);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

866

void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

868

amdgpu_gfx_do_off_ctrl(adev, enable, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

349

void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

602

void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

603

void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

956

bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

969

if (enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

156

void (*set_prt)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

443

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.h

35

void (*update_clock_gating)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

36

void (*update_memory_power_gating)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

267

int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

272

return mca_funcs->mca_set_debug_mode(adev, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h

131

int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h

162

int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

703

uint32_t node_id, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

709

op_input.change_config.option.limit_single_process = enable ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h

65

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

68

void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

78

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

80

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

84

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

86

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

88

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

95

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1855

union ta_ras_cmd_input *info, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1863

cmd_id = enable ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

572

union ta_ras_cmd_input *info, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4924

int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4930

ret = amdgpu_mca_smu_set_debug_mode(adev, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4932

con->is_aca_debug_mode = enable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4938

int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4945

ret = amdgpu_aca_smu_set_debug_mode(adev, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4947

ret = amdgpu_mca_smu_set_debug_mode(adev, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4949

con->is_aca_debug_mode = enable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

833

struct ras_common_if *head, int enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

847

if (enable) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

869

struct ras_common_if *head, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

893

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

905

ret = psp_ras_enable_features(&adev->psp, info, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

908

enable ? "enable":"disable",

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

919

__amdgpu_ras_feature_enable(adev, head, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

926

struct ras_common_if *head, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

935

if (enable) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

971

ret = amdgpu_ras_feature_enable(adev, head, enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

870

struct ras_common_if *head, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

873

struct ras_common_if *head, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

940

int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

941

int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

287

void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

41

void (*update_rom_clock_gating)(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2257

void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2264

adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2267

if (enable) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2300

if (enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2305

adev->mman.buffer_funcs_enabled = enable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

168

bool enable);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1474

bool enable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1477

enable = !!atomic_read(&adev->vm_manager.num_prt_users);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1478

adev->gmc.gmc_funcs->set_prt(adev, enable);

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

33

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

39

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

49

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

55

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

35

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

44

if (enable)

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

55

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

65

if (enable)

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

34

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

40

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

51

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

57

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

72

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

78

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

89

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

95

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

58

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

64

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

75

bool enable)

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

81

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

241

int enable,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

250

if (enable) {

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

294

args.v3.ucEnable = enable;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

341

static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

372

if (enable) {

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

398

static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

403

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

410

if (enable)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

874

bool enable)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

878

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

895

bool enable)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

899

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1415

bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1421

enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1742

static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1753

if (enable && dig->afmt->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1755

if (!enable && !dig->afmt->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1758

if (!enable && dig->afmt->pin) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1763

dig->afmt->enabled = enable;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1766

enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1813

static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1821

if (enable)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1827

static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1833

if (enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1393

bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1399

enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1649

static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1657

if (enable) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1686

static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1694

if (enable) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1784

static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1795

if (enable && dig->afmt->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1798

if (!enable && !dig->afmt->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1801

if (!enable && dig->afmt->pin) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1806

dig->afmt->enabled = enable;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1809

enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1857

static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1865

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1868

static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1874

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1387

bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1393

enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1689

static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1700

if (enable && dig->afmt->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1702

if (!enable && !dig->afmt->enabled)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1705

if (!enable && dig->afmt->pin) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1710

dig->afmt->enabled = enable;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1713

enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1760

static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1768

if (enable)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1774

static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1780

if (enable)

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

115

bool enable)

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

118

ForceParWrRMW, enable);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

44

bool enable)

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

48

if (enable) {

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

80

bool enable)

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

87

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

265

bool enable)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

269

if (enable) {

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

307

bool enable)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

315

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4554

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4560

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5419

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5434

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5436

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5438

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5440

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5485

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5491

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6072

static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6077

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6078

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6079

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6086

if (amdgpu_in_reset(adev) && !enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6096

DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6602

static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6604

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7275

static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7277

gfx_v10_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7278

gfx_v10_0_cp_compute_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7927

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7935

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7971

} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8001

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8009

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8060

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8067

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8119

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8126

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8249

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8253

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8255

gfx_v10_0_update_fine_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8259

gfx_v10_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8261

gfx_v10_0_update_3d_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8263

gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8276

gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8278

gfx_v10_0_update_3d_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8280

gfx_v10_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8282

gfx_v10_0_update_fine_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8291

gfx_v10_0_enable_gui_idle_interrupt(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8357

static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8361

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8378

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8393

static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8397

gfx_v10_cntl_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8435

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8448

amdgpu_gfx_off_ctrl(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8454

if (!enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8457

gfx_v10_cntl_pg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8459

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2206

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2221

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2223

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2225

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2227

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2264

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2270

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3113

static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3118

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3119

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3129

DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

345

bool enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3813

static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3820

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3822

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3824

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3826

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3828

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3830

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3832

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3834

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3836

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3838

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3843

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4645

static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4647

gfx_v11_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4648

gfx_v11_0_cp_compute_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4841

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4850

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4868

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5324

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5333

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5343

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5352

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5362

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5371

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5381

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5389

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5416

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5427

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5544

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5548

gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5550

gfx_v11_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5552

gfx_v11_0_update_repeater_fgcg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5554

gfx_v11_0_update_sram_fgcg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5556

gfx_v11_0_update_perf_clk(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5564

gfx_v11_0_enable_gui_idle_interrupt(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5616

static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5620

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5628

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5644

static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5648

gfx_v11_cntl_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5657

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5666

amdgpu_gfx_off_ctrl(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5674

if (!enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5677

gfx_v11_cntl_pg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5679

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1871

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1886

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1888

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1890

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1892

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1929

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1935

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2326

static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2331

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2332

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2342

DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2772

static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2778

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2780

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2782

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2784

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2786

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2788

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2790

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2792

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2794

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2796

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2799

adev->gfx.kiq[0].ring.sched.ready = enable;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

290

bool enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3509

static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3511

gfx_v12_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3512

gfx_v12_0_cp_compute_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3698

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3707

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3725

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3939

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3948

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4001

static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4006

static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4016

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4024

amdgpu_gfx_off_ctrl(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4034

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4045

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4151

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4158

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4185

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4194

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4206

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4215

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4225

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4229

gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4231

gfx_v12_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4233

gfx_v12_0_update_repeater_fgcg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4235

gfx_v12_0_update_sram_fgcg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4237

gfx_v12_0_update_perf_clk(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4245

gfx_v12_0_enable_gui_idle_interrupt(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1936

static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1938

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2226

static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2228

gfx_v6_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2237

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2243

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2251

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2410

static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2412

WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2414

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2547

static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2553

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2586

static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2591

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2658

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2663

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2667

static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2672

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2680

static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2752

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2754

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2777

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2782

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2791

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2796

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2819

static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2821

gfx_v6_0_enable_gfx_cgpg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2822

gfx_v6_0_enable_gfx_static_mgpg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2823

gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2372

static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2374

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2638

static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2640

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3042

static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3044

gfx_v7_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3045

gfx_v7_0_cp_compute_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3063

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3067

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3253

static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3258

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3490

static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3496

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3533

static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3537

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3619

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3623

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3634

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3639

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3648

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3653

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3661

static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3666

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3674

static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3679

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3696

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3700

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3767

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3772

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3781

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3786

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3846

static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3848

gfx_v7_0_enable_gfx_cgpg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3849

gfx_v7_0_enable_gfx_static_mgpg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3850

gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3844

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3848

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3849

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3850

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3851

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4004

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4006

WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4010

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4012

WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4015

static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4017

WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4084

static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4088

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4280

static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4282

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4738

static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4740

gfx_v8_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4741

gfx_v8_0_cp_compute_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5276

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5282

amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5284

WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5288

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5290

WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5294

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5296

WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5300

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5302

WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5306

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5308

WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5311

if (!enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5316

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5318

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5332

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5358

cz_update_gfx_cg_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5360

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5365

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5373

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5378

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5383

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5582

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5587

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5682

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5688

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5770

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5774

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5778

gfx_v8_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5779

gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5784

gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5785

gfx_v8_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6767

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6772

val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6797

static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6807

val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6817

gfx_v8_0_emit_wave_limit_cs(ring, i, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1807

static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1809

WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2751

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2759

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2760

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2761

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2763

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2926

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2932

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2994

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3002

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3008

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3016

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3022

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3030

enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3036

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3043

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3049

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3056

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3060

if (!enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3066

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3073

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3079

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3086

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3241

static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3245

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3246

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3247

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3248

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3249

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3250

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3251

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3252

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3253

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3254

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3255

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3256

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3457

static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3459

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4011

static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4014

gfx_v9_0_cp_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4015

gfx_v9_0_cp_compute_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4921

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4925

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4939

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4944

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4949

if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4958

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4963

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5029

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5037

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5080

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5084

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5128

bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5131

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5135

gfx_v9_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5137

gfx_v9_0_update_3d_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5139

gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5144

gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5146

gfx_v9_0_update_3d_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5148

gfx_v9_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5232

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5238

if (!enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5255

gfx_v9_0_update_gfx_cg_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5258

gfx_v9_0_update_gfx_mg_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5260

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5264

amdgpu_gfx_off_ctrl_immediate(adev, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7103

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7110

val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7133

static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7144

val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7156

gfx_v9_0_emit_wave_limit_cs(ring, i, enable);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1506

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1514

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1515

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1516

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1731

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1733

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2558

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2568

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2580

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2590

if (enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2602

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2607

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2667

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2671

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2714

bool enable, int xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2718

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2720

gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2721

gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2726

gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2729

gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2735

gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2738

gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2742

gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2743

gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3413

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3420

val = enable ? 0x1 : 0x7f;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3443

static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3453

val = enable ? 0x1f : 0x07ffffff;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3465

gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

421

static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

425

if (enable && !adev->gmc.prt_warning) {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

433

enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

436

enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

439

enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

442

enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

445

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

669

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

676

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

686

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

693

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

703

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

709

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

726

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

732

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

742

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

748

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

549

static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

553

if (enable && !adev->gmc.prt_warning) {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

560

CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

562

CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

564

TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

566

TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

568

L2_CACHE_STORE_INVALID_ENTRIES, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

570

L1_TLB_STORE_INVALID_ENTRIES, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

572

MASK_PDE0_FAULT, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

575

if (enable) {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

827

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

834

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

844

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

851

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

861

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

867

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

884

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

890

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

900

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

906

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1504

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1508

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1584

bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1588

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

766

static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

770

if (enable && !adev->gmc.prt_warning) {

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

777

CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

779

CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

781

TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

783

TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

785

L2_CACHE_STORE_INVALID_ENTRIES, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

787

L1_TLB_STORE_INVALID_ENTRIES, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

789

MASK_PDE0_FAULT, enable);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

792

if (enable) {

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

104

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

84

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

94

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

137

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

146

if (enable) {

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

168

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

170

hdp_v5_0_update_mem_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

171

hdp_v5_0_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

43

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

85

if (enable) {

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

140

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

149

if (enable) {

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

196

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

198

hdp_v5_2_update_mem_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

199

hdp_v5_2_update_medium_grain_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

55

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

95

if (enable) {

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

34

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

79

if (enable) {

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

31

bool enable)

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

70

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

129

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

139

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

168

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

177

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

198

static int ih_v6_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

206

r = ih_v6_0_toggle_ring_interrupts(adev, ih[i], enable);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

677

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

683

field_val = enable ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

710

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

721

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

766

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

769

ih_v6_0_update_ih_mem_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

129

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

149

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

170

static int ih_v6_1_toggle_interrupts(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

178

r = ih_v6_1_toggle_ring_interrupts(adev, ih[i], enable);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

652

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

658

field_val = enable ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

687

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

698

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

743

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

746

ih_v6_1_update_ih_mem_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

129

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

149

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

170

static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

178

r = ih_v7_0_toggle_ring_interrupts(adev, ih[i], enable);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

642

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

648

field_val = enable ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

677

bool enable)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

688

if (enable) {

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

733

bool enable = (state == AMD_PG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

736

ih_v7_0_update_ih_mem_power_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

709

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

711

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

561

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

568

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

501

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

503

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

661

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

663

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1009

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1013

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

689

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

696

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

587

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

589

if (enable) {

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

700

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

704

if (!enable)

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

105

bool enable)

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

113

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

105

bool enable)

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

113

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

943

static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

948

if (enable) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1083

static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1088

if (enable) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

860

struct amdgpu_mes *mes, bool enable)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

874

data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

351

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

359

enable, 0);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

499

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

511

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

562

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

568

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

482

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

491

if (enable) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

536

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

542

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

567

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

586

if (enable) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

624

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

642

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

494

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

501

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

528

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

536

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

544

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

557

if (enable) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

605

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

611

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

526

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

532

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

542

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

548

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

532

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

538

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

674

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

680

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

690

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

696

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

539

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

551

if (enable) {

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

584

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

591

if (enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

591

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

602

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

616

if (enable &&

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

648

bool enable)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

658

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

154

bool enable)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

162

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

166

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

175

if (enable) {

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

196

static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

204

r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

647

bool enable)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

653

field_val = enable ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

156

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

159

BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

164

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

168

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

244

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

250

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

51

static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

53

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

156

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

159

enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

163

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

167

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

229

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

237

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

258

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

266

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

348

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

354

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

93

static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

95

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

152

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

155

BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

159

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

163

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

239

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

243

if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

247

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

268

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

272

if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

277

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

49

static void nbio_v4_3_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

51

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

107

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

109

WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

113

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

117

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

164

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

169

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

192

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

197

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

73

static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

75

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

105

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

107

WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

111

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

148

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

155

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

166

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

177

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

187

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

192

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

53

static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

55

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

137

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

144

BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

150

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

154

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

289

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

297

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

318

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

326

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

335

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

49

static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

51

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

151

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

157

BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

163

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

167

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

234

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

239

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

260

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

269

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

279

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

292

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

78

static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

84

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

92

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

124

static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

126

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

209

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

211

WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

215

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

219

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

249

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

255

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

260

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

644

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

648

DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

651

DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

108

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

114

BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

120

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

124

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

258

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

266

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

287

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

295

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

304

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

49

static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

51

if (enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

233

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

238

BIF_DOORBELL_APER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

242

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

246

if (enable) {

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

308

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

313

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

387

bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

390

DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

59

static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

61

if (enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

373

static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

378

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

385

if (enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1425

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1430

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1464

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1469

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

549

static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

580

if (enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

610

static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

615

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

622

if (enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1013

AUTO_CTXSW_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1014

if (enable && amdgpu_sdma_phase_quantum) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1029

WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1044

static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1049

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1050

sdma_v4_0_gfx_enable(adev, enable);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1058

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1252

sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1256

if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2237

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2242

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2276

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2281

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

922

static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

929

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

932

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

981

static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1942

struct amdgpu_device *adev, bool enable, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1951

if (enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1971

struct amdgpu_device *adev, bool enable, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1980

if (enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

576

bool enable, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

608

AUTO_CTXSW_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

609

if (enable && amdgpu_sdma_phase_quantum) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

630

static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

636

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

653

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1762

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1768

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1799

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1805

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

598

static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

631

AUTO_CTXSW_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

634

if (enable && amdgpu_sdma_phase_quantum) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

656

static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

663

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

673

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1724

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1734

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1761

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1772

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

448

static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

478

if (enable && amdgpu_sdma_phase_quantum) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

490

AUTO_CTXSW_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

505

static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

512

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

520

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1431

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1439

if (enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

429

static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

438

CTXEMPTY_INT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

452

static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

457

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

467

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1387

bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1395

if (enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

433

static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

445

static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

450

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

460

mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

653

bool enable;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

656

enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/si_dma.c

658

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

524

u32 status, enable, en_stat;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

530

enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

539

status, enable, en_stat);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

76

static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

81

WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

83

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

38

static void smuio_v11_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

51

if (enable)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

38

static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

48

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

40

static void smuio_v13_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

50

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

38

static void smuio_v9_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

48

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))

sys/dev/pci/drm/amd/amdgpu/soc15.c

1373

static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1379

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))

sys/dev/pci/drm/amd/amdgpu/soc15.c

1402

static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1408

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

596

bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

600

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

146

bool enable);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

610

bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

614

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

48

bool enable);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

633

static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

646

if (enable) {

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

768

bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

772

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

797

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

799

if (enable) {

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1283

static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1304

if (enable) {

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1430

bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1434

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1459

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1461

if (enable) {

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

54

bool enable);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

642

bool enable)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

648

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

389

static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

392

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

767

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

781

if (!enable) {

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

795

vce_v3_0_set_vce_sw_clock_gating(adev, enable);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1447

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1449

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1401

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1406

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1986

bool enable = (state == AMD_CG_STATE_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1995

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2231

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2239

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2091

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2100

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1731

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1737

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1594

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1603

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1315

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1324

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1431

bool enable = state == AMD_CG_STATE_GATE;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1437

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

106

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

110

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

120

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

141

static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

149

r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

578

bool enable)

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

584

field_val = enable ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

98

bool enable)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

106

bool enable)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

114

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

117

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

146

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

156

if (enable) {

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

177

static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

185

r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

678

bool enable)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

684

field_val = enable ? 0 : 1;

sys/dev/pci/drm/amd/amdgpu/vi.c

1279

bool enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1288

if (enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1744

bool enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1750

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/amd/amdgpu/vi.c

1764

bool enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1770

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))

sys/dev/pci/drm/amd/amdgpu/vi.c

1780

bool enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1786

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/amd/amdgpu/vi.c

1796

bool enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1802

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))

sys/dev/pci/drm/amd/amdgpu/vi.c

1813

bool enable)

sys/dev/pci/drm/amd/amdgpu/vi.c

1819

if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

100

static void vpe_v6_1_set_collaborate_mode(struct amdgpu_vpe *vpe, bool enable)

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

111

COLLABORATE_MODE_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

116

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

118

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_EN, enable ? 1 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3009

args->enable.dbg_fd,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3010

(void __user *)args->enable.rinfo_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3011

&args->enable.rinfo_size);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3013

target->exception_enable_mask = args->enable.exception_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

299

static int kfd_dbg_set_queue_workaround(struct queue *q, bool enable)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

310

if (enable && q->properties.is_user_cu_masked)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

313

minfo.update_flag = enable ? UPDATE_FLAG_DBG_WA_ENABLE : UPDATE_FLAG_DBG_WA_DISABLE;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

315

q->properties.is_dbg_wa = enable;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

323

static int kfd_dbg_set_workaround(struct kfd_process *target, bool enable)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

330

r = kfd_dbg_set_queue_workaround(pqn->q, enable);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

331

if (enable && r)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

341

if (enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10257

new_crtc_state->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10539

old_crtc_state->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10547

new_crtc_state->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10834

if (acrtc->dm_irq_params.window_param[cnt].enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11200

bool enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11229

if (connector && enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11310

new_crtc_state->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11318

if (!enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11425

if (!(enable && connector && new_crtc_state->active))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11701

bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11707

if (!enable || !new_plane_crtc ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11731

bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11736

if (!enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11762

bool enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11784

enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11788

new_plane_state, enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11799

if (!enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11917

if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11919

new_plane_state, enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12338

if (!new_crtc_state->enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2059

adev->dm.dc->debug.fams2_config.bits.enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2240

adev->dm.idle_workqueue->enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3031

struct dc_state *state, bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3044

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3047

enable ? "enable" : "disable");

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3050

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3061

enable ? "en" : "dis");

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3068

if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3069

drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis");

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9233

old_crtc_state->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9241

new_crtc_state->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9596

if (!position.enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9827

bundle->plane_infos[planes_count].dcc.enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

143

bool enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

156

bool enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

313

acrtc->dm_irq_params.window_param[i].enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

503

bool enable = amdgpu_dm_is_valid_crc_source(source);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

519

stream_state, NULL, enable, enable, 0, true)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

556

bool enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

591

enable = amdgpu_dm_is_valid_crc_source(source);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

658

if (!enabled && enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

674

if (!enabled && enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

682

} else if (enabled && !enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

832

crtc_ctx->roi[i].enable = acrtc->dm_irq_params.window_param[i].enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

834

if (!acrtc->dm_irq_params.window_param[i].enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

904

if (!crtc_ctx->roi[i].enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

83

bool enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

161

dm->idle_workqueue->enable &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

202

while (idle_work->enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

221

if (idle_work->enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

239

idle_work->enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

254

if (vblank_work->enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

274

vblank_work, vblank_work->enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

290

static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

300

if (enable && !acrtc->base.enabled) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

309

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

331

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

345

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

364

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

378

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

402

work->enable = enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

677

if (crtc_state->enable &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

77

int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

89

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

92

acrtc->crtc_id, enable ? "en" : "dis", rc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h

36

int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2683

seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2885

bool enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2892

ret = kstrtobool_from_user(buf, size, &enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2898

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3734

acrtc->dm_irq_params.window_param[0].enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1172

bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1179

ret = dc_interrupt_set(ctx->dc, irq_source, enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1182

enable ? "en" : "dis", ret);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1354

void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1359

adev->dm.idle_workqueue->enable = enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1360

if (enable && !adev->dm.idle_workqueue->running && amdgpu_dm_is_headless(adev))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

177

bool enable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

191

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

270

bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

291

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

310

fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

792

bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

799

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

809

ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

818

ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

829

bool enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

839

uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

840

uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

855

if (enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1423

if (new_crtc_state->enable && new_crtc_state->active) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1327

position->enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1363

if (!position.enable) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

277

if (!dcc->enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

331

dcc->enable = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

382

dcc->enable = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h

43

bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

170

__field(bool, enable)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

192

__entry->enable = state->enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

218

__entry->color_mgmt_changed, __entry->enable, __entry->active,

sys/dev/pci/drm/amd/display/dc/basics/calcs_logger.h

388

DC_LOG_BANDWIDTH_CALCS(" [bool] enable[%d]:%d", i, data->enable[i]);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1002

if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1088

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1106

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1127

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1133

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1146

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1177

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1206

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1289

if (data->enable[k]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1295

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1310

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1329

if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1375

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1390

if (data->enable[k]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1425

if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1434

if (data->enable[k]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1447

if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1449

if ((i == j || data->display_synchronization_enabled) && (data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1482

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1490

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1504

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1664

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1714

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1726

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1799

if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1821

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1838

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1855

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1862

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1897

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1934

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1944

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1972

if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

1996

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2017

if (data->enable[k]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

214

data->enable[0] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

215

data->enable[1] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

218

data->enable[0] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

219

data->enable[1] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

224

data->enable[0] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

225

data->enable[1] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

230

data->enable[2] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

231

data->enable[3] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

234

data->enable[2] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

235

data->enable[3] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

240

data->enable[2] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

241

data->enable[3] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

307

data->enable[i] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

311

data->enable[i] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

315

data->enable[i] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

319

data->enable[i] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

323

data->enable[i] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

327

data->enable[i] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

332

data->enable[i] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

365

data->enable[maximum_number_of_surfaces - 2] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

366

data->enable[maximum_number_of_surfaces - 1] = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

369

data->enable[maximum_number_of_surfaces - 2] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

370

data->enable[maximum_number_of_surfaces - 1] = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

432

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

518

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

538

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

553

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

587

if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

593

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

645

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

802

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

873

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

886

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

942

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

957

if (data->enable[i] && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

962

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

972

if (data->enable[i]) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

790

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

798

bp, bp_params, enable);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

831

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

838

return bp->cmd_tbl.enable_crtc(bp, id, enable);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1676

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1683

return bp->cmd_tbl.enable_crtc(bp, id, enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1286

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1290

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1294

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1322

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1329

if ((enable == true) && (bp_params->percentage > 0))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1366

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1380

if ((enable == true) && (bp_params->percentage > 0)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1418

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1450

if (enable == true) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1622

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1627

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1653

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1658

if (enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1671

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1680

enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1692

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1701

enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1720

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1723

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1746

struct bios_parser *bp, bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1751

if (enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1763

struct bios_parser *bp, bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1768

if (enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1988

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2007

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2018

if (enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2040

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2057

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2066

if (enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

51

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

57

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

62

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

67

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

70

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

77

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

81

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

707

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

724

bool enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

735

if (enable)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

736

params.enable = ATOM_ENABLE;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

738

params.enable = ATOM_DISABLE;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

859

ps.param.enable =

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

51

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

57

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

62

bool enable,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

67

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

70

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

77

bool enable);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

81

bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

234

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

239

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

38

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

312

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

315

uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

318

enable, cache_timer_delay, cache_timer_scale);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

324

void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

326

smu_print("SMU Set external client df cstate allow: enable = %d\n", enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

329

DALSMC_MSG_SetExternalClientDfCstateAllow, enable ? 1 : 0, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

47

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

48

void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

230

void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

234

if (enable) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

239

DC_LOG_DEBUG("%s(%d)\n", __func__, enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

157

void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

255

void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

262

if (enable) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

350

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

358

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

261

void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

269

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

274

void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

281

if (enable) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

389

void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

397

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

100

void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

108

void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

268

void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

275

if (enable) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

357

void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

365

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

120

void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

129

void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

243

void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

250

if (enable) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

309

void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

317

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

128

void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

135

void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

161

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

163

smu_print("FCLK P-state support value is : %d\n", enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

166

DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

303

void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

305

smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

307

dcn32_smu_send_msg_with_param(clk_mgr, 0x14, enable ? 1 : 0, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

39

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

44

void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

294

void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

301

if (enable) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

310

smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

445

void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

453

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

454

smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

457

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

465

enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

466

smu_print("%s: smu_enable_48mhz_tmdp_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

203

void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

211

void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

212

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1053

block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

726

params->update_wait_for_dmub_ack_params.enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

877

block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

48

bool enable;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

321

void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

323

smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

325

dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetAlwaysWaitDmcubResp, enable ? 1 : 0, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

24

void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2582

bool dc_set_generic_gpio_for_stereo(bool enable,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2612

config->enable_output_from_mux = enable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2691

if (u->plane_info->dcc.enable != u->surface->dcc.enable

sys/dev/pci/drm/amd/display/dc/core/dc.c

3958

if (dc->debug.fams2_config.bits.enable &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

5416

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5422

return dal_irq_service_set(dc->res_pool->irqs, src, enable);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5511

bool dc_set_psr_allow_active(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5525

if (enable && !link->psr_settings.psr_allow_active) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5529

} else if (!enable && link->psr_settings.psr_allow_active) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5733

void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5749

if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5759

} else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5770

dc->clk_mgr->dc_mode_softmax_enabled = enable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6087

cmd.dpia_hpd_int_enable.enable = hpd_int_enable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6125

void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6166

pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

640

cmd.secure_display.mul_roi_ctl.roi_ctl[i].enable = window[i].enable;

sys/dev/pci/drm/amd/display/dc/core/dc.c

699

struct crc_params *crc_window, bool enable, bool continuous,

sys/dev/pci/drm/amd/display/dc/core/dc.c

742

param.enable = enable;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

572

if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

590

if (!pipe_ctx->plane_state->dcc.enable) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

711

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

514

void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

516

link->dc->link_srv->enable_hpd_filter(link, enable);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

1060

!stream->cursor_position.enable ||

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

980

is_fams2_in_use |= state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

983

is_fams2_in_use |= dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1233

!stream->cursor_position.enable ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

438

(!old_position->enable || dc->debug.exit_idle_opt_for_cursor_updates) &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

439

position->enable) {

sys/dev/pci/drm/amd/display/dc/dc.h

1899

bool dc_set_generic_gpio_for_stereo(bool enable,

sys/dev/pci/drm/amd/display/dc/dc.h

2060

void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2402

bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,

sys/dev/pci/drm/amd/display/dc/dc.h

2422

bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,

sys/dev/pci/drm/amd/display/dc/dc.h

2612

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2617

void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2660

void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

2668

bool dc_set_psr_allow_active(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/dc.h

710

bool enable;

sys/dev/pci/drm/amd/display/dc/dc.h

727

unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \

sys/dev/pci/drm/amd/display/dc/dc.h

731

if (dc->debug.bw_val_profile.enable) \

sys/dev/pci/drm/amd/display/dc/dc.h

735

if (dc->debug.bw_val_profile.enable) { \

sys/dev/pci/drm/amd/display/dc/dc.h

742

if (dc->debug.bw_val_profile.enable) \

sys/dev/pci/drm/amd/display/dc/dc.h

746

if (dc->debug.bw_val_profile.enable) \

sys/dev/pci/drm/amd/display/dc/dc.h

750

if (dc->debug.bw_val_profile.enable) { \

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

103

bool enable);

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

116

bool enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1046

payload->enable = hubp->pos.cur_ctl.bits.cur_enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1693

bool enable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1707

if (enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1745

global_cmd->config.global.features.bits.enable = enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1747

if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1759

bool enable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1774

if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1799

config->global.features.bits.enable = enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1806

bool enable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1809

dc_dmub_srv_rb_based_fams2_update_config(dc, context, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1811

dc_dmub_srv_ib_based_fams2_update_config(dc, context, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

371

void dc_dmub_trace_event_control(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

373

dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

872

bool enable)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

900

if (enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

198

bool enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

84

void dc_dmub_trace_event_control(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

99

void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

114

void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

154

bool enable;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

487

bool enable;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

154

spl_in->adaptive_sharpness.enable = false;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

156

spl_in->adaptive_sharpness.enable = true;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

173

spl_in->adaptive_sharpness.enable = true;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

176

spl_in->adaptive_sharpness.enable = false;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

179

spl_in->adaptive_sharpness.enable = true;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

556

bool enable,

sys/dev/pci/drm/amd/display/dc/dc_types.h

969

bool enable;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

330

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

340

SYMCLK32_LE0_GATE_DISABLE, enable ? 1 : 0,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

341

SYMCLK32_ROOT_LE0_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

345

SYMCLK32_LE1_GATE_DISABLE, enable ? 1 : 0,

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

346

SYMCLK32_ROOT_LE1_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

191

bool enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1119

uint32_t dpp_inst, uint32_t enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1126

REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1129

REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1132

REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1135

REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1140

DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1493

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1500

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1501

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1506

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1507

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1512

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1513

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1518

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1519

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1527

__func__, dp_hpo_inst, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1535

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1545

PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1549

PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1553

PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1557

PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1561

PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1567

DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE: %d\n", __func__, phy_inst, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

170

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

174

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

182

SYMCLK32_SE0_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

183

SYMCLK32_ROOT_SE0_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

187

SYMCLK32_SE1_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

188

SYMCLK32_ROOT_SE1_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

192

SYMCLK32_SE2_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

193

SYMCLK32_ROOT_SE2_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

197

SYMCLK32_SE3_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

198

SYMCLK32_ROOT_SE3_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

209

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

213

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

219

SYMCLK32_LE0_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

220

SYMCLK32_ROOT_LE0_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

224

SYMCLK32_LE1_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

225

SYMCLK32_ROOT_LE1_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

236

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

240

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

246

PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

250

PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

254

PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

258

PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

262

PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

273

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

277

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

283

SYMCLKA_FE_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

285

SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

289

SYMCLKB_FE_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

291

SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

295

SYMCLKC_FE_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

297

SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

301

SYMCLKD_FE_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

303

SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

307

SYMCLKE_FE_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

309

SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

320

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

326

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

332

SYMCLKA_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

334

SYMCLKA_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

338

SYMCLKB_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

340

SYMCLKB_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

344

SYMCLKC_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

346

SYMCLKC_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

350

SYMCLKD_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

352

SYMCLKD_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

356

SYMCLKE_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

358

SYMCLKE_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

366

static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

371

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

376

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

379

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

382

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

385

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

426

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

430

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

436

DPSTREAMCLK0_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

437

DPSTREAMCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

441

DPSTREAMCLK1_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

442

DPSTREAMCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

446

DPSTREAMCLK2_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

447

DPSTREAMCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

451

DPSTREAMCLK3_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

452

DPSTREAMCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

463

bool enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

467

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

473

SYMCLK32_SE0_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

474

SYMCLK32_ROOT_SE0_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

478

SYMCLK32_SE1_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

479

SYMCLK32_ROOT_SE1_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

483

SYMCLK32_SE2_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

484

SYMCLK32_ROOT_SE2_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

488

SYMCLK32_SE3_GATE_DISABLE, enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

489

SYMCLK32_ROOT_SE3_GATE_DISABLE, enable ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

849

uint32_t enable = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

855

SYMCLKA_FE_ROOT_GATE_DISABLE, &enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

859

SYMCLKB_FE_ROOT_GATE_DISABLE, &enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

863

SYMCLKC_FE_ROOT_GATE_DISABLE, &enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

867

SYMCLKD_FE_ROOT_GATE_DISABLE, &enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

871

SYMCLKE_FE_ROOT_GATE_DISABLE, &enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

877

return enable;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

56

uint32_t dpp_inst, uint32_t enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

596

bool enable = false;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

613

enable = true;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

62

REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

65

REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

68

REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

693

DP_DTO_ENABLE[params->otg_inst], enable,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

694

PIPE_DTO_SRC_SEL[params->otg_inst], enable);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

71

REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

129

static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

144

if (enable)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

156

if (enable) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

546

static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

565

if (enable)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

582

if (enable) {

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

53

REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

136

bool enable)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

141

REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

775

uint32_t enable = (total_stream_num > 1) ? 0 :

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

779

ENABLE, enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

805

uint32_t enable = (total_stream_num > 1) ? 0 :

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

809

ENABLE, enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1014

bool enable)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1017

unsigned int value = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1377

bool enable)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1384

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1488

int tg_inst, bool enable)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1492

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

198

cmd.abm_pause.abm_pause_data.enable = pause;

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.c

49

cmd.outbox1_enable.enable = true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

179

static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

192

if (enable)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

209

if (enable) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.h

42

void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait,

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

356

cmd.replay_set_frameupdate_timer.data.enable =

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

357

cmd_element->timer_data.enable;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

47

static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

59

if (enable)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

60

cmd.replay_enable.data.enable = REPLAY_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

62

cmd.replay_enable.data.enable = REPLAY_DISABLE;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

76

if (enable) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h

21

void (*replay_enable)(struct dmub_replay *dmub, bool enable, bool wait,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

647

enable(mem_input110);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1411

bool enable,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1418

if (enable) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2130

if (!params->enable || params->reset)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2134

if (!params->enable)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

246

bool enable,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

385

bool enable,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

391

if (enable) {

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1103

if (!params->enable || params->reset)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1108

if (!params->enable)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

623

bool enable,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

637

enable ? 0 : 1,

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

126

bool enable,

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

126

bool enable,

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

133

if (enable) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

105

.enable = dwb1_enable,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

317

.enable = dwb2_enable,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c

45

bool enable,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c

52

MPC_OUT_RATE_CONTROL_DISABLE, !enable,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c

75

mpcc->sm_cfg.enable = false;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

107

bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

112

REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1033

bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1036

unsigned int value = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1367

bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1374

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1482

int tg_inst, bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1486

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

687

int tg_inst, bool enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

691

bool enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

730

bool enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

173

void enc2_fec_set_enable(struct link_encoder *enc, bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

177

enable ? "Enabling" : "Disabling", enc->id.enum_id);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

178

REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

340

void enc2_fec_set_enable(struct link_encoder *enc, bool enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

297

bool enable,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

303

if (enable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

320

bool enable,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

326

if (enable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

323

bool enable,

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

311

bool enable,

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

126

void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

130

REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

235

bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

239

if (enable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

321

bool enable,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

400

bool enable)

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

403

if (enable) {

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

228

bool enable);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

167

bool enable

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

194

void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

198

bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

82

bool enable);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

323

input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

993

v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1646

pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

146

timing->dsc.enable = dml2_dsc_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

150

timing->dsc.enable = dml2_dsc_disable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

17

bool disable_fams2 = !in_dc->debug.fams2_config.bits.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

376

surface->dcc.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

427

plane->dynamic_meta_data.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

442

surface->dcc.enable = plane_state->dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

626

plane->dynamic_meta_data.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

743

dml_dispcfg->overrides.hw.force_unbounded_requesting.enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

510

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

182

bool enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

257

enum dml2_dsc_enable_option enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

355

bool enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

398

bool enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

451

bool enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

456

bool enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

183

phantom->dynamic_meta_data.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

207

svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10070

if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10479

display_cfg->overrides.hw.force_nom_det_size_kbytes.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10685

s->SurfaceParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10790

calculate_mcache_setting_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10890

if (display_cfg->plane_descriptors[k].surface.dcc.enable)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11204

myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11228

CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11258

CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11521

mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11625

display_cfg->plane_descriptors[k].surface.dcc.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11840

if (!display_cfg->plane_descriptors[k].dynamic_meta_data.enable)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11856

if (display_cfg->plane_descriptors[k].dynamic_meta_data.enable && mode_lib->ip.dynamic_metadata_vm_enabled) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12735

fams2_global_config->features.bits.enable = display_cfg->stage3.fams2_required;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12737

if (fams2_global_config->features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

161

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

177

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

183

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3084

if (p->display_cfg->plane_descriptors[k].overrides.hw.force_pte_buffer_mode.enable == 1) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3771

*p->UnboundedRequestEnabled = UnboundedRequest(p->display_cfg->overrides.hw.force_unbounded_requesting.enable, p->display_cfg->overrides.hw.force_unbounded_requesting.value, TotalActiveDPP, NoChromaOrLinear);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3932

&& p->display_cfg->plane_descriptors[k].surface.dcc.enable

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4753

if (display_cfg->plane_descriptors[k].surface.dcc.enable)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6979

if (p->display_cfg->plane_descriptors[plane_index].surface.dcc.enable && p->mrq_present) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7436

myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7461

CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7491

CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7790

mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7991

display_cfg->overrides.hw.force_nom_det_size_kbytes.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8172

} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelY[k] == 8 && display_cfg->plane_descriptors[k].surface.dcc.enable == true) { // vert 64bpp

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8260

if (mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8365

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8366

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8443

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8658

if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8876

if (display_cfg->plane_descriptors[k].surface.dcc.enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8897

s->SurfParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9318

calculate_mcache_setting_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9750

if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true && p->mrq_present) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9947

bool dcc_mrq_enable = display_cfg->plane_descriptors[k].surface.dcc.enable && mrq_present;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

339

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

355

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

362

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

602

phantom->dynamic_meta_data.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

626

svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1095

if (plane_descriptor->surface.dcc.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1112

if (plane_descriptor->surface.dcc.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

1034

if (params->mcache_configurations[config_index].plane_descriptor->surface.dcc.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

532

if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

744

if (!params->display_config->plane_descriptors[i].surface.dcc.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

86

if (pipe->plane_state->dcc.enable)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

919

out->DCCEnable[location] = in->dcc.enable;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

450

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

508

bool enable)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

512

if (enable) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1508

bool enable);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

592

uint32_t enable, uint32_t additive_blending);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

641

uint32_t enable, uint32_t additive_blending);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

147

uint32_t enable, uint32_t additive_blending)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

152

CM_DEALPHA_EN, enable,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

146

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

148

REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

43

bool enable)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

47

if (enable) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

55

bool enable);

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

62

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

132

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

962

ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1437

void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1439

dsc_policy_enable_dsc_when_not_needed = enable;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

109

void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

111

REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h

57

void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

390

void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

392

REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

335

void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

133

void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable)

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

145

REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, enable);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

247

.enable = dwb3_enable,

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

892

void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

54

void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable)

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

56

REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h

59

void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

550

bool enable,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

556

if (enable) {

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

107

uint32_t enable = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

110

DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

112

return enable ? true : false;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

512

static void hubbub35_set_fgcg(struct dcn20_hubbub *hubbub2, bool enable)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

514

REG_UPDATE(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1212

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1298

void hubp1_clk_cntl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1301

uint32_t clk_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

190

if (!dcc->enable) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

535

void hubp1_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

538

uint32_t dcc_en = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

565

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

770

bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

797

void hubp1_clk_cntl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1002

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1109

void hubp2_clk_cntl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1112

uint32_t clk_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

360

if (!dcc->enable) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

423

void hubp2_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

426

uint32_t dcc_en = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

562

hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

891

bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

899

if (tri_buffer_en != enable) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

901

SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

916

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

920

REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

347

bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

352

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

364

void hubp2_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

402

void hubp2_clk_cntl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

52

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

353

void hubp3_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

356

uint32_t dcc_en = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

372

PRIMARY_SURFACE_DCC_EN, dcc->enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

375

SECONDARY_SURFACE_DCC_EN, dcc->enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

287

void hubp3_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

42

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

46

REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

246

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

68

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

71

REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

83

REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

53

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

41

void hubp35_set_fgcg(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

45

REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

59

void hubp35_set_fgcg(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1014

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1018

REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

578

PRIMARY_SURFACE_DCC_EN, dcc->enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

579

SECONDARY_SURFACE_DCC_EN, dcc->enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

59

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

63

REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

743

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

329

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

344

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

164

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

166

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

41

unsigned int fe_inst, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

44

DCFE_CLOCK_ENABLE, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1280

unsigned int inst, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1296

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1043

if (enable && link->dpcd_sink_ext_caps.bits.oled &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1053

ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1070

if (!enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1267

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1270

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3153

pos_cpy.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3156

pos_cpy.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

951

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

970

if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

982

__func__, (enable ? "On":"Off"));

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

984

cntl.action = enable ?

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

61

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

84

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3746

pos_cpy.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3748

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3749

pos_cpy.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

832

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

836

if (enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

103

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

160

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

174

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1524

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1551

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1558

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1695

if (pipe_ctx->update_flags.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1738

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1801

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1813

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1829

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1855

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1870

if (pipe_ctx->update_flags.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1936

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1952

if (pipe_ctx->update_flags.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1977

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1985

pipe_ctx->update_flags.bits.enable))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1992

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2002

if (pipe_ctx->update_flags.bits.enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

220

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

227

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2273

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2560

dwb->funcs->enable(dwb, &wb_info->dwb_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

292

pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

309

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3109

bool enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3118

enable = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3127

stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

314

if (enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

101

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

156

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

548

dwb->funcs->enable(dwb, &wb_info->dwb_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

830

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

838

enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

841

if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

887

bool enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

896

enable = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

905

stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

909

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

921

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

951

cursor_cache_enable = stream->cursor_position.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

71

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

81

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

61

void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

35

void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

347

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

352

if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

366

if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

660

void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

663

REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

42

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

59

void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

295

void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

300

if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

314

if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

72

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

83

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

38

void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1002

dc->debug.fams2_config.bits.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1013

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1037

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

135

bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

140

if (enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1465

phantom_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

252

bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

273

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

dc->debug.fams2_config.bits.enable &= true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

40

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

44

bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

46

void dcn32_cab_for_ss_control(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

74

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

124

void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

127

RBBMIF_FGCG_REP_DIS, !enable,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

128

IHC_FGCG_REP_DIS, !enable,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

129

LONO_FGCG_REP_DIS, !enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

133

void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

135

REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

327

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

340

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

563

bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

568

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

605

dc_dmub_srv_apply_idle_power_optimizations(dc, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

44

void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

46

void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

56

bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

85

void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1005

void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1007

REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1200

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1201

pos_cpy.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1210

pos_cpy.enable = false; /* not visible beyond right edge*/

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1213

pos_cpy.enable = false; /* not visible beyond bottom edge*/

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1216

pos_cpy.enable = false; /* not visible beyond left edge*/

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1219

pos_cpy.enable = false; /* not visible beyond top edge*/

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1271

bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1295

if (enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1354

pipe_ctx->plane_state->dcc.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1415

if (dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1436

if (dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1485

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1511

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1515

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1518

fams2_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1520

dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_required);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1637

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1645

dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1659

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1991

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2007

if (pipe_ctx->update_flags.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2031

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2039

pipe_ctx->update_flags.bits.enable))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2046

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2056

if (pipe_ctx->update_flags.bits.enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2295

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2494

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2521

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2528

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

360

dc->debug.fams2_config.bits.enable &=

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

56

void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

64

bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

79

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

213

void (*edp_power_control)(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

244

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

299

void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

398

bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

460

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

465

void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

105

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

117

bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

162

void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

403

uint32_t enable : 1;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

368

bool enable[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

112

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

141

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

152

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h

65

void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

220

uint32_t enable, uint32_t additive_blending);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

329

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h

180

bool (*enable)(

sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h

195

enum dwb_frame_capture_enable enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

179

void (*dcc_control)(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

236

void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

255

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

262

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

272

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

281

void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

298

void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

153

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

112

void (*dcc_control)(struct mem_input *mem_input, bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1097

void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

240

bool enable;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

828

bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

330

bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

335

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

147

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

172

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

174

void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

218

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

221

struct stream_encoder *enc, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

230

bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

252

bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

257

bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

336

bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

143

bool enable;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

274

bool enable, const struct dc_crtc_timing *timing);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

294

void (*enable_optc_clock)(struct timing_generator *tg, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

299

void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

381

void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

84

int enable;

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

122

void (*enable_hpd_filter)(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

167

void (*set_dsc_on_stream)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

168

bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

287

const bool *enable, bool wait, bool force_static,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

305

bool (*edp_backlight_enable_aux)(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

309

bool (*edp_power_alpm_dpcd_enable)(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

184

bool enable)

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

204

bool enable)

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

221

if (enable) {

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

228

dal_irq_service_set_generic(irq_service, info, enable);

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h

42

bool enable);

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h

51

bool enable);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

104

(info->enable_value[enable ? 0 : 1] & info->enable_mask);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

111

bool enable)

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

128

source, enable);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

132

return info->funcs->set(irq_service, info, enable);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

135

dal_irq_service_set_generic(irq_service, info, enable);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

98

bool enable)

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

40

bool enable);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

83

bool enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1010

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1020

if (enable) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

727

static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

734

dc->hwss.set_avmute(pipe_ctx, enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

737

static void enable_mst_on_sink(struct dc_link *link, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

742

if (enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

772

static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

781

result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

802

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

829

if (enable) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

946

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

959

if (enable) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

46

bool enable, bool immediate_update);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

50

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

51

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

180

void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

190

if (enable && dp_should_enable_fec(link)) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.h

56

const struct link_resource *link_res, bool enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1239

struct link_resource *link_res, bool enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1259

if (enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1266

cmd.assr_enable.assr_data.enable = enable;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1276

enum dp_panel_mode *panel_mode, bool enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1285

edp_set_assr_enable(link->dc, link, link_res, enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1286

} else if (cp_psp && cp_psp->funcs.enable_assr && enable) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

269

bool edp_backlight_enable_aux(struct dc_link *link, bool enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

271

uint8_t backlight_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

515

bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

523

alpm_config.bits.ENABLE = (enable ? true : false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

55

bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

73

bool edp_backlight_enable_aux(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

77

bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

80

enum dp_panel_mode *panel_mode, bool enable);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

63

void link_enable_hpd_filter(struct dc_link *link, bool enable)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

67

if (enable) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h

53

void link_enable_hpd_filter(struct dc_link *link, bool enable);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

102

MPCC_SM_EN, sm_cfg->enable,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

344

mpcc->sm_cfg.enable = false;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

522

mpcc->sm_cfg.enable = false;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1062

mpcc->sm_cfg.enable = false;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

116

bool enable,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1091

bool enable,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

325

bool enable,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

335

if (!enable) {

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

367

void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

370

uint32_t regval = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

184

bool enable,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

187

void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

50

void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable)

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

52

REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

65

void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1475

if (!params->enable || params->reset)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1478

if (!params->enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

390

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

394

uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

411

void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

414

uint32_t mode = enable ? 2 : 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

482

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

486

if (enable) {

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

327

static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

330

uint32_t mode = enable ? 2 : 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

356

void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

192

if (!params->enable || params->reset)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

195

if (!params->enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

534

void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

536

REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

79

void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

323

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

388

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

438

void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable)

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

445

OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, enable);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

194

void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1189

if (!plane->dcc.enable)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1356

plane_state->dcc.enable = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1844

stream->cursor_position.enable &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

67

if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1665

stream->cursor_position.enable &&

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

732

.enable = true,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1686

dscl_prog_data->isharp_noise_det.enable = 1; /* ISHARP_NOISEDET_EN */

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1689

dscl_prog_data->isharp_noise_det.enable = 0; // ISHARP_NOISEDET_EN

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

853

if (spl_in->adaptive_sharpness.enable == false)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

223

uint32_t enable; // ISHARP_NOISEDET_EN

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

501

bool enable;

sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c

104

bool enable,

sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c

61

bool enable) {}

sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c

99

bool enable)

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

502

void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

509

void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2350

uint32_t enable: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2734

uint32_t enable; /* dpia hpd interrupt enable */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2853

uint32_t enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3785

uint8_t enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4249

uint8_t enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4519

uint8_t enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5312

uint8_t enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5930

bool enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5965

uint8_t enable;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

627

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

629

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

656

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

658

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

281

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

287

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/include/irq_service_interface.h

40

bool enable);

sys/dev/pci/drm/amd/include/atomfirmware.h

4148

uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE

sys/dev/pci/drm/amd/include/atomfirmware.h

4159

uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

415

void (*enable_bapm)(void *handle, bool enable);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

591

void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

597

if (enable) {

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

609

ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

612

enable ? "enable" : "disable", ret);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

615

void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

619

ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

622

enable ? "enable" : "disable", ret);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

625

void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

631

if (enable) {

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

644

ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

647

enable ? "enable" : "disable", ret);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

650

void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

654

ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

657

enable ? "enable" : "disable", ret);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

660

void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

664

ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

667

enable ? "enable" : "disable", ret);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

694

int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

701

enable);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

447

void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

448

void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

449

void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

450

void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

451

void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

453

int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

118

static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1199

static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1201

return amdgpu_kv_notify_message_to_smu(adev, enable ?

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1236

static void kv_dpm_enable_bapm(void *handle, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1243

ret = amdgpu_kv_smc_bapm_enable(adev, enable);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

128

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1475

static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1477

return amdgpu_kv_notify_message_to_smu(adev, enable ?

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1481

static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1483

return amdgpu_kv_notify_message_to_smu(adev, enable ?

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1487

static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1489

return amdgpu_kv_notify_message_to_smu(adev, enable ?

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1493

static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1495

return amdgpu_kv_notify_message_to_smu(adev, enable ?

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1849

bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1854

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2313

u32 index, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2317

pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

449

static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

456

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

465

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

474

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

483

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

49

bool enable);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

491

static int kv_enable_didt(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

502

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

510

kv_do_enable_didt(adev, enable);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

551

static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

557

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

708

u32 index, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

712

pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

223

int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

224

int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

105

int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

107

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

113

int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

115

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2547

bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2554

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2911

bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2919

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3834

bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3838

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3861

static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3863

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4109

bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4111

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4242

static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4246

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6232

static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6234

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6465

bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6469

if (enable) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

147

void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

151

if (enable)

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

399

void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

441

static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

444

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

417

static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

419

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

28

static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

30

return smum_send_msg_to_smc(hwmgr, enable ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

36

static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

38

return smum_send_msg_to_smc(hwmgr, enable ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

424

int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

428

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h

35

int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1693

static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1698

if (enable) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

850

static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

853

uint32_t en = enable ? 1 : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

888

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1880

static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1885

if (enable &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1936

static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1941

if (enable && phm_cap_enabled(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

797

static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

802

if (enable) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2444

static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2450

if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2453

if (enable) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3009

static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3014

if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3015

pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3017

enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3020

data->smu_features[GNLD_PCC_LIMIT].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3796

int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3802

enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3806

data->smu_features[GNLD_DPM_VCE].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4990

static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4996

enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5000

data->smu_features[GNLD_DPM_UVD].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

444

int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

800

static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

803

uint32_t en = (enable ? 1 : 0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

877

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

37

static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

40

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1322

int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1329

enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1333

data->smu_features[GNLD_DPM_VCE].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2583

static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2590

enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2594

data->smu_features[GNLD_DPM_UVD].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2826

static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2828

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

455

int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

34

static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

37

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2011

static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2018

if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2019

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2026

enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2031

data->smu_features[GNLD_DPM_VCE].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3680

static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3687

if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3688

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3695

enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3700

data->smu_features[GNLD_DPM_UVD].enabled = enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

36

static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

39

if (enable)

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

317

int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

323

int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

112

bool enable, uint32_t feature_mask)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

114

int msg = enable ? PPSMC_MSG_EnableSmuFeatures :

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.h

46

bool enable, uint32_t feature_mask);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

126

bool enable, uint64_t feature_mask)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

133

if (enable) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.h

52

bool enable, uint64_t feature_mask);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

318

bool enable, uint64_t feature_mask)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

326

if (enable) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h

51

bool enable, uint64_t feature_mask);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

250

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2504

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2518

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2528

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

266

if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

269

ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

271

atomic_set(&power_gate->vcn_gated[inst], !enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

277

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

289

if (atomic_read(&power_gate->jpeg_gated) ^ enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

292

ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

294

atomic_set(&power_gate->jpeg_gated, !enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

300

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

309

if (atomic_read(&power_gate->vpe_gated) ^ enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

312

ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

314

atomic_set(&power_gate->vpe_gated, !enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

320

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

329

if (atomic_read(&power_gate->isp_gated) ^ enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

332

ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

334

atomic_set(&power_gate->isp_gated, !enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

340

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

352

if (atomic_read(&power_gate->umsch_mm_gated) ^ enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

355

ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

357

atomic_set(&power_gate->umsch_mm_gated, !enable);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3743

int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3748

ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1052

int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1204

int (*gfx_off_control)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1414

int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1479

int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1485

int (*dpm_set_isp_enable)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1491

int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1511

int (*enable_uclk_shadow)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1769

int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

802

int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

808

int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

231

int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

300

int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h

46

int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h

50

int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

202

int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

251

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

255

bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

291

int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

170

int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

214

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

218

bool enable);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1604

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1609

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1139

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1144

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1162

static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1166

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1156

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1166

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1174

static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1178

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1107

int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1124

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1705

int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1709

ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

473

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

478

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

492

static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

496

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

644

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

649

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

667

static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

671

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

121

int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

129

enable ? 1 : 0,

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

158

int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

162

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1309

static int aldebaran_system_features_control(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1313

ret = smu_v13_0_system_features_control(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1314

if (!ret && enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1997

static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2000

ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2000

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2009

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2017

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2019

return smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2455

int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2457

return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

782

int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

799

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

197

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

203

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

213

static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

217

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1993

static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2000

enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2005

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2013

if (enable) {

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2015

ret = smu_v13_0_system_features_control(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3249

static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3253

return smu_v13_0_6_mca_set_debug_mode(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3714

static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3718

return smu_v13_0_6_mca_set_debug_mode(smu, enable);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

224

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

230

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

240

static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

244

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1571

bool enable,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1582

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1586

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1590

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1599

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1610

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1614

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1618

ret = smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

767

int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

781

if (enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1545

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1547

return smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1553

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1555

return smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1561

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1563

return smu_cmn_send_smc_msg_with_param(smu, enable ?

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

778

bool enable)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

790

enable);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

150

bool enable);

sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h

101

#define smu_enable_uclk_shadow(smu, enable) smu_ppt_funcs(enable_uclk_shadow, 0, smu, enable)

sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h

48

#define smu_gfx_off_control(smu, enable) smu_ppt_funcs(gfx_off_control, 0, smu, enable)

sys/dev/pci/drm/apple/iomfb_template.c

1380

if (crtc_state->enable && crtc_state->active &&

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

362

struct i2c_adapter *adapter, bool enable)

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

364

uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE;

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

382

enable ? "enable" : "disable", retry + 1);

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

391

enable ? "enabling" : "disabling", retry + 1);

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

400

enable ? "enabling" : "disabling");

sys/dev/pci/drm/display/drm_dp_helper.c

2961

int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable)

sys/dev/pci/drm/display/drm_dp_helper.c

2963

u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :

sys/dev/pci/drm/display/drm_dp_helper.c

4006

bool enable)

sys/dev/pci/drm/display/drm_dp_helper.c

4021

if (enable)

sys/dev/pci/drm/display/drm_dp_helper.c

700

void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable)

sys/dev/pci/drm/display/drm_dp_helper.c

702

WRITE_ONCE(aux->dpcd_probe_disabled, !enable);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5490

int pbn, bool enable)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5508

if (payload->dsc_enabled == enable) {

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5511

port, enable, payload->time_slots);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5515

if (enable) {

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5524

payload->dsc_enabled = enable;

sys/dev/pci/drm/display/drm_dp_tunnel.c

912

static int set_bw_alloc_mode(struct drm_dp_tunnel *tunnel, bool enable)

sys/dev/pci/drm/display/drm_dp_tunnel.c

920

if (enable)

sys/dev/pci/drm/display/drm_dp_tunnel.c

928

tunnel->bw_alloc_enabled = enable;

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

50

bool enable, int direction)

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

57

return funcs->mute_stream(connector, enable, direction);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

21

static int drm_connector_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

26

return data->funcs->enable(connector, enable);

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

97

if (!funcs->init || !funcs->enable || !funcs->log_addr || !funcs->transmit)

sys/dev/pci/drm/display/drm_scdc_helper.c

184

bool enable)

sys/dev/pci/drm/display/drm_scdc_helper.c

197

if (enable)

sys/dev/pci/drm/drm_atomic.c

1489

if (new_crtc_state->enable)

sys/dev/pci/drm/drm_atomic.c

1541

if (new_crtc_state->enable)

sys/dev/pci/drm/drm_atomic.c

390

if (new_crtc_state->active && !new_crtc_state->enable) {

sys/dev/pci/drm/drm_atomic.c

402

WARN_ON(new_crtc_state->enable && !new_crtc_state->mode_blob)) {

sys/dev/pci/drm/drm_atomic.c

410

WARN_ON(!new_crtc_state->enable && new_crtc_state->mode_blob)) {

sys/dev/pci/drm/drm_atomic.c

444

drm_printf(p, "\tenable=%d\n", state->enable);

sys/dev/pci/drm/drm_atomic_helper.c

1283

if (new_crtc_state->enable && funcs->prepare)

sys/dev/pci/drm/drm_atomic_helper.c

1450

crtc->enabled = new_crtc_state->enable;

sys/dev/pci/drm/drm_atomic_helper.c

1477

if (new_crtc_state->enable)

sys/dev/pci/drm/drm_atomic_helper.c

1510

if (new_crtc_state->enable && funcs->mode_set_nofb) {

sys/dev/pci/drm/drm_atomic_helper.c

1684

if (new_crtc_state->enable) {

sys/dev/pci/drm/drm_atomic_helper.c

1738

else if (funcs->enable)

sys/dev/pci/drm/drm_atomic_helper.c

1739

funcs->enable(encoder);

sys/dev/pci/drm/drm_atomic_helper.c

489

if (!new_crtc_state->enable)

sys/dev/pci/drm/drm_atomic_helper.c

673

if (old_crtc_state->enable != new_crtc_state->enable) {

sys/dev/pci/drm/drm_atomic_helper.c

695

if (new_crtc_state->enable != has_connectors) {

sys/dev/pci/drm/drm_atomic_helper.c

698

new_crtc_state->enable, has_connectors);

sys/dev/pci/drm/drm_atomic_helper.c

766

new_crtc_state->enable ? 'y' : 'n',

sys/dev/pci/drm/drm_atomic_helper.c

928

if (!crtc_state->enable && !can_update_disabled) {

sys/dev/pci/drm/drm_atomic_helper.c

947

if (crtc_state->enable)

sys/dev/pci/drm/drm_atomic_uapi.c

100

state->enable = false;

sys/dev/pci/drm/drm_atomic_uapi.c

159

state->enable = true;

sys/dev/pci/drm/drm_atomic_uapi.c

165

state->enable = false;

sys/dev/pci/drm/drm_atomic_uapi.c

94

state->enable = true;

sys/dev/pci/drm/drm_bridge.c

916

} else if (bridge->funcs->enable) {

sys/dev/pci/drm/drm_bridge.c

917

bridge->funcs->enable(bridge);

sys/dev/pci/drm/drm_client_modeset.c

232

bool enable;

sys/dev/pci/drm/drm_client_modeset.c

238

enable = connector->status == connector_status_connected;

sys/dev/pci/drm/drm_client_modeset.c

240

enable = connector->status != connector_status_disconnected;

sys/dev/pci/drm/drm_client_modeset.c

242

return enable;

sys/dev/pci/drm/drm_crtc.c

560

if (crtc->state->enable) {

sys/dev/pci/drm/drm_crtc_helper.c

453

if (!new_crtc_state->enable)

sys/dev/pci/drm/drm_mipi_dsi.c

1598

bool enable,

sys/dev/pci/drm/drm_mipi_dsi.c

1609

ret = mipi_dsi_compression_mode_ext(dsi, enable, algo, pps_selector);

sys/dev/pci/drm/drm_mipi_dsi.c

1627

bool enable)

sys/dev/pci/drm/drm_mipi_dsi.c

1629

return mipi_dsi_compression_mode_ext_multi(ctx, enable,

sys/dev/pci/drm/drm_mipi_dsi.c

677

int mipi_dsi_compression_mode_ext(struct mipi_dsi_device *dsi, bool enable,

sys/dev/pci/drm/drm_mipi_dsi.c

693

tx[0] = (enable << 0) |

sys/dev/pci/drm/drm_mipi_dsi.c

713

int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)

sys/dev/pci/drm/drm_mipi_dsi.c

715

return mipi_dsi_compression_mode_ext(dsi, enable, MIPI_DSI_COMPRESSION_DSC, 0);

sys/dev/pci/drm/drm_panel.c

231

if (panel->funcs && panel->funcs->enable) {

sys/dev/pci/drm/drm_panel.c

232

ret = panel->funcs->enable(panel);

sys/dev/pci/drm/drm_plane_helper.c

123

.enable = crtc->enabled,

sys/dev/pci/drm/drm_self_refresh_helper.c

99

if (!crtc_state->enable)

sys/dev/pci/drm/drm_vblank.c

2060

get_seq->active = crtc->state->enable;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

169

static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable);

sys/dev/pci/drm/i915/display/dvo_ch7017.c

337

static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable)

sys/dev/pci/drm/i915/display/dvo_ch7017.c

351

if (enable) {

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

335

static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

337

if (enable)

sys/dev/pci/drm/i915/display/dvo_ivch.c

345

static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)

sys/dev/pci/drm/i915/display/dvo_ivch.c

356

if (enable)

sys/dev/pci/drm/i915/display/dvo_ivch.c

363

if (enable)

sys/dev/pci/drm/i915/display/dvo_ivch.c

375

if (((vr30 & VR30_PANEL_ON) != 0) == enable)

sys/dev/pci/drm/i915/display/dvo_ns2501.c

656

static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)

sys/dev/pci/drm/i915/display/dvo_ns2501.c

660

DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);

sys/dev/pci/drm/i915/display/dvo_ns2501.c

662

if (enable) {

sys/dev/pci/drm/i915/display/dvo_sil164.c

224

static void sil164_dpms(struct intel_dvo_device *dvo, bool enable)

sys/dev/pci/drm/i915/display/dvo_sil164.c

233

if (enable)

sys/dev/pci/drm/i915/display/dvo_tfp410.c

240

static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable)

sys/dev/pci/drm/i915/display/dvo_tfp410.c

247

if (enable)

sys/dev/pci/drm/i915/display/g4x_dp.c

1336

intel_encoder->enable = vlv_enable_dp;

sys/dev/pci/drm/i915/display/g4x_dp.c

1343

intel_encoder->enable = vlv_enable_dp;

sys/dev/pci/drm/i915/display/g4x_dp.c

1348

intel_encoder->enable = g4x_enable_dp;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

175

pipe_config->infoframes.enable |=

sys/dev/pci/drm/i915/display/g4x_hdmi.c

178

if (pipe_config->infoframes.enable)

sys/dev/pci/drm/i915/display/g4x_hdmi.c

720

intel_encoder->enable = vlv_enable_hdmi;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

726

intel_encoder->enable = vlv_enable_hdmi;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

731

intel_encoder->enable = cpt_enable_hdmi;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

733

intel_encoder->enable = ibx_enable_hdmi;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

735

intel_encoder->enable = g4x_enable_hdmi;

sys/dev/pci/drm/i915/display/i9xx_wm.c

115

static void chv_set_memory_dvfs(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

123

if (enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

141

static void chv_set_memory_pm5(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

148

if (enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

160

static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

167

intel_de_write(display, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

171

intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

sys/dev/pci/drm/i915/display/i9xx_wm.c

176

if (enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

184

val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :

sys/dev/pci/drm/i915/display/i9xx_wm.c

195

val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :

sys/dev/pci/drm/i915/display/i9xx_wm.c

203

trace_intel_memory_cxsr(display, was_enabled, enable);

sys/dev/pci/drm/i915/display/i9xx_wm.c

206

str_enabled_disabled(enable),

sys/dev/pci/drm/i915/display/i9xx_wm.c

249

bool intel_set_memory_cxsr(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

254

ret = _intel_set_memory_cxsr(display, enable);

sys/dev/pci/drm/i915/display/i9xx_wm.c

256

display->wm.vlv.cxsr = enable;

sys/dev/pci/drm/i915/display/i9xx_wm.c

258

display->wm.g4x.cxsr = enable;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2672

if (!result->enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2675

result->enable = result->pri_val <= max->pri &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

2679

ret = result->enable;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2686

if (level == 0 && !result->enable) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2703

result->enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2741

result->enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3028

intermediate_wm->enable &= active_wm->enable;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3083

ret_wm->enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3097

if (!wm->enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3098

ret_wm->enable = false;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3133

wm->enable = false;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3143

if (wm->enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3155

wm->enable = false;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3163

return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3204

if (r->enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3230

if (drm_WARN_ON(display->drm, !r->enable))

sys/dev/pci/drm/i915/display/i9xx_wm.c

3252

if (r1->wm[level].enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3254

if (r2->wm[level].enable)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3519

active->wm[0].enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3532

active->wm[level].enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.h

18

bool intel_set_memory_cxsr(struct intel_display *display, bool enable);

sys/dev/pci/drm/i915/display/i9xx_wm.h

28

static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/icl_dsi.c

1106

bool enable)

sys/dev/pci/drm/i915/display/icl_dsi.c

1122

if (enable) {

sys/dev/pci/drm/i915/display/icl_dsi.c

1247

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/icl_dsi.c

1254

enable ? IGNORE_KVMR_PIPE_A : 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

1963

encoder->enable = gen11_dsi_enable;

sys/dev/pci/drm/i915/display/intel_audio.c

1088

bool enable)

sys/dev/pci/drm/i915/display/intel_audio.c

1106

if (enable) {

sys/dev/pci/drm/i915/display/intel_audio.c

401

bool enable)

sys/dev/pci/drm/i915/display/intel_audio.c

410

enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);

sys/dev/pci/drm/i915/display/intel_audio.c

940

bool enable)

sys/dev/pci/drm/i915/display/intel_audio.c

954

intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0);

sys/dev/pci/drm/i915/display/intel_audio.c

960

bool enable)

sys/dev/pci/drm/i915/display/intel_audio.c

981

enable);

sys/dev/pci/drm/i915/display/intel_backlight.c

1640

panel->backlight.pwm_funcs->enable(crtc_state, conn_state,

sys/dev/pci/drm/i915/display/intel_backlight.c

1746

.enable = bxt_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1755

.enable = cnp_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1764

.enable = lpt_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1773

.enable = lpt_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1782

.enable = pch_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1791

.enable = ext_pwm_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1799

.enable = vlv_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1808

.enable = i965_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1817

.enable = i9xx_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

1826

.enable = intel_pwm_enable_backlight,

sys/dev/pci/drm/i915/display/intel_backlight.c

804

panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level);

sys/dev/pci/drm/i915/display/intel_backlight.c

904

bool enable = bd->props.power == BACKLIGHT_POWER_ON &&

sys/dev/pci/drm/i915/display/intel_backlight.c

906

panel->backlight.power(connector, enable);

sys/dev/pci/drm/i915/display/intel_bios.c

1361

panel->vbt.psr.enable = driver->psr_enabled;

sys/dev/pci/drm/i915/display/intel_bios.c

1381

panel->vbt.psr.enable = panel_bool(power->psr, panel_type);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2830

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2940

if (crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3036

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_crt.c

1095

crt->base.enable = hsw_enable_crt;

sys/dev/pci/drm/i915/display/intel_crt.c

1115

crt->base.enable = intel_enable_crt;

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

195

str_yes_no(pipe_config->hw.enable), context);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

197

if (!pipe_config->hw.enable)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

224

str_enabled_disabled(pipe_config->splitter.enable),

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

258

pipe_config->infoframes.enable);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

260

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

263

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

266

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

269

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

272

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

275

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

278

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

281

if (pipe_config->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

298

str_yes_no(pipe_config->vrr.enable),

sys/dev/pci/drm/i915/display/intel_cursor.c

606

if (level->enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

2311

bool enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

2315

if (!crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

2319

enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)

sys/dev/pci/drm/i915/display/intel_ddi.c

2322

str_enable_disable(enable));

sys/dev/pci/drm/i915/display/intel_ddi.c

2327

bool enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

2335

enable ? DP_FEC_READY : 0) <= 0)

sys/dev/pci/drm/i915/display/intel_ddi.c

2337

str_enabled_disabled(enable));

sys/dev/pci/drm/i915/display/intel_ddi.c

2339

if (enable &&

sys/dev/pci/drm/i915/display/intel_ddi.c

2501

pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;

sys/dev/pci/drm/i915/display/intel_ddi.c

2502

if (!pipe_config->splitter.enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

2506

pipe_config->splitter.enable = false;

sys/dev/pci/drm/i915/display/intel_ddi.c

2536

if (crtc_state->splitter.enable) {

sys/dev/pci/drm/i915/display/intel_ddi.c

4005

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_ddi.c

4008

if (crtc_state->infoframes.enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

4065

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_ddi.c

4068

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_ddi.c

4095

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_ddi.c

487

bool enable)

sys/dev/pci/drm/i915/display/intel_ddi.c

496

if (enable && intel_dp_is_uhbr(crtc_state))

sys/dev/pci/drm/i915/display/intel_ddi.c

5205

encoder->enable = intel_ddi_enable;

sys/dev/pci/drm/i915/display/intel_ddi.c

725

bool enable, u32 hdcp_mask)

sys/dev/pci/drm/i915/display/intel_ddi.c

737

hdcp_mask, enable ? hdcp_mask : 0);

sys/dev/pci/drm/i915/display/intel_ddi.h

79

bool enable, u32 hdcp_mask);

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

23

u8 enable; /* scale enable */

sys/dev/pci/drm/i915/display/intel_display.c

1015

return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||

sys/dev/pci/drm/i915/display/intel_display.c

1016

(old_crtc_state->vrr.enable &&

sys/dev/pci/drm/i915/display/intel_display.c

1402

if (encoder->enable)

sys/dev/pci/drm/i915/display/intel_display.c

1403

encoder->enable(state, encoder,

sys/dev/pci/drm/i915/display/intel_display.c

1600

static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

1606

mask, enable ? mask : 0);

sys/dev/pci/drm/i915/display/intel_display.c

211

skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

215

enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);

sys/dev/pci/drm/i915/display/intel_display.c

221

bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

225

enable ? DPFR_GATING_DIS : 0);

sys/dev/pci/drm/i915/display/intel_display.c

2266

if (!crtc_state->splitter.enable)

sys/dev/pci/drm/i915/display/intel_display.c

231

bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

235

enable ? CURSOR_GATING_DIS : 0);

sys/dev/pci/drm/i915/display/intel_display.c

4156

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_display.c

4172

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_display.c

4188

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_display.c

4474

crtc_state->hw.enable = crtc_state->uapi.enable;

sys/dev/pci/drm/i915/display/intel_display.c

4537

secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;

sys/dev/pci/drm/i915/display/intel_display.c

5242

PIPE_CONF_CHECK_BOOL(hw.enable);

sys/dev/pci/drm/i915/display/intel_display.c

5376

if (current_config->vrr.enable || pipe_config->vrr.enable)

sys/dev/pci/drm/i915/display/intel_display.c

5379

PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes);

sys/dev/pci/drm/i915/display/intel_display.c

5429

PIPE_CONF_CHECK_BOOL(splitter.enable);

sys/dev/pci/drm/i915/display/intel_display.c

5434

PIPE_CONF_CHECK_BOOL(vrr.enable);

sys/dev/pci/drm/i915/display/intel_display.c

5442

PIPE_CONF_CHECK_BOOL(cmrr.enable);

sys/dev/pci/drm/i915/display/intel_display.c

5536

if (!crtc_state->hw.enable ||

sys/dev/pci/drm/i915/display/intel_display.c

5796

if (new_crtc_state->hw.enable &&

sys/dev/pci/drm/i915/display/intel_display.c

5813

if (new_crtc_state->hw.enable &&

sys/dev/pci/drm/i915/display/intel_display.c

5857

if (secondary_crtc_state->uapi.enable) {

sys/dev/pci/drm/i915/display/intel_display.c

6276

if (!new_crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_display.c

6291

if (!new_crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_display.c

6400

drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);

sys/dev/pci/drm/i915/display/intel_display.c

6431

if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))

sys/dev/pci/drm/i915/display/intel_display.c

6810

new_crtc_state->vrr.enable);

sys/dev/pci/drm/i915/display/intel_display.c

7224

!new_crtc_state->vrr.enable &&

sys/dev/pci/drm/i915/display/intel_display.c

873

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_display.c

882

enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);

sys/dev/pci/drm/i915/display/intel_display.c

887

enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);

sys/dev/pci/drm/i915/display/intel_display.c

998

return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||

sys/dev/pci/drm/i915/display/intel_display.c

999

(new_crtc_state->vrr.enable &&

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

548

str_yes_no(crtc_state->uapi.enable),

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

553

str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1568

void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1572

if (enable)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1683

bool enable)

sys/dev/pci/drm/i915/display/intel_display_irq.c

1698

intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1799

u32 status, enable, tmp;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1803

enable = tmp >> 16;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1813

*dpinvgtt = status & enable;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1814

enable &= ~status;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1818

intel_de_write(display, DPINVGTT, enable << 16);

sys/dev/pci/drm/i915/display/intel_display_irq.h

87

void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);

sys/dev/pci/drm/i915/display/intel_display_power.c

1071

enum dbuf_slice slice, bool enable)

sys/dev/pci/drm/i915/display/intel_display_power.c

1077

enable ? DBUF_POWER_REQUEST : 0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1082

drm_WARN(display->drm, enable != state,

sys/dev/pci/drm/i915/display/intel_display_power.c

1084

slice, str_enable_disable(enable));

sys/dev/pci/drm/i915/display/intel_display_power.c

1436

bool enable)

sys/dev/pci/drm/i915/display/intel_display_power.c

1452

intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1123

struct i915_power_well *power_well, bool enable)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1133

state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :

sys/dev/pci/drm/i915/display/intel_display_power_well.c

119

power_well->desc->ops->enable(display, power_well);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1718

bool enable)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1725

state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1734

ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1930

.enable = i9xx_always_on_power_well_noop,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1937

.enable = chv_pipe_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1944

.enable = chv_dpio_cmn_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1951

.enable = i830_pipes_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1966

.enable = hsw_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1973

.enable = gen9_dc_off_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1980

.enable = bxt_dpio_cmn_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1987

.enable = vlv_display_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1994

.enable = vlv_dpio_cmn_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

2001

.enable = vlv_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

2015

.enable = icl_aux_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

2029

.enable = hsw_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

2036

.enable = tgl_tc_cold_off_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

2043

.enable = xelpdp_aux_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

2050

.enable = xe2lpd_pica_power_well_enable,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

73

void (*enable)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_display_types.h

1228

u32 enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

1321

bool enable, in_range;

sys/dev/pci/drm/i915/display/intel_display_types.h

1329

bool enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

1335

bool enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

1927

bool enable,

sys/dev/pci/drm/i915/display/intel_display_types.h

193

void (*enable)(struct intel_atomic_state *,

sys/dev/pci/drm/i915/display/intel_display_types.h

307

void (*enable)(const struct intel_crtc_state *crtc_state,

sys/dev/pci/drm/i915/display/intel_display_types.h

356

bool enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

441

void (*power)(struct intel_connector *, bool enable);

sys/dev/pci/drm/i915/display/intel_display_types.h

780

bool enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

799

bool enable;

sys/dev/pci/drm/i915/display/intel_display_types.h

980

bool active, enable;

sys/dev/pci/drm/i915/display/intel_dmc.c

463

static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

474

if (enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

496

static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

498

if (display->platform.meteorlake && enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

501

adlp_pipedmc_clock_gating_wa(display, enable);

sys/dev/pci/drm/i915/display/intel_dmc.c

818

bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

831

intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable());

sys/dev/pci/drm/i915/display/intel_dmc.c

868

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_dmc.c

872

dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable);

sys/dev/pci/drm/i915/display/intel_dmc.h

28

enum pipe pipe, bool enable);

sys/dev/pci/drm/i915/display/intel_dp.c

2884

if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)

sys/dev/pci/drm/i915/display/intel_dp.c

2887

crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);

sys/dev/pci/drm/i915/display/intel_dp.c

2894

if (crtc_state->cmrr.enable) {

sys/dev/pci/drm/i915/display/intel_dp.c

2917

crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);

sys/dev/pci/drm/i915/display/intel_dp.c

2985

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_dp.c

2995

if (pipe_config->vrr.enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3048

if (pipe_config->splitter.enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3057

if (pipe_config->splitter.enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3326

pipe_config->splitter.enable = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3359

if (pipe_config->splitter.enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3460

bool enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3465

DP_DECOMPRESSION_EN, enable) < 0)

sys/dev/pci/drm/i915/display/intel_dp.c

3468

str_enable_disable(enable));

sys/dev/pci/drm/i915/display/intel_dp.c

3473

bool enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3483

DP_DSC_PASSTHROUGH_EN, enable) < 0)

sys/dev/pci/drm/i915/display/intel_dp.c

3486

str_enable_disable(enable));

sys/dev/pci/drm/i915/display/intel_dp.c

4804

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_dp.c

4833

bool enable,

sys/dev/pci/drm/i915/display/intel_dp.c

4849

if (!enable && HAS_DSC(display))

sys/dev/pci/drm/i915/display/intel_dp.c

4856

if (!enable || !crtc_state->has_psr)

sys/dev/pci/drm/i915/display/intel_dp.c

4862

if (!enable)

sys/dev/pci/drm/i915/display/intel_dp.c

4987

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_dp.c

5055

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_dp.c

5077

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_dp.c

6255

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_dp.h

127

void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

334

panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

499

panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

628

.enable = intel_dp_aux_hdr_enable_backlight,

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

636

.enable = intel_dp_aux_vesa_enable_backlight,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

250

bool enable)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

748

bool enable)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

756

hdcp->stream_transcoder, enable,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

760

enable ? "Enable" : "Disable", ret);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

766

bool enable)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

776

ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

786

stream_enc_status, enable ? stream_enc_status : 0,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

789

transcoder_name(cpu_transcoder), str_enabled_disabled(enable));

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

798

bool enable)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

815

drm_WARN_ON(display->drm, enable &&

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

819

ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

826

enable ? STREAM_ENCRYPTION_STATUS : 0,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

829

transcoder_name(cpu_transcoder), str_enabled_disabled(enable));

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

837

drm_WARN_ON(display->drm, enable &&

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

121

intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

123

u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1837

encoder->enable = mst_stream_enable;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

333

trans->entries[level].bxt.enable ?

sys/dev/pci/drm/i915/display/intel_dpll.c

1749

if (!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_dpll.c

1771

drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1773

if (!crtc_state->hw.enable || crtc_state->intel_dpll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1274

.enable = hsw_ddi_wrpll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1281

.enable = hsw_ddi_spll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1306

.enable = hsw_ddi_lcpll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2008

.enable = skl_ddi_pll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2015

.enable = skl_ddi_dpll0_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

238

pll->info->funcs->enable(display, pll, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2498

.enable = bxt_ddi_pll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4140

.enable = combo_pll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4147

.enable = tbt_pll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4154

.enable = mg_pll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4202

.enable = mg_pll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

674

.enable = ibx_pch_dpll_enable,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

72

void (*enable)(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_dsb.c

115

return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

185

.enable = dcs_enable_backlight,

sys/dev/pci/drm/i915/display/intel_dvo.c

512

encoder->enable = intel_enable_dvo;

sys/dev/pci/drm/i915/display/intel_dvo_dev.h

62

void (*dpms)(struct intel_dvo_device *dvo, bool enable);

sys/dev/pci/drm/i915/display/intel_fbc.c

702

bool enable)

sys/dev/pci/drm/i915/display/intel_fbc.c

705

DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);

sys/dev/pci/drm/i915/display/intel_fbc.c

83

void (*set_false_color)(struct intel_fbc *fbc, bool enable);

sys/dev/pci/drm/i915/display/intel_fdi.c

179

if (crtc_state->hw.enable && crtc_state->has_pch_encoder)

sys/dev/pci/drm/i915/display/intel_fdi.c

378

!crtc_state->hw.enable)

sys/dev/pci/drm/i915/display/intel_fdi.c

389

static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_fdi.c

394

if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)

sys/dev/pci/drm/i915/display/intel_fdi.c

405

if (enable)

sys/dev/pci/drm/i915/display/intel_fdi.c

409

enable ? "en" : "dis");

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

115

bool enable, bool old)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

121

if (enable) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

135

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

140

if (enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

165

enum pipe pipe, bool enable,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

168

if (enable) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

189

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

191

if (enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

199

bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

204

if (enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

232

bool enable, bool old)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

234

if (enable) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

255

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

263

crtc->cpu_fifo_underrun_disabled = !enable;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

266

i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

268

ilk_set_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

270

ivb_set_fifo_underrun_reporting(display, pipe, enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

272

bdw_set_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

294

enum pipe pipe, bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

300

ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

322

bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

340

crtc->pch_fifo_underrun_disabled = !enable;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

345

enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

349

enable, old);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

462

bool enable)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

464

crtc->cpu_fifo_underrun_disabled = !enable;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

476

crtc->pch_fifo_underrun_disabled = !enable;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

16

struct intel_crtc *crtc, bool enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

18

enum pipe pipe, bool enable);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

21

bool enable);

sys/dev/pci/drm/i915/display/intel_gmbus.c

222

bool enable)

sys/dev/pci/drm/i915/display/intel_gmbus.c

227

!enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

231

bool enable)

sys/dev/pci/drm/i915/display/intel_gmbus.c

235

!enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);

sys/dev/pci/drm/i915/display/intel_gmbus.c

239

bool enable)

sys/dev/pci/drm/i915/display/intel_gmbus.c

242

!enable ? BXT_GMBUS_GATING_DIS : 0);

sys/dev/pci/drm/i915/display/intel_hdcp.c

47

bool enable)

sys/dev/pci/drm/i915/display/intel_hdcp.c

70

intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

126

bool enable);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

87

bool enable);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

91

bool enable);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1012

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_hdmi.c

1037

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_hdmi.c

1051

bool enable,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1068

if (!enable) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

1110

bool enable,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1125

if (!enable) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

1159

bool enable,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1175

if (!enable) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

1225

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_hdmi.c

1241

bool enable,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1258

if (!enable) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

1284

void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1293

enable ? "Enabling" : "Disabling");

sys/dev/pci/drm/i915/display/intel_hdmi.c

1296

hdmi->dp_dual_mode.type, ddc, enable);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1537

bool enable)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1544

if (!enable)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1548

cpu_transcoder, enable,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1552

enable ? "Enable" : "Disable", ret);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1560

if (display->platform.kabylake && enable)

sys/dev/pci/drm/i915/display/intel_hdmi.c

659

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_hdmi.c

688

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_hdmi.c

726

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_hdmi.c

781

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_hdmi.c

815

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_hdmi.c

849

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_hdmi.c

867

bool enable,

sys/dev/pci/drm/i915/display/intel_hdmi.c

891

if (!enable) {

sys/dev/pci/drm/i915/display/intel_hdmi.c

987

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_hdmi.h

37

void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1095

enum hpd_pin hpd_pin, bool enable)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1104

mask, enable ? mask : 0);

sys/dev/pci/drm/i915/display/intel_load_detect.c

101

if (possible_crtc->base.state->enable) {

sys/dev/pci/drm/i915/display/intel_lspcon.c

539

bool enable,

sys/dev/pci/drm/i915/display/intel_lspcon.h

34

bool enable,

sys/dev/pci/drm/i915/display/intel_lvds.c

910

encoder->enable = intel_enable_lvds;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

328

crtc_state->uapi.enable = crtc_state->hw.enable;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

710

crtc_state->hw.enable = crtc_state->hw.active;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

712

crtc->base.enabled = crtc_state->hw.enable;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

833

crtc_state->vrr.enable);

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

180

hw_crtc_state->hw.enable = sw_crtc_state->hw.enable;

sys/dev/pci/drm/i915/display/intel_opregion.c

392

bool enable)

sys/dev/pci/drm/i915/display/intel_opregion.c

436

if (!enable)

sys/dev/pci/drm/i915/display/intel_opregion.h

101

intel_opregion_notify_encoder(struct intel_encoder *encoder, bool enable)

sys/dev/pci/drm/i915/display/intel_opregion.h

50

bool enable);

sys/dev/pci/drm/i915/display/intel_overlay.c

213

bool enable)

sys/dev/pci/drm/i915/display/intel_overlay.c

219

if (enable)

sys/dev/pci/drm/i915/display/intel_overlay.c

227

if (enable)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

282

intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

291

i915gm_irq_cstate_wa(display, enable);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

312

pipe_config->crc_enabled = enable;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

331

"Toggling workaround to %i returns %i\n", enable, ret);

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

593

bool enable;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

608

enable = source != INTEL_PIPE_CRC_SOURCE_NONE;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

609

if (enable)

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

628

if (!enable)

sys/dev/pci/drm/i915/display/intel_pps.c

1147

void intel_pps_backlight_power(struct intel_connector *connector, bool enable)

sys/dev/pci/drm/i915/display/intel_pps.c

1157

if (is_enabled == enable)

sys/dev/pci/drm/i915/display/intel_pps.c

1161

str_enable_disable(enable));

sys/dev/pci/drm/i915/display/intel_pps.c

1163

if (enable)

sys/dev/pci/drm/i915/display/intel_pps.h

28

void intel_pps_backlight_power(struct intel_connector *connector, bool enable);

sys/dev/pci/drm/i915/display/intel_psr.c

1491

if (crtc_state->vrr.enable &&

sys/dev/pci/drm/i915/display/intel_psr.c

1582

if (crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_psr.c

1771

pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);

sys/dev/pci/drm/i915/display/intel_psr.c

243

connector->panel.vbt.psr.enable : true;

sys/dev/pci/drm/i915/display/intel_psr.c

2713

crtc_state->splitter.enable)

sys/dev/pci/drm/i915/display/intel_psr.c

3889

struct intel_crtc *crtc, bool enable)

sys/dev/pci/drm/i915/display/intel_psr.c

3909

if (enable)

sys/dev/pci/drm/i915/display/intel_psr.c

3917

if ((enable && intel_dp->psr.active_non_psr_pipes) ||

sys/dev/pci/drm/i915/display/intel_psr.c

3918

(!enable && !intel_dp->psr.active_non_psr_pipes) ||

sys/dev/pci/drm/i915/display/intel_psr.c

3941

bool enable)

sys/dev/pci/drm/i915/display/intel_psr.c

3968

intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :

sys/dev/pci/drm/i915/display/intel_psr.h

68

struct intel_crtc *crtc, bool enable);

sys/dev/pci/drm/i915/display/intel_psr.h

72

bool enable);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1111

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_sdvo.c

1142

if ((crtc_state->infoframes.enable &

sys/dev/pci/drm/i915/display/intel_sdvo.c

1180

crtc_state->infoframes.enable |=

sys/dev/pci/drm/i915/display/intel_sdvo.c

3435

intel_encoder->enable = intel_enable_sdvo;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

587

unsigned int enable:1;

sys/dev/pci/drm/i915/display/intel_snps_phy.c

52

bool enable)

sys/dev/pci/drm/i915/display/intel_snps_phy.c

62

enable ? 2 : 3);

sys/dev/pci/drm/i915/display/intel_snps_phy.h

21

bool enable);

sys/dev/pci/drm/i915/display/intel_tc.c

1076

static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)

sys/dev/pci/drm/i915/display/intel_tc.c

1086

intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable ? 1 : 0);

sys/dev/pci/drm/i915/display/intel_tc.c

1100

static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)

sys/dev/pci/drm/i915/display/intel_tc.c

1110

xelpdp_tc_power_request_wa(display, enable);

sys/dev/pci/drm/i915/display/intel_tc.c

1113

if (enable)

sys/dev/pci/drm/i915/display/intel_tc.c

1120

static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)

sys/dev/pci/drm/i915/display/intel_tc.c

1124

__xelpdp_tc_phy_enable_tcss_power(tc, enable);

sys/dev/pci/drm/i915/display/intel_tc.c

1126

if (enable && !tc_phy_wait_for_ready(tc))

sys/dev/pci/drm/i915/display/intel_tc.c

1129

if (!xelpdp_tc_phy_wait_for_tcss_power(tc, enable))

sys/dev/pci/drm/i915/display/intel_tc.c

1138

if (!enable)

sys/dev/pci/drm/i915/display/intel_tv.c

2006

intel_encoder->enable = intel_enable_tv;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1516

u8 enable;

sys/dev/pci/drm/i915/display/intel_vrr.c

233

crtc_state->cmrr.enable = true;

sys/dev/pci/drm/i915/display/intel_vrr.c

249

crtc_state->vrr.enable = true;

sys/dev/pci/drm/i915/display/intel_vrr.c

494

if (crtc_state->cmrr.enable) {

sys/dev/pci/drm/i915/display/intel_vrr.c

507

if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

524

if (!crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

545

if (!crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

577

if (!crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

618

if (!crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

634

if (crtc_state->cmrr.enable) {

sys/dev/pci/drm/i915/display/intel_vrr.c

650

if (!old_crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/intel_vrr.c

729

crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);

sys/dev/pci/drm/i915/display/intel_vrr.c

731

if (crtc_state->cmrr.enable) {

sys/dev/pci/drm/i915/display/intel_vrr.c

780

crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state);

sys/dev/pci/drm/i915/display/intel_vrr.c

782

crtc_state->vrr.enable = vrr_enable;

sys/dev/pci/drm/i915/display/intel_vrr.c

789

if (crtc_state->vrr.enable)

sys/dev/pci/drm/i915/display/skl_scaler.c

185

if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1783

if (crtc_state->hw.enable &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

815

if (level->enable)

sys/dev/pci/drm/i915/display/skl_watermark.c

1375

return level > 0 && !wm->wm[level].enable;

sys/dev/pci/drm/i915/display/skl_watermark.c

1929

result->enable = true;

sys/dev/pci/drm/i915/display/skl_watermark.c

2036

trans_wm->enable = true;

sys/dev/pci/drm/i915/display/skl_watermark.c

2337

wm->wm[level].enable = false;

sys/dev/pci/drm/i915/display/skl_watermark.c

2338

wm->uv_wm[level].enable = false;

sys/dev/pci/drm/i915/display/skl_watermark.c

2352

wm->sagv.wm0.enable = false;

sys/dev/pci/drm/i915/display/skl_watermark.c

2353

wm->sagv.trans_wm.enable = false;

sys/dev/pci/drm/i915/display/skl_watermark.c

2395

return l1->enable == l2->enable &&

sys/dev/pci/drm/i915/display/skl_watermark.c

2619

static char enast(bool enable)

sys/dev/pci/drm/i915/display/skl_watermark.c

2621

return enable ? '*' : ' ';

sys/dev/pci/drm/i915/display/skl_watermark.c

2634

enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2635

enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2636

enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2637

enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2638

enast(old_wm->trans_wm.enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2639

enast(old_wm->sagv.wm0.enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2640

enast(old_wm->sagv.trans_wm.enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2641

enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2642

enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2643

enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2644

enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2645

enast(new_wm->trans_wm.enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2646

enast(new_wm->sagv.wm0.enable),

sys/dev/pci/drm/i915/display/skl_watermark.c

2647

enast(new_wm->sagv.trans_wm.enable));

sys/dev/pci/drm/i915/display/skl_watermark.c

2877

display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;

sys/dev/pci/drm/i915/display/skl_watermark.c

3000

level->enable = val & PLANE_WM_EN;

sys/dev/pci/drm/i915/display/skl_watermark.c

324

if (!wm->wm[0].enable)

sys/dev/pci/drm/i915/display/skl_watermark.c

329

!wm->wm[level].enable; --level)

sys/dev/pci/drm/i915/display/skl_watermark.c

348

if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)

sys/dev/pci/drm/i915/display/skl_watermark.c

367

if (wm->wm[0].enable && !wm->sagv.wm0.enable)

sys/dev/pci/drm/i915/display/skl_watermark.c

3882

sw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3885

hw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3897

sw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3900

hw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3913

sw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3916

hw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3929

sw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3932

hw_wm_level->enable,

sys/dev/pci/drm/i915/display/skl_watermark.c

3992

bool enable;

sys/dev/pci/drm/i915/display/skl_watermark.c

3995

ret = kstrtobool_from_user(ubuf, len, &enable);

sys/dev/pci/drm/i915/display/skl_watermark.c

4000

if (!skl_watermark_ipc_enabled(display) && enable)

sys/dev/pci/drm/i915/display/skl_watermark.c

4003

display->wm.ipc_enabled = enable;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1941

encoder->enable = bxt_dsi_enable;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

485

u32 enable;

sys/dev/pci/drm/i915/gt/intel_rps.c

2657

static void intel_rps_set_manual(struct intel_rps *rps, bool enable)

sys/dev/pci/drm/i915/gt/intel_rps.c

2660

u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

197

guc->interrupts.enable = gen11_enable_guc_interrupts;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

212

guc->interrupts.enable = gen9_enable_guc_interrupts;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

480

guc->interrupts.enable(guc);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

98

void (*enable)(struct intel_guc *guc);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

206

static int ct_control_enable(struct intel_guc_ct *ct, bool enable)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

210

err = guc_action_control_ctb(ct_to_guc(ct), enable ?

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

214

str_enable_disable(enable), ERR_PTR(err));

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

204

static int guc_action_control_log(struct intel_guc *guc, bool enable,

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

209

(enable ? GUC_LOG_CONTROL_LOGGING_ENABLED : 0) |

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

34

static int guc_action_control_gucrc(struct intel_guc *guc, bool enable)

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

36

u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL :

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

50

static int __guc_rc_control(struct intel_guc *guc, bool enable)

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

61

ret = guc_action_control_gucrc(guc, enable);

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

64

str_enable_disable(enable), ERR_PTR(ret));

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

68

guc_info(guc, "RC %s\n", str_enabled_disabled(enable));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3183

bool enable;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3192

enable = false;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3194

enable = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3204

if (enable) {

sys/dev/pci/drm/i915/i915_mitigations.c

104

bool enable;

sys/dev/pci/drm/i915/i915_mitigations.c

111

enable = false;

sys/dev/pci/drm/i915/i915_mitigations.c

113

enable = true;

sys/dev/pci/drm/i915/i915_mitigations.c

118

if ((local & BIT(i)) != enable)

sys/dev/pci/drm/i915/i915_mitigations.c

122

"%s%s,", enable ? "" : "!", names[i]);

sys/dev/pci/drm/i915/i915_mitigations.c

46

bool enable = true;

sys/dev/pci/drm/i915/i915_mitigations.c

64

enable = !enable;

sys/dev/pci/drm/i915/i915_mitigations.c

69

enable = !enable;

sys/dev/pci/drm/i915/i915_mitigations.c

78

if (enable)

sys/dev/pci/drm/i915/i915_perf.c

3159

.enable = i915_oa_stream_enable,

sys/dev/pci/drm/i915/i915_perf.c

3611

if (stream->ops->enable)

sys/dev/pci/drm/i915/i915_perf.c

3612

stream->ops->enable(stream);

sys/dev/pci/drm/i915/i915_perf_types.h

109

void (*enable)(struct i915_perf_stream *stream);

sys/dev/pci/drm/i915/i915_pmu.c

118

enable)) - 1);

sys/dev/pci/drm/i915/i915_pmu.c

122

enable)) - 1);

sys/dev/pci/drm/i915/i915_pmu.c

152

u32 enable;

sys/dev/pci/drm/i915/i915_pmu.c

159

enable = pmu->enable;

sys/dev/pci/drm/i915/i915_pmu.c

165

enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;

sys/dev/pci/drm/i915/i915_pmu.c

172

enable &= ~BIT(I915_SAMPLE_BUSY);

sys/dev/pci/drm/i915/i915_pmu.c

177

return enable;

sys/dev/pci/drm/i915/i915_pmu.c

424

if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)

sys/dev/pci/drm/i915/i915_pmu.c

431

if (!engine->pmu.enable)

sys/dev/pci/drm/i915/i915_pmu.c

452

return pmu->enable &

sys/dev/pci/drm/i915/i915_pmu.c

474

if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) {

sys/dev/pci/drm/i915/i915_pmu.c

494

if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) {

sys/dev/pci/drm/i915/i915_pmu.c

753

pmu->enable |= BIT(bit);

sys/dev/pci/drm/i915/i915_pmu.c

781

engine->pmu.enable |= BIT(sample);

sys/dev/pci/drm/i915/i915_pmu.c

825

engine->pmu.enable &= ~BIT(sample);

sys/dev/pci/drm/i915/i915_pmu.c

835

pmu->enable &= ~BIT(bit);

sys/dev/pci/drm/i915/i915_pmu.h

94

u32 enable;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

65

static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)

sys/dev/pci/drm/i915/pxp/intel_pxp.c

67

u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :

sys/dev/pci/drm/include/drm/display/drm_dp_dual_mode_helper.h

114

struct i2c_adapter *adapter, bool enable);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

535

void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

734

int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable);

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

939

int pbn, bool enable);

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

27

int (*enable)(struct drm_connector *connector, bool enable);

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

77

bool drm_scdc_set_scrambling(struct drm_connector *connector, bool enable);

sys/dev/pci/drm/include/drm/drm_audio_component.h

39

void (*codec_wake_override)(struct device *, bool enable);

sys/dev/pci/drm/include/drm/drm_bridge.h

300

void (*enable)(struct drm_bridge *bridge);

sys/dev/pci/drm/include/drm/drm_bridge.h

751

bool enable, int direction);

sys/dev/pci/drm/include/drm/drm_bridge.h

780

int (*hdmi_cec_enable)(struct drm_bridge *bridge, bool enable);

sys/dev/pci/drm/include/drm/drm_bridge.h

868

bool enable, int direction);

sys/dev/pci/drm/include/drm/drm_connector.h

1198

bool enable, int direction);

sys/dev/pci/drm/include/drm/drm_crtc.h

90

bool enable;

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

801

void (*enable)(struct drm_encoder *encoder);

sys/dev/pci/drm/include/drm/drm_panel.h

90

int (*enable)(struct drm_panel *panel);

sys/dev/pci/drm/include/uapi/linux/kfd_ioctl.h

1537

struct kfd_ioctl_dbg_trap_enable_args enable;

sys/dev/pci/drm/radeon/atombios_crtc.c

444

int enable,

sys/dev/pci/drm/radeon/atombios_crtc.c

453

if (enable) {

sys/dev/pci/drm/radeon/atombios_crtc.c

498

args.v3.ucEnable = enable;

sys/dev/pci/drm/radeon/atombios_crtc.c

517

args.v2.ucEnable = enable;

sys/dev/pci/drm/radeon/atombios_crtc.c

525

args.v1.ucEnable = enable;

sys/dev/pci/drm/radeon/atombios_crtc.c

527

if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||

sys/dev/pci/drm/radeon/atombios_crtc.c

537

args.lvds_ss_2.ucEnable = enable;

sys/dev/pci/drm/radeon/atombios_crtc.c

539

if (enable == ATOM_DISABLE) {

sys/dev/pci/drm/radeon/atombios_crtc.c

547

args.lvds_ss.ucEnable = enable;

sys/dev/pci/drm/radeon/atombios_encoders.c

1526

atombios_yuv_setup(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/radeon/atombios_encoders.c

1553

if (enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1304

bool enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1310

if (enable) {

sys/dev/pci/drm/radeon/btc_dpm.c

1346

bool enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1348

btc_enable_bif_dynamic_pcie_gen2(rdev, enable);

sys/dev/pci/drm/radeon/btc_dpm.c

1350

if (enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1445

bool enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1450

if (enable) {

sys/dev/pci/drm/radeon/btc_dpm.c

1500

bool enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1505

if (enable) {

sys/dev/pci/drm/radeon/btc_dpm.c

1555

bool enable)

sys/dev/pci/drm/radeon/btc_dpm.c

1560

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

1389

bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1393

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

1438

static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1443

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

1577

static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1581

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1863

bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1867

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1921

bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1925

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

1977

static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

1982

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

3061

static int ci_enable_ulv(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

3067

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

3881

static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

3892

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

3925

return (ci_send_msg_to_smc(rdev, enable ?

sys/dev/pci/drm/radeon/ci_dpm.c

3930

static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

3941

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

3957

return (ci_send_msg_to_smc(rdev, enable ?

sys/dev/pci/drm/radeon/ci_dpm.c

3963

static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

3974

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

3989

return (ci_send_msg_to_smc(rdev, enable ?

sys/dev/pci/drm/radeon/ci_dpm.c

3994

static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

4005

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

4021

return (ci_send_msg_to_smc(rdev, enable ?

sys/dev/pci/drm/radeon/ci_dpm.c

496

static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

503

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

512

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

521

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

530

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

586

static int ci_enable_didt(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

595

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

603

ci_do_enable_didt(rdev, enable);

sys/dev/pci/drm/radeon/ci_dpm.c

611

static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

617

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

669

static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

676

if (enable) {

sys/dev/pci/drm/radeon/ci_dpm.c

694

bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

700

if (enable)

sys/dev/pci/drm/radeon/ci_dpm.c

877

bool enable)

sys/dev/pci/drm/radeon/ci_dpm.c

882

if (enable) {

sys/dev/pci/drm/radeon/cik.c

141

bool enable);

sys/dev/pci/drm/radeon/cik.c

3863

static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

3865

if (enable)

sys/dev/pci/drm/radeon/cik.c

4217

static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

4219

if (enable)

sys/dev/pci/drm/radeon/cik.c

4745

static void cik_cp_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

4747

cik_cp_gfx_enable(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

4748

cik_cp_compute_enable(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

5758

bool enable)

sys/dev/pci/drm/radeon/cik.c

5762

if (enable)

sys/dev/pci/drm/radeon/cik.c

5769

static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

5774

if (enable)

sys/dev/pci/drm/radeon/cik.c

5990

static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

5996

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/radeon/cik.c

6026

static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

6030

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/radeon/cik.c

6120

bool enable)

sys/dev/pci/drm/radeon/cik.c

6127

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))

sys/dev/pci/drm/radeon/cik.c

6137

bool enable)

sys/dev/pci/drm/radeon/cik.c

6144

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/radeon/cik.c

6154

bool enable)

sys/dev/pci/drm/radeon/cik.c

6158

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/radeon/cik.c

6175

bool enable)

sys/dev/pci/drm/radeon/cik.c

6179

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {

sys/dev/pci/drm/radeon/cik.c

6203

bool enable)

sys/dev/pci/drm/radeon/cik.c

6207

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {

sys/dev/pci/drm/radeon/cik.c

6229

bool enable)

sys/dev/pci/drm/radeon/cik.c

6235

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/radeon/cik.c

6247

bool enable)

sys/dev/pci/drm/radeon/cik.c

6253

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))

sys/dev/pci/drm/radeon/cik.c

6263

bool enable)

sys/dev/pci/drm/radeon/cik.c

6269

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/radeon/cik.c

6279

u32 block, bool enable)

sys/dev/pci/drm/radeon/cik.c

6285

if (enable) {

sys/dev/pci/drm/radeon/cik.c

6297

cik_enable_mc_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6298

cik_enable_mc_ls(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6303

cik_enable_sdma_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6304

cik_enable_sdma_mgls(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6308

cik_enable_bif_mgls(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6313

cik_enable_uvd_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6317

cik_enable_hdp_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6318

cik_enable_hdp_ls(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6322

vce_v2_0_enable_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6353

bool enable)

sys/dev/pci/drm/radeon/cik.c

6358

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))

sys/dev/pci/drm/radeon/cik.c

6367

bool enable)

sys/dev/pci/drm/radeon/cik.c

6372

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))

sys/dev/pci/drm/radeon/cik.c

6380

static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

6385

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))

sys/dev/pci/drm/radeon/cik.c

6393

static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

6398

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))

sys/dev/pci/drm/radeon/cik.c

6495

bool enable)

sys/dev/pci/drm/radeon/cik.c

6499

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {

sys/dev/pci/drm/radeon/cik.c

6581

bool enable)

sys/dev/pci/drm/radeon/cik.c

6586

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))

sys/dev/pci/drm/radeon/cik.c

6595

bool enable)

sys/dev/pci/drm/radeon/cik.c

6600

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))

sys/dev/pci/drm/radeon/cik.c

6660

static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik.c

6662

cik_enable_gfx_cgpg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6663

cik_enable_gfx_static_mgpg(rdev, enable);

sys/dev/pci/drm/radeon/cik.c

6664

cik_enable_gfx_dynamic_mgpg(rdev, enable);

sys/dev/pci/drm/radeon/cik.h

31

void cik_update_cg(struct radeon_device *rdev, u32 block, bool enable);

sys/dev/pci/drm/radeon/cik.h

38

void cik_sdma_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/cik_sdma.c

303

static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik_sdma.c

314

if (enable)

sys/dev/pci/drm/radeon/cik_sdma.c

330

void cik_sdma_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/cik_sdma.c

335

if (!enable) {

sys/dev/pci/drm/radeon/cik_sdma.c

346

if (enable)

sys/dev/pci/drm/radeon/cik_sdma.c

353

cik_sdma_ctx_switch_enable(rdev, enable);

sys/dev/pci/drm/radeon/cypress_dpm.c

119

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

123

if (enable) {

sys/dev/pci/drm/radeon/cypress_dpm.c

171

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

176

if (enable) {

sys/dev/pci/drm/radeon/cypress_dpm.c

220

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

224

if (enable) {

sys/dev/pci/drm/radeon/cypress_dpm.c

244

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

246

if (enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

253

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

255

if (enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

49

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

55

if (enable) {

sys/dev/pci/drm/radeon/cypress_dpm.c

86

bool enable)

sys/dev/pci/drm/radeon/cypress_dpm.c

88

cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);

sys/dev/pci/drm/radeon/cypress_dpm.c

90

if (enable)

sys/dev/pci/drm/radeon/cypress_dpm.h

141

bool enable);

sys/dev/pci/drm/radeon/cypress_dpm.h

150

bool enable);

sys/dev/pci/drm/radeon/cypress_dpm.h

152

bool enable);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

402

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

412

if (enable) {

sys/dev/pci/drm/radeon/evergreen_hdmi.c

436

dig->afmt->enabled = enable;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

439

enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

442

void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

453

if (enable && connector && connector->display_info.has_audio) {

sys/dev/pci/drm/radeon/evergreen_hdmi.c

489

dig->afmt->enabled = enable;

sys/dev/pci/drm/radeon/evergreen_hdmi.h

47

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

48

void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);

sys/dev/pci/drm/radeon/kv_dpm.c

1002

void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1008

ret = kv_smc_bapm_enable(rdev, enable);

sys/dev/pci/drm/radeon/kv_dpm.c

1014

static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1019

if (enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1219

static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1221

return kv_notify_message_to_smu(rdev, enable ?

sys/dev/pci/drm/radeon/kv_dpm.c

1225

static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1227

return kv_notify_message_to_smu(rdev, enable ?

sys/dev/pci/drm/radeon/kv_dpm.c

1231

static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1233

return kv_notify_message_to_smu(rdev, enable ?

sys/dev/pci/drm/radeon/kv_dpm.c

1237

static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1239

return kv_notify_message_to_smu(rdev, enable ?

sys/dev/pci/drm/radeon/kv_dpm.c

1611

bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

1616

if (enable) {

sys/dev/pci/drm/radeon/kv_dpm.c

2051

u32 index, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

2055

pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;

sys/dev/pci/drm/radeon/kv_dpm.c

206

static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

213

if (enable)

sys/dev/pci/drm/radeon/kv_dpm.c

222

if (enable)

sys/dev/pci/drm/radeon/kv_dpm.c

231

if (enable)

sys/dev/pci/drm/radeon/kv_dpm.c

240

if (enable)

sys/dev/pci/drm/radeon/kv_dpm.c

248

static int kv_enable_didt(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

259

if (enable) {

sys/dev/pci/drm/radeon/kv_dpm.c

267

kv_do_enable_didt(rdev, enable);

sys/dev/pci/drm/radeon/kv_dpm.c

275

static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

281

if (enable) {

sys/dev/pci/drm/radeon/kv_dpm.c

38

bool enable);

sys/dev/pci/drm/radeon/kv_dpm.c

478

u32 index, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

482

pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;

sys/dev/pci/drm/radeon/kv_dpm.c

65

u32 block, bool enable);

sys/dev/pci/drm/radeon/kv_dpm.c

967

static int kv_enable_ulv(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_dpm.c

969

return kv_notify_message_to_smu(rdev, enable ?

sys/dev/pci/drm/radeon/kv_dpm.h

194

int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/kv_dpm.h

195

int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/kv_smc.c

101

int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_smc.c

103

if (enable)

sys/dev/pci/drm/radeon/kv_smc.c

109

int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/kv_smc.c

111

if (enable)

sys/dev/pci/drm/radeon/ni.c

1435

static void cayman_cp_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/ni.c

1437

if (enable)

sys/dev/pci/drm/radeon/ni_dpm.c

2600

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

2607

if (enable) {

sys/dev/pci/drm/radeon/ni_dpm.c

3379

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

3386

if (enable) {

sys/dev/pci/drm/radeon/ni_dpm.c

3459

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

3468

if (enable) {

sys/dev/pci/drm/radeon/ni_dpm.c

3498

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

3500

ni_enable_bif_dynamic_pcie_gen2(rdev, enable);

sys/dev/pci/drm/radeon/ni_dpm.c

3502

if (enable)

sys/dev/pci/drm/radeon/ni_dpm.c

916

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

921

if (enable) {

sys/dev/pci/drm/radeon/ni_dpm.c

944

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

949

if (enable) {

sys/dev/pci/drm/radeon/ni_dpm.c

972

bool enable)

sys/dev/pci/drm/radeon/ni_dpm.c

977

if (enable) {

sys/dev/pci/drm/radeon/r100.c

608

unsigned enable = 0;

sys/dev/pci/drm/radeon/r100.c

613

enable |= 1 << radeon_connector->hpd.hpd;

sys/dev/pci/drm/radeon/r100.c

616

radeon_irq_kms_enable_hpd(rdev, enable);

sys/dev/pci/drm/radeon/r600.c

1012

enable |= 1 << radeon_connector->hpd.hpd;

sys/dev/pci/drm/radeon/r600.c

1015

radeon_irq_kms_enable_hpd(rdev, enable);

sys/dev/pci/drm/radeon/r600.c

955

unsigned enable = 0;

sys/dev/pci/drm/radeon/r600.h

53

void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.c

240

void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

244

if (enable) {

sys/dev/pci/drm/radeon/r600_dpm.c

264

void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

266

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

272

void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

274

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

285

void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

287

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

301

void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

303

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

309

void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

311

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

317

void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

319

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

444

u32 index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

446

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

455

u32 index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

457

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

466

u32 index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

468

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.c

560

enum r600_power_level index, bool enable)

sys/dev/pci/drm/radeon/r600_dpm.c

564

if (enable)

sys/dev/pci/drm/radeon/r600_dpm.h

142

void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

143

void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

144

void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

146

void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

148

void r600_enable_sclk_control(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

149

void r600_enable_mclk_control(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

150

void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

174

u32 index, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

176

u32 index, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

178

u32 index, bool enable);

sys/dev/pci/drm/radeon/r600_dpm.h

197

enum r600_power_level index, bool enable);

sys/dev/pci/drm/radeon/r600_hdmi.c

448

void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)

sys/dev/pci/drm/radeon/r600_hdmi.c

461

if (enable)

sys/dev/pci/drm/radeon/r600_hdmi.c

465

if (enable) {

sys/dev/pci/drm/radeon/r600_hdmi.c

473

if (enable) {

sys/dev/pci/drm/radeon/r600_hdmi.c

481

if (enable) {

sys/dev/pci/drm/radeon/r600_hdmi.c

489

if (enable)

sys/dev/pci/drm/radeon/r600_hdmi.c

503

if (enable)

sys/dev/pci/drm/radeon/r600_hdmi.c

509

dig->afmt->enabled = enable;

sys/dev/pci/drm/radeon/r600_hdmi.c

512

enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);

sys/dev/pci/drm/radeon/radeon.h

1594

void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/radeon.h

1595

void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/radeon.h

1911

void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);

sys/dev/pci/drm/radeon/radeon.h

1964

void (*set_clock_gating)(struct radeon_device *rdev, int enable);

sys/dev/pci/drm/radeon/radeon.h

1973

int (*enable)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

1988

void (*enable_bapm)(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/radeon.h

2810

#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))

sys/dev/pci/drm/radeon/radeon.h

2847

extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);

sys/dev/pci/drm/radeon/radeon.h

2848

extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);

sys/dev/pci/drm/radeon/radeon.h

3002

bool enable, const char *name,

sys/dev/pci/drm/radeon/radeon_asic.c

1087

.enable = &rv6xx_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1180

.enable = &rs780_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1286

.enable = &rv770_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1406

.enable = &cypress_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1500

.enable = &sumo_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1594

.enable = &btc_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1742

.enable = &ni_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

1863

.enable = &trinity_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

2001

.enable = &si_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

2171

.enable = &ci_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.c

2284

.enable = &kv_dpm_enable,

sys/dev/pci/drm/radeon/radeon_asic.h

37

void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);

sys/dev/pci/drm/radeon/radeon_asic.h

43

void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);

sys/dev/pci/drm/radeon/radeon_asic.h

694

void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/radeon_asic.h

922

void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/radeon_atombios.c

3011

void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)

sys/dev/pci/drm/radeon/radeon_atombios.c

3016

args.ucEnable = enable;

sys/dev/pci/drm/radeon/radeon_audio.c

212

if (rdev->audio.funcs->enable)

sys/dev/pci/drm/radeon/radeon_audio.c

213

rdev->audio.funcs->enable(rdev, pin, enable_mask);

sys/dev/pci/drm/radeon/radeon_audio.c

71

.enable = r600_audio_enable,

sys/dev/pci/drm/radeon/radeon_audio.c

77

.enable = r600_audio_enable,

sys/dev/pci/drm/radeon/radeon_audio.c

83

.enable = dce4_audio_enable,

sys/dev/pci/drm/radeon/radeon_audio.c

89

.enable = dce6_audio_enable,

sys/dev/pci/drm/radeon/radeon_audio.h

41

void (*enable)(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_clocks.c

560

void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)

sys/dev/pci/drm/radeon/radeon_clocks.c

564

if (enable) {

sys/dev/pci/drm/radeon/radeon_irq_kms.c

609

bool enable, const char *name, unsigned n)

sys/dev/pci/drm/radeon/radeon_irq_kms.c

614

if (!!(tmp & mask) == enable)

sys/dev/pci/drm/radeon/radeon_irq_kms.c

617

if (enable) {

sys/dev/pci/drm/radeon/radeon_pm.c

1202

void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/radeon_pm.c

1210

enable |= rdev->pm.dpm.sd > 0;

sys/dev/pci/drm/radeon/radeon_pm.c

1211

enable |= rdev->pm.dpm.hd > 0;

sys/dev/pci/drm/radeon/radeon_pm.c

1213

radeon_dpm_powergate_uvd(rdev, !enable);

sys/dev/pci/drm/radeon/radeon_pm.c

1216

if (enable) {

sys/dev/pci/drm/radeon/radeon_pm.c

1244

void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/radeon_pm.c

1246

if (enable) {

sys/dev/pci/drm/radeon/rs600.c

413

unsigned enable = 0;

sys/dev/pci/drm/radeon/rs600.c

430

enable |= 1 << radeon_connector->hpd.hpd;

sys/dev/pci/drm/radeon/rs600.c

433

radeon_irq_kms_enable_hpd(rdev, enable);

sys/dev/pci/drm/radeon/rs780_dpm.c

303

static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/rs780_dpm.c

305

if (enable)

sys/dev/pci/drm/radeon/rs780_dpm.c

313

static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/rs780_dpm.c

315

if (enable)

sys/dev/pci/drm/radeon/rs780_dpm.c

73

static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1170

static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1172

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1255

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1257

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1264

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1266

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1390

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1394

if (enable) {

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1409

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1414

r600_enable_thermal_protection(rdev, enable);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1472

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1474

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1495

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1499

if (enable) {

sys/dev/pci/drm/radeon/rv6xx_dpm.c

329

u32 index, bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

331

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

352

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

354

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

361

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

363

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

370

u32 index, bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

372

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

88

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

93

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

967

bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

971

if (enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

980

static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

982

if (enable) {

sys/dev/pci/drm/radeon/rv740_dpm.c

400

bool enable)

sys/dev/pci/drm/radeon/rv740_dpm.c

402

if (enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

132

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

1335

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

1337

if (enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

134

if (enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

1362

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

1364

rv770_enable_bif_dynamic_pcie_gen2(rdev, enable);

sys/dev/pci/drm/radeon/rv770_dpm.c

1366

if (enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

145

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

149

if (enable) {

sys/dev/pci/drm/radeon/rv770_dpm.c

1853

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

1857

if (enable) {

sys/dev/pci/drm/radeon/rv770_dpm.c

215

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

217

if (enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

71

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

77

if (enable) {

sys/dev/pci/drm/radeon/rv770_dpm.c

773

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

775

if (enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

782

bool enable)

sys/dev/pci/drm/radeon/rv770_dpm.c

786

if (enable) {

sys/dev/pci/drm/radeon/rv770_dpm.h

195

bool enable);

sys/dev/pci/drm/radeon/rv770_dpm.h

211

bool enable);

sys/dev/pci/drm/radeon/rv770_dpm.h

245

bool enable);

sys/dev/pci/drm/radeon/rv770_dpm.h

247

bool enable);

sys/dev/pci/drm/radeon/rv770_dpm.h

249

bool enable);

sys/dev/pci/drm/radeon/rv770_dpm.h

252

bool enable);

sys/dev/pci/drm/radeon/si.c

134

bool enable);

sys/dev/pci/drm/radeon/si.c

3440

static void si_cp_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/si.c

3442

if (enable)

sys/dev/pci/drm/radeon/si.c

5126

bool enable)

sys/dev/pci/drm/radeon/si.c

5132

if (enable)

sys/dev/pci/drm/radeon/si.c

5138

if (!enable) {

sys/dev/pci/drm/radeon/si.c

5210

static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/si.c

5215

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))

sys/dev/pci/drm/radeon/si.c

5235

bool enable)

sys/dev/pci/drm/radeon/si.c

5239

if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {

sys/dev/pci/drm/radeon/si.c

5336

bool enable)

sys/dev/pci/drm/radeon/si.c

5342

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {

sys/dev/pci/drm/radeon/si.c

5376

bool enable)

sys/dev/pci/drm/radeon/si.c

5380

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {

sys/dev/pci/drm/radeon/si.c

5432

bool enable)

sys/dev/pci/drm/radeon/si.c

5436

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {

sys/dev/pci/drm/radeon/si.c

5477

bool enable)

sys/dev/pci/drm/radeon/si.c

5484

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))

sys/dev/pci/drm/radeon/si.c

5494

bool enable)

sys/dev/pci/drm/radeon/si.c

5501

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))

sys/dev/pci/drm/radeon/si.c

5511

bool enable)

sys/dev/pci/drm/radeon/si.c

5516

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {

sys/dev/pci/drm/radeon/si.c

5548

bool enable)

sys/dev/pci/drm/radeon/si.c

5554

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))

sys/dev/pci/drm/radeon/si.c

5566

bool enable)

sys/dev/pci/drm/radeon/si.c

5572

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))

sys/dev/pci/drm/radeon/si.c

5582

bool enable)

sys/dev/pci/drm/radeon/si.c

5588

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))

sys/dev/pci/drm/radeon/si.c

5598

u32 block, bool enable)

sys/dev/pci/drm/radeon/si.c

5603

if (enable) {

sys/dev/pci/drm/radeon/si.c

5614

si_enable_mc_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5615

si_enable_mc_ls(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5619

si_enable_dma_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5623

si_enable_bif_mgls(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5628

si_enable_uvd_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5633

si_enable_hdp_mgcg(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5634

si_enable_hdp_ls(rdev, enable);

sys/dev/pci/drm/radeon/si.c

5828

static void si_enable_lbpw(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/si.c

5833

if (enable)

sys/dev/pci/drm/radeon/si.c

5839

if (!enable) {

sys/dev/pci/drm/radeon/si_dpm.c

2375

bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

2382

if (enable) {

sys/dev/pci/drm/radeon/si_dpm.c

2736

bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

2744

if (enable) {

sys/dev/pci/drm/radeon/si_dpm.c

3259

bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

3263

if (enable) {

sys/dev/pci/drm/radeon/si_dpm.c

3286

static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

3288

if (enable)

sys/dev/pci/drm/radeon/si_dpm.c

3533

bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

3535

if (enable)

sys/dev/pci/drm/radeon/si_dpm.c

3669

static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

3673

if (enable) {

sys/dev/pci/drm/radeon/si_dpm.c

5654

static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

5656

if (enable)

sys/dev/pci/drm/radeon/si_dpm.c

5902

bool enable)

sys/dev/pci/drm/radeon/si_dpm.c

5906

if (enable) {

sys/dev/pci/drm/radeon/sumo_dpm.c

101

static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

109

if (enable) {

sys/dev/pci/drm/radeon/sumo_dpm.c

272

static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

274

if (enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

578

static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

585

enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);

sys/dev/pci/drm/radeon/sumo_dpm.c

588

enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);

sys/dev/pci/drm/radeon/sumo_dpm.c

591

enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);

sys/dev/pci/drm/radeon/sumo_dpm.c

594

enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);

sys/dev/pci/drm/radeon/sumo_dpm.c

615

static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

617

if (enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

713

bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

717

if (enable) {

sys/dev/pci/drm/radeon/sumo_dpm.c

86

static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

867

void sumo_take_smu_control(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

877

if (enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

88

if (enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

886

static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

888

if (enable) {

sys/dev/pci/drm/radeon/sumo_dpm.c

950

static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_dpm.c

952

if (enable) {

sys/dev/pci/drm/radeon/sumo_dpm.h

196

void sumo_take_smu_control(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/sumo_dpm.h

218

void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/sumo_smc.c

205

void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/sumo_smc.c

210

boost_disable |= (enable ? 0 : 1);

sys/dev/pci/drm/radeon/trinity_dpm.c

1041

void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

1047

trinity_dpm_bapm_enable(rdev, enable);

sys/dev/pci/drm/radeon/trinity_dpm.c

355

bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

360

if (enable) {

sys/dev/pci/drm/radeon/trinity_dpm.c

395

bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

397

if (enable) {

sys/dev/pci/drm/radeon/trinity_dpm.c

438

bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

443

if (enable) {

sys/dev/pci/drm/radeon/trinity_dpm.c

455

bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

457

if (enable) {

sys/dev/pci/drm/radeon/trinity_dpm.c

469

bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

473

if (enable) {

sys/dev/pci/drm/radeon/trinity_dpm.c

686

u32 index, bool enable)

sys/dev/pci/drm/radeon/trinity_dpm.c

693

if (enable)

sys/dev/pci/drm/radeon/trinity_dpm.h

121

int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/trinity_dpm.h

122

int trinity_dpm_config(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/trinity_dpm.h

128

bool enable);

sys/dev/pci/drm/radeon/trinity_smc.c

100

if (enable)

sys/dev/pci/drm/radeon/trinity_smc.c

55

int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/trinity_smc.c

57

if (enable)

sys/dev/pci/drm/radeon/trinity_smc.c

63

int trinity_dpm_config(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/trinity_smc.c

65

if (enable)

sys/dev/pci/drm/radeon/trinity_smc.c

98

bool enable)

sys/dev/pci/drm/radeon/vce.h

32

void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/vce.h

33

void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);

sys/dev/pci/drm/radeon/vce_v1_0.c

103

void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/vce_v1_0.c

107

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {

sys/dev/pci/drm/radeon/vce_v2_0.c

112

void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)

sys/dev/pci/drm/radeon/vce_v2_0.c

116

if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {

sys/dev/pci/if_bnxt.c

2378

int enable)

sys/dev/pci/if_bnxt.c

2386

if (enable)

sys/dev/pci/if_bnxt.c

2401

if (enable == 0)

sys/dev/pci/if_bnxt.c

2415

uint32_t index, int enable)

sys/dev/pci/if_bnxt.c

2423

if (enable)

sys/dev/pci/if_bnxt.c

2439

if (enable == 0)

sys/dev/pci/if_bnxt.c

4050

softc->hw_lro.enable = min(softc->hw_lro.enable, 1);

sys/dev/pci/if_bnxt.c

4075

if (softc->hw_lro.enable) {

sys/dev/pci/if_bnxtreg.h

63500

uint8_t enable;

sys/dev/pci/if_ice.c

11054

ice_control_rx_queue(struct ice_vsi *vsi, uint16_t qidx, bool enable)

sys/dev/pci/if_ice.c

11071

if (enable == !!(qrx_ctrl & QRX_CTRL_QENA_STAT_M))

sys/dev/pci/if_ice.c

11074

if (enable)

sys/dev/pci/if_ice.c

11084

sc->sc_dev.dv_xname, pf_q, (enable ? "en" : "dis"));

sys/dev/pci/if_ice.c

11089

if (enable != !!(qrx_ctrl & QRX_CTRL_QENA_STAT_M)) {

sys/dev/pci/if_ice.c

11108

ice_control_all_rx_queues(struct ice_vsi *vsi, bool enable)

sys/dev/pci/if_ice.c

11117

err = ice_control_rx_queue(vsi, i, enable);

sys/dev/pci/if_ice.c

18964

ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,

sys/dev/pci/if_ice.c

18975

if (!enable) {

sys/dev/pci/if_ice.c

22315

uint16_t maxqs, uint8_t owner, bool enable)

sys/dev/pci/if_ice.c

22333

if (!enable) {

sys/dev/pci/if_iwm.c

2460

cmd.enable = 1;

sys/dev/pci/if_iwm.c

2485

cmd.enable = 0;

sys/dev/pci/if_iwm.c

7107

iwm_update_beacon_abort(struct iwm_softc *sc, struct iwm_node *in, int enable)

sys/dev/pci/if_iwm.c

7112

.ba_enable_beacon_abort = htole32(enable),

sys/dev/pci/if_iwm.c

7118

sc->sc_bf.ba_enabled = enable;

sys/dev/pci/if_iwmreg.h

5253

uint8_t enable;

sys/dev/pci/if_iwn.c

4929

cmd.ucode.once.enable = 0xffffffff;

sys/dev/pci/if_iwn.c

6117

cmd.ucode.once.enable = 0xffffffff;

sys/dev/pci/if_iwnreg.h

793

uint32_t enable;

sys/dev/pci/if_iwx.c

6600

iwx_update_beacon_abort(struct iwx_softc *sc, struct iwx_node *in, int enable)

sys/dev/pci/if_iwx.c

6605

.ba_enable_beacon_abort = htole32(enable),

sys/dev/pci/if_iwx.c

6611

sc->sc_bf.ba_enabled = enable;

sys/dev/pci/if_iwxreg.h

7195

uint8_t enable;

sys/dev/pci/if_ixl.c

2621

ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable)

sys/dev/pci/if_ixl.c

2634

SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK :

sys/dev/pci/if_mwx.c

3538

mt7921_mcu_set_mac_enable(struct mwx_softc *sc, int band, int enable)

sys/dev/pci/if_mwx.c

3541

uint8_t enable;

sys/dev/pci/if_mwx.c

3545

.enable = enable,

sys/dev/pci/if_mwx.c

3930

struct mwx_node *mn, int enable)

sys/dev/pci/if_mwx.c

3953

.active = enable,

sys/dev/pci/if_mwx.c

3973

.active = enable,

sys/dev/pci/if_mwx.c

4005

if (enable) {

sys/dev/pci/if_mwx.c

4020

if (enable) {

sys/dev/pci/if_mwx.c

4035

mt7921_mcu_set_sniffer(struct mwx_softc *sc, int enable)

sys/dev/pci/if_mwx.c

4043

uint8_t enable;

sys/dev/pci/if_mwx.c

4045

} enable;

sys/dev/pci/if_mwx.c

4048

.enable = {

sys/dev/pci/if_mwx.c

4051

.enable = enable,

sys/dev/pci/if_mwx.c

4059

mt7921_mcu_set_beacon_filter(struct mwx_softc *sc, int enable)

sys/dev/pci/if_mwx.c

4063

if (enable) {

sys/dev/pci/if_mwx.c

4080

mt7921_mcu_set_bss_pm(struct mwx_softc *sc, int enable)

sys/dev/pci/if_mwx.c

4111

if (rv != 0 || !enable)

sys/dev/pci/if_nfe.c

1591

nfe_wol(struct ifnet *ifp, int enable)

sys/dev/pci/if_nfe.c

1595

if (enable) {

sys/dev/pci/if_oce.c

3060

oce_config_rss(struct oce_softc *sc, int enable)

sys/dev/pci/if_oce.c

3068

if (enable)

sys/dev/pci/if_oce.c

3133

oce_set_promisc(struct oce_softc *sc, int enable)

sys/dev/pci/if_oce.c

3143

if (enable)

sys/dev/pci/if_oce.c

468

int oce_config_rss(struct oce_softc *, int enable);

sys/dev/pci/if_oce.c

471

int oce_set_promisc(struct oce_softc *, int enable);

sys/dev/pci/if_ocereg.h

1312

uint32_t enable;

sys/dev/pci/if_qwx_pci.c

2121

qwx_pci_msi_config(struct qwx_softc *sc, bool enable)

sys/dev/pci/if_qwx_pci.c

2129

if (enable)

sys/dev/pci/if_qwz_pci.c

1988

qwz_pci_msi_config(struct qwz_softc *sc, bool enable)

sys/dev/pci/if_qwz_pci.c

1996

if (enable)

sys/dev/pci/if_rge.c

3714

rge_wol(struct ifnet *ifp, int enable)

sys/dev/pci/if_rge.c

3718

if (enable) {

sys/dev/pci/if_rge.c

3729

if (enable)

sys/dev/pci/if_rge.c

3738

if (enable)

sys/dev/pci/if_vr.c

1661

vr_wol(struct ifnet *ifp, int enable)

sys/dev/pci/if_vr.c

1675

if (enable) {

sys/dev/pci/ixgbe_x550.c

1037

void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,

sys/dev/pci/ixgbe_x550.c

1049

if (enable)

sys/dev/pci/ixgbe_x550.c

74

void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,

sys/dev/pci/pccbb.c

1791

u_int8_t ioctl, enable;

sys/dev/pci/pccbb.c

1809

enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);

sys/dev/pci/pccbb.c

1816

enable |= PCIC_ADDRWIN_ENABLE_IO0;

sys/dev/pci/pccbb.c

1823

enable |= PCIC_ADDRWIN_ENABLE_IO1;

sys/dev/pci/pccbb.c

1827

Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable);

sys/dev/pci/pccbb.c

1840

start_low, start_high, stop_low, stop_high, ioctl, enable);

sys/dev/pci/sdhc_pci.c

328

int enable, dir;

sys/dev/pci/sdhc_pci.c

367

enable = !(misc & GL9755_MISC_SSC_OFF);

sys/dev/pci/sdhc_pci.c

372

pll |= enable ? GL9755_PLL_SSC_EN : 0;

sys/dev/pci/sv.c

269

goto enable;

sys/dev/pci/sv.c

289

goto enable;

sys/dev/pci/sv.c

298

enable:

sys/dev/pci/tga.c

914

if (cursorp->enable)

sys/dev/pci/tga.c

952

cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;

sys/dev/pckbc/pms.c

552

if (pms_protocols[i].enable(sc)) {

sys/dev/pckbc/pms.c

78

int (*enable)(struct pms_softc *);

sys/dev/pckbc/pms.c

839

if (sc->protocol->enable != NULL &&

sys/dev/pckbc/pms.c

840

sc->protocol->enable(sc) == 0)

sys/dev/pcmcia/com_pcmcia.c

286

sc->enable = com_pcmcia_enable;

sys/dev/pcmcia/if_ep_pcmcia.c

332

sc->enable = ep_pcmcia_enable;

sys/dev/pcmcia/if_malo.c

1923

body->enable = 1;

sys/dev/pcmcia/if_malo.c

879

cmalo_intr_mask(struct malo_softc *sc, int enable)

sys/dev/pcmcia/if_malo.c

888

if (enable)

sys/dev/pcmcia/if_malovar.h

195

uint8_t enable;

sys/dev/sbus/cgsix.c

303

curs->enable = sc->sc_curs_enabled;

sys/dev/sbus/cgsix.c

416

sc->sc_curs_enabled = curs->enable;

sys/dev/sdmmc/sdhc.c

803

sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)

sys/dev/sdmmc/sdhc.c

807

if (enable) {

sys/dev/sdmmc/sdmmc_io.c

888

sdmmc_io_set_highspeed(struct sdmmc_function *sf, int enable)

sys/dev/sdmmc/sdmmc_io.c

895

if (enable && !(rv & CCCR_SPEED_SHS))

sys/dev/sdmmc/sdmmc_io.c

898

if (enable)

sys/dev/sdmmc/sdmmcchip.h

76

#define sdmmc_chip_card_intr_mask(tag, handle, enable) \

sys/dev/sdmmc/sdmmcchip.h

77

((tag)->card_intr_mask((handle), (enable)))

sys/dev/usb/dwc2/dwc2_hcdddma.c

243

int enable)

sys/dev/usb/dwc2/dwc2_hcdddma.c

273

if (enable)

sys/dev/usb/dwc2/dwc2_hcdddma.c

287

if (!enable)

sys/dev/usb/if_mtw.c

3023

mtw_wlan_enable(struct mtw_softc *sc, int enable)

sys/dev/usb/if_mtw.c

3028

if (enable) {

sys/dev/usb/ubcmtp.c

642

ubcmtp_raw_mode(struct ubcmtp_softc *sc, int enable)

sys/dev/usb/ubcmtp.c

673

buf[0] = (enable ? UBCMTP_WELLSPRING_MODE_RAW :

sys/dev/usb/ubcmtp.c

676

buf[1] = (enable ? UBCMTP_WELLSPRING9_MODE_RAW :

sys/dev/usb/ucc.c

98

.enable = ucc_enable,

sys/dev/usb/uslhcom.c

209

uslhcom_uart_endis(struct uslhcom_softc *sc, int enable)

sys/dev/usb/uslhcom.c

215

val = enable;

sys/dev/usb/xhci.c

2136

xhci_cmd_slot_control(struct xhci_softc *sc, uint8_t *slotp, int enable)

sys/dev/usb/xhci.c

2145

if (enable)

sys/dev/usb/xhci.c

2158

if (enable)

sys/dev/wscons/wsconsio.h

503

u_int enable; /* enable/disable */

sys/dev/wscons/wskbd.c

814

error = (*sc->sc_accessops->enable)(sc->sc_accesscookie, on);

sys/dev/wscons/wskbdvar.h

45

int (*enable)(void *, int);

sys/dev/wscons/wsmouse.c

383

error = (*sc->sc_accessops->enable)(sc->sc_accesscookie);

sys/dev/wscons/wsmousevar.h

66

int (*enable)(void *);

sys/net80211/ieee80211.c

294

ieee80211_configure_ampdu_tx(struct ieee80211com *ic, int enable)

sys/net80211/ieee80211.c

303

if (enable)

usr.bin/skeyinit/skeyinit.c

109

if (argc > 1 || (enable && argc))

usr.bin/skeyinit/skeyinit.c

113

if (enable) {

usr.bin/skeyinit/skeyinit.c

114

enable_db(enable);

usr.bin/skeyinit/skeyinit.c

47

int rval, i, l, n, defaultsetup, rmkey, hexmode, enable;

usr.bin/skeyinit/skeyinit.c

56

n = rmkey = hexmode = enable = 0;

usr.bin/skeyinit/skeyinit.c

89

enable = -1;

usr.bin/skeyinit/skeyinit.c

92

enable = 1;

usr.sbin/config/cmd.c

156

enable(a);

usr.sbin/config/ukc.h

105

void enable(int);

usr.sbin/config/ukcutil.c

1431

enable(devno);

usr.sbin/config/ukcutil.c

777

enable(i);

usr.sbin/config/ukcutil.c

896

enable(i);

usr.sbin/config/ukcutil.c

924

enable(totdev+1+i);

usr.sbin/eigrpd/interface.c

643

if_set_ipv4_recvif(int fd, int enable)

usr.sbin/eigrpd/interface.c

645

if (setsockopt(fd, IPPROTO_IP, IP_RECVIF, &enable,

usr.sbin/eigrpd/interface.c

646

sizeof(enable)) == -1) {

usr.sbin/eigrpd/interface.c

744

if_set_ipv6_pktinfo(int fd, int enable)

usr.sbin/eigrpd/interface.c

746

if (setsockopt(fd, IPPROTO_IPV6, IPV6_RECVPKTINFO, &enable,

usr.sbin/eigrpd/interface.c

747

sizeof(enable)) == -1) {

usr.sbin/ldpd/init.c

223

send_capability(struct nbr *nbr, uint16_t capability, int enable)

usr.sbin/ldpd/init.c

241

err |= gen_cap_twcard_tlv(buf, enable);

usr.sbin/ldpd/init.c

244

err |= gen_cap_unotif_tlv(buf, enable);

usr.sbin/ldpd/init.c

271

int enable = 0;

usr.sbin/ldpd/init.c

318

enable = reserved & STATE_BIT;

usr.sbin/ldpd/init.c

319

if (enable)

usr.sbin/ldpd/init.c

326

(enable) ? "announced" : "withdrew");

usr.sbin/ldpd/init.c

343

enable = reserved & STATE_BIT;

usr.sbin/ldpd/init.c

344

if (enable)

usr.sbin/ldpd/init.c

351

inet_ntoa(nbr->id), (enable) ? "announced" :

usr.sbin/ldpd/init.c

414

gen_cap_twcard_tlv(struct ibuf *buf, int enable)

usr.sbin/ldpd/init.c

421

if (enable)

usr.sbin/ldpd/init.c

428

gen_cap_unotif_tlv(struct ibuf *buf, int enable)

usr.sbin/ldpd/init.c

435

if (enable)

usr.sbin/ldpd/socket.c

195

sock_set_reuse(int fd, int enable)

usr.sbin/ldpd/socket.c

197

if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &enable,

usr.sbin/ldpd/socket.c

207

sock_set_bindany(int fd, int enable)

usr.sbin/ldpd/socket.c

209

if (setsockopt(fd, SOL_SOCKET, SO_BINDANY, &enable,

usr.sbin/ldpd/socket.c

230

sock_set_ipv4_recvif(int fd, int enable)

usr.sbin/ldpd/socket.c

232

if (setsockopt(fd, IPPROTO_IP, IP_RECVIF, &enable,

usr.sbin/ldpd/socket.c

233

sizeof(enable)) == -1) {

usr.sbin/ldpd/socket.c

319

sock_set_ipv6_pktinfo(int fd, int enable)

usr.sbin/ldpd/socket.c

321

if (setsockopt(fd, IPPROTO_IPV6, IPV6_RECVPKTINFO, &enable,

usr.sbin/ldpd/socket.c

322

sizeof(enable)) == -1) {

usr.sbin/lpr/lpc/cmds.c

719

startpr(int enable)

usr.sbin/lpr/lpc/cmds.c

735

if (enable && stat(line, &stbuf) >= 0) {

usr.sbin/lpr/lpc/cmds.c

736

if (enable == 2)

usr.sbin/lpr/lpc/cmdtab.c

57

{ "enable", enablehelp, enable, 1 },

usr.sbin/lpr/lpc/extern.h

42

void enable(int, char **);

usr.sbin/ospf6d/interface.c

839

if_set_ipv6_pktinfo(int fd, int enable)

usr.sbin/ospf6d/interface.c

841

if (setsockopt(fd, IPPROTO_IPV6, IPV6_RECVPKTINFO, &enable,

usr.sbin/ospf6d/interface.c

842

sizeof(enable)) == -1) {

usr.sbin/ospfd/interface.c

664

if_set_recvif(int fd, int enable)

usr.sbin/ospfd/interface.c

666

if (setsockopt(fd, IPPROTO_IP, IP_RECVIF, &enable,

usr.sbin/ospfd/interface.c

667

sizeof(enable)) == -1) {

usr.sbin/relayd/pfe_filter.c

334

sync_ruleset(struct relayd *env, struct rdr *rdr, int enable)

usr.sbin/relayd/pfe_filter.c

358

if (!enable) {

usr.sbin/smtpd/mproc.c

100

if (p->enable == 1) {

usr.sbin/smtpd/mproc.c

104

p->enable = 0;

usr.sbin/smtpd/mproc.c

114

if (p->enable)

usr.sbin/smtpd/mproc.c

88

if (p->enable == 0) {

usr.sbin/smtpd/mproc.c

92

p->enable = 1;

usr.sbin/smtpd/smtpd.h

989

int enable;

usr.sbin/snmpd/snmpd.c

305

const int enable = 1;

usr.sbin/snmpd/snmpd.c

312

if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &enable,

usr.sbin/snmpd/snmpd.c

313

sizeof(enable)) == -1) {

usr.sbin/unbound/daemon/remote.c

3612

do_rpz_enable_disable(RES* ssl, struct worker* worker, char* arg, int enable) {

usr.sbin/unbound/daemon/remote.c

3638

if (enable) {