include/stdlib.h

106

div_t div(int, int);

lib/libc/arch/sparc64/fpu/fpu_qp.c

176

_QP_OP(div)

lib/libc/hidden/stdlib.h

86

PROTO_NORMAL(div);

lib/libc/stdlib/div.c

72

DEF_STRONG(div);

lib/libc/stdlib/random.c

217

val = div(state[i-1], 127773);

lib/libform/frm_driver.c

490

*((div_t *) & (form->currow)) = div(idx, field->dcols);

sys/arch/arm64/dev/aplnco.c

172

uint32_t div, parent_freq;

sys/arch/arm64/dev/aplnco.c

181

div = HREAD4(sc, NCO_DIV(idx));

sys/arch/arm64/dev/aplnco.c

182

coarse = NCO_DIV_COARSE(div);

sys/arch/arm64/dev/aplnco.c

183

fine = NCO_DIV_FINE(div);

sys/arch/arm64/dev/aplnco.c

186

div = (coarse << 2) + fine;

sys/arch/arm64/dev/aplnco.c

193

div64 = (int64_t)div * (inc1 - inc2) + inc1;

sys/arch/arm64/dev/aplnco.c

205

uint32_t div, parent_freq;

sys/arch/arm64/dev/aplnco.c

217

div = (parent_freq * 2) / freq;

sys/arch/arm64/dev/aplnco.c

218

coarse = (div >> 2) - 2;

sys/arch/arm64/dev/aplnco.c

222

inc1 = 2 * parent_freq - div * freq;

sys/arch/arm64/dev/aplnco.c

226

div = (coarse << 2) + (div & 3);

sys/arch/arm64/dev/aplnco.c

230

HWRITE4(sc, NCO_DIV(idx), div);

sys/arch/arm64/dev/aplnco.c

37

#define NCO_DIV_COARSE(div) ((div >> 2) & NCO_LFSR_MASK)

sys/arch/arm64/dev/aplnco.c

38

#define NCO_DIV_FINE(div) (div & 0x3)

sys/arch/arm64/dev/aplspi.c

198

uint32_t div = 0;

sys/arch/arm64/dev/aplspi.c

200

while ((freq * div) < sc->sc_pfreq)

sys/arch/arm64/dev/aplspi.c

201

div++;

sys/arch/arm64/dev/aplspi.c

202

if (div < SPI_CLKDIV_MIN)

sys/arch/arm64/dev/aplspi.c

203

div = SPI_CLKDIV_MIN;

sys/arch/arm64/dev/aplspi.c

204

if (div > SPI_CLKDIV_MAX)

sys/arch/arm64/dev/aplspi.c

205

div = SPI_CLKDIV_MAX;

sys/arch/arm64/dev/aplspi.c

207

return div << 1;

sys/arch/arm64/dev/rpiclock.c

272

uint64_t div;

sys/arch/arm64/dev/rpiclock.c

287

div = DIV_ROUND((uint64_t)freq << 32, parent_freq);

sys/arch/arm64/dev/rpiclock.c

290

div += (1 << (32 - 24 - 1));

sys/arch/arm64/dev/rpiclock.c

292

fbdiv_int = div >> 32;

sys/arch/arm64/dev/rpiclock.c

293

fbdiv_frac = (div >> (32 - 24)) & 0xffffff;

sys/arch/arm64/dev/rpiclock.c

371

uint32_t sec, div;

sys/arch/arm64/dev/rpiclock.c

374

div = (sec & PLL_SEC_DIV_MASK) >> PLL_SEC_DIV_SHIFT;

sys/arch/arm64/dev/rpiclock.c

375

if (div == 0)

sys/arch/arm64/dev/rpiclock.c

378

return freq / div;

sys/arch/arm64/dev/rpiclock.c

386

uint32_t sec, div;

sys/arch/arm64/dev/rpiclock.c

393

div = DIV_ROUND(parent_freq, freq);

sys/arch/arm64/dev/rpiclock.c

394

div = MAX(div, 8);

sys/arch/arm64/dev/rpiclock.c

395

div = MIN(div, 19);

sys/arch/arm64/dev/rpiclock.c

399

sec |= (div << PLL_SEC_DIV_SHIFT);

sys/arch/arm64/dev/rpiclock.c

402

delay((10 * div * 1000000) / parent_freq);

sys/arch/arm64/dev/rpiclock.c

413

uint32_t parent_freq, div;

sys/arch/arm64/dev/rpiclock.c

417

div = (parent_freq + freq - 1) / freq;

sys/arch/arm64/dev/rpiclock.c

418

if (div == 0)

sys/arch/arm64/dev/rpiclock.c

420

return parent_freq / div;

sys/arch/arm64/dev/rpiclock.c

429

uint32_t ctrl, sel, div;

sys/arch/arm64/dev/rpiclock.c

472

div = HREAD4(sc, clk->div_int_reg);

sys/arch/arm64/dev/rpiclock.c

473

if (div == 0)

sys/arch/arm64/dev/rpiclock.c

476

return freq / div;

sys/arch/arm64/dev/rpiclock.c

487

uint32_t ctrl, div, sel;

sys/arch/arm64/dev/rpiclock.c

562

div = (parent_freq + freq - 1) / freq;

sys/arch/arm64/dev/rpiclock.c

563

HWRITE4(sc, clk->div_int_reg, div);

sys/arch/armv7/exynos/exclock.c

236

uint32_t reg, div, mux;

sys/arch/armv7/exynos/exclock.c

249

div = ((reg >> 20) & ((1 << 10) - 1)) + 1;

sys/arch/armv7/exynos/exclock.c

263

return exynos5420_get_frequency(sc, &idx) / div;

sys/arch/armv7/exynos/exclock.c

452

uint32_t div, armclk, arm_ratio, arm2_ratio;

sys/arch/armv7/exynos/exclock.c

454

div = HREAD4(sc, CLOCK_CLK_DIV_CPU0);

sys/arch/armv7/exynos/exclock.c

457

arm_ratio = (div >> 0) & 0x7;

sys/arch/armv7/exynos/exclock.c

458

arm2_ratio = (div >> 28) & 0x7;

sys/arch/armv7/exynos/exclock.c

469

uint32_t div, kfc_ratio;

sys/arch/armv7/exynos/exclock.c

471

div = HREAD4(sc, EXYNOS5420_DIV_KFC0);

sys/arch/armv7/exynos/exclock.c

474

kfc_ratio = (div >> 0) & 0x7;

sys/arch/armv7/exynos/exclock.c

483

uint32_t aclk_66, aclk_66_pre, div, ratio;

sys/arch/armv7/exynos/exclock.c

485

div = HREAD4(sc, CLOCK_CLK_DIV_TOP1);

sys/arch/armv7/exynos/exclock.c

486

ratio = (div >> 24) & 0x7;

sys/arch/armv7/exynos/exclock.c

488

div = HREAD4(sc, CLOCK_CLK_DIV_TOP0);

sys/arch/armv7/exynos/exclock.c

489

ratio = (div >> 0) & 0x7;

sys/arch/armv7/exynos/exiic.c

187

uint32_t freq, div = 0, pres = 16;

sys/arch/armv7/exynos/exiic.c

195

while ((freq / pres / (div + 1)) > speed)

sys/arch/armv7/exynos/exiic.c

196

div++;

sys/arch/armv7/exynos/exiic.c

199

sc->frequency = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);

sys/arch/armv7/omap/amdisplay.c

560

uint64_t mul, div, i, j, delta, min_delta;

sys/arch/armv7/omap/amdisplay.c

568

div = j;

sys/arch/armv7/omap/amdisplay.c

575

div--;

sys/arch/armv7/omap/amdisplay.c

577

prcm_setclock(4, div);

sys/arch/armv7/omap/nxphdmi.c

630

uint8_t reg, div;

sys/arch/armv7/omap/nxphdmi.c

677

div = 148500 / mode->dot_clock;

sys/arch/armv7/omap/nxphdmi.c

678

if (div != 0) {

sys/arch/armv7/omap/nxphdmi.c

679

div--;

sys/arch/armv7/omap/nxphdmi.c

680

if (div > 3)

sys/arch/armv7/omap/nxphdmi.c

681

div = 3;

sys/arch/armv7/omap/nxphdmi.c

706

nxphdmi_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |

sys/arch/armv7/omap/ommmc.c

690

int div;

sys/arch/armv7/omap/ommmc.c

693

for (div = 1; div <= maxclk; div++)

sys/arch/armv7/omap/ommmc.c

694

if ((sc->clkbase / div) <= freq) {

sys/arch/armv7/omap/ommmc.c

695

return (div);

sys/arch/armv7/omap/ommmc.c

714

int div;

sys/arch/armv7/omap/ommmc.c

741

if ((div = ommmc_clock_divisor(sc, freq)) < 0) {

sys/arch/armv7/omap/ommmc.c

748

reg |= div << MMCHS_SYSCTL_CLKD_SH;

sys/arch/armv7/xilinx/zqclock.c

181

uint32_t ctl, div, freq;

sys/arch/armv7/xilinx/zqclock.c

191

div = SLCR_CLK_CTRL_DIVISOR(ctl);

sys/arch/armv7/xilinx/zqclock.c

193

div *= SLCR_CLK_CTRL_DIVISOR1(ctl);

sys/arch/armv7/xilinx/zqclock.c

196

freq = (freq + div / 2) / div;

sys/arch/armv7/xilinx/zqclock.c

218

uint32_t ctl, div, div1, maxdiv1, si;

sys/arch/armv7/xilinx/zqclock.c

243

div = (pllf + (freq * div1 / 2)) / (freq * div1);

sys/arch/armv7/xilinx/zqclock.c

244

if (div > SLCR_DIV_MASK)

sys/arch/armv7/xilinx/zqclock.c

246

if (div == 0)

sys/arch/armv7/xilinx/zqclock.c

249

f = (pllf + (div * div1 / 2)) / (div * div1);

sys/arch/armv7/xilinx/zqclock.c

270

div = (best_pllf + (freq * div1 / 2)) / (freq * div1);

sys/arch/armv7/xilinx/zqclock.c

272

KASSERT(div > 0 && div <= SLCR_DIV_MASK);

sys/arch/armv7/xilinx/zqclock.c

280

ctl |= (div & SLCR_DIV_MASK) << SLCR_CLK_CTRL_DIVISOR_SHIFT;

sys/arch/i386/i386/machdep.c

3016

extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),

sys/arch/i386/i386/machdep.c

3113

setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL);

sys/arch/octeon/dev/octuctl.c

125

int div;

sys/arch/octeon/dev/octuctl.c

130

div = octeon_ioclock_speed() / UCTL_CLK_TARGET_FREQ;

sys/arch/octeon/dev/octuctl.c

150

if (div < validdiv[i]) {

sys/arch/octeon/dev/octuctl.c

151

div = lastdiv;

sys/arch/octeon/dev/octuctl.c

158

ctl |= (div << UCTL_CLK_RST_CTL_H_DIV_SHIFT);

sys/arch/riscv64/dev/mpfclock.c

163

uint32_t div, shift;

sys/arch/riscv64/dev/mpfclock.c

186

div = 1U << ((sc->sc_clkcfg >> shift) & CLOCK_CONFIG_CR_DIV_MASK);

sys/arch/riscv64/dev/mpfclock.c

188

return sc->sc_refclk / div;

sys/arch/riscv64/dev/mpfiic.c

109

uint32_t div;

sys/arch/riscv64/dev/mpfiic.c

152

if (clock_freq / mpfiic_clk_divs[i].div <= bus_freq)

sys/arch/riscv64/dev/mpfiic.c

155

sc->sc_bus_freq = clock_freq / mpfiic_clk_divs[i].div;

sys/arch/riscv64/dev/sfclock.c

139

uint32_t reg, div;

sys/arch/riscv64/dev/sfclock.c

152

div = HREAD4(sc, HFPCLK_DIV) + 2;

sys/arch/riscv64/dev/sfclock.c

154

return sfclock_get_frequency(sc, &idx) / div;

sys/arch/riscv64/dev/sfuart.c

286

uint32_t div;

sys/arch/riscv64/dev/sfuart.c

315

div = (sc->sc_frequency + ospeed / 2) / ospeed;

sys/arch/riscv64/dev/sfuart.c

316

if (div < 16 || div > 65536)

sys/arch/riscv64/dev/sfuart.c

318

HWRITE4(sc, UART_DIV, div - 1);

sys/arch/riscv64/dev/stfclock.c

1050

div = (parent_freq + freq / 2) / freq;

sys/arch/riscv64/dev/stfclock.c

1051

if (div == 0)

sys/arch/riscv64/dev/stfclock.c

1052

div = 1;

sys/arch/riscv64/dev/stfclock.c

1055

reg |= (div << CLKDIV_SHIFT);

sys/arch/riscv64/dev/stfclock.c

331

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

352

div = (reg & CLKDIV_MASK) >> CLKDIV_SHIFT;

sys/arch/riscv64/dev/stfclock.c

425

div = 1;

sys/arch/riscv64/dev/stfclock.c

429

div = 1;

sys/arch/riscv64/dev/stfclock.c

433

div = 1;

sys/arch/riscv64/dev/stfclock.c

447

return freq / div;

sys/arch/riscv64/dev/stfclock.c

501

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

516

div = (reg & CLKDIV_MASK) >> CLKDIV_SHIFT;

sys/arch/riscv64/dev/stfclock.c

528

div = 1;

sys/arch/riscv64/dev/stfclock.c

535

div = 1;

sys/arch/riscv64/dev/stfclock.c

542

if (div == 0) {

sys/arch/riscv64/dev/stfclock.c

548

return freq / div;

sys/arch/riscv64/dev/stfclock.c

557

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

590

div = (parent_freq + freq / 2) / freq;

sys/arch/riscv64/dev/stfclock.c

591

if (div == 0)

sys/arch/riscv64/dev/stfclock.c

592

div = 1;

sys/arch/riscv64/dev/stfclock.c

595

reg |= (div << CLKDIV_SHIFT);

sys/arch/riscv64/dev/stfclock.c

864

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

881

div = (reg & CLKDIV_MASK) >> CLKDIV_SHIFT;

sys/arch/riscv64/dev/stfclock.c

915

div = 1;

sys/arch/riscv64/dev/stfclock.c

927

div = 1;

sys/arch/riscv64/dev/stfclock.c

937

div = 1;

sys/arch/riscv64/dev/stfclock.c

952

div = 1;

sys/arch/riscv64/dev/stfclock.c

959

div = 1;

sys/arch/riscv64/dev/stfclock.c

963

div = 1;

sys/arch/riscv64/dev/stfclock.c

970

if (div == 0) {

sys/arch/riscv64/dev/stfclock.c

976

return freq / div;

sys/arch/riscv64/dev/stfclock.c

985

uint32_t reg, div, mux;

sys/arch/riscv64/riscv64/db_instruction.h

2238

DECLARE_INSN(div, MATCH_DIV, MASK_DIV)

sys/arch/sparc64/sparc64/cpu.c

503

hummingbird_estar_mode(int div)

sys/arch/sparc64/sparc64/cpu.c

505

switch(div) {

sys/arch/sparc64/sparc64/cpu.c

544

hummingbird_set_refresh_count(int div, int new_div)

sys/arch/sparc64/sparc64/cpu.c

560

if (new_div > div && (reg & HB_MC0_SELF_REFRESH) == 0) {

sys/arch/sparc64/sparc64/cpu.c

562

((count + new_count) * 1000000UL * div) / cpu_clockrate[0];

sys/arch/sparc64/sparc64/cpu.c

573

int div, new_div, i;

sys/arch/sparc64/sparc64/cpu.c

588

div = hummingbird_div(estar_mode);

sys/arch/sparc64/sparc64/cpu.c

624

hummingbird_set_refresh_count(div, 2);

sys/arch/sparc64/sparc64/cpu.c

630

} else if (div < new_div) {

sys/arch/sparc64/sparc64/cpu.c

631

hummingbird_set_refresh_count(div, new_div);

sys/arch/sparc64/sparc64/cpu.c

634

} else if (div > new_div) {

sys/arch/sparc64/sparc64/cpu.c

637

hummingbird_set_refresh_count(div, new_div);

sys/dev/fdt/amlclock.c

208

uint32_t reg, mux, div;

sys/dev/fdt/amlclock.c

220

div = (reg & HHI_SYS_CPU_CLK_POSTMUX1) ?

sys/dev/fdt/amlclock.c

224

div = (reg & HHI_SYS_CPU_CLK_POSTMUX0) ?

sys/dev/fdt/amlclock.c

230

return sc->sc_xtal / div;

sys/dev/fdt/amlclock.c

240

return amlclock_get_frequency(sc, &idx) / div;

sys/dev/fdt/amlclock.c

247

uint32_t reg, div;

sys/dev/fdt/amlclock.c

288

div = 2;

sys/dev/fdt/amlclock.c

290

while (parent_freq / div > freq)

sys/dev/fdt/amlclock.c

291

div++;

sys/dev/fdt/amlclock.c

292

while ((div % 2) != 0 && (div % 3) != 0)

sys/dev/fdt/amlclock.c

293

div++;

sys/dev/fdt/amlclock.c

294

if (div > 32)

sys/dev/fdt/amlclock.c

296

if ((div % 2) == 0) {

sys/dev/fdt/amlclock.c

298

div /= 2;

sys/dev/fdt/amlclock.c

301

div /= 3;

sys/dev/fdt/amlclock.c

320

reg |= ((div - 1) << HHI_SYS_CPU_CLK_MUX0_DIVN_TCNT_SHIFT);

sys/dev/fdt/amlclock.c

324

if (div != 1)

sys/dev/fdt/amlclock.c

351

reg |= ((div - 1) << HHI_SYS_CPU_CLK_MUX1_DIVN_TCNT_SHIFT);

sys/dev/fdt/amlclock.c

355

if (div != 1)

sys/dev/fdt/amlclock.c

375

uint32_t reg, div;

sys/dev/fdt/amlclock.c

383

div = 1;

sys/dev/fdt/amlclock.c

384

while ((div * (uint64_t)freq) / sc->sc_xtal < 128)

sys/dev/fdt/amlclock.c

385

div *= 2;

sys/dev/fdt/amlclock.c

386

if (div > 128)

sys/dev/fdt/amlclock.c

388

m = (div * (uint64_t)freq) / sc->sc_xtal;

sys/dev/fdt/amlclock.c

397

reg |= ((fls(div) - 1) << HHI_SYS_DPLL_OD_SHIFT);

sys/dev/fdt/amlclock.c

420

uint32_t reg, mux, div;

sys/dev/fdt/amlclock.c

426

div = 1 << HHI_SYS_DPLL_OD(reg);

sys/dev/fdt/amlclock.c

429

return (((uint64_t)sc->sc_xtal * m) / n) / div;

sys/dev/fdt/amlclock.c

432

div = 1 << HHI_SYS_DPLL_OD(reg);

sys/dev/fdt/amlclock.c

435

return (((uint64_t)sc->sc_xtal * m) / n) / div;

sys/dev/fdt/amlclock.c

452

div = ((reg >> 0) & 0x7f) + 1;

sys/dev/fdt/amlclock.c

455

return sc->sc_xtal / div;

sys/dev/fdt/amlclock.c

477

return amlclock_get_frequency(sc, &idx) / div;

sys/dev/fdt/amlclock.c

481

div = ((reg >> 0) & 0x7f) + 1;

sys/dev/fdt/amlclock.c

484

return sc->sc_xtal / div;

sys/dev/fdt/amlclock.c

500

return amlclock_get_frequency(sc, &idx) / div;

sys/dev/fdt/amlclock.c

504

div = ((reg >> 16) & 0x7f) + 1;

sys/dev/fdt/amlclock.c

507

return sc->sc_xtal / div;

sys/dev/fdt/amlclock.c

523

return amlclock_get_frequency(sc, &idx) / div;

sys/dev/fdt/amlclock.c

527

div = ((reg >> 0) & 0x7f) + 1;

sys/dev/fdt/amlclock.c

530

return sc->sc_xtal / div;

sys/dev/fdt/amlclock.c

546

return amlclock_get_frequency(sc, &idx) / div;

sys/dev/fdt/amliic.c

109

uint32_t div, divl, divh;

sys/dev/fdt/amliic.c

134

div = clock_speed / bus_speed / 4;

sys/dev/fdt/amliic.c

135

divl = div & 0x3ff;

sys/dev/fdt/amliic.c

136

divh = div >> 10;

sys/dev/fdt/amlmmc.c

506

uint32_t div, clock;

sys/dev/fdt/amlmmc.c

525

div = (sc->sc_clkin0 + freq - 1) / freq;

sys/dev/fdt/amlmmc.c

526

clock = SD_EMMC_CLOCK_CLK_SRC_24M | div;

sys/dev/fdt/amlmmc.c

528

div = (sc->sc_clkin1 + freq - 1) / freq;

sys/dev/fdt/amlmmc.c

529

clock = SD_EMMC_CLOCK_CLK_SRC_FCLK | div;

sys/dev/fdt/amlmmc.c

531

if (div > SD_EMMC_CLOCK_DIV_MAX)

sys/dev/fdt/amlmmc.c

773

uint32_t adjust, cfg, div;

sys/dev/fdt/amlmmc.c

790

div = HREAD4(sc, SD_EMMC_CLOCK) & SD_EMMC_CLOCK_DIV_MAX;

sys/dev/fdt/amlmmc.c

796

for (delay = 0; delay < div; delay++) {

sys/dev/fdt/bcm2835_bsc.c

112

uint32_t div, fedl, redl;

sys/dev/fdt/bcm2835_bsc.c

137

div = clock_speed / bus_speed;

sys/dev/fdt/bcm2835_bsc.c

138

if (div & 1)

sys/dev/fdt/bcm2835_bsc.c

139

div++;

sys/dev/fdt/bcm2835_bsc.c

140

fedl = MAX(div / 16, 1);

sys/dev/fdt/bcm2835_bsc.c

141

redl = MAX(div / 4, 1);

sys/dev/fdt/bcm2835_bsc.c

142

HWRITE4(sc, BSC_DIV, div);

sys/dev/fdt/bcm2835_sdhost.c

369

int div;

sys/dev/fdt/bcm2835_sdhost.c

372

div = SDCDIV_MASK;

sys/dev/fdt/bcm2835_sdhost.c

374

div = sc->sc_rate / target_rate;

sys/dev/fdt/bcm2835_sdhost.c

375

if (div < 2)

sys/dev/fdt/bcm2835_sdhost.c

376

div = 2;

sys/dev/fdt/bcm2835_sdhost.c

377

if ((sc->sc_rate / div) > target_rate)

sys/dev/fdt/bcm2835_sdhost.c

378

div++;

sys/dev/fdt/bcm2835_sdhost.c

379

div -= 2;

sys/dev/fdt/bcm2835_sdhost.c

380

if (div > SDCDIV_MASK)

sys/dev/fdt/bcm2835_sdhost.c

381

div = SDCDIV_MASK;

sys/dev/fdt/bcm2835_sdhost.c

384

bcmsdhost_write(sc, SDCDIV, div);

sys/dev/fdt/dwmmc.c

293

uint32_t freq = 0, div = 0;

sys/dev/fdt/dwmmc.c

351

div = 1;

sys/dev/fdt/dwmmc.c

354

div = 7;

sys/dev/fdt/dwmmc.c

362

clock_set_frequency(faa->fa_node, "ciu", (div + 1) * freq);

sys/dev/fdt/dwmmc.c

372

div = OF_getpropint(faa->fa_node, "samsung,dw-mshc-ciu-div", div);

sys/dev/fdt/dwmmc.c

373

sc->sc_clkbase /= (div + 1);

sys/dev/fdt/dwmmc.c

663

int div = 0, timeout;

sys/dev/fdt/dwmmc.c

673

for (div = 1; div < 256; div++)

sys/dev/fdt/dwmmc.c

674

if (sc->sc_clkbase / (2 * 1000 * div) <= freq)

sys/dev/fdt/dwmmc.c

677

HWRITE4(sc, SDMMC_CLKDIV, div);

sys/dev/fdt/hiclock.c

230

uint32_t reg, freq, div;

sys/dev/fdt/hiclock.c

270

div = (reg >> 0) & 0xf;

sys/dev/fdt/hiclock.c

273

return freq / (div + 1);

sys/dev/fdt/if_cad.c

662

uint32_t div, netcfg;

sys/dev/fdt/if_cad.c

695

for (div = 0; div < nitems(mdcclk_divs) - 1; div++) {

sys/dev/fdt/if_cad.c

696

if (freq / mdcclk_divs[div] <= 2500000)

sys/dev/fdt/if_cad.c

699

KASSERT(div < nitems(mdcclk_divs));

sys/dev/fdt/if_cad.c

703

netcfg |= div << GEM_NETCFG_MDCCLKDIV_SHIFT;

sys/dev/fdt/imxanatop.c

263

uint32_t div;

sys/dev/fdt/imxanatop.c

272

div = HREAD4(sc, ANALOG_PLL_ARM)

sys/dev/fdt/imxanatop.c

274

return (freq * div) / 2;

sys/dev/fdt/imxanatop.c

276

div = HREAD4(sc, ANALOG_PLL_SYS)

sys/dev/fdt/imxanatop.c

278

return freq * (20 + (div << 1));

sys/dev/fdt/imxanatop.c

280

div = HREAD4(sc, ANALOG_PLL_USB2)

sys/dev/fdt/imxanatop.c

282

return freq * (20 + (div << 1));

sys/dev/fdt/imxccm.c

1307

uint64_t div;

sys/dev/fdt/imxccm.c

1319

div = 0;

sys/dev/fdt/imxccm.c

1320

while (parent_freq / (div + 1) > freq)

sys/dev/fdt/imxccm.c

1321

div++;

sys/dev/fdt/imxccm.c

1324

reg |= (div << sc->sc_divs[idx].shift);

sys/dev/fdt/imxccm.c

1497

uint32_t div, pre, reg, parent;

sys/dev/fdt/imxccm.c

1510

div = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

1511

div = div >> sc->sc_divs[idx].shift;

sys/dev/fdt/imxccm.c

1512

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1514

return imxccm_get_frequency(sc, &parent) / (div + 1);

sys/dev/fdt/imxccm.c

1560

div = reg >> sc->sc_divs[idx].shift;

sys/dev/fdt/imxccm.c

1561

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1564

return ((freq / (pre + 1)) / (div + 1));

sys/dev/fdt/imxccm.c

1612

div = reg >> sc->sc_divs[idx].shift;

sys/dev/fdt/imxccm.c

1613

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1616

return ((freq / (pre + 1)) / (div + 1));

sys/dev/fdt/imxccm.c

1676

div = reg >> sc->sc_divs[idx].shift;

sys/dev/fdt/imxccm.c

1677

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1680

return ((freq / (pre + 1)) / (div + 1));

sys/dev/fdt/imxccm.c

1750

uint32_t reg, div, parent, parent_freq;

sys/dev/fdt/imxccm.c

1832

div = 0;

sys/dev/fdt/imxccm.c

1833

while (parent_freq / (div + 1) > freq)

sys/dev/fdt/imxccm.c

1834

div++;

sys/dev/fdt/imxccm.c

1837

reg |= (div << sc->sc_divs[idx].shift);

sys/dev/fdt/imxccm.c

654

uint64_t main_div, pre_div, post_div, div;

sys/dev/fdt/imxccm.c

664

div = 1;

sys/dev/fdt/imxccm.c

683

freq = freq / (pre_div * (1 << post_div) * div);

sys/dev/fdt/imxesdhc.c

686

int div, pre_div, cur_freq, s;

sys/dev/fdt/imxesdhc.c

701

for (div = 1; div <= 16; div++)

sys/dev/fdt/imxesdhc.c

702

if ((sc->clkbase / (div * pre_div)) <= freq)

sys/dev/fdt/imxesdhc.c

705

div -= 1;

sys/dev/fdt/imxesdhc.c

708

cur_freq = sc->clkbase / (pre_div * 2) / (div + 1);

sys/dev/fdt/imxesdhc.c

720

(div << SDHC_SYS_CTRL_CLOCK_DIV_SHIFT) |

sys/dev/fdt/mvclock.c

475

uint64_t mult, div, freq;

sys/dev/fdt/mvclock.c

518

div = reg;

sys/dev/fdt/mvclock.c

520

if (div == 0)

sys/dev/fdt/mvclock.c

521

div = 1;

sys/dev/fdt/mvclock.c

522

div *= 1 << vcodiv;

sys/dev/fdt/mvclock.c

525

return (freq * mult) / div;

sys/dev/fdt/ociic.c

129

uint32_t div;

sys/dev/fdt/ociic.c

156

div = (clock_speed / (5 * bus_speed));

sys/dev/fdt/ociic.c

157

if (div > 0)

sys/dev/fdt/ociic.c

158

div -= 1;

sys/dev/fdt/ociic.c

159

if (div > 0xffff)

sys/dev/fdt/ociic.c

160

div = 0xffff;

sys/dev/fdt/ociic.c

162

ociic_write(sc, I2C_PRER_LO, div & 0xff);

sys/dev/fdt/ociic.c

163

ociic_write(sc, I2C_PRER_HI, div >> 8);

sys/dev/fdt/rkclock.c

1229

uint32_t old_freq, div;

sys/dev/fdt/rkclock.c

1241

div = 1;

sys/dev/fdt/rkclock.c

1242

while (freq / (div + 1) > 300000000)

sys/dev/fdt/rkclock.c

1243

div++;

sys/dev/fdt/rkclock.c

1245

if ((div % 2) == 0)

sys/dev/fdt/rkclock.c

1246

div++;

sys/dev/fdt/rkclock.c

1256

div << RK3308_CRU_CLK_CORE_DBG_DIV_CON_SHIFT);

sys/dev/fdt/rkclock.c

1273

div << RK3308_CRU_CLK_CORE_DBG_DIV_CON_SHIFT);

sys/dev/fdt/rkclock.c

1845

uint32_t old_freq, div;

sys/dev/fdt/rkclock.c

1857

div = 1;

sys/dev/fdt/rkclock.c

1858

while (freq / (div + 1) > 300000000)

sys/dev/fdt/rkclock.c

1859

div++;

sys/dev/fdt/rkclock.c

1861

if ((div % 2) == 0)

sys/dev/fdt/rkclock.c

1862

div++;

sys/dev/fdt/rkclock.c

1873

div << RK3328_CRU_CLK_CORE_DBG_DIV_CON_SHIFT);

sys/dev/fdt/rkclock.c

1891

div << RK3328_CRU_CLK_CORE_DBG_DIV_CON_SHIFT);

sys/dev/fdt/rkclock.c

2797

uint32_t old_freq, div;

sys/dev/fdt/rkclock.c

2810

div = 1;

sys/dev/fdt/rkclock.c

2811

while (freq / (div + 1) > 200000000)

sys/dev/fdt/rkclock.c

2812

div++;

sys/dev/fdt/rkclock.c

2823

div << RK3399_CRU_PCLK_DBG_DIV_CON_SHIFT |

sys/dev/fdt/rkclock.c

2825

div << RK3399_CRU_ATCLK_CORE_DIV_CON_SHIFT);

sys/dev/fdt/rkclock.c

2839

div << RK3399_CRU_PCLK_DBG_DIV_CON_SHIFT |

sys/dev/fdt/rkclock.c

2841

div << RK3399_CRU_ATCLK_CORE_DIV_CON_SHIFT);

sys/dev/fdt/rkclock.c

547

uint32_t parent_freq, div, div_con, max_div_con;

sys/dev/fdt/rkclock.c

554

div = (parent_freq + freq - 1) / freq;

sys/dev/fdt/rkclock.c

555

div_con = (div > 0 ? div - 1 : 0);

sys/dev/fdt/rkiic.c

125

uint32_t div, divl, divh;

sys/dev/fdt/rkiic.c

153

div = 2;

sys/dev/fdt/rkiic.c

154

while (clock_speed > div * bus_speed * 8)

sys/dev/fdt/rkiic.c

155

div++;

sys/dev/fdt/rkiic.c

156

divl = div / 2;

sys/dev/fdt/rkiic.c

157

divh = div - divl;

sys/dev/fdt/rkspi.c

206

uint16_t div;

sys/dev/fdt/rkspi.c

209

div = 2;

sys/dev/fdt/rkspi.c

210

while ((sc->sc_spi_freq / div) > conf->sc_freq)

sys/dev/fdt/rkspi.c

211

div++;

sys/dev/fdt/rkspi.c

213

if (div & 1)

sys/dev/fdt/rkspi.c

214

div++;

sys/dev/fdt/rkspi.c

248

HWRITE4(sc, SPI_BAUDR, div);

sys/dev/fdt/sxiccmu.c

1008

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1043

div = 1 << A10_AXI_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1045

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1048

div = 1 << A10_AHB_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1050

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1076

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1091

div = CCU_AHB1_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1104

div *= CCU_AHB1_PRE_DIV(reg);

sys/dev/fdt/sxiccmu.c

1109

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1138

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1179

div = CCU_AHB1_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1192

div *= CCU_AHB1_PRE_DIV(reg);

sys/dev/fdt/sxiccmu.c

1197

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1203

div = 1;

sys/dev/fdt/sxiccmu.c

1207

div = 2;

sys/dev/fdt/sxiccmu.c

1212

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1229

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1237

div = A80_AHB1_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1249

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1348

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1387

div = CCU_AHB1_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1400

div *= CCU_AHB1_PRE_DIV(reg);

sys/dev/fdt/sxiccmu.c

1405

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1411

div = 1;

sys/dev/fdt/sxiccmu.c

1415

div = 2;

sys/dev/fdt/sxiccmu.c

1420

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1442

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1462

div = H3_AHB0_CLK_PRE_DIV(reg) * H3_AHB0_CLK_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1463

return freq / div;

sys/dev/fdt/sxiccmu.c

1466

div = H3_APB0_CLK_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1468

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1571

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1585

div = CCU_AHB1_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1598

div *= CCU_AHB1_PRE_DIV(reg);

sys/dev/fdt/sxiccmu.c

1601

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1615

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1630

div = CCU_AHB1_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

1643

div *= CCU_AHB1_PRE_DIV(reg);

sys/dev/fdt/sxiccmu.c

1648

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

1654

div = 1;

sys/dev/fdt/sxiccmu.c

1658

div = 2;

sys/dev/fdt/sxiccmu.c

1663

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

949

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

987

div = 1 << A10_AXI_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

989

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxiccmu.c

992

div = 1 << A10_AHB_CLK_DIV_RATIO(reg);

sys/dev/fdt/sxiccmu.c

994

return sxiccmu_ccu_get_frequency(sc, &parent) / div;

sys/dev/fdt/sxirsb.c

175

uint32_t freq, parent_freq, div, odly;

sys/dev/fdt/sxirsb.c

199

div = parent_freq / freq / 2;

sys/dev/fdt/sxirsb.c

200

if (div == 0)

sys/dev/fdt/sxirsb.c

201

div = 1;

sys/dev/fdt/sxirsb.c

202

if (div > (RSB_CCR_CK_DIV_MAX + 1))

sys/dev/fdt/sxirsb.c

203

div = (RSB_CCR_CK_DIV_MAX + 1);

sys/dev/fdt/sxirsb.c

204

odly = div >> 1;

sys/dev/fdt/sxirsb.c

210

((div - 1) << RSB_CCR_CK_DIV_SHIFT));

sys/dev/ic/ar9003.c

2229

int32_t min, max, div, f1, f2, f3, m, p, c;

sys/dev/ic/ar9003.c

2268

div = max - (max / 32) + (min / 8) + (min / 4);

sys/dev/ic/ar9003.c

2269

if (div == 0)

sys/dev/ic/ar9003.c

2272

sin[i] = (sin[i] * SCALE) / div;

sys/dev/ic/ar9003.c

2273

cos[i] = (cos[i] * SCALE) / div;

sys/dev/ic/bwi.c

6849

uint div;

sys/dev/ic/bwi.c

6863

div = 0;

sys/dev/ic/bwi.c

6868

div = 64;

sys/dev/ic/bwi.c

6871

div = 32;

sys/dev/ic/bwi.c

6878

div = 1;

sys/dev/ic/bwi.c

6880

div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;

sys/dev/ic/bwi.c

6890

div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;

sys/dev/ic/bwi.c

6894

KASSERT(div != 0);

sys/dev/ic/bwi.c

6901

freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;

sys/dev/ic/bwi.c

6902

freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;

sys/dev/ic/imxiic.c

113

uint32_t div;

sys/dev/ic/imxiic.c

116

div = (sc->sc_clkrate + speed - 1) / speed;

sys/dev/ic/imxiic.c

117

if (div < sc->sc_clk_div[0].div)

sys/dev/ic/imxiic.c

119

else if (div > sc->sc_clk_div[sc->sc_clk_ndiv - 1].div)

sys/dev/ic/imxiic.c

122

for (i = 0; sc->sc_clk_div[i].div < div; i++)

sys/dev/ic/imxiicvar.h

60

uint16_t div;

sys/dev/ic/pluart.c

338

int cr, div, lcr;

sys/dev/ic/pluart.c

376

div = 4 * sc->sc_clkfreq / ospeed;

sys/dev/ic/pluart.c

378

UART_IBRD_DIVINT(div >> 6));

sys/dev/ic/pluart.c

380

UART_FBRD_DIVFRAC(div));

sys/dev/ic/rtsx.c

583

rtsx_switch_sd_clock(struct rtsx_softc *sc, u_int8_t n, int div, int mcu)

sys/dev/ic/rtsx.c

594

RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);

sys/dev/ic/rtsx.c

664

int div;

sys/dev/ic/rtsx.c

689

div = RTSX_CLK_DIV_8;

sys/dev/ic/rtsx.c

695

div = RTSX_CLK_DIV_4;

sys/dev/ic/rtsx.c

701

div = RTSX_CLK_DIV_2;

sys/dev/ic/rtsx.c

713

error = rtsx_switch_sd_clock(sc, n, div, mcu);

sys/dev/ofw/ofw_clock.c

66

uint32_t mult, div, freq;

sys/dev/ofw/ofw_clock.c

69

div = OF_getpropint(node, "clock-div", 1);

sys/dev/ofw/ofw_clock.c

71

return (freq * mult) / div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

54

unsigned long div, mul;

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

61

div = gcd(n, cts);

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

63

n /= div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

64

cts /= div;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

248

struct fixed31_32 base, div;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

259

div = dc_fixpt_sub(c2, dc_fixpt_mul(c3, l_pow_m1));

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

261

base2 = dc_fixpt_div(base, div);

sys/dev/pci/drm/apple/apple_drv.c

44

#define FRAC_16_16(mult, div) (((mult) << 16) / (div))

sys/dev/pci/drm/i915/display/icl_dsi.c

1510

int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/icl_dsi.c

1514

DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

1516

DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

1518

DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

883

int mul = 1, div = 1;

sys/dev/pci/drm/i915/display/icl_dsi.c

895

div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

sys/dev/pci/drm/i915/display/icl_dsi.c

901

htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

903

htotal = DIV_ROUND_UP((hactive + 160) * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

905

hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);

sys/dev/pci/drm/i915/display/icl_dsi.c

906

hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1740

int div;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1760

div = 2;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1763

div = 3;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1766

div = 4;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1769

div = 8;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1787

cdclk_config->vco, size * div);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1789

cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);

sys/dev/pci/drm/i915/display/intel_display.c

5360

PIPE_CONF_CHECK_X(dsi_pll.div);

sys/dev/pci/drm/i915/display/intel_display_regs.h

1798

#define CNP_RAWCLK_DIV(div) ((div) << 16)

sys/dev/pci/drm/i915/display/intel_display_types.h

1106

u32 ctrl, div;

sys/dev/pci/drm/i915/display/intel_pps.c

1601

int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;

sys/dev/pci/drm/i915/display/intel_pps.c

1674

(100 * div) / 2 - 1) |

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

111

config->dsi_pll.div =

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

131

pll_div = config->dsi_pll.div;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

200

config->dsi_pll.div, config->dsi_pll.ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

225

vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

342

config->dsi_pll.div = pll_div;

sys/dev/pci/drm/i915/gt/intel_rc6.c

792

u32 mul, div;

sys/dev/pci/drm/i915/gt/intel_rc6.c

805

div = i915->czclk_freq;

sys/dev/pci/drm/i915/gt/intel_rc6.c

812

div = 12;

sys/dev/pci/drm/i915/gt/intel_rc6.c

815

div = 1;

sys/dev/pci/drm/i915/gt/intel_rc6.c

844

return mul_u64_u32_div(time_hw, mul, div);

sys/dev/pci/drm/i915/gt/intel_rps.c

483

int div = (vidfreq & 0x3f0000) >> 16;

sys/dev/pci/drm/i915/gt/intel_rps.c

490

return div * 133333 / (pre << post);

sys/dev/pci/drm/include/linux/math64.h

54

mul_u64_u32_div(uint64_t x, uint32_t y, uint32_t div)

sys/dev/pci/drm/include/linux/math64.h

56

return (x * y) / div;

sys/dev/pci/drm/radeon/dce6_afmt.c

306

unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &

sys/dev/pci/drm/radeon/dce6_afmt.c

309

div = radeon_audio_decode_dfs_div(div);

sys/dev/pci/drm/radeon/dce6_afmt.c

311

if (div)

sys/dev/pci/drm/radeon/dce6_afmt.c

312

clock = clock * 100 / div;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

295

unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &

sys/dev/pci/drm/radeon/evergreen_hdmi.c

298

div = radeon_audio_decode_dfs_div(div);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

300

if (div)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

301

clock = 100 * clock / div;

sys/dev/pci/drm/radeon/radeon_audio.c

497

unsigned long div, mul;

sys/dev/pci/drm/radeon/radeon_audio.c

504

div = gcd(n, cts);

sys/dev/pci/drm/radeon/radeon_audio.c

506

n /= div;

sys/dev/pci/drm/radeon/radeon_audio.c

507

cts /= div;

sys/dev/pci/drm/radeon/radeon_audio.c

720

unsigned int radeon_audio_decode_dfs_div(unsigned int div)

sys/dev/pci/drm/radeon/radeon_audio.c

722

if (div >= 8 && div < 64)

sys/dev/pci/drm/radeon/radeon_audio.c

723

return (div - 8) * 25 + 200;

sys/dev/pci/drm/radeon/radeon_audio.c

724

else if (div >= 64 && div < 96)

sys/dev/pci/drm/radeon/radeon_audio.c

725

return (div - 64) * 50 + 1600;

sys/dev/pci/drm/radeon/radeon_audio.c

726

else if (div >= 96 && div < 128)

sys/dev/pci/drm/radeon/radeon_audio.c

727

return (div - 96) * 100 + 3200;

sys/dev/pci/drm/radeon/radeon_audio.h

82

unsigned int radeon_audio_decode_dfs_div(unsigned int div);

sys/dev/pci/eap.c

809

u_int32_t div;

sys/dev/pci/eap.c

865

div = EREAD4(sc, EAP_ICSC) & ~EAP_PCLKBITS;

sys/dev/pci/eap.c

873

div |= EAP_SET_PCLKDIV(EAP_XTAL_FREQ /

sys/dev/pci/eap.c

876

div |= EAP_SET_PCLKDIV(EAP_XTAL_FREQ /

sys/dev/pci/eap.c

878

div |= EAP_CCB_INTRM;

sys/dev/pci/eap.c

879

EWRITE4(sc, EAP_ICSC, div);

sys/dev/pci/eap.c

880

DPRINTFN(2, ("eap_set_params: set ICSC = 0x%08x\n", div));

sys/dev/pci/if_iwmreg.h

3521

struct iwm_statistics_div div;

sys/dev/pci/if_iwn.c

4545

int i, ant, div, delta;

sys/dev/pci/if_iwn.c

4548

div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;

sys/dev/pci/if_iwn.c

4566

(int32_t)calib->noise[i]) / div;

sys/dev/pci/viapm.c

698

val_to_rpm(unsigned int val, int div)

sys/dev/pci/viapm.c

703

return 1350000 / val / div;

sys/dev/sdmmc/sdhc.c

662

int div;

sys/dev/sdmmc/sdhc.c

668

for (div = 2; div <= SDHC_SDCLK_DIV_MAX_V3; div += 2)

sys/dev/sdmmc/sdhc.c

669

if ((hp->clkbase / div) <= freq)

sys/dev/sdmmc/sdhc.c

670

return (div / 2);

sys/dev/sdmmc/sdhc.c

672

for (div = 1; div <= SDHC_SDCLK_DIV_MAX; div *= 2)

sys/dev/sdmmc/sdhc.c

673

if ((hp->clkbase / div) <= freq)

sys/dev/sdmmc/sdhc.c

674

return (div / 2);

sys/dev/sdmmc/sdhc.c

691

int div;

sys/dev/sdmmc/sdhc.c

734

if ((div = sdhc_clock_divisor(hp, freq)) < 0) {

sys/dev/sdmmc/sdhc.c

740

sdclk = SDHC_SDCLK_DIV_V3(div);

sys/dev/sdmmc/sdhc.c

742

sdclk = SDHC_SDCLK_DIV(div);

sys/dev/sdmmc/sdhcreg.h

213

#define SDHC_SDCLK_DIV(div) \

sys/dev/sdmmc/sdhcreg.h

214

(((div) & SDHC_SDCLK_DIV_MASK) << SDHC_SDCLK_DIV_SHIFT)

sys/dev/sdmmc/sdhcreg.h

215

#define SDHC_SDCLK_DIV_V3(div) \

sys/dev/sdmmc/sdhcreg.h

216

(SDHC_SDCLK_DIV(div) | \

sys/dev/sdmmc/sdhcreg.h

217

(((div) & SDHC_SDCLK_DIV_MASK_V3) >> SDHC_SDCLK_DIV_RSHIFT_V3))

sys/dev/usb/uaudio.c

1020

unsigned int mult = 1, div = 1;

sys/dev/usb/uaudio.c

1031

mult, div);

sys/dev/usb/uaudio.c

879

unsigned int mult, unsigned int div)

sys/dev/usb/uaudio.c

888

v = (unsigned long long)uaudio_rates[i] * mult / div;

sys/dev/usb/uchcom.c

670

uint8_t factor, div;

sys/dev/usb/uchcom.c

672

uchcom_calc_baudrate(sc, rate, &div, &factor);

sys/dev/usb/uchcom.c

676

UCHCOM_REG_BPS_PRE, div | 0x80,

sys/dev/usb/uchcom.c

682

idx = (factor << 8) | div;

sys/dev/usb/ukspan.c

473

u_int32_t div;

sys/dev/usb/ukspan.c

479

div = 1;

sys/dev/usb/ukspan.c

493

div = UKSPAN_CLOCK / (baud * 16);

sys/dev/usb/ukspan.c

501

cmsg->baudlo = div & 0xff;

sys/dev/usb/ukspan.c

502

cmsg->baudhi = div >> 8;

sys/dev/usb/umcs.c

403

uint16_t div;

sys/dev/usb/umcs.c

405

if (umcs_calc_baudrate(rate, &div, &clk))

sys/dev/usb/umcs.c

409

rate, clk, div);

sys/dev/usb/umcs.c

424

if (umcs_set_uart_reg(sc, portno, UMCS_REG_DLL, div & 0xff) ||

sys/dev/usb/umcs.c

425

umcs_set_uart_reg(sc, portno, UMCS_REG_DLM, (div >> 8) & 0xff))

sys/dev/x86emu/x86emu.c

8066

int32_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8073

div = dvd / (int8_t) s;

sys/dev/x86emu/x86emu.c

8075

if (div > 0x7f || div < -0x7f) {

sys/dev/x86emu/x86emu.c

8079

emu->x86.R_AL = (int8_t) div;

sys/dev/x86emu/x86emu.c

8090

int32_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8097

div = dvd / (int16_t) s;

sys/dev/x86emu/x86emu.c

8099

if (div > 0x7fff || div < -0x7fff) {

sys/dev/x86emu/x86emu.c

8105

CONDITIONAL_SET_FLAG(div == 0, F_ZF);

sys/dev/x86emu/x86emu.c

8108

emu->x86.R_AX = (uint16_t) div;

sys/dev/x86emu/x86emu.c

8119

int64_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8126

div = dvd / (int32_t) s;

sys/dev/x86emu/x86emu.c

8128

if (div > 0x7fffffff || div < -0x7fffffff) {

sys/dev/x86emu/x86emu.c

8138

emu->x86.R_EAX = (uint32_t) div;

sys/dev/x86emu/x86emu.c

8149

uint32_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8156

div = dvd / (uint8_t) s;

sys/dev/x86emu/x86emu.c

8158

if (div > 0xff) {

sys/dev/x86emu/x86emu.c

8162

emu->x86.R_AL = (uint8_t) div;

sys/dev/x86emu/x86emu.c

8173

uint32_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8180

div = dvd / (uint16_t) s;

sys/dev/x86emu/x86emu.c

8182

if (div > 0xffff) {

sys/dev/x86emu/x86emu.c

8188

CONDITIONAL_SET_FLAG(div == 0, F_ZF);

sys/dev/x86emu/x86emu.c

8191

emu->x86.R_AX = (uint16_t) div;

sys/dev/x86emu/x86emu.c

8202

uint64_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8209

div = dvd / (uint32_t) s;

sys/dev/x86emu/x86emu.c

8211

if (div > 0xffffffff) {

sys/dev/x86emu/x86emu.c

8221

emu->x86.R_EAX = (uint32_t) div;

sys/kern/tty_msts.c

357

long fac = 36000L, div = 6L, secs = 0L;

sys/kern/tty_msts.c

375

div = 16 - div;

sys/kern/tty_msts.c

376

fac /= div;

sys/kern/tty_nmea.c

596

long fac = 36000L, div = 6L, secs = 0L, frac = 0L;

sys/kern/tty_nmea.c

602

div = 16 - div;

sys/kern/tty_nmea.c

603

fac /= div;

sys/kern/tty_nmea.c

625

div = 1L;

sys/kern/tty_nmea.c

627

for (++s; div < 1000000 && *s && *s >= '0' && *s <= '9'; s++) {

sys/kern/tty_nmea.c

630

div *= 10;

sys/kern/tty_nmea.c

637

*nano = secs * 1000000000LL + (int64_t)frac * (1000000000 / div);

sys/net/pf_lb.c

732

u_int16_t div;

sys/net/pf_lb.c

734

div = r->rdr.proxy_port[1] - r->rdr.proxy_port[0] + 1;

sys/net/pf_lb.c

735

div = (div == 0) ? 1 : div;

sys/net/pf_lb.c

737

tmp_nport = ((ntohs(pd->ndport) - ntohs(r->dst.port[0])) % div) +

usr.bin/sdiff/sdiff.c

41

char div;

usr.bin/sdiff/sdiff.c

543

println(const char *s1, const char div, const char *s2)

usr.bin/sdiff/sdiff.c

556

if (div == ' ' && !s2) {

usr.bin/sdiff/sdiff.c

570

printf(" %c\n", div);

usr.bin/sdiff/sdiff.c

573

printf(" %c ", div);

usr.bin/sdiff/sdiff.c

797

enqueue(char *left, char div, char *right)

usr.bin/sdiff/sdiff.c

804

diffp->div = div;

usr.bin/sdiff/sdiff.c

901

divc = SIMPLEQ_FIRST(&diffhead)->div;

usr.bin/sdiff/sdiff.c

914

if (!sflag || diffp->div == '|' || diffp->div == '<' ||

usr.bin/sdiff/sdiff.c

915

diffp->div == '>')

usr.bin/sdiff/sdiff.c

916

println(diffp->left, diffp->div, diffp->right);

usr.bin/systat/if.c

342

int div = show_bits ? 1000 : 1024;

usr.bin/systat/if.c

365

print_fld_sdiv(FLD_IF_IBYTES, ifs->ifs_cur.ifc_ib * conv, div);

usr.bin/systat/if.c

369

print_fld_sdiv(FLD_IF_OBYTES, ifs->ifs_cur.ifc_ob * conv, div);

usr.bin/systat/if.c

382

int div = show_bits ? 1000 : 1024;

usr.bin/systat/if.c

386

print_fld_sdiv(FLD_IF_IBYTES, sum.ifc_ib * conv, div);

usr.bin/systat/if.c

390

print_fld_sdiv(FLD_IF_OBYTES, sum.ifc_ob * conv, div);