Symbol: outb
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2357
char *outb;
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2360
outb = malloc(inlen * 2);
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2361
if (outb == NULL)
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2368
outlen = BIO_read(bio, outb, inlen * 2);
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2378
memcpy(res->v, outb, outlen);
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2381
if (outb)
crypto/dist/ipsec-tools/src/racoon/crypto_openssl.c
2382
free(outb);
sys/arch/arc/arc/p_dti_tyne.c
139
outb(arc_bus_io.bs_vbase + 0x3ce, 6); /* Correct video mode */
sys/arch/arc/arc/p_dti_tyne.c
140
outb(arc_bus_io.bs_vbase + 0x3cf,
sys/arch/arc/include/isa_machdep.h
46
#define isa_outb(x,y) outb(arc_bus_io.bs_vbase + (x)- arc_bus_io.bs_start, y)
sys/arch/arc/isa/isadma.c
186
outb(dmapageport[0][chan], di->phys[0].addr>>16);
sys/arch/arc/isa/isadma.c
187
outb(waport, di->phys[0].addr);
sys/arch/arc/isa/isadma.c
188
outb(waport, di->phys[0].addr>>8);
sys/arch/arc/isa/isadma.c
191
outb(waport + 1, --nbytes);
sys/arch/arc/isa/isadma.c
192
outb(waport + 1, nbytes>>8);
sys/arch/arc/isa/isadma.c
209
outb(dmapageport[1][chan], di->phys[0].addr >> 16);
sys/arch/arc/isa/isadma.c
210
outb(waport, di->phys[0].addr >> 1);
sys/arch/arc/isa/isadma.c
211
outb(waport, di->phys[0].addr >> 9);
sys/arch/arc/isa/isadma.c
215
outb(waport + 2, --nbytes);
sys/arch/arc/isa/isadma.c
216
outb(waport + 2, nbytes>>8);
sys/arch/arm/footbridge/isa/icu.h
53
outb(IO_ICU1 + 1, imen); \
sys/arch/arm/footbridge/isa/icu.h
54
outb(IO_ICU2 + 1, imen >> 8); \
sys/arch/arm/footbridge/isa/isa_machdep.c
125
outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
sys/arch/arm/footbridge/isa/isa_machdep.c
126
outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
sys/arch/arm/footbridge/isa/isa_machdep.c
127
outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
sys/arch/arm/footbridge/isa/isa_machdep.c
129
outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
sys/arch/arm/footbridge/isa/isa_machdep.c
131
outb(IO_ICU1+1, 1); /* 8086 mode */
sys/arch/arm/footbridge/isa/isa_machdep.c
133
outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
sys/arch/arm/footbridge/isa/isa_machdep.c
134
outb(IO_ICU1, 0x68); /* special mask mode (if available) */
sys/arch/arm/footbridge/isa/isa_machdep.c
135
outb(IO_ICU1, 0x0a); /* Read IRR by default. */
sys/arch/arm/footbridge/isa/isa_machdep.c
137
outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
sys/arch/arm/footbridge/isa/isa_machdep.c
140
outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
sys/arch/arm/footbridge/isa/isa_machdep.c
141
outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
sys/arch/arm/footbridge/isa/isa_machdep.c
142
outb(IO_ICU2+1, IRQ_SLAVE);
sys/arch/arm/footbridge/isa/isa_machdep.c
144
outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
sys/arch/arm/footbridge/isa/isa_machdep.c
146
outb(IO_ICU2+1, 1); /* 8086 mode */
sys/arch/arm/footbridge/isa/isa_machdep.c
148
outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
sys/arch/arm/footbridge/isa/isa_machdep.c
149
outb(IO_ICU2, 0x68); /* special mask mode (if available) */
sys/arch/arm/footbridge/isa/isa_machdep.c
150
outb(IO_ICU2, 0x0a); /* Read IRR by default. */
sys/arch/arm/footbridge/isa/isa_machdep.c
355
outb(0x4d0, (inb(0x4d0) & ~(1 << irq))
sys/arch/arm/footbridge/isa/isa_machdep.c
359
outb(0x4d1, (inb(0x4d1) & ~(1 << irq))
sys/arch/bebox/bebox/machdep.c
327
outb(PREP_BUS_SPACE_IO + 0x0c00, LEFT_LED(15) | RIGHT_LED(15));
sys/arch/bebox/include/isa_machdep.h
42
#define isa_outb(x,y) outb(PREP_BUS_SPACE_IO + (x), y)
sys/arch/bebox/stand/boot/boot.h
50
void outb(int, u_char);
sys/arch/bebox/stand/boot/fd.c
364
outb(FDC_RATE(ctlr), un->un_type->rate); /* rate set */
sys/arch/bebox/stand/boot/fd.c
409
outb(FDC_DATA(ctlr), cmd);
sys/arch/bebox/stand/boot/fd.c
459
outb(FDC_DOR(ctlr), DOR_RESET | DOR_DMAEN | unit
sys/arch/bebox/stand/boot/fd.c
468
outb(FDC_DOR(ctlr), DOR_RESET); /* reset & motor off */
sys/arch/bebox/stand/boot/fd.c
477
outb(FDC_DOR(ctlr), 0); /* fdc reset */
sys/arch/bebox/stand/boot/fd.c
479
outb(FDC_DOR(ctlr), DOR_RESET);
sys/arch/bebox/stand/boot/fd.c
656
outb(INT_CTL0, ICW1_AT); /* ICW1 */
sys/arch/bebox/stand/boot/fd.c
657
outb(INT_CTL1, 0); /* ICW2 for master */
sys/arch/bebox/stand/boot/fd.c
658
outb(INT_CTL1, (1 << CASCADE_IRQ)); /* ICW3 tells slaves */
sys/arch/bebox/stand/boot/fd.c
659
outb(INT_CTL1, ICW4_AT); /* ICW4 */
sys/arch/bebox/stand/boot/fd.c
661
outb(INT_CTL1, (INT_MASK = ~(1 << CASCADE_IRQ)));
sys/arch/bebox/stand/boot/fd.c
664
outb(INT2_CTL0, ICW1_AT); /* ICW1 */
sys/arch/bebox/stand/boot/fd.c
665
outb(INT2_CTL1, 8); /* ICW2 for slave */
sys/arch/bebox/stand/boot/fd.c
666
outb(INT2_CTL1, CASCADE_IRQ); /* ICW3 is slave nr */
sys/arch/bebox/stand/boot/fd.c
667
outb(INT2_CTL1, ICW4_AT); /* ICW4 */
sys/arch/bebox/stand/boot/fd.c
669
outb(INT2_CTL1, (INT2_MASK = ~0)); /* IRQ 8-15 mask */
sys/arch/bebox/stand/boot/fd.c
685
outb(irc_no ? INT2_CTL1 : INT_CTL1, ~(1 << (irq_no >> (irc_no * 3))));
sys/arch/bebox/stand/boot/fd.c
688
outb(irc_no ? INT2_CTL0 : INT_CTL0, OCW3_PL);
sys/arch/bebox/stand/boot/fd.c
701
outb(INT2_CTL0, OCW2_CLEAR | (irq_no >> 3));
sys/arch/bebox/stand/boot/fd.c
702
outb(INT_CTL0, OCW2_CLEAR | CASCADE_IRQ);
sys/arch/bebox/stand/boot/fd.c
704
outb(INT_CTL0, OCW2_CLEAR | irq_no);
sys/arch/bebox/stand/boot/fd.c
707
outb(INT_CTL1, INT_MASK);
sys/arch/bebox/stand/boot/fd.c
708
outb(INT2_CTL1, INT2_MASK);
sys/arch/bebox/stand/boot/fd.c
742
outb(DMA_RESET, 0);
sys/arch/bebox/stand/boot/fd.c
744
outb(DMA_DEVCON, 0x00);
sys/arch/bebox/stand/boot/fd.c
745
outb(DMA_INIT, DMA_RESET_VAL); /* reset the dma controller */
sys/arch/bebox/stand/boot/fd.c
747
outb(DMA_MODE, func == F_READ ? DMA_READ : DMA_WRITE);
sys/arch/bebox/stand/boot/fd.c
748
outb(DMA_FLIPFLOP, 0); /* write anything to reset it */
sys/arch/bebox/stand/boot/fd.c
750
outb(DMA_ADDR, (int)pbuf >> 0);
sys/arch/bebox/stand/boot/fd.c
751
outb(DMA_ADDR, (int)pbuf >> 8);
sys/arch/bebox/stand/boot/fd.c
752
outb(DMA_LTOP, (int)pbuf >> 16);
sys/arch/bebox/stand/boot/fd.c
753
outb(DMA_HTOP, (int)pbuf >> 24);
sys/arch/bebox/stand/boot/fd.c
755
outb(DMA_COUNT, (size - 1) >> 0);
sys/arch/bebox/stand/boot/fd.c
756
outb(DMA_COUNT, (size - 1) >> 8);
sys/arch/bebox/stand/boot/fd.c
757
outb(DMA_INIT, chan); /* some sort of enable */
sys/arch/bebox/stand/boot/io.c
55
outb(port, val >> 8);
sys/arch/bebox/stand/boot/io.c
56
outb(port + 1, val);
sys/arch/bebox/stand/boot/kbd.c
179
outb(KBSTATP, 0xAA);
sys/arch/bebox/stand/boot/kbd.c
188
outb(KBSTATP, 0x60);
sys/arch/bebox/stand/boot/kbd.c
191
outb(KBDATAP, 0x45);
sys/arch/bebox/stand/boot/kbd.c
196
outb(KBSTATP, 0xAE);
sys/arch/bebox/stand/boot/vga.c
103
outb(addr_6845, 14);
sys/arch/bebox/stand/boot/vga.c
104
outb(addr_6845+1, pos >> 8);
sys/arch/bebox/stand/boot/vga.c
105
outb(addr_6845, 15);
sys/arch/bebox/stand/boot/vga.c
106
outb(addr_6845+1, pos);
sys/arch/bebox/stand/boot/vga.c
267
outb(addr_6845, 10);
sys/arch/bebox/stand/boot/vga.c
268
outb(addr_6845+1, d->cx);
sys/arch/bebox/stand/boot/vga.c
269
outb(addr_6845, 11);
sys/arch/bebox/stand/boot/vga.c
270
outb(addr_6845+1, 13);
sys/arch/bebox/stand/boot/vga.c
408
outb(0x3C4, 0x01);
sys/arch/bebox/stand/boot/vga.c
409
outb(0x3C5, inb(0x3C5) & ~0x20);
sys/arch/bebox/stand/boot/vga.c
417
outb(0x3C4, 0x01);
sys/arch/bebox/stand/boot/vga.c
418
outb(0x3C5, inb(0x3C5) | 0x20);
sys/arch/bebox/stand/boot/vreset.c
450
outb(0x3CE, 0x06);
sys/arch/bebox/stand/boot/vreset.c
484
outb(0x3c2, 0x63); /* MISC */
sys/arch/bebox/stand/boot/vreset.c
485
outb(0x3c2, 0x67); /* MISC */
sys/arch/bebox/stand/boot/vreset.c
498
outb(0x3c2, 0x63); /* MISC */
sys/arch/bebox/stand/boot/vreset.c
515
outb(0x3c2, 0x63); /* MISC */
sys/arch/bebox/stand/boot/vreset.c
553
outb(0x3c0, (index & 0x1F) | 0x20);
sys/arch/bebox/stand/boot/vreset.c
555
outb(0x3c0, (index & 0x1F));
sys/arch/bebox/stand/boot/vreset.c
556
outb(0x3c0, data);
sys/arch/bebox/stand/boot/vreset.c
568
outb(svp->io_port, svp->io_index);
sys/arch/bebox/stand/boot/vreset.c
569
outb(svp->io_port+1, svp->io_value);
sys/arch/bebox/stand/boot/vreset.c
573
outb(0x3c2, 0x67); /* MISC */
sys/arch/bebox/stand/boot/vreset.c
574
outb(0x3c6, 0xff); /* MASK */
sys/arch/bebox/stand/boot/vreset.c
590
outb(0x3C6, 0xFF);
sys/arch/bebox/stand/boot/vreset.c
592
outb(0x3C8, 0);
sys/arch/bebox/stand/boot/vreset.c
596
outb(0x3C9, TextCLUT[i].r);
sys/arch/bebox/stand/boot/vreset.c
597
outb(0x3C9, TextCLUT[i].g);
sys/arch/bebox/stand/boot/vreset.c
598
outb(0x3C9, TextCLUT[i].b);
sys/arch/bebox/stand/boot/vreset.c
608
outb(0x3C2, 0x67);
sys/arch/bebox/stand/boot/vreset.c
614
outb(0x3C0, 0x30);
sys/arch/bebox/stand/boot/vreset.c
615
outb(0x3C0, 0x01); /* graphics mode */
sys/arch/bebox/stand/boot/vreset.c
637
outb(0x46E8, 0x10); /* Put into setup mode */
sys/arch/bebox/stand/boot/vreset.c
638
outb(0x3C3, 0x10);
sys/arch/bebox/stand/boot/vreset.c
639
outb(0x102, 0x01); /* Enable registers */
sys/arch/bebox/stand/boot/vreset.c
640
outb(0x46E8, 0x08); /* Enable video */
sys/arch/bebox/stand/boot/vreset.c
641
outb(0x3C3, 0x08);
sys/arch/bebox/stand/boot/vreset.c
642
outb(0x4AE8, 0x00);
sys/arch/bebox/stand/boot/vreset.c
644
outb(0x42E8, 0x80); /* Reset graphics engine? */
sys/arch/bebox/stand/boot/vreset.c
646
outb(0x3D4, 0x38); /* Unlock all registers */
sys/arch/bebox/stand/boot/vreset.c
647
outb(0x3D5, 0x48);
sys/arch/bebox/stand/boot/vreset.c
648
outb(0x3D4, 0x39);
sys/arch/bebox/stand/boot/vreset.c
649
outb(0x3D5, 0xA5);
sys/arch/bebox/stand/boot/vreset.c
650
outb(0x3D4, 0x40);
sys/arch/bebox/stand/boot/vreset.c
651
outb(0x3D5, inb(0x3D5)|0x01);
sys/arch/bebox/stand/boot/vreset.c
652
outb(0x3D4, 0x33);
sys/arch/bebox/stand/boot/vreset.c
653
outb(0x3D5, inb(0x3D5)&~0x52);
sys/arch/bebox/stand/boot/vreset.c
654
outb(0x3D4, 0x35);
sys/arch/bebox/stand/boot/vreset.c
655
outb(0x3D5, inb(0x3D5)&~0x30);
sys/arch/bebox/stand/boot/vreset.c
656
outb(0x3D4, 0x3A);
sys/arch/bebox/stand/boot/vreset.c
657
outb(0x3D5, 0x00);
sys/arch/bebox/stand/boot/vreset.c
658
outb(0x3D4, 0x53);
sys/arch/bebox/stand/boot/vreset.c
659
outb(0x3D5, 0x00);
sys/arch/bebox/stand/boot/vreset.c
660
outb(0x3D4, 0x31);
sys/arch/bebox/stand/boot/vreset.c
661
outb(0x3D5, inb(0x3D5)&~0x4B);
sys/arch/bebox/stand/boot/vreset.c
662
outb(0x3D4, 0x58);
sys/arch/bebox/stand/boot/vreset.c
664
outb(0x3D5, 0);
sys/arch/bebox/stand/boot/vreset.c
666
outb(0x3D4, 0x54);
sys/arch/bebox/stand/boot/vreset.c
667
outb(0x3D5, 0x38);
sys/arch/bebox/stand/boot/vreset.c
668
outb(0x3D4, 0x60);
sys/arch/bebox/stand/boot/vreset.c
669
outb(0x3D5, 0x07);
sys/arch/bebox/stand/boot/vreset.c
670
outb(0x3D4, 0x61);
sys/arch/bebox/stand/boot/vreset.c
671
outb(0x3D5, 0x80);
sys/arch/bebox/stand/boot/vreset.c
672
outb(0x3D4, 0x62);
sys/arch/bebox/stand/boot/vreset.c
673
outb(0x3D5, 0xA1);
sys/arch/bebox/stand/boot/vreset.c
674
outb(0x3D4, 0x69); /* High order bits for cursor address */
sys/arch/bebox/stand/boot/vreset.c
675
outb(0x3D5, 0);
sys/arch/bebox/stand/boot/vreset.c
677
outb(0x3D4, 0x32);
sys/arch/bebox/stand/boot/vreset.c
678
outb(0x3D5, inb(0x3D5)&~0x10);
sys/arch/bebox/stand/boot/vreset.c
691
outb(0x3d4, 0x11);
sys/arch/bebox/stand/boot/vreset.c
692
outb(0x3d5, 0x0e); /* unlock CR0-CR7 */
sys/arch/bebox/stand/boot/wdvar.h
54
#define WDC_WRITE_REG(chp, reg, val) outb((chp)->c_cmdreg[(reg)], (val))
sys/arch/bebox/stand/boot/wdvar.h
56
#define WDC_WRITE_CTLREG(chp, reg, val) outb((chp)->c_ctlbase, (val))
sys/arch/i386/i386/machdep.c
1638
outb(IO_RTC, NVRAM_RESET);
sys/arch/i386/i386/machdep.c
1639
outb(IO_RTC+1, NVRAM_RESET_RST);
sys/arch/i386/mca/mca_machdep.c
166
outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */
sys/arch/i386/mca/mca_machdep.c
167
outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
sys/arch/i386/mca/mca_machdep.c
169
outb(MCA_ADAP_SETUP_REG, 0);
sys/arch/i386/mca/mca_machdep.c
182
outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */
sys/arch/i386/mca/mca_machdep.c
183
outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
sys/arch/i386/mca/mca_machdep.c
184
outb(MCA_POS_REG(reg), data);
sys/arch/i386/mca/mca_machdep.c
185
outb(MCA_ADAP_SETUP_REG, 0);
sys/arch/i386/mca/mca_machdep.c
239
outb(MCA_MB_SETUP_REG, 0xff);
sys/arch/i386/mca/mca_machdep.c
243
outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
sys/arch/i386/mca/mca_machdep.c
255
outb(MCA_ADAP_SETUP_REG, 0);
sys/arch/i386/mca/mca_machdep.c
329
outb(PORT_DISKLED, inb(PORT_DISKLED) | DISKLED_ON);
sys/arch/i386/mca/mca_machdep.c
338
outb(PORT_DISKLED, inb(PORT_DISKLED) & ~DISKLED_ON);
sys/arch/i386/stand/efiboot/eficpufunc.h
38
void outb(uint32_t, uint8_t);
sys/arch/i386/stand/lib/comio_direct.c
164
outb(combase + com_data, c);
sys/arch/i386/stand/lib/comio_direct.c
188
outb(combase + com_cfcr, LCR_DLAB);
sys/arch/i386/stand/lib/comio_direct.c
203
outb(combase + com_dlbl, rate);
sys/arch/i386/stand/lib/comio_direct.c
204
outb(combase + com_dlbh, rate >> 8);
sys/arch/i386/stand/lib/comio_direct.c
205
outb(combase + com_cfcr, LCR_8BITS);
sys/arch/i386/stand/lib/comio_direct.c
206
outb(combase + com_mcr, MCR_DTR | MCR_RTS);
sys/arch/i386/stand/lib/comio_direct.c
207
outb(combase + com_fifo,
sys/arch/i386/stand/lib/comio_direct.c
209
outb(combase + com_ier, 0);
sys/arch/i386/stand/lib/cpufunc.h
44
void outb(unsigned, uint8_t);
sys/arch/i386/stand/lib/gatea20.c
61
outb(0x92, data | 0x2);
sys/arch/i386/stand/lib/gatea20.c
68
outb(K_CMD, KC_CMD_WOUT);
sys/arch/i386/stand/lib/gatea20.c
72
outb(K_RDWR, x_20);
sys/arch/ia64/include/acpi_machdep.h
10
#define acpi_md_OsOut8(x, v) outb((x), (v))
sys/arch/ia64/include/bus.h
381
outb((h) + (o), (v)); \
sys/arch/ia64/include/bus.h
504
outb(__port, *__src); \
sys/arch/ia64/include/bus.h
629
outb(addr, v);
sys/arch/ia64/include/bus.h
722
outb(addr, v);
sys/arch/ia64/include/bus.h
826
outb(addr2, inb(addr1));
sys/arch/ia64/include/bus.h
831
outb(addr2, inb(addr1));
sys/arch/ia64/include/cpufunc.h
176
outb(port, *buf++);
sys/arch/ibmnws/include/isa_machdep.h
42
#define isa_outb(x,y) outb(PREP_BUS_SPACE_IO + (x), y)
sys/arch/mvmeppc/include/isa_machdep.h
37
#define isa_outb(x,y) outb(PREP_BUS_SPACE_IO + (x), y)
sys/arch/mvmeppc/mvmeppc/platform_160x.c
160
outb(0x80000092, inb(0x80000092) | 1);
sys/arch/mvmeppc/mvmeppc/platform_160x.c
171
outb(0x80000074, off & 0xff);
sys/arch/mvmeppc/mvmeppc/platform_160x.c
172
outb(0x80000075, (off >> 8) & 0xff);
sys/arch/powerpc/include/pio.h
161
#define out8(a,v) outb(a,v)
sys/arch/powerpc/include/pio.h
173
#define out8rb(a,v) outb(a,v)
sys/arch/prep/include/isa_machdep.h
42
#define isa_outb(x,y) outb(PREP_BUS_SPACE_IO + (x), y)
sys/arch/prep/pnpbus/mcclock_pnpbus.c
173
outb(PREP_BUS_SPACE_IO + 0x856, 1);
sys/arch/prep/prep/platform.c
116
outb(PREP_BUS_SPACE_IO + 0x92, reg);
sys/arch/prep/prep/platform.c
119
outb(PREP_BUS_SPACE_IO + 0x92, reg);
sys/arch/prep/prep/platform.c
95
outb(PREP_BUS_SPACE_IO + 0x81c, l2ctrl | 0xc0);
sys/arch/prep/stand/boot/boot.h
40
void outb(int, char);
sys/arch/prep/stand/boot/io.c
58
outb(port, val>>8);
sys/arch/prep/stand/boot/io.c
59
outb(port+1, val);
sys/arch/prep/stand/boot/kbd.c
179
outb(KBSTATP, 0xAA);
sys/arch/prep/stand/boot/kbd.c
188
outb(KBSTATP, 0x60);
sys/arch/prep/stand/boot/kbd.c
191
outb(KBDATAP, 0x45);
sys/arch/prep/stand/boot/kbd.c
196
outb(KBSTATP, 0xAE);
sys/arch/prep/stand/boot/pci.c
151
outb(0x3d4, 0x11);
sys/arch/prep/stand/boot/pci.c
152
outb(0x3d5, 0x0e); /* unlock CR0-CR7 */
sys/arch/prep/stand/boot/vga.c
105
outb(addr_6845, 14);
sys/arch/prep/stand/boot/vga.c
106
outb(addr_6845+1, pos >> 8);
sys/arch/prep/stand/boot/vga.c
107
outb(addr_6845, 15);
sys/arch/prep/stand/boot/vga.c
108
outb(addr_6845+1, pos);
sys/arch/prep/stand/boot/vga.c
269
outb(addr_6845, 10);
sys/arch/prep/stand/boot/vga.c
270
outb(addr_6845+1, d->cx);
sys/arch/prep/stand/boot/vga.c
271
outb(addr_6845, 11);
sys/arch/prep/stand/boot/vga.c
272
outb(addr_6845+1, 13);
sys/arch/prep/stand/boot/vga.c
410
outb(0x3C4, 0x01);
sys/arch/prep/stand/boot/vga.c
411
outb(0x3C5, inb(0x3C5) & ~0x20);
sys/arch/prep/stand/boot/vga.c
419
outb(0x3C4, 0x01);
sys/arch/prep/stand/boot/vga.c
420
outb(0x3C5, inb(0x3C5) | 0x20);
sys/arch/prep/stand/boot/vreset.c
167
outb(VGA_GR_PORT, 0x06);
sys/arch/prep/stand/boot/vreset.c
188
outb(VGA_GR_PORT, 0x0b); /* disable linear addressing */
sys/arch/prep/stand/boot/vreset.c
189
outb(VGA_GR_DATA, inb(VGA_GR_DATA) & ~0x30);
sys/arch/prep/stand/boot/vreset.c
191
outb(VGA_GR_PORT, 0x0e); /* disable 256 color mode */
sys/arch/prep/stand/boot/vreset.c
192
outb(VGA_GR_DATA, inb(VGA_GR_DATA) & ~0x01);
sys/arch/prep/stand/boot/vreset.c
193
outb(0xd00, 0xff); /* enable auto-centering */
sys/arch/prep/stand/boot/vreset.c
195
outb(VGA_CR_PORT, 0x33);
sys/arch/prep/stand/boot/vreset.c
196
outb(VGA_CR_DATA, inb(VGA_CR_DATA) & ~0x90);
sys/arch/prep/stand/boot/vreset.c
197
outb(VGA_CR_PORT, 0x32);
sys/arch/prep/stand/boot/vreset.c
198
outb(VGA_CR_DATA, inb(VGA_CR_DATA) | 0x04);
sys/arch/prep/stand/boot/vreset.c
226
outb(0x3c2, 0x63); /* ??? */
sys/arch/prep/stand/boot/vreset.c
240
outb(0x3c0, (index & 0x1F) | 0x20);
sys/arch/prep/stand/boot/vreset.c
242
outb(0x3c0, (index & 0x1F));
sys/arch/prep/stand/boot/vreset.c
243
outb(0x3c0, data);
sys/arch/prep/stand/boot/vreset.c
252
outb(VGA_SR_PORT, SR_regs[i].idx);
sys/arch/prep/stand/boot/vreset.c
253
outb(VGA_SR_PORT + 1, SR_regs[i].val);
sys/arch/prep/stand/boot/vreset.c
256
outb(VGA_CR_PORT, CR_regs[i].idx);
sys/arch/prep/stand/boot/vreset.c
257
outb(VGA_CR_PORT + 1, CR_regs[i].val);
sys/arch/prep/stand/boot/vreset.c
260
outb(VGA_GR_PORT, GR_regs[i].idx);
sys/arch/prep/stand/boot/vreset.c
261
outb(VGA_GR_PORT + 1, GR_regs[i].val);
sys/arch/prep/stand/boot/vreset.c
264
outb(0x3c2, 0x67); /* MISC */
sys/arch/prep/stand/boot/vreset.c
265
outb(0x3c6, 0xff); /* MASK */
sys/arch/prep/stand/boot/vreset.c
277
outb(0x3C6, 0xFF);
sys/arch/prep/stand/boot/vreset.c
279
outb(0x3C8, 0);
sys/arch/prep/stand/boot/vreset.c
283
outb(0x3c9, vga_dacpal[i++] << shift);
sys/arch/prep/stand/boot/vreset.c
284
outb(0x3c9, vga_dacpal[i++] << shift);
sys/arch/prep/stand/boot/vreset.c
285
outb(0x3c9, vga_dacpal[i++] << shift);
sys/arch/prep/stand/boot/vreset.c
295
outb(0x3C2, 0x67);
sys/arch/prep/stand/boot/vreset.c
298
outb(0x3C0, 0x30);
sys/arch/prep/stand/boot/vreset.c
299
outb(0x3C0, 0x01); /* graphics mode */
sys/arch/prep/stand/boot/vreset.c
323
outb(VGA_CR_PORT, 0x2d);
sys/arch/prep/stand/boot/vreset.c
325
outb(VGA_CR_PORT, 0x2e);
sys/arch/prep/stand/boot/vreset.c
330
outb(0x46E8, 0x10); /* Put into setup mode */
sys/arch/prep/stand/boot/vreset.c
331
outb(0x3C3, 0x10);
sys/arch/prep/stand/boot/vreset.c
332
outb(0x102, 0x01); /* Enable registers */
sys/arch/prep/stand/boot/vreset.c
333
outb(0x46E8, 0x08); /* Enable video */
sys/arch/prep/stand/boot/vreset.c
334
outb(0x3C3, 0x08);
sys/arch/prep/stand/boot/vreset.c
335
outb(0x4AE8, 0x00);
sys/arch/prep/stand/boot/vreset.c
336
outb(VGA_CR_PORT, 0x38); /* Unlock all registers */
sys/arch/prep/stand/boot/vreset.c
337
outb(VGA_CR_DATA, 0x48);
sys/arch/prep/stand/boot/vreset.c
338
outb(VGA_CR_PORT, 0x39);
sys/arch/prep/stand/boot/vreset.c
339
outb(VGA_CR_DATA, 0xA5);
sys/arch/prep/stand/boot/vreset.c
340
outb(VGA_CR_PORT, 0x40);
sys/arch/prep/stand/boot/vreset.c
341
outb(VGA_CR_DATA, inb(0x3D5)|0x01);
sys/arch/prep/stand/boot/vreset.c
342
outb(VGA_CR_PORT, 0x33);
sys/arch/prep/stand/boot/vreset.c
343
outb(VGA_CR_DATA, inb(0x3D5)&~0x52);
sys/arch/prep/stand/boot/vreset.c
344
outb(VGA_CR_PORT, 0x35);
sys/arch/prep/stand/boot/vreset.c
345
outb(VGA_CR_DATA, inb(0x3D5)&~0x30);
sys/arch/prep/stand/boot/vreset.c
346
outb(VGA_CR_PORT, 0x3A);
sys/arch/prep/stand/boot/vreset.c
347
outb(VGA_CR_DATA, 0x00);
sys/arch/prep/stand/boot/vreset.c
348
outb(VGA_CR_PORT, 0x53);
sys/arch/prep/stand/boot/vreset.c
349
outb(VGA_CR_DATA, 0x00);
sys/arch/prep/stand/boot/vreset.c
350
outb(VGA_CR_PORT, 0x31);
sys/arch/prep/stand/boot/vreset.c
351
outb(VGA_CR_DATA, inb(0x3D5)&~0x4B);
sys/arch/prep/stand/boot/vreset.c
352
outb(VGA_CR_PORT, 0x58);
sys/arch/prep/stand/boot/vreset.c
354
outb(VGA_CR_DATA, 0);
sys/arch/prep/stand/boot/vreset.c
356
outb(VGA_CR_PORT, 0x54);
sys/arch/prep/stand/boot/vreset.c
357
outb(VGA_CR_DATA, 0x38);
sys/arch/prep/stand/boot/vreset.c
358
outb(VGA_CR_PORT, 0x60);
sys/arch/prep/stand/boot/vreset.c
359
outb(VGA_CR_DATA, 0x07);
sys/arch/prep/stand/boot/vreset.c
360
outb(VGA_CR_PORT, 0x61);
sys/arch/prep/stand/boot/vreset.c
361
outb(VGA_CR_DATA, 0x80);
sys/arch/prep/stand/boot/vreset.c
362
outb(VGA_CR_PORT, 0x62);
sys/arch/prep/stand/boot/vreset.c
363
outb(VGA_CR_DATA, 0xA1);
sys/arch/prep/stand/boot/vreset.c
364
outb(VGA_CR_PORT, 0x69); /* High order bits for cursor address */
sys/arch/prep/stand/boot/vreset.c
365
outb(VGA_CR_DATA, 0);
sys/arch/prep/stand/boot/vreset.c
367
outb(VGA_CR_PORT, 0x32);
sys/arch/prep/stand/boot/vreset.c
368
outb(VGA_CR_DATA, inb(0x3D5)&~0x10);
sys/arch/rs6000/mca/mca_machdep.c
152
outb(RS6000_BUS_SPACE_IO + MCA_POS_REG(reg) + (slot<<16), data);
sys/arch/rs6000/mca/mca_machdep.c
200
outb(MCA_MB_SETUP_REG, 0xff);
sys/arch/rs6000/mca/mca_machdep.c
204
outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
sys/arch/rs6000/mca/mca_machdep.c
216
outb(MCA_ADAP_SETUP_REG, 0);
sys/arch/rs6000/mca/mca_machdep.c
248
outb(PORT_DISKLED, inb(PORT_DISKLED) | DISKLED_ON);
sys/arch/rs6000/mca/mca_machdep.c
257
outb(PORT_DISKLED, inb(PORT_DISKLED) & ~DISKLED_ON);
sys/arch/rs6000/rs6000/machdep.c
472
outb(sysinfo->prcr_addr, 0x1);
sys/arch/rs6000/stand/boot/boot.h
41
void outb(int, char);
sys/arch/rs6000/stand/boot/io.c
41
outb(port, val>>8);
sys/arch/rs6000/stand/boot/io.c
42
outb(port+1, val);
sys/arch/sandpoint/include/isa_machdep.h
37
#define isa_outb(x,y) outb(SANDPOINT_BUS_SPACE_IO + (x), y)
sys/arch/shark/isa/clock.c
200
outb(IO_RTC, reg);
sys/arch/shark/isa/clock.c
208
outb(IO_RTC, reg);
sys/arch/shark/isa/clock.c
209
outb(IO_RTC+1, datum);
sys/arch/shark/isa/clock.c
284
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
sys/arch/shark/isa/clock.c
285
outb(IO_TIMER1 + TIMER_CNTR0, TIMER0_ROLLOVER % 256);
sys/arch/shark/isa/clock.c
286
outb(IO_TIMER1 + TIMER_CNTR0, TIMER0_ROLLOVER / 256);
sys/arch/shark/isa/clock.c
392
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
sys/arch/shark/isa/clock.c
485
outb(IO_TIMER1 + TIMER_MODE,
sys/arch/shark/isa/clock.c
487
outb(IO_TIMER1 + TIMER_CNTR0, 0xff);
sys/arch/shark/isa/clock.c
488
outb(IO_TIMER1 + TIMER_CNTR0, 0xff);
sys/arch/shark/isa/icu.h
53
outb(IO_ICU1 + 1, imen); \
sys/arch/shark/isa/icu.h
54
outb(IO_ICU2 + 1, imen >> 8); \
sys/arch/shark/isa/isa_shark_machdep.c
124
outb(IO_ICU1, 0x19); /* reset; four bytes, level triggered */
sys/arch/shark/isa/isa_shark_machdep.c
125
outb(IO_ICU1+1, ICU_OFFSET); /* int base: not used */
sys/arch/shark/isa/isa_shark_machdep.c
126
outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
sys/arch/shark/isa/isa_shark_machdep.c
127
outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
sys/arch/shark/isa/isa_shark_machdep.c
128
outb(IO_ICU1+1, 0xff); /* disable all interrupts */
sys/arch/shark/isa/isa_shark_machdep.c
129
outb(IO_ICU1, 0x68); /* special mask mode (if available) */
sys/arch/shark/isa/isa_shark_machdep.c
130
outb(IO_ICU1, 0x0a); /* Read IRR, not ISR */
sys/arch/shark/isa/isa_shark_machdep.c
132
outb(IO_ICU2, 0x19); /* reset; four bytes, level triggered */
sys/arch/shark/isa/isa_shark_machdep.c
133
outb(IO_ICU2+1, ICU_OFFSET+8); /* int base + offset for master: not used */
sys/arch/shark/isa/isa_shark_machdep.c
134
outb(IO_ICU2+1, IRQ_SLAVE); /* who ami i? */
sys/arch/shark/isa/isa_shark_machdep.c
135
outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
sys/arch/shark/isa/isa_shark_machdep.c
136
outb(IO_ICU2+1, 0xff); /* disable all interrupts */
sys/arch/shark/isa/isa_shark_machdep.c
137
outb(IO_ICU2, 0x68); /* special mask mode (if available) */
sys/arch/shark/isa/isa_shark_machdep.c
138
outb(IO_ICU2, 0x0a); /* Read IRR by default. */
sys/arch/shark/shark/hat.c
101
outb(ATSR_REG1_REG,
sys/arch/shark/shark/hat.c
151
outb(ATSR_REG1_REG,
sys/arch/shark/shark/hat.c
227
outb(TIMER_MODE, TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT);
sys/arch/shark/shark/hat.c
228
outb(TIMER_CNTR2, count % 256);
sys/arch/shark/shark/hat.c
229
outb(TIMER_CNTR2, count / 256);
sys/arch/x68k/stand/boot/dp8390.c
51
#define NIC_PUT(reg, val) outb(WE_IOBASE + (reg) * 2, val)
sys/arch/x68k/stand/boot/ne.c
72
#define NIC_OUTB(x, b) outb(NIC_PORT(x), (b))
sys/arch/x68k/stand/boot/ne.c
87
#define ASIC_OUTB(x, b) outb(ASIC_PORT(x), (b))
sys/arch/x86/include/acpi_machdep.h
55
#define acpi_md_OsOut8(x, v) outb((x), (v))
sys/arch/x86/include/i8259.h
103
outb %al,$IO_ICU1
sys/arch/x86/include/i8259.h
111
outb %al,$IO_ICU2 /* do the second ICU first */ ;\
sys/arch/x86/include/i8259.h
113
outb %al,$IO_ICU1
sys/arch/x86/include/i8259.h
131
outb %al,$(ICUADDR+1)
sys/arch/x86/include/i8259.h
137
outb %al,$(ICUADDR+1)
sys/arch/x86/include/i8259.h
50
#define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
sys/arch/x86/include/i8259.h
92
outb %al,$IO_ICU1
sys/arch/x86/include/i8259.h
96
outb %al,$ICUADDR
sys/arch/x86/include/pio.h
43
void outb(unsigned, uint8_t);
sys/arch/x86/isa/clock.c
315
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
sys/arch/x86/isa/clock.c
318
outb(IO_TIMER1+TIMER_CNTR0, tval % 256);
sys/arch/x86/isa/clock.c
319
outb(IO_TIMER1+TIMER_CNTR0, tval / 256);
sys/arch/x86/isa/clock.c
391
outb(0x61, inb(0x61) | 0x80);
sys/arch/x86/isa/clock.c
409
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
sys/arch/x86/isa/clock.c
441
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
sys/arch/x86/isa/rtc.c
164
outb(IO_RTC, reg);
sys/arch/x86/isa/rtc.c
172
outb(IO_RTC, reg);
sys/arch/x86/isa/rtc.c
173
outb(IO_RTC+1, datum);
sys/arch/x86/pci/pci_machdep.c
1055
outb(IO_VGA + VGA_DAC_ADDRW, index);
sys/arch/x86/pci/pci_machdep.c
1056
outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2);
sys/arch/x86/pci/pci_machdep.c
1057
outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2);
sys/arch/x86/pci/pci_machdep.c
1058
outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2);
sys/arch/x86/pci/pci_machdep.c
430
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
sys/arch/x86/pci/pci_machdep.c
432
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
sys/arch/x86/pci/pci_machdep.c
854
outb(PCI_MODE1_ADDRESS_REG + 3, 0);
sys/arch/x86/pci/pci_machdep.c
885
outb(PCI_MODE2_ENABLE_REG, 0);
sys/arch/x86/pci/pci_machdep.c
886
outb(PCI_MODE2_FORWARD_REG, 0);
sys/arch/x86/x86/bus_space.c
681
outb(addr, v);
sys/arch/x86/x86/bus_space.c
727
outb(addr, v);
sys/arch/x86/x86/bus_space.c
777
outb(addr2, inb(addr1));
sys/arch/x86/x86/bus_space.c
782
outb(addr2, inb(addr1));
sys/arch/x86/x86/cpu.c
1150
outb(IO_RTC, NVRAM_RESET);
sys/arch/x86/x86/cpu.c
1151
outb(IO_RTC+1, NVRAM_RESET_JUMP);
sys/arch/x86/x86/cpu.c
1214
outb(IO_RTC, NVRAM_RESET);
sys/arch/x86/x86/cpu.c
1215
outb(IO_RTC+1, NVRAM_RESET_RST);
sys/arch/x86/x86/i8259.c
133
outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);
sys/arch/x86/x86/i8259.c
137
outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
sys/arch/x86/x86/i8259.c
140
outb(IO_ICU1 + PIC_ICW2, ICU_OFFSET);
sys/arch/x86/x86/i8259.c
142
outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE));
sys/arch/x86/x86/i8259.c
146
outb(IO_ICU1 + PIC_ICW4, ICW4_AEOI | ICW4_8086);
sys/arch/x86/x86/i8259.c
149
outb(IO_ICU1 + PIC_ICW4, ICW4_8086);
sys/arch/x86/x86/i8259.c
152
outb(IO_ICU1 + PIC_OCW1, 0xff);
sys/arch/x86/x86/i8259.c
154
outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
sys/arch/x86/x86/i8259.c
156
outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR);
sys/arch/x86/x86/i8259.c
159
outb(IO_ICU1 + PIC_OCW2, OCW2_SELECT | OCW2_R | OCW2_SL |
sys/arch/x86/x86/i8259.c
167
outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);
sys/arch/x86/x86/i8259.c
171
outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
sys/arch/x86/x86/i8259.c
174
outb(IO_ICU2 + PIC_ICW2, ICU_OFFSET + 8);
sys/arch/x86/x86/i8259.c
176
outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE));
sys/arch/x86/x86/i8259.c
179
outb(IO_ICU2 + PIC_ICW4, ICW4_AEOI | ICW4_8086);
sys/arch/x86/x86/i8259.c
182
outb(IO_ICU2 + PIC_ICW4, ICW4_8086);
sys/arch/x86/x86/i8259.c
185
outb(IO_ICU2 + PIC_OCW1, 0xff);
sys/arch/x86/x86/i8259.c
187
outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
sys/arch/x86/x86/i8259.c
189
outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR);
sys/arch/x86/x86/i8259.c
209
outb(port, byte);
sys/arch/x86/x86/i8259.c
230
outb(port, byte);
sys/arch/x86/x86/i8259.c
251
outb(IO_ICU1 + PIC_OCW1, i8259_imen);
sys/arch/x86/x86/i8259.c
252
outb(IO_ICU2 + PIC_OCW1, i8259_imen >> 8);
sys/arch/x86/x86/i8259.c
276
outb(IO_ICU1 + PIC_OCW1, i8259_imen);
sys/arch/x86/x86/i8259.c
277
outb(IO_ICU2 + PIC_OCW1, i8259_imen >> 8);
sys/arch/x86/x86/identcpu.c
389
outb(0x22, reg);
sys/arch/x86/x86/identcpu.c
397
outb(0x22, reg);
sys/arch/x86/x86/identcpu.c
398
outb(0x23, data);
sys/arch/x86/x86/ioapic.c
471
outb(IMCR_ADDR, IMCR_REGISTER);
sys/arch/x86/x86/ioapic.c
472
outb(IMCR_DATA, IMCR_APIC);
sys/arch/x86/x86/vga_post.c
116
outb(port, val);
sys/arch/x86/x86/x86_machdep.c
1230
outb(IO_KBD + KBCMDP, KBC_PULSE0);
sys/arch/x86/x86/x86_machdep.c
1232
outb(IO_KBD + KBCMDP, KBC_PULSE0);
sys/arch/x86/x86/x86_machdep.c
1245
outb(0xcf9, 0x2);
sys/arch/x86/x86/x86_machdep.c
1246
outb(0xcf9, 0x6);
sys/arch/x86/x86/x86_machdep.c
1259
outb(0x92, b & 0xfe);
sys/arch/x86/x86/x86_machdep.c
1260
outb(0x92, b | 0x1);
sys/dev/acpi/hpqlb_acpi.c
247
outb(IO_RTC+2, 0xaf);
sys/dev/acpi/hpqlb_acpi.c
248
outb(IO_RTC+3, 7 /* val */);
sys/dev/i2o/dpti.c
374
outb (0x70, 0x12);
sys/dev/i2o/dpti.c
378
outb (0x70, 0x19);
sys/dev/i2o/dpti.c
385
outb (0x70, 0x1a);
sys/dev/i2o/dpti.c
394
outb(0x70, 0x16);
sys/dev/i2o/dpti.c
397
outb(0x70, 0x15);
sys/dev/i2o/dpti.c
404
outb(0x70, 0x31);
sys/dev/i2o/dpti.c
407
outb(0x70, 0x30);
sys/dev/ic/dpt.c
1213
outb (0x70, 0x12);
sys/dev/ic/dpt.c
1217
outb (0x70, 0x19);
sys/dev/ic/dpt.c
1224
outb (0x70, 0x1a);
sys/dev/ic/dpt.c
1233
outb(0x70, 0x16);
sys/dev/ic/dpt.c
1236
outb(0x70, 0x15);
sys/dev/ic/dpt.c
1243
outb(0x70, 0x31);
sys/dev/ic/dpt.c
1246
outb(0x70, 0x30);
sys/dev/isa/pas.c
166
#define paswrite(d, p) outb((p), (d))
sys/dev/isa/pas.c
318
outb(MASTER_DECODE, 0xbc);
sys/dev/isa/pas.c
333
outb(MASTER_DECODE, iobase >> 2);
sys/dev/isapnp/isapnpvar.h
53
# define ISAPNP_WRITE_ADDR(sc, v) outb(ISAPNP_ADDR, v)
sys/dev/isapnp/isapnpvar.h
54
# define ISAPNP_WRITE_DATA(sc, v) outb(ISAPNP_WRDATA, v)
sys/dev/pci/icp_pci.c
388
outb(0x00,PTR2USHORT(&ha->plx->control1));
sys/dev/pci/icp_pci.c
389
outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
sys/dev/pci/icp_pci.c
397
outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
sys/dev/pci/icp_pci.c
427
outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
usr.bin/mail/mime_codecs.c
102
**outb = '\0';
usr.bin/mail/mime_codecs.c
84
mime_iconv(iconv_t cd, const char **inb, size_t *inbleft, char **outb, size_t *outbleft)
usr.bin/mail/mime_codecs.c
88
while ((sz = iconv(cd, __UNCONST(inb), inbleft, outb, outbleft))
usr.bin/mail/mime_codecs.c
92
*(*outb)++ = '?';
usr.bin/mail/mime_codecs.c
95
**outb = '\0';
usr.bin/tcopy/tcopy.c
234
verify(int inp, int outp, char *outb)
usr.bin/tcopy/tcopy.c
252
r1: if ((outn = read(outp, outb, outmaxblk)) == -1) {
usr.bin/tcopy/tcopy.c
255
outn = read(outp, outb, outmaxblk);
usr.bin/tcopy/tcopy.c
276
if (memcmp(inb, outb, inn)) {