mfpr
sc->sc_intcpu = 1 << mfpr(PR_BINID);
ipl = mfpr(PR_IPL);
int mid = mfpr(PR_SID);
mid = mfpr(PR_SID);
while (mfpr(PR_RXCS) & GC_DON) {
if ((mfpr(PR_RXDB) & 0x7f) == 19) {
while ((mfpr(PR_RXCS) & GC_DON) == 0)
if ((mfpr(PR_RXDB) & 0x7f) == 17)
while ((mfpr(PR_TXCS) & GC_RDY) == 0) /* Wait until xmit ready */
while ((mfpr(PR_RXCS) & GC_DON) == 0)
return (mfpr(PR_RXDB)); /* now get it */
if (mfpr(PR_RXCS) & GC_DON)
return mfpr(PR_RXDB);
while ((mfpr(PR_CSRS) & 0x80) == 0)
status = mfpr(PR_CSRD);
while ((mfpr(PR_CSTS) & 0x80) == 0)
vax_cputype = (mfpr(PR_SID) >> 24) & 0xFF;
while (mfpr(PR_RXCS) & GC_DON) {
if ((mfpr(PR_RXDB) & 0x7f) == 19) {
while ((mfpr(PR_RXCS) & GC_DON) == 0)
if ((mfpr(PR_RXDB) & 0x7f) == 17)
while ((mfpr(PR_TXCS) & GC_RDY) == 0)
#define curlwp ((struct lwp *)mfpr(PR_SSP))
int ipl = mfpr(PR_IPL);
return mfpr(PR_IPL);
if ((mfpr(PR_TXCS) & GC_RDY) == 0)
unsigned klocka = mfpr(PR_TODR);
counter = mfpr(PR_ICR) + tick;
if ((mfpr(PR_STXCS) & STXCS_RDY) == 0)
i = mfpr(PR_STXCS);
crlstat.crl_ds = mfpr(PR_STXDB);
*crltab.crl_xaddr++ = mfpr(PR_STXDB);
crlstat.crl_cs = mfpr(PR_STXDB);
#define WAIT while ((mfpr(PR_CSTS) & 0x80) == 0)
if ((mfpr(PR_CSRS) & 0x80))
return mfpr(PR_CSRD);
int status = mfpr(PR_CSRD);
#define WAIT while ((mfpr(PR_CSTS) & 0x80) == 0)
while ((mfpr(PR_CSTS) & 0x80) == 0)
tf->tf_sp = mfpr(PR_USP);
vax_cpudata = mfpr(PR_SID);
i = mfpr(pr_rxdb[sc->unit]) & 0377; /* Mask status flags etc... */
while (mfpr(PR_RXCS) & GC_DON) {
if ((mfpr(PR_RXDB) & 0x7f) == 19) {
while ((mfpr(PR_RXCS) & GC_DON) == 0)
if ((mfpr(PR_RXDB) & 0x7f) == 17)
while ((mfpr(PR_TXCS) & GC_RDY) == 0) /* Wait until xmit ready */
while ((mfpr(PR_RXCS) & GC_DON) == 0) /* Receive chr */
i = mfpr(PR_RXDB) & 0x7f;
if (mfpr(PR_PCSTS) & KA43_PCS_TRAP2) {
snprintb(sbuf, sizeof(sbuf), KA43_PCSTS_BITS, mfpr(PR_PCSTS));
snprintb(sbuf, sizeof(sbuf), KA43_PCSTS_BITS, mfpr(PR_PCSTS));
val = mfpr(PR_PCSTS);
mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
mtpr(mfpr(PR_CCTL) | 0x10, PR_CCTL); /* Set cache size */
mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
mtpr(mfpr(PR_CCTL) | 0x10 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
{ volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
volatile int *hej = (void *)mfpr(PR_ISP);
int c = mfpr(PR_RXCD);
mtpr(mfpr(PR_PCSTS), PR_PCSTS); /* clear error flags */
ka6400_txrx(id, "D/I C %x\r", mfpr(PR_SBR)); /* SBR */
ka6400_txrx(id, "D/I D %x\r", mfpr(PR_SLR)); /* SLR */
ka6400_txrx(id, "D/I 11 %x\r", mfpr(PR_SCBB)); /* SCB */
ka6400_txrx(id, "D/I 38 %x\r", mfpr(PR_MAPEN)); /* Enable MM */
if (mfpr(PR_TODR) == 0)
i = mfpr(PR_CAER);
if (mfpr(PR_PCSTS) & KA670_PCS_TRAP2) {
snprintb(sbuf, sizeof(sbuf), KA670_PCSTS_BITS, mfpr(PR_PCSTS));
snprintb(sbuf, sizeof(sbuf), KA670_BCSTS_BITS, mfpr(PR_BCSTS));
val = mfpr(PR_PCSTS);
snprintb(sbuf, sizeof(sbuf), KA670_PCSTS_BITS, mfpr(PR_PCSTS));
snprintb(sbuf, sizeof(sbuf), KA670_BCSTS_BITS, mfpr(PR_BCSTS));
volatile int *hej = (void *)mfpr(PR_ISP);
mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
mcf->mc3_pc, mcf->mc3_psl, mfpr(PR_MCESR));
#define WAIT while ((mfpr(PR_TXCS) & GC_RDY) == 0) ;
if (mfpr(PR_TODR) == 0) { /* Check for failing battery */
if (mfpr(PR_ACCS) & 255) {
int mcsr = mfpr(PR_MCSR);
#define WAIT while ((mfpr(PR_TXCS) & GC_RDY) == 0) ;
sbifs = mfpr(PR_SBIFS);
mtpr(mfpr(PR_SBIER) | 0x70c0, PR_SBIER);
if (mfpr(PR_ACCS) & 255) {
mastercpu = mfpr(PR_BINID);
int c = mfpr(PR_RXCD);
ka820_txrx(id, "D/I C %x\r", mfpr(PR_SBR)); /* SBR */
ka820_txrx(id, "D/I D %x\r", mfpr(PR_SLR)); /* SLR */
ka820_txrx(id, "D/I 11 %x\r", mfpr(PR_SCBB)); /* SCB */
ka820_txrx(id, "D/I 38 %x\r", mfpr(PR_MAPEN)); /* Enable MM */
mtpr(mfpr(PR_MERG) | M8600_ICRD, PR_MERG);
mtpr(mfpr(PR_MERG) & ~M8600_ICRD, PR_MERG);
fpa = mfpr(PR_ACCS);
int s = splhigh(), old = mfpr(PR_TXCS);
#define WAIT while ((mfpr(PR_TXCS) & GC_RDY) == 0) ;
mfpr(PR_SID) & 65535, (mfpr(PR_SID) >> 16) & 127);
int c = mfpr(PR_RXCD);
while ((mfpr(PR_TXCS) & GC_RDY) == 0) /* Wait until xmit ready */
while ((mfpr(PR_RXCS) & GC_DON) == 0)
ret = mfpr(PR_RXDB);
ka88_confdata = mfpr(PR_RXDB);
ka88_txrx(id, "D/I C %x\r", mfpr(PR_SBR)); /* SBR */
ka88_txrx(id, "D/I D %x\r", mfpr(PR_SLR)); /* SLR */
ka88_txrx(id, "D/I 11 %x\r", mfpr(PR_SCBB)); /* SCB */
ka88_txrx(id, "D/I 38 %x\r", mfpr(PR_MAPEN)); /* Enable MM */
while ((mfpr(PR_TXCS) & GC_RDY) == 0)
if (((end & 0x3fffffff) >> VAX_PGSHIFT) > mfpr(PR_SLR))
pte = (u_int *)mfpr(PR_P1BR);
pte = (u_int *)mfpr(PR_P0BR);
rpb.sbr = mfpr(PR_SBR);
rpb.slr = mfpr(PR_SLR);
ipl = mfpr(PR_IPL);
mfpr(PR_KSP), (u_int)tf->tf_pc, pcb,
if (mfpr(PR_MAPEN) == 0)
nipqb->np_spt = nipqb->np_gpt = mfpr(PR_SBR);
nipqb->np_sptlen = nipqb->np_gptlen = mfpr(PR_SLR);
+ (mfpr(PR_SBR) | 0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));
if ((mfpr(PR_MAPEN) & 1) == 0)
if (mfpr(PR_MAPEN) == 0)
((VTOP(DMAheader[unit]*4)) + (mfpr(PR_SBR)|0x80000000));
((VTOP(eq_header[unit])*4) + (mfpr(PR_SBR)|0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));
+ (mfpr(PR_SBR) | 0x80000000));