in32rb
cr = in32rb(gt_base + GTMPSC_RCRR);
datal = in32rb(gt_base + di->low_decode);
datah = in32rb(gt_base + di->high_decode);
datal = in32rb(gt_base + GT_PCI0_Mem0_Low_Decode);
datah = in32rb(gt_base + GT_PCI0_Mem0_High_Decode);
datal = in32rb(gt_base + GT_PCI0_IO_Low_Decode);
datah = in32rb(gt_base + GT_PCI0_IO_High_Decode);
datal = in32rb(gt_base + GT_PCI1_Mem0_Low_Decode);
datah = in32rb(gt_base + GT_PCI1_Mem0_High_Decode);
datal = in32rb(gt_base + GT_PCI1_IO_Low_Decode);
datah = in32rb(gt_base + GT_PCI1_IO_High_Decode);
nstart = GT_LowAddr_GET(in32rb(gt_base + di->low_decode));
nend = GT_HighAddr_GET(in32rb(gt_base + di->high_decode)) + 1;
sa = in32rb(PCI_MODE1_DATA_REG);
ea = in32rb(PCI_MODE1_DATA_REG);
banks = in32rb(PCI_MODE1_DATA_REG) & 0xFF;
reg = in32rb(0xf3000034);
while (in32rb(&dmap->d_status) &
while (in32rb(&dmap->d_status) & (DBDMA_CNTRL_FLUSH));
while (in32rb(&dmap->d_status) & DBDMA_CNTRL_RUN);
#define DBDMA_LD4_ENDIAN(a) in32rb(a)
return in32rb(sc->sc_reg + reg);
if (MEDIABAY_ID(sc, in32rb(sc->sc_addr)) != MEDIABAY_ID_NONE)
fcr = in32rb(sc->sc_fcr);
out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_RESET);
out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_POWER);
out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~MBCR_MEDIABAY0_ENABLE);
in32rb(sc->sc_addr) | MBCR_MEDIABAY0_IDE_ENABLE);
out32rb(sc->sc_addr, in32rb(sc->sc_addr) | MBCR_MEDIABAY0_RESET);
out32rb(sc->sc_fcr, in32rb(sc->sc_fcr) | FCR1_EIDE0_RESET);
out32rb(sc->sc_fcr, in32rb(sc->sc_fcr) | FCR1_EIDE0_ENABLE);
out32rb(sc->sc_addr, in32rb(sc->sc_addr) | MBCR_MEDIABAY0_ENABLE);
out32rb(sc->sc_addr, in32rb(sc->sc_addr) & ~0xf);
x = in32rb(sc->sc_addr);
fcr = in32rb(sc->sc_fcr);
x = in32rb(OHARE_FEATURE_REG);
if (in32rb(HH_ARBCONF) & 0x02)
levels = in32rb(INT_STATE_REG_H);
levels = in32rb(INT_STATE_REG_L);
irqs = in32rb(INT_STATE_REG_L);
levels = in32rb(INT_LEVEL_REG_L) & heathrow->enable_mask_l;
irqs = in32rb(INT_STATE_REG_H);
levels = in32rb(INT_LEVEL_REG_L) & heathrow->enable_mask_h;
levels = in32rb(INT_STATE_REG);
irqs = in32rb(INT_STATE_REG);
levels = in32rb(INT_LEVEL_REG) & ohare->enable_mask;
printf("levels: %08x\n", in32rb(INT_LEVEL_REG));
printf("states: %08x\n", in32rb(INT_STATE_REG));
printf("enable: %08x\n", in32rb(INT_ENABLE_REG));
tmp = in32rb(dev_reg + PCI_COMMAND_STATUS_REG);
nirq = in32rb(base + 0x04);
DPRINTF("devreg %08x\n", in32rb(dev_reg + PCI_ID_REG));
tmp = in32rb(base + 0x04);
tmp = in32rb(dev_reg + PCI_ID_REG);
irqmap[irq].im_data = in32rb(base + 0x04);
x = in32rb(irqmap->im_base + 0x04);
x = in32rb(irqmap->im_base + 0x04);
x = in32rb(irqmap->im_base + 0x04);
return in32rb(addr);
data = in32rb(pc->pc_data);
data = in32rb(pc->pc_data);
data = in32rb(x);
in32rb(pc->pc_addr);
data = in32rb(daddr);
in32rb(pc->pc_addr);
in32rb(pc->pc_addr);
in32rb(pc->pc_addr);
in32rb(pc->pc_addr);
data = in32rb(daddr);
in32rb(pc->pc_addr);
in32rb(pc->pc_addr);
in32rb(pc->pc_addr);
return in32rb(addr);
data = in32rb(pc->pc_data); /* config data: little-endian */
reg2 = in32rb(PREP_BUS_SPACE_IO+IBM_82660_SYSTEM_CTRL);
v = in32rb(python+0x30);
data = in32rb(pc->pc_data);
return in32rb(addr);
data = in32rb(PCI_DCONF_BASE | tag | reg);
mask = in32rb(RS6000_BUS_SPACE_IO + IOCC_IEE);
mask = in32rb(RS6000_BUS_SPACE_IO + IOCC_IEE);
rv = in32rb(RS6000_BUS_SPACE_IO + IOCC_IRR);
data = in32rb(SANDPOINT_PCI_CONFIG_DATA);
val = in32rb(0xfee00000);
val = in32rb(0xfee00000);
val = in32rb(0xfee00000);
#define CSR_READ_4(r) in32rb(r)
#define CSR_READ_4(l, r) in32rb((l)->iobase+(r))
unsigned in32rb(unsigned);
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(r) in32rb(r)
#define CSR_READ(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ(l, r) in32rb((l)->csr+(r))
#define CSR_READ_4(l, r) in32rb((l)->csr+(r))
#define CSR_READ(l, r) in32rb((l)->csr+(r))