Symbol: ctrl
lib/libossaudio/oss4_mixer.c
276
if (ext->ctrl == 0) {
lib/libossaudio/oss4_mixer.c
310
mdi.index = ext->ctrl - 1;
lib/libossaudio/oss4_mixer.c
388
if (ei->ctrl == 0) {
lib/libossaudio/oss4_mixer.c
395
mdi.index = ei->ctrl - 1;
lib/libossaudio/oss4_mixer.c
446
if (mv->ctrl == 0) {
lib/libossaudio/oss4_mixer.c
453
mdi.index = mc.dev = mv->ctrl - 1;
lib/libossaudio/oss4_mixer.c
517
if (mv->ctrl == 0) {
lib/libossaudio/oss4_mixer.c
524
mdi.index = mc.dev = (mv->ctrl - 1);
lib/libossaudio/soundcard.h
599
int ctrl; /* Set by caller */
lib/libossaudio/soundcard.h
611
int ctrl; /* Set by caller */
lib/libossaudio/soundcard.h
620
int ctrl;
sys/arch/alpha/pci/cia.c
190
uint32_t ctrl;
sys/arch/alpha/pci/cia.c
203
ctrl = REGVAL(CIA_CSR_CTRL);
sys/arch/alpha/pci/cia.c
204
if ((ctrl & CTRL_PCI_LOOP_EN) == 0) {
sys/arch/alpha/pci/cia.c
205
REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
sys/arch/alpha/pci/cia.c
316
uint32_t ctrl;
sys/arch/alpha/pci/cia.c
325
ctrl = REGVAL(CIA_CSR_CTRL);
sys/arch/alpha/pci/cia.c
326
ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
sys/arch/alpha/pci/cia.c
327
REGVAL(CIA_CSR_CTRL) = ctrl;
sys/arch/alpha/pci/cia_dma.c
534
uint32_t ctrl;
sys/arch/alpha/pci/cia_dma.c
543
ctrl = REGVAL(CIA_CSR_CTRL);
sys/arch/alpha/pci/cia_dma.c
544
REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
sys/arch/alpha/pci/cia_dma.c
567
REGVAL(CIA_CSR_CTRL) = ctrl;
sys/arch/amiga/dev/grf_ul.c
179
thebits = ba->ctrl;
sys/arch/amiga/dev/grf_ul.c
183
ba->ctrl = thebits & ~INTOUT;
sys/arch/amiga/dev/grf_ul.c
225
ba->ctrl = (ba->ctrl & ~INCR) | (LBL | INCW);
sys/arch/amiga/dev/grf_ul.c
233
ba->ctrl = (ba->ctrl & ~INCW) | LBL;
sys/arch/amiga/dev/grf_ul.c
257
ba->ctrl |= INCW;
sys/arch/amiga/dev/grf_ul.c
266
ba->ctrl = LBL | INCW | NMI | NMIM | HLT | CF;
sys/arch/amiga/dev/grf_ul.c
286
ba->ctrl |= INCW;
sys/arch/amiga/dev/grf_ul.c
288
ba->ctrl &= ~INCW;
sys/arch/amiga/dev/grf_ul.c
312
ba->ctrl &= ~(HLT|CF);
sys/arch/amiga/dev/grf_ul.c
340
ba->ctrl &= ~(HLT|CF);
sys/arch/amiga/dev/grf_ul.c
376
ba->ctrl = (ba->ctrl & ~INCR) | (LBL | INCW); /* XXX */
sys/arch/amiga/dev/grf_ul.c
391
ba->ctrl &= ~INCW;
sys/arch/amiga/dev/grf_ul.c
406
ba->ctrl |= LBL | INCW;
sys/arch/amiga/dev/grf_ul.c
633
ba->ctrl = LBL;
sys/arch/amiga/dev/grf_ul.c
834
ba->ctrl = LBL;
sys/arch/amiga/dev/grf_ul.c
837
ba->ctrl |= INCW;
sys/arch/amiga/dev/grf_ul.c
839
ba->ctrl &= ~INCW;
sys/arch/amiga/dev/grf_ul.c
868
gsp->ctrl = (gsp->ctrl & ~(INCR | INCW)) | LBL;
sys/arch/amiga/dev/grf_ul.c
905
oc = gsp->ctrl;
sys/arch/amiga/dev/grf_ul.c
908
gsp->ctrl = (oc & ~INCR) | LBL | INCW;
sys/arch/amiga/dev/grf_ul.c
942
gsp->ctrl = oc;
sys/arch/amiga/dev/grf_ulreg.h
44
volatile u_short ctrl;
sys/arch/amiga/dev/ite_ul.c
161
ba->ctrl = LBL|INCW;
sys/arch/arm/amlogic/meson_platform.c
401
uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG);
sys/arch/arm/amlogic/meson_platform.c
402
ctrl |= __BITS(cpuno,0);
sys/arch/arm/amlogic/meson_platform.c
403
bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl);
sys/arch/arm/apple/apple_mbox.c
129
const uint32_t ctrl = MBOX_READ4(sc, MBOX_I2A_CTRL);
sys/arch/arm/apple/apple_mbox.c
131
if (ctrl & MBOX_I2A_CTRL_EMPTY)
sys/arch/arm/apple/apple_mbox.c
185
uint32_t ctrl = MBOX_READ4(sc, MBOX_A2I_CTRL);
sys/arch/arm/apple/apple_mbox.c
186
if (ctrl & MBOX_A2I_CTRL_FULL)
sys/arch/arm/apple/apple_mbox.c
205
uint32_t ctrl = MBOX_READ4(sc, MBOX_I2A_CTRL);
sys/arch/arm/apple/apple_mbox.c
206
if (ctrl & MBOX_I2A_CTRL_EMPTY)
sys/arch/arm/apple/apple_nvme.c
379
uint32_t ctrl, status;
sys/arch/arm/apple/apple_nvme.c
426
ctrl = bus_space_read_4(asc->asc_iot, asc->asc_ioh, ANS_CPU_CTRL);
sys/arch/arm/apple/apple_nvme.c
428
ctrl | ANS_CPU_CTRL_RUN);
sys/arch/arm/apple/apple_nvme.c
445
ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANS_UNKNOWN_CTRL);
sys/arch/arm/apple/apple_nvme.c
447
ctrl & ~ANS_PRP_NULL_CHECK);
sys/arch/arm/arm32/arm11_pmc.c
114
uint32_t ctrl;
sys/arch/arm/arm32/arm11_pmc.c
128
ctrl = arm11_pmc_ctrl_read();
sys/arch/arm/arm32/arm11_pmc.c
129
if (ctrl & ARM11_PMCCTL_CCR) {
sys/arch/arm/arm32/arm11_pmc.c
134
ctrl &= ~(ARM11_PMCCTL_CR0|ARM11_PMCCTL_CR1);
sys/arch/arm/arm32/arm11_pmc.c
135
arm11_pmc_ctrl_write(ctrl);
sys/arch/arm/arm32/cortex_pmc.c
102
ctrl = armreg_pmovsr_read();
sys/arch/arm/arm32/cortex_pmc.c
103
if (ctrl & CORTEX_CNTOFL_C) {
sys/arch/arm/arm32/cortex_pmc.c
81
uint32_t ctrl;
sys/arch/arm/broadcom/bcm2835_rng.c
118
ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RNG_CTRL);
sys/arch/arm/broadcom/bcm2835_rng.c
119
ctrl |= RNG_CTRL_EN;
sys/arch/arm/broadcom/bcm2835_rng.c
120
bus_space_write_4(sc->sc_iot, sc->sc_ioh, RNG_CTRL, ctrl);
sys/arch/arm/broadcom/bcm2835_rng.c
91
uint32_t ctrl;
sys/arch/arm/ep93xx/epcom.c
1204
u_int lcrlo, lcrmid, lcrhi, ctrl, pwrcnt;
sys/arch/arm/ep93xx/epcom.c
1216
ctrl = Ctrl_UARTE;
sys/arch/arm/ep93xx/epcom.c
1229
bus_space_write_4(iot, ioh, EPCOM_Ctrl, ctrl);
sys/arch/arm/footbridge/footbridge.c
272
u_int ctrl, intr;
sys/arch/arm/footbridge/footbridge.c
278
ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL);
sys/arch/arm/footbridge/footbridge.c
279
intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR |
sys/arch/arm/footbridge/footbridge.c
287
ctrl | intr);
sys/arch/arm/footbridge/footbridge.c
292
ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG);
sys/arch/arm/footbridge/footbridge.c
293
intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT
sys/arch/arm/footbridge/footbridge.c
302
PCI_COMMAND_STATUS_REG, ctrl | intr);
sys/arch/arm/imx/imx23_timrot.c
173
uint32_t ctrl = IRQ_EN | UPDATE | RELOAD | SELECT_32KHZ;
sys/arch/arm/imx/imx23_timrot.c
179
TIMER_WRITE(sc, HW_TIMROT_TIMCTRL0, ctrl);
sys/arch/arm/imx/imx23_timrot.c
185
TIMER_WRITE(sc, HW_TIMROT_TIMCTRL1, ctrl);
sys/arch/arm/iomd/iomd_dma.c
290
struct dma_ctrl *dp = &ctrl[ch];
sys/arch/arm/iomd/iomd_dma.c
61
static struct dma_ctrl ctrl[6];
sys/arch/arm/iomd/vidcaudio.c
488
vidcaudio_ctrl(int ctrl)
sys/arch/arm/iomd/vidcaudio.c
491
WriteWord(vidc_base, VIDC_SCR | ctrl);
sys/arch/arm/marvell/armadaxp.c
581
int ctrl;
sys/arch/arm/marvell/armadaxp.c
601
ctrl = MPIC_READ(ARMADAXP_MLMB_MPIC_CTRL);
sys/arch/arm/marvell/armadaxp.c
603
ctrl |= (1 << 0);
sys/arch/arm/marvell/armadaxp.c
604
MPIC_WRITE(ARMADAXP_MLMB_MPIC_CTRL, ctrl);
sys/arch/arm/marvell/mvsoctmr.c
341
uint32_t ctrl;
sys/arch/arm/marvell/mvsoctmr.c
347
ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR);
sys/arch/arm/marvell/mvsoctmr.c
349
ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num);
sys/arch/arm/marvell/mvsoctmr.c
351
ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num);
sys/arch/arm/marvell/mvsoctmr.c
353
ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num);
sys/arch/arm/marvell/mvsoctmr.c
355
ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num);
sys/arch/arm/marvell/mvsoctmr.c
358
ctrl |= MVSOCTMR_CTCR_25MHZEN(num);
sys/arch/arm/marvell/mvsoctmr.c
359
bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl);
sys/arch/arm/nvidia/tegra_drm_mode.c
1032
uint32_t ctrl =
sys/arch/arm/nvidia/tegra_drm_mode.c
1036
ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */
sys/arch/arm/nvidia/tegra_drm_mode.c
1038
HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl);
sys/arch/arm/rockchip/rk_pwm.c
117
uint32_t ctrl, octrl;
sys/arch/arm/rockchip/rk_pwm.c
119
octrl = ctrl = PWM_READ(sc, PWM0_CTRL);
sys/arch/arm/rockchip/rk_pwm.c
121
ctrl |= CTRL_PWM_EN;
sys/arch/arm/rockchip/rk_pwm.c
123
ctrl &= ~CTRL_PWM_EN;
sys/arch/arm/rockchip/rk_pwm.c
125
if (ctrl != octrl)
sys/arch/arm/rockchip/rk_pwm.c
126
PWM_WRITE(sc, PWM0_CTRL, ctrl);
sys/arch/arm/rockchip/rk_pwm.c
139
uint32_t ctrl, period, duty;
sys/arch/arm/rockchip/rk_pwm.c
142
ctrl = PWM_READ(sc, PWM0_CTRL);
sys/arch/arm/rockchip/rk_pwm.c
146
if (ctrl & CTRL_CLK_SEL) {
sys/arch/arm/rockchip/rk_pwm.c
147
div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2;
sys/arch/arm/rockchip/rk_pwm.c
153
div /= (1 << __SHIFTOUT(ctrl, CTRL_PRESCALE));
sys/arch/arm/rockchip/rk_pwm.c
157
conf->polarity = (ctrl & CTRL_DUTY_POL) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
sys/arch/arm/rockchip/rk_pwm.c
171
uint32_t ctrl;
sys/arch/arm/rockchip/rk_pwm.c
178
ctrl = PWM_READ(sc, PWM0_CTRL) & CTRL_PWM_EN;
sys/arch/arm/rockchip/rk_pwm.c
180
ctrl |= __SHIFTIN(CTRL_PWM_MODE_CONTINUOUS, CTRL_PWM_MODE);
sys/arch/arm/rockchip/rk_pwm.c
182
ctrl |= CTRL_DUTY_POL;
sys/arch/arm/rockchip/rk_pwm.c
184
ctrl |= CTRL_INACTIVE_POL;
sys/arch/arm/rockchip/rk_pwm.c
189
PWM_WRITE(sc, PWM0_CTRL, ctrl);
sys/arch/arm/rockchip/rk_v1crypto.c
141
uint32_t ctrl;
sys/arch/arm/rockchip/rk_v1crypto.c
190
ctrl = RK_V1CRYPTO_TRNG_CTRL_OSC_ENABLE;
sys/arch/arm/rockchip/rk_v1crypto.c
191
ctrl |= __SHIFTIN(100, RK_V1CRYPTO_TRNG_CTRL_CYCLES);
sys/arch/arm/rockchip/rk_v1crypto.c
192
RKC_WRITE(sc, RK_V1CRYPTO_TRNG_CTRL, ctrl);
sys/arch/arm/rockchip/rk_v1crypto.c
209
uint32_t ctrl;
sys/arch/arm/rockchip/rk_v1crypto.c
222
ctrl = 0;
sys/arch/arm/rockchip/rk_v1crypto.c
223
ctrl |= RK_V1CRYPTO_AES_CTRL_KEYCHANGE;
sys/arch/arm/rockchip/rk_v1crypto.c
224
ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_MODE_ECB,
sys/arch/arm/rockchip/rk_v1crypto.c
226
ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_KEYSIZE_128,
sys/arch/arm/rockchip/rk_v1crypto.c
228
ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_DIR_ENC,
sys/arch/arm/rockchip/rk_v1crypto.c
230
RKC_WRITE(sc, RK_V1CRYPTO_AES_CTRL, ctrl);
sys/arch/arm/sunxi/sunxi_hdmi.c
444
uint32_t hpd, ctrl;
sys/arch/arm/sunxi/sunxi_hdmi.c
459
ctrl = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG);
sys/arch/arm/sunxi/sunxi_hdmi.c
460
if (ctrl & SUNXI_HDMI_DDC_CTRL_SW_RST) {
sys/arch/arm/sunxi/sunxi_pwm.c
112
uint32_t ctrl, octrl;
sys/arch/arm/sunxi/sunxi_pwm.c
114
octrl = ctrl = PWM_READ(sc, PWM_CH_CTRL);
sys/arch/arm/sunxi/sunxi_pwm.c
116
ctrl |= (PWM_CH0_EN | SCLK_CH0_GATING);
sys/arch/arm/sunxi/sunxi_pwm.c
118
ctrl &= ~(PWM_CH0_EN | SCLK_CH0_GATING);
sys/arch/arm/sunxi/sunxi_pwm.c
120
if (ctrl != octrl)
sys/arch/arm/sunxi/sunxi_pwm.c
121
PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
sys/arch/arm/sunxi/sunxi_pwm.c
130
uint32_t ctrl, ch_period;
sys/arch/arm/sunxi/sunxi_pwm.c
132
ctrl = PWM_READ(sc, PWM_CH_CTRL);
sys/arch/arm/sunxi/sunxi_pwm.c
139
conf->polarity = (ctrl & PWM_CH0_ACT_STA) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
sys/arch/arm/sunxi/sunxi_pwm.c
150
uint32_t ctrl, ch_period;
sys/arch/arm/sunxi/sunxi_pwm.c
152
ctrl = PWM_READ(sc, PWM_CH_CTRL);
sys/arch/arm/sunxi/sunxi_pwm.c
153
if (ctrl & PWM0_RDY)
sys/arch/arm/sunxi/sunxi_pwm.c
156
ctrl &= ~PWM0_BYPASS; /* Prescaler /120 = 200 kHz */
sys/arch/arm/sunxi/sunxi_pwm.c
157
ctrl &= ~PWM_CH0_PRESCAL;
sys/arch/arm/sunxi/sunxi_pwm.c
158
ctrl |= __SHIFTIN(0, PWM_CH0_PRESCAL);
sys/arch/arm/sunxi/sunxi_pwm.c
160
ctrl &= ~PWM_CHANNEL0_MODE; /* Cycle mode */
sys/arch/arm/sunxi/sunxi_pwm.c
162
ctrl |= PWM_CH0_ACT_STA;
sys/arch/arm/sunxi/sunxi_pwm.c
164
ctrl &= ~PWM_CH0_ACT_STA;
sys/arch/arm/sunxi/sunxi_pwm.c
174
PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
sys/arch/arm/sunxi/sunxi_rsb.c
283
uint32_t dar, ctrl;
sys/arch/arm/sunxi/sunxi_rsb.c
296
ctrl = RSB_READ(sc, RSB_CTRL_REG);
sys/arch/arm/sunxi/sunxi_rsb.c
297
if (ctrl & RSB_CTRL_START_TRANS) {
sys/arch/arm/sunxi/sunxi_rsb.c
304
ctrl | RSB_CTRL_START_TRANS);
sys/arch/arm/sunxi/sunxi_rsb.c
314
uint32_t dlen, ctrl;
sys/arch/arm/sunxi/sunxi_rsb.c
418
ctrl = RSB_READ(sc, RSB_CTRL_REG);
sys/arch/arm/sunxi/sunxi_rsb.c
419
if (ctrl & RSB_CTRL_START_TRANS) {
sys/arch/arm/sunxi/sunxi_rsb.c
427
ctrl | RSB_CTRL_START_TRANS);
sys/arch/arm/sunxi/sunxi_wdt.c
158
const uint32_t ctrl = SUN4I_WDT_CTRL_RSTART |
sys/arch/arm/sunxi/sunxi_wdt.c
161
WDT_WRITE(sc, SUN4I_WDT_CTRL_REG, ctrl);
sys/arch/arm/sunxi/sunxi_wdt.c
197
const uint32_t ctrl = SUN6I_WDT_CTRL_RSTART |
sys/arch/arm/sunxi/sunxi_wdt.c
200
WDT_WRITE(sc, SUN6I_WDT_CTRL_REG, ctrl);
sys/arch/emips/ebus/flash_ebus.c
261
uint32_t base, ctrl;
sys/arch/emips/ebus/flash_ebus.c
274
ctrl = sc->sc_dp->Control;
sys/arch/emips/ebus/flash_ebus.c
276
sc->sc_size = ctrl & FLASHST_SIZE;
sys/arch/emips/ebus/flash_ebus.c
280
sc->sc_chips = (ctrl & FLASHST_BUS_32) ? 2 : 1;
sys/arch/epoc32/windermere/windermere.c
246
uint32_t ctrl;
sys/arch/epoc32/windermere/windermere.c
254
ctrl = TC_READ(tc1, TC_CTRL);
sys/arch/epoc32/windermere/windermere.c
255
ctrl |= (CTRL_CLKSEL | CTRL_MODE | CTRL_ENABLE); /* select 512kHz */
sys/arch/epoc32/windermere/windermere.c
256
TC_WRITE(tc1, TC_CTRL, ctrl);
sys/arch/epoc32/windermere/windermere.c
261
ctrl = TC_READ(tc2, TC_CTRL);
sys/arch/epoc32/windermere/windermere.c
262
ctrl |= (CTRL_CLKSEL | CTRL_MODE | CTRL_ENABLE); /* select 512kHz */
sys/arch/epoc32/windermere/windermere.c
263
TC_WRITE(tc2, TC_CTRL, ctrl);
sys/arch/evbarm/armadillo/armadillo9_machdep.c
373
uint32_t ctrl = EP93XX_APB_VBASE + EP93XX_APB_WDOG + EP93XX_WDOG_Ctrl;
sys/arch/evbarm/armadillo/armadillo9_machdep.c
378
: "r" (ctrl), "r" (val)
sys/arch/evbarm/tsarm/tsarm_machdep.c
288
uint32_t feed, ctrl;
sys/arch/evbarm/tsarm/tsarm_machdep.c
291
ctrl = TS7XXX_IO16_VBASE + TS7XXX_WDOGCTRL;
sys/arch/evbarm/tsarm/tsarm_machdep.c
299
: "r" (feed), "r" (ctrl)
sys/arch/evbarm/tsarm/tslcd.c
175
uint8_t ctrl;
sys/arch/evbarm/tsarm/tslcd.c
181
ctrl = GPIO_GET(PHDR);
sys/arch/evbarm/tsarm/tslcd.c
185
ctrl |= 0x10; /* assert RS */
sys/arch/evbarm/tsarm/tslcd.c
186
ctrl &= ~0x20; /* assert WR */
sys/arch/evbarm/tsarm/tslcd.c
188
ctrl &= ~0x30; /* de-assert WR, de-assert RS */
sys/arch/evbarm/tsarm/tslcd.c
190
GPIO_SET(PHDR, ctrl);
sys/arch/evbarm/tsarm/tslcd.c
196
ctrl |= 0x8;
sys/arch/evbarm/tsarm/tslcd.c
197
GPIO_SET(PHDR, ctrl);
sys/arch/evbarm/tsarm/tslcd.c
203
ctrl &= ~0x8;
sys/arch/evbarm/tsarm/tslcd.c
204
GPIO_SET(PHDR, ctrl);
sys/arch/evbarm/tsarm/tslcd.c
210
ctrl |= 0x2;
sys/arch/evbarm/tsarm/tslcd.c
211
GPIO_SET(PHDR, ctrl);
sys/arch/evbarm/tsarm/tslcd.c
221
uint8_t ret, ctrl;
sys/arch/evbarm/tsarm/tslcd.c
227
ctrl = GPIO_GET(PHDR);
sys/arch/evbarm/tsarm/tslcd.c
230
ctrl |= 0x30; /* de-assert WR, assert RS */
sys/arch/evbarm/tsarm/tslcd.c
232
ctrl |= 0x20; /* de-assert WR */
sys/arch/evbarm/tsarm/tslcd.c
233
ctrl &= ~0x10; /* de-assert RS */
sys/arch/evbarm/tsarm/tslcd.c
235
GPIO_SET(PHDR, ctrl);
sys/arch/evbarm/tsarm/tslcd.c
241
ctrl |= 0x8;
sys/arch/evbarm/tsarm/tslcd.c
242
GPIO_SET(PHDR, ctrl);
sys/arch/evbarm/tsarm/tslcd.c
249
ctrl &= ~0x8;
sys/arch/evbarm/tsarm/tslcd.c
250
GPIO_SET(PHDR, ctrl);
sys/arch/evbmips/loongson/dev/kb3310.c
445
int ctrl;
sys/arch/evbmips/loongson/dev/kb3310.c
460
ctrl = PMUCFG_SCI_WAKEUP | PMUCFG_WDT_WAKEUP | PMUCFG_GPWU_WAKEUP |
sys/arch/evbmips/loongson/dev/kb3310.c
462
ykbec_write(sc, REG_PMUCFG, ctrl);
sys/arch/evbppc/nintendo/dev/hwaes.c
254
uint32_t ctrl;
sys/arch/evbppc/nintendo/dev/hwaes.c
262
ctrl = AES_CTRL_EXEC | AES_CTRL_ENA | flags;
sys/arch/evbppc/nintendo/dev/hwaes.c
263
ctrl |= __SHIFTIN(blocks - 1, AES_CTRL_BLOCKS);
sys/arch/evbppc/nintendo/dev/hwaes.c
265
WR4(sc, AES_CTRL, ctrl);
sys/arch/evbppc/nintendo/dev/hwaes.c
267
ctrl = RD4(sc, AES_CTRL);
sys/arch/evbppc/nintendo/dev/hwaes.c
268
if ((ctrl & AES_CTRL_ERR) != 0) {
sys/arch/evbppc/nintendo/dev/hwaes.c
269
printf("AES error, AES_CTRL = %#x\n", ctrl);
sys/arch/evbppc/nintendo/dev/hwaes.c
272
if ((ctrl & AES_CTRL_EXEC) == 0) {
sys/arch/ews4800mips/include/sbd_tr2.h
142
uint32_t ctrl; /* DMA status/command */
sys/arch/ews4800mips/stand/common/cons_zskbd.c
130
zskbd.ctrl = map_ctrl;
sys/arch/ews4800mips/stand/common/cons_zskbd.c
230
return *(zskbd.ctrl + c);
sys/arch/ews4800mips/stand/common/console.h
93
const uint8_t *ctrl;
sys/arch/hppa/dev/mongoose.c
94
uint8_t ctrl;
sys/arch/mips/alchemy/dev/aupsc.c
106
struct aupsc_controller ctrl;
sys/arch/mips/alchemy/dev/aupsc.c
127
ctrl.psc_bust = sc->sc_bust;
sys/arch/mips/alchemy/dev/aupsc.c
128
ctrl.psc_bush = sc->sc_bush;
sys/arch/mips/alchemy/dev/aupsc.c
129
ctrl.psc_sel = &(sc->sc_pscsel);
sys/arch/mips/alchemy/dev/aupsc.c
130
ctrl.psc_enable = aupsc_enable;
sys/arch/mips/alchemy/dev/aupsc.c
131
ctrl.psc_disable = aupsc_disable;
sys/arch/mips/alchemy/dev/aupsc.c
132
ctrl.psc_suspend = aupsc_suspend;
sys/arch/mips/alchemy/dev/aupsc.c
133
pa.aupsc_ctrl = ctrl;
sys/arch/mips/alchemy/dev/aupsc.c
144
p.sc_ctrl = ctrl;
sys/arch/mips/bonito/bonito_iobc.c
78
uint32_t ctrl;
sys/arch/mips/bonito/bonito_iobc.c
80
ctrl = (cmd << BONITO_PCICACHECTRL_CACHECMD_SHIFT) |
sys/arch/mips/bonito/bonito_iobc.c
83
REGVAL(BONITO_PCICACHECTRL) = ctrl;
sys/arch/mips/bonito/bonito_iobc.c
86
REGVAL(BONITO_PCICACHECTRL) = ctrl | BONITO_PCICACHECTRL_CMDEXEC;
sys/arch/mips/bonito/bonito_iobc.c
92
REGVAL(BONITO_PCICACHECTRL) = ctrl;
sys/arch/mips/cavium/dev/octeon_mpi.c
129
sc->ctrl.sc_bust = sc->sc_regt;
sys/arch/mips/cavium/dev/octeon_mpi.c
130
sc->ctrl.sc_bush = sc->sc_regh;
sys/arch/mips/cavium/dev/octeon_mpi.c
131
sc->ctrl.sct_cookie = sc;
sys/arch/mips/cavium/dev/octeon_mpi.c
132
sc->ctrl.sct_configure = octmpi_configure;
sys/arch/mips/cavium/dev/octeon_mpi.c
133
sc->ctrl.sct_read = octmpi_read;
sys/arch/mips/cavium/dev/octeon_mpi.c
134
sc->ctrl.sct_write = octmpi_write;
sys/arch/mips/cavium/dev/octeon_mpi.c
135
pa.octmpi_ctrl = &(sc->ctrl);
sys/arch/mips/cavium/dev/octeon_mpi.c
61
struct octmpi_controller ctrl;
sys/arch/mvme68k/include/prom.h
64
u_char ctrl;
sys/arch/mvme68k/stand/libsa/bugdev.c
128
dio.ctrl_lun = pp->ctrl;
sys/arch/mvme68k/stand/libsa/bugdev.c
161
bugsc_softc[0].ctrl = (short)bugargs.ctrl_lun;
sys/arch/mvme68k/stand/libsa/bugdev.c
165
bugsc_softc[0].ctrl, bugsc_softc[0].dev);
sys/arch/mvme68k/stand/libsa/bugdev.c
47
short ctrl;
sys/arch/powerpc/mpc5200/pic_mpc5200.c
173
m->ctrl = SIU_CTRL_INIT;
sys/arch/powerpc/mpc5200/pic_mpc5200.c
179
siu_write(m, SIU_CTRL, m->ctrl);
sys/arch/powerpc/mpc5200/pic_mpc5200.c
216
m->ctrl |= bit;
sys/arch/powerpc/mpc5200/pic_mpc5200.c
217
siu_write(m, SIU_CTRL, m->ctrl);
sys/arch/powerpc/mpc5200/pic_mpc5200.c
249
m->ctrl &= ~bit;
sys/arch/powerpc/mpc5200/pic_mpc5200.c
250
siu_write(m, SIU_CTRL, m->ctrl);
sys/arch/powerpc/mpc5200/pic_mpc5200var.h
44
uint32_t ctrl; /* shadow of SIU_CTRL */
sys/arch/sgimips/hpc/haltwo.c
665
uint32_t ctrl;
sys/arch/sgimips/hpc/haltwo.c
701
ctrl = HPC3_PBUS_DMACTL_RT
sys/arch/sgimips/hpc/haltwo.c
714
ctrl | HPC3_PBUS_DMACTL_ACT);
sys/arch/sgimips/mace/macekbc.c
266
uint32_t ctrl;
sys/arch/sgimips/mace/macekbc.c
283
ctrl = bus_space_read_8(iot, ioh, MACEKBC_CTRL);
sys/arch/sgimips/mace/macekbc.c
299
ctrl | MACEKBC_CTRL_RXCLKON | MACEKBC_CTRL_TXON);
sys/arch/sparc64/dev/bq4802_ebus.c
105
uint8_t ctrl, new;
sys/arch/sparc64/dev/bq4802_ebus.c
127
ctrl = bq4802_read(sc, BQ4802_CTRL);
sys/arch/sparc64/dev/bq4802_ebus.c
128
if (ctrl & BQ4802_CTRL_STP)
sys/arch/sparc64/dev/bq4802_ebus.c
132
"WARNING: oscillator is stopped (0x%02x)\n", ctrl);
sys/arch/sparc64/dev/bq4802_ebus.c
135
new = ctrl & ~(BQ4802_CTRL_DSE | BQ4802_CTRL_UTI);
sys/arch/sparc64/dev/bq4802_ebus.c
137
if (new != ctrl)
sys/arch/sparc64/dev/bq4802_ebus.c
138
bq4802_write(sc, BQ4802_CTRL, ctrl);
sys/arch/sparc64/dev/bq4802_ebus.c
223
uint8_t ctrl;
sys/arch/sparc64/dev/bq4802_ebus.c
235
ctrl = bq4802_read(sc, BQ4802_CTRL);
sys/arch/sparc64/dev/bq4802_ebus.c
237
ctrl &= ~BQ4802_CTRL_STP;
sys/arch/sparc64/dev/bq4802_ebus.c
239
ctrl |= BQ4802_CTRL_STP;
sys/arch/sparc64/dev/bq4802_ebus.c
240
bq4802_write(sc, BQ4802_CTRL, ctrl);
sys/arch/sparc64/dev/fhc.c
63
u_int32_t ctrl;
sys/arch/sparc64/dev/fhc.c
74
ctrl = bus_space_read_4(sc->sc_bt, sc->sc_preg, FHC_P_CTRL);
sys/arch/sparc64/dev/fhc.c
76
ctrl |= FHC_P_CTRL_IXIST;
sys/arch/sparc64/dev/fhc.c
77
ctrl &= ~(FHC_P_CTRL_AOFF | FHC_P_CTRL_BOFF | FHC_P_CTRL_SLINE);
sys/arch/sparc64/dev/fhc.c
78
bus_space_write_4(sc->sc_bt, sc->sc_preg, FHC_P_CTRL, ctrl);
sys/arch/sparc64/dev/fire_i2c.c
225
uint8_t ctrl, val;
sys/arch/sparc64/dev/fire_i2c.c
227
ctrl = FIREI2C_CTRL_ENAB | FIREI2C_CTRL_STP;
sys/arch/sparc64/dev/fire_i2c.c
228
firei2c_reg_write(sc, FIREI2C_CTRL, ctrl);
sys/arch/sparc64/dev/fire_i2c.c
236
ctrl = FIREI2C_CTRL_ENAB;
sys/arch/sparc64/dev/fire_i2c.c
237
firei2c_reg_write(sc, FIREI2C_CTRL, ctrl);
sys/arch/sparc64/dev/fire_i2c.c
245
volatile uint8_t ctrl;
sys/arch/sparc64/dev/fire_i2c.c
250
ctrl = firei2c_reg_read(sc, FIREI2C_CTRL);
sys/arch/sparc64/dev/fire_i2c.c
251
if (ctrl & FIREI2C_CTRL_IFLG)
sys/arch/sparc64/dev/fire_i2c.c
299
uint8_t ctrl, val, ack, nack;
sys/arch/sparc64/dev/fire_i2c.c
316
ctrl = FIREI2C_CTRL_ENAB;
sys/arch/sparc64/dev/fire_i2c.c
318
ctrl |= FIREI2C_CTRL_IEN;
sys/arch/sparc64/dev/fire_i2c.c
334
val = ctrl | FIREI2C_CTRL_STA;
sys/arch/sparc64/dev/fire_i2c.c
361
firei2c_reg_write(sc, FIREI2C_CTRL, ctrl);
sys/arch/sparc64/dev/fire_i2c.c
382
NULL, 0, ctrl, flags);
sys/arch/sparc64/dev/fire_i2c.c
387
val = ctrl | FIREI2C_CTRL_STA;
sys/arch/sparc64/dev/fire_i2c.c
409
firei2c_reg_write(sc, FIREI2C_CTRL, ctrl);
sys/arch/sparc64/dev/fire_i2c.c
427
err = firei2c_read(sc, buf, buflen, ctrl, flags);
sys/arch/sparc64/dev/fire_i2c.c
430
err = firei2c_write(sc, cmd, cmdlen, buf, buflen, ctrl, flags);
sys/arch/sparc64/dev/fire_i2c.c
440
uint8_t *buf, size_t buflen, int ctrl, int flags)
sys/arch/sparc64/dev/fire_i2c.c
452
firei2c_reg_write(sc, FIREI2C_CTRL, ctrl);
sys/arch/sparc64/dev/fire_i2c.c
473
int ctrl, int flags)
sys/arch/sparc64/dev/fire_i2c.c
481
val = ctrl | FIREI2C_CTRL_AAK;
sys/arch/sparc64/dev/fire_i2c.c
484
val = ctrl;
sys/arch/sparc64/dev/fire_i2c.c
510
uint8_t ctrl;
sys/arch/sparc64/dev/fire_i2c.c
513
ctrl = firei2c_reg_read(sc, FIREI2C_CTRL);
sys/arch/sparc64/dev/fire_i2c.c
514
if (ctrl & FIREI2C_CTRL_IFLG) {
sys/arch/sparc64/dev/fire_i2c.c
516
firei2c_reg_write(sc, FIREI2C_CTRL, ctrl & ~FIREI2C_CTRL_IEN);
sys/arch/sparc64/dev/ldc.c
263
lp->ctrl = LDC_VERS;
sys/arch/sparc64/dev/ldc.c
302
lp->ctrl = LDC_VERS;
sys/arch/sparc64/dev/ldc.c
340
lp->ctrl = LDC_RTS;
sys/arch/sparc64/dev/ldc.c
378
lp->ctrl = LDC_RTR;
sys/arch/sparc64/dev/ldc.c
416
lp->ctrl = LDC_RDX;
sys/arch/sparc64/dev/ldc.c
49
switch (lp->ctrl) {
sys/arch/sparc64/dev/ldc.c
67
DPRINTF(("CTRL/0x%02x/0x%02x\n", lp->stype, lp->ctrl));
sys/arch/sparc64/dev/ldcvar.h
55
uint8_t ctrl;
sys/arch/sparc64/dev/pcf8591_envctrl.c
325
u_int8_t ctrl = PCF8591_CTRL_CH0 | PCF8591_CTRL_AUTOINC |
sys/arch/sparc64/dev/pcf8591_envctrl.c
331
&ctrl, 1, NULL, 0, 0)) {
sys/arch/sparc64/dev/pcf8591_envctrl.c
441
u_int8_t ctrl = PCF8591_CTRL_AUTOINC | PCF8591_CTRL_OSCILLATOR;
sys/arch/sparc64/dev/pcf8591_envctrl.c
444
ctrl |= chan;
sys/arch/sparc64/dev/pcf8591_envctrl.c
452
&ctrl, 1, &val, 1, 0);
sys/arch/sparc64/dev/schizo.c
395
u_int64_t afsr, afar, ctrl, tfar;
sys/arch/sparc64/dev/schizo.c
401
ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL);
sys/arch/sparc64/dev/schizo.c
410
snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl);
sys/arch/sparc64/dev/schizo.c
417
if (ctrl & SCZ_PCICTRL_MMU_ERR) {
sys/arch/sparc64/dev/schizo.c
418
ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL);
sys/arch/sparc64/dev/schizo.c
419
printf("IOMMUCTRL=%" PRIx64 "\n", ctrl);
sys/arch/sparc64/dev/schizo.c
421
if ((ctrl & TOM_IOMMU_ERR) == 0)
sys/arch/sparc64/dev/schizo.c
430
if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR ||
sys/arch/sparc64/dev/schizo.c
431
ctrl & TOM_IOMMU_ILLTSBTBW_ERR ||
sys/arch/sparc64/dev/schizo.c
432
ctrl & TOM_IOMMU_BADVA_ERR) {
sys/arch/sparc64/dev/schizo.c
434
schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl);
sys/arch/sparc64/dev/schizo.c
444
schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl);
sys/arch/sparc64/dev/schizoreg.h
47
volatile u_int64_t ctrl;
sys/arch/sparc64/dev/vdsk.c
527
lp->ctrl));
sys/arch/sparc64/dev/vnet.c
443
__func__, lp->type, lp->stype, lp->ctrl));
sys/arch/sun2/dev/if_ie_obio.c
231
uint8_t ctrl;
sys/arch/sun2/dev/if_ie_obio.c
242
!bus_space_peek_1(oba->oba_bustag, bh, 0, &ctrl) &&
sys/arch/sun2/dev/if_ie_obio.c
243
(ctrl & (IEOB_ONAIR|IEOB_IENAB)) == 0);
sys/arch/sun3/dev/xd.c
1205
struct xd_iopb_ctrl *ctrl =
sys/arch/sun3/dev/xd.c
1210
ctrl->param_a = XDPA_TMOD | XDPA_DACF;
sys/arch/sun3/dev/xd.c
1211
ctrl->param_b = XDPB_ROR | XDPB_TDT_3_2USEC;
sys/arch/sun3/dev/xd.c
1212
ctrl->param_c = XDPC_OVS | XDPC_COP | XDPC_ASR |
sys/arch/sun3/dev/xd.c
1214
ctrl->throttle = XDC_THROTTLE;
sys/arch/sun3/dev/xd.c
1217
ctrl->delay = XDC_DELAY_4_300;
sys/arch/sun3/dev/xd.c
1219
ctrl->delay = XDC_DELAY_SPARC;
sys/arch/sun3/dev/xd.c
1222
ctrl->delay = XDC_DELAY_SUN3;
sys/arch/x68k/x68k/iodevice.h
277
char pad3; unsigned char ctrl;
sys/arch/x86/acpi/acpi_cpu_md.c
812
const uint64_t ctrl = ps->ps_control;
sys/arch/x86/acpi/acpi_cpu_md.c
823
fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID);
sys/arch/x86/acpi/acpi_cpu_md.c
824
vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID);
sys/arch/x86/acpi/acpi_cpu_md.c
825
irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT);
sys/arch/x86/acpi/acpi_cpu_md.c
826
vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST);
sys/arch/x86/acpi/acpi_cpu_md.c
827
pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL);
sys/arch/x86/acpi/acpi_cpu_md.c
838
val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS);
sys/arch/x86/acpi/acpi_cpu_md.c
848
i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO);
sys/arch/x86/x86/powernow.c
137
static uint64_t powernow_k8_fidvid(u_int fid, uint64_t vid, uint64_t ctrl);
sys/arch/x86/x86/powernow.c
902
powernow_k8_fidvid(u_int fid, uint64_t vid, uint64_t ctrl)
sys/arch/x86/x86/powernow.c
908
msr.msr_value = (ctrl << 32) | (1ULL << 16) | (vid << 8) | fid;
sys/dev/hdaudio/hdafg.c
2003
w->w_pin.ctrl &= ~(
sys/dev/hdaudio/hdafg.c
2022
w->w_pin.ctrl |= COP_PWC_OUT_ENABLE;
sys/dev/hdaudio/hdafg.c
2029
w->w_pin.ctrl |= COP_PWC_IN_ENABLE;
sys/dev/hdaudio/hdafg.c
2032
w->w_pin.ctrl);
sys/dev/hdaudio/hdafg.c
2038
w->w_pin.ctrl |= COP_PWC_VREF_80;
sys/dev/hdaudio/hdafg.c
2040
w->w_pin.ctrl |= COP_PWC_VREF_50;
sys/dev/hdaudio/hdafg.c
2044
w->w_pin.ctrl |= COP_PWC_OUT_ENABLE;
sys/dev/hdaudio/hdafg.c
2048
w->w_pin.ctrl |= COP_PWC_HPHN_ENABLE;
sys/dev/hdaudio/hdafg.c
2051
w->w_pin.ctrl);
sys/dev/hdaudio/hdafg.c
251
uint32_t ctrl;
sys/dev/hdaudio/hdafg.c
3095
CORB_SET_PIN_WIDGET_CONTROL, w->w_pin.ctrl);
sys/dev/hdaudio/hdafg.c
3600
w->w_pin.ctrl |= COP_PWC_OUT_ENABLE;
sys/dev/hdaudio/hdafg.c
3602
w->w_pin.ctrl &= ~COP_PWC_OUT_ENABLE;
sys/dev/hdaudio/hdafg.c
3604
CORB_SET_PIN_WIDGET_CONTROL, w->w_pin.ctrl);
sys/dev/hdaudio/hdafg.c
3610
w->w_pin.ctrl &= ~COP_PWC_OUT_ENABLE;
sys/dev/hdaudio/hdafg.c
3612
w->w_pin.ctrl |= COP_PWC_OUT_ENABLE;
sys/dev/hdaudio/hdafg.c
3614
CORB_SET_PIN_WIDGET_CONTROL, w->w_pin.ctrl);
sys/dev/hdaudio/hdafg.c
627
w->w_pin.ctrl = hdaudio_command(sc->sc_codec, w->w_nid,
sys/dev/i2c/anxedp.c
176
uint8_t ctrl[2];
sys/dev/i2c/anxedp.c
179
ctrl[0] = __SHIFTIN(comm, ANX_AUX_TX_COMM);
sys/dev/i2c/anxedp.c
181
ctrl[0] |= __SHIFTIN(buflen - 1, ANX_AUX_LENGTH);
sys/dev/i2c/anxedp.c
182
ctrl[1] = ANX_AUX_EN;
sys/dev/i2c/anxedp.c
184
ctrl[1] |= ANX_ADDR_ONLY;
sys/dev/i2c/anxedp.c
194
anxedp_write(sc, 0, ANX_DP_AUX_CH_CTL_1, ctrl[0]);
sys/dev/i2c/anxedp.c
195
anxedp_write(sc, 0, ANX_DP_AUX_CH_CTL_2, ctrl[1]);
sys/dev/i2c/axppmic.c
1288
const struct axppmic_ctrl *ctrl = &c->controls[i];
sys/dev/i2c/axppmic.c
1289
child = of_find_firstchild_byname(phandle, ctrl->c_name);
sys/dev/i2c/axppmic.c
1292
aaa.reg_ctrl = ctrl;
sys/dev/i2c/es8316ac.c
177
enum escodec_mixer_ctrl ctrl;
sys/dev/i2c/rkpmic.c
133
.ctrl = rk805_ctrls,
sys/dev/i2c/rkpmic.c
197
.ctrl = rk808_ctrls,
sys/dev/i2c/rkpmic.c
524
child = of_find_firstchild_byname(regulators, sc->sc_conf->ctrl[n].name);
sys/dev/i2c/rkpmic.c
527
raa.reg_ctrl = &sc->sc_conf->ctrl[n];
sys/dev/i2c/rkpmic.c
92
const struct rkpmic_ctrl *ctrl;
sys/dev/ic/bq4802reg.h
140
uint8_t ctrl; \
sys/dev/ic/bq4802reg.h
143
ctrl = bq4802_read(sc, BQ4802_CTRL); \
sys/dev/ic/bq4802reg.h
144
bq4802_write(sc, BQ4802_CTRL, ctrl | BQ4802_CTRL_UTI); \
sys/dev/ic/bq4802reg.h
152
bq4802_write(sc, BQ4802_CTRL, ctrl); \
sys/dev/ic/bq4802reg.h
162
uint8_t ctrl; \
sys/dev/ic/bq4802reg.h
165
ctrl = bq4802_read(sc, BQ4802_CTRL); \
sys/dev/ic/bq4802reg.h
166
bq4802_write(sc, BQ4802_CTRL, ctrl | BQ4802_CTRL_UTI); \
sys/dev/ic/bq4802reg.h
174
bq4802_write(sc, BQ4802_CTRL, ctrl); \
sys/dev/ic/bwi.c
3039
bwi_phy_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
sys/dev/ic/bwi.c
3044
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
sys/dev/ic/bwi.c
3049
bwi_phy_read(struct bwi_mac *mac, uint16_t ctrl)
sys/dev/ic/bwi.c
3054
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
sys/dev/ic/bwi.c
3961
bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
sys/dev/ic/bwi.c
3965
CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
sys/dev/ic/bwi.c
3970
bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
sys/dev/ic/bwi.c
3975
ctrl |= rf->rf_ctrl_rd;
sys/dev/ic/bwi.c
3978
if (ctrl < 0x70)
sys/dev/ic/bwi.c
3979
ctrl += 0x80;
sys/dev/ic/bwi.c
3980
else if (ctrl < 0x80)
sys/dev/ic/bwi.c
3981
ctrl += 0x70;
sys/dev/ic/bwi.c
3984
CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
sys/dev/ic/bwi.c
5163
bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
sys/dev/ic/bwi.c
5170
ctrl <<= 8;
sys/dev/ic/bwi.c
5175
PHY_WRITE(mac, 0x812, ctrl | 0xb0);
sys/dev/ic/bwi.c
5177
PHY_WRITE(mac, 0x812, ctrl | 0xb2);
sys/dev/ic/bwi.c
5179
PHY_WRITE(mac, 0x812, ctrl | 0xb3);
sys/dev/ic/bwi.c
5183
PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
sys/dev/ic/bwi.c
5185
PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
sys/dev/ic/bwi.c
5187
PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
sys/dev/ic/bwi.c
6470
uint32_t ctrl, addr, addr_hi, addr_lo;
sys/dev/ic/bwi.c
6478
ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
sys/dev/ic/bwi.c
6481
ctrl |= BWI_DESC32_C_EOR;
sys/dev/ic/bwi.c
6484
ctrl |= BWI_DESC32_C_FRAME_START |
sys/dev/ic/bwi.c
6490
desc->ctrl = htole32(ctrl);
sys/dev/ic/bwivar.h
114
uint32_t ctrl;
sys/dev/ic/bwivar.h
847
#define PHY_WRITE(mac, ctrl, val) bwi_phy_write((mac), (ctrl), (val))
sys/dev/ic/bwivar.h
848
#define PHY_READ(mac, ctrl) bwi_phy_read((mac), (ctrl))
sys/dev/ic/bwivar.h
850
#define PHY_SETBITS(mac, ctrl, bits) \
sys/dev/ic/bwivar.h
851
PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) | (bits))
sys/dev/ic/bwivar.h
852
#define PHY_CLRBITS(mac, ctrl, bits) \
sys/dev/ic/bwivar.h
853
PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) & ~(bits))
sys/dev/ic/bwivar.h
854
#define PHY_FILT_SETBITS(mac, ctrl, filt, bits) \
sys/dev/ic/bwivar.h
855
PHY_WRITE((mac), (ctrl), (PHY_READ((mac), (ctrl)) & (filt)) | (bits))
sys/dev/ic/dwc_mmc.c
216
uint32_t fifoth, ctrl;
sys/dev/ic/dwc_mmc.c
228
ctrl = MMC_READ(sc, DWC_MMC_GCTRL);
sys/dev/ic/dwc_mmc.c
229
ctrl &= ~DWC_MMC_GCTRL_USE_INTERNAL_DMAC;
sys/dev/ic/dwc_mmc.c
230
MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl);
sys/dev/ic/dwc_mmc.c
260
ctrl = MMC_READ(sc, DWC_MMC_GCTRL);
sys/dev/ic/dwc_mmc.c
261
ctrl |= DWC_MMC_GCTRL_INTEN;
sys/dev/ic/dwc_mmc.c
262
ctrl |= DWC_MMC_GCTRL_DMAEN;
sys/dev/ic/dwc_mmc.c
263
ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD;
sys/dev/ic/dwc_mmc.c
264
ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC;
sys/dev/ic/dwc_mmc.c
265
MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl);
sys/dev/ic/mvsata.c
656
uint32_t sstat, ctrl;
sys/dev/ic/mvsata.c
676
ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG);
sys/dev/ic/mvsata.c
677
ctrl &= ~(1 << 17); /* Disable GenII */
sys/dev/ic/mvsata.c
678
MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl);
sys/dev/ic/seeq8005.c
1125
int ctrl;
sys/dev/ic/seeq8005.c
1145
ctrl = rxhdr[2];
sys/dev/ic/seeq8005.c
1150
addr, ptr, ctrl, status));
sys/dev/ic/seeq8005.c
1157
(ctrl & SEEQ_PKTCMD_TX))) {
sys/dev/ic/sl811hs.c
2774
uint8_t r, pol, ctrl;
sys/dev/ic/sl811hs.c
2813
pol = ctrl = 0;
sys/dev/ic/sl811hs.c
2817
ctrl = SL11_CTRL_LOWSPEED;
sys/dev/ic/sl811hs.c
2825
slhci_write(sc, SL11_CTRL, ctrl|SL11_CTRL_ENABLESOF);
sys/dev/isa/gus.c
2910
u_char ctrl;
sys/dev/isa/gus.c
2915
ctrl = (port & 0xf0) >> 4; /* set port address middle nibble */
sys/dev/isa/gus.c
2919
ctrl |= GUS_MAX_CODEC_ENABLE;
sys/dev/isa/gus.c
2921
ctrl |= GUS_MAX_RECCHAN16;
sys/dev/isa/gus.c
2923
ctrl |= GUS_MAX_PLAYCHAN16;
sys/dev/isa/gus.c
2925
bus_space_write_1(iot, ioh1, GUS_MAX_CTRL, ctrl);
sys/dev/nvmm/x86/nvmm_x86_svm.c
1115
exit->u.insn.npc = vmcb->ctrl.nrip;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1199
uint64_t info = cpudata->vmcb->ctrl.exitinfo1;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1200
uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1320
exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1343
exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1358
uint64_t info = cpudata->vmcb->ctrl.exitinfo1;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1372
gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1375
if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1377
else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_I)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1382
exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1383
memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes,
sys/dev/nvmm/x86/nvmm_x86_svm.c
1678
vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1687
if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) {
sys/dev/nvmm/x86/nvmm_x86_svm.c
1697
if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) {
sys/dev/nvmm/x86/nvmm_x86_svm.c
1698
vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1737
vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1739
vmcb->ctrl.tlb_ctrl = 0;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1743
vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc();
sys/dev/nvmm/x86/nvmm_x86_svm.c
1757
if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) {
sys/dev/nvmm/x86/nvmm_x86_svm.c
1764
switch (vmcb->ctrl.exitcode) {
sys/dev/nvmm/x86/nvmm_x86_svm.c
1826
svm_exit_invalid(exit, vmcb->ctrl.exitcode);
sys/dev/nvmm/x86/nvmm_x86_svm.c
1839
cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset;
sys/dev/nvmm/x86/nvmm_x86_svm.c
1847
exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR);
sys/dev/nvmm/x86/nvmm_x86_svm.c
1849
((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0);
sys/dev/nvmm/x86/nvmm_x86_svm.c
2074
vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2075
vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8],
sys/dev/nvmm/x86/nvmm_x86_svm.c
2119
vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2121
vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2213
state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v,
sys/dev/nvmm/x86/nvmm_x86_svm.c
2249
(vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2304
vmcb->ctrl.guest_asid = i;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2314
vmcb->ctrl.guest_asid = svm_maxasid - 1;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2329
oct = vmcb->ctrl.guest_asid / 8;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2330
bit = vmcb->ctrl.guest_asid % 8;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2344
vmcb->ctrl.intercept_cr = 0;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2347
vmcb->ctrl.intercept_dr = 0;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2350
vmcb->ctrl.intercept_vec = 0;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2376
vmcb->ctrl.intercept_misc1 =
sys/dev/nvmm/x86/nvmm_x86_svm.c
2399
vmcb->ctrl.intercept_misc2 =
sys/dev/nvmm/x86/nvmm_x86_svm.c
2416
vmcb->ctrl.intercept_misc3 =
sys/dev/nvmm/x86/nvmm_x86_svm.c
2424
vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2440
vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2446
vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2449
vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP;
sys/dev/nvmm/x86/nvmm_x86_svm.c
2450
vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0];
sys/dev/nvmm/x86/nvmm_x86_svm.c
477
struct vmcb_ctrl ctrl;
sys/dev/nvmm/x86/nvmm_x86_svm.c
624
vmcb->ctrl.vmcb_clean =
sys/dev/nvmm/x86/nvmm_x86_svm.c
643
vmcb->ctrl.vmcb_clean &=
sys/dev/nvmm/x86/nvmm_x86_svm.c
647
vmcb->ctrl.vmcb_clean &=
sys/dev/nvmm/x86/nvmm_x86_svm.c
652
vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR;
sys/dev/nvmm/x86/nvmm_x86_svm.c
656
vmcb->ctrl.vmcb_clean &=
sys/dev/nvmm/x86/nvmm_x86_svm.c
664
vmcb->ctrl.vmcb_clean &= ~flags;
sys/dev/nvmm/x86/nvmm_x86_svm.c
670
vmcb->ctrl.vmcb_clean = 0;
sys/dev/nvmm/x86/nvmm_x86_svm.c
685
vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET;
sys/dev/nvmm/x86/nvmm_x86_svm.c
688
vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR;
sys/dev/nvmm/x86/nvmm_x86_svm.c
689
vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR);
sys/dev/nvmm/x86/nvmm_x86_svm.c
704
vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET;
sys/dev/nvmm/x86/nvmm_x86_svm.c
707
vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR;
sys/dev/nvmm/x86/nvmm_x86_svm.c
708
vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR);
sys/dev/nvmm/x86/nvmm_x86_svm.c
789
vmcb->ctrl.eventinj =
sys/dev/nvmm/x86/nvmm_x86_svm.c
847
vmcb->state.rip = vmcb->ctrl.nrip;
sys/dev/nvmm/x86/nvmm_x86_svm.c
849
vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW;
sys/dev/pci/autri.c
1067
uint32_t delta, dch[2], ctrl;
sys/dev/pci/autri.c
1074
ctrl = AUTRI_CTRL_LOOPMODE;
sys/dev/pci/autri.c
1078
ctrl |= AUTRI_CTRL_SIGNED;
sys/dev/pci/autri.c
1084
ctrl |= AUTRI_CTRL_16BIT;
sys/dev/pci/autri.c
1089
ctrl |= AUTRI_CTRL_STEREO;
sys/dev/pci/autri.c
1105
ctrl |= AUTRI_CTRL_WAVEVOL;
sys/dev/pci/autri.c
1110
ctrl |= AUTRI_CTRL_MUTEVOL_SIS;
sys/dev/pci/autri.c
1115
ctrl |= AUTRI_CTRL_MUTEVOL;
sys/dev/pci/autri.c
1131
ctrl |= AUTRI_CTRL_MUTEVOL_SIS;
sys/dev/pci/autri.c
1133
ctrl |= AUTRI_CTRL_MUTEVOL;
sys/dev/pci/autri.c
1146
cr[4] = ctrl;
sys/dev/pci/autri.c
1153
cr[4] = ctrl;
sys/dev/pci/autri.c
1160
cr[4] = ctrl;
sys/dev/pci/autri.c
1167
cr[4] = ctrl;
sys/dev/pci/cmdide.c
133
u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL);
sys/dev/pci/cmdide.c
177
if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) {
sys/dev/pci/coram.c
489
uint32_t ctrl;
sys/dev/pci/coram.c
495
ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1;
sys/dev/pci/coram.c
497
ctrl |= I2C_NOSTOP | I2C_EXTEND;
sys/dev/pci/coram.c
500
bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
sys/dev/pci/coram.c
524
uint32_t wdata, addrreg, ctrl;
sys/dev/pci/coram.c
531
ctrl = (0x9d << 24) | (1 << 12) | (1 << 2);
sys/dev/pci/coram.c
534
ctrl |= I2C_NOSTOP | I2C_EXTEND;
sys/dev/pci/coram.c
536
ctrl |= I2C_NOSTOP;
sys/dev/pci/coram.c
540
bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
sys/dev/pci/coram.c
546
ctrl = (0x9d << 24) | (1 << 12) | (1 << 2);
sys/dev/pci/coram.c
550
ctrl |= I2C_NOSTOP | I2C_EXTEND;
sys/dev/pci/coram.c
552
ctrl |= I2C_NOSTOP;
sys/dev/pci/coram.c
556
bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
sys/dev/pci/cxgb/cxgb_sge.c
228
u_int ctrl, ups;
sys/dev/pci/cxgb/cxgb_sge.c
232
ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |
sys/dev/pci/cxgb/cxgb_sge.c
237
ctrl |= F_EGRGENCTRL;
sys/dev/pci/cxgb/cxgb_sge.c
241
ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;
sys/dev/pci/cxgb/cxgb_sge.c
242
ctrl |= F_CQCRDTCTRL | F_AVOIDCQOVFL;
sys/dev/pci/cxgb/cxgb_sge.c
244
t3_write_reg(adap, A_SG_CONTROL, ctrl);
sys/dev/pci/cxgb/cxgb_xgmac.c
63
u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;
sys/dev/pci/cxgb/cxgb_xgmac.c
65
t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
sys/dev/pci/cxgb/cxgb_xgmac.c
69
(void)t3_read_reg(adap, ctrl);
sys/dev/pci/cxgb/cxgb_xgmac.c
73
t3_set_reg_field(adap, ctrl, clear[i], 0);
sys/dev/pci/if_bce.c
147
__bced->ctrl = htole32(BCE_RXBUF_LEN); \
sys/dev/pci/if_bce.c
149
__bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \
sys/dev/pci/if_bce.c
589
uint32_t ctrl;
sys/dev/pci/if_bce.c
591
ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK;
sys/dev/pci/if_bce.c
593
ctrl |= CTRL_SOF;
sys/dev/pci/if_bce.c
595
ctrl |= CTRL_EOF;
sys/dev/pci/if_bce.c
597
ctrl |= CTRL_EOT;
sys/dev/pci/if_bce.c
598
ctrl |= CTRL_IOC;
sys/dev/pci/if_bce.c
599
sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl);
sys/dev/pci/if_bce.c
71
uint32_t ctrl;
sys/dev/pci/if_et.c
451
uint32_t cfg1, cfg2, ctrl;
sys/dev/pci/if_et.c
474
ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
sys/dev/pci/if_et.c
475
ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
sys/dev/pci/if_et.c
490
ctrl |= ET_MAC_CTRL_MODE_MII;
sys/dev/pci/if_et.c
513
ctrl |= ET_MAC_CTRL_GHDX;
sys/dev/pci/if_et.c
515
CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
sys/dev/pci/if_tl.c
409
sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl,
sys/dev/pci/if_tl.c
670
memset(sc->ctrl, 0, PAGE_SIZE);
sys/dev/pci/if_tl.c
671
sc->hw_Rx_list = (void *)sc->ctrl;
sys/dev/pci/if_tl.c
673
(void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF);
sys/dev/pci/if_tl.c
674
nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF +
sys/dev/pci/if_tlvar.h
58
char *ctrl; /* vaddr for ctrl_segs */
sys/dev/pci/if_wm.c
13406
wm_tbi_havesignal(struct wm_softc *sc, uint32_t ctrl)
sys/dev/pci/if_wm.c
13410
sig = ctrl & CTRL_SWDPIN(1);
sys/dev/pci/if_wm.c
13541
uint32_t status, ctrl;
sys/dev/pci/if_wm.c
13575
ctrl = CSR_READ(sc, WMREG_CTRL);
sys/dev/pci/if_wm.c
13576
signal = wm_tbi_havesignal(sc, ctrl);
sys/dev/pci/if_wm.c
13654
uint32_t ctrl, status;
sys/dev/pci/if_wm.c
13675
ctrl = CSR_READ(sc, WMREG_CTRL);
sys/dev/pci/if_wm.c
13676
if (ctrl & CTRL_RFCE)
sys/dev/pci/if_wm.c
13678
if (ctrl & CTRL_TFCE)
sys/dev/pci/if_wm.c
13688
uint32_t ctrl;
sys/dev/pci/if_wm.c
13704
ctrl = CSR_READ(sc, WMREG_CTRL);
sys/dev/pci/if_wm.c
13706
signal = wm_tbi_havesignal(sc, ctrl);
sys/dev/pci/if_wm.c
13739
sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD;
sys/dev/pci/if_wm.c
13748
CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU));
sys/dev/pci/if_wm.c
13754
device_xname(sc->sc_dev), __func__, rxcw, ctrl,
sys/dev/pci/if_wm.c
17831
uint32_t ctrl, ctrl_ext, tmp;
sys/dev/pci/if_wm.c
17852
ctrl = CSR_READ(sc, WMREG_CTRL);
sys/dev/pci/if_wm.c
17855
tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100);
sys/dev/pci/if_wm.c
17863
CSR_WRITE(sc, WMREG_CTRL, ctrl);
sys/dev/pci/igc/if_igc.c
1543
uint32_t ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL);
sys/dev/pci/igc/if_igc.c
1544
ctrl |= IGC_CTRL_VME;
sys/dev/pci/igc/if_igc.c
1545
IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl);
sys/dev/pci/igc/igc_i225.c
185
uint32_t ctrl;
sys/dev/pci/igc/igc_i225.c
207
ctrl = IGC_READ_REG(hw, IGC_CTRL);
sys/dev/pci/igc/igc_i225.c
210
IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);
sys/dev/pci/igc/igc_i225.c
352
uint32_t ctrl, phpm_reg;
sys/dev/pci/igc/igc_i225.c
357
ctrl = IGC_READ_REG(hw, IGC_CTRL);
sys/dev/pci/igc/igc_i225.c
358
ctrl |= IGC_CTRL_SLU;
sys/dev/pci/igc/igc_i225.c
359
ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
sys/dev/pci/igc/igc_i225.c
360
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
sys/dev/pci/igc/igc_mac.c
514
uint32_t ctrl;
sys/dev/pci/igc/igc_mac.c
518
ctrl = IGC_READ_REG(hw, IGC_CTRL);
sys/dev/pci/igc/igc_mac.c
541
ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
sys/dev/pci/igc/igc_mac.c
544
ctrl &= (~IGC_CTRL_TFCE);
sys/dev/pci/igc/igc_mac.c
545
ctrl |= IGC_CTRL_RFCE;
sys/dev/pci/igc/igc_mac.c
548
ctrl &= (~IGC_CTRL_RFCE);
sys/dev/pci/igc/igc_mac.c
549
ctrl |= IGC_CTRL_TFCE;
sys/dev/pci/igc/igc_mac.c
552
ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
sys/dev/pci/igc/igc_mac.c
559
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
sys/dev/pci/igc/igc_mac.c
840
uint32_t ctrl;
sys/dev/pci/igc/igc_mac.c
845
ctrl = IGC_READ_REG(hw, IGC_CTRL);
sys/dev/pci/igc/igc_mac.c
846
ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
sys/dev/pci/igc/igc_mac.c
847
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
sys/dev/pci/igc/igc_phy.c
705
uint32_t ctrl, timeout = 10000, phpm = 0;
sys/dev/pci/igc/igc_phy.c
722
ctrl = IGC_READ_REG(hw, IGC_CTRL);
sys/dev/pci/igc/igc_phy.c
723
IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
sys/dev/pci/igc/igc_phy.c
728
IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe.c
2512
u32 ctrl;
sys/dev/pci/ixgbe/ixgbe.c
2527
ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me));
sys/dev/pci/ixgbe/ixgbe.c
2529
ctrl |= IXGBE_RXDCTL_VME;
sys/dev/pci/ixgbe/ixgbe.c
2531
ctrl &= ~IXGBE_RXDCTL_VME;
sys/dev/pci/ixgbe/ixgbe.c
2532
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl);
sys/dev/pci/ixgbe/ixgbe.c
2539
ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
sys/dev/pci/ixgbe/ixgbe.c
2541
ctrl |= IXGBE_VLNCTRL_VME;
sys/dev/pci/ixgbe/ixgbe.c
2543
ctrl &= ~IXGBE_VLNCTRL_VME;
sys/dev/pci/ixgbe/ixgbe.c
2544
IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe.c
2554
u32 ctrl;
sys/dev/pci/ixgbe/ixgbe.c
2588
ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
sys/dev/pci/ixgbe/ixgbe.c
2591
ctrl |= IXGBE_VLNCTRL_VFE;
sys/dev/pci/ixgbe/ixgbe.c
2593
ctrl &= ~IXGBE_VLNCTRL_VFE;
sys/dev/pci/ixgbe/ixgbe.c
2594
IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe_82598.c
820
u32 ctrl;
sys/dev/pci/ixgbe/ixgbe_82598.c
884
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
sys/dev/pci/ixgbe/ixgbe_82598.c
885
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe_82598.c
891
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_82598.c
892
if (!(ctrl & IXGBE_CTRL_RST))
sys/dev/pci/ixgbe/ixgbe_82598.c
895
if (ctrl & IXGBE_CTRL_RST) {
sys/dev/pci/ixgbe/ixgbe_82599.c
1052
u32 ctrl = 0;
sys/dev/pci/ixgbe/ixgbe_82599.c
1099
ctrl = IXGBE_CTRL_LNK_RST;
sys/dev/pci/ixgbe/ixgbe_82599.c
1103
ctrl = IXGBE_CTRL_RST;
sys/dev/pci/ixgbe/ixgbe_82599.c
1106
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_82599.c
1107
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe_82599.c
1113
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_82599.c
1114
if (!(ctrl & IXGBE_CTRL_RST_MASK))
sys/dev/pci/ixgbe/ixgbe_82599.c
1118
if (ctrl & IXGBE_CTRL_RST_MASK) {
sys/dev/pci/ixgbe/ixgbe_common.c
5109
s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
sys/dev/pci/ixgbe/ixgbe_common.c
5117
cmd = ctrl; /* just reading only need control number */
sys/dev/pci/ixgbe/ixgbe_common.h
175
s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
sys/dev/pci/ixgbe/ixgbe_phy.c
505
u16 ctrl = 0;
sys/dev/pci/ixgbe/ixgbe_phy.c
544
&ctrl);
sys/dev/pci/ixgbe/ixgbe_phy.c
548
if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
sys/dev/pci/ixgbe/ixgbe_phy.c
556
&ctrl);
sys/dev/pci/ixgbe/ixgbe_phy.c
560
if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
sys/dev/pci/ixgbe/ixgbe_phy.c
567
if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
sys/dev/pci/ixgbe/ixgbe_phy.c
862
u16 ctrl;
sys/dev/pci/ixgbe/ixgbe_phy.c
866
&ctrl);
sys/dev/pci/ixgbe/ixgbe_phy.c
867
ctrl &= ~PMAPMD_CTRL1_SPEED_MASK;
sys/dev/pci/ixgbe/ixgbe_phy.c
868
ctrl |= PMAPMD_CTRL1_SPEED_100;
sys/dev/pci/ixgbe/ixgbe_phy.c
870
ctrl);
sys/dev/pci/ixgbe/ixgbe_x540.c
221
u32 ctrl, i;
sys/dev/pci/ixgbe/ixgbe_x540.c
241
ctrl = IXGBE_CTRL_RST;
sys/dev/pci/ixgbe/ixgbe_x540.c
242
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_x540.c
243
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe_x540.c
250
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_x540.c
251
if (!(ctrl & IXGBE_CTRL_RST_MASK))
sys/dev/pci/ixgbe/ixgbe_x540.c
255
if (ctrl & IXGBE_CTRL_RST_MASK) {
sys/dev/pci/ixgbe/ixgbe_x550.c
1276
static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
sys/dev/pci/ixgbe/ixgbe_x550.c
1290
if (ctrl)
sys/dev/pci/ixgbe/ixgbe_x550.c
1291
*ctrl = command;
sys/dev/pci/ixgbe/ixgbe_x550.c
2610
u32 ctrl = 0;
sys/dev/pci/ixgbe/ixgbe_x550.c
2672
ctrl = IXGBE_CTRL_LNK_RST;
sys/dev/pci/ixgbe/ixgbe_x550.c
2676
ctrl = IXGBE_CTRL_RST;
sys/dev/pci/ixgbe/ixgbe_x550.c
2685
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_x550.c
2686
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
sys/dev/pci/ixgbe/ixgbe_x550.c
2693
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
sys/dev/pci/ixgbe/ixgbe_x550.c
2694
if (!(ctrl & IXGBE_CTRL_RST_MASK))
sys/dev/pci/ixgbe/ixgbe_x550.c
2698
if (ctrl & IXGBE_CTRL_RST_MASK) {
sys/dev/pci/ixgbe/ixv.c
2118
u32 ctrl;
sys/dev/pci/ixgbe/ixv.c
2129
ctrl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(rxr->me));
sys/dev/pci/ixgbe/ixv.c
2131
ctrl |= IXGBE_RXDCTL_VME;
sys/dev/pci/ixgbe/ixv.c
2133
ctrl &= ~IXGBE_RXDCTL_VME;
sys/dev/pci/ixgbe/ixv.c
2134
IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(rxr->me), ctrl);
sys/dev/pci/ubsec.c
2177
volatile u_int32_t ctrl;
sys/dev/pci/ubsec.c
2179
ctrl = READ_REG(sc, BS_CTRL);
sys/dev/pci/ubsec.c
2180
ctrl |= BS_CTRL_RESET;
sys/dev/pci/ubsec.c
2181
WRITE_REG(sc, BS_CTRL, ctrl);
sys/dev/pci/ubsec.c
2203
u_int32_t ctrl;
sys/dev/pci/ubsec.c
2205
ctrl = READ_REG(sc, BS_CTRL);
sys/dev/pci/ubsec.c
2206
ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
sys/dev/pci/ubsec.c
2207
ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
sys/dev/pci/ubsec.c
2214
ctrl |= BS_CTRL_MCR2INT;
sys/dev/pci/ubsec.c
2216
ctrl &= ~BS_CTRL_MCR2INT;
sys/dev/pci/ubsec.c
2219
ctrl &= ~BS_CTRL_SWNORM;
sys/dev/pci/ubsec.c
2222
ctrl |= BS_CTRL_BSIZE240;
sys/dev/pci/ubsec.c
2223
ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */
sys/dev/pci/ubsec.c
2226
ctrl |= BS_CTRL_MCR4INT;
sys/dev/pci/ubsec.c
2228
ctrl &= ~BS_CTRL_MCR4INT;
sys/dev/pci/ubsec.c
2231
WRITE_REG(sc, BS_CTRL, ctrl);
sys/dev/pci/ubsec.c
524
volatile u_int32_t ctrl;
sys/dev/pci/ubsec.c
528
ctrl = READ_REG(sc, BS_CTRL);
sys/dev/pci/ubsec.c
530
ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR);
sys/dev/pci/ubsec.c
532
ctrl &= ~BS_CTRL_MCR4INT;
sys/dev/pci/ubsec.c
534
WRITE_REG(sc, BS_CTRL, ctrl);
sys/dev/pci/voyager/voyagerfb.c
395
uint32_t ht, hs, vt, vs, ctrl;
sys/dev/pci/voyager/voyagerfb.c
411
ctrl = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PANEL_DISP_CTRL);
sys/dev/pci/voyager/voyagerfb.c
412
ctrl &= ~(SM502_PDC_HSYNC_PHASE_LOW | SM502_PDC_VSYNC_PHASE_LOW);
sys/dev/pci/voyager/voyagerfb.c
414
ctrl |= SM502_PDC_HSYNC_PHASE_LOW;
sys/dev/pci/voyager/voyagerfb.c
416
ctrl |= SM502_PDC_VSYNC_PHASE_LOW;
sys/dev/pci/voyager/voyagerfb.c
417
bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PANEL_DISP_CTRL, ctrl);
sys/dev/pci/voyager/voyagerfb.c
424
uint32_t ctrl = bus_space_read_4(sc->sc_memt, sc->sc_regh,
sys/dev/pci/voyager/voyagerfb.c
427
return (ctrl & SM502_PMCTL_MODE_MASK) ? SM502_POWER_MODE1_CLOCK :
sys/dev/pci/voyager/voyagerfb.c
536
uint32_t ctrl;
sys/dev/pci/voyager/voyagerfb.c
538
ctrl = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PANEL_DISP_CTRL);
sys/dev/pci/voyager/voyagerfb.c
540
ctrl & ~SM502_PDC_TIMING_ENABLE);
sys/dev/pci/voyager/voyagerfb.c
546
ctrl = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PANEL_DISP_CTRL);
sys/dev/pci/voyager/voyagerfb.c
548
ctrl | SM502_PDC_TIMING_ENABLE);
sys/dev/pci/yds.c
355
u_int ctrl;
sys/dev/pci/yds.c
381
ctrl = YREAD2(sc, YDS_GLOBAL_CONTROL);
sys/dev/pci/yds.c
382
YWRITE2(sc, YDS_GLOBAL_CONTROL, ctrl & ~0x0007);
sys/dev/pci/ydsreg.h
328
} ctrl[N_REC_SLOT_CTRL];
sys/dev/pcmcia/btbc.c
790
uint8_t id, ctrl;
sys/dev/pcmcia/btbc.c
812
ctrl = BLUECARD_CONTROL_RESET | BLUECARD_CONTROL_CARDRESET;
sys/dev/pcmcia/btbc.c
814
ctrl);
sys/dev/pcmcia/btbc.c
828
ctrl = BLUECARD_CONTROL_ON | BLUECARD_CONTROL_RESPU;
sys/dev/pcmcia/btbc.c
830
ctrl);
sys/dev/pcmcia/btbc.c
833
sc->sc_ctrlreg = ctrl;
sys/dev/pcmcia/btbc.c
853
ctrl |= BLUECARD_CONTROL_RTS;
sys/dev/pcmcia/btbc.c
855
BLUECARD_CONTROL, ctrl);
sys/dev/pcmcia/btbc.c
858
ctrl |= BLUECARD_CONTROL_BAUDRATE_460800;
sys/dev/pcmcia/btbc.c
860
BLUECARD_CONTROL, ctrl);
sys/dev/pcmcia/btbc.c
863
ctrl &= ~BLUECARD_CONTROL_RTS;
sys/dev/pcmcia/btbc.c
865
BLUECARD_CONTROL, ctrl);
sys/dev/raidframe/rf_reconstruct.c
1177
RF_PerDiskReconCtrl_t *ctrl = &raidPtr->reconControl->perDiskInfo[col];
sys/dev/raidframe/rf_reconstruct.c
1179
RF_ReconBuffer_t *rbuf = ctrl->rbuf;
sys/dev/raidframe/rf_reconstruct.c
1186
if (ctrl->headSepCounter <= raidPtr->reconControl->minHeadSepCounter)
sys/dev/raidframe/rf_reconstruct.c
1191
ctrl->ru_count++;
sys/dev/raidframe/rf_reconstruct.c
1192
if (ctrl->ru_count < RUsPerPU) {
sys/dev/raidframe/rf_reconstruct.c
1193
ctrl->diskOffset += sectorsPerRU;
sys/dev/raidframe/rf_reconstruct.c
1196
ctrl->curPSID++;
sys/dev/raidframe/rf_reconstruct.c
1197
ctrl->ru_count = 0;
sys/dev/raidframe/rf_reconstruct.c
1200
if (ctrl->curPSID > raidPtr->reconControl->lastPSID) {
sys/dev/raidframe/rf_reconstruct.c
1201
CheckForNewMinHeadSep(raidPtr, ++(ctrl->headSepCounter));
sys/dev/raidframe/rf_reconstruct.c
1208
status = ComputePSDiskOffsets(raidPtr, ctrl->curPSID, col, &ctrl->diskOffset, &rbuf->failedDiskSectorOffset,
sys/dev/raidframe/rf_reconstruct.c
1211
ctrl->ru_count = RUsPerPU - 1;
sys/dev/raidframe/rf_reconstruct.c
1215
rbuf->which_ru = ctrl->ru_count;
sys/dev/raidframe/rf_reconstruct.c
1219
Dprintf2("Skipping psid %ld ru %d: already reconstructed\n", ctrl->curPSID, ctrl->ru_count);
sys/dev/raidframe/rf_reconstruct.c
1224
ctrl->headSepCounter++;
sys/dev/raidframe/rf_reconstruct.c
1226
CheckForNewMinHeadSep(raidPtr, ctrl->headSepCounter); /* update min if needed */
sys/dev/raidframe/rf_reconstruct.c
1231
rbuf->parityStripeID = ctrl->curPSID;
sys/dev/raidframe/rf_reconstruct.c
1232
rbuf->which_ru = ctrl->ru_count;
sys/dev/raidframe/rf_reconstruct.c
1255
RF_PerDiskReconCtrl_t *ctrl = &raidPtr->reconControl->perDiskInfo[col];
sys/dev/raidframe/rf_reconstruct.c
1257
RF_StripeNum_t psid = ctrl->curPSID;
sys/dev/raidframe/rf_reconstruct.c
1258
RF_ReconUnitNum_t which_ru = ctrl->ru_count;
sys/dev/raidframe/rf_reconstruct.c
1265
if (CheckHeadSeparation(raidPtr, ctrl, col, ctrl->headSepCounter, which_ru))
sys/dev/raidframe/rf_reconstruct.c
1281
status = CheckForcedOrBlockedReconstruction(raidPtr, pssPtr, ctrl, col, psid, which_ru);
sys/dev/raidframe/rf_reconstruct.c
1297
if (rf_CheckRUReconstructed(raidPtr->reconControl->reconMap, ctrl->rbuf->failedDiskSectorOffset)) {
sys/dev/raidframe/rf_reconstruct.c
1306
psid, col, ctrl->diskOffset, ctrl->rbuf->buffer);
sys/dev/raidframe/rf_reconstruct.c
1316
req = rf_CreateDiskQueueData(RF_IO_TYPE_READ, ctrl->diskOffset, sectorsPerRU, ctrl->rbuf->buffer, psid, which_ru,
sys/dev/raidframe/rf_reconstruct.c
1317
ReconReadDoneProc, (void *) ctrl,
sys/dev/raidframe/rf_reconstruct.c
1325
ctrl->rbuf->arg = (void *) req;
sys/dev/raidframe/rf_reconstruct.c
1533
RF_PerDiskReconCtrl_t *ctrl = (RF_PerDiskReconCtrl_t *) arg;
sys/dev/raidframe/rf_reconstruct.c
1540
if (ctrl->reconCtrl == NULL)
sys/dev/raidframe/rf_reconstruct.c
1543
raidPtr = ctrl->reconCtrl->reconDesc->raidPtr;
sys/dev/raidframe/rf_reconstruct.c
1547
rf_CauseReconEvent(raidPtr, ctrl->col, NULL, RF_REVENT_READ_FAILED);
sys/dev/raidframe/rf_reconstruct.c
1551
RF_ETIMER_STOP(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
sys/dev/raidframe/rf_reconstruct.c
1552
RF_ETIMER_EVAL(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
sys/dev/raidframe/rf_reconstruct.c
1553
raidPtr->recon_tracerecs[ctrl->col].specific.recon.recon_fetch_to_return_us =
sys/dev/raidframe/rf_reconstruct.c
1554
RF_ETIMER_VAL_US(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
sys/dev/raidframe/rf_reconstruct.c
1555
RF_ETIMER_START(raidPtr->recon_tracerecs[ctrl->col].recon_timer);
sys/dev/raidframe/rf_reconstruct.c
1557
rf_CauseReconEvent(raidPtr, ctrl->col, NULL, RF_REVENT_READDONE);
sys/dev/raidframe/rf_reconstruct.c
1649
CheckHeadSeparation(RF_Raid_t *raidPtr, RF_PerDiskReconCtrl_t *ctrl,
sys/dev/raidframe/rf_reconstruct.c
1672
((ctrl->headSepCounter - reconCtrlPtr->minHeadSepCounter) > raidPtr->headSepLimit)) {
sys/dev/raidframe/rf_reconstruct.c
1674
raidPtr->raidid, col, ctrl->headSepCounter,
sys/dev/raidframe/rf_reconstruct.c
1680
cb->v = (ctrl->headSepCounter - raidPtr->headSepLimit + raidPtr->headSepLimit / 5);
sys/dev/raidframe/rf_reconstruct.c
1700
ctrl->reconCtrl->reconDesc->hsStallCount++;
sys/dev/raidframe/rf_reconstruct.c
1720
RF_PerDiskReconCtrl_t *ctrl,
sys/dev/sbus/bereg.h
210
uint32_t ctrl; /* control */
sys/dev/sbus/qereg.h
64
uint32_t ctrl; /* control */
sys/dev/spi/mcp3k.c
420
uint8_t buf[2], ctrl;
sys/dev/spi/mcp3k.c
429
ctrl = 1; /* start bit */
sys/dev/spi/mcp3k.c
433
ctrl <<= 1;
sys/dev/spi/mcp3k.c
434
ctrl |= edata->private >= model->channels;
sys/dev/spi/mcp3k.c
439
ctrl <<= 3;
sys/dev/spi/mcp3k.c
440
ctrl |= edata->private & (model->channels - 1);
sys/dev/spi/mcp3k.c
443
ctrl <<= 1;
sys/dev/spi/mcp3k.c
444
ctrl |= edata->private & 1;
sys/dev/spi/mcp3k.c
449
ctrl <<= 1;
sys/dev/spi/mcp3k.c
450
ctrl |= 1;
sys/dev/spi/mcp3k.c
454
if (spi_send_recv(sc->sc_sh, 1, &ctrl, 2, buf) != 0) {
sys/dev/usb/ehci.c
149
} ctrl;
sys/dev/usb/ehci.c
2092
&epipe->ctrl.reqdma);
sys/dev/usb/ehci.c
3653
const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
sys/dev/usb/ehci.c
3755
memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req));
sys/dev/usb/ehci.c
3756
usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
sys/dev/usb/ehci.c
3772
const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
sys/dev/usb/ehci.c
3886
usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req),
sys/dev/usb/ehci.c
3920
usb_freemem(&epipe->ctrl.reqdma);
sys/dev/usb/if_axen.c
427
qctrl.ctrl = 0x07;
sys/dev/usb/if_axen.c
435
qctrl.ctrl = 0x07;
sys/dev/usb/if_axen.c
443
qctrl.ctrl = 0x07;
sys/dev/usb/if_axenreg.h
225
uint8_t ctrl;
sys/dev/usb/motg.c
716
uint8_t ctrl)
sys/dev/usb/motg.c
721
sc->sc_intr_ctrl = ctrl;
sys/dev/usb/ohci.c
1705
usb_syncmem(&opipe->ctrl.reqdma, 0,
sys/dev/usb/ohci.c
2164
USBMALLOC_COHERENT, &opipe->ctrl.reqdma);
sys/dev/usb/ohci.c
271
} ctrl;
sys/dev/usb/ohci.c
2884
memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
sys/dev/usb/ohci.c
2885
usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
sys/dev/usb/ohci.c
2893
setup->td->td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
sys/dev/usb/ohci.c
2982
usb_freemem(&opipe->ctrl.reqdma);
sys/dev/usb/uhci.c
146
} ctrl;
sys/dev/usb/uhci.c
1574
uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
sys/dev/usb/uhci.c
1575
uhci_soft_td_t *stat = upipe->ctrl.stat;
sys/dev/usb/uhci.c
2441
uxfer->ux_setup = upipe->ctrl.setup;
sys/dev/usb/uhci.c
2442
uxfer->ux_stat = upipe->ctrl.stat;
sys/dev/usb/uhci.c
2504
setup = upipe->ctrl.setup;
sys/dev/usb/uhci.c
2505
stat = upipe->ctrl.stat;
sys/dev/usb/uhci.c
2506
sqh = upipe->ctrl.sqh;
sys/dev/usb/uhci.c
2508
memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
sys/dev/usb/uhci.c
2509
usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
sys/dev/usb/uhci.c
2536
setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
sys/dev/usb/uhci.c
2758
uhci_free_sqh(sc, upipe->ctrl.sqh);
sys/dev/usb/uhci.c
2759
uhci_free_std_locked(sc, upipe->ctrl.setup);
sys/dev/usb/uhci.c
2760
uhci_free_std_locked(sc, upipe->ctrl.stat);
sys/dev/usb/uhci.c
2762
usb_freemem(&upipe->ctrl.reqdma);
sys/dev/usb/uhci.c
3216
uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
sys/dev/usb/uhci.c
3218
uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
sys/dev/usb/uhci.c
3224
usb_syncmem(&upipe->ctrl.reqdma, 0,
sys/dev/usb/uhci.c
3417
upipe->ctrl.sqh = uhci_alloc_sqh(sc);
sys/dev/usb/uhci.c
3418
if (upipe->ctrl.sqh == NULL)
sys/dev/usb/uhci.c
3420
upipe->ctrl.setup = uhci_alloc_std(sc);
sys/dev/usb/uhci.c
3421
if (upipe->ctrl.setup == NULL) {
sys/dev/usb/uhci.c
3422
uhci_free_sqh(sc, upipe->ctrl.sqh);
sys/dev/usb/uhci.c
3425
upipe->ctrl.stat = uhci_alloc_std(sc);
sys/dev/usb/uhci.c
3426
if (upipe->ctrl.stat == NULL) {
sys/dev/usb/uhci.c
3427
uhci_free_sqh(sc, upipe->ctrl.sqh);
sys/dev/usb/uhci.c
3428
uhci_free_std(sc, upipe->ctrl.setup);
sys/dev/usb/uhci.c
3433
USBMALLOC_COHERENT, &upipe->ctrl.reqdma);
sys/dev/usb/uhci.c
3435
uhci_free_sqh(sc, upipe->ctrl.sqh);
sys/dev/usb/uhci.c
3436
uhci_free_std(sc, upipe->ctrl.setup);
sys/dev/usb/uhci.c
3437
uhci_free_std(sc, upipe->ctrl.stat);
sys/dev/usb/vhci.c
300
memcpy(&vxfer->reqbuf.u.ctrl, &xfer->ux_request,
sys/dev/usb/vhci.h
37
usb_device_request_t ctrl;
sys/dev/vme/xd.c
1388
struct xd_iopb_ctrl *ctrl =
sys/dev/vme/xd.c
1394
ctrl->param_a = XDPA_TMOD | XDPA_DACF;
sys/dev/vme/xd.c
1395
ctrl->param_b = XDPB_ROR | XDPB_TDT_3_2USEC;
sys/dev/vme/xd.c
1396
ctrl->param_c = XDPC_OVS | XDPC_COP | XDPC_ASR |
sys/dev/vme/xd.c
1398
ctrl->throttle = XDC_THROTTLE;
sys/dev/vme/xd.c
1399
ctrl->delay = XDC_DELAY;
sys/net/bsd-comp.c
807
int adrs, ctrl, ilen;
sys/net/bsd-comp.c
817
ctrl = PPP_CONTROL(rptr);
sys/net/bsd-comp.c
864
wptr[1] = ctrl;
sys/net/if_ppp.c
1448
u_char *cp, adrs, ctrl;
sys/net/if_ppp.c
1468
ctrl = PPP_CONTROL(cp);
sys/net/if_ppp.c
1581
cp[1] = ctrl;
sys/net/lagg/if_lagg.c
1484
enum lagg_portctrl ctrl)
sys/net/lagg/if_lagg.c
1502
switch (ctrl) {
sys/sys/videoio.h
3223
struct v4l2_event_ctrl ctrl;
usr.bin/aiomixer/main.c
215
struct mixer_ctrl ctrl;
usr.bin/aiomixer/main.c
219
ctrl.dev = control->info.index;
usr.bin/aiomixer/main.c
220
ctrl.type = control->info.type;
usr.bin/aiomixer/main.c
225
if (ioctl(aio->fd, AUDIO_MIXER_READ, &ctrl) < 0)
usr.bin/aiomixer/main.c
228
ctrl.un.mask ^= control->info.un.s.member[control->setindex].mask;
usr.bin/aiomixer/main.c
230
if (ioctl(aio->fd, AUDIO_MIXER_WRITE, &ctrl) < 0)
usr.bin/tip/cmds.c
446
(void)printf("\r\ntimeout error (%s)\r\n", ctrl(c));
usr.bin/tip/tip.c
474
(void)printf("%s", ctrl(c));
usr.bin/tip/tip.c
548
(void)printf("%2s", ctrl(character(value(ESCAPE))));
usr.bin/tip/tip.c
549
(void)printf("%-2s %c %s\r\n", ctrl(p->e_char),
usr.bin/tip/tip.h
267
char *ctrl(char);
usr.bin/tip/value.c
236
cp = ctrl(character(p->v_value));
usr.bin/videoctl/videoctl.c
567
struct v4l2_control ctrl;
usr.bin/videoctl/videoctl.c
572
for (ctrl.id = V4L2_CID_BASE; ctrl.id != V4L2_CID_LASTP1; ctrl.id++) {
usr.bin/videoctl/videoctl.c
573
if (ctrl_id != 0 && ctrl_id != ctrl.id)
usr.bin/videoctl/videoctl.c
575
error = ioctl(video_fd, VIDIOC_G_CTRL, &ctrl);
usr.bin/videoctl/videoctl.c
578
ctrlname = video_cid2name(ctrl.id);
usr.bin/videoctl/videoctl.c
580
printf("ctrl.%s=%d\n", ctrlname, ctrl.value);
usr.bin/videoctl/videoctl.c
582
printf("ctrl.%08x=%d\n", ctrl.id, ctrl.value);
usr.bin/videoctl/videoctl.c
636
struct v4l2_control ctrl;
usr.bin/videoctl/videoctl.c
643
ctrl.id = ctrl_id;
usr.bin/videoctl/videoctl.c
644
error = ioctl(video_fd, VIDIOC_G_CTRL, &ctrl);
usr.bin/videoctl/videoctl.c
647
ovalue = ctrl.value;
usr.bin/videoctl/videoctl.c
648
ctrl.value = value;
usr.bin/videoctl/videoctl.c
649
error = ioctl(video_fd, VIDIOC_S_CTRL, &ctrl);
usr.bin/videoctl/videoctl.c
652
error = ioctl(video_fd, VIDIOC_G_CTRL, &ctrl);
usr.bin/videoctl/videoctl.c
657
printf("ctrl.%s: %d -> %d\n", ctrlname, ovalue, ctrl.value);
usr.bin/videoctl/videoctl.c
659
printf("ctrl.%08x: %d -> %d\n", ctrl.id, ovalue, ctrl.value);
usr.sbin/inetd/inetd.c
1556
tcpmux(int ctrl, struct servtab *sep)
usr.sbin/inetd/inetd.c
1562
if ((len = get_line(ctrl, service, MAX_SERV_LEN)) < 0) {
usr.sbin/inetd/inetd.c
1563
strwrite(ctrl, "-Error reading service name\r\n");
usr.sbin/inetd/inetd.c
1575
strwrite(ctrl, "+Available services:\r\n");
usr.sbin/inetd/inetd.c
1576
strwrite(ctrl, "help\r\n");
usr.sbin/inetd/inetd.c
1580
(void)write(ctrl, sep->se_service,
usr.sbin/inetd/inetd.c
1582
strwrite(ctrl, "\r\n");
usr.sbin/inetd/inetd.c
1593
strwrite(ctrl, "+Go\r\n");
usr.sbin/inetd/inetd.c
1594
run_service(ctrl, sep, true /* forked */);
usr.sbin/inetd/inetd.c
1598
strwrite(ctrl, "-Service not available\r\n");
usr.sbin/inetd/inetd.c
414
int ctrl;
usr.sbin/inetd/inetd.c
454
ctrl = accept(sep->se_fd, NULL, NULL);
usr.sbin/inetd/inetd.c
456
SERV_PARAMS(sep), ctrl);
usr.sbin/inetd/inetd.c
457
if (ctrl < 0) {
usr.sbin/inetd/inetd.c
469
ctrl = sep->se_fd;
usr.sbin/inetd/inetd.c
470
spawn(sep, ctrl);
usr.sbin/inetd/inetd.c
476
spawn(struct servtab *sep, int ctrl)
usr.sbin/inetd/inetd.c
488
if (rl_process(sep, ctrl)) {
usr.sbin/inetd/inetd.c
499
close(ctrl);
usr.sbin/inetd/inetd.c
525
run_service(ctrl, sep, dofork);
usr.sbin/inetd/inetd.c
530
close(ctrl);
usr.sbin/inetd/inetd.c
534
run_service(int ctrl, struct servtab *sep, int didfork)
usr.sbin/inetd/inetd.c
553
sep->se_argv[0] : sep->se_service, RQ_FILE, ctrl, NULL);
usr.sbin/inetd/inetd.c
589
if (s->se_fd != -1 && s->se_fd != ctrl) {
usr.sbin/inetd/inetd.c
594
(*sep->se_bi->bi_fn)(ctrl, sep);
usr.sbin/inetd/inetd.c
630
if (fcntl(ctrl, F_SETFD, 0) < 0)
usr.sbin/inetd/inetd.c
631
syslog(LOG_ERR, "fcntl (%d, F_SETFD, 0): %m", ctrl);
usr.sbin/inetd/inetd.c
633
if (ctrl != 0) {
usr.sbin/inetd/inetd.c
634
dup2(ctrl, 0);
usr.sbin/inetd/inetd.c
635
close(ctrl);
usr.sbin/inetd/inetd.c
636
ctrl = 0;
usr.sbin/inetd/inetd.c
647
recv(ctrl, buf, sizeof (buf), 0);
usr.sbin/inetd/ratelimit.c
110
rl_get_name(struct servtab *sep, int ctrl, union addr *out)
usr.sbin/inetd/ratelimit.c
123
if (getpeername(ctrl, &addr.sa, &len) == -1) {
usr.sbin/inetd/ratelimit.c
141
count = recvmsg(ctrl, &header, MSG_PEEK);
usr.sbin/inetd/ratelimit.c
189
rl_drop_connection(struct servtab *sep, int ctrl)
usr.sbin/inetd/ratelimit.c
197
close(ctrl);
usr.sbin/inetd/ratelimit.c
214
count = recvmsg(ctrl, &header, 0);
usr.sbin/inetd/ratelimit.c
350
rl_process_service_max(struct servtab *sep, int ctrl, time_t *now)
usr.sbin/inetd/ratelimit.c
376
rl_drop_connection(sep, ctrl);
usr.sbin/inetd/ratelimit.c
393
rl_process_ip_max(struct servtab *sep, int ctrl, time_t *now) {
usr.sbin/inetd/ratelimit.c
398
rl_get_name(sep, ctrl, &addr);
usr.sbin/inetd/ratelimit.c
448
rl_drop_connection(sep, ctrl);
usr.sbin/inetd/ratelimit.c
78
rl_process(struct servtab *sep, int ctrl)
usr.sbin/inetd/ratelimit.c
93
if (!rl_process_service_max(sep, ctrl, &now)
usr.sbin/inetd/ratelimit.c
94
|| !rl_process_ip_max(sep, ctrl, &now)) {