____cacheline_aligned
unsigned long bits ____cacheline_aligned;
} ____cacheline_aligned;
unsigned long bits ____cacheline_aligned;
unsigned long stats[IPI_MAX] ____cacheline_aligned;
} ____cacheline_aligned irq_cpustat_t;
} ____cacheline_aligned irq_cpustat_t;
} ____cacheline_aligned irq_cpustat_t;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
unsigned long normsave[8] ____cacheline_aligned;
static struct ibm_arch_vec __prombss ibm_architecture_vec ____cacheline_aligned;
static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
struct napi_struct napi ____cacheline_aligned;
} ____cacheline_aligned irq_cpustat_t;
} ____cacheline_aligned;
} ____cacheline_aligned irq_cpustat_t;
struct estack_pages estack_pages[CEA_ESTACK_PAGES] ____cacheline_aligned = {
const sys_call_ptr_t sys_call_table[] ____cacheline_aligned = {
const sys_call_ptr_t sys_call_table[] ____cacheline_aligned = {
static const u32 ____cacheline_aligned fk[4] = {
static const u32 ____cacheline_aligned ck[32] = {
static const u8 ____cacheline_aligned sbox[256] = {
} ____cacheline_aligned;
atomic_t tfm_count ____cacheline_aligned;
__u8 decryption_tag[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 key[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
u8 buf[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
u8 key[CAAM_MAX_HASH_KEY_SIZE] ____cacheline_aligned;
dma_addr_t sh_desc_update_dma ____cacheline_aligned;
u8 buf[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
int (*update)(struct ahash_request *req) ____cacheline_aligned;
u32 hw_desc[DESC_JOB_IO_LEN_MAX / sizeof(u32)] ____cacheline_aligned;
u32 sh_desc_update[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
atomic_t tfm_count ____cacheline_aligned;
spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
} ____cacheline_aligned;
} ____cacheline_aligned;
static struct caam_qi_priv qipriv ____cacheline_aligned;
struct mutex q_mutex ____cacheline_aligned;
} ____cacheline_aligned;
struct mutex req_mutex ____cacheline_aligned;
spinlock_t cmd_lock ____cacheline_aligned;
atomic_t current_id ____cacheline_aligned;
struct mutex sb_mutex ____cacheline_aligned;
u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
unsigned int hw_iv_size ____cacheline_aligned;
u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
u8 opad_tmp_keys_buff[CC_MAX_OPAD_KEYS_SIZE] ____cacheline_aligned;
dma_addr_t opad_tmp_keys_dma_addr ____cacheline_aligned;
u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
struct async_gen_req_ctx gen_ctx ____cacheline_aligned;
spinlock_t tail_lock ____cacheline_aligned;
spinlock_t reg_lock ____cacheline_aligned;
atomic_t last_chan ____cacheline_aligned;
atomic_t submit_count ____cacheline_aligned;
spinlock_t head_lock ____cacheline_aligned;
spinlock_t q_lock ____cacheline_aligned;
} ____cacheline_aligned;
spinlock_t cmd_lock ____cacheline_aligned;
struct list_head desc_node ____cacheline_aligned;
u8 xfer_buf[SZ_2K] ____cacheline_aligned;
u8 buf[2] ____cacheline_aligned;
u8 data[] ____cacheline_aligned; /* variable length payload here */
u16 rx ____cacheline_aligned;
u8 write_buf[ADM1266_PMBUS_BLOCK_MAX + 1] ____cacheline_aligned;
u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1] ____cacheline_aligned;
struct virtio_i2c_out_hdr out_hdr ____cacheline_aligned;
uint8_t *buf ____cacheline_aligned;
struct virtio_i2c_in_hdr in_hdr ____cacheline_aligned;
} ____cacheline_aligned;
spinlock_t flush_q_lock ____cacheline_aligned;
spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
spinlock_t comp_handler_lock ____cacheline_aligned;
spinlock_t q_lock ____cacheline_aligned;
spinlock_t q_lock ____cacheline_aligned;
u8 data_in[IFORCE_MAX_LENGTH] ____cacheline_aligned;
u8 data_out[IFORCE_MAX_LENGTH] ____cacheline_aligned;
static const u64 polldata[] ____cacheline_aligned = {
static const u64 __initconst scandata[] ____cacheline_aligned = {
u64 si_buf[8] ____cacheline_aligned;
u8 sendbuf[0x20] ____cacheline_aligned;
u8 response[sizeof(PSX_CMD_POLL)] ____cacheline_aligned;
__be16 xfer_buf[16] ____cacheline_aligned;
u8 xfer_buf[8] ____cacheline_aligned;
u16 sample ____cacheline_aligned;
u16 conversion_data[AD7877_NR_SENSE] ____cacheline_aligned;
__be16 sample ____cacheline_aligned;
u8 sample[3] ____cacheline_aligned;
u8 xfer_buf[] ____cacheline_aligned;
u8 buf[MAX_PACKET_SIZE] ____cacheline_aligned;
u8 rd_buf[SURFACE3_PACKET_SIZE] ____cacheline_aligned;
struct dbdma_cmd cmd[4] ____cacheline_aligned;
u32 mark ____cacheline_aligned;
u32 buf1[SAMPLE_COUNT] ____cacheline_aligned;
u32 buf2[SAMPLE_COUNT] ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
wait_queue_head_t waiting_worker_threads ____cacheline_aligned;
char tx_buf[MEI_VSC_MAX_MSG_SIZE + sizeof(struct mei_msg_hdr)] ____cacheline_aligned;
char rx_buf[MEI_VSC_MAX_MSG_SIZE + sizeof(struct mei_msg_hdr)] ____cacheline_aligned;
char data ____cacheline_aligned; /* CL 2 */
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
#define __3xp_aligned ____cacheline_aligned
struct transmit_ring txLoRing ____cacheline_aligned;
void __iomem *ioaddr ____cacheline_aligned;
spinlock_t command_lock ____cacheline_aligned;
u8 data[ADIN1110_MAX_BUFF] ____cacheline_aligned;
u32 msix_vector ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
u8 first_interrupt ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
struct ag71xx_ring rx_ring ____cacheline_aligned;
struct ag71xx_ring tx_ring ____cacheline_aligned;
struct napi_struct napi ____cacheline_aligned;
struct napi_struct napi ____cacheline_aligned;
struct napi_struct napi ____cacheline_aligned;
u32 consmbox ____cacheline_aligned;
u32 tx_prod ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
struct bnad_rx_unmap unmap[] ____cacheline_aligned;
struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned;
struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned;
spinlock_t bna_lock ____cacheline_aligned;
spinlock_t async_lock ____cacheline_aligned;
} ____cacheline_aligned;
spinlock_t stid_lock ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
u32 q_num ____cacheline_aligned; /* queue idx */
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
struct ibmvnic_sub_crq_queue **tx_scrq ____cacheline_aligned;
struct ibmvnic_sub_crq_queue **rx_scrq ____cacheline_aligned;
u32 msg_enable ____cacheline_aligned;
struct rx *rxs ____cacheline_aligned;
spinlock_t cb_lock ____cacheline_aligned;
} flags ____cacheline_aligned;
union ks8851_tx_hdr txh ____cacheline_aligned;
u32 msg_enable ____cacheline_aligned;
int req ____cacheline_aligned; /* transmit slots submitted */
int done ____cacheline_aligned; /* transmit slots completed */
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
struct qed_chain rx_comp_ring ____cacheline_aligned;
unsigned rx_head ____cacheline_aligned;
unsigned tx_head ____cacheline_aligned;
unsigned int __pad[] ____cacheline_aligned;
unsigned int __pad[] ____cacheline_aligned;
unsigned int __pad[] ____cacheline_aligned;
unsigned long tx_underflow ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
u32 msg_enable ____cacheline_aligned;
u8 cmd_buf[4] ____cacheline_aligned;
u8 cmd_buf[3] ____cacheline_aligned;
u8 buf[3] ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} *io_dmabuf ____cacheline_aligned;
u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
} ____cacheline_aligned;
struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;
____cacheline_aligned struct fnic_io_req **io_req_table;
____cacheline_aligned struct vnic_wq_copy hw_copy_wq[FNIC_WQ_COPY_MAX];
____cacheline_aligned struct fnic_cpy_wq sw_copy_wq[FNIC_WQ_COPY_MAX];
____cacheline_aligned struct vnic_cq cq[FNIC_CQ_MAX];
____cacheline_aligned struct vnic_wq wq[FNIC_WQ_MAX];
____cacheline_aligned struct vnic_rq rq[FNIC_RQ_MAX];
____cacheline_aligned struct vnic_intr intr[FNIC_MSIX_INTR_MAX];
struct qla_fw_resources fwres ____cacheline_aligned;
spinlock_t atio_lock ____cacheline_aligned;
spinlock_t hardware_lock ____cacheline_aligned;
struct qla_fw_res fwres ____cacheline_aligned;
spinlock_t hardware_lock ____cacheline_aligned;
____cacheline_aligned spinlock_t io_req_lock[SNIC_IO_LOCKS];
____cacheline_aligned spinlock_t spl_cmd_lock;
____cacheline_aligned struct vnic_cq cq[SNIC_CQ_MAX];
____cacheline_aligned struct vnic_wq wq[SNIC_WQ_MAX];
____cacheline_aligned struct vnic_intr intr[SNIC_MSIX_INTR_MAX];
struct snic_trc trc ____cacheline_aligned;
} ____cacheline_aligned;
static struct bm_buffer bufs_in[NUM_BUFS] ____cacheline_aligned;
static struct bm_buffer bufs_out[NUM_BUFS] ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
u32 clear_rx_cs ____cacheline_aligned;
struct spi_transfer_head transfer_head ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
spinlock_t ____cacheline_aligned m_sb_lock; /* sb counter lock */
} ____cacheline_aligned irq_cpustat_t;
struct bpf_local_storage_data sdata ____cacheline_aligned;
#define ____cacheline_aligned_in_smp ____cacheline_aligned
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
# define __hrtimer_clock_base_align ____cacheline_aligned
} ____cacheline_aligned;
} ____cacheline_aligned;
u8 gp_log_dir[ATA_SECT_SIZE] ____cacheline_aligned;
u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
#define __module_memory_align ____cacheline_aligned
} ____cacheline_aligned __randomize_layout;
u8 priv[] ____cacheline_aligned
} ____cacheline_aligned;
struct ebt_counter counters[] ____cacheline_aligned;
spinlock_t ____cacheline_aligned lock;
} ____cacheline_aligned;
unsigned long private[] ____cacheline_aligned;
____cacheline_aligned
____cacheline_aligned
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
__cacheline_group_begin(tcp_sock_write_tx) ____cacheline_aligned;
} ____cacheline_aligned;
const struct nft_object_ops *ops ____cacheline_aligned;
struct list_head hook_list ____cacheline_aligned;
const struct nft_set_ops *ops ____cacheline_aligned;
struct hlist_head ht[RAW_HTABLE_SIZE] ____cacheline_aligned;
__cacheline_group_begin(Qdisc_read_mostly) ____cacheline_aligned;
__cacheline_group_begin(Qdisc_write) ____cacheline_aligned;
long privdata[] ____cacheline_aligned;
} ____cacheline_aligned; /* perf critical, avoid false-sharing */
struct smp_rps_resp rps_resp ____cacheline_aligned; /* report_phy_sata_resp */
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
} ____cacheline_aligned;
#ifndef ____cacheline_aligned
} ____cacheline_aligned;
} nohz ____cacheline_aligned;
u64 nr_switches ____cacheline_aligned;
struct uclamp_rq uclamp[UCLAMP_CNT] ____cacheline_aligned;
u64 clock_task ____cacheline_aligned;
atomic_long_t load_avg ____cacheline_aligned;
raw_spinlock_t lock ____cacheline_aligned;
static struct clock_data cd ____cacheline_aligned = {
static struct tk_fast tk_fast_mono ____cacheline_aligned = {
static struct tk_fast tk_fast_raw ____cacheline_aligned = {
} ____cacheline_aligned;
} ____cacheline_aligned;
unsigned int flags ____cacheline_aligned; /* WQ: WQ_* flags */
} crc32_lsb_0x82f63b78_consts ____cacheline_aligned __maybe_unused = {
} crc64_msb_0x42f0e1eba9ea3693_consts ____cacheline_aligned __maybe_unused = {
} crc64_lsb_0x9a6c9329ac4bc9b5_consts ____cacheline_aligned __maybe_unused = {
} crc16_msb_0x8bb7_consts ____cacheline_aligned __maybe_unused = {
} crc32_lsb_0xedb88320_consts ____cacheline_aligned __maybe_unused = {
const u32 ____cacheline_aligned aes_dec_tab[256] = {
static const u8 ____cacheline_aligned aes_sbox[] = {
static const u8 ____cacheline_aligned aes_inv_sbox[] = {
const u32 ____cacheline_aligned aes_enc_tab[256] = {
static const u32 ____cacheline_aligned K[64] = {
} ____cacheline_aligned;
} ____cacheline_aligned;
const struct header_ops eth_header_ops ____cacheline_aligned = {
u32 history[ROLLOVER_HLEN] ____cacheline_aligned;
____cacheline_aligned;
} ____cacheline_aligned;
atomic64_t seqno ____cacheline_aligned;
refcount_t refcnt ____cacheline_aligned;
} ____cacheline_aligned;
atomic64_t sndnxt ____cacheline_aligned;
} ____cacheline_aligned;