arch/arc/kernel/troubleshoot.c

194

#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : ""

arch/arm/mach-omap2/id.c

271

if (((status & OMAP3_ ##feat## _MASK) \

arch/arm/mach-pxa/mfp-pxa2xx.c

293

gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \

arch/arm64/include/asm/image.h

26

(((flags) >> field##_SHIFT) & field##_MASK)

arch/arm64/include/asm/kvm_host.h

1559

FIELD_GET(id##_##fld##_MASK, __val); \

arch/arm64/include/asm/sysreg.h

1255

FIELD_GET(reg##_##field##_MASK, val)

arch/arm64/include/asm/sysreg.h

1258

FIELD_PREP(reg##_##field##_MASK, val)

arch/arm64/include/asm/sysreg.h

1261

FIELD_PREP(reg##_##field##_MASK, \

arch/arm64/include/uapi/asm/kvm.h

245

KVM_REG_ARM64_SYSREG_ ## n ## _MASK)

arch/arm64/kvm/sys_regs.h

262

u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \

arch/arm64/kvm/sys_regs.h

263

(val) &= ~reg##_##field##_MASK; \

arch/arm64/kvm/sys_regs.h

264

(val) |= FIELD_PREP(reg##_##field##_MASK, \

arch/arm64/kvm/vgic/vgic-mmio-v3.c

1050

((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \

arch/arm64/kvm/vgic/vgic.h

34

((((reg) & VGIC_AFFINITY_## level ##_MASK) \

arch/m68k/include/asm/MC68328.h

21

#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)

arch/m68k/include/asm/MC68328.h

22

#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)

arch/m68k/include/asm/MC68EZ328.h

22

#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)

arch/m68k/include/asm/MC68EZ328.h

23

#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)

arch/m68k/include/asm/MC68VZ328.h

24

#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)

arch/m68k/include/asm/MC68VZ328.h

25

#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)

arch/mips/include/asm/mach-loongson2ef/loongson.h

315

s##_WIN##w##_MASK = ~(size-1); \

arch/mips/include/asm/mips-boards/bonito64.h

410

#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)

arch/mips/include/asm/mips-boards/bonito64.h

413

#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)

arch/mips/include/asm/mips-boards/bonito64.h

416

#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)

arch/riscv/include/asm/image.h

34

(((flags) >> field##_SHIFT) & field##_MASK)

arch/xtensa/include/asm/processor.h

75

#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)

drivers/accel/habanalabs/common/habanalabs.h

2650

#define REG_FIELD_MASK(reg, field) reg##_##field##_MASK

drivers/accel/ivpu/ivpu_hw_reg_io.h

33

(REG##_##FLD##_MASK)

drivers/accel/ivpu/ivpu_hw_reg_io.h

35

FIELD_PREP(REG##_##FLD##_MASK, num)

drivers/accel/ivpu/ivpu_hw_reg_io.h

37

FIELD_GET(REG##_##FLD##_MASK, val)

drivers/accel/ivpu/ivpu_hw_reg_io.h

39

((val) & ~(REG##_##FLD##_MASK))

drivers/accel/ivpu/ivpu_hw_reg_io.h

41

((val) | (REG##_##FLD##_MASK))

drivers/accel/ivpu/ivpu_hw_reg_io.h

43

(((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))

drivers/accel/ivpu/ivpu_hw_reg_io.h

45

((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))

drivers/accel/ivpu/ivpu_hw_reg_io.h

47

((num) == FIELD_GET(REG##_##FLD##_MASK, val))

drivers/accel/ivpu/ivpu_hw_reg_io.h

50

ivpu_hw_reg_poll_fld(vdev, vdev->regb, reg, reg##_##fld##_MASK, \

drivers/accel/ivpu/ivpu_hw_reg_io.h

51

FIELD_PREP(reg##_##fld##_MASK, exp_fld_val), timeout_us, \

drivers/accel/ivpu/ivpu_hw_reg_io.h

55

ivpu_hw_reg_poll_fld(vdev, vdev->regv, reg, reg##_##fld##_MASK, \

drivers/accel/ivpu/ivpu_hw_reg_io.h

56

FIELD_PREP(reg##_##fld##_MASK, exp_fld_val), timeout_us, \

drivers/block/drbd/drbd_state.h

38

({ union drbd_state mask; mask.i = 0; mask.T = T##_MASK; mask; }), \

drivers/block/drbd/drbd_state.h

41

({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \

drivers/block/drbd/drbd_state.h

42

mask.T2 = T2##_MASK; mask; }), \

drivers/block/drbd/drbd_state.h

46

({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \

drivers/block/drbd/drbd_state.h

47

mask.T2 = T2##_MASK; mask.T3 = T3##_MASK; mask; }), \

drivers/clk/clk-nspire.c

40

#define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c

14

PM_INFO_REGSET_ENTRY_MASK(_reg_, _field_, ADF_GEN4_PM_##_field_##_MASK)

drivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c

14

PM_INFO_REGSET_ENTRY_MASK(_reg_, _field_, ADF_GEN6_PM_##_field_##_MASK)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1371

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1372

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1425

#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

130

(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

132

(((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK)

drivers/gpu/drm/amd/amdgpu/soc15.h

103

#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

62

CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

51

CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

53

CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

66

CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

70

CLK_MASK_SH_LIST_NV10(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

72

CLK_COMMON_MASK_SH_LIST_DCN201_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

76

CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

111

CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

127

CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

119

CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

150

CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

69

CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/dm_services.h

116

reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

135

reg_field ## _MASK

drivers/gpu/drm/amd/display/dc/dm_services.h

168

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

175

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

99

reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

109

DDC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

73

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

126

DDC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

90

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

113

DDC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

77

HPD_MASK_SH_LIST_DCE6(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

113

DDC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

77

HPD_MASK_SH_LIST_DCE8(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

122

DDC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

147

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

148

GENERIC_MASK_SH_LIST(_MASK, B),

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

86

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

146

DDC_MASK_SH_LIST_DCN2(_MASK, 1),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

147

DDC_MASK_SH_LIST_DCN2(_MASK, 2),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

148

DDC_MASK_SH_LIST_DCN2(_MASK, 3),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

149

DDC_MASK_SH_LIST_DCN2(_MASK, 4),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

150

DDC_MASK_SH_LIST_DCN2(_MASK, 5),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

151

DDC_MASK_SH_LIST_DCN2(_MASK, 6),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

152

DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

177

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

178

GENERIC_MASK_SH_LIST(_MASK, B),

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

96

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

128

DDC_MASK_SH_LIST_DCN2(_MASK, 1),

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

129

DDC_MASK_SH_LIST_DCN2(_MASK, 2),

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

130

DDC_MASK_SH_LIST_DCN2(_MASK, 3),

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

131

DDC_MASK_SH_LIST_DCN2(_MASK, 4),

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

132

DDC_MASK_SH_LIST_DCN2(_MASK, 5),

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

133

DDC_MASK_SH_LIST_DCN2(_MASK, 6)

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

156

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

93

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

103

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

153

DDC_MASK_SH_LIST_DCN2(_MASK, 1),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

154

DDC_MASK_SH_LIST_DCN2(_MASK, 2),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

155

DDC_MASK_SH_LIST_DCN2(_MASK, 3),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

156

DDC_MASK_SH_LIST_DCN2(_MASK, 4),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

157

DDC_MASK_SH_LIST_DCN2(_MASK, 5),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

158

DDC_MASK_SH_LIST_DCN2(_MASK, 6),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

159

DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

184

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

185

GENERIC_MASK_SH_LIST(_MASK, B),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

146

DDC_MASK_SH_LIST_DCN2(_MASK, 1),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

147

DDC_MASK_SH_LIST_DCN2(_MASK, 2),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

148

DDC_MASK_SH_LIST_DCN2(_MASK, 3),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

149

DDC_MASK_SH_LIST_DCN2(_MASK, 4),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

150

DDC_MASK_SH_LIST_DCN2(_MASK, 5),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

151

DDC_MASK_SH_LIST_DCN2(_MASK, 6)

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

176

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

177

GENERIC_MASK_SH_LIST(_MASK, B),

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

99

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

157

DDC_MASK_SH_LIST_DCN2(_MASK, 1),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

158

DDC_MASK_SH_LIST_DCN2(_MASK, 2),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

159

DDC_MASK_SH_LIST_DCN2(_MASK, 3),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

160

DDC_MASK_SH_LIST_DCN2(_MASK, 4),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

161

DDC_MASK_SH_LIST_DCN2(_MASK, 5),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

162

DDC_MASK_SH_LIST_DCN2(_MASK, 6),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

163

DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

188

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

189

GENERIC_MASK_SH_LIST(_MASK, B),

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

95

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

149

DDC_MASK_SH_LIST_DCN2(_MASK, 1),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

150

DDC_MASK_SH_LIST_DCN2(_MASK, 2),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

151

DDC_MASK_SH_LIST_DCN2(_MASK, 3),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

152

DDC_MASK_SH_LIST_DCN2(_MASK, 4),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

153

DDC_MASK_SH_LIST_DCN2(_MASK, 5),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

154

DDC_MASK_SH_LIST_DCN2(_MASK, 6),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

155

DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

180

GENERIC_MASK_SH_LIST(_MASK, A),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

181

GENERIC_MASK_SH_LIST(_MASK, B),

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

75

HPD_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

36

.type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

59

.type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

76

.type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h

33

.type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h

41

.type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

79

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

81

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

82

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

86

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

88

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

176

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

178

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

179

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

183

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

185

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

179

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

181

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

182

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

186

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

188

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

128

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

130

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

131

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

135

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

137

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

189

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

191

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

192

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

196

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

198

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

203

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

205

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

206

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

210

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

212

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

196

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

198

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

199

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

203

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

205

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

210

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

212

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

213

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

217

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

219

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

180

.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

182

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

183

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

186

.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

187

.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

199

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

201

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

202

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

206

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

208

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

123

.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

125

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

126

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

129

.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

130

.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

184

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

186

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

187

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

191

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

193

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

198

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

200

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

201

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

205

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

207

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

186

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

188

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

189

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

193

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

195

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

200

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

202

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

203

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

207

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

209

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

191

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

193

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

194

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

198

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

200

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

205

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

207

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

208

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

212

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

214

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

195

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

197

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

198

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

202

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

204

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

209

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

211

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

212

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

216

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

218

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

183

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

185

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

187

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

190

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

192

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

197

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

199

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

201

~reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

204

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

206

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

162

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

164

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

166

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

169

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

171

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

176

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

178

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

180

~reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

183

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

185

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

161

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

163

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

165

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

168

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

170

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

175

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

177

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

179

~reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

182

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

184

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

175

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

177

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

178

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

182

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

184

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

189

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

191

reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

192

~reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

196

reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

198

reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

163

IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

185

XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

254

SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

266

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

288

OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

325

AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

344

CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

356

DMCU_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

368

ABM_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

517

HWSEQ_DCE10_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

560

MI_DCE8_MASK_SH_LIST(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

569

DCE10_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

733

I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

161

DMCU_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

173

ABM_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

192

IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

211

XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

275

SE_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

287

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

295

DCE_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

317

OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

355

AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

377

CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

560

HWSEQ_DCE11_MASK_SH_LIST(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

602

MI_DCE11_MASK_SH_LIST(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

757

I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

162

DMCU_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

174

ABM_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

182

DCE_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

204

IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

226

XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

252

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

304

SE_COMMON_MASK_SH_LIST_DCE112(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

326

OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

363

AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

385

CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

537

HWSEQ_DCE112_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

576

MI_DCE11_2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

733

I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

169

DMCU_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

181

ABM_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

203

IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

225

XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

293

SE_COMMON_MASK_SH_LIST_DCE120(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

305

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

313

DCE12_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

335

OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

377

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

423

CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

475

I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

797

HWSEQ_DCE12_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

810

HWSEQ_VG20_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

871

MI_DCE12_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

180

IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

202

XFM_COMMON_MASK_SH_LIST_DCE60(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

271

SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

283

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

305

OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

313

DCE10_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

350

AUD_DCE60_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

370

CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

437

DMCU_MASK_SH_LIST_DCE60(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

448

ABM_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

569

I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

635

HWSEQ_DCE6_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

678

MI_DCE6_MASK_SH_LIST(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

179

IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

201

XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

270

SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

282

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

304

OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

312

DCE10_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

350

AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

370

CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

443

DMCU_MASK_SH_LIST_DCE80(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

454

ABM_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

575

I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

641

HWSEQ_DCE8_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

684

MI_DCE8_MASK_SH_LIST(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

169

DMCU_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

181

ABM_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

201

SE_COMMON_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

226

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

271

LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

283

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

291

DCN10_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

311

IPP_MASK_SH_LIST_DCN10(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

331

OPP_MASK_SH_LIST_DCN10(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

368

TF_REG_LIST_SH_MASK_DCN10(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

389

MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

390

SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

408

TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

433

HUBP_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

445

HUBBUB_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

460

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

514

CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

682

I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

870

HWSEQ_DCN1_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1056

HWSEQ_DCN2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

208

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

220

DMCU_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

232

ABM_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

260

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

282

SE_COMMON_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

337

LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

338

DPCS_DCN2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

350

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

372

IPP_MASK_SH_LIST_DCN20(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

394

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

435

TF_REG_LIST_SH_MASK_DCN20(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

453

DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

470

MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

495

MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

517

TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

539

HUBP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

551

HUBBUB_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

566

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

610

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

618

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

668

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

680

DCCG_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

849

I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

321

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

344

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

362

SE_COMMON_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

370

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

412

LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

432

IPP_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

450

OPP_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

481

TF_REG_LIST_SH_MASK_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

499

MPC_COMMON_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

515

TG_COMMON_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

535

HUBP_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

547

HUBBUB_MASK_SH_LIST_DCN201(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

560

DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

710

I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

771

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

909

HWSEQ_DCN201_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1190

HWSEQ_DCN21_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1254

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1289

LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1290

DPCS_DCN21_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

166

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

183

DMCU_MASK_SH_LIST_DCN10(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

195

ABM_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

222

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

234

DCCG_MASK_SH_LIST_DCN2_1(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

256

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

274

TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

297

MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

318

HUBP_MASK_SH_LIST_DCN21(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

330

HUBBUB_MASK_SH_LIST_DCN21(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

382

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

404

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

424

IPP_MASK_SH_LIST_DCN20(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

468

TF_REG_LIST_SH_MASK_DCN20(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

490

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

498

SE_COMMON_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

573

I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

215

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

237

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

267

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

290

DCN3_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

313

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

335

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

380

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

398

LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

399

DPCS_DCN2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

412

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

434

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

456

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

490

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

507

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

529

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

557

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

578

OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

600

HUBP_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

612

HUBBUB_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

624

DCCG_MASK_SH_LIST_DCN3(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

636

HWSEQ_DCN30_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

667

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

823

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

902

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

216

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

236

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

264

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

284

DCN3_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

304

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

324

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

366

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

382

LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

383

DPCS_DCN2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

401

DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

421

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

441

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

473

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

490

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

509

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

532

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

551

OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

571

HUBP_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

583

HUBBUB_MASK_SH_LIST_DCN301(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

595

DCCG_MASK_SH_LIST_DCN301(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

607

HWSEQ_DCN301_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

638

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

781

I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

859

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1212

DCCG_MASK_SH_LIST_DCN3_02(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1231

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

224

HUBBUB_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

254

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

269

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

325

DCN3_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

357

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

395

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

419

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

470

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

500

HWSEQ_DCN302_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

532

HUBP_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

566

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

600

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

632

OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

677

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

708

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

736

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

771

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

815

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

846

I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

895

LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

896

DPCS_DCN2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

946

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1156

DCCG_MASK_SH_LIST_DCN3_03(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1172

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

220

HUBBUB_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

250

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

265

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

318

DCN3_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

347

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

385

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

406

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

454

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

484

HWSEQ_DCN303_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

513

HUBP_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

544

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

575

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

604

OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

641

MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

669

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

697

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

732

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

773

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

801

I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

846

LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

847

DPCS_DCN2_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

891

DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1002

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

233

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

253

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

281

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

307

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

329

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

349

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

371

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

413

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

430

LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

431

DPCS_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

451

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

474

DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

494

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

514

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

547

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

564

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

583

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

607

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

625

OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

646

HUBP_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

657

HUBBUB_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

669

DCCG_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

780

HWSEQ_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

811

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

826

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1038

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

242

CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

262

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

290

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

316

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

338

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

358

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

379

SE_COMMON_MASK_SH_LIST_DCN314(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

420

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

437

LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

438

DPCS_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

458

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

480

DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

500

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

520

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

553

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

570

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

590

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

614

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

632

OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

653

HUBP_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

664

HUBBUB_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

676

DCCG_MASK_SH_LIST_DCN314(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

792

HWSEQ_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

823

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

838

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1001

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

236

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

256

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

284

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

310

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

332

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

352

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

373

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

415

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

432

LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

433

DPCS_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

453

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

477

DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

497

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

517

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

550

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

567

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

586

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

606

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

624

OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

645

HUBP_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

656

HUBBUB_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

668

DCCG_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

779

HWSEQ_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

810

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

825

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

222

CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

242

ABM_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

270

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

296

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

318

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

339

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

361

SE_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

403

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

420

LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

421

DPCS_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

443

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

467

DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

488

DPP_REG_LIST_SH_MASK_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

508

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

541

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

558

MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

577

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

601

MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

619

OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

640

HUBP_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

651

HUBBUB_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

663

DCCG_MASK_SH_LIST_DCN31(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

774

HWSEQ_DCN31_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

805

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

820

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

994

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

220

CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

233

ABM_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

251

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

264

DCN3_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

277

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

290

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

303

SE_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

332

LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

346

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

364

DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

377

DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

391

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

410

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

423

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

436

MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

449

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

470

MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

483

OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

497

HUBP_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

509

HUBBUB_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

522

DCCG_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

632

HWSEQ_DCN32_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

644

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

657

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

799

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

219

CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

232

ABM_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

250

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

263

DCN3_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

276

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

289

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

302

SE_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

331

LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

345

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

363

DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

376

DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

390

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

408

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

421

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

434

MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

447

DSC_REG_LIST_SH_MASK_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

467

MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

480

OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

493

HUBP_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

505

HUBBUB_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

518

DCCG_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

628

HWSEQ_DCN32_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

640

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

653

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

793

I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

232

CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

245

ABM_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

264

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

277

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

290

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

303

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

316

SE_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

335

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

352

LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

366

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

383

DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

396

DPP_REG_LIST_SH_MASK_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

409

OPP_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

432

DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

445

MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

458

DSC_REG_LIST_SH_MASK_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

479

MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

492

OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

506

HUBP_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

519

HUBBUB_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

532

DCCG_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

545

PG_CNTL_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

652

HWSEQ_DCN35_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

665

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

678

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

918

I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

212

CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

225

ABM_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

244

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

257

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

270

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

283

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

296

SE_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

315

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

332

LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

346

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

363

DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

376

DPP_REG_LIST_SH_MASK_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

389

OPP_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

412

DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

425

MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

438

DSC_REG_LIST_SH_MASK_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

459

MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

472

OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

486

HUBP_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

499

HUBBUB_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

512

DCCG_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

525

PG_CNTL_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

632

HWSEQ_DCN35_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

645

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

658

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

898

I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

217

CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

230

ABM_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

249

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

262

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

275

DCN31_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

288

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

301

SE_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

320

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

337

LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

351

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

364

DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

377

DPP_REG_LIST_SH_MASK_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

390

OPP_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

413

DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

426

MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

439

DSC_REG_LIST_SH_MASK_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

460

MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

479

OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

493

HUBP_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

506

HUBBUB_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

519

DCCG_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

532

PG_CNTL_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

639

HWSEQ_DCN36_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

652

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

665

DIO_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

905

I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

204

CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

217

ABM_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

235

DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

248

DCN31_VPG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

261

DCN3_AFMT_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

274

DCN31_APG_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

287

SE_COMMON_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

312

LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

326

DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

344

DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

357

DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

370

OPP_MASK_SH_LIST_DCN20(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

386

DCN_AUX_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

399

DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

413

MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

426

DSC_REG_LIST_SH_MASK_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

447

MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

460

OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

473

HUBP_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

485

HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

498

DCCG_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

622

HWSEQ_DCN401_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

635

DCN20_VMID_MASK_SH_LIST(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

651

DIO_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

796

I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

41

#define FD_MASK(reg_name, field) reg_name##__##field##_MASK

drivers/gpu/drm/amd/include/cgs_common.h

121

#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

138

#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK

drivers/gpu/drm/gma500/psb_intel_reg.h

1238

#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)

drivers/gpu/drm/gma500/psb_intel_reg.h

1239

#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h

203

#define HIBMC_FIELD(field, value) (field(value) & field##_MASK)

drivers/gpu/drm/i915/display/i9xx_wm.c

159

(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)

drivers/gpu/drm/i915/display/i9xx_wm.c

3660

(((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)

drivers/gpu/drm/radeon/radeon.h

2511

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

drivers/gpu/drm/radeon/radeon.h

2512

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

drivers/gpu/drm/v3d/v3d_regs.h

14

WARN_ON((fieldval & ~field##_MASK) != 0); \

drivers/gpu/drm/v3d/v3d_regs.h

15

fieldval & field##_MASK; \

drivers/gpu/drm/v3d/v3d_regs.h

22

WARN_ON((fieldval & ~field##_MASK(_ver)) != 0); \

drivers/gpu/drm/v3d/v3d_regs.h

23

fieldval & field##_MASK(_ver); \

drivers/gpu/drm/v3d/v3d_regs.h

26

#define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \

drivers/gpu/drm/vc4/vc4_qpu_defines.h

211

((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))

drivers/gpu/drm/vc4/vc4_regs.h

16

WARN_ON(!FIELD_FIT(field##_MASK, value)); \

drivers/gpu/drm/vc4/vc4_regs.h

17

FIELD_PREP(field##_MASK, value); \

drivers/gpu/drm/vc4/vc4_regs.h

20

#define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word)

drivers/gpu/drm/vc4/vc4_regs.h

25

SCALER6_ ## field ## _MASK : \

drivers/gpu/drm/vc4/vc4_regs.h

26

SCALER6D_ ## field ## _MASK, value));\

drivers/gpu/drm/vc4/vc4_regs.h

28

SCALER6_ ## field ## _MASK : \

drivers/gpu/drm/vc4/vc4_regs.h

29

SCALER6D_ ## field ## _MASK, value); \

drivers/gpu/drm/vc4/vc4_regs.h

33

SCALER6_ ## field ## _MASK : \

drivers/gpu/drm/vc4/vc4_regs.h

34

SCALER6D_ ## field ## _MASK, word)

drivers/gpu/drm/xe/xe_gt.h

24

(((gt)->info.engine_mask & XE_HW_ENGINE_##NAME##_MASK) >> XE_HW_ENGINE_##NAME##0)

drivers/hwmon/adt7462.c

189

(((value) & prefix##_MASK) >> prefix##_SHIFT)

drivers/infiniband/hw/efa/efa_common_defs.h

14

#define EFA_GET(ptr, mask) FIELD_GET(mask##_MASK, *(ptr))

drivers/infiniband/hw/efa/efa_common_defs.h

19

*_ptr = (*_ptr & ~(mask##_MASK)) | \

drivers/infiniband/hw/efa/efa_common_defs.h

20

FIELD_PREP(mask##_MASK, value); \

drivers/infiniband/hw/efa/efa_verbs.c

180

EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_##cap##_MASK)

drivers/infiniband/hw/erdma/erdma.h

260

#define ERDMA_GET(val, name) FIELD_GET(ERDMA_CMD_##name##_MASK, val)

drivers/infiniband/hw/erdma/erdma_main.c

376

#define ERDMA_GET_CAP(name, cap) FIELD_GET(ERDMA_CMD_DEV_CAP_##name##_MASK, cap)

drivers/infiniband/hw/hfi1/chip.c

1089

{ reg##_STATUS, reg##_CLEAR, reg##_MASK, \

drivers/infiniband/hw/hfi1/exp_rcv.h

19

(((tid) >> EXP_TID_TID##field##_SHIFT) & EXP_TID_TID##field##_MASK)

drivers/infiniband/hw/hfi1/exp_rcv.h

22

(((value) & EXP_TID_TID##field##_MASK) << \

drivers/infiniband/hw/hfi1/exp_rcv.h

25

(tid) &= ~(EXP_TID_TID##field##_MASK << \

drivers/infiniband/hw/hfi1/exp_rcv.h

59

(((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK)

drivers/infiniband/hw/hfi1/exp_rcv.h

62

dwval &= ~(KDETH_##field##_MASK << KDETH_##field##_SHIFT); \

drivers/infiniband/hw/hfi1/exp_rcv.h

63

dwval |= (((val) & KDETH_##field##_MASK) << \

drivers/infiniband/hw/hfi1/file_ops.c

128

(((val) & HFI1_MMAP_##field##_MASK) << HFI1_MMAP_##field##_SHIFT)

drivers/infiniband/hw/hfi1/file_ops.c

130

(((token) >> HFI1_MMAP_##field##_SHIFT) & HFI1_MMAP_##field##_MASK)

drivers/iommu/msm_iommu_hw-8xxx.h

24

#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)

drivers/iommu/msm_iommu_hw-8xxx.h

26

GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)

drivers/iommu/msm_iommu_hw-8xxx.h

29

SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))

drivers/iommu/msm_iommu_hw-8xxx.h

31

SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))

drivers/mailbox/bcm74110-mailbox.c

84

hdr &= ~BCM_MSG_##field##_MASK; \

drivers/mailbox/bcm74110-mailbox.c

85

hdr |= FIELD_PREP(BCM_MSG_##field##_MASK, val); \

drivers/mailbox/bcm74110-mailbox.c

89

FIELD_GET(BCM_MSG_##field##_MASK, hdr)

drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h

17

(((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \

drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h

57

(((_m) & (ofst##_MASK)) == (ofst##_MASK)) ? \

drivers/media/radio/radio-gemtek.c

145

((dev)->bu2614data & ~field##_MASK) | ((data) << field##_SHIFT))

drivers/memory/tegra/tegra210-emc-core.c

61

_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte ## _MASK & \

drivers/memory/tegra/tegra210-emc-core.c

78

_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte1 ## _MASK) \

drivers/memory/tegra/tegra210-emc-core.c

83

_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte2 ## _MASK))

drivers/mfd/tps65219.c

274

REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK)

drivers/net/ethernet/atheros/alx/hw.h

457

(((_data) >> _field ## _SHIFT) & _field ## _MASK)

drivers/net/ethernet/atheros/alx/hw.h

460

(_data) &= ~(_field ## _MASK << _field ## _SHIFT); \

drivers/net/ethernet/atheros/alx/hw.h

461

(_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\

drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

15

#define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK))

drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

17

(((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\

drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

18

(((_v) & (_name##_MASK)) << (_name##_SHIFT)))

drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

19

#define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT))

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h

2505

(((value) & (fname##_MASK)) >> (fname##_SHIFT))

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

103

HINIC_API_CMD_STATUS_HEADER_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

117

HINIC_API_CMD_STATUS_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

20

(((u32)(val) & HINIC_API_CMD_PI_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

24

((val) & (~(HINIC_API_CMD_PI_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

32

(((u32)(val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

37

HINIC_API_CMD_CHAIN_REQ_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

40

((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

58

(((u32)(val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

62

((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

76

((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h

94

((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

40

& CMDQ_CEQE_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

48

& CMDQ_WQE_ERRCODE_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

31

(((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

36

& HINIC_CMDQ_CTXT_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

39

((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

49

(((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

54

& HINIC_CMDQ_CTXT_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

57

((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

65

(((u32)(val) & HINIC_SAVED_DATA_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

70

& HINIC_SAVED_DATA_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

73

((val) & (~(HINIC_SAVED_DATA_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h

87

(((u32)(val) & HINIC_CMDQ_DB_INFO_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

103

HINIC_EQ_ELEM_DESC_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

116

(((u32)(val) & HINIC_EQ_CI_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

120

((val) & (~(HINIC_EQ_CI_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

30

(((u32)(val) & HINIC_AEQ_CTRL_0_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

34

((val) & (~(HINIC_AEQ_CTRL_0_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

46

(((u32)(val) & HINIC_AEQ_CTRL_1_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

50

((val) & (~(HINIC_AEQ_CTRL_1_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

66

(((u32)(val) & HINIC_CEQ_CTRL_0_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

70

((val) & (~(HINIC_CEQ_CTRL_0_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

80

(((u32)(val) & HINIC_CEQ_CTRL_1_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

84

((val) & (~(HINIC_CEQ_CTRL_1_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

98

(((u32)(val) & HINIC_EQ_ELEM_DESC_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

101

((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

107

(((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

112

HINIC_PPF_ELECTION_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

115

((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

131

(((u32)(val) & HINIC_MSIX_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

139

(((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

30

(((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

34

((val) & (~(HINIC_DMA_ATTR_##member##_MASK \

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

51

(((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

71

(((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

77

(((val) >> HINIC_FA2_##member##_SHIFT) & HINIC_FA2_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

86

(((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

89

((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

92

((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))

drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

98

(((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)

drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c

38

(((val) & HINIC_MBOX_INT_##field##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c

57

(((val) & HINIC_MBOX_CTRL_##field##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c

91

HINIC_MBOX_HEADER_##field##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c

93

((u64)((val) & HINIC_MBOX_HEADER_##field##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h

47

((u64)((val) & HINIC_MSG_HEADER_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h

52

HINIC_MSG_HEADER_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h

35

(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

115

(((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

123

(((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

21

(((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

31

(((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

41

(((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

59

(((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

67

(((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

77

(((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

87

(((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h

97

(((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

115

(((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

129

(((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

147

(((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

157

(((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

170

HINIC_RQ_CQE_STATUS_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

173

((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

182

HINIC_RQ_CQE_SGE_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

195

(((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

218

RQ_CQE_STATUS_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

230

RQ_CQE_OFFOLAD_TYPE_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

243

RQ_CQE_SGE_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

25

(((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

30

& HINIC_CMDQ_CTRL_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

49

(((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

54

& HINIC_CMDQ_WQE_HEADER_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

85

(((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

90

& HINIC_SQ_CTRL_##member##_MASK)

drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h

93

((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

28

FIELD_PREP(CMDQ_CTXT_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

38

FIELD_PREP(CMDQ_WQE_HDR_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

40

FIELD_GET(CMDQ_WQE_HDR_##member##_MASK, le32_to_cpu(val))

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

47

FIELD_PREP(CMDQ_CTRL_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

49

FIELD_GET(CMDQ_CTRL_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

53

FIELD_GET(CMDQ_WQE_ERRCODE_##member##_MASK, le32_to_cpu(val))

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

57

FIELD_PREP(CMDQ_DB_INFO_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

62

FIELD_PREP(CMDQ_DB_HEAD_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

66

FIELD_GET(CMDQ_CEQE_##member##_MASK, le32_to_cpu(val))

drivers/net/ethernet/huawei/hinic3/hinic3_csr.h

46

FIELD_PREP(HINIC3_MSI_CLR_INDIR_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

17

FIELD_PREP(AEQ_CTRL_0_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

23

FIELD_PREP(AEQ_CTRL_1_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

32

FIELD_PREP(CEQ_CTRL_0_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

36

FIELD_PREP(CEQ_CTRL_1_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

50

FIELD_GET(EQ_ELEM_DESC_##member##_MASK, le32_to_cpu(val))

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

57

FIELD_PREP(EQ_CI_SIMPLE_INDIR_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c

20

FIELD_PREP(HINIC3_DMA_ATTR_INDIR_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c

28

FIELD_PREP(HINIC3_DMA_ATTR_ENTRY_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

32

FIELD_GET(HINIC3_AF0_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

38

FIELD_GET(HINIC3_AF1_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

43

FIELD_GET(HINIC3_AF2_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

47

FIELD_GET(HINIC3_AF3_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

51

FIELD_GET(HINIC3_AF4_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

53

FIELD_PREP(HINIC3_AF4_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

57

FIELD_GET(HINIC3_AF5_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

63

FIELD_PREP(HINIC3_AF6_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

65

FIELD_GET(HINIC3_AF6_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

69

FIELD_PREP(HINIC3_PPF_ELECTION_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

71

FIELD_GET(HINIC3_PPF_ELECTION_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

21

FIELD_PREP(MBOX_INT_##field##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

27

FIELD_PREP(MBOX_CTRL_##field##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

29

FIELD_PREP(MBOX_MSG_HEADER_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

31

FIELD_GET(MBOX_MSG_HEADER_##member##_MASK, le64_to_cpu(val))

drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h

176

FIELD_PREP(L2NIC_RSS_TYPE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h

178

FIELD_GET(L2NIC_RSS_TYPE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

123

FIELD_PREP(SQ_CTXT_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

128

FIELD_PREP(SQ_CTXT_MODE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

133

FIELD_PREP(SQ_CTXT_WQ_PAGE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

138

FIELD_PREP(SQ_CTXT_PKT_DROP_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

142

FIELD_PREP(SQ_CTXT_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

147

FIELD_PREP(SQ_CTXT_VLAN_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

159

FIELD_PREP(SQ_CTXT_PREF_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

163

FIELD_PREP(SQ_CTXT_WQ_BLOCK_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

171

FIELD_PREP(RQ_CTXT_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

176

FIELD_PREP(RQ_CTXT_CEQ_ATTR_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

182

FIELD_PREP(RQ_CTXT_WQ_PAGE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

186

FIELD_PREP(RQ_CTXT_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

198

FIELD_PREP(RQ_CTXT_PREF_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

202

FIELD_PREP(RQ_CTXT_WQ_BLOCK_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

63

FIELD_PREP(DB_INFO_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

16

FIELD_GET(RQ_CQE_OFFOLAD_TYPE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

21

FIELD_GET(RQ_CQE_SGE_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

27

FIELD_GET(RQ_CQE_STATUS_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

50

FIELD_PREP(SQ_CTRL_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

59

FIELD_PREP(SQ_CTRL_QUEUE_INFO_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

61

FIELD_GET(SQ_CTRL_QUEUE_INFO_##member##_MASK, le32_to_cpu(val))

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

71

FIELD_PREP(SQ_TASK_INFO0_##member##_MASK, val)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

77

FIELD_PREP(SQ_TASK_INFO3_##member##_MASK, val)

drivers/net/ethernet/qlogic/qed/qed.h

69

(((name) & (field ## _MASK)) >> (field ## _SHIFT))

drivers/net/ethernet/qlogic/qed/qed.h

73

(name) &= ~(field ## _MASK); \

drivers/net/ethernet/qlogic/qed/qed.h

74

(name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\

drivers/net/ethernet/sun/cassini.h

2558

#define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))

drivers/net/ethernet/sun/cassini.h

2559

#define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))

drivers/net/wireless/ath/ath10k/core.h

33

#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)

drivers/net/wireless/ath/ath10k/core.h

34

#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)

drivers/net/wireless/ath/ath11k/core.h

40

#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)

drivers/net/wireless/ath/ath12k/core.h

40

#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

238

BRCMF_SKB_IF_FLAGS_ ## field ## _MASK, \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

242

BRCMF_SKB_IF_FLAGS_ ## field ## _MASK, \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

273

BRCMF_SKB_HTOD_TAG_ ## field ## _MASK, \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

277

BRCMF_SKB_HTOD_TAG_ ## field ## _MASK, \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

289

BRCMF_SKB_HTOD_SEQ_ ## field ## _MASK, \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

293

BRCMF_SKB_HTOD_SEQ_ ## field ## _MASK, \

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c

308

brcmu_maskget32(txs, BRCMF_FWS_TXSTAT_ ## field ## _MASK, \

drivers/ntb/hw/idt/ntb_hw_idt.h

950

(((u32)(data) & IDT_ ##field## _MASK) >> IDT_ ##field## _FLD)

drivers/ntb/hw/idt/ntb_hw_idt.h

952

(((u32)(data) & ~IDT_ ##field## _MASK) | \

drivers/ntb/hw/idt/ntb_hw_idt.h

955

(((u32)(data) & IDT_ ##field## _MASK) == IDT_ ##field## _ ##value)

drivers/nvmem/vf610-ocotp.c

52

#define BF(value, field) (((value) << field) & field##_MASK)

drivers/pci/controller/plda/pcie-microchip-host.c

160

.mask = x ## _MASK, \

drivers/pci/controller/plda/pcie-microchip-host.c

173

{ x ## _MASK, EVENT_LOCAL_ ## x }

drivers/phy/broadcom/phy-brcm-usb-init.h

29

USB_CTRL_##reg##_##field##_MASK

drivers/phy/broadcom/phy-brcm-usb-init.h

32

USB_CTRL_##reg##_##field##_MASK)

drivers/phy/broadcom/phy-brcm-usb-init.h

35

USB_CTRL_##reg##_##field##_MASK)

drivers/phy/broadcom/phy-brcm-usb-init.h

40

USB_XHCI_GBL_##reg##_##field##_MASK)

drivers/phy/broadcom/phy-brcm-usb-init.h

43

USB_XHCI_GBL_##reg##_##field##_MASK)

drivers/pinctrl/bcm/pinctrl-bcm281xx.c

1561

(BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)

drivers/pinctrl/pinctrl-st.c

131

& ST_PINCONF_ ##param ##_MASK)

drivers/pinctrl/pinctrl-st.c

134

((val & ST_PINCONF_ ##param ##_MASK) << \

drivers/power/supply/bq24190_charger.c

382

.mask = BQ24190_REG_##r##_##f##_MASK, \

drivers/regulator/da9063-regulator.c

103

.desc.vsel_mask = DA9063_V##regl_name##_MASK, \

drivers/regulator/max77693-regulator.c

158

.vsel_mask = SAFEOUT_CTRL_SAFEOUT##_num##_MASK, \

drivers/regulator/max77693-regulator.c

160

.enable_mask = SAFEOUT_CTRL_ENSAFEOUT##_num##_MASK , \

drivers/regulator/max77693-regulator.c

201

.vsel_mask = MAX77843_REG_SAFEOUTCTRL_SAFEOUT ## num ## _MASK, \

drivers/regulator/pv88090-regulator.c

177

.vsel_mask = PV88090_V##regl_name##_MASK, \

drivers/regulator/pv88090-regulator.c

203

.vsel_mask = PV88090_V##regl_name##_MASK, \

drivers/regulator/rtq2208-regulator.c

372

#define MTP_SEL_MASK(_sel) RTQ2208_BUCK_EN_NR_MTP_SEL##_sel##_MASK

drivers/regulator/s2dos05-regulator.c

100

_REG(_EN), _MASK(_L2), _TIME(_LDO), _REG(_LDO2_CFG)),

drivers/regulator/s2dos05-regulator.c

103

_REG(_EN), _MASK(_L3), _TIME(_LDO), _REG(_LDO3_CFG)),

drivers/regulator/s2dos05-regulator.c

106

_REG(_EN), _MASK(_L4), _TIME(_LDO), _REG(_LDO4_CFG)),

drivers/regulator/s2dos05-regulator.c

109

_REG(_EN), _MASK(_B1), _TIME(_BUCK), _REG(_BUCK_CFG)),

drivers/regulator/s2dos05-regulator.c

97

_REG(_EN), _MASK(_L1), _TIME(_LDO), _REG(_LDO1_CFG)),

drivers/scsi/isci/registers.h

179

(((value) << name ## _SHIFT) & (name ## _MASK))

drivers/scsi/lpfc/lpfc_bsg.h

164

((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)

drivers/scsi/lpfc/lpfc_bsg.h

166

(((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)

drivers/scsi/lpfc/lpfc_bsg.h

169

name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \

drivers/scsi/lpfc/lpfc_bsg.h

170

~(name##_MASK << name##_SHIFT)))))

drivers/scsi/lpfc/lpfc_bsg.h

172

((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \

drivers/scsi/lpfc/lpfc_bsg.h

173

((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))

drivers/scsi/lpfc/lpfc_hw4.h

50

((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)

drivers/scsi/lpfc/lpfc_hw4.h

52

((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)

drivers/scsi/lpfc/lpfc_hw4.h

54

(((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)

drivers/scsi/lpfc/lpfc_hw4.h

57

name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \

drivers/scsi/lpfc/lpfc_hw4.h

58

~(name##_MASK << name##_SHIFT)))))

drivers/scsi/lpfc/lpfc_hw4.h

60

((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \

drivers/scsi/lpfc/lpfc_hw4.h

61

((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))

drivers/scsi/qedi/qedi.h

31

(((value) & (name ## _MASK)) >> (name ## _OFFSET))

drivers/staging/most/net/net.c

43

(((value) >> bitset_name##_SHIFT) & bitset_name##_MASK)

drivers/usb/gadget/udc/amd5536udc.h

628

(((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK)))) \

drivers/usb/gadget/udc/amd5536udc.h

630

& ((u32) bitfield_stub_name##_MASK)))

drivers/usb/gadget/udc/amd5536udc.h

639

& ((u32) bitfield_stub_name##_MASK)))

drivers/usb/gadget/udc/amd5536udc.h

643

((u32Val & ((u32) bitfield_stub_name##_MASK)) \

include/linux/qed/qed_if.h

1214

((_value) &= (_name ## _MASK))

include/linux/qed/qed_if.h

1217

((_value & _name ## _MASK) << _name ## _SHIFT)

include/linux/qed/qed_if.h

1221

(value) &= ~(name ## _MASK << name ## _SHIFT); \

include/linux/qed/qed_if.h

1226

(((value) >> (name ## _SHIFT)) & name ## _MASK)

include/linux/qed/qed_if.h

1229

(((name) & (field ## _MASK)) >> (field ## _OFFSET))

include/linux/qed/qed_if.h

1233

(name) &= ~(field ## _MASK); \

include/linux/qed/qed_if.h

1234

(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\

include/sound/cs35l41.h

875

.mask = CS35L41_ ## _irq ## _MASK \

include/uapi/drm/amdgpu_drm.h

693

(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)

include/uapi/drm/amdgpu_drm.h

695

(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)

include/uapi/drm/drm_fourcc.h

1754

(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)

include/uapi/drm/drm_fourcc.h

1756

(~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))

net/mac80211/debugfs_sta.c

707

u8 msk = IEEE80211_HE_##t##_CAP##i##_##n##_MASK; \

sound/soc/codecs/ak4613.c

176

#define AK4613_CONFIG_GET(priv, x) (priv->configs & AK4613_CONFIG_##x##_MASK)

sound/soc/codecs/cs35l45.h

458

.mask = CS35L45_ ## _irq ## _MASK \

sound/soc/generic/audio-graph-card2.c

707

if (!(*daifmt & SND_SOC_DAIFMT_##name##_MASK) && \

sound/soc/generic/audio-graph-card2.c

708

(fmt & SND_SOC_DAIFMT_##name##_MASK)) \

sound/soc/generic/audio-graph-card2.c

709

*daifmt |= fmt & SND_SOC_DAIFMT_##name##_MASK

tools/arch/arm64/include/asm/sysreg.h

1190

FIELD_GET(reg##_##field##_MASK, val)

tools/arch/arm64/include/asm/sysreg.h

1193

FIELD_PREP(reg##_##field##_MASK, val)

tools/arch/arm64/include/asm/sysreg.h

1196

FIELD_PREP(reg##_##field##_MASK, \

tools/arch/arm64/include/uapi/asm/kvm.h

245

KVM_REG_ARM64_SYSREG_ ## n ## _MASK)

tools/testing/selftests/kvm/arm64/set_id_regs.c

59

reg##_##field##_MASK, safe_val)

tools/testing/selftests/kvm/arm64/set_id_regs.c

63

reg##_##field##_MASK, safe_val)